1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2014 Renesas Electronics Corporation 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2014 Renesas Solutions Corp. 6 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 7 * Copyright (C) 2014 Codethink Limited 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 */ 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/etherdevice.h> 28 #include <linux/delay.h> 29 #include <linux/platform_device.h> 30 #include <linux/mdio-bitbang.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_net.h> 36 #include <linux/phy.h> 37 #include <linux/cache.h> 38 #include <linux/io.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/slab.h> 41 #include <linux/ethtool.h> 42 #include <linux/if_vlan.h> 43 #include <linux/sh_eth.h> 44 #include <linux/of_mdio.h> 45 46 #include "sh_eth.h" 47 48 #define SH_ETH_DEF_MSG_ENABLE \ 49 (NETIF_MSG_LINK | \ 50 NETIF_MSG_TIMER | \ 51 NETIF_MSG_RX_ERR| \ 52 NETIF_MSG_TX_ERR) 53 54 #define SH_ETH_OFFSET_INVALID ((u16)~0) 55 56 #define SH_ETH_OFFSET_DEFAULTS \ 57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 58 59 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 60 SH_ETH_OFFSET_DEFAULTS, 61 62 [EDSR] = 0x0000, 63 [EDMR] = 0x0400, 64 [EDTRR] = 0x0408, 65 [EDRRR] = 0x0410, 66 [EESR] = 0x0428, 67 [EESIPR] = 0x0430, 68 [TDLAR] = 0x0010, 69 [TDFAR] = 0x0014, 70 [TDFXR] = 0x0018, 71 [TDFFR] = 0x001c, 72 [RDLAR] = 0x0030, 73 [RDFAR] = 0x0034, 74 [RDFXR] = 0x0038, 75 [RDFFR] = 0x003c, 76 [TRSCER] = 0x0438, 77 [RMFCR] = 0x0440, 78 [TFTR] = 0x0448, 79 [FDR] = 0x0450, 80 [RMCR] = 0x0458, 81 [RPADIR] = 0x0460, 82 [FCFTR] = 0x0468, 83 [CSMR] = 0x04E4, 84 85 [ECMR] = 0x0500, 86 [ECSR] = 0x0510, 87 [ECSIPR] = 0x0518, 88 [PIR] = 0x0520, 89 [PSR] = 0x0528, 90 [PIPR] = 0x052c, 91 [RFLR] = 0x0508, 92 [APR] = 0x0554, 93 [MPR] = 0x0558, 94 [PFTCR] = 0x055c, 95 [PFRCR] = 0x0560, 96 [TPAUSER] = 0x0564, 97 [GECMR] = 0x05b0, 98 [BCULR] = 0x05b4, 99 [MAHR] = 0x05c0, 100 [MALR] = 0x05c8, 101 [TROCR] = 0x0700, 102 [CDCR] = 0x0708, 103 [LCCR] = 0x0710, 104 [CEFCR] = 0x0740, 105 [FRECR] = 0x0748, 106 [TSFRCR] = 0x0750, 107 [TLFRCR] = 0x0758, 108 [RFCR] = 0x0760, 109 [CERCR] = 0x0768, 110 [CEECR] = 0x0770, 111 [MAFCR] = 0x0778, 112 [RMII_MII] = 0x0790, 113 114 [ARSTR] = 0x0000, 115 [TSU_CTRST] = 0x0004, 116 [TSU_FWEN0] = 0x0010, 117 [TSU_FWEN1] = 0x0014, 118 [TSU_FCM] = 0x0018, 119 [TSU_BSYSL0] = 0x0020, 120 [TSU_BSYSL1] = 0x0024, 121 [TSU_PRISL0] = 0x0028, 122 [TSU_PRISL1] = 0x002c, 123 [TSU_FWSL0] = 0x0030, 124 [TSU_FWSL1] = 0x0034, 125 [TSU_FWSLC] = 0x0038, 126 [TSU_QTAG0] = 0x0040, 127 [TSU_QTAG1] = 0x0044, 128 [TSU_FWSR] = 0x0050, 129 [TSU_FWINMK] = 0x0054, 130 [TSU_ADQT0] = 0x0048, 131 [TSU_ADQT1] = 0x004c, 132 [TSU_VTAG0] = 0x0058, 133 [TSU_VTAG1] = 0x005c, 134 [TSU_ADSBSY] = 0x0060, 135 [TSU_TEN] = 0x0064, 136 [TSU_POST1] = 0x0070, 137 [TSU_POST2] = 0x0074, 138 [TSU_POST3] = 0x0078, 139 [TSU_POST4] = 0x007c, 140 [TSU_ADRH0] = 0x0100, 141 142 [TXNLCR0] = 0x0080, 143 [TXALCR0] = 0x0084, 144 [RXNLCR0] = 0x0088, 145 [RXALCR0] = 0x008c, 146 [FWNLCR0] = 0x0090, 147 [FWALCR0] = 0x0094, 148 [TXNLCR1] = 0x00a0, 149 [TXALCR1] = 0x00a4, 150 [RXNLCR1] = 0x00a8, 151 [RXALCR1] = 0x00ac, 152 [FWNLCR1] = 0x00b0, 153 [FWALCR1] = 0x00b4, 154 }; 155 156 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 157 SH_ETH_OFFSET_DEFAULTS, 158 159 [EDSR] = 0x0000, 160 [EDMR] = 0x0400, 161 [EDTRR] = 0x0408, 162 [EDRRR] = 0x0410, 163 [EESR] = 0x0428, 164 [EESIPR] = 0x0430, 165 [TDLAR] = 0x0010, 166 [TDFAR] = 0x0014, 167 [TDFXR] = 0x0018, 168 [TDFFR] = 0x001c, 169 [RDLAR] = 0x0030, 170 [RDFAR] = 0x0034, 171 [RDFXR] = 0x0038, 172 [RDFFR] = 0x003c, 173 [TRSCER] = 0x0438, 174 [RMFCR] = 0x0440, 175 [TFTR] = 0x0448, 176 [FDR] = 0x0450, 177 [RMCR] = 0x0458, 178 [RPADIR] = 0x0460, 179 [FCFTR] = 0x0468, 180 [CSMR] = 0x04E4, 181 182 [ECMR] = 0x0500, 183 [RFLR] = 0x0508, 184 [ECSR] = 0x0510, 185 [ECSIPR] = 0x0518, 186 [PIR] = 0x0520, 187 [APR] = 0x0554, 188 [MPR] = 0x0558, 189 [PFTCR] = 0x055c, 190 [PFRCR] = 0x0560, 191 [TPAUSER] = 0x0564, 192 [MAHR] = 0x05c0, 193 [MALR] = 0x05c8, 194 [CEFCR] = 0x0740, 195 [FRECR] = 0x0748, 196 [TSFRCR] = 0x0750, 197 [TLFRCR] = 0x0758, 198 [RFCR] = 0x0760, 199 [MAFCR] = 0x0778, 200 201 [ARSTR] = 0x0000, 202 [TSU_CTRST] = 0x0004, 203 [TSU_FWSLC] = 0x0038, 204 [TSU_VTAG0] = 0x0058, 205 [TSU_ADSBSY] = 0x0060, 206 [TSU_TEN] = 0x0064, 207 [TSU_POST1] = 0x0070, 208 [TSU_POST2] = 0x0074, 209 [TSU_POST3] = 0x0078, 210 [TSU_POST4] = 0x007c, 211 [TSU_ADRH0] = 0x0100, 212 213 [TXNLCR0] = 0x0080, 214 [TXALCR0] = 0x0084, 215 [RXNLCR0] = 0x0088, 216 [RXALCR0] = 0x008C, 217 }; 218 219 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 220 SH_ETH_OFFSET_DEFAULTS, 221 222 [ECMR] = 0x0300, 223 [RFLR] = 0x0308, 224 [ECSR] = 0x0310, 225 [ECSIPR] = 0x0318, 226 [PIR] = 0x0320, 227 [PSR] = 0x0328, 228 [RDMLR] = 0x0340, 229 [IPGR] = 0x0350, 230 [APR] = 0x0354, 231 [MPR] = 0x0358, 232 [RFCF] = 0x0360, 233 [TPAUSER] = 0x0364, 234 [TPAUSECR] = 0x0368, 235 [MAHR] = 0x03c0, 236 [MALR] = 0x03c8, 237 [TROCR] = 0x03d0, 238 [CDCR] = 0x03d4, 239 [LCCR] = 0x03d8, 240 [CNDCR] = 0x03dc, 241 [CEFCR] = 0x03e4, 242 [FRECR] = 0x03e8, 243 [TSFRCR] = 0x03ec, 244 [TLFRCR] = 0x03f0, 245 [RFCR] = 0x03f4, 246 [MAFCR] = 0x03f8, 247 248 [EDMR] = 0x0200, 249 [EDTRR] = 0x0208, 250 [EDRRR] = 0x0210, 251 [TDLAR] = 0x0218, 252 [RDLAR] = 0x0220, 253 [EESR] = 0x0228, 254 [EESIPR] = 0x0230, 255 [TRSCER] = 0x0238, 256 [RMFCR] = 0x0240, 257 [TFTR] = 0x0248, 258 [FDR] = 0x0250, 259 [RMCR] = 0x0258, 260 [TFUCR] = 0x0264, 261 [RFOCR] = 0x0268, 262 [RMIIMODE] = 0x026c, 263 [FCFTR] = 0x0270, 264 [TRIMD] = 0x027c, 265 }; 266 267 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 268 SH_ETH_OFFSET_DEFAULTS, 269 270 [ECMR] = 0x0100, 271 [RFLR] = 0x0108, 272 [ECSR] = 0x0110, 273 [ECSIPR] = 0x0118, 274 [PIR] = 0x0120, 275 [PSR] = 0x0128, 276 [RDMLR] = 0x0140, 277 [IPGR] = 0x0150, 278 [APR] = 0x0154, 279 [MPR] = 0x0158, 280 [TPAUSER] = 0x0164, 281 [RFCF] = 0x0160, 282 [TPAUSECR] = 0x0168, 283 [BCFRR] = 0x016c, 284 [MAHR] = 0x01c0, 285 [MALR] = 0x01c8, 286 [TROCR] = 0x01d0, 287 [CDCR] = 0x01d4, 288 [LCCR] = 0x01d8, 289 [CNDCR] = 0x01dc, 290 [CEFCR] = 0x01e4, 291 [FRECR] = 0x01e8, 292 [TSFRCR] = 0x01ec, 293 [TLFRCR] = 0x01f0, 294 [RFCR] = 0x01f4, 295 [MAFCR] = 0x01f8, 296 [RTRATE] = 0x01fc, 297 298 [EDMR] = 0x0000, 299 [EDTRR] = 0x0008, 300 [EDRRR] = 0x0010, 301 [TDLAR] = 0x0018, 302 [RDLAR] = 0x0020, 303 [EESR] = 0x0028, 304 [EESIPR] = 0x0030, 305 [TRSCER] = 0x0038, 306 [RMFCR] = 0x0040, 307 [TFTR] = 0x0048, 308 [FDR] = 0x0050, 309 [RMCR] = 0x0058, 310 [TFUCR] = 0x0064, 311 [RFOCR] = 0x0068, 312 [FCFTR] = 0x0070, 313 [RPADIR] = 0x0078, 314 [TRIMD] = 0x007c, 315 [RBWAR] = 0x00c8, 316 [RDFAR] = 0x00cc, 317 [TBRAR] = 0x00d4, 318 [TDFAR] = 0x00d8, 319 }; 320 321 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 322 SH_ETH_OFFSET_DEFAULTS, 323 324 [EDMR] = 0x0000, 325 [EDTRR] = 0x0004, 326 [EDRRR] = 0x0008, 327 [TDLAR] = 0x000c, 328 [RDLAR] = 0x0010, 329 [EESR] = 0x0014, 330 [EESIPR] = 0x0018, 331 [TRSCER] = 0x001c, 332 [RMFCR] = 0x0020, 333 [TFTR] = 0x0024, 334 [FDR] = 0x0028, 335 [RMCR] = 0x002c, 336 [EDOCR] = 0x0030, 337 [FCFTR] = 0x0034, 338 [RPADIR] = 0x0038, 339 [TRIMD] = 0x003c, 340 [RBWAR] = 0x0040, 341 [RDFAR] = 0x0044, 342 [TBRAR] = 0x004c, 343 [TDFAR] = 0x0050, 344 345 [ECMR] = 0x0160, 346 [ECSR] = 0x0164, 347 [ECSIPR] = 0x0168, 348 [PIR] = 0x016c, 349 [MAHR] = 0x0170, 350 [MALR] = 0x0174, 351 [RFLR] = 0x0178, 352 [PSR] = 0x017c, 353 [TROCR] = 0x0180, 354 [CDCR] = 0x0184, 355 [LCCR] = 0x0188, 356 [CNDCR] = 0x018c, 357 [CEFCR] = 0x0194, 358 [FRECR] = 0x0198, 359 [TSFRCR] = 0x019c, 360 [TLFRCR] = 0x01a0, 361 [RFCR] = 0x01a4, 362 [MAFCR] = 0x01a8, 363 [IPGR] = 0x01b4, 364 [APR] = 0x01b8, 365 [MPR] = 0x01bc, 366 [TPAUSER] = 0x01c4, 367 [BCFR] = 0x01cc, 368 369 [ARSTR] = 0x0000, 370 [TSU_CTRST] = 0x0004, 371 [TSU_FWEN0] = 0x0010, 372 [TSU_FWEN1] = 0x0014, 373 [TSU_FCM] = 0x0018, 374 [TSU_BSYSL0] = 0x0020, 375 [TSU_BSYSL1] = 0x0024, 376 [TSU_PRISL0] = 0x0028, 377 [TSU_PRISL1] = 0x002c, 378 [TSU_FWSL0] = 0x0030, 379 [TSU_FWSL1] = 0x0034, 380 [TSU_FWSLC] = 0x0038, 381 [TSU_QTAGM0] = 0x0040, 382 [TSU_QTAGM1] = 0x0044, 383 [TSU_ADQT0] = 0x0048, 384 [TSU_ADQT1] = 0x004c, 385 [TSU_FWSR] = 0x0050, 386 [TSU_FWINMK] = 0x0054, 387 [TSU_ADSBSY] = 0x0060, 388 [TSU_TEN] = 0x0064, 389 [TSU_POST1] = 0x0070, 390 [TSU_POST2] = 0x0074, 391 [TSU_POST3] = 0x0078, 392 [TSU_POST4] = 0x007c, 393 394 [TXNLCR0] = 0x0080, 395 [TXALCR0] = 0x0084, 396 [RXNLCR0] = 0x0088, 397 [RXALCR0] = 0x008c, 398 [FWNLCR0] = 0x0090, 399 [FWALCR0] = 0x0094, 400 [TXNLCR1] = 0x00a0, 401 [TXALCR1] = 0x00a4, 402 [RXNLCR1] = 0x00a8, 403 [RXALCR1] = 0x00ac, 404 [FWNLCR1] = 0x00b0, 405 [FWALCR1] = 0x00b4, 406 407 [TSU_ADRH0] = 0x0100, 408 }; 409 410 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 412 413 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 414 { 415 struct sh_eth_private *mdp = netdev_priv(ndev); 416 u16 offset = mdp->reg_offset[enum_index]; 417 418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 419 return; 420 421 iowrite32(data, mdp->addr + offset); 422 } 423 424 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 425 { 426 struct sh_eth_private *mdp = netdev_priv(ndev); 427 u16 offset = mdp->reg_offset[enum_index]; 428 429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 430 return ~0U; 431 432 return ioread32(mdp->addr + offset); 433 } 434 435 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 436 u32 set) 437 { 438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 439 enum_index); 440 } 441 442 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data, 443 int enum_index) 444 { 445 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]); 446 } 447 448 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index) 449 { 450 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]); 451 } 452 453 static bool sh_eth_is_gether(struct sh_eth_private *mdp) 454 { 455 return mdp->reg_offset == sh_eth_offset_gigabit; 456 } 457 458 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp) 459 { 460 return mdp->reg_offset == sh_eth_offset_fast_rz; 461 } 462 463 static void sh_eth_select_mii(struct net_device *ndev) 464 { 465 struct sh_eth_private *mdp = netdev_priv(ndev); 466 u32 value; 467 468 switch (mdp->phy_interface) { 469 case PHY_INTERFACE_MODE_GMII: 470 value = 0x2; 471 break; 472 case PHY_INTERFACE_MODE_MII: 473 value = 0x1; 474 break; 475 case PHY_INTERFACE_MODE_RMII: 476 value = 0x0; 477 break; 478 default: 479 netdev_warn(ndev, 480 "PHY interface mode was not setup. Set to MII.\n"); 481 value = 0x1; 482 break; 483 } 484 485 sh_eth_write(ndev, value, RMII_MII); 486 } 487 488 static void sh_eth_set_duplex(struct net_device *ndev) 489 { 490 struct sh_eth_private *mdp = netdev_priv(ndev); 491 492 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 493 } 494 495 static void sh_eth_chip_reset(struct net_device *ndev) 496 { 497 struct sh_eth_private *mdp = netdev_priv(ndev); 498 499 /* reset device */ 500 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 501 mdelay(1); 502 } 503 504 static void sh_eth_set_rate_gether(struct net_device *ndev) 505 { 506 struct sh_eth_private *mdp = netdev_priv(ndev); 507 508 switch (mdp->speed) { 509 case 10: /* 10BASE */ 510 sh_eth_write(ndev, GECMR_10, GECMR); 511 break; 512 case 100:/* 100BASE */ 513 sh_eth_write(ndev, GECMR_100, GECMR); 514 break; 515 case 1000: /* 1000BASE */ 516 sh_eth_write(ndev, GECMR_1000, GECMR); 517 break; 518 } 519 } 520 521 #ifdef CONFIG_OF 522 /* R7S72100 */ 523 static struct sh_eth_cpu_data r7s72100_data = { 524 .chip_reset = sh_eth_chip_reset, 525 .set_duplex = sh_eth_set_duplex, 526 527 .register_type = SH_ETH_REG_FAST_RZ, 528 529 .ecsr_value = ECSR_ICD, 530 .ecsipr_value = ECSIPR_ICDIP, 531 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 532 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 533 EESIPR_ECIIP | 534 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 535 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 536 EESIPR_RMAFIP | EESIPR_RRFIP | 537 EESIPR_RTLFIP | EESIPR_RTSFIP | 538 EESIPR_PREIP | EESIPR_CERFIP, 539 540 .tx_check = EESR_TC1 | EESR_FTC, 541 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 542 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 543 EESR_TDE, 544 .fdr_value = 0x0000070f, 545 546 .no_psr = 1, 547 .apr = 1, 548 .mpr = 1, 549 .tpauser = 1, 550 .hw_swap = 1, 551 .rpadir = 1, 552 .rpadir_value = 2 << 16, 553 .no_trimd = 1, 554 .no_ade = 1, 555 .hw_checksum = 1, 556 .tsu = 1, 557 }; 558 559 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 560 { 561 sh_eth_chip_reset(ndev); 562 563 sh_eth_select_mii(ndev); 564 } 565 566 /* R8A7740 */ 567 static struct sh_eth_cpu_data r8a7740_data = { 568 .chip_reset = sh_eth_chip_reset_r8a7740, 569 .set_duplex = sh_eth_set_duplex, 570 .set_rate = sh_eth_set_rate_gether, 571 572 .register_type = SH_ETH_REG_GIGABIT, 573 574 .ecsr_value = ECSR_ICD | ECSR_MPD, 575 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 576 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 577 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 578 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 579 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 580 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 581 EESIPR_CEEFIP | EESIPR_CELFIP | 582 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 583 EESIPR_PREIP | EESIPR_CERFIP, 584 585 .tx_check = EESR_TC1 | EESR_FTC, 586 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 587 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 588 EESR_TDE, 589 .fdr_value = 0x0000070f, 590 591 .apr = 1, 592 .mpr = 1, 593 .tpauser = 1, 594 .bculr = 1, 595 .hw_swap = 1, 596 .rpadir = 1, 597 .rpadir_value = 2 << 16, 598 .no_trimd = 1, 599 .no_ade = 1, 600 .hw_checksum = 1, 601 .tsu = 1, 602 .select_mii = 1, 603 .magic = 1, 604 }; 605 606 /* There is CPU dependent code */ 607 static void sh_eth_set_rate_rcar(struct net_device *ndev) 608 { 609 struct sh_eth_private *mdp = netdev_priv(ndev); 610 611 switch (mdp->speed) { 612 case 10: /* 10BASE */ 613 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 614 break; 615 case 100:/* 100BASE */ 616 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 617 break; 618 } 619 } 620 621 /* R-Car Gen1 */ 622 static struct sh_eth_cpu_data rcar_gen1_data = { 623 .set_duplex = sh_eth_set_duplex, 624 .set_rate = sh_eth_set_rate_rcar, 625 626 .register_type = SH_ETH_REG_FAST_RCAR, 627 628 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 629 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 630 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 631 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 632 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 633 EESIPR_RMAFIP | EESIPR_RRFIP | 634 EESIPR_RTLFIP | EESIPR_RTSFIP | 635 EESIPR_PREIP | EESIPR_CERFIP, 636 637 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 638 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 639 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 640 .fdr_value = 0x00000f0f, 641 642 .apr = 1, 643 .mpr = 1, 644 .tpauser = 1, 645 .hw_swap = 1, 646 }; 647 648 /* R-Car Gen2 and RZ/G1 */ 649 static struct sh_eth_cpu_data rcar_gen2_data = { 650 .set_duplex = sh_eth_set_duplex, 651 .set_rate = sh_eth_set_rate_rcar, 652 653 .register_type = SH_ETH_REG_FAST_RCAR, 654 655 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 656 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 657 ECSIPR_MPDIP, 658 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 659 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 660 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 661 EESIPR_RMAFIP | EESIPR_RRFIP | 662 EESIPR_RTLFIP | EESIPR_RTSFIP | 663 EESIPR_PREIP | EESIPR_CERFIP, 664 665 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 666 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 667 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 668 .fdr_value = 0x00000f0f, 669 670 .trscer_err_mask = DESC_I_RINT8, 671 672 .apr = 1, 673 .mpr = 1, 674 .tpauser = 1, 675 .hw_swap = 1, 676 .rmiimode = 1, 677 .magic = 1, 678 }; 679 #endif /* CONFIG_OF */ 680 681 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 682 { 683 struct sh_eth_private *mdp = netdev_priv(ndev); 684 685 switch (mdp->speed) { 686 case 10: /* 10BASE */ 687 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 688 break; 689 case 100:/* 100BASE */ 690 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 691 break; 692 } 693 } 694 695 /* SH7724 */ 696 static struct sh_eth_cpu_data sh7724_data = { 697 .set_duplex = sh_eth_set_duplex, 698 .set_rate = sh_eth_set_rate_sh7724, 699 700 .register_type = SH_ETH_REG_FAST_SH4, 701 702 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 703 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 704 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 705 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 706 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 707 EESIPR_RMAFIP | EESIPR_RRFIP | 708 EESIPR_RTLFIP | EESIPR_RTSFIP | 709 EESIPR_PREIP | EESIPR_CERFIP, 710 711 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 712 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 713 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 714 715 .apr = 1, 716 .mpr = 1, 717 .tpauser = 1, 718 .hw_swap = 1, 719 .rpadir = 1, 720 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 721 }; 722 723 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 724 { 725 struct sh_eth_private *mdp = netdev_priv(ndev); 726 727 switch (mdp->speed) { 728 case 10: /* 10BASE */ 729 sh_eth_write(ndev, 0, RTRATE); 730 break; 731 case 100:/* 100BASE */ 732 sh_eth_write(ndev, 1, RTRATE); 733 break; 734 } 735 } 736 737 /* SH7757 */ 738 static struct sh_eth_cpu_data sh7757_data = { 739 .set_duplex = sh_eth_set_duplex, 740 .set_rate = sh_eth_set_rate_sh7757, 741 742 .register_type = SH_ETH_REG_FAST_SH4, 743 744 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 745 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 746 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 747 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 748 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 749 EESIPR_CEEFIP | EESIPR_CELFIP | 750 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 751 EESIPR_PREIP | EESIPR_CERFIP, 752 753 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 754 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 755 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 756 757 .irq_flags = IRQF_SHARED, 758 .apr = 1, 759 .mpr = 1, 760 .tpauser = 1, 761 .hw_swap = 1, 762 .no_ade = 1, 763 .rpadir = 1, 764 .rpadir_value = 2 << 16, 765 .rtrate = 1, 766 }; 767 768 #define SH_GIGA_ETH_BASE 0xfee00000UL 769 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 770 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 771 static void sh_eth_chip_reset_giga(struct net_device *ndev) 772 { 773 u32 mahr[2], malr[2]; 774 int i; 775 776 /* save MAHR and MALR */ 777 for (i = 0; i < 2; i++) { 778 malr[i] = ioread32((void *)GIGA_MALR(i)); 779 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 780 } 781 782 sh_eth_chip_reset(ndev); 783 784 /* restore MAHR and MALR */ 785 for (i = 0; i < 2; i++) { 786 iowrite32(malr[i], (void *)GIGA_MALR(i)); 787 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 788 } 789 } 790 791 static void sh_eth_set_rate_giga(struct net_device *ndev) 792 { 793 struct sh_eth_private *mdp = netdev_priv(ndev); 794 795 switch (mdp->speed) { 796 case 10: /* 10BASE */ 797 sh_eth_write(ndev, 0x00000000, GECMR); 798 break; 799 case 100:/* 100BASE */ 800 sh_eth_write(ndev, 0x00000010, GECMR); 801 break; 802 case 1000: /* 1000BASE */ 803 sh_eth_write(ndev, 0x00000020, GECMR); 804 break; 805 } 806 } 807 808 /* SH7757(GETHERC) */ 809 static struct sh_eth_cpu_data sh7757_data_giga = { 810 .chip_reset = sh_eth_chip_reset_giga, 811 .set_duplex = sh_eth_set_duplex, 812 .set_rate = sh_eth_set_rate_giga, 813 814 .register_type = SH_ETH_REG_GIGABIT, 815 816 .ecsr_value = ECSR_ICD | ECSR_MPD, 817 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 818 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 819 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 820 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 821 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 822 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 823 EESIPR_CEEFIP | EESIPR_CELFIP | 824 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 825 EESIPR_PREIP | EESIPR_CERFIP, 826 827 .tx_check = EESR_TC1 | EESR_FTC, 828 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 829 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 830 EESR_TDE, 831 .fdr_value = 0x0000072f, 832 833 .irq_flags = IRQF_SHARED, 834 .apr = 1, 835 .mpr = 1, 836 .tpauser = 1, 837 .bculr = 1, 838 .hw_swap = 1, 839 .rpadir = 1, 840 .rpadir_value = 2 << 16, 841 .no_trimd = 1, 842 .no_ade = 1, 843 .tsu = 1, 844 }; 845 846 /* SH7734 */ 847 static struct sh_eth_cpu_data sh7734_data = { 848 .chip_reset = sh_eth_chip_reset, 849 .set_duplex = sh_eth_set_duplex, 850 .set_rate = sh_eth_set_rate_gether, 851 852 .register_type = SH_ETH_REG_GIGABIT, 853 854 .ecsr_value = ECSR_ICD | ECSR_MPD, 855 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 856 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 857 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 858 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 859 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 860 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 861 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 862 EESIPR_PREIP | EESIPR_CERFIP, 863 864 .tx_check = EESR_TC1 | EESR_FTC, 865 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 866 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 867 EESR_TDE, 868 869 .apr = 1, 870 .mpr = 1, 871 .tpauser = 1, 872 .bculr = 1, 873 .hw_swap = 1, 874 .no_trimd = 1, 875 .no_ade = 1, 876 .tsu = 1, 877 .hw_checksum = 1, 878 .select_mii = 1, 879 .magic = 1, 880 }; 881 882 /* SH7763 */ 883 static struct sh_eth_cpu_data sh7763_data = { 884 .chip_reset = sh_eth_chip_reset, 885 .set_duplex = sh_eth_set_duplex, 886 .set_rate = sh_eth_set_rate_gether, 887 888 .register_type = SH_ETH_REG_GIGABIT, 889 890 .ecsr_value = ECSR_ICD | ECSR_MPD, 891 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 892 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 893 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 894 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 895 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 896 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 897 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 898 EESIPR_PREIP | EESIPR_CERFIP, 899 900 .tx_check = EESR_TC1 | EESR_FTC, 901 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 902 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 903 904 .apr = 1, 905 .mpr = 1, 906 .tpauser = 1, 907 .bculr = 1, 908 .hw_swap = 1, 909 .no_trimd = 1, 910 .no_ade = 1, 911 .tsu = 1, 912 .irq_flags = IRQF_SHARED, 913 .magic = 1, 914 }; 915 916 static struct sh_eth_cpu_data sh7619_data = { 917 .register_type = SH_ETH_REG_FAST_SH3_SH2, 918 919 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 920 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 921 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 922 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 923 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 924 EESIPR_CEEFIP | EESIPR_CELFIP | 925 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 926 EESIPR_PREIP | EESIPR_CERFIP, 927 928 .apr = 1, 929 .mpr = 1, 930 .tpauser = 1, 931 .hw_swap = 1, 932 }; 933 934 static struct sh_eth_cpu_data sh771x_data = { 935 .register_type = SH_ETH_REG_FAST_SH3_SH2, 936 937 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 938 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 939 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 940 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 941 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 942 EESIPR_CEEFIP | EESIPR_CELFIP | 943 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 944 EESIPR_PREIP | EESIPR_CERFIP, 945 .tsu = 1, 946 }; 947 948 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 949 { 950 if (!cd->ecsr_value) 951 cd->ecsr_value = DEFAULT_ECSR_INIT; 952 953 if (!cd->ecsipr_value) 954 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 955 956 if (!cd->fcftr_value) 957 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 958 DEFAULT_FIFO_F_D_RFD; 959 960 if (!cd->fdr_value) 961 cd->fdr_value = DEFAULT_FDR_INIT; 962 963 if (!cd->tx_check) 964 cd->tx_check = DEFAULT_TX_CHECK; 965 966 if (!cd->eesr_err_check) 967 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 968 969 if (!cd->trscer_err_mask) 970 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 971 } 972 973 static int sh_eth_check_reset(struct net_device *ndev) 974 { 975 int ret = 0; 976 int cnt = 100; 977 978 while (cnt > 0) { 979 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 980 break; 981 mdelay(1); 982 cnt--; 983 } 984 if (cnt <= 0) { 985 netdev_err(ndev, "Device reset failed\n"); 986 ret = -ETIMEDOUT; 987 } 988 return ret; 989 } 990 991 static int sh_eth_reset(struct net_device *ndev) 992 { 993 struct sh_eth_private *mdp = netdev_priv(ndev); 994 int ret = 0; 995 996 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) { 997 sh_eth_write(ndev, EDSR_ENALL, EDSR); 998 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 999 1000 ret = sh_eth_check_reset(ndev); 1001 if (ret) 1002 return ret; 1003 1004 /* Table Init */ 1005 sh_eth_write(ndev, 0x0, TDLAR); 1006 sh_eth_write(ndev, 0x0, TDFAR); 1007 sh_eth_write(ndev, 0x0, TDFXR); 1008 sh_eth_write(ndev, 0x0, TDFFR); 1009 sh_eth_write(ndev, 0x0, RDLAR); 1010 sh_eth_write(ndev, 0x0, RDFAR); 1011 sh_eth_write(ndev, 0x0, RDFXR); 1012 sh_eth_write(ndev, 0x0, RDFFR); 1013 1014 /* Reset HW CRC register */ 1015 if (mdp->cd->hw_checksum) 1016 sh_eth_write(ndev, 0x0, CSMR); 1017 1018 /* Select MII mode */ 1019 if (mdp->cd->select_mii) 1020 sh_eth_select_mii(ndev); 1021 } else { 1022 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 1023 mdelay(3); 1024 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 1025 } 1026 1027 return ret; 1028 } 1029 1030 static void sh_eth_set_receive_align(struct sk_buff *skb) 1031 { 1032 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1033 1034 if (reserve) 1035 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1036 } 1037 1038 /* Program the hardware MAC address from dev->dev_addr. */ 1039 static void update_mac_address(struct net_device *ndev) 1040 { 1041 sh_eth_write(ndev, 1042 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1043 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1044 sh_eth_write(ndev, 1045 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1046 } 1047 1048 /* Get MAC address from SuperH MAC address register 1049 * 1050 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1051 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1052 * When you want use this device, you must set MAC address in bootloader. 1053 * 1054 */ 1055 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1056 { 1057 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1058 memcpy(ndev->dev_addr, mac, ETH_ALEN); 1059 } else { 1060 u32 mahr = sh_eth_read(ndev, MAHR); 1061 u32 malr = sh_eth_read(ndev, MALR); 1062 1063 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 1064 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 1065 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 1066 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 1067 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1068 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1069 } 1070 } 1071 1072 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 1073 { 1074 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) 1075 return EDTRR_TRNS_GETHER; 1076 else 1077 return EDTRR_TRNS_ETHER; 1078 } 1079 1080 struct bb_info { 1081 void (*set_gate)(void *addr); 1082 struct mdiobb_ctrl ctrl; 1083 void *addr; 1084 }; 1085 1086 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1087 { 1088 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1089 u32 pir; 1090 1091 if (bitbang->set_gate) 1092 bitbang->set_gate(bitbang->addr); 1093 1094 pir = ioread32(bitbang->addr); 1095 if (set) 1096 pir |= mask; 1097 else 1098 pir &= ~mask; 1099 iowrite32(pir, bitbang->addr); 1100 } 1101 1102 /* Data I/O pin control */ 1103 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1104 { 1105 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1106 } 1107 1108 /* Set bit data*/ 1109 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1110 { 1111 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1112 } 1113 1114 /* Get bit data*/ 1115 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1116 { 1117 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1118 1119 if (bitbang->set_gate) 1120 bitbang->set_gate(bitbang->addr); 1121 1122 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1123 } 1124 1125 /* MDC pin control */ 1126 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1127 { 1128 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1129 } 1130 1131 /* mdio bus control struct */ 1132 static struct mdiobb_ops bb_ops = { 1133 .owner = THIS_MODULE, 1134 .set_mdc = sh_mdc_ctrl, 1135 .set_mdio_dir = sh_mmd_ctrl, 1136 .set_mdio_data = sh_set_mdio, 1137 .get_mdio_data = sh_get_mdio, 1138 }; 1139 1140 /* free Tx skb function */ 1141 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1142 { 1143 struct sh_eth_private *mdp = netdev_priv(ndev); 1144 struct sh_eth_txdesc *txdesc; 1145 int free_num = 0; 1146 int entry; 1147 bool sent; 1148 1149 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1150 entry = mdp->dirty_tx % mdp->num_tx_ring; 1151 txdesc = &mdp->tx_ring[entry]; 1152 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1153 if (sent_only && !sent) 1154 break; 1155 /* TACT bit must be checked before all the following reads */ 1156 dma_rmb(); 1157 netif_info(mdp, tx_done, ndev, 1158 "tx entry %d status 0x%08x\n", 1159 entry, le32_to_cpu(txdesc->status)); 1160 /* Free the original skb. */ 1161 if (mdp->tx_skbuff[entry]) { 1162 dma_unmap_single(&mdp->pdev->dev, 1163 le32_to_cpu(txdesc->addr), 1164 le32_to_cpu(txdesc->len) >> 16, 1165 DMA_TO_DEVICE); 1166 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1167 mdp->tx_skbuff[entry] = NULL; 1168 free_num++; 1169 } 1170 txdesc->status = cpu_to_le32(TD_TFP); 1171 if (entry >= mdp->num_tx_ring - 1) 1172 txdesc->status |= cpu_to_le32(TD_TDLE); 1173 1174 if (sent) { 1175 ndev->stats.tx_packets++; 1176 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1177 } 1178 } 1179 return free_num; 1180 } 1181 1182 /* free skb and descriptor buffer */ 1183 static void sh_eth_ring_free(struct net_device *ndev) 1184 { 1185 struct sh_eth_private *mdp = netdev_priv(ndev); 1186 int ringsize, i; 1187 1188 if (mdp->rx_ring) { 1189 for (i = 0; i < mdp->num_rx_ring; i++) { 1190 if (mdp->rx_skbuff[i]) { 1191 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1192 1193 dma_unmap_single(&mdp->pdev->dev, 1194 le32_to_cpu(rxdesc->addr), 1195 ALIGN(mdp->rx_buf_sz, 32), 1196 DMA_FROM_DEVICE); 1197 } 1198 } 1199 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1200 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1201 mdp->rx_desc_dma); 1202 mdp->rx_ring = NULL; 1203 } 1204 1205 /* Free Rx skb ringbuffer */ 1206 if (mdp->rx_skbuff) { 1207 for (i = 0; i < mdp->num_rx_ring; i++) 1208 dev_kfree_skb(mdp->rx_skbuff[i]); 1209 } 1210 kfree(mdp->rx_skbuff); 1211 mdp->rx_skbuff = NULL; 1212 1213 if (mdp->tx_ring) { 1214 sh_eth_tx_free(ndev, false); 1215 1216 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1217 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1218 mdp->tx_desc_dma); 1219 mdp->tx_ring = NULL; 1220 } 1221 1222 /* Free Tx skb ringbuffer */ 1223 kfree(mdp->tx_skbuff); 1224 mdp->tx_skbuff = NULL; 1225 } 1226 1227 /* format skb and descriptor buffer */ 1228 static void sh_eth_ring_format(struct net_device *ndev) 1229 { 1230 struct sh_eth_private *mdp = netdev_priv(ndev); 1231 int i; 1232 struct sk_buff *skb; 1233 struct sh_eth_rxdesc *rxdesc = NULL; 1234 struct sh_eth_txdesc *txdesc = NULL; 1235 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1236 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1237 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1238 dma_addr_t dma_addr; 1239 u32 buf_len; 1240 1241 mdp->cur_rx = 0; 1242 mdp->cur_tx = 0; 1243 mdp->dirty_rx = 0; 1244 mdp->dirty_tx = 0; 1245 1246 memset(mdp->rx_ring, 0, rx_ringsize); 1247 1248 /* build Rx ring buffer */ 1249 for (i = 0; i < mdp->num_rx_ring; i++) { 1250 /* skb */ 1251 mdp->rx_skbuff[i] = NULL; 1252 skb = netdev_alloc_skb(ndev, skbuff_size); 1253 if (skb == NULL) 1254 break; 1255 sh_eth_set_receive_align(skb); 1256 1257 /* The size of the buffer is a multiple of 32 bytes. */ 1258 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1259 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1260 DMA_FROM_DEVICE); 1261 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1262 kfree_skb(skb); 1263 break; 1264 } 1265 mdp->rx_skbuff[i] = skb; 1266 1267 /* RX descriptor */ 1268 rxdesc = &mdp->rx_ring[i]; 1269 rxdesc->len = cpu_to_le32(buf_len << 16); 1270 rxdesc->addr = cpu_to_le32(dma_addr); 1271 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1272 1273 /* Rx descriptor address set */ 1274 if (i == 0) { 1275 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1276 if (sh_eth_is_gether(mdp) || 1277 sh_eth_is_rz_fast_ether(mdp)) 1278 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1279 } 1280 } 1281 1282 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1283 1284 /* Mark the last entry as wrapping the ring. */ 1285 if (rxdesc) 1286 rxdesc->status |= cpu_to_le32(RD_RDLE); 1287 1288 memset(mdp->tx_ring, 0, tx_ringsize); 1289 1290 /* build Tx ring buffer */ 1291 for (i = 0; i < mdp->num_tx_ring; i++) { 1292 mdp->tx_skbuff[i] = NULL; 1293 txdesc = &mdp->tx_ring[i]; 1294 txdesc->status = cpu_to_le32(TD_TFP); 1295 txdesc->len = cpu_to_le32(0); 1296 if (i == 0) { 1297 /* Tx descriptor address set */ 1298 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1299 if (sh_eth_is_gether(mdp) || 1300 sh_eth_is_rz_fast_ether(mdp)) 1301 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1302 } 1303 } 1304 1305 txdesc->status |= cpu_to_le32(TD_TDLE); 1306 } 1307 1308 /* Get skb and descriptor buffer */ 1309 static int sh_eth_ring_init(struct net_device *ndev) 1310 { 1311 struct sh_eth_private *mdp = netdev_priv(ndev); 1312 int rx_ringsize, tx_ringsize; 1313 1314 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1315 * card needs room to do 8 byte alignment, +2 so we can reserve 1316 * the first 2 bytes, and +16 gets room for the status word from the 1317 * card. 1318 */ 1319 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1320 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1321 if (mdp->cd->rpadir) 1322 mdp->rx_buf_sz += NET_IP_ALIGN; 1323 1324 /* Allocate RX and TX skb rings */ 1325 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1326 GFP_KERNEL); 1327 if (!mdp->rx_skbuff) 1328 return -ENOMEM; 1329 1330 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1331 GFP_KERNEL); 1332 if (!mdp->tx_skbuff) 1333 goto ring_free; 1334 1335 /* Allocate all Rx descriptors. */ 1336 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1337 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1338 &mdp->rx_desc_dma, GFP_KERNEL); 1339 if (!mdp->rx_ring) 1340 goto ring_free; 1341 1342 mdp->dirty_rx = 0; 1343 1344 /* Allocate all Tx descriptors. */ 1345 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1346 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1347 &mdp->tx_desc_dma, GFP_KERNEL); 1348 if (!mdp->tx_ring) 1349 goto ring_free; 1350 return 0; 1351 1352 ring_free: 1353 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1354 sh_eth_ring_free(ndev); 1355 1356 return -ENOMEM; 1357 } 1358 1359 static int sh_eth_dev_init(struct net_device *ndev) 1360 { 1361 struct sh_eth_private *mdp = netdev_priv(ndev); 1362 int ret; 1363 1364 /* Soft Reset */ 1365 ret = sh_eth_reset(ndev); 1366 if (ret) 1367 return ret; 1368 1369 if (mdp->cd->rmiimode) 1370 sh_eth_write(ndev, 0x1, RMIIMODE); 1371 1372 /* Descriptor format */ 1373 sh_eth_ring_format(ndev); 1374 if (mdp->cd->rpadir) 1375 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1376 1377 /* all sh_eth int mask */ 1378 sh_eth_write(ndev, 0, EESIPR); 1379 1380 #if defined(__LITTLE_ENDIAN) 1381 if (mdp->cd->hw_swap) 1382 sh_eth_write(ndev, EDMR_EL, EDMR); 1383 else 1384 #endif 1385 sh_eth_write(ndev, 0, EDMR); 1386 1387 /* FIFO size set */ 1388 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1389 sh_eth_write(ndev, 0, TFTR); 1390 1391 /* Frame recv control (enable multiple-packets per rx irq) */ 1392 sh_eth_write(ndev, RMCR_RNC, RMCR); 1393 1394 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1395 1396 if (mdp->cd->bculr) 1397 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1398 1399 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1400 1401 if (!mdp->cd->no_trimd) 1402 sh_eth_write(ndev, 0, TRIMD); 1403 1404 /* Recv frame limit set register */ 1405 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1406 RFLR); 1407 1408 sh_eth_modify(ndev, EESR, 0, 0); 1409 mdp->irq_enabled = true; 1410 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1411 1412 /* PAUSE Prohibition */ 1413 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1414 ECMR_TE | ECMR_RE, ECMR); 1415 1416 if (mdp->cd->set_rate) 1417 mdp->cd->set_rate(ndev); 1418 1419 /* E-MAC Status Register clear */ 1420 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1421 1422 /* E-MAC Interrupt Enable register */ 1423 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1424 1425 /* Set MAC address */ 1426 update_mac_address(ndev); 1427 1428 /* mask reset */ 1429 if (mdp->cd->apr) 1430 sh_eth_write(ndev, APR_AP, APR); 1431 if (mdp->cd->mpr) 1432 sh_eth_write(ndev, MPR_MP, MPR); 1433 if (mdp->cd->tpauser) 1434 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1435 1436 /* Setting the Rx mode will start the Rx process. */ 1437 sh_eth_write(ndev, EDRRR_R, EDRRR); 1438 1439 return ret; 1440 } 1441 1442 static void sh_eth_dev_exit(struct net_device *ndev) 1443 { 1444 struct sh_eth_private *mdp = netdev_priv(ndev); 1445 int i; 1446 1447 /* Deactivate all TX descriptors, so DMA should stop at next 1448 * packet boundary if it's currently running 1449 */ 1450 for (i = 0; i < mdp->num_tx_ring; i++) 1451 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1452 1453 /* Disable TX FIFO egress to MAC */ 1454 sh_eth_rcv_snd_disable(ndev); 1455 1456 /* Stop RX DMA at next packet boundary */ 1457 sh_eth_write(ndev, 0, EDRRR); 1458 1459 /* Aside from TX DMA, we can't tell when the hardware is 1460 * really stopped, so we need to reset to make sure. 1461 * Before doing that, wait for long enough to *probably* 1462 * finish transmitting the last packet and poll stats. 1463 */ 1464 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1465 sh_eth_get_stats(ndev); 1466 sh_eth_reset(ndev); 1467 1468 /* Set MAC address again */ 1469 update_mac_address(ndev); 1470 } 1471 1472 /* Packet receive function */ 1473 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1474 { 1475 struct sh_eth_private *mdp = netdev_priv(ndev); 1476 struct sh_eth_rxdesc *rxdesc; 1477 1478 int entry = mdp->cur_rx % mdp->num_rx_ring; 1479 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1480 int limit; 1481 struct sk_buff *skb; 1482 u32 desc_status; 1483 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1484 dma_addr_t dma_addr; 1485 u16 pkt_len; 1486 u32 buf_len; 1487 1488 boguscnt = min(boguscnt, *quota); 1489 limit = boguscnt; 1490 rxdesc = &mdp->rx_ring[entry]; 1491 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1492 /* RACT bit must be checked before all the following reads */ 1493 dma_rmb(); 1494 desc_status = le32_to_cpu(rxdesc->status); 1495 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1496 1497 if (--boguscnt < 0) 1498 break; 1499 1500 netif_info(mdp, rx_status, ndev, 1501 "rx entry %d status 0x%08x len %d\n", 1502 entry, desc_status, pkt_len); 1503 1504 if (!(desc_status & RDFEND)) 1505 ndev->stats.rx_length_errors++; 1506 1507 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1508 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1509 * bit 0. However, in case of the R8A7740 and R7S72100 1510 * the RFS bits are from bit 25 to bit 16. So, the 1511 * driver needs right shifting by 16. 1512 */ 1513 if (mdp->cd->hw_checksum) 1514 desc_status >>= 16; 1515 1516 skb = mdp->rx_skbuff[entry]; 1517 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1518 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1519 ndev->stats.rx_errors++; 1520 if (desc_status & RD_RFS1) 1521 ndev->stats.rx_crc_errors++; 1522 if (desc_status & RD_RFS2) 1523 ndev->stats.rx_frame_errors++; 1524 if (desc_status & RD_RFS3) 1525 ndev->stats.rx_length_errors++; 1526 if (desc_status & RD_RFS4) 1527 ndev->stats.rx_length_errors++; 1528 if (desc_status & RD_RFS6) 1529 ndev->stats.rx_missed_errors++; 1530 if (desc_status & RD_RFS10) 1531 ndev->stats.rx_over_errors++; 1532 } else if (skb) { 1533 dma_addr = le32_to_cpu(rxdesc->addr); 1534 if (!mdp->cd->hw_swap) 1535 sh_eth_soft_swap( 1536 phys_to_virt(ALIGN(dma_addr, 4)), 1537 pkt_len + 2); 1538 mdp->rx_skbuff[entry] = NULL; 1539 if (mdp->cd->rpadir) 1540 skb_reserve(skb, NET_IP_ALIGN); 1541 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1542 ALIGN(mdp->rx_buf_sz, 32), 1543 DMA_FROM_DEVICE); 1544 skb_put(skb, pkt_len); 1545 skb->protocol = eth_type_trans(skb, ndev); 1546 netif_receive_skb(skb); 1547 ndev->stats.rx_packets++; 1548 ndev->stats.rx_bytes += pkt_len; 1549 if (desc_status & RD_RFS8) 1550 ndev->stats.multicast++; 1551 } 1552 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1553 rxdesc = &mdp->rx_ring[entry]; 1554 } 1555 1556 /* Refill the Rx ring buffers. */ 1557 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1558 entry = mdp->dirty_rx % mdp->num_rx_ring; 1559 rxdesc = &mdp->rx_ring[entry]; 1560 /* The size of the buffer is 32 byte boundary. */ 1561 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1562 rxdesc->len = cpu_to_le32(buf_len << 16); 1563 1564 if (mdp->rx_skbuff[entry] == NULL) { 1565 skb = netdev_alloc_skb(ndev, skbuff_size); 1566 if (skb == NULL) 1567 break; /* Better luck next round. */ 1568 sh_eth_set_receive_align(skb); 1569 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1570 buf_len, DMA_FROM_DEVICE); 1571 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1572 kfree_skb(skb); 1573 break; 1574 } 1575 mdp->rx_skbuff[entry] = skb; 1576 1577 skb_checksum_none_assert(skb); 1578 rxdesc->addr = cpu_to_le32(dma_addr); 1579 } 1580 dma_wmb(); /* RACT bit must be set after all the above writes */ 1581 if (entry >= mdp->num_rx_ring - 1) 1582 rxdesc->status |= 1583 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1584 else 1585 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1586 } 1587 1588 /* Restart Rx engine if stopped. */ 1589 /* If we don't need to check status, don't. -KDU */ 1590 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1591 /* fix the values for the next receiving if RDE is set */ 1592 if (intr_status & EESR_RDE && 1593 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) { 1594 u32 count = (sh_eth_read(ndev, RDFAR) - 1595 sh_eth_read(ndev, RDLAR)) >> 4; 1596 1597 mdp->cur_rx = count; 1598 mdp->dirty_rx = count; 1599 } 1600 sh_eth_write(ndev, EDRRR_R, EDRRR); 1601 } 1602 1603 *quota -= limit - boguscnt - 1; 1604 1605 return *quota <= 0; 1606 } 1607 1608 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1609 { 1610 /* disable tx and rx */ 1611 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1612 } 1613 1614 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1615 { 1616 /* enable tx and rx */ 1617 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1618 } 1619 1620 /* E-MAC interrupt handler */ 1621 static void sh_eth_emac_interrupt(struct net_device *ndev) 1622 { 1623 struct sh_eth_private *mdp = netdev_priv(ndev); 1624 u32 felic_stat; 1625 u32 link_stat; 1626 1627 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1628 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1629 if (felic_stat & ECSR_ICD) 1630 ndev->stats.tx_carrier_errors++; 1631 if (felic_stat & ECSR_MPD) 1632 pm_wakeup_event(&mdp->pdev->dev, 0); 1633 if (felic_stat & ECSR_LCHNG) { 1634 /* Link Changed */ 1635 if (mdp->cd->no_psr || mdp->no_ether_link) 1636 return; 1637 link_stat = sh_eth_read(ndev, PSR); 1638 if (mdp->ether_link_active_low) 1639 link_stat = ~link_stat; 1640 if (!(link_stat & PHY_ST_LINK)) { 1641 sh_eth_rcv_snd_disable(ndev); 1642 } else { 1643 /* Link Up */ 1644 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1645 /* clear int */ 1646 sh_eth_modify(ndev, ECSR, 0, 0); 1647 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1648 /* enable tx and rx */ 1649 sh_eth_rcv_snd_enable(ndev); 1650 } 1651 } 1652 } 1653 1654 /* error control function */ 1655 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1656 { 1657 struct sh_eth_private *mdp = netdev_priv(ndev); 1658 u32 mask; 1659 1660 if (intr_status & EESR_TWB) { 1661 /* Unused write back interrupt */ 1662 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1663 ndev->stats.tx_aborted_errors++; 1664 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1665 } 1666 } 1667 1668 if (intr_status & EESR_RABT) { 1669 /* Receive Abort int */ 1670 if (intr_status & EESR_RFRMER) { 1671 /* Receive Frame Overflow int */ 1672 ndev->stats.rx_frame_errors++; 1673 } 1674 } 1675 1676 if (intr_status & EESR_TDE) { 1677 /* Transmit Descriptor Empty int */ 1678 ndev->stats.tx_fifo_errors++; 1679 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1680 } 1681 1682 if (intr_status & EESR_TFE) { 1683 /* FIFO under flow */ 1684 ndev->stats.tx_fifo_errors++; 1685 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1686 } 1687 1688 if (intr_status & EESR_RDE) { 1689 /* Receive Descriptor Empty int */ 1690 ndev->stats.rx_over_errors++; 1691 } 1692 1693 if (intr_status & EESR_RFE) { 1694 /* Receive FIFO Overflow int */ 1695 ndev->stats.rx_fifo_errors++; 1696 } 1697 1698 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1699 /* Address Error */ 1700 ndev->stats.tx_fifo_errors++; 1701 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1702 } 1703 1704 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1705 if (mdp->cd->no_ade) 1706 mask &= ~EESR_ADE; 1707 if (intr_status & mask) { 1708 /* Tx error */ 1709 u32 edtrr = sh_eth_read(ndev, EDTRR); 1710 1711 /* dmesg */ 1712 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1713 intr_status, mdp->cur_tx, mdp->dirty_tx, 1714 (u32)ndev->state, edtrr); 1715 /* dirty buffer free */ 1716 sh_eth_tx_free(ndev, true); 1717 1718 /* SH7712 BUG */ 1719 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1720 /* tx dma start */ 1721 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1722 } 1723 /* wakeup */ 1724 netif_wake_queue(ndev); 1725 } 1726 } 1727 1728 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1729 { 1730 struct net_device *ndev = netdev; 1731 struct sh_eth_private *mdp = netdev_priv(ndev); 1732 struct sh_eth_cpu_data *cd = mdp->cd; 1733 irqreturn_t ret = IRQ_NONE; 1734 u32 intr_status, intr_enable; 1735 1736 spin_lock(&mdp->lock); 1737 1738 /* Get interrupt status */ 1739 intr_status = sh_eth_read(ndev, EESR); 1740 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1741 * enabled since it's the one that comes thru regardless of the mask, 1742 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1743 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1744 * bit... 1745 */ 1746 intr_enable = sh_eth_read(ndev, EESIPR); 1747 intr_status &= intr_enable | EESIPR_ECIIP; 1748 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1749 cd->eesr_err_check)) 1750 ret = IRQ_HANDLED; 1751 else 1752 goto out; 1753 1754 if (unlikely(!mdp->irq_enabled)) { 1755 sh_eth_write(ndev, 0, EESIPR); 1756 goto out; 1757 } 1758 1759 if (intr_status & EESR_RX_CHECK) { 1760 if (napi_schedule_prep(&mdp->napi)) { 1761 /* Mask Rx interrupts */ 1762 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1763 EESIPR); 1764 __napi_schedule(&mdp->napi); 1765 } else { 1766 netdev_warn(ndev, 1767 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1768 intr_status, intr_enable); 1769 } 1770 } 1771 1772 /* Tx Check */ 1773 if (intr_status & cd->tx_check) { 1774 /* Clear Tx interrupts */ 1775 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1776 1777 sh_eth_tx_free(ndev, true); 1778 netif_wake_queue(ndev); 1779 } 1780 1781 /* E-MAC interrupt */ 1782 if (intr_status & EESR_ECI) 1783 sh_eth_emac_interrupt(ndev); 1784 1785 if (intr_status & cd->eesr_err_check) { 1786 /* Clear error interrupts */ 1787 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1788 1789 sh_eth_error(ndev, intr_status); 1790 } 1791 1792 out: 1793 spin_unlock(&mdp->lock); 1794 1795 return ret; 1796 } 1797 1798 static int sh_eth_poll(struct napi_struct *napi, int budget) 1799 { 1800 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1801 napi); 1802 struct net_device *ndev = napi->dev; 1803 int quota = budget; 1804 u32 intr_status; 1805 1806 for (;;) { 1807 intr_status = sh_eth_read(ndev, EESR); 1808 if (!(intr_status & EESR_RX_CHECK)) 1809 break; 1810 /* Clear Rx interrupts */ 1811 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1812 1813 if (sh_eth_rx(ndev, intr_status, "a)) 1814 goto out; 1815 } 1816 1817 napi_complete(napi); 1818 1819 /* Reenable Rx interrupts */ 1820 if (mdp->irq_enabled) 1821 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1822 out: 1823 return budget - quota; 1824 } 1825 1826 /* PHY state control function */ 1827 static void sh_eth_adjust_link(struct net_device *ndev) 1828 { 1829 struct sh_eth_private *mdp = netdev_priv(ndev); 1830 struct phy_device *phydev = ndev->phydev; 1831 int new_state = 0; 1832 1833 if (phydev->link) { 1834 if (phydev->duplex != mdp->duplex) { 1835 new_state = 1; 1836 mdp->duplex = phydev->duplex; 1837 if (mdp->cd->set_duplex) 1838 mdp->cd->set_duplex(ndev); 1839 } 1840 1841 if (phydev->speed != mdp->speed) { 1842 new_state = 1; 1843 mdp->speed = phydev->speed; 1844 if (mdp->cd->set_rate) 1845 mdp->cd->set_rate(ndev); 1846 } 1847 if (!mdp->link) { 1848 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1849 new_state = 1; 1850 mdp->link = phydev->link; 1851 if (mdp->cd->no_psr || mdp->no_ether_link) 1852 sh_eth_rcv_snd_enable(ndev); 1853 } 1854 } else if (mdp->link) { 1855 new_state = 1; 1856 mdp->link = 0; 1857 mdp->speed = 0; 1858 mdp->duplex = -1; 1859 if (mdp->cd->no_psr || mdp->no_ether_link) 1860 sh_eth_rcv_snd_disable(ndev); 1861 } 1862 1863 if (new_state && netif_msg_link(mdp)) 1864 phy_print_status(phydev); 1865 } 1866 1867 /* PHY init function */ 1868 static int sh_eth_phy_init(struct net_device *ndev) 1869 { 1870 struct device_node *np = ndev->dev.parent->of_node; 1871 struct sh_eth_private *mdp = netdev_priv(ndev); 1872 struct phy_device *phydev; 1873 1874 mdp->link = 0; 1875 mdp->speed = 0; 1876 mdp->duplex = -1; 1877 1878 /* Try connect to PHY */ 1879 if (np) { 1880 struct device_node *pn; 1881 1882 pn = of_parse_phandle(np, "phy-handle", 0); 1883 phydev = of_phy_connect(ndev, pn, 1884 sh_eth_adjust_link, 0, 1885 mdp->phy_interface); 1886 1887 of_node_put(pn); 1888 if (!phydev) 1889 phydev = ERR_PTR(-ENOENT); 1890 } else { 1891 char phy_id[MII_BUS_ID_SIZE + 3]; 1892 1893 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1894 mdp->mii_bus->id, mdp->phy_id); 1895 1896 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1897 mdp->phy_interface); 1898 } 1899 1900 if (IS_ERR(phydev)) { 1901 netdev_err(ndev, "failed to connect PHY\n"); 1902 return PTR_ERR(phydev); 1903 } 1904 1905 /* mask with MAC supported features */ 1906 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) { 1907 int err = phy_set_max_speed(phydev, SPEED_100); 1908 if (err) { 1909 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n"); 1910 phy_disconnect(phydev); 1911 return err; 1912 } 1913 } 1914 1915 phy_attached_info(phydev); 1916 1917 return 0; 1918 } 1919 1920 /* PHY control start function */ 1921 static int sh_eth_phy_start(struct net_device *ndev) 1922 { 1923 int ret; 1924 1925 ret = sh_eth_phy_init(ndev); 1926 if (ret) 1927 return ret; 1928 1929 phy_start(ndev->phydev); 1930 1931 return 0; 1932 } 1933 1934 static int sh_eth_get_link_ksettings(struct net_device *ndev, 1935 struct ethtool_link_ksettings *cmd) 1936 { 1937 struct sh_eth_private *mdp = netdev_priv(ndev); 1938 unsigned long flags; 1939 1940 if (!ndev->phydev) 1941 return -ENODEV; 1942 1943 spin_lock_irqsave(&mdp->lock, flags); 1944 phy_ethtool_ksettings_get(ndev->phydev, cmd); 1945 spin_unlock_irqrestore(&mdp->lock, flags); 1946 1947 return 0; 1948 } 1949 1950 static int sh_eth_set_link_ksettings(struct net_device *ndev, 1951 const struct ethtool_link_ksettings *cmd) 1952 { 1953 struct sh_eth_private *mdp = netdev_priv(ndev); 1954 unsigned long flags; 1955 int ret; 1956 1957 if (!ndev->phydev) 1958 return -ENODEV; 1959 1960 spin_lock_irqsave(&mdp->lock, flags); 1961 1962 /* disable tx and rx */ 1963 sh_eth_rcv_snd_disable(ndev); 1964 1965 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd); 1966 if (ret) 1967 goto error_exit; 1968 1969 if (cmd->base.duplex == DUPLEX_FULL) 1970 mdp->duplex = 1; 1971 else 1972 mdp->duplex = 0; 1973 1974 if (mdp->cd->set_duplex) 1975 mdp->cd->set_duplex(ndev); 1976 1977 error_exit: 1978 mdelay(1); 1979 1980 /* enable tx and rx */ 1981 sh_eth_rcv_snd_enable(ndev); 1982 1983 spin_unlock_irqrestore(&mdp->lock, flags); 1984 1985 return ret; 1986 } 1987 1988 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 1989 * version must be bumped as well. Just adding registers up to that 1990 * limit is fine, as long as the existing register indices don't 1991 * change. 1992 */ 1993 #define SH_ETH_REG_DUMP_VERSION 1 1994 #define SH_ETH_REG_DUMP_MAX_REGS 256 1995 1996 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 1997 { 1998 struct sh_eth_private *mdp = netdev_priv(ndev); 1999 struct sh_eth_cpu_data *cd = mdp->cd; 2000 u32 *valid_map; 2001 size_t len; 2002 2003 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 2004 2005 /* Dump starts with a bitmap that tells ethtool which 2006 * registers are defined for this chip. 2007 */ 2008 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 2009 if (buf) { 2010 valid_map = buf; 2011 buf += len; 2012 } else { 2013 valid_map = NULL; 2014 } 2015 2016 /* Add a register to the dump, if it has a defined offset. 2017 * This automatically skips most undefined registers, but for 2018 * some it is also necessary to check a capability flag in 2019 * struct sh_eth_cpu_data. 2020 */ 2021 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2022 #define add_reg_from(reg, read_expr) do { \ 2023 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2024 if (buf) { \ 2025 mark_reg_valid(reg); \ 2026 *buf++ = read_expr; \ 2027 } \ 2028 ++len; \ 2029 } \ 2030 } while (0) 2031 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2032 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2033 2034 add_reg(EDSR); 2035 add_reg(EDMR); 2036 add_reg(EDTRR); 2037 add_reg(EDRRR); 2038 add_reg(EESR); 2039 add_reg(EESIPR); 2040 add_reg(TDLAR); 2041 add_reg(TDFAR); 2042 add_reg(TDFXR); 2043 add_reg(TDFFR); 2044 add_reg(RDLAR); 2045 add_reg(RDFAR); 2046 add_reg(RDFXR); 2047 add_reg(RDFFR); 2048 add_reg(TRSCER); 2049 add_reg(RMFCR); 2050 add_reg(TFTR); 2051 add_reg(FDR); 2052 add_reg(RMCR); 2053 add_reg(TFUCR); 2054 add_reg(RFOCR); 2055 if (cd->rmiimode) 2056 add_reg(RMIIMODE); 2057 add_reg(FCFTR); 2058 if (cd->rpadir) 2059 add_reg(RPADIR); 2060 if (!cd->no_trimd) 2061 add_reg(TRIMD); 2062 add_reg(ECMR); 2063 add_reg(ECSR); 2064 add_reg(ECSIPR); 2065 add_reg(PIR); 2066 if (!cd->no_psr) 2067 add_reg(PSR); 2068 add_reg(RDMLR); 2069 add_reg(RFLR); 2070 add_reg(IPGR); 2071 if (cd->apr) 2072 add_reg(APR); 2073 if (cd->mpr) 2074 add_reg(MPR); 2075 add_reg(RFCR); 2076 add_reg(RFCF); 2077 if (cd->tpauser) 2078 add_reg(TPAUSER); 2079 add_reg(TPAUSECR); 2080 add_reg(GECMR); 2081 if (cd->bculr) 2082 add_reg(BCULR); 2083 add_reg(MAHR); 2084 add_reg(MALR); 2085 add_reg(TROCR); 2086 add_reg(CDCR); 2087 add_reg(LCCR); 2088 add_reg(CNDCR); 2089 add_reg(CEFCR); 2090 add_reg(FRECR); 2091 add_reg(TSFRCR); 2092 add_reg(TLFRCR); 2093 add_reg(CERCR); 2094 add_reg(CEECR); 2095 add_reg(MAFCR); 2096 if (cd->rtrate) 2097 add_reg(RTRATE); 2098 if (cd->hw_checksum) 2099 add_reg(CSMR); 2100 if (cd->select_mii) 2101 add_reg(RMII_MII); 2102 if (cd->tsu) { 2103 add_tsu_reg(ARSTR); 2104 add_tsu_reg(TSU_CTRST); 2105 add_tsu_reg(TSU_FWEN0); 2106 add_tsu_reg(TSU_FWEN1); 2107 add_tsu_reg(TSU_FCM); 2108 add_tsu_reg(TSU_BSYSL0); 2109 add_tsu_reg(TSU_BSYSL1); 2110 add_tsu_reg(TSU_PRISL0); 2111 add_tsu_reg(TSU_PRISL1); 2112 add_tsu_reg(TSU_FWSL0); 2113 add_tsu_reg(TSU_FWSL1); 2114 add_tsu_reg(TSU_FWSLC); 2115 add_tsu_reg(TSU_QTAG0); 2116 add_tsu_reg(TSU_QTAG1); 2117 add_tsu_reg(TSU_QTAGM0); 2118 add_tsu_reg(TSU_QTAGM1); 2119 add_tsu_reg(TSU_FWSR); 2120 add_tsu_reg(TSU_FWINMK); 2121 add_tsu_reg(TSU_ADQT0); 2122 add_tsu_reg(TSU_ADQT1); 2123 add_tsu_reg(TSU_VTAG0); 2124 add_tsu_reg(TSU_VTAG1); 2125 add_tsu_reg(TSU_ADSBSY); 2126 add_tsu_reg(TSU_TEN); 2127 add_tsu_reg(TSU_POST1); 2128 add_tsu_reg(TSU_POST2); 2129 add_tsu_reg(TSU_POST3); 2130 add_tsu_reg(TSU_POST4); 2131 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) { 2132 /* This is the start of a table, not just a single 2133 * register. 2134 */ 2135 if (buf) { 2136 unsigned int i; 2137 2138 mark_reg_valid(TSU_ADRH0); 2139 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2140 *buf++ = ioread32( 2141 mdp->tsu_addr + 2142 mdp->reg_offset[TSU_ADRH0] + 2143 i * 4); 2144 } 2145 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2146 } 2147 } 2148 2149 #undef mark_reg_valid 2150 #undef add_reg_from 2151 #undef add_reg 2152 #undef add_tsu_reg 2153 2154 return len * 4; 2155 } 2156 2157 static int sh_eth_get_regs_len(struct net_device *ndev) 2158 { 2159 return __sh_eth_get_regs(ndev, NULL); 2160 } 2161 2162 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2163 void *buf) 2164 { 2165 struct sh_eth_private *mdp = netdev_priv(ndev); 2166 2167 regs->version = SH_ETH_REG_DUMP_VERSION; 2168 2169 pm_runtime_get_sync(&mdp->pdev->dev); 2170 __sh_eth_get_regs(ndev, buf); 2171 pm_runtime_put_sync(&mdp->pdev->dev); 2172 } 2173 2174 static int sh_eth_nway_reset(struct net_device *ndev) 2175 { 2176 struct sh_eth_private *mdp = netdev_priv(ndev); 2177 unsigned long flags; 2178 int ret; 2179 2180 if (!ndev->phydev) 2181 return -ENODEV; 2182 2183 spin_lock_irqsave(&mdp->lock, flags); 2184 ret = phy_start_aneg(ndev->phydev); 2185 spin_unlock_irqrestore(&mdp->lock, flags); 2186 2187 return ret; 2188 } 2189 2190 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2191 { 2192 struct sh_eth_private *mdp = netdev_priv(ndev); 2193 return mdp->msg_enable; 2194 } 2195 2196 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2197 { 2198 struct sh_eth_private *mdp = netdev_priv(ndev); 2199 mdp->msg_enable = value; 2200 } 2201 2202 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2203 "rx_current", "tx_current", 2204 "rx_dirty", "tx_dirty", 2205 }; 2206 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2207 2208 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2209 { 2210 switch (sset) { 2211 case ETH_SS_STATS: 2212 return SH_ETH_STATS_LEN; 2213 default: 2214 return -EOPNOTSUPP; 2215 } 2216 } 2217 2218 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2219 struct ethtool_stats *stats, u64 *data) 2220 { 2221 struct sh_eth_private *mdp = netdev_priv(ndev); 2222 int i = 0; 2223 2224 /* device-specific stats */ 2225 data[i++] = mdp->cur_rx; 2226 data[i++] = mdp->cur_tx; 2227 data[i++] = mdp->dirty_rx; 2228 data[i++] = mdp->dirty_tx; 2229 } 2230 2231 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2232 { 2233 switch (stringset) { 2234 case ETH_SS_STATS: 2235 memcpy(data, *sh_eth_gstrings_stats, 2236 sizeof(sh_eth_gstrings_stats)); 2237 break; 2238 } 2239 } 2240 2241 static void sh_eth_get_ringparam(struct net_device *ndev, 2242 struct ethtool_ringparam *ring) 2243 { 2244 struct sh_eth_private *mdp = netdev_priv(ndev); 2245 2246 ring->rx_max_pending = RX_RING_MAX; 2247 ring->tx_max_pending = TX_RING_MAX; 2248 ring->rx_pending = mdp->num_rx_ring; 2249 ring->tx_pending = mdp->num_tx_ring; 2250 } 2251 2252 static int sh_eth_set_ringparam(struct net_device *ndev, 2253 struct ethtool_ringparam *ring) 2254 { 2255 struct sh_eth_private *mdp = netdev_priv(ndev); 2256 int ret; 2257 2258 if (ring->tx_pending > TX_RING_MAX || 2259 ring->rx_pending > RX_RING_MAX || 2260 ring->tx_pending < TX_RING_MIN || 2261 ring->rx_pending < RX_RING_MIN) 2262 return -EINVAL; 2263 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2264 return -EINVAL; 2265 2266 if (netif_running(ndev)) { 2267 netif_device_detach(ndev); 2268 netif_tx_disable(ndev); 2269 2270 /* Serialise with the interrupt handler and NAPI, then 2271 * disable interrupts. We have to clear the 2272 * irq_enabled flag first to ensure that interrupts 2273 * won't be re-enabled. 2274 */ 2275 mdp->irq_enabled = false; 2276 synchronize_irq(ndev->irq); 2277 napi_synchronize(&mdp->napi); 2278 sh_eth_write(ndev, 0x0000, EESIPR); 2279 2280 sh_eth_dev_exit(ndev); 2281 2282 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2283 sh_eth_ring_free(ndev); 2284 } 2285 2286 /* Set new parameters */ 2287 mdp->num_rx_ring = ring->rx_pending; 2288 mdp->num_tx_ring = ring->tx_pending; 2289 2290 if (netif_running(ndev)) { 2291 ret = sh_eth_ring_init(ndev); 2292 if (ret < 0) { 2293 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2294 __func__); 2295 return ret; 2296 } 2297 ret = sh_eth_dev_init(ndev); 2298 if (ret < 0) { 2299 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2300 __func__); 2301 return ret; 2302 } 2303 2304 netif_device_attach(ndev); 2305 } 2306 2307 return 0; 2308 } 2309 2310 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2311 { 2312 struct sh_eth_private *mdp = netdev_priv(ndev); 2313 2314 wol->supported = 0; 2315 wol->wolopts = 0; 2316 2317 if (mdp->cd->magic) { 2318 wol->supported = WAKE_MAGIC; 2319 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2320 } 2321 } 2322 2323 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2324 { 2325 struct sh_eth_private *mdp = netdev_priv(ndev); 2326 2327 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2328 return -EOPNOTSUPP; 2329 2330 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2331 2332 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2333 2334 return 0; 2335 } 2336 2337 static const struct ethtool_ops sh_eth_ethtool_ops = { 2338 .get_regs_len = sh_eth_get_regs_len, 2339 .get_regs = sh_eth_get_regs, 2340 .nway_reset = sh_eth_nway_reset, 2341 .get_msglevel = sh_eth_get_msglevel, 2342 .set_msglevel = sh_eth_set_msglevel, 2343 .get_link = ethtool_op_get_link, 2344 .get_strings = sh_eth_get_strings, 2345 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2346 .get_sset_count = sh_eth_get_sset_count, 2347 .get_ringparam = sh_eth_get_ringparam, 2348 .set_ringparam = sh_eth_set_ringparam, 2349 .get_link_ksettings = sh_eth_get_link_ksettings, 2350 .set_link_ksettings = sh_eth_set_link_ksettings, 2351 .get_wol = sh_eth_get_wol, 2352 .set_wol = sh_eth_set_wol, 2353 }; 2354 2355 /* network device open function */ 2356 static int sh_eth_open(struct net_device *ndev) 2357 { 2358 struct sh_eth_private *mdp = netdev_priv(ndev); 2359 int ret; 2360 2361 pm_runtime_get_sync(&mdp->pdev->dev); 2362 2363 napi_enable(&mdp->napi); 2364 2365 ret = request_irq(ndev->irq, sh_eth_interrupt, 2366 mdp->cd->irq_flags, ndev->name, ndev); 2367 if (ret) { 2368 netdev_err(ndev, "Can not assign IRQ number\n"); 2369 goto out_napi_off; 2370 } 2371 2372 /* Descriptor set */ 2373 ret = sh_eth_ring_init(ndev); 2374 if (ret) 2375 goto out_free_irq; 2376 2377 /* device init */ 2378 ret = sh_eth_dev_init(ndev); 2379 if (ret) 2380 goto out_free_irq; 2381 2382 /* PHY control start*/ 2383 ret = sh_eth_phy_start(ndev); 2384 if (ret) 2385 goto out_free_irq; 2386 2387 netif_start_queue(ndev); 2388 2389 mdp->is_opened = 1; 2390 2391 return ret; 2392 2393 out_free_irq: 2394 free_irq(ndev->irq, ndev); 2395 out_napi_off: 2396 napi_disable(&mdp->napi); 2397 pm_runtime_put_sync(&mdp->pdev->dev); 2398 return ret; 2399 } 2400 2401 /* Timeout function */ 2402 static void sh_eth_tx_timeout(struct net_device *ndev) 2403 { 2404 struct sh_eth_private *mdp = netdev_priv(ndev); 2405 struct sh_eth_rxdesc *rxdesc; 2406 int i; 2407 2408 netif_stop_queue(ndev); 2409 2410 netif_err(mdp, timer, ndev, 2411 "transmit timed out, status %8.8x, resetting...\n", 2412 sh_eth_read(ndev, EESR)); 2413 2414 /* tx_errors count up */ 2415 ndev->stats.tx_errors++; 2416 2417 /* Free all the skbuffs in the Rx queue. */ 2418 for (i = 0; i < mdp->num_rx_ring; i++) { 2419 rxdesc = &mdp->rx_ring[i]; 2420 rxdesc->status = cpu_to_le32(0); 2421 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2422 dev_kfree_skb(mdp->rx_skbuff[i]); 2423 mdp->rx_skbuff[i] = NULL; 2424 } 2425 for (i = 0; i < mdp->num_tx_ring; i++) { 2426 dev_kfree_skb(mdp->tx_skbuff[i]); 2427 mdp->tx_skbuff[i] = NULL; 2428 } 2429 2430 /* device init */ 2431 sh_eth_dev_init(ndev); 2432 2433 netif_start_queue(ndev); 2434 } 2435 2436 /* Packet transmit function */ 2437 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2438 { 2439 struct sh_eth_private *mdp = netdev_priv(ndev); 2440 struct sh_eth_txdesc *txdesc; 2441 dma_addr_t dma_addr; 2442 u32 entry; 2443 unsigned long flags; 2444 2445 spin_lock_irqsave(&mdp->lock, flags); 2446 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2447 if (!sh_eth_tx_free(ndev, true)) { 2448 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2449 netif_stop_queue(ndev); 2450 spin_unlock_irqrestore(&mdp->lock, flags); 2451 return NETDEV_TX_BUSY; 2452 } 2453 } 2454 spin_unlock_irqrestore(&mdp->lock, flags); 2455 2456 if (skb_put_padto(skb, ETH_ZLEN)) 2457 return NETDEV_TX_OK; 2458 2459 entry = mdp->cur_tx % mdp->num_tx_ring; 2460 mdp->tx_skbuff[entry] = skb; 2461 txdesc = &mdp->tx_ring[entry]; 2462 /* soft swap. */ 2463 if (!mdp->cd->hw_swap) 2464 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2465 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2466 DMA_TO_DEVICE); 2467 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2468 kfree_skb(skb); 2469 return NETDEV_TX_OK; 2470 } 2471 txdesc->addr = cpu_to_le32(dma_addr); 2472 txdesc->len = cpu_to_le32(skb->len << 16); 2473 2474 dma_wmb(); /* TACT bit must be set after all the above writes */ 2475 if (entry >= mdp->num_tx_ring - 1) 2476 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2477 else 2478 txdesc->status |= cpu_to_le32(TD_TACT); 2479 2480 mdp->cur_tx++; 2481 2482 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 2483 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 2484 2485 return NETDEV_TX_OK; 2486 } 2487 2488 /* The statistics registers have write-clear behaviour, which means we 2489 * will lose any increment between the read and write. We mitigate 2490 * this by only clearing when we read a non-zero value, so we will 2491 * never falsely report a total of zero. 2492 */ 2493 static void 2494 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2495 { 2496 u32 delta = sh_eth_read(ndev, reg); 2497 2498 if (delta) { 2499 *stat += delta; 2500 sh_eth_write(ndev, 0, reg); 2501 } 2502 } 2503 2504 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2505 { 2506 struct sh_eth_private *mdp = netdev_priv(ndev); 2507 2508 if (sh_eth_is_rz_fast_ether(mdp)) 2509 return &ndev->stats; 2510 2511 if (!mdp->is_opened) 2512 return &ndev->stats; 2513 2514 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2515 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2516 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2517 2518 if (sh_eth_is_gether(mdp)) { 2519 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2520 CERCR); 2521 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2522 CEECR); 2523 } else { 2524 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2525 CNDCR); 2526 } 2527 2528 return &ndev->stats; 2529 } 2530 2531 /* device close function */ 2532 static int sh_eth_close(struct net_device *ndev) 2533 { 2534 struct sh_eth_private *mdp = netdev_priv(ndev); 2535 2536 netif_stop_queue(ndev); 2537 2538 /* Serialise with the interrupt handler and NAPI, then disable 2539 * interrupts. We have to clear the irq_enabled flag first to 2540 * ensure that interrupts won't be re-enabled. 2541 */ 2542 mdp->irq_enabled = false; 2543 synchronize_irq(ndev->irq); 2544 napi_disable(&mdp->napi); 2545 sh_eth_write(ndev, 0x0000, EESIPR); 2546 2547 sh_eth_dev_exit(ndev); 2548 2549 /* PHY Disconnect */ 2550 if (ndev->phydev) { 2551 phy_stop(ndev->phydev); 2552 phy_disconnect(ndev->phydev); 2553 } 2554 2555 free_irq(ndev->irq, ndev); 2556 2557 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2558 sh_eth_ring_free(ndev); 2559 2560 pm_runtime_put_sync(&mdp->pdev->dev); 2561 2562 mdp->is_opened = 0; 2563 2564 return 0; 2565 } 2566 2567 /* ioctl to device function */ 2568 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2569 { 2570 struct phy_device *phydev = ndev->phydev; 2571 2572 if (!netif_running(ndev)) 2573 return -EINVAL; 2574 2575 if (!phydev) 2576 return -ENODEV; 2577 2578 return phy_mii_ioctl(phydev, rq, cmd); 2579 } 2580 2581 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2582 { 2583 if (netif_running(ndev)) 2584 return -EBUSY; 2585 2586 ndev->mtu = new_mtu; 2587 netdev_update_features(ndev); 2588 2589 return 0; 2590 } 2591 2592 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2593 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2594 int entry) 2595 { 2596 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2597 } 2598 2599 static u32 sh_eth_tsu_get_post_mask(int entry) 2600 { 2601 return 0x0f << (28 - ((entry % 8) * 4)); 2602 } 2603 2604 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2605 { 2606 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2607 } 2608 2609 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2610 int entry) 2611 { 2612 struct sh_eth_private *mdp = netdev_priv(ndev); 2613 u32 tmp; 2614 void *reg_offset; 2615 2616 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2617 tmp = ioread32(reg_offset); 2618 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2619 } 2620 2621 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2622 int entry) 2623 { 2624 struct sh_eth_private *mdp = netdev_priv(ndev); 2625 u32 post_mask, ref_mask, tmp; 2626 void *reg_offset; 2627 2628 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2629 post_mask = sh_eth_tsu_get_post_mask(entry); 2630 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2631 2632 tmp = ioread32(reg_offset); 2633 iowrite32(tmp & ~post_mask, reg_offset); 2634 2635 /* If other port enables, the function returns "true" */ 2636 return tmp & ref_mask; 2637 } 2638 2639 static int sh_eth_tsu_busy(struct net_device *ndev) 2640 { 2641 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2642 struct sh_eth_private *mdp = netdev_priv(ndev); 2643 2644 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2645 udelay(10); 2646 timeout--; 2647 if (timeout <= 0) { 2648 netdev_err(ndev, "%s: timeout\n", __func__); 2649 return -ETIMEDOUT; 2650 } 2651 } 2652 2653 return 0; 2654 } 2655 2656 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2657 const u8 *addr) 2658 { 2659 u32 val; 2660 2661 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2662 iowrite32(val, reg); 2663 if (sh_eth_tsu_busy(ndev) < 0) 2664 return -EBUSY; 2665 2666 val = addr[4] << 8 | addr[5]; 2667 iowrite32(val, reg + 4); 2668 if (sh_eth_tsu_busy(ndev) < 0) 2669 return -EBUSY; 2670 2671 return 0; 2672 } 2673 2674 static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2675 { 2676 u32 val; 2677 2678 val = ioread32(reg); 2679 addr[0] = (val >> 24) & 0xff; 2680 addr[1] = (val >> 16) & 0xff; 2681 addr[2] = (val >> 8) & 0xff; 2682 addr[3] = val & 0xff; 2683 val = ioread32(reg + 4); 2684 addr[4] = (val >> 8) & 0xff; 2685 addr[5] = val & 0xff; 2686 } 2687 2688 2689 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2690 { 2691 struct sh_eth_private *mdp = netdev_priv(ndev); 2692 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2693 int i; 2694 u8 c_addr[ETH_ALEN]; 2695 2696 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2697 sh_eth_tsu_read_entry(reg_offset, c_addr); 2698 if (ether_addr_equal(addr, c_addr)) 2699 return i; 2700 } 2701 2702 return -ENOENT; 2703 } 2704 2705 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2706 { 2707 u8 blank[ETH_ALEN]; 2708 int entry; 2709 2710 memset(blank, 0, sizeof(blank)); 2711 entry = sh_eth_tsu_find_entry(ndev, blank); 2712 return (entry < 0) ? -ENOMEM : entry; 2713 } 2714 2715 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2716 int entry) 2717 { 2718 struct sh_eth_private *mdp = netdev_priv(ndev); 2719 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2720 int ret; 2721 u8 blank[ETH_ALEN]; 2722 2723 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2724 ~(1 << (31 - entry)), TSU_TEN); 2725 2726 memset(blank, 0, sizeof(blank)); 2727 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2728 if (ret < 0) 2729 return ret; 2730 return 0; 2731 } 2732 2733 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2734 { 2735 struct sh_eth_private *mdp = netdev_priv(ndev); 2736 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2737 int i, ret; 2738 2739 if (!mdp->cd->tsu) 2740 return 0; 2741 2742 i = sh_eth_tsu_find_entry(ndev, addr); 2743 if (i < 0) { 2744 /* No entry found, create one */ 2745 i = sh_eth_tsu_find_empty(ndev); 2746 if (i < 0) 2747 return -ENOMEM; 2748 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2749 if (ret < 0) 2750 return ret; 2751 2752 /* Enable the entry */ 2753 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2754 (1 << (31 - i)), TSU_TEN); 2755 } 2756 2757 /* Entry found or created, enable POST */ 2758 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2759 2760 return 0; 2761 } 2762 2763 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2764 { 2765 struct sh_eth_private *mdp = netdev_priv(ndev); 2766 int i, ret; 2767 2768 if (!mdp->cd->tsu) 2769 return 0; 2770 2771 i = sh_eth_tsu_find_entry(ndev, addr); 2772 if (i) { 2773 /* Entry found */ 2774 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2775 goto done; 2776 2777 /* Disable the entry if both ports was disabled */ 2778 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2779 if (ret < 0) 2780 return ret; 2781 } 2782 done: 2783 return 0; 2784 } 2785 2786 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2787 { 2788 struct sh_eth_private *mdp = netdev_priv(ndev); 2789 int i, ret; 2790 2791 if (!mdp->cd->tsu) 2792 return 0; 2793 2794 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2795 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2796 continue; 2797 2798 /* Disable the entry if both ports was disabled */ 2799 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2800 if (ret < 0) 2801 return ret; 2802 } 2803 2804 return 0; 2805 } 2806 2807 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2808 { 2809 struct sh_eth_private *mdp = netdev_priv(ndev); 2810 u8 addr[ETH_ALEN]; 2811 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2812 int i; 2813 2814 if (!mdp->cd->tsu) 2815 return; 2816 2817 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2818 sh_eth_tsu_read_entry(reg_offset, addr); 2819 if (is_multicast_ether_addr(addr)) 2820 sh_eth_tsu_del_entry(ndev, addr); 2821 } 2822 } 2823 2824 /* Update promiscuous flag and multicast filter */ 2825 static void sh_eth_set_rx_mode(struct net_device *ndev) 2826 { 2827 struct sh_eth_private *mdp = netdev_priv(ndev); 2828 u32 ecmr_bits; 2829 int mcast_all = 0; 2830 unsigned long flags; 2831 2832 spin_lock_irqsave(&mdp->lock, flags); 2833 /* Initial condition is MCT = 1, PRM = 0. 2834 * Depending on ndev->flags, set PRM or clear MCT 2835 */ 2836 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2837 if (mdp->cd->tsu) 2838 ecmr_bits |= ECMR_MCT; 2839 2840 if (!(ndev->flags & IFF_MULTICAST)) { 2841 sh_eth_tsu_purge_mcast(ndev); 2842 mcast_all = 1; 2843 } 2844 if (ndev->flags & IFF_ALLMULTI) { 2845 sh_eth_tsu_purge_mcast(ndev); 2846 ecmr_bits &= ~ECMR_MCT; 2847 mcast_all = 1; 2848 } 2849 2850 if (ndev->flags & IFF_PROMISC) { 2851 sh_eth_tsu_purge_all(ndev); 2852 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2853 } else if (mdp->cd->tsu) { 2854 struct netdev_hw_addr *ha; 2855 netdev_for_each_mc_addr(ha, ndev) { 2856 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2857 continue; 2858 2859 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2860 if (!mcast_all) { 2861 sh_eth_tsu_purge_mcast(ndev); 2862 ecmr_bits &= ~ECMR_MCT; 2863 mcast_all = 1; 2864 } 2865 } 2866 } 2867 } 2868 2869 /* update the ethernet mode */ 2870 sh_eth_write(ndev, ecmr_bits, ECMR); 2871 2872 spin_unlock_irqrestore(&mdp->lock, flags); 2873 } 2874 2875 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2876 { 2877 if (!mdp->port) 2878 return TSU_VTAG0; 2879 else 2880 return TSU_VTAG1; 2881 } 2882 2883 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2884 __be16 proto, u16 vid) 2885 { 2886 struct sh_eth_private *mdp = netdev_priv(ndev); 2887 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2888 2889 if (unlikely(!mdp->cd->tsu)) 2890 return -EPERM; 2891 2892 /* No filtering if vid = 0 */ 2893 if (!vid) 2894 return 0; 2895 2896 mdp->vlan_num_ids++; 2897 2898 /* The controller has one VLAN tag HW filter. So, if the filter is 2899 * already enabled, the driver disables it and the filte 2900 */ 2901 if (mdp->vlan_num_ids > 1) { 2902 /* disable VLAN filter */ 2903 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2904 return 0; 2905 } 2906 2907 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2908 vtag_reg_index); 2909 2910 return 0; 2911 } 2912 2913 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2914 __be16 proto, u16 vid) 2915 { 2916 struct sh_eth_private *mdp = netdev_priv(ndev); 2917 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2918 2919 if (unlikely(!mdp->cd->tsu)) 2920 return -EPERM; 2921 2922 /* No filtering if vid = 0 */ 2923 if (!vid) 2924 return 0; 2925 2926 mdp->vlan_num_ids--; 2927 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2928 2929 return 0; 2930 } 2931 2932 /* SuperH's TSU register init function */ 2933 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2934 { 2935 if (sh_eth_is_rz_fast_ether(mdp)) { 2936 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2937 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 2938 TSU_FWSLC); /* Enable POST registers */ 2939 return; 2940 } 2941 2942 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2943 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2944 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2945 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2946 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2947 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2948 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2949 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2950 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2951 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2952 if (sh_eth_is_gether(mdp)) { 2953 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2954 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2955 } else { 2956 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2957 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2958 } 2959 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2960 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2961 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2962 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2963 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2964 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2965 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2966 } 2967 2968 /* MDIO bus release function */ 2969 static int sh_mdio_release(struct sh_eth_private *mdp) 2970 { 2971 /* unregister mdio bus */ 2972 mdiobus_unregister(mdp->mii_bus); 2973 2974 /* free bitbang info */ 2975 free_mdio_bitbang(mdp->mii_bus); 2976 2977 return 0; 2978 } 2979 2980 /* MDIO bus init function */ 2981 static int sh_mdio_init(struct sh_eth_private *mdp, 2982 struct sh_eth_plat_data *pd) 2983 { 2984 int ret; 2985 struct bb_info *bitbang; 2986 struct platform_device *pdev = mdp->pdev; 2987 struct device *dev = &mdp->pdev->dev; 2988 2989 /* create bit control struct for PHY */ 2990 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 2991 if (!bitbang) 2992 return -ENOMEM; 2993 2994 /* bitbang init */ 2995 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2996 bitbang->set_gate = pd->set_mdio_gate; 2997 bitbang->ctrl.ops = &bb_ops; 2998 2999 /* MII controller setting */ 3000 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 3001 if (!mdp->mii_bus) 3002 return -ENOMEM; 3003 3004 /* Hook up MII support for ethtool */ 3005 mdp->mii_bus->name = "sh_mii"; 3006 mdp->mii_bus->parent = dev; 3007 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 3008 pdev->name, pdev->id); 3009 3010 /* register MDIO bus */ 3011 if (dev->of_node) { 3012 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3013 } else { 3014 if (pd->phy_irq > 0) 3015 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3016 3017 ret = mdiobus_register(mdp->mii_bus); 3018 } 3019 3020 if (ret) 3021 goto out_free_bus; 3022 3023 return 0; 3024 3025 out_free_bus: 3026 free_mdio_bitbang(mdp->mii_bus); 3027 return ret; 3028 } 3029 3030 static const u16 *sh_eth_get_register_offset(int register_type) 3031 { 3032 const u16 *reg_offset = NULL; 3033 3034 switch (register_type) { 3035 case SH_ETH_REG_GIGABIT: 3036 reg_offset = sh_eth_offset_gigabit; 3037 break; 3038 case SH_ETH_REG_FAST_RZ: 3039 reg_offset = sh_eth_offset_fast_rz; 3040 break; 3041 case SH_ETH_REG_FAST_RCAR: 3042 reg_offset = sh_eth_offset_fast_rcar; 3043 break; 3044 case SH_ETH_REG_FAST_SH4: 3045 reg_offset = sh_eth_offset_fast_sh4; 3046 break; 3047 case SH_ETH_REG_FAST_SH3_SH2: 3048 reg_offset = sh_eth_offset_fast_sh3_sh2; 3049 break; 3050 } 3051 3052 return reg_offset; 3053 } 3054 3055 static const struct net_device_ops sh_eth_netdev_ops = { 3056 .ndo_open = sh_eth_open, 3057 .ndo_stop = sh_eth_close, 3058 .ndo_start_xmit = sh_eth_start_xmit, 3059 .ndo_get_stats = sh_eth_get_stats, 3060 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3061 .ndo_tx_timeout = sh_eth_tx_timeout, 3062 .ndo_do_ioctl = sh_eth_do_ioctl, 3063 .ndo_change_mtu = sh_eth_change_mtu, 3064 .ndo_validate_addr = eth_validate_addr, 3065 .ndo_set_mac_address = eth_mac_addr, 3066 }; 3067 3068 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3069 .ndo_open = sh_eth_open, 3070 .ndo_stop = sh_eth_close, 3071 .ndo_start_xmit = sh_eth_start_xmit, 3072 .ndo_get_stats = sh_eth_get_stats, 3073 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3074 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3075 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3076 .ndo_tx_timeout = sh_eth_tx_timeout, 3077 .ndo_do_ioctl = sh_eth_do_ioctl, 3078 .ndo_change_mtu = sh_eth_change_mtu, 3079 .ndo_validate_addr = eth_validate_addr, 3080 .ndo_set_mac_address = eth_mac_addr, 3081 }; 3082 3083 #ifdef CONFIG_OF 3084 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3085 { 3086 struct device_node *np = dev->of_node; 3087 struct sh_eth_plat_data *pdata; 3088 const char *mac_addr; 3089 3090 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3091 if (!pdata) 3092 return NULL; 3093 3094 pdata->phy_interface = of_get_phy_mode(np); 3095 3096 mac_addr = of_get_mac_address(np); 3097 if (mac_addr) 3098 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 3099 3100 pdata->no_ether_link = 3101 of_property_read_bool(np, "renesas,no-ether-link"); 3102 pdata->ether_link_active_low = 3103 of_property_read_bool(np, "renesas,ether-link-active-low"); 3104 3105 return pdata; 3106 } 3107 3108 static const struct of_device_id sh_eth_match_table[] = { 3109 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3110 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3111 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3112 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3113 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3114 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3115 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3116 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3117 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3118 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3119 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3120 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3121 { } 3122 }; 3123 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3124 #else 3125 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3126 { 3127 return NULL; 3128 } 3129 #endif 3130 3131 static int sh_eth_drv_probe(struct platform_device *pdev) 3132 { 3133 struct resource *res; 3134 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3135 const struct platform_device_id *id = platform_get_device_id(pdev); 3136 struct sh_eth_private *mdp; 3137 struct net_device *ndev; 3138 int ret; 3139 3140 /* get base addr */ 3141 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3142 3143 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3144 if (!ndev) 3145 return -ENOMEM; 3146 3147 pm_runtime_enable(&pdev->dev); 3148 pm_runtime_get_sync(&pdev->dev); 3149 3150 ret = platform_get_irq(pdev, 0); 3151 if (ret < 0) 3152 goto out_release; 3153 ndev->irq = ret; 3154 3155 SET_NETDEV_DEV(ndev, &pdev->dev); 3156 3157 mdp = netdev_priv(ndev); 3158 mdp->num_tx_ring = TX_RING_SIZE; 3159 mdp->num_rx_ring = RX_RING_SIZE; 3160 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3161 if (IS_ERR(mdp->addr)) { 3162 ret = PTR_ERR(mdp->addr); 3163 goto out_release; 3164 } 3165 3166 ndev->base_addr = res->start; 3167 3168 spin_lock_init(&mdp->lock); 3169 mdp->pdev = pdev; 3170 3171 if (pdev->dev.of_node) 3172 pd = sh_eth_parse_dt(&pdev->dev); 3173 if (!pd) { 3174 dev_err(&pdev->dev, "no platform data\n"); 3175 ret = -EINVAL; 3176 goto out_release; 3177 } 3178 3179 /* get PHY ID */ 3180 mdp->phy_id = pd->phy; 3181 mdp->phy_interface = pd->phy_interface; 3182 mdp->no_ether_link = pd->no_ether_link; 3183 mdp->ether_link_active_low = pd->ether_link_active_low; 3184 3185 /* set cpu data */ 3186 if (id) 3187 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3188 else 3189 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3190 3191 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3192 if (!mdp->reg_offset) { 3193 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3194 mdp->cd->register_type); 3195 ret = -EINVAL; 3196 goto out_release; 3197 } 3198 sh_eth_set_default_cpu_data(mdp->cd); 3199 3200 /* User's manual states max MTU should be 2048 but due to the 3201 * alignment calculations in sh_eth_ring_init() the practical 3202 * MTU is a bit less. Maybe this can be optimized some more. 3203 */ 3204 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3205 ndev->min_mtu = ETH_MIN_MTU; 3206 3207 /* set function */ 3208 if (mdp->cd->tsu) 3209 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3210 else 3211 ndev->netdev_ops = &sh_eth_netdev_ops; 3212 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3213 ndev->watchdog_timeo = TX_TIMEOUT; 3214 3215 /* debug message level */ 3216 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3217 3218 /* read and set MAC address */ 3219 read_mac_address(ndev, pd->mac_addr); 3220 if (!is_valid_ether_addr(ndev->dev_addr)) { 3221 dev_warn(&pdev->dev, 3222 "no valid MAC address supplied, using a random one.\n"); 3223 eth_hw_addr_random(ndev); 3224 } 3225 3226 if (mdp->cd->tsu) { 3227 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3228 struct resource *rtsu; 3229 3230 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3231 if (!rtsu) { 3232 dev_err(&pdev->dev, "no TSU resource\n"); 3233 ret = -ENODEV; 3234 goto out_release; 3235 } 3236 /* We can only request the TSU region for the first port 3237 * of the two sharing this TSU for the probe to succeed... 3238 */ 3239 if (port == 0 && 3240 !devm_request_mem_region(&pdev->dev, rtsu->start, 3241 resource_size(rtsu), 3242 dev_name(&pdev->dev))) { 3243 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3244 ret = -EBUSY; 3245 goto out_release; 3246 } 3247 /* ioremap the TSU registers */ 3248 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3249 resource_size(rtsu)); 3250 if (!mdp->tsu_addr) { 3251 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3252 ret = -ENOMEM; 3253 goto out_release; 3254 } 3255 mdp->port = port; 3256 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 3257 3258 /* Need to init only the first port of the two sharing a TSU */ 3259 if (port == 0) { 3260 if (mdp->cd->chip_reset) 3261 mdp->cd->chip_reset(ndev); 3262 3263 /* TSU init (Init only)*/ 3264 sh_eth_tsu_init(mdp); 3265 } 3266 } 3267 3268 if (mdp->cd->rmiimode) 3269 sh_eth_write(ndev, 0x1, RMIIMODE); 3270 3271 /* MDIO bus init */ 3272 ret = sh_mdio_init(mdp, pd); 3273 if (ret) { 3274 if (ret != -EPROBE_DEFER) 3275 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); 3276 goto out_release; 3277 } 3278 3279 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3280 3281 /* network device register */ 3282 ret = register_netdev(ndev); 3283 if (ret) 3284 goto out_napi_del; 3285 3286 if (mdp->cd->magic) 3287 device_set_wakeup_capable(&pdev->dev, 1); 3288 3289 /* print device information */ 3290 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3291 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3292 3293 pm_runtime_put(&pdev->dev); 3294 platform_set_drvdata(pdev, ndev); 3295 3296 return ret; 3297 3298 out_napi_del: 3299 netif_napi_del(&mdp->napi); 3300 sh_mdio_release(mdp); 3301 3302 out_release: 3303 /* net_dev free */ 3304 free_netdev(ndev); 3305 3306 pm_runtime_put(&pdev->dev); 3307 pm_runtime_disable(&pdev->dev); 3308 return ret; 3309 } 3310 3311 static int sh_eth_drv_remove(struct platform_device *pdev) 3312 { 3313 struct net_device *ndev = platform_get_drvdata(pdev); 3314 struct sh_eth_private *mdp = netdev_priv(ndev); 3315 3316 unregister_netdev(ndev); 3317 netif_napi_del(&mdp->napi); 3318 sh_mdio_release(mdp); 3319 pm_runtime_disable(&pdev->dev); 3320 free_netdev(ndev); 3321 3322 return 0; 3323 } 3324 3325 #ifdef CONFIG_PM 3326 #ifdef CONFIG_PM_SLEEP 3327 static int sh_eth_wol_setup(struct net_device *ndev) 3328 { 3329 struct sh_eth_private *mdp = netdev_priv(ndev); 3330 3331 /* Only allow ECI interrupts */ 3332 synchronize_irq(ndev->irq); 3333 napi_disable(&mdp->napi); 3334 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3335 3336 /* Enable MagicPacket */ 3337 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3338 3339 return enable_irq_wake(ndev->irq); 3340 } 3341 3342 static int sh_eth_wol_restore(struct net_device *ndev) 3343 { 3344 struct sh_eth_private *mdp = netdev_priv(ndev); 3345 int ret; 3346 3347 napi_enable(&mdp->napi); 3348 3349 /* Disable MagicPacket */ 3350 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3351 3352 /* The device needs to be reset to restore MagicPacket logic 3353 * for next wakeup. If we close and open the device it will 3354 * both be reset and all registers restored. This is what 3355 * happens during suspend and resume without WoL enabled. 3356 */ 3357 ret = sh_eth_close(ndev); 3358 if (ret < 0) 3359 return ret; 3360 ret = sh_eth_open(ndev); 3361 if (ret < 0) 3362 return ret; 3363 3364 return disable_irq_wake(ndev->irq); 3365 } 3366 3367 static int sh_eth_suspend(struct device *dev) 3368 { 3369 struct net_device *ndev = dev_get_drvdata(dev); 3370 struct sh_eth_private *mdp = netdev_priv(ndev); 3371 int ret = 0; 3372 3373 if (!netif_running(ndev)) 3374 return 0; 3375 3376 netif_device_detach(ndev); 3377 3378 if (mdp->wol_enabled) 3379 ret = sh_eth_wol_setup(ndev); 3380 else 3381 ret = sh_eth_close(ndev); 3382 3383 return ret; 3384 } 3385 3386 static int sh_eth_resume(struct device *dev) 3387 { 3388 struct net_device *ndev = dev_get_drvdata(dev); 3389 struct sh_eth_private *mdp = netdev_priv(ndev); 3390 int ret = 0; 3391 3392 if (!netif_running(ndev)) 3393 return 0; 3394 3395 if (mdp->wol_enabled) 3396 ret = sh_eth_wol_restore(ndev); 3397 else 3398 ret = sh_eth_open(ndev); 3399 3400 if (ret < 0) 3401 return ret; 3402 3403 netif_device_attach(ndev); 3404 3405 return ret; 3406 } 3407 #endif 3408 3409 static int sh_eth_runtime_nop(struct device *dev) 3410 { 3411 /* Runtime PM callback shared between ->runtime_suspend() 3412 * and ->runtime_resume(). Simply returns success. 3413 * 3414 * This driver re-initializes all registers after 3415 * pm_runtime_get_sync() anyway so there is no need 3416 * to save and restore registers here. 3417 */ 3418 return 0; 3419 } 3420 3421 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3422 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3423 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3424 }; 3425 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3426 #else 3427 #define SH_ETH_PM_OPS NULL 3428 #endif 3429 3430 static const struct platform_device_id sh_eth_id_table[] = { 3431 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3432 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3433 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3434 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3435 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3436 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3437 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3438 { } 3439 }; 3440 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3441 3442 static struct platform_driver sh_eth_driver = { 3443 .probe = sh_eth_drv_probe, 3444 .remove = sh_eth_drv_remove, 3445 .id_table = sh_eth_id_table, 3446 .driver = { 3447 .name = CARDNAME, 3448 .pm = SH_ETH_PM_OPS, 3449 .of_match_table = of_match_ptr(sh_eth_match_table), 3450 }, 3451 }; 3452 3453 module_platform_driver(sh_eth_driver); 3454 3455 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3456 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3457 MODULE_LICENSE("GPL v2"); 3458