1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2014 Renesas Electronics Corporation 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2014 Renesas Solutions Corp. 6 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 7 * Copyright (C) 2014 Codethink Limited 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 */ 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/etherdevice.h> 28 #include <linux/delay.h> 29 #include <linux/platform_device.h> 30 #include <linux/mdio-bitbang.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_net.h> 36 #include <linux/phy.h> 37 #include <linux/cache.h> 38 #include <linux/io.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/slab.h> 41 #include <linux/ethtool.h> 42 #include <linux/if_vlan.h> 43 #include <linux/sh_eth.h> 44 #include <linux/of_mdio.h> 45 46 #include "sh_eth.h" 47 48 #define SH_ETH_DEF_MSG_ENABLE \ 49 (NETIF_MSG_LINK | \ 50 NETIF_MSG_TIMER | \ 51 NETIF_MSG_RX_ERR| \ 52 NETIF_MSG_TX_ERR) 53 54 #define SH_ETH_OFFSET_INVALID ((u16)~0) 55 56 #define SH_ETH_OFFSET_DEFAULTS \ 57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 58 59 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 60 SH_ETH_OFFSET_DEFAULTS, 61 62 [EDSR] = 0x0000, 63 [EDMR] = 0x0400, 64 [EDTRR] = 0x0408, 65 [EDRRR] = 0x0410, 66 [EESR] = 0x0428, 67 [EESIPR] = 0x0430, 68 [TDLAR] = 0x0010, 69 [TDFAR] = 0x0014, 70 [TDFXR] = 0x0018, 71 [TDFFR] = 0x001c, 72 [RDLAR] = 0x0030, 73 [RDFAR] = 0x0034, 74 [RDFXR] = 0x0038, 75 [RDFFR] = 0x003c, 76 [TRSCER] = 0x0438, 77 [RMFCR] = 0x0440, 78 [TFTR] = 0x0448, 79 [FDR] = 0x0450, 80 [RMCR] = 0x0458, 81 [RPADIR] = 0x0460, 82 [FCFTR] = 0x0468, 83 [CSMR] = 0x04E4, 84 85 [ECMR] = 0x0500, 86 [ECSR] = 0x0510, 87 [ECSIPR] = 0x0518, 88 [PIR] = 0x0520, 89 [PSR] = 0x0528, 90 [PIPR] = 0x052c, 91 [RFLR] = 0x0508, 92 [APR] = 0x0554, 93 [MPR] = 0x0558, 94 [PFTCR] = 0x055c, 95 [PFRCR] = 0x0560, 96 [TPAUSER] = 0x0564, 97 [GECMR] = 0x05b0, 98 [BCULR] = 0x05b4, 99 [MAHR] = 0x05c0, 100 [MALR] = 0x05c8, 101 [TROCR] = 0x0700, 102 [CDCR] = 0x0708, 103 [LCCR] = 0x0710, 104 [CEFCR] = 0x0740, 105 [FRECR] = 0x0748, 106 [TSFRCR] = 0x0750, 107 [TLFRCR] = 0x0758, 108 [RFCR] = 0x0760, 109 [CERCR] = 0x0768, 110 [CEECR] = 0x0770, 111 [MAFCR] = 0x0778, 112 [RMII_MII] = 0x0790, 113 114 [ARSTR] = 0x0000, 115 [TSU_CTRST] = 0x0004, 116 [TSU_FWEN0] = 0x0010, 117 [TSU_FWEN1] = 0x0014, 118 [TSU_FCM] = 0x0018, 119 [TSU_BSYSL0] = 0x0020, 120 [TSU_BSYSL1] = 0x0024, 121 [TSU_PRISL0] = 0x0028, 122 [TSU_PRISL1] = 0x002c, 123 [TSU_FWSL0] = 0x0030, 124 [TSU_FWSL1] = 0x0034, 125 [TSU_FWSLC] = 0x0038, 126 [TSU_QTAGM0] = 0x0040, 127 [TSU_QTAGM1] = 0x0044, 128 [TSU_FWSR] = 0x0050, 129 [TSU_FWINMK] = 0x0054, 130 [TSU_ADQT0] = 0x0048, 131 [TSU_ADQT1] = 0x004c, 132 [TSU_VTAG0] = 0x0058, 133 [TSU_VTAG1] = 0x005c, 134 [TSU_ADSBSY] = 0x0060, 135 [TSU_TEN] = 0x0064, 136 [TSU_POST1] = 0x0070, 137 [TSU_POST2] = 0x0074, 138 [TSU_POST3] = 0x0078, 139 [TSU_POST4] = 0x007c, 140 [TSU_ADRH0] = 0x0100, 141 142 [TXNLCR0] = 0x0080, 143 [TXALCR0] = 0x0084, 144 [RXNLCR0] = 0x0088, 145 [RXALCR0] = 0x008c, 146 [FWNLCR0] = 0x0090, 147 [FWALCR0] = 0x0094, 148 [TXNLCR1] = 0x00a0, 149 [TXALCR1] = 0x00a4, 150 [RXNLCR1] = 0x00a8, 151 [RXALCR1] = 0x00ac, 152 [FWNLCR1] = 0x00b0, 153 [FWALCR1] = 0x00b4, 154 }; 155 156 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 157 SH_ETH_OFFSET_DEFAULTS, 158 159 [EDSR] = 0x0000, 160 [EDMR] = 0x0400, 161 [EDTRR] = 0x0408, 162 [EDRRR] = 0x0410, 163 [EESR] = 0x0428, 164 [EESIPR] = 0x0430, 165 [TDLAR] = 0x0010, 166 [TDFAR] = 0x0014, 167 [TDFXR] = 0x0018, 168 [TDFFR] = 0x001c, 169 [RDLAR] = 0x0030, 170 [RDFAR] = 0x0034, 171 [RDFXR] = 0x0038, 172 [RDFFR] = 0x003c, 173 [TRSCER] = 0x0438, 174 [RMFCR] = 0x0440, 175 [TFTR] = 0x0448, 176 [FDR] = 0x0450, 177 [RMCR] = 0x0458, 178 [RPADIR] = 0x0460, 179 [FCFTR] = 0x0468, 180 [CSMR] = 0x04E4, 181 182 [ECMR] = 0x0500, 183 [RFLR] = 0x0508, 184 [ECSR] = 0x0510, 185 [ECSIPR] = 0x0518, 186 [PIR] = 0x0520, 187 [APR] = 0x0554, 188 [MPR] = 0x0558, 189 [PFTCR] = 0x055c, 190 [PFRCR] = 0x0560, 191 [TPAUSER] = 0x0564, 192 [MAHR] = 0x05c0, 193 [MALR] = 0x05c8, 194 [CEFCR] = 0x0740, 195 [FRECR] = 0x0748, 196 [TSFRCR] = 0x0750, 197 [TLFRCR] = 0x0758, 198 [RFCR] = 0x0760, 199 [MAFCR] = 0x0778, 200 201 [ARSTR] = 0x0000, 202 [TSU_CTRST] = 0x0004, 203 [TSU_FWSLC] = 0x0038, 204 [TSU_VTAG0] = 0x0058, 205 [TSU_ADSBSY] = 0x0060, 206 [TSU_TEN] = 0x0064, 207 [TSU_POST1] = 0x0070, 208 [TSU_POST2] = 0x0074, 209 [TSU_POST3] = 0x0078, 210 [TSU_POST4] = 0x007c, 211 [TSU_ADRH0] = 0x0100, 212 213 [TXNLCR0] = 0x0080, 214 [TXALCR0] = 0x0084, 215 [RXNLCR0] = 0x0088, 216 [RXALCR0] = 0x008C, 217 }; 218 219 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 220 SH_ETH_OFFSET_DEFAULTS, 221 222 [ECMR] = 0x0300, 223 [RFLR] = 0x0308, 224 [ECSR] = 0x0310, 225 [ECSIPR] = 0x0318, 226 [PIR] = 0x0320, 227 [PSR] = 0x0328, 228 [RDMLR] = 0x0340, 229 [IPGR] = 0x0350, 230 [APR] = 0x0354, 231 [MPR] = 0x0358, 232 [RFCF] = 0x0360, 233 [TPAUSER] = 0x0364, 234 [TPAUSECR] = 0x0368, 235 [MAHR] = 0x03c0, 236 [MALR] = 0x03c8, 237 [TROCR] = 0x03d0, 238 [CDCR] = 0x03d4, 239 [LCCR] = 0x03d8, 240 [CNDCR] = 0x03dc, 241 [CEFCR] = 0x03e4, 242 [FRECR] = 0x03e8, 243 [TSFRCR] = 0x03ec, 244 [TLFRCR] = 0x03f0, 245 [RFCR] = 0x03f4, 246 [MAFCR] = 0x03f8, 247 248 [EDMR] = 0x0200, 249 [EDTRR] = 0x0208, 250 [EDRRR] = 0x0210, 251 [TDLAR] = 0x0218, 252 [RDLAR] = 0x0220, 253 [EESR] = 0x0228, 254 [EESIPR] = 0x0230, 255 [TRSCER] = 0x0238, 256 [RMFCR] = 0x0240, 257 [TFTR] = 0x0248, 258 [FDR] = 0x0250, 259 [RMCR] = 0x0258, 260 [TFUCR] = 0x0264, 261 [RFOCR] = 0x0268, 262 [RMIIMODE] = 0x026c, 263 [FCFTR] = 0x0270, 264 [TRIMD] = 0x027c, 265 }; 266 267 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 268 SH_ETH_OFFSET_DEFAULTS, 269 270 [ECMR] = 0x0100, 271 [RFLR] = 0x0108, 272 [ECSR] = 0x0110, 273 [ECSIPR] = 0x0118, 274 [PIR] = 0x0120, 275 [PSR] = 0x0128, 276 [RDMLR] = 0x0140, 277 [IPGR] = 0x0150, 278 [APR] = 0x0154, 279 [MPR] = 0x0158, 280 [TPAUSER] = 0x0164, 281 [RFCF] = 0x0160, 282 [TPAUSECR] = 0x0168, 283 [BCFRR] = 0x016c, 284 [MAHR] = 0x01c0, 285 [MALR] = 0x01c8, 286 [TROCR] = 0x01d0, 287 [CDCR] = 0x01d4, 288 [LCCR] = 0x01d8, 289 [CNDCR] = 0x01dc, 290 [CEFCR] = 0x01e4, 291 [FRECR] = 0x01e8, 292 [TSFRCR] = 0x01ec, 293 [TLFRCR] = 0x01f0, 294 [RFCR] = 0x01f4, 295 [MAFCR] = 0x01f8, 296 [RTRATE] = 0x01fc, 297 298 [EDMR] = 0x0000, 299 [EDTRR] = 0x0008, 300 [EDRRR] = 0x0010, 301 [TDLAR] = 0x0018, 302 [RDLAR] = 0x0020, 303 [EESR] = 0x0028, 304 [EESIPR] = 0x0030, 305 [TRSCER] = 0x0038, 306 [RMFCR] = 0x0040, 307 [TFTR] = 0x0048, 308 [FDR] = 0x0050, 309 [RMCR] = 0x0058, 310 [TFUCR] = 0x0064, 311 [RFOCR] = 0x0068, 312 [FCFTR] = 0x0070, 313 [RPADIR] = 0x0078, 314 [TRIMD] = 0x007c, 315 [RBWAR] = 0x00c8, 316 [RDFAR] = 0x00cc, 317 [TBRAR] = 0x00d4, 318 [TDFAR] = 0x00d8, 319 }; 320 321 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 322 SH_ETH_OFFSET_DEFAULTS, 323 324 [EDMR] = 0x0000, 325 [EDTRR] = 0x0004, 326 [EDRRR] = 0x0008, 327 [TDLAR] = 0x000c, 328 [RDLAR] = 0x0010, 329 [EESR] = 0x0014, 330 [EESIPR] = 0x0018, 331 [TRSCER] = 0x001c, 332 [RMFCR] = 0x0020, 333 [TFTR] = 0x0024, 334 [FDR] = 0x0028, 335 [RMCR] = 0x002c, 336 [EDOCR] = 0x0030, 337 [FCFTR] = 0x0034, 338 [RPADIR] = 0x0038, 339 [TRIMD] = 0x003c, 340 [RBWAR] = 0x0040, 341 [RDFAR] = 0x0044, 342 [TBRAR] = 0x004c, 343 [TDFAR] = 0x0050, 344 345 [ECMR] = 0x0160, 346 [ECSR] = 0x0164, 347 [ECSIPR] = 0x0168, 348 [PIR] = 0x016c, 349 [MAHR] = 0x0170, 350 [MALR] = 0x0174, 351 [RFLR] = 0x0178, 352 [PSR] = 0x017c, 353 [TROCR] = 0x0180, 354 [CDCR] = 0x0184, 355 [LCCR] = 0x0188, 356 [CNDCR] = 0x018c, 357 [CEFCR] = 0x0194, 358 [FRECR] = 0x0198, 359 [TSFRCR] = 0x019c, 360 [TLFRCR] = 0x01a0, 361 [RFCR] = 0x01a4, 362 [MAFCR] = 0x01a8, 363 [IPGR] = 0x01b4, 364 [APR] = 0x01b8, 365 [MPR] = 0x01bc, 366 [TPAUSER] = 0x01c4, 367 [BCFR] = 0x01cc, 368 369 [ARSTR] = 0x0000, 370 [TSU_CTRST] = 0x0004, 371 [TSU_FWEN0] = 0x0010, 372 [TSU_FWEN1] = 0x0014, 373 [TSU_FCM] = 0x0018, 374 [TSU_BSYSL0] = 0x0020, 375 [TSU_BSYSL1] = 0x0024, 376 [TSU_PRISL0] = 0x0028, 377 [TSU_PRISL1] = 0x002c, 378 [TSU_FWSL0] = 0x0030, 379 [TSU_FWSL1] = 0x0034, 380 [TSU_FWSLC] = 0x0038, 381 [TSU_QTAGM0] = 0x0040, 382 [TSU_QTAGM1] = 0x0044, 383 [TSU_ADQT0] = 0x0048, 384 [TSU_ADQT1] = 0x004c, 385 [TSU_FWSR] = 0x0050, 386 [TSU_FWINMK] = 0x0054, 387 [TSU_ADSBSY] = 0x0060, 388 [TSU_TEN] = 0x0064, 389 [TSU_POST1] = 0x0070, 390 [TSU_POST2] = 0x0074, 391 [TSU_POST3] = 0x0078, 392 [TSU_POST4] = 0x007c, 393 394 [TXNLCR0] = 0x0080, 395 [TXALCR0] = 0x0084, 396 [RXNLCR0] = 0x0088, 397 [RXALCR0] = 0x008c, 398 [FWNLCR0] = 0x0090, 399 [FWALCR0] = 0x0094, 400 [TXNLCR1] = 0x00a0, 401 [TXALCR1] = 0x00a4, 402 [RXNLCR1] = 0x00a8, 403 [RXALCR1] = 0x00ac, 404 [FWNLCR1] = 0x00b0, 405 [FWALCR1] = 0x00b4, 406 407 [TSU_ADRH0] = 0x0100, 408 }; 409 410 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 412 413 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 414 { 415 struct sh_eth_private *mdp = netdev_priv(ndev); 416 u16 offset = mdp->reg_offset[enum_index]; 417 418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 419 return; 420 421 iowrite32(data, mdp->addr + offset); 422 } 423 424 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 425 { 426 struct sh_eth_private *mdp = netdev_priv(ndev); 427 u16 offset = mdp->reg_offset[enum_index]; 428 429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 430 return ~0U; 431 432 return ioread32(mdp->addr + offset); 433 } 434 435 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 436 u32 set) 437 { 438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 439 enum_index); 440 } 441 442 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data, 443 int enum_index) 444 { 445 u16 offset = mdp->reg_offset[enum_index]; 446 447 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 448 return; 449 450 iowrite32(data, mdp->tsu_addr + offset); 451 } 452 453 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index) 454 { 455 u16 offset = mdp->reg_offset[enum_index]; 456 457 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 458 return ~0U; 459 460 return ioread32(mdp->tsu_addr + offset); 461 } 462 463 static void sh_eth_select_mii(struct net_device *ndev) 464 { 465 struct sh_eth_private *mdp = netdev_priv(ndev); 466 u32 value; 467 468 switch (mdp->phy_interface) { 469 case PHY_INTERFACE_MODE_GMII: 470 value = 0x2; 471 break; 472 case PHY_INTERFACE_MODE_MII: 473 value = 0x1; 474 break; 475 case PHY_INTERFACE_MODE_RMII: 476 value = 0x0; 477 break; 478 default: 479 netdev_warn(ndev, 480 "PHY interface mode was not setup. Set to MII.\n"); 481 value = 0x1; 482 break; 483 } 484 485 sh_eth_write(ndev, value, RMII_MII); 486 } 487 488 static void sh_eth_set_duplex(struct net_device *ndev) 489 { 490 struct sh_eth_private *mdp = netdev_priv(ndev); 491 492 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 493 } 494 495 static void sh_eth_chip_reset(struct net_device *ndev) 496 { 497 struct sh_eth_private *mdp = netdev_priv(ndev); 498 499 /* reset device */ 500 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 501 mdelay(1); 502 } 503 504 static int sh_eth_soft_reset(struct net_device *ndev) 505 { 506 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 507 mdelay(3); 508 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 509 510 return 0; 511 } 512 513 static int sh_eth_check_soft_reset(struct net_device *ndev) 514 { 515 int cnt; 516 517 for (cnt = 100; cnt > 0; cnt--) { 518 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 519 return 0; 520 mdelay(1); 521 } 522 523 netdev_err(ndev, "Device reset failed\n"); 524 return -ETIMEDOUT; 525 } 526 527 static int sh_eth_soft_reset_gether(struct net_device *ndev) 528 { 529 struct sh_eth_private *mdp = netdev_priv(ndev); 530 int ret; 531 532 sh_eth_write(ndev, EDSR_ENALL, EDSR); 533 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 534 535 ret = sh_eth_check_soft_reset(ndev); 536 if (ret) 537 return ret; 538 539 /* Table Init */ 540 sh_eth_write(ndev, 0, TDLAR); 541 sh_eth_write(ndev, 0, TDFAR); 542 sh_eth_write(ndev, 0, TDFXR); 543 sh_eth_write(ndev, 0, TDFFR); 544 sh_eth_write(ndev, 0, RDLAR); 545 sh_eth_write(ndev, 0, RDFAR); 546 sh_eth_write(ndev, 0, RDFXR); 547 sh_eth_write(ndev, 0, RDFFR); 548 549 /* Reset HW CRC register */ 550 if (mdp->cd->hw_checksum) 551 sh_eth_write(ndev, 0, CSMR); 552 553 /* Select MII mode */ 554 if (mdp->cd->select_mii) 555 sh_eth_select_mii(ndev); 556 557 return ret; 558 } 559 560 static void sh_eth_set_rate_gether(struct net_device *ndev) 561 { 562 struct sh_eth_private *mdp = netdev_priv(ndev); 563 564 switch (mdp->speed) { 565 case 10: /* 10BASE */ 566 sh_eth_write(ndev, GECMR_10, GECMR); 567 break; 568 case 100:/* 100BASE */ 569 sh_eth_write(ndev, GECMR_100, GECMR); 570 break; 571 case 1000: /* 1000BASE */ 572 sh_eth_write(ndev, GECMR_1000, GECMR); 573 break; 574 } 575 } 576 577 #ifdef CONFIG_OF 578 /* R7S72100 */ 579 static struct sh_eth_cpu_data r7s72100_data = { 580 .soft_reset = sh_eth_soft_reset_gether, 581 582 .chip_reset = sh_eth_chip_reset, 583 .set_duplex = sh_eth_set_duplex, 584 585 .register_type = SH_ETH_REG_FAST_RZ, 586 587 .edtrr_trns = EDTRR_TRNS_GETHER, 588 .ecsr_value = ECSR_ICD, 589 .ecsipr_value = ECSIPR_ICDIP, 590 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 591 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 592 EESIPR_ECIIP | 593 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 594 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 595 EESIPR_RMAFIP | EESIPR_RRFIP | 596 EESIPR_RTLFIP | EESIPR_RTSFIP | 597 EESIPR_PREIP | EESIPR_CERFIP, 598 599 .tx_check = EESR_TC1 | EESR_FTC, 600 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 601 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 602 EESR_TDE, 603 .fdr_value = 0x0000070f, 604 605 .no_psr = 1, 606 .apr = 1, 607 .mpr = 1, 608 .tpauser = 1, 609 .hw_swap = 1, 610 .rpadir = 1, 611 .rpadir_value = 2 << 16, 612 .no_trimd = 1, 613 .no_ade = 1, 614 .xdfar_rw = 1, 615 .hw_checksum = 1, 616 .tsu = 1, 617 .no_tx_cntrs = 1, 618 }; 619 620 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 621 { 622 sh_eth_chip_reset(ndev); 623 624 sh_eth_select_mii(ndev); 625 } 626 627 /* R8A7740 */ 628 static struct sh_eth_cpu_data r8a7740_data = { 629 .soft_reset = sh_eth_soft_reset_gether, 630 631 .chip_reset = sh_eth_chip_reset_r8a7740, 632 .set_duplex = sh_eth_set_duplex, 633 .set_rate = sh_eth_set_rate_gether, 634 635 .register_type = SH_ETH_REG_GIGABIT, 636 637 .edtrr_trns = EDTRR_TRNS_GETHER, 638 .ecsr_value = ECSR_ICD | ECSR_MPD, 639 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 640 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 641 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 642 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 643 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 644 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 645 EESIPR_CEEFIP | EESIPR_CELFIP | 646 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 647 EESIPR_PREIP | EESIPR_CERFIP, 648 649 .tx_check = EESR_TC1 | EESR_FTC, 650 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 651 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 652 EESR_TDE, 653 .fdr_value = 0x0000070f, 654 655 .apr = 1, 656 .mpr = 1, 657 .tpauser = 1, 658 .bculr = 1, 659 .hw_swap = 1, 660 .rpadir = 1, 661 .rpadir_value = 2 << 16, 662 .no_trimd = 1, 663 .no_ade = 1, 664 .xdfar_rw = 1, 665 .hw_checksum = 1, 666 .tsu = 1, 667 .select_mii = 1, 668 .magic = 1, 669 .cexcr = 1, 670 }; 671 672 /* There is CPU dependent code */ 673 static void sh_eth_set_rate_rcar(struct net_device *ndev) 674 { 675 struct sh_eth_private *mdp = netdev_priv(ndev); 676 677 switch (mdp->speed) { 678 case 10: /* 10BASE */ 679 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 680 break; 681 case 100:/* 100BASE */ 682 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 683 break; 684 } 685 } 686 687 /* R-Car Gen1 */ 688 static struct sh_eth_cpu_data rcar_gen1_data = { 689 .soft_reset = sh_eth_soft_reset, 690 691 .set_duplex = sh_eth_set_duplex, 692 .set_rate = sh_eth_set_rate_rcar, 693 694 .register_type = SH_ETH_REG_FAST_RCAR, 695 696 .edtrr_trns = EDTRR_TRNS_ETHER, 697 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 698 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 699 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 700 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 701 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 702 EESIPR_RMAFIP | EESIPR_RRFIP | 703 EESIPR_RTLFIP | EESIPR_RTSFIP | 704 EESIPR_PREIP | EESIPR_CERFIP, 705 706 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 707 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 708 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 709 .fdr_value = 0x00000f0f, 710 711 .apr = 1, 712 .mpr = 1, 713 .tpauser = 1, 714 .hw_swap = 1, 715 .no_xdfar = 1, 716 }; 717 718 /* R-Car Gen2 and RZ/G1 */ 719 static struct sh_eth_cpu_data rcar_gen2_data = { 720 .soft_reset = sh_eth_soft_reset, 721 722 .set_duplex = sh_eth_set_duplex, 723 .set_rate = sh_eth_set_rate_rcar, 724 725 .register_type = SH_ETH_REG_FAST_RCAR, 726 727 .edtrr_trns = EDTRR_TRNS_ETHER, 728 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 729 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 730 ECSIPR_MPDIP, 731 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 732 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 733 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 734 EESIPR_RMAFIP | EESIPR_RRFIP | 735 EESIPR_RTLFIP | EESIPR_RTSFIP | 736 EESIPR_PREIP | EESIPR_CERFIP, 737 738 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 739 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 740 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 741 .fdr_value = 0x00000f0f, 742 743 .trscer_err_mask = DESC_I_RINT8, 744 745 .apr = 1, 746 .mpr = 1, 747 .tpauser = 1, 748 .hw_swap = 1, 749 .no_xdfar = 1, 750 .rmiimode = 1, 751 .magic = 1, 752 }; 753 #endif /* CONFIG_OF */ 754 755 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 756 { 757 struct sh_eth_private *mdp = netdev_priv(ndev); 758 759 switch (mdp->speed) { 760 case 10: /* 10BASE */ 761 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 762 break; 763 case 100:/* 100BASE */ 764 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 765 break; 766 } 767 } 768 769 /* SH7724 */ 770 static struct sh_eth_cpu_data sh7724_data = { 771 .soft_reset = sh_eth_soft_reset, 772 773 .set_duplex = sh_eth_set_duplex, 774 .set_rate = sh_eth_set_rate_sh7724, 775 776 .register_type = SH_ETH_REG_FAST_SH4, 777 778 .edtrr_trns = EDTRR_TRNS_ETHER, 779 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 780 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 781 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 782 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 783 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 784 EESIPR_RMAFIP | EESIPR_RRFIP | 785 EESIPR_RTLFIP | EESIPR_RTSFIP | 786 EESIPR_PREIP | EESIPR_CERFIP, 787 788 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 789 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 790 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 791 792 .apr = 1, 793 .mpr = 1, 794 .tpauser = 1, 795 .hw_swap = 1, 796 .rpadir = 1, 797 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 798 }; 799 800 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 801 { 802 struct sh_eth_private *mdp = netdev_priv(ndev); 803 804 switch (mdp->speed) { 805 case 10: /* 10BASE */ 806 sh_eth_write(ndev, 0, RTRATE); 807 break; 808 case 100:/* 100BASE */ 809 sh_eth_write(ndev, 1, RTRATE); 810 break; 811 } 812 } 813 814 /* SH7757 */ 815 static struct sh_eth_cpu_data sh7757_data = { 816 .soft_reset = sh_eth_soft_reset, 817 818 .set_duplex = sh_eth_set_duplex, 819 .set_rate = sh_eth_set_rate_sh7757, 820 821 .register_type = SH_ETH_REG_FAST_SH4, 822 823 .edtrr_trns = EDTRR_TRNS_ETHER, 824 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 825 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 826 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 827 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 828 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 829 EESIPR_CEEFIP | EESIPR_CELFIP | 830 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 831 EESIPR_PREIP | EESIPR_CERFIP, 832 833 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 834 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 835 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 836 837 .irq_flags = IRQF_SHARED, 838 .apr = 1, 839 .mpr = 1, 840 .tpauser = 1, 841 .hw_swap = 1, 842 .no_ade = 1, 843 .rpadir = 1, 844 .rpadir_value = 2 << 16, 845 .rtrate = 1, 846 .dual_port = 1, 847 }; 848 849 #define SH_GIGA_ETH_BASE 0xfee00000UL 850 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 851 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 852 static void sh_eth_chip_reset_giga(struct net_device *ndev) 853 { 854 u32 mahr[2], malr[2]; 855 int i; 856 857 /* save MAHR and MALR */ 858 for (i = 0; i < 2; i++) { 859 malr[i] = ioread32((void *)GIGA_MALR(i)); 860 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 861 } 862 863 sh_eth_chip_reset(ndev); 864 865 /* restore MAHR and MALR */ 866 for (i = 0; i < 2; i++) { 867 iowrite32(malr[i], (void *)GIGA_MALR(i)); 868 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 869 } 870 } 871 872 static void sh_eth_set_rate_giga(struct net_device *ndev) 873 { 874 struct sh_eth_private *mdp = netdev_priv(ndev); 875 876 switch (mdp->speed) { 877 case 10: /* 10BASE */ 878 sh_eth_write(ndev, 0x00000000, GECMR); 879 break; 880 case 100:/* 100BASE */ 881 sh_eth_write(ndev, 0x00000010, GECMR); 882 break; 883 case 1000: /* 1000BASE */ 884 sh_eth_write(ndev, 0x00000020, GECMR); 885 break; 886 } 887 } 888 889 /* SH7757(GETHERC) */ 890 static struct sh_eth_cpu_data sh7757_data_giga = { 891 .soft_reset = sh_eth_soft_reset_gether, 892 893 .chip_reset = sh_eth_chip_reset_giga, 894 .set_duplex = sh_eth_set_duplex, 895 .set_rate = sh_eth_set_rate_giga, 896 897 .register_type = SH_ETH_REG_GIGABIT, 898 899 .edtrr_trns = EDTRR_TRNS_GETHER, 900 .ecsr_value = ECSR_ICD | ECSR_MPD, 901 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 902 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 903 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 904 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 905 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 906 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 907 EESIPR_CEEFIP | EESIPR_CELFIP | 908 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 909 EESIPR_PREIP | EESIPR_CERFIP, 910 911 .tx_check = EESR_TC1 | EESR_FTC, 912 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 913 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 914 EESR_TDE, 915 .fdr_value = 0x0000072f, 916 917 .irq_flags = IRQF_SHARED, 918 .apr = 1, 919 .mpr = 1, 920 .tpauser = 1, 921 .bculr = 1, 922 .hw_swap = 1, 923 .rpadir = 1, 924 .rpadir_value = 2 << 16, 925 .no_trimd = 1, 926 .no_ade = 1, 927 .xdfar_rw = 1, 928 .tsu = 1, 929 .cexcr = 1, 930 .dual_port = 1, 931 }; 932 933 /* SH7734 */ 934 static struct sh_eth_cpu_data sh7734_data = { 935 .soft_reset = sh_eth_soft_reset_gether, 936 937 .chip_reset = sh_eth_chip_reset, 938 .set_duplex = sh_eth_set_duplex, 939 .set_rate = sh_eth_set_rate_gether, 940 941 .register_type = SH_ETH_REG_GIGABIT, 942 943 .edtrr_trns = EDTRR_TRNS_GETHER, 944 .ecsr_value = ECSR_ICD | ECSR_MPD, 945 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 946 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 947 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 948 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 949 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 950 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 951 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 952 EESIPR_PREIP | EESIPR_CERFIP, 953 954 .tx_check = EESR_TC1 | EESR_FTC, 955 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 956 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 957 EESR_TDE, 958 959 .apr = 1, 960 .mpr = 1, 961 .tpauser = 1, 962 .bculr = 1, 963 .hw_swap = 1, 964 .no_trimd = 1, 965 .no_ade = 1, 966 .xdfar_rw = 1, 967 .tsu = 1, 968 .hw_checksum = 1, 969 .select_mii = 1, 970 .magic = 1, 971 .cexcr = 1, 972 }; 973 974 /* SH7763 */ 975 static struct sh_eth_cpu_data sh7763_data = { 976 .soft_reset = sh_eth_soft_reset_gether, 977 978 .chip_reset = sh_eth_chip_reset, 979 .set_duplex = sh_eth_set_duplex, 980 .set_rate = sh_eth_set_rate_gether, 981 982 .register_type = SH_ETH_REG_GIGABIT, 983 984 .edtrr_trns = EDTRR_TRNS_GETHER, 985 .ecsr_value = ECSR_ICD | ECSR_MPD, 986 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 987 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 988 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 989 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 990 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 991 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 992 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 993 EESIPR_PREIP | EESIPR_CERFIP, 994 995 .tx_check = EESR_TC1 | EESR_FTC, 996 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 997 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 998 999 .apr = 1, 1000 .mpr = 1, 1001 .tpauser = 1, 1002 .bculr = 1, 1003 .hw_swap = 1, 1004 .no_trimd = 1, 1005 .no_ade = 1, 1006 .xdfar_rw = 1, 1007 .tsu = 1, 1008 .irq_flags = IRQF_SHARED, 1009 .magic = 1, 1010 .cexcr = 1, 1011 .dual_port = 1, 1012 }; 1013 1014 static struct sh_eth_cpu_data sh7619_data = { 1015 .soft_reset = sh_eth_soft_reset, 1016 1017 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1018 1019 .edtrr_trns = EDTRR_TRNS_ETHER, 1020 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1021 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1022 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1023 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1024 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1025 EESIPR_CEEFIP | EESIPR_CELFIP | 1026 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1027 EESIPR_PREIP | EESIPR_CERFIP, 1028 1029 .apr = 1, 1030 .mpr = 1, 1031 .tpauser = 1, 1032 .hw_swap = 1, 1033 }; 1034 1035 static struct sh_eth_cpu_data sh771x_data = { 1036 .soft_reset = sh_eth_soft_reset, 1037 1038 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1039 1040 .edtrr_trns = EDTRR_TRNS_ETHER, 1041 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1042 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1043 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1044 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1045 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1046 EESIPR_CEEFIP | EESIPR_CELFIP | 1047 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1048 EESIPR_PREIP | EESIPR_CERFIP, 1049 .tsu = 1, 1050 .dual_port = 1, 1051 }; 1052 1053 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 1054 { 1055 if (!cd->ecsr_value) 1056 cd->ecsr_value = DEFAULT_ECSR_INIT; 1057 1058 if (!cd->ecsipr_value) 1059 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 1060 1061 if (!cd->fcftr_value) 1062 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 1063 DEFAULT_FIFO_F_D_RFD; 1064 1065 if (!cd->fdr_value) 1066 cd->fdr_value = DEFAULT_FDR_INIT; 1067 1068 if (!cd->tx_check) 1069 cd->tx_check = DEFAULT_TX_CHECK; 1070 1071 if (!cd->eesr_err_check) 1072 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 1073 1074 if (!cd->trscer_err_mask) 1075 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 1076 } 1077 1078 static void sh_eth_set_receive_align(struct sk_buff *skb) 1079 { 1080 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1081 1082 if (reserve) 1083 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1084 } 1085 1086 /* Program the hardware MAC address from dev->dev_addr. */ 1087 static void update_mac_address(struct net_device *ndev) 1088 { 1089 sh_eth_write(ndev, 1090 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1091 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1092 sh_eth_write(ndev, 1093 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1094 } 1095 1096 /* Get MAC address from SuperH MAC address register 1097 * 1098 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1099 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1100 * When you want use this device, you must set MAC address in bootloader. 1101 * 1102 */ 1103 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1104 { 1105 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1106 memcpy(ndev->dev_addr, mac, ETH_ALEN); 1107 } else { 1108 u32 mahr = sh_eth_read(ndev, MAHR); 1109 u32 malr = sh_eth_read(ndev, MALR); 1110 1111 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 1112 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 1113 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 1114 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 1115 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1116 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1117 } 1118 } 1119 1120 struct bb_info { 1121 void (*set_gate)(void *addr); 1122 struct mdiobb_ctrl ctrl; 1123 void *addr; 1124 }; 1125 1126 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1127 { 1128 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1129 u32 pir; 1130 1131 if (bitbang->set_gate) 1132 bitbang->set_gate(bitbang->addr); 1133 1134 pir = ioread32(bitbang->addr); 1135 if (set) 1136 pir |= mask; 1137 else 1138 pir &= ~mask; 1139 iowrite32(pir, bitbang->addr); 1140 } 1141 1142 /* Data I/O pin control */ 1143 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1144 { 1145 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1146 } 1147 1148 /* Set bit data*/ 1149 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1150 { 1151 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1152 } 1153 1154 /* Get bit data*/ 1155 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1156 { 1157 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1158 1159 if (bitbang->set_gate) 1160 bitbang->set_gate(bitbang->addr); 1161 1162 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1163 } 1164 1165 /* MDC pin control */ 1166 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1167 { 1168 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1169 } 1170 1171 /* mdio bus control struct */ 1172 static struct mdiobb_ops bb_ops = { 1173 .owner = THIS_MODULE, 1174 .set_mdc = sh_mdc_ctrl, 1175 .set_mdio_dir = sh_mmd_ctrl, 1176 .set_mdio_data = sh_set_mdio, 1177 .get_mdio_data = sh_get_mdio, 1178 }; 1179 1180 /* free Tx skb function */ 1181 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1182 { 1183 struct sh_eth_private *mdp = netdev_priv(ndev); 1184 struct sh_eth_txdesc *txdesc; 1185 int free_num = 0; 1186 int entry; 1187 bool sent; 1188 1189 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1190 entry = mdp->dirty_tx % mdp->num_tx_ring; 1191 txdesc = &mdp->tx_ring[entry]; 1192 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1193 if (sent_only && !sent) 1194 break; 1195 /* TACT bit must be checked before all the following reads */ 1196 dma_rmb(); 1197 netif_info(mdp, tx_done, ndev, 1198 "tx entry %d status 0x%08x\n", 1199 entry, le32_to_cpu(txdesc->status)); 1200 /* Free the original skb. */ 1201 if (mdp->tx_skbuff[entry]) { 1202 dma_unmap_single(&mdp->pdev->dev, 1203 le32_to_cpu(txdesc->addr), 1204 le32_to_cpu(txdesc->len) >> 16, 1205 DMA_TO_DEVICE); 1206 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1207 mdp->tx_skbuff[entry] = NULL; 1208 free_num++; 1209 } 1210 txdesc->status = cpu_to_le32(TD_TFP); 1211 if (entry >= mdp->num_tx_ring - 1) 1212 txdesc->status |= cpu_to_le32(TD_TDLE); 1213 1214 if (sent) { 1215 ndev->stats.tx_packets++; 1216 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1217 } 1218 } 1219 return free_num; 1220 } 1221 1222 /* free skb and descriptor buffer */ 1223 static void sh_eth_ring_free(struct net_device *ndev) 1224 { 1225 struct sh_eth_private *mdp = netdev_priv(ndev); 1226 int ringsize, i; 1227 1228 if (mdp->rx_ring) { 1229 for (i = 0; i < mdp->num_rx_ring; i++) { 1230 if (mdp->rx_skbuff[i]) { 1231 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1232 1233 dma_unmap_single(&mdp->pdev->dev, 1234 le32_to_cpu(rxdesc->addr), 1235 ALIGN(mdp->rx_buf_sz, 32), 1236 DMA_FROM_DEVICE); 1237 } 1238 } 1239 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1240 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1241 mdp->rx_desc_dma); 1242 mdp->rx_ring = NULL; 1243 } 1244 1245 /* Free Rx skb ringbuffer */ 1246 if (mdp->rx_skbuff) { 1247 for (i = 0; i < mdp->num_rx_ring; i++) 1248 dev_kfree_skb(mdp->rx_skbuff[i]); 1249 } 1250 kfree(mdp->rx_skbuff); 1251 mdp->rx_skbuff = NULL; 1252 1253 if (mdp->tx_ring) { 1254 sh_eth_tx_free(ndev, false); 1255 1256 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1257 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1258 mdp->tx_desc_dma); 1259 mdp->tx_ring = NULL; 1260 } 1261 1262 /* Free Tx skb ringbuffer */ 1263 kfree(mdp->tx_skbuff); 1264 mdp->tx_skbuff = NULL; 1265 } 1266 1267 /* format skb and descriptor buffer */ 1268 static void sh_eth_ring_format(struct net_device *ndev) 1269 { 1270 struct sh_eth_private *mdp = netdev_priv(ndev); 1271 int i; 1272 struct sk_buff *skb; 1273 struct sh_eth_rxdesc *rxdesc = NULL; 1274 struct sh_eth_txdesc *txdesc = NULL; 1275 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1276 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1277 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1278 dma_addr_t dma_addr; 1279 u32 buf_len; 1280 1281 mdp->cur_rx = 0; 1282 mdp->cur_tx = 0; 1283 mdp->dirty_rx = 0; 1284 mdp->dirty_tx = 0; 1285 1286 memset(mdp->rx_ring, 0, rx_ringsize); 1287 1288 /* build Rx ring buffer */ 1289 for (i = 0; i < mdp->num_rx_ring; i++) { 1290 /* skb */ 1291 mdp->rx_skbuff[i] = NULL; 1292 skb = netdev_alloc_skb(ndev, skbuff_size); 1293 if (skb == NULL) 1294 break; 1295 sh_eth_set_receive_align(skb); 1296 1297 /* The size of the buffer is a multiple of 32 bytes. */ 1298 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1299 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1300 DMA_FROM_DEVICE); 1301 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1302 kfree_skb(skb); 1303 break; 1304 } 1305 mdp->rx_skbuff[i] = skb; 1306 1307 /* RX descriptor */ 1308 rxdesc = &mdp->rx_ring[i]; 1309 rxdesc->len = cpu_to_le32(buf_len << 16); 1310 rxdesc->addr = cpu_to_le32(dma_addr); 1311 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1312 1313 /* Rx descriptor address set */ 1314 if (i == 0) { 1315 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1316 if (mdp->cd->xdfar_rw) 1317 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1318 } 1319 } 1320 1321 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1322 1323 /* Mark the last entry as wrapping the ring. */ 1324 if (rxdesc) 1325 rxdesc->status |= cpu_to_le32(RD_RDLE); 1326 1327 memset(mdp->tx_ring, 0, tx_ringsize); 1328 1329 /* build Tx ring buffer */ 1330 for (i = 0; i < mdp->num_tx_ring; i++) { 1331 mdp->tx_skbuff[i] = NULL; 1332 txdesc = &mdp->tx_ring[i]; 1333 txdesc->status = cpu_to_le32(TD_TFP); 1334 txdesc->len = cpu_to_le32(0); 1335 if (i == 0) { 1336 /* Tx descriptor address set */ 1337 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1338 if (mdp->cd->xdfar_rw) 1339 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1340 } 1341 } 1342 1343 txdesc->status |= cpu_to_le32(TD_TDLE); 1344 } 1345 1346 /* Get skb and descriptor buffer */ 1347 static int sh_eth_ring_init(struct net_device *ndev) 1348 { 1349 struct sh_eth_private *mdp = netdev_priv(ndev); 1350 int rx_ringsize, tx_ringsize; 1351 1352 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1353 * card needs room to do 8 byte alignment, +2 so we can reserve 1354 * the first 2 bytes, and +16 gets room for the status word from the 1355 * card. 1356 */ 1357 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1358 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1359 if (mdp->cd->rpadir) 1360 mdp->rx_buf_sz += NET_IP_ALIGN; 1361 1362 /* Allocate RX and TX skb rings */ 1363 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1364 GFP_KERNEL); 1365 if (!mdp->rx_skbuff) 1366 return -ENOMEM; 1367 1368 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1369 GFP_KERNEL); 1370 if (!mdp->tx_skbuff) 1371 goto ring_free; 1372 1373 /* Allocate all Rx descriptors. */ 1374 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1375 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1376 &mdp->rx_desc_dma, GFP_KERNEL); 1377 if (!mdp->rx_ring) 1378 goto ring_free; 1379 1380 mdp->dirty_rx = 0; 1381 1382 /* Allocate all Tx descriptors. */ 1383 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1384 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1385 &mdp->tx_desc_dma, GFP_KERNEL); 1386 if (!mdp->tx_ring) 1387 goto ring_free; 1388 return 0; 1389 1390 ring_free: 1391 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1392 sh_eth_ring_free(ndev); 1393 1394 return -ENOMEM; 1395 } 1396 1397 static int sh_eth_dev_init(struct net_device *ndev) 1398 { 1399 struct sh_eth_private *mdp = netdev_priv(ndev); 1400 int ret; 1401 1402 /* Soft Reset */ 1403 ret = mdp->cd->soft_reset(ndev); 1404 if (ret) 1405 return ret; 1406 1407 if (mdp->cd->rmiimode) 1408 sh_eth_write(ndev, 0x1, RMIIMODE); 1409 1410 /* Descriptor format */ 1411 sh_eth_ring_format(ndev); 1412 if (mdp->cd->rpadir) 1413 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1414 1415 /* all sh_eth int mask */ 1416 sh_eth_write(ndev, 0, EESIPR); 1417 1418 #if defined(__LITTLE_ENDIAN) 1419 if (mdp->cd->hw_swap) 1420 sh_eth_write(ndev, EDMR_EL, EDMR); 1421 else 1422 #endif 1423 sh_eth_write(ndev, 0, EDMR); 1424 1425 /* FIFO size set */ 1426 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1427 sh_eth_write(ndev, 0, TFTR); 1428 1429 /* Frame recv control (enable multiple-packets per rx irq) */ 1430 sh_eth_write(ndev, RMCR_RNC, RMCR); 1431 1432 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1433 1434 if (mdp->cd->bculr) 1435 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1436 1437 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1438 1439 if (!mdp->cd->no_trimd) 1440 sh_eth_write(ndev, 0, TRIMD); 1441 1442 /* Recv frame limit set register */ 1443 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1444 RFLR); 1445 1446 sh_eth_modify(ndev, EESR, 0, 0); 1447 mdp->irq_enabled = true; 1448 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1449 1450 /* PAUSE Prohibition */ 1451 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1452 ECMR_TE | ECMR_RE, ECMR); 1453 1454 if (mdp->cd->set_rate) 1455 mdp->cd->set_rate(ndev); 1456 1457 /* E-MAC Status Register clear */ 1458 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1459 1460 /* E-MAC Interrupt Enable register */ 1461 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1462 1463 /* Set MAC address */ 1464 update_mac_address(ndev); 1465 1466 /* mask reset */ 1467 if (mdp->cd->apr) 1468 sh_eth_write(ndev, APR_AP, APR); 1469 if (mdp->cd->mpr) 1470 sh_eth_write(ndev, MPR_MP, MPR); 1471 if (mdp->cd->tpauser) 1472 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1473 1474 /* Setting the Rx mode will start the Rx process. */ 1475 sh_eth_write(ndev, EDRRR_R, EDRRR); 1476 1477 return ret; 1478 } 1479 1480 static void sh_eth_dev_exit(struct net_device *ndev) 1481 { 1482 struct sh_eth_private *mdp = netdev_priv(ndev); 1483 int i; 1484 1485 /* Deactivate all TX descriptors, so DMA should stop at next 1486 * packet boundary if it's currently running 1487 */ 1488 for (i = 0; i < mdp->num_tx_ring; i++) 1489 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1490 1491 /* Disable TX FIFO egress to MAC */ 1492 sh_eth_rcv_snd_disable(ndev); 1493 1494 /* Stop RX DMA at next packet boundary */ 1495 sh_eth_write(ndev, 0, EDRRR); 1496 1497 /* Aside from TX DMA, we can't tell when the hardware is 1498 * really stopped, so we need to reset to make sure. 1499 * Before doing that, wait for long enough to *probably* 1500 * finish transmitting the last packet and poll stats. 1501 */ 1502 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1503 sh_eth_get_stats(ndev); 1504 mdp->cd->soft_reset(ndev); 1505 1506 /* Set MAC address again */ 1507 update_mac_address(ndev); 1508 } 1509 1510 /* Packet receive function */ 1511 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1512 { 1513 struct sh_eth_private *mdp = netdev_priv(ndev); 1514 struct sh_eth_rxdesc *rxdesc; 1515 1516 int entry = mdp->cur_rx % mdp->num_rx_ring; 1517 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1518 int limit; 1519 struct sk_buff *skb; 1520 u32 desc_status; 1521 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1522 dma_addr_t dma_addr; 1523 u16 pkt_len; 1524 u32 buf_len; 1525 1526 boguscnt = min(boguscnt, *quota); 1527 limit = boguscnt; 1528 rxdesc = &mdp->rx_ring[entry]; 1529 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1530 /* RACT bit must be checked before all the following reads */ 1531 dma_rmb(); 1532 desc_status = le32_to_cpu(rxdesc->status); 1533 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1534 1535 if (--boguscnt < 0) 1536 break; 1537 1538 netif_info(mdp, rx_status, ndev, 1539 "rx entry %d status 0x%08x len %d\n", 1540 entry, desc_status, pkt_len); 1541 1542 if (!(desc_status & RDFEND)) 1543 ndev->stats.rx_length_errors++; 1544 1545 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1546 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1547 * bit 0. However, in case of the R8A7740 and R7S72100 1548 * the RFS bits are from bit 25 to bit 16. So, the 1549 * driver needs right shifting by 16. 1550 */ 1551 if (mdp->cd->hw_checksum) 1552 desc_status >>= 16; 1553 1554 skb = mdp->rx_skbuff[entry]; 1555 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1556 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1557 ndev->stats.rx_errors++; 1558 if (desc_status & RD_RFS1) 1559 ndev->stats.rx_crc_errors++; 1560 if (desc_status & RD_RFS2) 1561 ndev->stats.rx_frame_errors++; 1562 if (desc_status & RD_RFS3) 1563 ndev->stats.rx_length_errors++; 1564 if (desc_status & RD_RFS4) 1565 ndev->stats.rx_length_errors++; 1566 if (desc_status & RD_RFS6) 1567 ndev->stats.rx_missed_errors++; 1568 if (desc_status & RD_RFS10) 1569 ndev->stats.rx_over_errors++; 1570 } else if (skb) { 1571 dma_addr = le32_to_cpu(rxdesc->addr); 1572 if (!mdp->cd->hw_swap) 1573 sh_eth_soft_swap( 1574 phys_to_virt(ALIGN(dma_addr, 4)), 1575 pkt_len + 2); 1576 mdp->rx_skbuff[entry] = NULL; 1577 if (mdp->cd->rpadir) 1578 skb_reserve(skb, NET_IP_ALIGN); 1579 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1580 ALIGN(mdp->rx_buf_sz, 32), 1581 DMA_FROM_DEVICE); 1582 skb_put(skb, pkt_len); 1583 skb->protocol = eth_type_trans(skb, ndev); 1584 netif_receive_skb(skb); 1585 ndev->stats.rx_packets++; 1586 ndev->stats.rx_bytes += pkt_len; 1587 if (desc_status & RD_RFS8) 1588 ndev->stats.multicast++; 1589 } 1590 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1591 rxdesc = &mdp->rx_ring[entry]; 1592 } 1593 1594 /* Refill the Rx ring buffers. */ 1595 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1596 entry = mdp->dirty_rx % mdp->num_rx_ring; 1597 rxdesc = &mdp->rx_ring[entry]; 1598 /* The size of the buffer is 32 byte boundary. */ 1599 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1600 rxdesc->len = cpu_to_le32(buf_len << 16); 1601 1602 if (mdp->rx_skbuff[entry] == NULL) { 1603 skb = netdev_alloc_skb(ndev, skbuff_size); 1604 if (skb == NULL) 1605 break; /* Better luck next round. */ 1606 sh_eth_set_receive_align(skb); 1607 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1608 buf_len, DMA_FROM_DEVICE); 1609 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1610 kfree_skb(skb); 1611 break; 1612 } 1613 mdp->rx_skbuff[entry] = skb; 1614 1615 skb_checksum_none_assert(skb); 1616 rxdesc->addr = cpu_to_le32(dma_addr); 1617 } 1618 dma_wmb(); /* RACT bit must be set after all the above writes */ 1619 if (entry >= mdp->num_rx_ring - 1) 1620 rxdesc->status |= 1621 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1622 else 1623 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1624 } 1625 1626 /* Restart Rx engine if stopped. */ 1627 /* If we don't need to check status, don't. -KDU */ 1628 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1629 /* fix the values for the next receiving if RDE is set */ 1630 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) { 1631 u32 count = (sh_eth_read(ndev, RDFAR) - 1632 sh_eth_read(ndev, RDLAR)) >> 4; 1633 1634 mdp->cur_rx = count; 1635 mdp->dirty_rx = count; 1636 } 1637 sh_eth_write(ndev, EDRRR_R, EDRRR); 1638 } 1639 1640 *quota -= limit - boguscnt - 1; 1641 1642 return *quota <= 0; 1643 } 1644 1645 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1646 { 1647 /* disable tx and rx */ 1648 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1649 } 1650 1651 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1652 { 1653 /* enable tx and rx */ 1654 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1655 } 1656 1657 /* E-MAC interrupt handler */ 1658 static void sh_eth_emac_interrupt(struct net_device *ndev) 1659 { 1660 struct sh_eth_private *mdp = netdev_priv(ndev); 1661 u32 felic_stat; 1662 u32 link_stat; 1663 1664 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1665 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1666 if (felic_stat & ECSR_ICD) 1667 ndev->stats.tx_carrier_errors++; 1668 if (felic_stat & ECSR_MPD) 1669 pm_wakeup_event(&mdp->pdev->dev, 0); 1670 if (felic_stat & ECSR_LCHNG) { 1671 /* Link Changed */ 1672 if (mdp->cd->no_psr || mdp->no_ether_link) 1673 return; 1674 link_stat = sh_eth_read(ndev, PSR); 1675 if (mdp->ether_link_active_low) 1676 link_stat = ~link_stat; 1677 if (!(link_stat & PHY_ST_LINK)) { 1678 sh_eth_rcv_snd_disable(ndev); 1679 } else { 1680 /* Link Up */ 1681 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1682 /* clear int */ 1683 sh_eth_modify(ndev, ECSR, 0, 0); 1684 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1685 /* enable tx and rx */ 1686 sh_eth_rcv_snd_enable(ndev); 1687 } 1688 } 1689 } 1690 1691 /* error control function */ 1692 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1693 { 1694 struct sh_eth_private *mdp = netdev_priv(ndev); 1695 u32 mask; 1696 1697 if (intr_status & EESR_TWB) { 1698 /* Unused write back interrupt */ 1699 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1700 ndev->stats.tx_aborted_errors++; 1701 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1702 } 1703 } 1704 1705 if (intr_status & EESR_RABT) { 1706 /* Receive Abort int */ 1707 if (intr_status & EESR_RFRMER) { 1708 /* Receive Frame Overflow int */ 1709 ndev->stats.rx_frame_errors++; 1710 } 1711 } 1712 1713 if (intr_status & EESR_TDE) { 1714 /* Transmit Descriptor Empty int */ 1715 ndev->stats.tx_fifo_errors++; 1716 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1717 } 1718 1719 if (intr_status & EESR_TFE) { 1720 /* FIFO under flow */ 1721 ndev->stats.tx_fifo_errors++; 1722 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1723 } 1724 1725 if (intr_status & EESR_RDE) { 1726 /* Receive Descriptor Empty int */ 1727 ndev->stats.rx_over_errors++; 1728 } 1729 1730 if (intr_status & EESR_RFE) { 1731 /* Receive FIFO Overflow int */ 1732 ndev->stats.rx_fifo_errors++; 1733 } 1734 1735 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1736 /* Address Error */ 1737 ndev->stats.tx_fifo_errors++; 1738 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1739 } 1740 1741 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1742 if (mdp->cd->no_ade) 1743 mask &= ~EESR_ADE; 1744 if (intr_status & mask) { 1745 /* Tx error */ 1746 u32 edtrr = sh_eth_read(ndev, EDTRR); 1747 1748 /* dmesg */ 1749 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1750 intr_status, mdp->cur_tx, mdp->dirty_tx, 1751 (u32)ndev->state, edtrr); 1752 /* dirty buffer free */ 1753 sh_eth_tx_free(ndev, true); 1754 1755 /* SH7712 BUG */ 1756 if (edtrr ^ mdp->cd->edtrr_trns) { 1757 /* tx dma start */ 1758 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 1759 } 1760 /* wakeup */ 1761 netif_wake_queue(ndev); 1762 } 1763 } 1764 1765 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1766 { 1767 struct net_device *ndev = netdev; 1768 struct sh_eth_private *mdp = netdev_priv(ndev); 1769 struct sh_eth_cpu_data *cd = mdp->cd; 1770 irqreturn_t ret = IRQ_NONE; 1771 u32 intr_status, intr_enable; 1772 1773 spin_lock(&mdp->lock); 1774 1775 /* Get interrupt status */ 1776 intr_status = sh_eth_read(ndev, EESR); 1777 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1778 * enabled since it's the one that comes thru regardless of the mask, 1779 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1780 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1781 * bit... 1782 */ 1783 intr_enable = sh_eth_read(ndev, EESIPR); 1784 intr_status &= intr_enable | EESIPR_ECIIP; 1785 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1786 cd->eesr_err_check)) 1787 ret = IRQ_HANDLED; 1788 else 1789 goto out; 1790 1791 if (unlikely(!mdp->irq_enabled)) { 1792 sh_eth_write(ndev, 0, EESIPR); 1793 goto out; 1794 } 1795 1796 if (intr_status & EESR_RX_CHECK) { 1797 if (napi_schedule_prep(&mdp->napi)) { 1798 /* Mask Rx interrupts */ 1799 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1800 EESIPR); 1801 __napi_schedule(&mdp->napi); 1802 } else { 1803 netdev_warn(ndev, 1804 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1805 intr_status, intr_enable); 1806 } 1807 } 1808 1809 /* Tx Check */ 1810 if (intr_status & cd->tx_check) { 1811 /* Clear Tx interrupts */ 1812 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1813 1814 sh_eth_tx_free(ndev, true); 1815 netif_wake_queue(ndev); 1816 } 1817 1818 /* E-MAC interrupt */ 1819 if (intr_status & EESR_ECI) 1820 sh_eth_emac_interrupt(ndev); 1821 1822 if (intr_status & cd->eesr_err_check) { 1823 /* Clear error interrupts */ 1824 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1825 1826 sh_eth_error(ndev, intr_status); 1827 } 1828 1829 out: 1830 spin_unlock(&mdp->lock); 1831 1832 return ret; 1833 } 1834 1835 static int sh_eth_poll(struct napi_struct *napi, int budget) 1836 { 1837 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1838 napi); 1839 struct net_device *ndev = napi->dev; 1840 int quota = budget; 1841 u32 intr_status; 1842 1843 for (;;) { 1844 intr_status = sh_eth_read(ndev, EESR); 1845 if (!(intr_status & EESR_RX_CHECK)) 1846 break; 1847 /* Clear Rx interrupts */ 1848 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1849 1850 if (sh_eth_rx(ndev, intr_status, "a)) 1851 goto out; 1852 } 1853 1854 napi_complete(napi); 1855 1856 /* Reenable Rx interrupts */ 1857 if (mdp->irq_enabled) 1858 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1859 out: 1860 return budget - quota; 1861 } 1862 1863 /* PHY state control function */ 1864 static void sh_eth_adjust_link(struct net_device *ndev) 1865 { 1866 struct sh_eth_private *mdp = netdev_priv(ndev); 1867 struct phy_device *phydev = ndev->phydev; 1868 int new_state = 0; 1869 1870 if (phydev->link) { 1871 if (phydev->duplex != mdp->duplex) { 1872 new_state = 1; 1873 mdp->duplex = phydev->duplex; 1874 if (mdp->cd->set_duplex) 1875 mdp->cd->set_duplex(ndev); 1876 } 1877 1878 if (phydev->speed != mdp->speed) { 1879 new_state = 1; 1880 mdp->speed = phydev->speed; 1881 if (mdp->cd->set_rate) 1882 mdp->cd->set_rate(ndev); 1883 } 1884 if (!mdp->link) { 1885 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1886 new_state = 1; 1887 mdp->link = phydev->link; 1888 if (mdp->cd->no_psr || mdp->no_ether_link) 1889 sh_eth_rcv_snd_enable(ndev); 1890 } 1891 } else if (mdp->link) { 1892 new_state = 1; 1893 mdp->link = 0; 1894 mdp->speed = 0; 1895 mdp->duplex = -1; 1896 if (mdp->cd->no_psr || mdp->no_ether_link) 1897 sh_eth_rcv_snd_disable(ndev); 1898 } 1899 1900 if (new_state && netif_msg_link(mdp)) 1901 phy_print_status(phydev); 1902 } 1903 1904 /* PHY init function */ 1905 static int sh_eth_phy_init(struct net_device *ndev) 1906 { 1907 struct device_node *np = ndev->dev.parent->of_node; 1908 struct sh_eth_private *mdp = netdev_priv(ndev); 1909 struct phy_device *phydev; 1910 1911 mdp->link = 0; 1912 mdp->speed = 0; 1913 mdp->duplex = -1; 1914 1915 /* Try connect to PHY */ 1916 if (np) { 1917 struct device_node *pn; 1918 1919 pn = of_parse_phandle(np, "phy-handle", 0); 1920 phydev = of_phy_connect(ndev, pn, 1921 sh_eth_adjust_link, 0, 1922 mdp->phy_interface); 1923 1924 of_node_put(pn); 1925 if (!phydev) 1926 phydev = ERR_PTR(-ENOENT); 1927 } else { 1928 char phy_id[MII_BUS_ID_SIZE + 3]; 1929 1930 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1931 mdp->mii_bus->id, mdp->phy_id); 1932 1933 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1934 mdp->phy_interface); 1935 } 1936 1937 if (IS_ERR(phydev)) { 1938 netdev_err(ndev, "failed to connect PHY\n"); 1939 return PTR_ERR(phydev); 1940 } 1941 1942 /* mask with MAC supported features */ 1943 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) { 1944 int err = phy_set_max_speed(phydev, SPEED_100); 1945 if (err) { 1946 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n"); 1947 phy_disconnect(phydev); 1948 return err; 1949 } 1950 } 1951 1952 phy_attached_info(phydev); 1953 1954 return 0; 1955 } 1956 1957 /* PHY control start function */ 1958 static int sh_eth_phy_start(struct net_device *ndev) 1959 { 1960 int ret; 1961 1962 ret = sh_eth_phy_init(ndev); 1963 if (ret) 1964 return ret; 1965 1966 phy_start(ndev->phydev); 1967 1968 return 0; 1969 } 1970 1971 static int sh_eth_get_link_ksettings(struct net_device *ndev, 1972 struct ethtool_link_ksettings *cmd) 1973 { 1974 struct sh_eth_private *mdp = netdev_priv(ndev); 1975 unsigned long flags; 1976 1977 if (!ndev->phydev) 1978 return -ENODEV; 1979 1980 spin_lock_irqsave(&mdp->lock, flags); 1981 phy_ethtool_ksettings_get(ndev->phydev, cmd); 1982 spin_unlock_irqrestore(&mdp->lock, flags); 1983 1984 return 0; 1985 } 1986 1987 static int sh_eth_set_link_ksettings(struct net_device *ndev, 1988 const struct ethtool_link_ksettings *cmd) 1989 { 1990 struct sh_eth_private *mdp = netdev_priv(ndev); 1991 unsigned long flags; 1992 int ret; 1993 1994 if (!ndev->phydev) 1995 return -ENODEV; 1996 1997 spin_lock_irqsave(&mdp->lock, flags); 1998 1999 /* disable tx and rx */ 2000 sh_eth_rcv_snd_disable(ndev); 2001 2002 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd); 2003 if (ret) 2004 goto error_exit; 2005 2006 if (cmd->base.duplex == DUPLEX_FULL) 2007 mdp->duplex = 1; 2008 else 2009 mdp->duplex = 0; 2010 2011 if (mdp->cd->set_duplex) 2012 mdp->cd->set_duplex(ndev); 2013 2014 error_exit: 2015 mdelay(1); 2016 2017 /* enable tx and rx */ 2018 sh_eth_rcv_snd_enable(ndev); 2019 2020 spin_unlock_irqrestore(&mdp->lock, flags); 2021 2022 return ret; 2023 } 2024 2025 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 2026 * version must be bumped as well. Just adding registers up to that 2027 * limit is fine, as long as the existing register indices don't 2028 * change. 2029 */ 2030 #define SH_ETH_REG_DUMP_VERSION 1 2031 #define SH_ETH_REG_DUMP_MAX_REGS 256 2032 2033 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 2034 { 2035 struct sh_eth_private *mdp = netdev_priv(ndev); 2036 struct sh_eth_cpu_data *cd = mdp->cd; 2037 u32 *valid_map; 2038 size_t len; 2039 2040 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 2041 2042 /* Dump starts with a bitmap that tells ethtool which 2043 * registers are defined for this chip. 2044 */ 2045 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 2046 if (buf) { 2047 valid_map = buf; 2048 buf += len; 2049 } else { 2050 valid_map = NULL; 2051 } 2052 2053 /* Add a register to the dump, if it has a defined offset. 2054 * This automatically skips most undefined registers, but for 2055 * some it is also necessary to check a capability flag in 2056 * struct sh_eth_cpu_data. 2057 */ 2058 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2059 #define add_reg_from(reg, read_expr) do { \ 2060 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2061 if (buf) { \ 2062 mark_reg_valid(reg); \ 2063 *buf++ = read_expr; \ 2064 } \ 2065 ++len; \ 2066 } \ 2067 } while (0) 2068 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2069 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2070 2071 add_reg(EDSR); 2072 add_reg(EDMR); 2073 add_reg(EDTRR); 2074 add_reg(EDRRR); 2075 add_reg(EESR); 2076 add_reg(EESIPR); 2077 add_reg(TDLAR); 2078 add_reg(TDFAR); 2079 add_reg(TDFXR); 2080 add_reg(TDFFR); 2081 add_reg(RDLAR); 2082 add_reg(RDFAR); 2083 add_reg(RDFXR); 2084 add_reg(RDFFR); 2085 add_reg(TRSCER); 2086 add_reg(RMFCR); 2087 add_reg(TFTR); 2088 add_reg(FDR); 2089 add_reg(RMCR); 2090 add_reg(TFUCR); 2091 add_reg(RFOCR); 2092 if (cd->rmiimode) 2093 add_reg(RMIIMODE); 2094 add_reg(FCFTR); 2095 if (cd->rpadir) 2096 add_reg(RPADIR); 2097 if (!cd->no_trimd) 2098 add_reg(TRIMD); 2099 add_reg(ECMR); 2100 add_reg(ECSR); 2101 add_reg(ECSIPR); 2102 add_reg(PIR); 2103 if (!cd->no_psr) 2104 add_reg(PSR); 2105 add_reg(RDMLR); 2106 add_reg(RFLR); 2107 add_reg(IPGR); 2108 if (cd->apr) 2109 add_reg(APR); 2110 if (cd->mpr) 2111 add_reg(MPR); 2112 add_reg(RFCR); 2113 add_reg(RFCF); 2114 if (cd->tpauser) 2115 add_reg(TPAUSER); 2116 add_reg(TPAUSECR); 2117 add_reg(GECMR); 2118 if (cd->bculr) 2119 add_reg(BCULR); 2120 add_reg(MAHR); 2121 add_reg(MALR); 2122 add_reg(TROCR); 2123 add_reg(CDCR); 2124 add_reg(LCCR); 2125 add_reg(CNDCR); 2126 add_reg(CEFCR); 2127 add_reg(FRECR); 2128 add_reg(TSFRCR); 2129 add_reg(TLFRCR); 2130 add_reg(CERCR); 2131 add_reg(CEECR); 2132 add_reg(MAFCR); 2133 if (cd->rtrate) 2134 add_reg(RTRATE); 2135 if (cd->hw_checksum) 2136 add_reg(CSMR); 2137 if (cd->select_mii) 2138 add_reg(RMII_MII); 2139 if (cd->tsu) { 2140 add_tsu_reg(ARSTR); 2141 add_tsu_reg(TSU_CTRST); 2142 add_tsu_reg(TSU_FWEN0); 2143 add_tsu_reg(TSU_FWEN1); 2144 add_tsu_reg(TSU_FCM); 2145 add_tsu_reg(TSU_BSYSL0); 2146 add_tsu_reg(TSU_BSYSL1); 2147 add_tsu_reg(TSU_PRISL0); 2148 add_tsu_reg(TSU_PRISL1); 2149 add_tsu_reg(TSU_FWSL0); 2150 add_tsu_reg(TSU_FWSL1); 2151 add_tsu_reg(TSU_FWSLC); 2152 add_tsu_reg(TSU_QTAGM0); 2153 add_tsu_reg(TSU_QTAGM1); 2154 add_tsu_reg(TSU_FWSR); 2155 add_tsu_reg(TSU_FWINMK); 2156 add_tsu_reg(TSU_ADQT0); 2157 add_tsu_reg(TSU_ADQT1); 2158 add_tsu_reg(TSU_VTAG0); 2159 add_tsu_reg(TSU_VTAG1); 2160 add_tsu_reg(TSU_ADSBSY); 2161 add_tsu_reg(TSU_TEN); 2162 add_tsu_reg(TSU_POST1); 2163 add_tsu_reg(TSU_POST2); 2164 add_tsu_reg(TSU_POST3); 2165 add_tsu_reg(TSU_POST4); 2166 /* This is the start of a table, not just a single register. */ 2167 if (buf) { 2168 unsigned int i; 2169 2170 mark_reg_valid(TSU_ADRH0); 2171 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2172 *buf++ = ioread32(mdp->tsu_addr + 2173 mdp->reg_offset[TSU_ADRH0] + 2174 i * 4); 2175 } 2176 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2177 } 2178 2179 #undef mark_reg_valid 2180 #undef add_reg_from 2181 #undef add_reg 2182 #undef add_tsu_reg 2183 2184 return len * 4; 2185 } 2186 2187 static int sh_eth_get_regs_len(struct net_device *ndev) 2188 { 2189 return __sh_eth_get_regs(ndev, NULL); 2190 } 2191 2192 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2193 void *buf) 2194 { 2195 struct sh_eth_private *mdp = netdev_priv(ndev); 2196 2197 regs->version = SH_ETH_REG_DUMP_VERSION; 2198 2199 pm_runtime_get_sync(&mdp->pdev->dev); 2200 __sh_eth_get_regs(ndev, buf); 2201 pm_runtime_put_sync(&mdp->pdev->dev); 2202 } 2203 2204 static int sh_eth_nway_reset(struct net_device *ndev) 2205 { 2206 struct sh_eth_private *mdp = netdev_priv(ndev); 2207 unsigned long flags; 2208 int ret; 2209 2210 if (!ndev->phydev) 2211 return -ENODEV; 2212 2213 spin_lock_irqsave(&mdp->lock, flags); 2214 ret = phy_start_aneg(ndev->phydev); 2215 spin_unlock_irqrestore(&mdp->lock, flags); 2216 2217 return ret; 2218 } 2219 2220 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2221 { 2222 struct sh_eth_private *mdp = netdev_priv(ndev); 2223 return mdp->msg_enable; 2224 } 2225 2226 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2227 { 2228 struct sh_eth_private *mdp = netdev_priv(ndev); 2229 mdp->msg_enable = value; 2230 } 2231 2232 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2233 "rx_current", "tx_current", 2234 "rx_dirty", "tx_dirty", 2235 }; 2236 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2237 2238 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2239 { 2240 switch (sset) { 2241 case ETH_SS_STATS: 2242 return SH_ETH_STATS_LEN; 2243 default: 2244 return -EOPNOTSUPP; 2245 } 2246 } 2247 2248 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2249 struct ethtool_stats *stats, u64 *data) 2250 { 2251 struct sh_eth_private *mdp = netdev_priv(ndev); 2252 int i = 0; 2253 2254 /* device-specific stats */ 2255 data[i++] = mdp->cur_rx; 2256 data[i++] = mdp->cur_tx; 2257 data[i++] = mdp->dirty_rx; 2258 data[i++] = mdp->dirty_tx; 2259 } 2260 2261 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2262 { 2263 switch (stringset) { 2264 case ETH_SS_STATS: 2265 memcpy(data, *sh_eth_gstrings_stats, 2266 sizeof(sh_eth_gstrings_stats)); 2267 break; 2268 } 2269 } 2270 2271 static void sh_eth_get_ringparam(struct net_device *ndev, 2272 struct ethtool_ringparam *ring) 2273 { 2274 struct sh_eth_private *mdp = netdev_priv(ndev); 2275 2276 ring->rx_max_pending = RX_RING_MAX; 2277 ring->tx_max_pending = TX_RING_MAX; 2278 ring->rx_pending = mdp->num_rx_ring; 2279 ring->tx_pending = mdp->num_tx_ring; 2280 } 2281 2282 static int sh_eth_set_ringparam(struct net_device *ndev, 2283 struct ethtool_ringparam *ring) 2284 { 2285 struct sh_eth_private *mdp = netdev_priv(ndev); 2286 int ret; 2287 2288 if (ring->tx_pending > TX_RING_MAX || 2289 ring->rx_pending > RX_RING_MAX || 2290 ring->tx_pending < TX_RING_MIN || 2291 ring->rx_pending < RX_RING_MIN) 2292 return -EINVAL; 2293 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2294 return -EINVAL; 2295 2296 if (netif_running(ndev)) { 2297 netif_device_detach(ndev); 2298 netif_tx_disable(ndev); 2299 2300 /* Serialise with the interrupt handler and NAPI, then 2301 * disable interrupts. We have to clear the 2302 * irq_enabled flag first to ensure that interrupts 2303 * won't be re-enabled. 2304 */ 2305 mdp->irq_enabled = false; 2306 synchronize_irq(ndev->irq); 2307 napi_synchronize(&mdp->napi); 2308 sh_eth_write(ndev, 0x0000, EESIPR); 2309 2310 sh_eth_dev_exit(ndev); 2311 2312 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2313 sh_eth_ring_free(ndev); 2314 } 2315 2316 /* Set new parameters */ 2317 mdp->num_rx_ring = ring->rx_pending; 2318 mdp->num_tx_ring = ring->tx_pending; 2319 2320 if (netif_running(ndev)) { 2321 ret = sh_eth_ring_init(ndev); 2322 if (ret < 0) { 2323 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2324 __func__); 2325 return ret; 2326 } 2327 ret = sh_eth_dev_init(ndev); 2328 if (ret < 0) { 2329 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2330 __func__); 2331 return ret; 2332 } 2333 2334 netif_device_attach(ndev); 2335 } 2336 2337 return 0; 2338 } 2339 2340 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2341 { 2342 struct sh_eth_private *mdp = netdev_priv(ndev); 2343 2344 wol->supported = 0; 2345 wol->wolopts = 0; 2346 2347 if (mdp->cd->magic) { 2348 wol->supported = WAKE_MAGIC; 2349 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2350 } 2351 } 2352 2353 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2354 { 2355 struct sh_eth_private *mdp = netdev_priv(ndev); 2356 2357 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2358 return -EOPNOTSUPP; 2359 2360 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2361 2362 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2363 2364 return 0; 2365 } 2366 2367 static const struct ethtool_ops sh_eth_ethtool_ops = { 2368 .get_regs_len = sh_eth_get_regs_len, 2369 .get_regs = sh_eth_get_regs, 2370 .nway_reset = sh_eth_nway_reset, 2371 .get_msglevel = sh_eth_get_msglevel, 2372 .set_msglevel = sh_eth_set_msglevel, 2373 .get_link = ethtool_op_get_link, 2374 .get_strings = sh_eth_get_strings, 2375 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2376 .get_sset_count = sh_eth_get_sset_count, 2377 .get_ringparam = sh_eth_get_ringparam, 2378 .set_ringparam = sh_eth_set_ringparam, 2379 .get_link_ksettings = sh_eth_get_link_ksettings, 2380 .set_link_ksettings = sh_eth_set_link_ksettings, 2381 .get_wol = sh_eth_get_wol, 2382 .set_wol = sh_eth_set_wol, 2383 }; 2384 2385 /* network device open function */ 2386 static int sh_eth_open(struct net_device *ndev) 2387 { 2388 struct sh_eth_private *mdp = netdev_priv(ndev); 2389 int ret; 2390 2391 pm_runtime_get_sync(&mdp->pdev->dev); 2392 2393 napi_enable(&mdp->napi); 2394 2395 ret = request_irq(ndev->irq, sh_eth_interrupt, 2396 mdp->cd->irq_flags, ndev->name, ndev); 2397 if (ret) { 2398 netdev_err(ndev, "Can not assign IRQ number\n"); 2399 goto out_napi_off; 2400 } 2401 2402 /* Descriptor set */ 2403 ret = sh_eth_ring_init(ndev); 2404 if (ret) 2405 goto out_free_irq; 2406 2407 /* device init */ 2408 ret = sh_eth_dev_init(ndev); 2409 if (ret) 2410 goto out_free_irq; 2411 2412 /* PHY control start*/ 2413 ret = sh_eth_phy_start(ndev); 2414 if (ret) 2415 goto out_free_irq; 2416 2417 netif_start_queue(ndev); 2418 2419 mdp->is_opened = 1; 2420 2421 return ret; 2422 2423 out_free_irq: 2424 free_irq(ndev->irq, ndev); 2425 out_napi_off: 2426 napi_disable(&mdp->napi); 2427 pm_runtime_put_sync(&mdp->pdev->dev); 2428 return ret; 2429 } 2430 2431 /* Timeout function */ 2432 static void sh_eth_tx_timeout(struct net_device *ndev) 2433 { 2434 struct sh_eth_private *mdp = netdev_priv(ndev); 2435 struct sh_eth_rxdesc *rxdesc; 2436 int i; 2437 2438 netif_stop_queue(ndev); 2439 2440 netif_err(mdp, timer, ndev, 2441 "transmit timed out, status %8.8x, resetting...\n", 2442 sh_eth_read(ndev, EESR)); 2443 2444 /* tx_errors count up */ 2445 ndev->stats.tx_errors++; 2446 2447 /* Free all the skbuffs in the Rx queue. */ 2448 for (i = 0; i < mdp->num_rx_ring; i++) { 2449 rxdesc = &mdp->rx_ring[i]; 2450 rxdesc->status = cpu_to_le32(0); 2451 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2452 dev_kfree_skb(mdp->rx_skbuff[i]); 2453 mdp->rx_skbuff[i] = NULL; 2454 } 2455 for (i = 0; i < mdp->num_tx_ring; i++) { 2456 dev_kfree_skb(mdp->tx_skbuff[i]); 2457 mdp->tx_skbuff[i] = NULL; 2458 } 2459 2460 /* device init */ 2461 sh_eth_dev_init(ndev); 2462 2463 netif_start_queue(ndev); 2464 } 2465 2466 /* Packet transmit function */ 2467 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2468 { 2469 struct sh_eth_private *mdp = netdev_priv(ndev); 2470 struct sh_eth_txdesc *txdesc; 2471 dma_addr_t dma_addr; 2472 u32 entry; 2473 unsigned long flags; 2474 2475 spin_lock_irqsave(&mdp->lock, flags); 2476 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2477 if (!sh_eth_tx_free(ndev, true)) { 2478 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2479 netif_stop_queue(ndev); 2480 spin_unlock_irqrestore(&mdp->lock, flags); 2481 return NETDEV_TX_BUSY; 2482 } 2483 } 2484 spin_unlock_irqrestore(&mdp->lock, flags); 2485 2486 if (skb_put_padto(skb, ETH_ZLEN)) 2487 return NETDEV_TX_OK; 2488 2489 entry = mdp->cur_tx % mdp->num_tx_ring; 2490 mdp->tx_skbuff[entry] = skb; 2491 txdesc = &mdp->tx_ring[entry]; 2492 /* soft swap. */ 2493 if (!mdp->cd->hw_swap) 2494 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2495 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2496 DMA_TO_DEVICE); 2497 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2498 kfree_skb(skb); 2499 return NETDEV_TX_OK; 2500 } 2501 txdesc->addr = cpu_to_le32(dma_addr); 2502 txdesc->len = cpu_to_le32(skb->len << 16); 2503 2504 dma_wmb(); /* TACT bit must be set after all the above writes */ 2505 if (entry >= mdp->num_tx_ring - 1) 2506 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2507 else 2508 txdesc->status |= cpu_to_le32(TD_TACT); 2509 2510 mdp->cur_tx++; 2511 2512 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns)) 2513 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 2514 2515 return NETDEV_TX_OK; 2516 } 2517 2518 /* The statistics registers have write-clear behaviour, which means we 2519 * will lose any increment between the read and write. We mitigate 2520 * this by only clearing when we read a non-zero value, so we will 2521 * never falsely report a total of zero. 2522 */ 2523 static void 2524 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2525 { 2526 u32 delta = sh_eth_read(ndev, reg); 2527 2528 if (delta) { 2529 *stat += delta; 2530 sh_eth_write(ndev, 0, reg); 2531 } 2532 } 2533 2534 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2535 { 2536 struct sh_eth_private *mdp = netdev_priv(ndev); 2537 2538 if (mdp->cd->no_tx_cntrs) 2539 return &ndev->stats; 2540 2541 if (!mdp->is_opened) 2542 return &ndev->stats; 2543 2544 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2545 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2546 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2547 2548 if (mdp->cd->cexcr) { 2549 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2550 CERCR); 2551 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2552 CEECR); 2553 } else { 2554 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2555 CNDCR); 2556 } 2557 2558 return &ndev->stats; 2559 } 2560 2561 /* device close function */ 2562 static int sh_eth_close(struct net_device *ndev) 2563 { 2564 struct sh_eth_private *mdp = netdev_priv(ndev); 2565 2566 netif_stop_queue(ndev); 2567 2568 /* Serialise with the interrupt handler and NAPI, then disable 2569 * interrupts. We have to clear the irq_enabled flag first to 2570 * ensure that interrupts won't be re-enabled. 2571 */ 2572 mdp->irq_enabled = false; 2573 synchronize_irq(ndev->irq); 2574 napi_disable(&mdp->napi); 2575 sh_eth_write(ndev, 0x0000, EESIPR); 2576 2577 sh_eth_dev_exit(ndev); 2578 2579 /* PHY Disconnect */ 2580 if (ndev->phydev) { 2581 phy_stop(ndev->phydev); 2582 phy_disconnect(ndev->phydev); 2583 } 2584 2585 free_irq(ndev->irq, ndev); 2586 2587 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2588 sh_eth_ring_free(ndev); 2589 2590 pm_runtime_put_sync(&mdp->pdev->dev); 2591 2592 mdp->is_opened = 0; 2593 2594 return 0; 2595 } 2596 2597 /* ioctl to device function */ 2598 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2599 { 2600 struct phy_device *phydev = ndev->phydev; 2601 2602 if (!netif_running(ndev)) 2603 return -EINVAL; 2604 2605 if (!phydev) 2606 return -ENODEV; 2607 2608 return phy_mii_ioctl(phydev, rq, cmd); 2609 } 2610 2611 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2612 { 2613 if (netif_running(ndev)) 2614 return -EBUSY; 2615 2616 ndev->mtu = new_mtu; 2617 netdev_update_features(ndev); 2618 2619 return 0; 2620 } 2621 2622 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2623 static u32 sh_eth_tsu_get_post_mask(int entry) 2624 { 2625 return 0x0f << (28 - ((entry % 8) * 4)); 2626 } 2627 2628 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2629 { 2630 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2631 } 2632 2633 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2634 int entry) 2635 { 2636 struct sh_eth_private *mdp = netdev_priv(ndev); 2637 int reg = TSU_POST1 + entry / 8; 2638 u32 tmp; 2639 2640 tmp = sh_eth_tsu_read(mdp, reg); 2641 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg); 2642 } 2643 2644 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2645 int entry) 2646 { 2647 struct sh_eth_private *mdp = netdev_priv(ndev); 2648 int reg = TSU_POST1 + entry / 8; 2649 u32 post_mask, ref_mask, tmp; 2650 2651 post_mask = sh_eth_tsu_get_post_mask(entry); 2652 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2653 2654 tmp = sh_eth_tsu_read(mdp, reg); 2655 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg); 2656 2657 /* If other port enables, the function returns "true" */ 2658 return tmp & ref_mask; 2659 } 2660 2661 static int sh_eth_tsu_busy(struct net_device *ndev) 2662 { 2663 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2664 struct sh_eth_private *mdp = netdev_priv(ndev); 2665 2666 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2667 udelay(10); 2668 timeout--; 2669 if (timeout <= 0) { 2670 netdev_err(ndev, "%s: timeout\n", __func__); 2671 return -ETIMEDOUT; 2672 } 2673 } 2674 2675 return 0; 2676 } 2677 2678 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2679 const u8 *addr) 2680 { 2681 u32 val; 2682 2683 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2684 iowrite32(val, reg); 2685 if (sh_eth_tsu_busy(ndev) < 0) 2686 return -EBUSY; 2687 2688 val = addr[4] << 8 | addr[5]; 2689 iowrite32(val, reg + 4); 2690 if (sh_eth_tsu_busy(ndev) < 0) 2691 return -EBUSY; 2692 2693 return 0; 2694 } 2695 2696 static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2697 { 2698 u32 val; 2699 2700 val = ioread32(reg); 2701 addr[0] = (val >> 24) & 0xff; 2702 addr[1] = (val >> 16) & 0xff; 2703 addr[2] = (val >> 8) & 0xff; 2704 addr[3] = val & 0xff; 2705 val = ioread32(reg + 4); 2706 addr[4] = (val >> 8) & 0xff; 2707 addr[5] = val & 0xff; 2708 } 2709 2710 2711 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2712 { 2713 struct sh_eth_private *mdp = netdev_priv(ndev); 2714 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2715 int i; 2716 u8 c_addr[ETH_ALEN]; 2717 2718 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2719 sh_eth_tsu_read_entry(reg_offset, c_addr); 2720 if (ether_addr_equal(addr, c_addr)) 2721 return i; 2722 } 2723 2724 return -ENOENT; 2725 } 2726 2727 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2728 { 2729 u8 blank[ETH_ALEN]; 2730 int entry; 2731 2732 memset(blank, 0, sizeof(blank)); 2733 entry = sh_eth_tsu_find_entry(ndev, blank); 2734 return (entry < 0) ? -ENOMEM : entry; 2735 } 2736 2737 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2738 int entry) 2739 { 2740 struct sh_eth_private *mdp = netdev_priv(ndev); 2741 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2742 int ret; 2743 u8 blank[ETH_ALEN]; 2744 2745 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2746 ~(1 << (31 - entry)), TSU_TEN); 2747 2748 memset(blank, 0, sizeof(blank)); 2749 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2750 if (ret < 0) 2751 return ret; 2752 return 0; 2753 } 2754 2755 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2756 { 2757 struct sh_eth_private *mdp = netdev_priv(ndev); 2758 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2759 int i, ret; 2760 2761 if (!mdp->cd->tsu) 2762 return 0; 2763 2764 i = sh_eth_tsu_find_entry(ndev, addr); 2765 if (i < 0) { 2766 /* No entry found, create one */ 2767 i = sh_eth_tsu_find_empty(ndev); 2768 if (i < 0) 2769 return -ENOMEM; 2770 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2771 if (ret < 0) 2772 return ret; 2773 2774 /* Enable the entry */ 2775 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2776 (1 << (31 - i)), TSU_TEN); 2777 } 2778 2779 /* Entry found or created, enable POST */ 2780 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2781 2782 return 0; 2783 } 2784 2785 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2786 { 2787 struct sh_eth_private *mdp = netdev_priv(ndev); 2788 int i, ret; 2789 2790 if (!mdp->cd->tsu) 2791 return 0; 2792 2793 i = sh_eth_tsu_find_entry(ndev, addr); 2794 if (i) { 2795 /* Entry found */ 2796 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2797 goto done; 2798 2799 /* Disable the entry if both ports was disabled */ 2800 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2801 if (ret < 0) 2802 return ret; 2803 } 2804 done: 2805 return 0; 2806 } 2807 2808 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2809 { 2810 struct sh_eth_private *mdp = netdev_priv(ndev); 2811 int i, ret; 2812 2813 if (!mdp->cd->tsu) 2814 return 0; 2815 2816 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2817 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2818 continue; 2819 2820 /* Disable the entry if both ports was disabled */ 2821 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2822 if (ret < 0) 2823 return ret; 2824 } 2825 2826 return 0; 2827 } 2828 2829 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2830 { 2831 struct sh_eth_private *mdp = netdev_priv(ndev); 2832 u8 addr[ETH_ALEN]; 2833 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2834 int i; 2835 2836 if (!mdp->cd->tsu) 2837 return; 2838 2839 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2840 sh_eth_tsu_read_entry(reg_offset, addr); 2841 if (is_multicast_ether_addr(addr)) 2842 sh_eth_tsu_del_entry(ndev, addr); 2843 } 2844 } 2845 2846 /* Update promiscuous flag and multicast filter */ 2847 static void sh_eth_set_rx_mode(struct net_device *ndev) 2848 { 2849 struct sh_eth_private *mdp = netdev_priv(ndev); 2850 u32 ecmr_bits; 2851 int mcast_all = 0; 2852 unsigned long flags; 2853 2854 spin_lock_irqsave(&mdp->lock, flags); 2855 /* Initial condition is MCT = 1, PRM = 0. 2856 * Depending on ndev->flags, set PRM or clear MCT 2857 */ 2858 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2859 if (mdp->cd->tsu) 2860 ecmr_bits |= ECMR_MCT; 2861 2862 if (!(ndev->flags & IFF_MULTICAST)) { 2863 sh_eth_tsu_purge_mcast(ndev); 2864 mcast_all = 1; 2865 } 2866 if (ndev->flags & IFF_ALLMULTI) { 2867 sh_eth_tsu_purge_mcast(ndev); 2868 ecmr_bits &= ~ECMR_MCT; 2869 mcast_all = 1; 2870 } 2871 2872 if (ndev->flags & IFF_PROMISC) { 2873 sh_eth_tsu_purge_all(ndev); 2874 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2875 } else if (mdp->cd->tsu) { 2876 struct netdev_hw_addr *ha; 2877 netdev_for_each_mc_addr(ha, ndev) { 2878 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2879 continue; 2880 2881 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2882 if (!mcast_all) { 2883 sh_eth_tsu_purge_mcast(ndev); 2884 ecmr_bits &= ~ECMR_MCT; 2885 mcast_all = 1; 2886 } 2887 } 2888 } 2889 } 2890 2891 /* update the ethernet mode */ 2892 sh_eth_write(ndev, ecmr_bits, ECMR); 2893 2894 spin_unlock_irqrestore(&mdp->lock, flags); 2895 } 2896 2897 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2898 { 2899 if (!mdp->port) 2900 return TSU_VTAG0; 2901 else 2902 return TSU_VTAG1; 2903 } 2904 2905 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2906 __be16 proto, u16 vid) 2907 { 2908 struct sh_eth_private *mdp = netdev_priv(ndev); 2909 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2910 2911 if (unlikely(!mdp->cd->tsu)) 2912 return -EPERM; 2913 2914 /* No filtering if vid = 0 */ 2915 if (!vid) 2916 return 0; 2917 2918 mdp->vlan_num_ids++; 2919 2920 /* The controller has one VLAN tag HW filter. So, if the filter is 2921 * already enabled, the driver disables it and the filte 2922 */ 2923 if (mdp->vlan_num_ids > 1) { 2924 /* disable VLAN filter */ 2925 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2926 return 0; 2927 } 2928 2929 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2930 vtag_reg_index); 2931 2932 return 0; 2933 } 2934 2935 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2936 __be16 proto, u16 vid) 2937 { 2938 struct sh_eth_private *mdp = netdev_priv(ndev); 2939 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2940 2941 if (unlikely(!mdp->cd->tsu)) 2942 return -EPERM; 2943 2944 /* No filtering if vid = 0 */ 2945 if (!vid) 2946 return 0; 2947 2948 mdp->vlan_num_ids--; 2949 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2950 2951 return 0; 2952 } 2953 2954 /* SuperH's TSU register init function */ 2955 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2956 { 2957 if (!mdp->cd->dual_port) { 2958 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2959 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 2960 TSU_FWSLC); /* Enable POST registers */ 2961 return; 2962 } 2963 2964 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2965 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2966 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2967 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2968 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2969 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2970 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2971 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2972 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2973 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2974 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2975 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2976 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2977 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2978 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2979 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2980 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2981 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2982 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2983 } 2984 2985 /* MDIO bus release function */ 2986 static int sh_mdio_release(struct sh_eth_private *mdp) 2987 { 2988 /* unregister mdio bus */ 2989 mdiobus_unregister(mdp->mii_bus); 2990 2991 /* free bitbang info */ 2992 free_mdio_bitbang(mdp->mii_bus); 2993 2994 return 0; 2995 } 2996 2997 /* MDIO bus init function */ 2998 static int sh_mdio_init(struct sh_eth_private *mdp, 2999 struct sh_eth_plat_data *pd) 3000 { 3001 int ret; 3002 struct bb_info *bitbang; 3003 struct platform_device *pdev = mdp->pdev; 3004 struct device *dev = &mdp->pdev->dev; 3005 3006 /* create bit control struct for PHY */ 3007 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 3008 if (!bitbang) 3009 return -ENOMEM; 3010 3011 /* bitbang init */ 3012 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 3013 bitbang->set_gate = pd->set_mdio_gate; 3014 bitbang->ctrl.ops = &bb_ops; 3015 3016 /* MII controller setting */ 3017 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 3018 if (!mdp->mii_bus) 3019 return -ENOMEM; 3020 3021 /* Hook up MII support for ethtool */ 3022 mdp->mii_bus->name = "sh_mii"; 3023 mdp->mii_bus->parent = dev; 3024 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 3025 pdev->name, pdev->id); 3026 3027 /* register MDIO bus */ 3028 if (pd->phy_irq > 0) 3029 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3030 3031 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3032 if (ret) 3033 goto out_free_bus; 3034 3035 return 0; 3036 3037 out_free_bus: 3038 free_mdio_bitbang(mdp->mii_bus); 3039 return ret; 3040 } 3041 3042 static const u16 *sh_eth_get_register_offset(int register_type) 3043 { 3044 const u16 *reg_offset = NULL; 3045 3046 switch (register_type) { 3047 case SH_ETH_REG_GIGABIT: 3048 reg_offset = sh_eth_offset_gigabit; 3049 break; 3050 case SH_ETH_REG_FAST_RZ: 3051 reg_offset = sh_eth_offset_fast_rz; 3052 break; 3053 case SH_ETH_REG_FAST_RCAR: 3054 reg_offset = sh_eth_offset_fast_rcar; 3055 break; 3056 case SH_ETH_REG_FAST_SH4: 3057 reg_offset = sh_eth_offset_fast_sh4; 3058 break; 3059 case SH_ETH_REG_FAST_SH3_SH2: 3060 reg_offset = sh_eth_offset_fast_sh3_sh2; 3061 break; 3062 } 3063 3064 return reg_offset; 3065 } 3066 3067 static const struct net_device_ops sh_eth_netdev_ops = { 3068 .ndo_open = sh_eth_open, 3069 .ndo_stop = sh_eth_close, 3070 .ndo_start_xmit = sh_eth_start_xmit, 3071 .ndo_get_stats = sh_eth_get_stats, 3072 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3073 .ndo_tx_timeout = sh_eth_tx_timeout, 3074 .ndo_do_ioctl = sh_eth_do_ioctl, 3075 .ndo_change_mtu = sh_eth_change_mtu, 3076 .ndo_validate_addr = eth_validate_addr, 3077 .ndo_set_mac_address = eth_mac_addr, 3078 }; 3079 3080 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3081 .ndo_open = sh_eth_open, 3082 .ndo_stop = sh_eth_close, 3083 .ndo_start_xmit = sh_eth_start_xmit, 3084 .ndo_get_stats = sh_eth_get_stats, 3085 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3086 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3087 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3088 .ndo_tx_timeout = sh_eth_tx_timeout, 3089 .ndo_do_ioctl = sh_eth_do_ioctl, 3090 .ndo_change_mtu = sh_eth_change_mtu, 3091 .ndo_validate_addr = eth_validate_addr, 3092 .ndo_set_mac_address = eth_mac_addr, 3093 }; 3094 3095 #ifdef CONFIG_OF 3096 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3097 { 3098 struct device_node *np = dev->of_node; 3099 struct sh_eth_plat_data *pdata; 3100 const char *mac_addr; 3101 3102 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3103 if (!pdata) 3104 return NULL; 3105 3106 pdata->phy_interface = of_get_phy_mode(np); 3107 3108 mac_addr = of_get_mac_address(np); 3109 if (mac_addr) 3110 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 3111 3112 pdata->no_ether_link = 3113 of_property_read_bool(np, "renesas,no-ether-link"); 3114 pdata->ether_link_active_low = 3115 of_property_read_bool(np, "renesas,ether-link-active-low"); 3116 3117 return pdata; 3118 } 3119 3120 static const struct of_device_id sh_eth_match_table[] = { 3121 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3122 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3123 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3124 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3125 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3126 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3127 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3128 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3129 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3130 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3131 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3132 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3133 { } 3134 }; 3135 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3136 #else 3137 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3138 { 3139 return NULL; 3140 } 3141 #endif 3142 3143 static int sh_eth_drv_probe(struct platform_device *pdev) 3144 { 3145 struct resource *res; 3146 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3147 const struct platform_device_id *id = platform_get_device_id(pdev); 3148 struct sh_eth_private *mdp; 3149 struct net_device *ndev; 3150 int ret; 3151 3152 /* get base addr */ 3153 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3154 3155 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3156 if (!ndev) 3157 return -ENOMEM; 3158 3159 pm_runtime_enable(&pdev->dev); 3160 pm_runtime_get_sync(&pdev->dev); 3161 3162 ret = platform_get_irq(pdev, 0); 3163 if (ret < 0) 3164 goto out_release; 3165 ndev->irq = ret; 3166 3167 SET_NETDEV_DEV(ndev, &pdev->dev); 3168 3169 mdp = netdev_priv(ndev); 3170 mdp->num_tx_ring = TX_RING_SIZE; 3171 mdp->num_rx_ring = RX_RING_SIZE; 3172 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3173 if (IS_ERR(mdp->addr)) { 3174 ret = PTR_ERR(mdp->addr); 3175 goto out_release; 3176 } 3177 3178 ndev->base_addr = res->start; 3179 3180 spin_lock_init(&mdp->lock); 3181 mdp->pdev = pdev; 3182 3183 if (pdev->dev.of_node) 3184 pd = sh_eth_parse_dt(&pdev->dev); 3185 if (!pd) { 3186 dev_err(&pdev->dev, "no platform data\n"); 3187 ret = -EINVAL; 3188 goto out_release; 3189 } 3190 3191 /* get PHY ID */ 3192 mdp->phy_id = pd->phy; 3193 mdp->phy_interface = pd->phy_interface; 3194 mdp->no_ether_link = pd->no_ether_link; 3195 mdp->ether_link_active_low = pd->ether_link_active_low; 3196 3197 /* set cpu data */ 3198 if (id) 3199 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3200 else 3201 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3202 3203 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3204 if (!mdp->reg_offset) { 3205 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3206 mdp->cd->register_type); 3207 ret = -EINVAL; 3208 goto out_release; 3209 } 3210 sh_eth_set_default_cpu_data(mdp->cd); 3211 3212 /* User's manual states max MTU should be 2048 but due to the 3213 * alignment calculations in sh_eth_ring_init() the practical 3214 * MTU is a bit less. Maybe this can be optimized some more. 3215 */ 3216 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3217 ndev->min_mtu = ETH_MIN_MTU; 3218 3219 /* set function */ 3220 if (mdp->cd->tsu) 3221 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3222 else 3223 ndev->netdev_ops = &sh_eth_netdev_ops; 3224 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3225 ndev->watchdog_timeo = TX_TIMEOUT; 3226 3227 /* debug message level */ 3228 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3229 3230 /* read and set MAC address */ 3231 read_mac_address(ndev, pd->mac_addr); 3232 if (!is_valid_ether_addr(ndev->dev_addr)) { 3233 dev_warn(&pdev->dev, 3234 "no valid MAC address supplied, using a random one.\n"); 3235 eth_hw_addr_random(ndev); 3236 } 3237 3238 if (mdp->cd->tsu) { 3239 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3240 struct resource *rtsu; 3241 3242 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3243 if (!rtsu) { 3244 dev_err(&pdev->dev, "no TSU resource\n"); 3245 ret = -ENODEV; 3246 goto out_release; 3247 } 3248 /* We can only request the TSU region for the first port 3249 * of the two sharing this TSU for the probe to succeed... 3250 */ 3251 if (port == 0 && 3252 !devm_request_mem_region(&pdev->dev, rtsu->start, 3253 resource_size(rtsu), 3254 dev_name(&pdev->dev))) { 3255 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3256 ret = -EBUSY; 3257 goto out_release; 3258 } 3259 /* ioremap the TSU registers */ 3260 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3261 resource_size(rtsu)); 3262 if (!mdp->tsu_addr) { 3263 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3264 ret = -ENOMEM; 3265 goto out_release; 3266 } 3267 mdp->port = port; 3268 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 3269 3270 /* Need to init only the first port of the two sharing a TSU */ 3271 if (port == 0) { 3272 if (mdp->cd->chip_reset) 3273 mdp->cd->chip_reset(ndev); 3274 3275 /* TSU init (Init only)*/ 3276 sh_eth_tsu_init(mdp); 3277 } 3278 } 3279 3280 if (mdp->cd->rmiimode) 3281 sh_eth_write(ndev, 0x1, RMIIMODE); 3282 3283 /* MDIO bus init */ 3284 ret = sh_mdio_init(mdp, pd); 3285 if (ret) { 3286 if (ret != -EPROBE_DEFER) 3287 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); 3288 goto out_release; 3289 } 3290 3291 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3292 3293 /* network device register */ 3294 ret = register_netdev(ndev); 3295 if (ret) 3296 goto out_napi_del; 3297 3298 if (mdp->cd->magic) 3299 device_set_wakeup_capable(&pdev->dev, 1); 3300 3301 /* print device information */ 3302 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3303 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3304 3305 pm_runtime_put(&pdev->dev); 3306 platform_set_drvdata(pdev, ndev); 3307 3308 return ret; 3309 3310 out_napi_del: 3311 netif_napi_del(&mdp->napi); 3312 sh_mdio_release(mdp); 3313 3314 out_release: 3315 /* net_dev free */ 3316 free_netdev(ndev); 3317 3318 pm_runtime_put(&pdev->dev); 3319 pm_runtime_disable(&pdev->dev); 3320 return ret; 3321 } 3322 3323 static int sh_eth_drv_remove(struct platform_device *pdev) 3324 { 3325 struct net_device *ndev = platform_get_drvdata(pdev); 3326 struct sh_eth_private *mdp = netdev_priv(ndev); 3327 3328 unregister_netdev(ndev); 3329 netif_napi_del(&mdp->napi); 3330 sh_mdio_release(mdp); 3331 pm_runtime_disable(&pdev->dev); 3332 free_netdev(ndev); 3333 3334 return 0; 3335 } 3336 3337 #ifdef CONFIG_PM 3338 #ifdef CONFIG_PM_SLEEP 3339 static int sh_eth_wol_setup(struct net_device *ndev) 3340 { 3341 struct sh_eth_private *mdp = netdev_priv(ndev); 3342 3343 /* Only allow ECI interrupts */ 3344 synchronize_irq(ndev->irq); 3345 napi_disable(&mdp->napi); 3346 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3347 3348 /* Enable MagicPacket */ 3349 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3350 3351 return enable_irq_wake(ndev->irq); 3352 } 3353 3354 static int sh_eth_wol_restore(struct net_device *ndev) 3355 { 3356 struct sh_eth_private *mdp = netdev_priv(ndev); 3357 int ret; 3358 3359 napi_enable(&mdp->napi); 3360 3361 /* Disable MagicPacket */ 3362 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3363 3364 /* The device needs to be reset to restore MagicPacket logic 3365 * for next wakeup. If we close and open the device it will 3366 * both be reset and all registers restored. This is what 3367 * happens during suspend and resume without WoL enabled. 3368 */ 3369 ret = sh_eth_close(ndev); 3370 if (ret < 0) 3371 return ret; 3372 ret = sh_eth_open(ndev); 3373 if (ret < 0) 3374 return ret; 3375 3376 return disable_irq_wake(ndev->irq); 3377 } 3378 3379 static int sh_eth_suspend(struct device *dev) 3380 { 3381 struct net_device *ndev = dev_get_drvdata(dev); 3382 struct sh_eth_private *mdp = netdev_priv(ndev); 3383 int ret = 0; 3384 3385 if (!netif_running(ndev)) 3386 return 0; 3387 3388 netif_device_detach(ndev); 3389 3390 if (mdp->wol_enabled) 3391 ret = sh_eth_wol_setup(ndev); 3392 else 3393 ret = sh_eth_close(ndev); 3394 3395 return ret; 3396 } 3397 3398 static int sh_eth_resume(struct device *dev) 3399 { 3400 struct net_device *ndev = dev_get_drvdata(dev); 3401 struct sh_eth_private *mdp = netdev_priv(ndev); 3402 int ret = 0; 3403 3404 if (!netif_running(ndev)) 3405 return 0; 3406 3407 if (mdp->wol_enabled) 3408 ret = sh_eth_wol_restore(ndev); 3409 else 3410 ret = sh_eth_open(ndev); 3411 3412 if (ret < 0) 3413 return ret; 3414 3415 netif_device_attach(ndev); 3416 3417 return ret; 3418 } 3419 #endif 3420 3421 static int sh_eth_runtime_nop(struct device *dev) 3422 { 3423 /* Runtime PM callback shared between ->runtime_suspend() 3424 * and ->runtime_resume(). Simply returns success. 3425 * 3426 * This driver re-initializes all registers after 3427 * pm_runtime_get_sync() anyway so there is no need 3428 * to save and restore registers here. 3429 */ 3430 return 0; 3431 } 3432 3433 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3434 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3435 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3436 }; 3437 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3438 #else 3439 #define SH_ETH_PM_OPS NULL 3440 #endif 3441 3442 static const struct platform_device_id sh_eth_id_table[] = { 3443 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3444 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3445 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3446 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3447 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3448 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3449 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3450 { } 3451 }; 3452 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3453 3454 static struct platform_driver sh_eth_driver = { 3455 .probe = sh_eth_drv_probe, 3456 .remove = sh_eth_drv_remove, 3457 .id_table = sh_eth_id_table, 3458 .driver = { 3459 .name = CARDNAME, 3460 .pm = SH_ETH_PM_OPS, 3461 .of_match_table = of_match_ptr(sh_eth_match_table), 3462 }, 3463 }; 3464 3465 module_platform_driver(sh_eth_driver); 3466 3467 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3468 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3469 MODULE_LICENSE("GPL v2"); 3470