1 // SPDX-License-Identifier: GPL-2.0 2 /* SuperH Ethernet device driver 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 6 * Copyright (C) 2008-2014 Renesas Solutions Corp. 7 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 8 * Copyright (C) 2014 Codethink Limited 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/spinlock.h> 14 #include <linux/interrupt.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/etherdevice.h> 17 #include <linux/delay.h> 18 #include <linux/platform_device.h> 19 #include <linux/mdio-bitbang.h> 20 #include <linux/netdevice.h> 21 #include <linux/of.h> 22 #include <linux/of_net.h> 23 #include <linux/phy.h> 24 #include <linux/cache.h> 25 #include <linux/io.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/slab.h> 28 #include <linux/ethtool.h> 29 #include <linux/if_vlan.h> 30 #include <linux/sh_eth.h> 31 #include <linux/of_mdio.h> 32 33 #include "sh_eth.h" 34 35 #define SH_ETH_DEF_MSG_ENABLE \ 36 (NETIF_MSG_LINK | \ 37 NETIF_MSG_TIMER | \ 38 NETIF_MSG_RX_ERR| \ 39 NETIF_MSG_TX_ERR) 40 41 #define SH_ETH_OFFSET_INVALID ((u16)~0) 42 43 #define SH_ETH_OFFSET_DEFAULTS \ 44 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 45 46 /* use some intentionally tricky logic here to initialize the whole struct to 47 * 0xffff, but then override certain fields, requiring us to indicate that we 48 * "know" that there are overrides in this structure, and we'll need to disable 49 * that warning from W=1 builds. GCC has supported this option since 4.2.X, but 50 * the macros available to do this only define GCC 8. 51 */ 52 __diag_push(); 53 __diag_ignore_all("-Woverride-init", 54 "logic to initialize all and then override some is OK"); 55 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 56 SH_ETH_OFFSET_DEFAULTS, 57 58 [EDSR] = 0x0000, 59 [EDMR] = 0x0400, 60 [EDTRR] = 0x0408, 61 [EDRRR] = 0x0410, 62 [EESR] = 0x0428, 63 [EESIPR] = 0x0430, 64 [TDLAR] = 0x0010, 65 [TDFAR] = 0x0014, 66 [TDFXR] = 0x0018, 67 [TDFFR] = 0x001c, 68 [RDLAR] = 0x0030, 69 [RDFAR] = 0x0034, 70 [RDFXR] = 0x0038, 71 [RDFFR] = 0x003c, 72 [TRSCER] = 0x0438, 73 [RMFCR] = 0x0440, 74 [TFTR] = 0x0448, 75 [FDR] = 0x0450, 76 [RMCR] = 0x0458, 77 [RPADIR] = 0x0460, 78 [FCFTR] = 0x0468, 79 [CSMR] = 0x04E4, 80 81 [ECMR] = 0x0500, 82 [ECSR] = 0x0510, 83 [ECSIPR] = 0x0518, 84 [PIR] = 0x0520, 85 [PSR] = 0x0528, 86 [PIPR] = 0x052c, 87 [RFLR] = 0x0508, 88 [APR] = 0x0554, 89 [MPR] = 0x0558, 90 [PFTCR] = 0x055c, 91 [PFRCR] = 0x0560, 92 [TPAUSER] = 0x0564, 93 [GECMR] = 0x05b0, 94 [BCULR] = 0x05b4, 95 [MAHR] = 0x05c0, 96 [MALR] = 0x05c8, 97 [TROCR] = 0x0700, 98 [CDCR] = 0x0708, 99 [LCCR] = 0x0710, 100 [CEFCR] = 0x0740, 101 [FRECR] = 0x0748, 102 [TSFRCR] = 0x0750, 103 [TLFRCR] = 0x0758, 104 [RFCR] = 0x0760, 105 [CERCR] = 0x0768, 106 [CEECR] = 0x0770, 107 [MAFCR] = 0x0778, 108 [RMII_MII] = 0x0790, 109 110 [ARSTR] = 0x0000, 111 [TSU_CTRST] = 0x0004, 112 [TSU_FWEN0] = 0x0010, 113 [TSU_FWEN1] = 0x0014, 114 [TSU_FCM] = 0x0018, 115 [TSU_BSYSL0] = 0x0020, 116 [TSU_BSYSL1] = 0x0024, 117 [TSU_PRISL0] = 0x0028, 118 [TSU_PRISL1] = 0x002c, 119 [TSU_FWSL0] = 0x0030, 120 [TSU_FWSL1] = 0x0034, 121 [TSU_FWSLC] = 0x0038, 122 [TSU_QTAGM0] = 0x0040, 123 [TSU_QTAGM1] = 0x0044, 124 [TSU_FWSR] = 0x0050, 125 [TSU_FWINMK] = 0x0054, 126 [TSU_ADQT0] = 0x0048, 127 [TSU_ADQT1] = 0x004c, 128 [TSU_VTAG0] = 0x0058, 129 [TSU_VTAG1] = 0x005c, 130 [TSU_ADSBSY] = 0x0060, 131 [TSU_TEN] = 0x0064, 132 [TSU_POST1] = 0x0070, 133 [TSU_POST2] = 0x0074, 134 [TSU_POST3] = 0x0078, 135 [TSU_POST4] = 0x007c, 136 [TSU_ADRH0] = 0x0100, 137 138 [TXNLCR0] = 0x0080, 139 [TXALCR0] = 0x0084, 140 [RXNLCR0] = 0x0088, 141 [RXALCR0] = 0x008c, 142 [FWNLCR0] = 0x0090, 143 [FWALCR0] = 0x0094, 144 [TXNLCR1] = 0x00a0, 145 [TXALCR1] = 0x00a4, 146 [RXNLCR1] = 0x00a8, 147 [RXALCR1] = 0x00ac, 148 [FWNLCR1] = 0x00b0, 149 [FWALCR1] = 0x00b4, 150 }; 151 152 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 153 SH_ETH_OFFSET_DEFAULTS, 154 155 [ECMR] = 0x0300, 156 [RFLR] = 0x0308, 157 [ECSR] = 0x0310, 158 [ECSIPR] = 0x0318, 159 [PIR] = 0x0320, 160 [PSR] = 0x0328, 161 [RDMLR] = 0x0340, 162 [IPGR] = 0x0350, 163 [APR] = 0x0354, 164 [MPR] = 0x0358, 165 [RFCF] = 0x0360, 166 [TPAUSER] = 0x0364, 167 [TPAUSECR] = 0x0368, 168 [MAHR] = 0x03c0, 169 [MALR] = 0x03c8, 170 [TROCR] = 0x03d0, 171 [CDCR] = 0x03d4, 172 [LCCR] = 0x03d8, 173 [CNDCR] = 0x03dc, 174 [CEFCR] = 0x03e4, 175 [FRECR] = 0x03e8, 176 [TSFRCR] = 0x03ec, 177 [TLFRCR] = 0x03f0, 178 [RFCR] = 0x03f4, 179 [MAFCR] = 0x03f8, 180 181 [EDMR] = 0x0200, 182 [EDTRR] = 0x0208, 183 [EDRRR] = 0x0210, 184 [TDLAR] = 0x0218, 185 [RDLAR] = 0x0220, 186 [EESR] = 0x0228, 187 [EESIPR] = 0x0230, 188 [TRSCER] = 0x0238, 189 [RMFCR] = 0x0240, 190 [TFTR] = 0x0248, 191 [FDR] = 0x0250, 192 [RMCR] = 0x0258, 193 [TFUCR] = 0x0264, 194 [RFOCR] = 0x0268, 195 [RMIIMODE] = 0x026c, 196 [FCFTR] = 0x0270, 197 [TRIMD] = 0x027c, 198 }; 199 200 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 201 SH_ETH_OFFSET_DEFAULTS, 202 203 [ECMR] = 0x0100, 204 [RFLR] = 0x0108, 205 [ECSR] = 0x0110, 206 [ECSIPR] = 0x0118, 207 [PIR] = 0x0120, 208 [PSR] = 0x0128, 209 [RDMLR] = 0x0140, 210 [IPGR] = 0x0150, 211 [APR] = 0x0154, 212 [MPR] = 0x0158, 213 [TPAUSER] = 0x0164, 214 [RFCF] = 0x0160, 215 [TPAUSECR] = 0x0168, 216 [BCFRR] = 0x016c, 217 [MAHR] = 0x01c0, 218 [MALR] = 0x01c8, 219 [TROCR] = 0x01d0, 220 [CDCR] = 0x01d4, 221 [LCCR] = 0x01d8, 222 [CNDCR] = 0x01dc, 223 [CEFCR] = 0x01e4, 224 [FRECR] = 0x01e8, 225 [TSFRCR] = 0x01ec, 226 [TLFRCR] = 0x01f0, 227 [RFCR] = 0x01f4, 228 [MAFCR] = 0x01f8, 229 [RTRATE] = 0x01fc, 230 231 [EDMR] = 0x0000, 232 [EDTRR] = 0x0008, 233 [EDRRR] = 0x0010, 234 [TDLAR] = 0x0018, 235 [RDLAR] = 0x0020, 236 [EESR] = 0x0028, 237 [EESIPR] = 0x0030, 238 [TRSCER] = 0x0038, 239 [RMFCR] = 0x0040, 240 [TFTR] = 0x0048, 241 [FDR] = 0x0050, 242 [RMCR] = 0x0058, 243 [TFUCR] = 0x0064, 244 [RFOCR] = 0x0068, 245 [FCFTR] = 0x0070, 246 [RPADIR] = 0x0078, 247 [TRIMD] = 0x007c, 248 [RBWAR] = 0x00c8, 249 [RDFAR] = 0x00cc, 250 [TBRAR] = 0x00d4, 251 [TDFAR] = 0x00d8, 252 }; 253 254 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 255 SH_ETH_OFFSET_DEFAULTS, 256 257 [EDMR] = 0x0000, 258 [EDTRR] = 0x0004, 259 [EDRRR] = 0x0008, 260 [TDLAR] = 0x000c, 261 [RDLAR] = 0x0010, 262 [EESR] = 0x0014, 263 [EESIPR] = 0x0018, 264 [TRSCER] = 0x001c, 265 [RMFCR] = 0x0020, 266 [TFTR] = 0x0024, 267 [FDR] = 0x0028, 268 [RMCR] = 0x002c, 269 [EDOCR] = 0x0030, 270 [FCFTR] = 0x0034, 271 [RPADIR] = 0x0038, 272 [TRIMD] = 0x003c, 273 [RBWAR] = 0x0040, 274 [RDFAR] = 0x0044, 275 [TBRAR] = 0x004c, 276 [TDFAR] = 0x0050, 277 278 [ECMR] = 0x0160, 279 [ECSR] = 0x0164, 280 [ECSIPR] = 0x0168, 281 [PIR] = 0x016c, 282 [MAHR] = 0x0170, 283 [MALR] = 0x0174, 284 [RFLR] = 0x0178, 285 [PSR] = 0x017c, 286 [TROCR] = 0x0180, 287 [CDCR] = 0x0184, 288 [LCCR] = 0x0188, 289 [CNDCR] = 0x018c, 290 [CEFCR] = 0x0194, 291 [FRECR] = 0x0198, 292 [TSFRCR] = 0x019c, 293 [TLFRCR] = 0x01a0, 294 [RFCR] = 0x01a4, 295 [MAFCR] = 0x01a8, 296 [IPGR] = 0x01b4, 297 [APR] = 0x01b8, 298 [MPR] = 0x01bc, 299 [TPAUSER] = 0x01c4, 300 [BCFR] = 0x01cc, 301 302 [ARSTR] = 0x0000, 303 [TSU_CTRST] = 0x0004, 304 [TSU_FWEN0] = 0x0010, 305 [TSU_FWEN1] = 0x0014, 306 [TSU_FCM] = 0x0018, 307 [TSU_BSYSL0] = 0x0020, 308 [TSU_BSYSL1] = 0x0024, 309 [TSU_PRISL0] = 0x0028, 310 [TSU_PRISL1] = 0x002c, 311 [TSU_FWSL0] = 0x0030, 312 [TSU_FWSL1] = 0x0034, 313 [TSU_FWSLC] = 0x0038, 314 [TSU_QTAGM0] = 0x0040, 315 [TSU_QTAGM1] = 0x0044, 316 [TSU_ADQT0] = 0x0048, 317 [TSU_ADQT1] = 0x004c, 318 [TSU_FWSR] = 0x0050, 319 [TSU_FWINMK] = 0x0054, 320 [TSU_ADSBSY] = 0x0060, 321 [TSU_TEN] = 0x0064, 322 [TSU_POST1] = 0x0070, 323 [TSU_POST2] = 0x0074, 324 [TSU_POST3] = 0x0078, 325 [TSU_POST4] = 0x007c, 326 327 [TXNLCR0] = 0x0080, 328 [TXALCR0] = 0x0084, 329 [RXNLCR0] = 0x0088, 330 [RXALCR0] = 0x008c, 331 [FWNLCR0] = 0x0090, 332 [FWALCR0] = 0x0094, 333 [TXNLCR1] = 0x00a0, 334 [TXALCR1] = 0x00a4, 335 [RXNLCR1] = 0x00a8, 336 [RXALCR1] = 0x00ac, 337 [FWNLCR1] = 0x00b0, 338 [FWALCR1] = 0x00b4, 339 340 [TSU_ADRH0] = 0x0100, 341 }; 342 __diag_pop(); 343 344 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 345 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 346 347 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 348 { 349 struct sh_eth_private *mdp = netdev_priv(ndev); 350 u16 offset = mdp->reg_offset[enum_index]; 351 352 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 353 return; 354 355 iowrite32(data, mdp->addr + offset); 356 } 357 358 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 359 { 360 struct sh_eth_private *mdp = netdev_priv(ndev); 361 u16 offset = mdp->reg_offset[enum_index]; 362 363 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 364 return ~0U; 365 366 return ioread32(mdp->addr + offset); 367 } 368 369 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 370 u32 set) 371 { 372 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 373 enum_index); 374 } 375 376 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index) 377 { 378 return mdp->reg_offset[enum_index]; 379 } 380 381 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data, 382 int enum_index) 383 { 384 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 385 386 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 387 return; 388 389 iowrite32(data, mdp->tsu_addr + offset); 390 } 391 392 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index) 393 { 394 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index); 395 396 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 397 return ~0U; 398 399 return ioread32(mdp->tsu_addr + offset); 400 } 401 402 static void sh_eth_soft_swap(char *src, int len) 403 { 404 #ifdef __LITTLE_ENDIAN 405 u32 *p = (u32 *)src; 406 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32)); 407 408 for (; p < maxp; p++) 409 *p = swab32(*p); 410 #endif 411 } 412 413 static void sh_eth_select_mii(struct net_device *ndev) 414 { 415 struct sh_eth_private *mdp = netdev_priv(ndev); 416 u32 value; 417 418 switch (mdp->phy_interface) { 419 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID: 420 value = 0x3; 421 break; 422 case PHY_INTERFACE_MODE_GMII: 423 value = 0x2; 424 break; 425 case PHY_INTERFACE_MODE_MII: 426 value = 0x1; 427 break; 428 case PHY_INTERFACE_MODE_RMII: 429 value = 0x0; 430 break; 431 default: 432 netdev_warn(ndev, 433 "PHY interface mode was not setup. Set to MII.\n"); 434 value = 0x1; 435 break; 436 } 437 438 sh_eth_write(ndev, value, RMII_MII); 439 } 440 441 static void sh_eth_set_duplex(struct net_device *ndev) 442 { 443 struct sh_eth_private *mdp = netdev_priv(ndev); 444 445 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 446 } 447 448 static void sh_eth_chip_reset(struct net_device *ndev) 449 { 450 struct sh_eth_private *mdp = netdev_priv(ndev); 451 452 /* reset device */ 453 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 454 mdelay(1); 455 } 456 457 static int sh_eth_soft_reset(struct net_device *ndev) 458 { 459 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 460 mdelay(3); 461 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 462 463 return 0; 464 } 465 466 static int sh_eth_check_soft_reset(struct net_device *ndev) 467 { 468 int cnt; 469 470 for (cnt = 100; cnt > 0; cnt--) { 471 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 472 return 0; 473 mdelay(1); 474 } 475 476 netdev_err(ndev, "Device reset failed\n"); 477 return -ETIMEDOUT; 478 } 479 480 static int sh_eth_soft_reset_gether(struct net_device *ndev) 481 { 482 struct sh_eth_private *mdp = netdev_priv(ndev); 483 int ret; 484 485 sh_eth_write(ndev, EDSR_ENALL, EDSR); 486 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 487 488 ret = sh_eth_check_soft_reset(ndev); 489 if (ret) 490 return ret; 491 492 /* Table Init */ 493 sh_eth_write(ndev, 0, TDLAR); 494 sh_eth_write(ndev, 0, TDFAR); 495 sh_eth_write(ndev, 0, TDFXR); 496 sh_eth_write(ndev, 0, TDFFR); 497 sh_eth_write(ndev, 0, RDLAR); 498 sh_eth_write(ndev, 0, RDFAR); 499 sh_eth_write(ndev, 0, RDFXR); 500 sh_eth_write(ndev, 0, RDFFR); 501 502 /* Reset HW CRC register */ 503 if (mdp->cd->csmr) 504 sh_eth_write(ndev, 0, CSMR); 505 506 /* Select MII mode */ 507 if (mdp->cd->select_mii) 508 sh_eth_select_mii(ndev); 509 510 return ret; 511 } 512 513 static void sh_eth_set_rate_gether(struct net_device *ndev) 514 { 515 struct sh_eth_private *mdp = netdev_priv(ndev); 516 517 if (WARN_ON(!mdp->cd->gecmr)) 518 return; 519 520 switch (mdp->speed) { 521 case 10: /* 10BASE */ 522 sh_eth_write(ndev, GECMR_10, GECMR); 523 break; 524 case 100:/* 100BASE */ 525 sh_eth_write(ndev, GECMR_100, GECMR); 526 break; 527 case 1000: /* 1000BASE */ 528 sh_eth_write(ndev, GECMR_1000, GECMR); 529 break; 530 } 531 } 532 533 #ifdef CONFIG_OF 534 /* R7S72100 */ 535 static struct sh_eth_cpu_data r7s72100_data = { 536 .soft_reset = sh_eth_soft_reset_gether, 537 538 .chip_reset = sh_eth_chip_reset, 539 .set_duplex = sh_eth_set_duplex, 540 541 .register_type = SH_ETH_REG_GIGABIT, 542 543 .edtrr_trns = EDTRR_TRNS_GETHER, 544 .ecsr_value = ECSR_ICD, 545 .ecsipr_value = ECSIPR_ICDIP, 546 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 547 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 548 EESIPR_ECIIP | 549 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 550 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 551 EESIPR_RMAFIP | EESIPR_RRFIP | 552 EESIPR_RTLFIP | EESIPR_RTSFIP | 553 EESIPR_PREIP | EESIPR_CERFIP, 554 555 .tx_check = EESR_TC1 | EESR_FTC, 556 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 557 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 558 EESR_TDE, 559 .fdr_value = 0x0000070f, 560 561 .trscer_err_mask = TRSCER_RMAFCE | TRSCER_RRFCE, 562 563 .no_psr = 1, 564 .apr = 1, 565 .mpr = 1, 566 .tpauser = 1, 567 .hw_swap = 1, 568 .rpadir = 1, 569 .no_trimd = 1, 570 .no_ade = 1, 571 .xdfar_rw = 1, 572 .csmr = 1, 573 .rx_csum = 1, 574 .tsu = 1, 575 .no_tx_cntrs = 1, 576 }; 577 578 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 579 { 580 sh_eth_chip_reset(ndev); 581 582 sh_eth_select_mii(ndev); 583 } 584 585 /* R8A7740 */ 586 static struct sh_eth_cpu_data r8a7740_data = { 587 .soft_reset = sh_eth_soft_reset_gether, 588 589 .chip_reset = sh_eth_chip_reset_r8a7740, 590 .set_duplex = sh_eth_set_duplex, 591 .set_rate = sh_eth_set_rate_gether, 592 593 .register_type = SH_ETH_REG_GIGABIT, 594 595 .edtrr_trns = EDTRR_TRNS_GETHER, 596 .ecsr_value = ECSR_ICD | ECSR_MPD, 597 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 598 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 599 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 600 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 601 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 602 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 603 EESIPR_CEEFIP | EESIPR_CELFIP | 604 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 605 EESIPR_PREIP | EESIPR_CERFIP, 606 607 .tx_check = EESR_TC1 | EESR_FTC, 608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 610 EESR_TDE, 611 .fdr_value = 0x0000070f, 612 613 .apr = 1, 614 .mpr = 1, 615 .tpauser = 1, 616 .gecmr = 1, 617 .bculr = 1, 618 .hw_swap = 1, 619 .rpadir = 1, 620 .no_trimd = 1, 621 .no_ade = 1, 622 .xdfar_rw = 1, 623 .csmr = 1, 624 .rx_csum = 1, 625 .tsu = 1, 626 .select_mii = 1, 627 .magic = 1, 628 .cexcr = 1, 629 }; 630 631 /* There is CPU dependent code */ 632 static void sh_eth_set_rate_rcar(struct net_device *ndev) 633 { 634 struct sh_eth_private *mdp = netdev_priv(ndev); 635 636 switch (mdp->speed) { 637 case 10: /* 10BASE */ 638 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 639 break; 640 case 100:/* 100BASE */ 641 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 642 break; 643 } 644 } 645 646 /* R-Car Gen1 */ 647 static struct sh_eth_cpu_data rcar_gen1_data = { 648 .soft_reset = sh_eth_soft_reset, 649 650 .set_duplex = sh_eth_set_duplex, 651 .set_rate = sh_eth_set_rate_rcar, 652 653 .register_type = SH_ETH_REG_FAST_RCAR, 654 655 .edtrr_trns = EDTRR_TRNS_ETHER, 656 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 657 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 658 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 659 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 660 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 661 EESIPR_RMAFIP | EESIPR_RRFIP | 662 EESIPR_RTLFIP | EESIPR_RTSFIP | 663 EESIPR_PREIP | EESIPR_CERFIP, 664 665 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 666 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 667 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 668 .fdr_value = 0x00000f0f, 669 670 .apr = 1, 671 .mpr = 1, 672 .tpauser = 1, 673 .hw_swap = 1, 674 .no_xdfar = 1, 675 }; 676 677 /* R-Car Gen2 and RZ/G1 */ 678 static struct sh_eth_cpu_data rcar_gen2_data = { 679 .soft_reset = sh_eth_soft_reset, 680 681 .set_duplex = sh_eth_set_duplex, 682 .set_rate = sh_eth_set_rate_rcar, 683 684 .register_type = SH_ETH_REG_FAST_RCAR, 685 686 .edtrr_trns = EDTRR_TRNS_ETHER, 687 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 688 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 689 ECSIPR_MPDIP, 690 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 691 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 692 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 693 EESIPR_RMAFIP | EESIPR_RRFIP | 694 EESIPR_RTLFIP | EESIPR_RTSFIP | 695 EESIPR_PREIP | EESIPR_CERFIP, 696 697 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 698 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 699 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 700 .fdr_value = 0x00000f0f, 701 702 .trscer_err_mask = TRSCER_RMAFCE, 703 704 .apr = 1, 705 .mpr = 1, 706 .tpauser = 1, 707 .hw_swap = 1, 708 .no_xdfar = 1, 709 .rmiimode = 1, 710 .magic = 1, 711 }; 712 713 /* R8A77980 */ 714 static struct sh_eth_cpu_data r8a77980_data = { 715 .soft_reset = sh_eth_soft_reset_gether, 716 717 .set_duplex = sh_eth_set_duplex, 718 .set_rate = sh_eth_set_rate_gether, 719 720 .register_type = SH_ETH_REG_GIGABIT, 721 722 .edtrr_trns = EDTRR_TRNS_GETHER, 723 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 724 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 725 ECSIPR_MPDIP, 726 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 727 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 728 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 729 EESIPR_RMAFIP | EESIPR_RRFIP | 730 EESIPR_RTLFIP | EESIPR_RTSFIP | 731 EESIPR_PREIP | EESIPR_CERFIP, 732 733 .tx_check = EESR_FTC | EESR_CD | EESR_TRO, 734 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 735 EESR_RFE | EESR_RDE | EESR_RFRMER | 736 EESR_TFE | EESR_TDE | EESR_ECI, 737 .fdr_value = 0x0000070f, 738 739 .apr = 1, 740 .mpr = 1, 741 .tpauser = 1, 742 .gecmr = 1, 743 .bculr = 1, 744 .hw_swap = 1, 745 .nbst = 1, 746 .rpadir = 1, 747 .no_trimd = 1, 748 .no_ade = 1, 749 .xdfar_rw = 1, 750 .csmr = 1, 751 .rx_csum = 1, 752 .select_mii = 1, 753 .magic = 1, 754 .cexcr = 1, 755 }; 756 757 /* R7S9210 */ 758 static struct sh_eth_cpu_data r7s9210_data = { 759 .soft_reset = sh_eth_soft_reset, 760 761 .set_duplex = sh_eth_set_duplex, 762 .set_rate = sh_eth_set_rate_rcar, 763 764 .register_type = SH_ETH_REG_FAST_SH4, 765 766 .edtrr_trns = EDTRR_TRNS_ETHER, 767 .ecsr_value = ECSR_ICD, 768 .ecsipr_value = ECSIPR_ICDIP, 769 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP | 770 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP | 771 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP | 772 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP | 773 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 774 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP | 775 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP, 776 777 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 778 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 779 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 780 781 .fdr_value = 0x0000070f, 782 783 .trscer_err_mask = TRSCER_RMAFCE | TRSCER_RRFCE, 784 785 .apr = 1, 786 .mpr = 1, 787 .tpauser = 1, 788 .hw_swap = 1, 789 .rpadir = 1, 790 .no_ade = 1, 791 .xdfar_rw = 1, 792 }; 793 #endif /* CONFIG_OF */ 794 795 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 796 { 797 struct sh_eth_private *mdp = netdev_priv(ndev); 798 799 switch (mdp->speed) { 800 case 10: /* 10BASE */ 801 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 802 break; 803 case 100:/* 100BASE */ 804 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 805 break; 806 } 807 } 808 809 /* SH7724 */ 810 static struct sh_eth_cpu_data sh7724_data = { 811 .soft_reset = sh_eth_soft_reset, 812 813 .set_duplex = sh_eth_set_duplex, 814 .set_rate = sh_eth_set_rate_sh7724, 815 816 .register_type = SH_ETH_REG_FAST_SH4, 817 818 .edtrr_trns = EDTRR_TRNS_ETHER, 819 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 820 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 821 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 822 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 823 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 824 EESIPR_RMAFIP | EESIPR_RRFIP | 825 EESIPR_RTLFIP | EESIPR_RTSFIP | 826 EESIPR_PREIP | EESIPR_CERFIP, 827 828 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 829 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 830 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 831 832 .apr = 1, 833 .mpr = 1, 834 .tpauser = 1, 835 .hw_swap = 1, 836 .rpadir = 1, 837 }; 838 839 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 840 { 841 struct sh_eth_private *mdp = netdev_priv(ndev); 842 843 switch (mdp->speed) { 844 case 10: /* 10BASE */ 845 sh_eth_write(ndev, 0, RTRATE); 846 break; 847 case 100:/* 100BASE */ 848 sh_eth_write(ndev, 1, RTRATE); 849 break; 850 } 851 } 852 853 /* SH7757 */ 854 static struct sh_eth_cpu_data sh7757_data = { 855 .soft_reset = sh_eth_soft_reset, 856 857 .set_duplex = sh_eth_set_duplex, 858 .set_rate = sh_eth_set_rate_sh7757, 859 860 .register_type = SH_ETH_REG_FAST_SH4, 861 862 .edtrr_trns = EDTRR_TRNS_ETHER, 863 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 864 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 865 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 866 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 867 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 868 EESIPR_CEEFIP | EESIPR_CELFIP | 869 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 870 EESIPR_PREIP | EESIPR_CERFIP, 871 872 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 873 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 874 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 875 876 .irq_flags = IRQF_SHARED, 877 .apr = 1, 878 .mpr = 1, 879 .tpauser = 1, 880 .hw_swap = 1, 881 .no_ade = 1, 882 .rpadir = 1, 883 .rtrate = 1, 884 .dual_port = 1, 885 }; 886 887 #define SH_GIGA_ETH_BASE 0xfee00000UL 888 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 889 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 890 static void sh_eth_chip_reset_giga(struct net_device *ndev) 891 { 892 u32 mahr[2], malr[2]; 893 int i; 894 895 /* save MAHR and MALR */ 896 for (i = 0; i < 2; i++) { 897 malr[i] = ioread32((void *)GIGA_MALR(i)); 898 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 899 } 900 901 sh_eth_chip_reset(ndev); 902 903 /* restore MAHR and MALR */ 904 for (i = 0; i < 2; i++) { 905 iowrite32(malr[i], (void *)GIGA_MALR(i)); 906 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 907 } 908 } 909 910 static void sh_eth_set_rate_giga(struct net_device *ndev) 911 { 912 struct sh_eth_private *mdp = netdev_priv(ndev); 913 914 if (WARN_ON(!mdp->cd->gecmr)) 915 return; 916 917 switch (mdp->speed) { 918 case 10: /* 10BASE */ 919 sh_eth_write(ndev, 0x00000000, GECMR); 920 break; 921 case 100:/* 100BASE */ 922 sh_eth_write(ndev, 0x00000010, GECMR); 923 break; 924 case 1000: /* 1000BASE */ 925 sh_eth_write(ndev, 0x00000020, GECMR); 926 break; 927 } 928 } 929 930 /* SH7757(GETHERC) */ 931 static struct sh_eth_cpu_data sh7757_data_giga = { 932 .soft_reset = sh_eth_soft_reset_gether, 933 934 .chip_reset = sh_eth_chip_reset_giga, 935 .set_duplex = sh_eth_set_duplex, 936 .set_rate = sh_eth_set_rate_giga, 937 938 .register_type = SH_ETH_REG_GIGABIT, 939 940 .edtrr_trns = EDTRR_TRNS_GETHER, 941 .ecsr_value = ECSR_ICD | ECSR_MPD, 942 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 943 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 944 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 945 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 946 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 947 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 948 EESIPR_CEEFIP | EESIPR_CELFIP | 949 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 950 EESIPR_PREIP | EESIPR_CERFIP, 951 952 .tx_check = EESR_TC1 | EESR_FTC, 953 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 954 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 955 EESR_TDE, 956 .fdr_value = 0x0000072f, 957 958 .irq_flags = IRQF_SHARED, 959 .apr = 1, 960 .mpr = 1, 961 .tpauser = 1, 962 .gecmr = 1, 963 .bculr = 1, 964 .hw_swap = 1, 965 .rpadir = 1, 966 .no_trimd = 1, 967 .no_ade = 1, 968 .xdfar_rw = 1, 969 .tsu = 1, 970 .cexcr = 1, 971 .dual_port = 1, 972 }; 973 974 /* SH7734 */ 975 static struct sh_eth_cpu_data sh7734_data = { 976 .soft_reset = sh_eth_soft_reset_gether, 977 978 .chip_reset = sh_eth_chip_reset, 979 .set_duplex = sh_eth_set_duplex, 980 .set_rate = sh_eth_set_rate_gether, 981 982 .register_type = SH_ETH_REG_GIGABIT, 983 984 .edtrr_trns = EDTRR_TRNS_GETHER, 985 .ecsr_value = ECSR_ICD | ECSR_MPD, 986 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 987 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 988 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 989 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 990 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 991 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 992 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 993 EESIPR_PREIP | EESIPR_CERFIP, 994 995 .tx_check = EESR_TC1 | EESR_FTC, 996 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 997 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 998 EESR_TDE, 999 1000 .apr = 1, 1001 .mpr = 1, 1002 .tpauser = 1, 1003 .gecmr = 1, 1004 .bculr = 1, 1005 .hw_swap = 1, 1006 .no_trimd = 1, 1007 .no_ade = 1, 1008 .xdfar_rw = 1, 1009 .tsu = 1, 1010 .csmr = 1, 1011 .rx_csum = 1, 1012 .select_mii = 1, 1013 .magic = 1, 1014 .cexcr = 1, 1015 }; 1016 1017 /* SH7763 */ 1018 static struct sh_eth_cpu_data sh7763_data = { 1019 .soft_reset = sh_eth_soft_reset_gether, 1020 1021 .chip_reset = sh_eth_chip_reset, 1022 .set_duplex = sh_eth_set_duplex, 1023 .set_rate = sh_eth_set_rate_gether, 1024 1025 .register_type = SH_ETH_REG_GIGABIT, 1026 1027 .edtrr_trns = EDTRR_TRNS_GETHER, 1028 .ecsr_value = ECSR_ICD | ECSR_MPD, 1029 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1030 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1031 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1032 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1033 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1034 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1035 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1036 EESIPR_PREIP | EESIPR_CERFIP, 1037 1038 .tx_check = EESR_TC1 | EESR_FTC, 1039 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1040 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 1041 1042 .apr = 1, 1043 .mpr = 1, 1044 .tpauser = 1, 1045 .gecmr = 1, 1046 .bculr = 1, 1047 .hw_swap = 1, 1048 .no_trimd = 1, 1049 .no_ade = 1, 1050 .xdfar_rw = 1, 1051 .tsu = 1, 1052 .irq_flags = IRQF_SHARED, 1053 .magic = 1, 1054 .cexcr = 1, 1055 .rx_csum = 1, 1056 .dual_port = 1, 1057 }; 1058 1059 static struct sh_eth_cpu_data sh7619_data = { 1060 .soft_reset = sh_eth_soft_reset, 1061 1062 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1063 1064 .edtrr_trns = EDTRR_TRNS_ETHER, 1065 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1066 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1067 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1068 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1069 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1070 EESIPR_CEEFIP | EESIPR_CELFIP | 1071 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1072 EESIPR_PREIP | EESIPR_CERFIP, 1073 1074 .apr = 1, 1075 .mpr = 1, 1076 .tpauser = 1, 1077 .hw_swap = 1, 1078 }; 1079 1080 static struct sh_eth_cpu_data sh771x_data = { 1081 .soft_reset = sh_eth_soft_reset, 1082 1083 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1084 1085 .edtrr_trns = EDTRR_TRNS_ETHER, 1086 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1087 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1088 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1089 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1090 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1091 EESIPR_CEEFIP | EESIPR_CELFIP | 1092 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1093 EESIPR_PREIP | EESIPR_CERFIP, 1094 1095 .trscer_err_mask = TRSCER_RMAFCE, 1096 1097 .tsu = 1, 1098 .dual_port = 1, 1099 }; 1100 1101 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 1102 { 1103 if (!cd->ecsr_value) 1104 cd->ecsr_value = DEFAULT_ECSR_INIT; 1105 1106 if (!cd->ecsipr_value) 1107 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 1108 1109 if (!cd->fcftr_value) 1110 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 1111 DEFAULT_FIFO_F_D_RFD; 1112 1113 if (!cd->fdr_value) 1114 cd->fdr_value = DEFAULT_FDR_INIT; 1115 1116 if (!cd->tx_check) 1117 cd->tx_check = DEFAULT_TX_CHECK; 1118 1119 if (!cd->eesr_err_check) 1120 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 1121 1122 if (!cd->trscer_err_mask) 1123 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 1124 } 1125 1126 static void sh_eth_set_receive_align(struct sk_buff *skb) 1127 { 1128 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1129 1130 if (reserve) 1131 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1132 } 1133 1134 /* Program the hardware MAC address from dev->dev_addr. */ 1135 static void update_mac_address(struct net_device *ndev) 1136 { 1137 sh_eth_write(ndev, 1138 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1139 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1140 sh_eth_write(ndev, 1141 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1142 } 1143 1144 /* Get MAC address from SuperH MAC address register 1145 * 1146 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1147 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1148 * When you want use this device, you must set MAC address in bootloader. 1149 * 1150 */ 1151 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1152 { 1153 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1154 eth_hw_addr_set(ndev, mac); 1155 } else { 1156 u32 mahr = sh_eth_read(ndev, MAHR); 1157 u32 malr = sh_eth_read(ndev, MALR); 1158 u8 addr[ETH_ALEN]; 1159 1160 addr[0] = (mahr >> 24) & 0xFF; 1161 addr[1] = (mahr >> 16) & 0xFF; 1162 addr[2] = (mahr >> 8) & 0xFF; 1163 addr[3] = (mahr >> 0) & 0xFF; 1164 addr[4] = (malr >> 8) & 0xFF; 1165 addr[5] = (malr >> 0) & 0xFF; 1166 eth_hw_addr_set(ndev, addr); 1167 } 1168 } 1169 1170 struct bb_info { 1171 void (*set_gate)(void *addr); 1172 struct mdiobb_ctrl ctrl; 1173 void *addr; 1174 }; 1175 1176 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1177 { 1178 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1179 u32 pir; 1180 1181 if (bitbang->set_gate) 1182 bitbang->set_gate(bitbang->addr); 1183 1184 pir = ioread32(bitbang->addr); 1185 if (set) 1186 pir |= mask; 1187 else 1188 pir &= ~mask; 1189 iowrite32(pir, bitbang->addr); 1190 } 1191 1192 /* Data I/O pin control */ 1193 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1194 { 1195 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1196 } 1197 1198 /* Set bit data*/ 1199 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1200 { 1201 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1202 } 1203 1204 /* Get bit data*/ 1205 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1206 { 1207 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1208 1209 if (bitbang->set_gate) 1210 bitbang->set_gate(bitbang->addr); 1211 1212 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1213 } 1214 1215 /* MDC pin control */ 1216 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1217 { 1218 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1219 } 1220 1221 /* mdio bus control struct */ 1222 static const struct mdiobb_ops bb_ops = { 1223 .owner = THIS_MODULE, 1224 .set_mdc = sh_mdc_ctrl, 1225 .set_mdio_dir = sh_mmd_ctrl, 1226 .set_mdio_data = sh_set_mdio, 1227 .get_mdio_data = sh_get_mdio, 1228 }; 1229 1230 /* free Tx skb function */ 1231 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1232 { 1233 struct sh_eth_private *mdp = netdev_priv(ndev); 1234 struct sh_eth_txdesc *txdesc; 1235 int free_num = 0; 1236 int entry; 1237 bool sent; 1238 1239 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1240 entry = mdp->dirty_tx % mdp->num_tx_ring; 1241 txdesc = &mdp->tx_ring[entry]; 1242 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1243 if (sent_only && !sent) 1244 break; 1245 /* TACT bit must be checked before all the following reads */ 1246 dma_rmb(); 1247 netif_info(mdp, tx_done, ndev, 1248 "tx entry %d status 0x%08x\n", 1249 entry, le32_to_cpu(txdesc->status)); 1250 /* Free the original skb. */ 1251 if (mdp->tx_skbuff[entry]) { 1252 dma_unmap_single(&mdp->pdev->dev, 1253 le32_to_cpu(txdesc->addr), 1254 le32_to_cpu(txdesc->len) >> 16, 1255 DMA_TO_DEVICE); 1256 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1257 mdp->tx_skbuff[entry] = NULL; 1258 free_num++; 1259 } 1260 txdesc->status = cpu_to_le32(TD_TFP); 1261 if (entry >= mdp->num_tx_ring - 1) 1262 txdesc->status |= cpu_to_le32(TD_TDLE); 1263 1264 if (sent) { 1265 ndev->stats.tx_packets++; 1266 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1267 } 1268 } 1269 return free_num; 1270 } 1271 1272 /* free skb and descriptor buffer */ 1273 static void sh_eth_ring_free(struct net_device *ndev) 1274 { 1275 struct sh_eth_private *mdp = netdev_priv(ndev); 1276 int ringsize, i; 1277 1278 if (mdp->rx_ring) { 1279 for (i = 0; i < mdp->num_rx_ring; i++) { 1280 if (mdp->rx_skbuff[i]) { 1281 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1282 1283 dma_unmap_single(&mdp->pdev->dev, 1284 le32_to_cpu(rxdesc->addr), 1285 ALIGN(mdp->rx_buf_sz, 32), 1286 DMA_FROM_DEVICE); 1287 } 1288 } 1289 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1290 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1291 mdp->rx_desc_dma); 1292 mdp->rx_ring = NULL; 1293 } 1294 1295 /* Free Rx skb ringbuffer */ 1296 if (mdp->rx_skbuff) { 1297 for (i = 0; i < mdp->num_rx_ring; i++) 1298 dev_kfree_skb(mdp->rx_skbuff[i]); 1299 } 1300 kfree(mdp->rx_skbuff); 1301 mdp->rx_skbuff = NULL; 1302 1303 if (mdp->tx_ring) { 1304 sh_eth_tx_free(ndev, false); 1305 1306 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1307 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1308 mdp->tx_desc_dma); 1309 mdp->tx_ring = NULL; 1310 } 1311 1312 /* Free Tx skb ringbuffer */ 1313 kfree(mdp->tx_skbuff); 1314 mdp->tx_skbuff = NULL; 1315 } 1316 1317 /* format skb and descriptor buffer */ 1318 static void sh_eth_ring_format(struct net_device *ndev) 1319 { 1320 struct sh_eth_private *mdp = netdev_priv(ndev); 1321 int i; 1322 struct sk_buff *skb; 1323 struct sh_eth_rxdesc *rxdesc = NULL; 1324 struct sh_eth_txdesc *txdesc = NULL; 1325 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1326 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1327 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1328 dma_addr_t dma_addr; 1329 u32 buf_len; 1330 1331 mdp->cur_rx = 0; 1332 mdp->cur_tx = 0; 1333 mdp->dirty_rx = 0; 1334 mdp->dirty_tx = 0; 1335 1336 memset(mdp->rx_ring, 0, rx_ringsize); 1337 1338 /* build Rx ring buffer */ 1339 for (i = 0; i < mdp->num_rx_ring; i++) { 1340 /* skb */ 1341 mdp->rx_skbuff[i] = NULL; 1342 skb = netdev_alloc_skb(ndev, skbuff_size); 1343 if (skb == NULL) 1344 break; 1345 sh_eth_set_receive_align(skb); 1346 1347 /* The size of the buffer is a multiple of 32 bytes. */ 1348 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1349 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1350 DMA_FROM_DEVICE); 1351 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1352 kfree_skb(skb); 1353 break; 1354 } 1355 mdp->rx_skbuff[i] = skb; 1356 1357 /* RX descriptor */ 1358 rxdesc = &mdp->rx_ring[i]; 1359 rxdesc->len = cpu_to_le32(buf_len << 16); 1360 rxdesc->addr = cpu_to_le32(dma_addr); 1361 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1362 1363 /* Rx descriptor address set */ 1364 if (i == 0) { 1365 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1366 if (mdp->cd->xdfar_rw) 1367 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1368 } 1369 } 1370 1371 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1372 1373 /* Mark the last entry as wrapping the ring. */ 1374 if (rxdesc) 1375 rxdesc->status |= cpu_to_le32(RD_RDLE); 1376 1377 memset(mdp->tx_ring, 0, tx_ringsize); 1378 1379 /* build Tx ring buffer */ 1380 for (i = 0; i < mdp->num_tx_ring; i++) { 1381 mdp->tx_skbuff[i] = NULL; 1382 txdesc = &mdp->tx_ring[i]; 1383 txdesc->status = cpu_to_le32(TD_TFP); 1384 txdesc->len = cpu_to_le32(0); 1385 if (i == 0) { 1386 /* Tx descriptor address set */ 1387 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1388 if (mdp->cd->xdfar_rw) 1389 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1390 } 1391 } 1392 1393 txdesc->status |= cpu_to_le32(TD_TDLE); 1394 } 1395 1396 /* Get skb and descriptor buffer */ 1397 static int sh_eth_ring_init(struct net_device *ndev) 1398 { 1399 struct sh_eth_private *mdp = netdev_priv(ndev); 1400 int rx_ringsize, tx_ringsize; 1401 1402 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1403 * card needs room to do 8 byte alignment, +2 so we can reserve 1404 * the first 2 bytes, and +16 gets room for the status word from the 1405 * card. 1406 */ 1407 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1408 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1409 if (mdp->cd->rpadir) 1410 mdp->rx_buf_sz += NET_IP_ALIGN; 1411 1412 /* Allocate RX and TX skb rings */ 1413 mdp->rx_skbuff = kzalloc_objs(*mdp->rx_skbuff, mdp->num_rx_ring); 1414 if (!mdp->rx_skbuff) 1415 return -ENOMEM; 1416 1417 mdp->tx_skbuff = kzalloc_objs(*mdp->tx_skbuff, mdp->num_tx_ring); 1418 if (!mdp->tx_skbuff) 1419 goto ring_free; 1420 1421 /* Allocate all Rx descriptors. */ 1422 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1423 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1424 &mdp->rx_desc_dma, GFP_KERNEL); 1425 if (!mdp->rx_ring) 1426 goto ring_free; 1427 1428 mdp->dirty_rx = 0; 1429 1430 /* Allocate all Tx descriptors. */ 1431 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1432 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1433 &mdp->tx_desc_dma, GFP_KERNEL); 1434 if (!mdp->tx_ring) 1435 goto ring_free; 1436 return 0; 1437 1438 ring_free: 1439 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1440 sh_eth_ring_free(ndev); 1441 1442 return -ENOMEM; 1443 } 1444 1445 static int sh_eth_dev_init(struct net_device *ndev) 1446 { 1447 struct sh_eth_private *mdp = netdev_priv(ndev); 1448 int ret; 1449 1450 /* Soft Reset */ 1451 ret = mdp->cd->soft_reset(ndev); 1452 if (ret) 1453 return ret; 1454 1455 if (mdp->cd->rmiimode) 1456 sh_eth_write(ndev, 0x1, RMIIMODE); 1457 1458 /* Descriptor format */ 1459 sh_eth_ring_format(ndev); 1460 if (mdp->cd->rpadir) 1461 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR); 1462 1463 /* all sh_eth int mask */ 1464 sh_eth_write(ndev, 0, EESIPR); 1465 1466 #if defined(__LITTLE_ENDIAN) 1467 if (mdp->cd->hw_swap) 1468 sh_eth_write(ndev, EDMR_EL, EDMR); 1469 else 1470 #endif 1471 sh_eth_write(ndev, 0, EDMR); 1472 1473 /* FIFO size set */ 1474 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1475 sh_eth_write(ndev, 0, TFTR); 1476 1477 /* Frame recv control (enable multiple-packets per rx irq) */ 1478 sh_eth_write(ndev, RMCR_RNC, RMCR); 1479 1480 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1481 1482 /* DMA transfer burst mode */ 1483 if (mdp->cd->nbst) 1484 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST); 1485 1486 /* Burst cycle count upper-limit */ 1487 if (mdp->cd->bculr) 1488 sh_eth_write(ndev, 0x800, BCULR); 1489 1490 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1491 1492 if (!mdp->cd->no_trimd) 1493 sh_eth_write(ndev, 0, TRIMD); 1494 1495 /* Recv frame limit set register */ 1496 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1497 RFLR); 1498 1499 sh_eth_modify(ndev, EESR, 0, 0); 1500 mdp->irq_enabled = true; 1501 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1502 1503 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 1504 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1505 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 1506 ECMR_TE | ECMR_RE, ECMR); 1507 1508 if (mdp->cd->set_rate) 1509 mdp->cd->set_rate(ndev); 1510 1511 /* E-MAC Status Register clear */ 1512 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1513 1514 /* E-MAC Interrupt Enable register */ 1515 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1516 1517 /* Set MAC address */ 1518 update_mac_address(ndev); 1519 1520 /* mask reset */ 1521 if (mdp->cd->apr) 1522 sh_eth_write(ndev, 1, APR); 1523 if (mdp->cd->mpr) 1524 sh_eth_write(ndev, 1, MPR); 1525 if (mdp->cd->tpauser) 1526 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1527 1528 /* Setting the Rx mode will start the Rx process. */ 1529 sh_eth_write(ndev, EDRRR_R, EDRRR); 1530 1531 return ret; 1532 } 1533 1534 static void sh_eth_dev_exit(struct net_device *ndev) 1535 { 1536 struct sh_eth_private *mdp = netdev_priv(ndev); 1537 int i; 1538 1539 /* Deactivate all TX descriptors, so DMA should stop at next 1540 * packet boundary if it's currently running 1541 */ 1542 for (i = 0; i < mdp->num_tx_ring; i++) 1543 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1544 1545 /* Disable TX FIFO egress to MAC */ 1546 sh_eth_rcv_snd_disable(ndev); 1547 1548 /* Stop RX DMA at next packet boundary */ 1549 sh_eth_write(ndev, 0, EDRRR); 1550 1551 /* Aside from TX DMA, we can't tell when the hardware is 1552 * really stopped, so we need to reset to make sure. 1553 * Before doing that, wait for long enough to *probably* 1554 * finish transmitting the last packet and poll stats. 1555 */ 1556 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1557 sh_eth_get_stats(ndev); 1558 mdp->cd->soft_reset(ndev); 1559 1560 /* Set the RMII mode again if required */ 1561 if (mdp->cd->rmiimode) 1562 sh_eth_write(ndev, 0x1, RMIIMODE); 1563 1564 /* Set MAC address again */ 1565 update_mac_address(ndev); 1566 } 1567 1568 static void sh_eth_rx_csum(struct sk_buff *skb) 1569 { 1570 u8 *hw_csum; 1571 1572 /* The hardware checksum is 2 bytes appended to packet data */ 1573 if (unlikely(skb->len < sizeof(__sum16))) 1574 return; 1575 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 1576 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 1577 skb->ip_summed = CHECKSUM_COMPLETE; 1578 skb_trim(skb, skb->len - sizeof(__sum16)); 1579 } 1580 1581 /* Packet receive function */ 1582 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1583 { 1584 struct sh_eth_private *mdp = netdev_priv(ndev); 1585 struct sh_eth_rxdesc *rxdesc; 1586 1587 int entry = mdp->cur_rx % mdp->num_rx_ring; 1588 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1589 int limit; 1590 struct sk_buff *skb; 1591 u32 desc_status; 1592 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1593 dma_addr_t dma_addr; 1594 u16 pkt_len; 1595 u32 buf_len; 1596 1597 boguscnt = min(boguscnt, *quota); 1598 limit = boguscnt; 1599 rxdesc = &mdp->rx_ring[entry]; 1600 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1601 /* RACT bit must be checked before all the following reads */ 1602 dma_rmb(); 1603 desc_status = le32_to_cpu(rxdesc->status); 1604 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1605 1606 if (--boguscnt < 0) 1607 break; 1608 1609 netif_info(mdp, rx_status, ndev, 1610 "rx entry %d status 0x%08x len %d\n", 1611 entry, desc_status, pkt_len); 1612 1613 if (!(desc_status & RDFEND)) 1614 ndev->stats.rx_length_errors++; 1615 1616 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1617 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1618 * bit 0. However, in case of the R8A7740 and R7S72100 1619 * the RFS bits are from bit 25 to bit 16. So, the 1620 * driver needs right shifting by 16. 1621 */ 1622 if (mdp->cd->csmr) 1623 desc_status >>= 16; 1624 1625 skb = mdp->rx_skbuff[entry]; 1626 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1627 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1628 ndev->stats.rx_errors++; 1629 if (desc_status & RD_RFS1) 1630 ndev->stats.rx_crc_errors++; 1631 if (desc_status & RD_RFS2) 1632 ndev->stats.rx_frame_errors++; 1633 if (desc_status & RD_RFS3) 1634 ndev->stats.rx_length_errors++; 1635 if (desc_status & RD_RFS4) 1636 ndev->stats.rx_length_errors++; 1637 if (desc_status & RD_RFS6) 1638 ndev->stats.rx_missed_errors++; 1639 if (desc_status & RD_RFS10) 1640 ndev->stats.rx_over_errors++; 1641 } else if (skb) { 1642 dma_addr = le32_to_cpu(rxdesc->addr); 1643 if (!mdp->cd->hw_swap) 1644 sh_eth_soft_swap( 1645 phys_to_virt(ALIGN(dma_addr, 4)), 1646 pkt_len + 2); 1647 mdp->rx_skbuff[entry] = NULL; 1648 if (mdp->cd->rpadir) 1649 skb_reserve(skb, NET_IP_ALIGN); 1650 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1651 ALIGN(mdp->rx_buf_sz, 32), 1652 DMA_FROM_DEVICE); 1653 skb_put(skb, pkt_len); 1654 skb->protocol = eth_type_trans(skb, ndev); 1655 if (ndev->features & NETIF_F_RXCSUM) 1656 sh_eth_rx_csum(skb); 1657 netif_receive_skb(skb); 1658 ndev->stats.rx_packets++; 1659 ndev->stats.rx_bytes += pkt_len; 1660 if (desc_status & RD_RFS8) 1661 ndev->stats.multicast++; 1662 } 1663 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1664 rxdesc = &mdp->rx_ring[entry]; 1665 } 1666 1667 /* Refill the Rx ring buffers. */ 1668 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1669 entry = mdp->dirty_rx % mdp->num_rx_ring; 1670 rxdesc = &mdp->rx_ring[entry]; 1671 /* The size of the buffer is 32 byte boundary. */ 1672 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1673 rxdesc->len = cpu_to_le32(buf_len << 16); 1674 1675 if (mdp->rx_skbuff[entry] == NULL) { 1676 skb = netdev_alloc_skb(ndev, skbuff_size); 1677 if (skb == NULL) 1678 break; /* Better luck next round. */ 1679 sh_eth_set_receive_align(skb); 1680 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1681 buf_len, DMA_FROM_DEVICE); 1682 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1683 kfree_skb(skb); 1684 break; 1685 } 1686 mdp->rx_skbuff[entry] = skb; 1687 1688 skb_checksum_none_assert(skb); 1689 rxdesc->addr = cpu_to_le32(dma_addr); 1690 } 1691 dma_wmb(); /* RACT bit must be set after all the above writes */ 1692 if (entry >= mdp->num_rx_ring - 1) 1693 rxdesc->status |= 1694 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1695 else 1696 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1697 } 1698 1699 /* Restart Rx engine if stopped. */ 1700 /* If we don't need to check status, don't. -KDU */ 1701 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1702 /* fix the values for the next receiving if RDE is set */ 1703 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) { 1704 u32 count = (sh_eth_read(ndev, RDFAR) - 1705 sh_eth_read(ndev, RDLAR)) >> 4; 1706 1707 mdp->cur_rx = count; 1708 mdp->dirty_rx = count; 1709 } 1710 sh_eth_write(ndev, EDRRR_R, EDRRR); 1711 } 1712 1713 *quota -= limit - boguscnt - 1; 1714 1715 return *quota <= 0; 1716 } 1717 1718 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1719 { 1720 /* disable tx and rx */ 1721 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1722 } 1723 1724 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1725 { 1726 /* enable tx and rx */ 1727 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1728 } 1729 1730 /* E-MAC interrupt handler */ 1731 static void sh_eth_emac_interrupt(struct net_device *ndev) 1732 { 1733 struct sh_eth_private *mdp = netdev_priv(ndev); 1734 u32 felic_stat; 1735 u32 link_stat; 1736 1737 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1738 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1739 if (felic_stat & ECSR_ICD) 1740 ndev->stats.tx_carrier_errors++; 1741 if (felic_stat & ECSR_MPD) 1742 pm_wakeup_event(&mdp->pdev->dev, 0); 1743 if (felic_stat & ECSR_LCHNG) { 1744 /* Link Changed */ 1745 if (mdp->cd->no_psr || mdp->no_ether_link) 1746 return; 1747 link_stat = sh_eth_read(ndev, PSR); 1748 if (mdp->ether_link_active_low) 1749 link_stat = ~link_stat; 1750 if (!(link_stat & PSR_LMON)) { 1751 sh_eth_rcv_snd_disable(ndev); 1752 } else { 1753 /* Link Up */ 1754 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1755 /* clear int */ 1756 sh_eth_modify(ndev, ECSR, 0, 0); 1757 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1758 /* enable tx and rx */ 1759 sh_eth_rcv_snd_enable(ndev); 1760 } 1761 } 1762 } 1763 1764 /* error control function */ 1765 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1766 { 1767 struct sh_eth_private *mdp = netdev_priv(ndev); 1768 u32 mask; 1769 1770 if (intr_status & EESR_TWB) { 1771 /* Unused write back interrupt */ 1772 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1773 ndev->stats.tx_aborted_errors++; 1774 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1775 } 1776 } 1777 1778 if (intr_status & EESR_RABT) { 1779 /* Receive Abort int */ 1780 if (intr_status & EESR_RFRMER) { 1781 /* Receive Frame Overflow int */ 1782 ndev->stats.rx_frame_errors++; 1783 } 1784 } 1785 1786 if (intr_status & EESR_TDE) { 1787 /* Transmit Descriptor Empty int */ 1788 ndev->stats.tx_fifo_errors++; 1789 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1790 } 1791 1792 if (intr_status & EESR_TFE) { 1793 /* FIFO under flow */ 1794 ndev->stats.tx_fifo_errors++; 1795 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1796 } 1797 1798 if (intr_status & EESR_RDE) { 1799 /* Receive Descriptor Empty int */ 1800 ndev->stats.rx_over_errors++; 1801 } 1802 1803 if (intr_status & EESR_RFE) { 1804 /* Receive FIFO Overflow int */ 1805 ndev->stats.rx_fifo_errors++; 1806 } 1807 1808 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1809 /* Address Error */ 1810 ndev->stats.tx_fifo_errors++; 1811 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1812 } 1813 1814 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1815 if (mdp->cd->no_ade) 1816 mask &= ~EESR_ADE; 1817 if (intr_status & mask) { 1818 /* Tx error */ 1819 u32 edtrr = sh_eth_read(ndev, EDTRR); 1820 1821 /* dmesg */ 1822 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1823 intr_status, mdp->cur_tx, mdp->dirty_tx, 1824 (u32)ndev->state, edtrr); 1825 /* dirty buffer free */ 1826 sh_eth_tx_free(ndev, true); 1827 1828 /* SH7712 BUG */ 1829 if (edtrr ^ mdp->cd->edtrr_trns) { 1830 /* tx dma start */ 1831 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 1832 } 1833 /* wakeup */ 1834 netif_wake_queue(ndev); 1835 } 1836 } 1837 1838 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1839 { 1840 struct net_device *ndev = netdev; 1841 struct sh_eth_private *mdp = netdev_priv(ndev); 1842 struct sh_eth_cpu_data *cd = mdp->cd; 1843 irqreturn_t ret = IRQ_NONE; 1844 u32 intr_status, intr_enable; 1845 1846 spin_lock(&mdp->lock); 1847 1848 /* Get interrupt status */ 1849 intr_status = sh_eth_read(ndev, EESR); 1850 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1851 * enabled since it's the one that comes thru regardless of the mask, 1852 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1853 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1854 * bit... 1855 */ 1856 intr_enable = sh_eth_read(ndev, EESIPR); 1857 intr_status &= intr_enable | EESIPR_ECIIP; 1858 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1859 cd->eesr_err_check)) 1860 ret = IRQ_HANDLED; 1861 else 1862 goto out; 1863 1864 if (unlikely(!mdp->irq_enabled)) { 1865 sh_eth_write(ndev, 0, EESIPR); 1866 goto out; 1867 } 1868 1869 if (intr_status & EESR_RX_CHECK) { 1870 if (napi_schedule_prep(&mdp->napi)) { 1871 /* Mask Rx interrupts */ 1872 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1873 EESIPR); 1874 __napi_schedule(&mdp->napi); 1875 } else { 1876 netdev_warn(ndev, 1877 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1878 intr_status, intr_enable); 1879 } 1880 } 1881 1882 /* Tx Check */ 1883 if (intr_status & cd->tx_check) { 1884 /* Clear Tx interrupts */ 1885 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1886 1887 sh_eth_tx_free(ndev, true); 1888 netif_wake_queue(ndev); 1889 } 1890 1891 /* E-MAC interrupt */ 1892 if (intr_status & EESR_ECI) 1893 sh_eth_emac_interrupt(ndev); 1894 1895 if (intr_status & cd->eesr_err_check) { 1896 /* Clear error interrupts */ 1897 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1898 1899 sh_eth_error(ndev, intr_status); 1900 } 1901 1902 out: 1903 spin_unlock(&mdp->lock); 1904 1905 return ret; 1906 } 1907 1908 static int sh_eth_poll(struct napi_struct *napi, int budget) 1909 { 1910 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1911 napi); 1912 struct net_device *ndev = napi->dev; 1913 int quota = budget; 1914 u32 intr_status; 1915 1916 for (;;) { 1917 intr_status = sh_eth_read(ndev, EESR); 1918 if (!(intr_status & EESR_RX_CHECK)) 1919 break; 1920 /* Clear Rx interrupts */ 1921 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1922 1923 if (sh_eth_rx(ndev, intr_status, "a)) 1924 goto out; 1925 } 1926 1927 napi_complete(napi); 1928 1929 /* Reenable Rx interrupts */ 1930 if (mdp->irq_enabled) 1931 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1932 out: 1933 return budget - quota; 1934 } 1935 1936 /* PHY state control function */ 1937 static void sh_eth_adjust_link(struct net_device *ndev) 1938 { 1939 struct sh_eth_private *mdp = netdev_priv(ndev); 1940 struct phy_device *phydev = ndev->phydev; 1941 unsigned long flags; 1942 int new_state = 0; 1943 1944 spin_lock_irqsave(&mdp->lock, flags); 1945 1946 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1947 if (mdp->cd->no_psr || mdp->no_ether_link) 1948 sh_eth_rcv_snd_disable(ndev); 1949 1950 if (phydev->link) { 1951 if (phydev->duplex != mdp->duplex) { 1952 new_state = 1; 1953 mdp->duplex = phydev->duplex; 1954 if (mdp->cd->set_duplex) 1955 mdp->cd->set_duplex(ndev); 1956 } 1957 1958 if (phydev->speed != mdp->speed) { 1959 new_state = 1; 1960 mdp->speed = phydev->speed; 1961 if (mdp->cd->set_rate) 1962 mdp->cd->set_rate(ndev); 1963 } 1964 if (!mdp->link) { 1965 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1966 new_state = 1; 1967 mdp->link = phydev->link; 1968 } 1969 } else if (mdp->link) { 1970 new_state = 1; 1971 mdp->link = 0; 1972 mdp->speed = 0; 1973 mdp->duplex = -1; 1974 } 1975 1976 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1977 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link) 1978 sh_eth_rcv_snd_enable(ndev); 1979 1980 spin_unlock_irqrestore(&mdp->lock, flags); 1981 1982 if (new_state && netif_msg_link(mdp)) 1983 phy_print_status(phydev); 1984 } 1985 1986 /* PHY init function */ 1987 static int sh_eth_phy_init(struct net_device *ndev) 1988 { 1989 struct device_node *np = ndev->dev.parent->of_node; 1990 struct sh_eth_private *mdp = netdev_priv(ndev); 1991 struct phy_device *phydev; 1992 1993 mdp->link = 0; 1994 mdp->speed = 0; 1995 mdp->duplex = -1; 1996 1997 /* Try connect to PHY */ 1998 if (np) { 1999 struct device_node *pn; 2000 2001 pn = of_parse_phandle(np, "phy-handle", 0); 2002 phydev = of_phy_connect(ndev, pn, 2003 sh_eth_adjust_link, 0, 2004 mdp->phy_interface); 2005 2006 of_node_put(pn); 2007 if (!phydev) 2008 phydev = ERR_PTR(-ENOENT); 2009 } else { 2010 char phy_id[MII_BUS_ID_SIZE + 3]; 2011 2012 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2013 mdp->mii_bus->id, mdp->phy_id); 2014 2015 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 2016 mdp->phy_interface); 2017 } 2018 2019 if (IS_ERR(phydev)) { 2020 netdev_err(ndev, "failed to connect PHY\n"); 2021 return PTR_ERR(phydev); 2022 } 2023 2024 /* mask with MAC supported features */ 2025 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) 2026 phy_set_max_speed(phydev, SPEED_100); 2027 2028 phy_attached_info(phydev); 2029 2030 return 0; 2031 } 2032 2033 /* PHY control start function */ 2034 static int sh_eth_phy_start(struct net_device *ndev) 2035 { 2036 int ret; 2037 2038 ret = sh_eth_phy_init(ndev); 2039 if (ret) 2040 return ret; 2041 2042 phy_start(ndev->phydev); 2043 2044 return 0; 2045 } 2046 2047 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 2048 * version must be bumped as well. Just adding registers up to that 2049 * limit is fine, as long as the existing register indices don't 2050 * change. 2051 */ 2052 #define SH_ETH_REG_DUMP_VERSION 1 2053 #define SH_ETH_REG_DUMP_MAX_REGS 256 2054 2055 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 2056 { 2057 struct sh_eth_private *mdp = netdev_priv(ndev); 2058 struct sh_eth_cpu_data *cd = mdp->cd; 2059 u32 *valid_map; 2060 size_t len; 2061 2062 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 2063 2064 /* Dump starts with a bitmap that tells ethtool which 2065 * registers are defined for this chip. 2066 */ 2067 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 2068 if (buf) { 2069 valid_map = buf; 2070 buf += len; 2071 } else { 2072 valid_map = NULL; 2073 } 2074 2075 /* Add a register to the dump, if it has a defined offset. 2076 * This automatically skips most undefined registers, but for 2077 * some it is also necessary to check a capability flag in 2078 * struct sh_eth_cpu_data. 2079 */ 2080 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2081 #define add_reg_from(reg, read_expr) do { \ 2082 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2083 if (buf) { \ 2084 mark_reg_valid(reg); \ 2085 *buf++ = read_expr; \ 2086 } \ 2087 ++len; \ 2088 } \ 2089 } while (0) 2090 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2091 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2092 2093 add_reg(EDSR); 2094 add_reg(EDMR); 2095 add_reg(EDTRR); 2096 add_reg(EDRRR); 2097 add_reg(EESR); 2098 add_reg(EESIPR); 2099 add_reg(TDLAR); 2100 if (!cd->no_xdfar) 2101 add_reg(TDFAR); 2102 add_reg(TDFXR); 2103 add_reg(TDFFR); 2104 add_reg(RDLAR); 2105 if (!cd->no_xdfar) 2106 add_reg(RDFAR); 2107 add_reg(RDFXR); 2108 add_reg(RDFFR); 2109 add_reg(TRSCER); 2110 add_reg(RMFCR); 2111 add_reg(TFTR); 2112 add_reg(FDR); 2113 add_reg(RMCR); 2114 add_reg(TFUCR); 2115 add_reg(RFOCR); 2116 if (cd->rmiimode) 2117 add_reg(RMIIMODE); 2118 add_reg(FCFTR); 2119 if (cd->rpadir) 2120 add_reg(RPADIR); 2121 if (!cd->no_trimd) 2122 add_reg(TRIMD); 2123 add_reg(ECMR); 2124 add_reg(ECSR); 2125 add_reg(ECSIPR); 2126 add_reg(PIR); 2127 if (!cd->no_psr) 2128 add_reg(PSR); 2129 add_reg(RDMLR); 2130 add_reg(RFLR); 2131 add_reg(IPGR); 2132 if (cd->apr) 2133 add_reg(APR); 2134 if (cd->mpr) 2135 add_reg(MPR); 2136 add_reg(RFCR); 2137 add_reg(RFCF); 2138 if (cd->tpauser) 2139 add_reg(TPAUSER); 2140 add_reg(TPAUSECR); 2141 if (cd->gecmr) 2142 add_reg(GECMR); 2143 if (cd->bculr) 2144 add_reg(BCULR); 2145 add_reg(MAHR); 2146 add_reg(MALR); 2147 if (!cd->no_tx_cntrs) { 2148 add_reg(TROCR); 2149 add_reg(CDCR); 2150 add_reg(LCCR); 2151 add_reg(CNDCR); 2152 } 2153 add_reg(CEFCR); 2154 add_reg(FRECR); 2155 add_reg(TSFRCR); 2156 add_reg(TLFRCR); 2157 if (cd->cexcr) { 2158 add_reg(CERCR); 2159 add_reg(CEECR); 2160 } 2161 add_reg(MAFCR); 2162 if (cd->rtrate) 2163 add_reg(RTRATE); 2164 if (cd->csmr) 2165 add_reg(CSMR); 2166 if (cd->select_mii) 2167 add_reg(RMII_MII); 2168 if (cd->tsu) { 2169 add_tsu_reg(ARSTR); 2170 add_tsu_reg(TSU_CTRST); 2171 if (cd->dual_port) { 2172 add_tsu_reg(TSU_FWEN0); 2173 add_tsu_reg(TSU_FWEN1); 2174 add_tsu_reg(TSU_FCM); 2175 add_tsu_reg(TSU_BSYSL0); 2176 add_tsu_reg(TSU_BSYSL1); 2177 add_tsu_reg(TSU_PRISL0); 2178 add_tsu_reg(TSU_PRISL1); 2179 add_tsu_reg(TSU_FWSL0); 2180 add_tsu_reg(TSU_FWSL1); 2181 } 2182 add_tsu_reg(TSU_FWSLC); 2183 if (cd->dual_port) { 2184 add_tsu_reg(TSU_QTAGM0); 2185 add_tsu_reg(TSU_QTAGM1); 2186 add_tsu_reg(TSU_FWSR); 2187 add_tsu_reg(TSU_FWINMK); 2188 add_tsu_reg(TSU_ADQT0); 2189 add_tsu_reg(TSU_ADQT1); 2190 add_tsu_reg(TSU_VTAG0); 2191 add_tsu_reg(TSU_VTAG1); 2192 } 2193 add_tsu_reg(TSU_ADSBSY); 2194 add_tsu_reg(TSU_TEN); 2195 add_tsu_reg(TSU_POST1); 2196 add_tsu_reg(TSU_POST2); 2197 add_tsu_reg(TSU_POST3); 2198 add_tsu_reg(TSU_POST4); 2199 /* This is the start of a table, not just a single register. */ 2200 if (buf) { 2201 unsigned int i; 2202 2203 mark_reg_valid(TSU_ADRH0); 2204 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2205 *buf++ = ioread32(mdp->tsu_addr + 2206 mdp->reg_offset[TSU_ADRH0] + 2207 i * 4); 2208 } 2209 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2210 } 2211 2212 #undef mark_reg_valid 2213 #undef add_reg_from 2214 #undef add_reg 2215 #undef add_tsu_reg 2216 2217 return len * 4; 2218 } 2219 2220 static int sh_eth_get_regs_len(struct net_device *ndev) 2221 { 2222 return __sh_eth_get_regs(ndev, NULL); 2223 } 2224 2225 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2226 void *buf) 2227 { 2228 struct sh_eth_private *mdp = netdev_priv(ndev); 2229 2230 regs->version = SH_ETH_REG_DUMP_VERSION; 2231 2232 pm_runtime_get_sync(&mdp->pdev->dev); 2233 __sh_eth_get_regs(ndev, buf); 2234 pm_runtime_put(&mdp->pdev->dev); 2235 } 2236 2237 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2238 { 2239 struct sh_eth_private *mdp = netdev_priv(ndev); 2240 return mdp->msg_enable; 2241 } 2242 2243 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2244 { 2245 struct sh_eth_private *mdp = netdev_priv(ndev); 2246 mdp->msg_enable = value; 2247 } 2248 2249 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2250 "rx_current", "tx_current", 2251 "rx_dirty", "tx_dirty", 2252 }; 2253 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2254 2255 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2256 { 2257 switch (sset) { 2258 case ETH_SS_STATS: 2259 return SH_ETH_STATS_LEN; 2260 default: 2261 return -EOPNOTSUPP; 2262 } 2263 } 2264 2265 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2266 struct ethtool_stats *stats, u64 *data) 2267 { 2268 struct sh_eth_private *mdp = netdev_priv(ndev); 2269 int i = 0; 2270 2271 /* device-specific stats */ 2272 data[i++] = mdp->cur_rx; 2273 data[i++] = mdp->cur_tx; 2274 data[i++] = mdp->dirty_rx; 2275 data[i++] = mdp->dirty_tx; 2276 } 2277 2278 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2279 { 2280 switch (stringset) { 2281 case ETH_SS_STATS: 2282 memcpy(data, sh_eth_gstrings_stats, 2283 sizeof(sh_eth_gstrings_stats)); 2284 break; 2285 } 2286 } 2287 2288 static void sh_eth_get_ringparam(struct net_device *ndev, 2289 struct ethtool_ringparam *ring, 2290 struct kernel_ethtool_ringparam *kernel_ring, 2291 struct netlink_ext_ack *extack) 2292 { 2293 struct sh_eth_private *mdp = netdev_priv(ndev); 2294 2295 ring->rx_max_pending = RX_RING_MAX; 2296 ring->tx_max_pending = TX_RING_MAX; 2297 ring->rx_pending = mdp->num_rx_ring; 2298 ring->tx_pending = mdp->num_tx_ring; 2299 } 2300 2301 static int sh_eth_set_ringparam(struct net_device *ndev, 2302 struct ethtool_ringparam *ring, 2303 struct kernel_ethtool_ringparam *kernel_ring, 2304 struct netlink_ext_ack *extack) 2305 { 2306 struct sh_eth_private *mdp = netdev_priv(ndev); 2307 int ret; 2308 2309 if (ring->tx_pending > TX_RING_MAX || 2310 ring->rx_pending > RX_RING_MAX || 2311 ring->tx_pending < TX_RING_MIN || 2312 ring->rx_pending < RX_RING_MIN) 2313 return -EINVAL; 2314 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2315 return -EINVAL; 2316 2317 if (netif_running(ndev)) { 2318 netif_device_detach(ndev); 2319 netif_tx_disable(ndev); 2320 2321 /* Serialise with the interrupt handler and NAPI, then 2322 * disable interrupts. We have to clear the 2323 * irq_enabled flag first to ensure that interrupts 2324 * won't be re-enabled. 2325 */ 2326 mdp->irq_enabled = false; 2327 synchronize_irq(ndev->irq); 2328 napi_synchronize(&mdp->napi); 2329 sh_eth_write(ndev, 0x0000, EESIPR); 2330 2331 sh_eth_dev_exit(ndev); 2332 2333 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2334 sh_eth_ring_free(ndev); 2335 } 2336 2337 /* Set new parameters */ 2338 mdp->num_rx_ring = ring->rx_pending; 2339 mdp->num_tx_ring = ring->tx_pending; 2340 2341 if (netif_running(ndev)) { 2342 ret = sh_eth_ring_init(ndev); 2343 if (ret < 0) { 2344 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2345 __func__); 2346 return ret; 2347 } 2348 ret = sh_eth_dev_init(ndev); 2349 if (ret < 0) { 2350 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2351 __func__); 2352 return ret; 2353 } 2354 2355 netif_device_attach(ndev); 2356 } 2357 2358 return 0; 2359 } 2360 2361 #ifdef CONFIG_PM_SLEEP 2362 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2363 { 2364 struct sh_eth_private *mdp = netdev_priv(ndev); 2365 2366 wol->supported = 0; 2367 wol->wolopts = 0; 2368 2369 if (mdp->cd->magic) { 2370 wol->supported = WAKE_MAGIC; 2371 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2372 } 2373 } 2374 2375 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2376 { 2377 struct sh_eth_private *mdp = netdev_priv(ndev); 2378 2379 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2380 return -EOPNOTSUPP; 2381 2382 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2383 2384 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2385 2386 return 0; 2387 } 2388 #endif 2389 2390 static const struct ethtool_ops sh_eth_ethtool_ops = { 2391 .get_regs_len = sh_eth_get_regs_len, 2392 .get_regs = sh_eth_get_regs, 2393 .nway_reset = phy_ethtool_nway_reset, 2394 .get_msglevel = sh_eth_get_msglevel, 2395 .set_msglevel = sh_eth_set_msglevel, 2396 .get_link = ethtool_op_get_link, 2397 .get_strings = sh_eth_get_strings, 2398 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2399 .get_sset_count = sh_eth_get_sset_count, 2400 .get_ringparam = sh_eth_get_ringparam, 2401 .set_ringparam = sh_eth_set_ringparam, 2402 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2403 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2404 #ifdef CONFIG_PM_SLEEP 2405 .get_wol = sh_eth_get_wol, 2406 .set_wol = sh_eth_set_wol, 2407 #endif 2408 }; 2409 2410 /* network device open function */ 2411 static int sh_eth_open(struct net_device *ndev) 2412 { 2413 struct sh_eth_private *mdp = netdev_priv(ndev); 2414 int ret; 2415 2416 pm_runtime_get_sync(&mdp->pdev->dev); 2417 2418 napi_enable(&mdp->napi); 2419 2420 ret = request_irq(ndev->irq, sh_eth_interrupt, 2421 mdp->cd->irq_flags, ndev->name, ndev); 2422 if (ret) { 2423 netdev_err(ndev, "Can not assign IRQ number\n"); 2424 goto out_napi_off; 2425 } 2426 2427 /* Descriptor set */ 2428 ret = sh_eth_ring_init(ndev); 2429 if (ret) 2430 goto out_free_irq; 2431 2432 /* device init */ 2433 ret = sh_eth_dev_init(ndev); 2434 if (ret) 2435 goto out_free_irq; 2436 2437 /* PHY control start*/ 2438 ret = sh_eth_phy_start(ndev); 2439 if (ret) 2440 goto out_free_irq; 2441 2442 netif_start_queue(ndev); 2443 2444 mdp->is_opened = 1; 2445 2446 return ret; 2447 2448 out_free_irq: 2449 free_irq(ndev->irq, ndev); 2450 out_napi_off: 2451 napi_disable(&mdp->napi); 2452 pm_runtime_put(&mdp->pdev->dev); 2453 return ret; 2454 } 2455 2456 /* Timeout function */ 2457 static void sh_eth_tx_timeout(struct net_device *ndev, unsigned int txqueue) 2458 { 2459 struct sh_eth_private *mdp = netdev_priv(ndev); 2460 struct sh_eth_rxdesc *rxdesc; 2461 int i; 2462 2463 netif_stop_queue(ndev); 2464 2465 netif_err(mdp, timer, ndev, 2466 "transmit timed out, status %8.8x, resetting...\n", 2467 sh_eth_read(ndev, EESR)); 2468 2469 /* tx_errors count up */ 2470 ndev->stats.tx_errors++; 2471 2472 /* Free all the skbuffs in the Rx queue. */ 2473 for (i = 0; i < mdp->num_rx_ring; i++) { 2474 rxdesc = &mdp->rx_ring[i]; 2475 rxdesc->status = cpu_to_le32(0); 2476 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2477 dev_kfree_skb(mdp->rx_skbuff[i]); 2478 mdp->rx_skbuff[i] = NULL; 2479 } 2480 for (i = 0; i < mdp->num_tx_ring; i++) { 2481 dev_kfree_skb(mdp->tx_skbuff[i]); 2482 mdp->tx_skbuff[i] = NULL; 2483 } 2484 2485 /* device init */ 2486 sh_eth_dev_init(ndev); 2487 2488 netif_start_queue(ndev); 2489 } 2490 2491 /* Packet transmit function */ 2492 static netdev_tx_t sh_eth_start_xmit(struct sk_buff *skb, 2493 struct net_device *ndev) 2494 { 2495 struct sh_eth_private *mdp = netdev_priv(ndev); 2496 struct sh_eth_txdesc *txdesc; 2497 dma_addr_t dma_addr; 2498 u32 entry; 2499 unsigned long flags; 2500 2501 spin_lock_irqsave(&mdp->lock, flags); 2502 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2503 if (!sh_eth_tx_free(ndev, true)) { 2504 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2505 netif_stop_queue(ndev); 2506 spin_unlock_irqrestore(&mdp->lock, flags); 2507 return NETDEV_TX_BUSY; 2508 } 2509 } 2510 spin_unlock_irqrestore(&mdp->lock, flags); 2511 2512 if (skb_put_padto(skb, ETH_ZLEN)) 2513 return NETDEV_TX_OK; 2514 2515 entry = mdp->cur_tx % mdp->num_tx_ring; 2516 mdp->tx_skbuff[entry] = skb; 2517 txdesc = &mdp->tx_ring[entry]; 2518 /* soft swap. */ 2519 if (!mdp->cd->hw_swap) 2520 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2521 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2522 DMA_TO_DEVICE); 2523 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2524 kfree_skb(skb); 2525 return NETDEV_TX_OK; 2526 } 2527 txdesc->addr = cpu_to_le32(dma_addr); 2528 txdesc->len = cpu_to_le32(skb->len << 16); 2529 2530 dma_wmb(); /* TACT bit must be set after all the above writes */ 2531 if (entry >= mdp->num_tx_ring - 1) 2532 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2533 else 2534 txdesc->status |= cpu_to_le32(TD_TACT); 2535 2536 wmb(); /* cur_tx must be incremented after TACT bit was set */ 2537 mdp->cur_tx++; 2538 2539 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns)) 2540 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 2541 2542 return NETDEV_TX_OK; 2543 } 2544 2545 /* The statistics registers have write-clear behaviour, which means we 2546 * will lose any increment between the read and write. We mitigate 2547 * this by only clearing when we read a non-zero value, so we will 2548 * never falsely report a total of zero. 2549 */ 2550 static void 2551 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2552 { 2553 u32 delta = sh_eth_read(ndev, reg); 2554 2555 if (delta) { 2556 *stat += delta; 2557 sh_eth_write(ndev, 0, reg); 2558 } 2559 } 2560 2561 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2562 { 2563 struct sh_eth_private *mdp = netdev_priv(ndev); 2564 2565 if (mdp->cd->no_tx_cntrs) 2566 return &ndev->stats; 2567 2568 if (!mdp->is_opened) 2569 return &ndev->stats; 2570 2571 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2572 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2573 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2574 2575 if (mdp->cd->cexcr) { 2576 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2577 CERCR); 2578 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2579 CEECR); 2580 } else { 2581 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2582 CNDCR); 2583 } 2584 2585 return &ndev->stats; 2586 } 2587 2588 /* device close function */ 2589 static int sh_eth_close(struct net_device *ndev) 2590 { 2591 struct sh_eth_private *mdp = netdev_priv(ndev); 2592 2593 netif_stop_queue(ndev); 2594 2595 /* Serialise with the interrupt handler and NAPI, then disable 2596 * interrupts. We have to clear the irq_enabled flag first to 2597 * ensure that interrupts won't be re-enabled. 2598 */ 2599 mdp->irq_enabled = false; 2600 synchronize_irq(ndev->irq); 2601 napi_disable(&mdp->napi); 2602 sh_eth_write(ndev, 0x0000, EESIPR); 2603 2604 sh_eth_dev_exit(ndev); 2605 2606 /* PHY Disconnect */ 2607 if (ndev->phydev) { 2608 phy_stop(ndev->phydev); 2609 phy_disconnect(ndev->phydev); 2610 } 2611 2612 free_irq(ndev->irq, ndev); 2613 2614 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2615 sh_eth_ring_free(ndev); 2616 2617 mdp->is_opened = 0; 2618 2619 pm_runtime_put(&mdp->pdev->dev); 2620 2621 return 0; 2622 } 2623 2624 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2625 { 2626 if (netif_running(ndev)) 2627 return -EBUSY; 2628 2629 WRITE_ONCE(ndev->mtu, new_mtu); 2630 netdev_update_features(ndev); 2631 2632 return 0; 2633 } 2634 2635 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2636 static u32 sh_eth_tsu_get_post_mask(int entry) 2637 { 2638 return 0x0f << (28 - ((entry % 8) * 4)); 2639 } 2640 2641 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2642 { 2643 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2644 } 2645 2646 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2647 int entry) 2648 { 2649 struct sh_eth_private *mdp = netdev_priv(ndev); 2650 int reg = TSU_POST1 + entry / 8; 2651 u32 tmp; 2652 2653 tmp = sh_eth_tsu_read(mdp, reg); 2654 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg); 2655 } 2656 2657 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2658 int entry) 2659 { 2660 struct sh_eth_private *mdp = netdev_priv(ndev); 2661 int reg = TSU_POST1 + entry / 8; 2662 u32 post_mask, ref_mask, tmp; 2663 2664 post_mask = sh_eth_tsu_get_post_mask(entry); 2665 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2666 2667 tmp = sh_eth_tsu_read(mdp, reg); 2668 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg); 2669 2670 /* If other port enables, the function returns "true" */ 2671 return tmp & ref_mask; 2672 } 2673 2674 static int sh_eth_tsu_busy(struct net_device *ndev) 2675 { 2676 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2677 struct sh_eth_private *mdp = netdev_priv(ndev); 2678 2679 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2680 udelay(10); 2681 timeout--; 2682 if (timeout <= 0) { 2683 netdev_err(ndev, "%s: timeout\n", __func__); 2684 return -ETIMEDOUT; 2685 } 2686 } 2687 2688 return 0; 2689 } 2690 2691 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset, 2692 const u8 *addr) 2693 { 2694 struct sh_eth_private *mdp = netdev_priv(ndev); 2695 u32 val; 2696 2697 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2698 iowrite32(val, mdp->tsu_addr + offset); 2699 if (sh_eth_tsu_busy(ndev) < 0) 2700 return -EBUSY; 2701 2702 val = addr[4] << 8 | addr[5]; 2703 iowrite32(val, mdp->tsu_addr + offset + 4); 2704 if (sh_eth_tsu_busy(ndev) < 0) 2705 return -EBUSY; 2706 2707 return 0; 2708 } 2709 2710 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr) 2711 { 2712 struct sh_eth_private *mdp = netdev_priv(ndev); 2713 u32 val; 2714 2715 val = ioread32(mdp->tsu_addr + offset); 2716 addr[0] = (val >> 24) & 0xff; 2717 addr[1] = (val >> 16) & 0xff; 2718 addr[2] = (val >> 8) & 0xff; 2719 addr[3] = val & 0xff; 2720 val = ioread32(mdp->tsu_addr + offset + 4); 2721 addr[4] = (val >> 8) & 0xff; 2722 addr[5] = val & 0xff; 2723 } 2724 2725 2726 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2727 { 2728 struct sh_eth_private *mdp = netdev_priv(ndev); 2729 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2730 int i; 2731 u8 c_addr[ETH_ALEN]; 2732 2733 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2734 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr); 2735 if (ether_addr_equal(addr, c_addr)) 2736 return i; 2737 } 2738 2739 return -ENOENT; 2740 } 2741 2742 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2743 { 2744 u8 blank[ETH_ALEN]; 2745 int entry; 2746 2747 memset(blank, 0, sizeof(blank)); 2748 entry = sh_eth_tsu_find_entry(ndev, blank); 2749 return (entry < 0) ? -ENOMEM : entry; 2750 } 2751 2752 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2753 int entry) 2754 { 2755 struct sh_eth_private *mdp = netdev_priv(ndev); 2756 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2757 int ret; 2758 u8 blank[ETH_ALEN]; 2759 2760 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2761 ~(1 << (31 - entry)), TSU_TEN); 2762 2763 memset(blank, 0, sizeof(blank)); 2764 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2765 if (ret < 0) 2766 return ret; 2767 return 0; 2768 } 2769 2770 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2771 { 2772 struct sh_eth_private *mdp = netdev_priv(ndev); 2773 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2774 int i, ret; 2775 2776 if (!mdp->cd->tsu) 2777 return 0; 2778 2779 i = sh_eth_tsu_find_entry(ndev, addr); 2780 if (i < 0) { 2781 /* No entry found, create one */ 2782 i = sh_eth_tsu_find_empty(ndev); 2783 if (i < 0) 2784 return -ENOMEM; 2785 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2786 if (ret < 0) 2787 return ret; 2788 2789 /* Enable the entry */ 2790 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2791 (1 << (31 - i)), TSU_TEN); 2792 } 2793 2794 /* Entry found or created, enable POST */ 2795 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2796 2797 return 0; 2798 } 2799 2800 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2801 { 2802 struct sh_eth_private *mdp = netdev_priv(ndev); 2803 int i, ret; 2804 2805 if (!mdp->cd->tsu) 2806 return 0; 2807 2808 i = sh_eth_tsu_find_entry(ndev, addr); 2809 if (i) { 2810 /* Entry found */ 2811 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2812 goto done; 2813 2814 /* Disable the entry if both ports was disabled */ 2815 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2816 if (ret < 0) 2817 return ret; 2818 } 2819 done: 2820 return 0; 2821 } 2822 2823 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2824 { 2825 struct sh_eth_private *mdp = netdev_priv(ndev); 2826 int i, ret; 2827 2828 if (!mdp->cd->tsu) 2829 return 0; 2830 2831 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2832 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2833 continue; 2834 2835 /* Disable the entry if both ports was disabled */ 2836 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2837 if (ret < 0) 2838 return ret; 2839 } 2840 2841 return 0; 2842 } 2843 2844 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2845 { 2846 struct sh_eth_private *mdp = netdev_priv(ndev); 2847 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2848 u8 addr[ETH_ALEN]; 2849 int i; 2850 2851 if (!mdp->cd->tsu) 2852 return; 2853 2854 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2855 sh_eth_tsu_read_entry(ndev, reg_offset, addr); 2856 if (is_multicast_ether_addr(addr)) 2857 sh_eth_tsu_del_entry(ndev, addr); 2858 } 2859 } 2860 2861 /* Update promiscuous flag and multicast filter */ 2862 static void sh_eth_set_rx_mode(struct net_device *ndev) 2863 { 2864 struct sh_eth_private *mdp = netdev_priv(ndev); 2865 u32 ecmr_bits; 2866 int mcast_all = 0; 2867 unsigned long flags; 2868 2869 spin_lock_irqsave(&mdp->lock, flags); 2870 /* Initial condition is MCT = 1, PRM = 0. 2871 * Depending on ndev->flags, set PRM or clear MCT 2872 */ 2873 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2874 if (mdp->cd->tsu) 2875 ecmr_bits |= ECMR_MCT; 2876 2877 if (!(ndev->flags & IFF_MULTICAST)) { 2878 sh_eth_tsu_purge_mcast(ndev); 2879 mcast_all = 1; 2880 } 2881 if (ndev->flags & IFF_ALLMULTI) { 2882 sh_eth_tsu_purge_mcast(ndev); 2883 ecmr_bits &= ~ECMR_MCT; 2884 mcast_all = 1; 2885 } 2886 2887 if (ndev->flags & IFF_PROMISC) { 2888 sh_eth_tsu_purge_all(ndev); 2889 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2890 } else if (mdp->cd->tsu) { 2891 struct netdev_hw_addr *ha; 2892 netdev_for_each_mc_addr(ha, ndev) { 2893 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2894 continue; 2895 2896 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2897 if (!mcast_all) { 2898 sh_eth_tsu_purge_mcast(ndev); 2899 ecmr_bits &= ~ECMR_MCT; 2900 mcast_all = 1; 2901 } 2902 } 2903 } 2904 } 2905 2906 /* update the ethernet mode */ 2907 sh_eth_write(ndev, ecmr_bits, ECMR); 2908 2909 spin_unlock_irqrestore(&mdp->lock, flags); 2910 } 2911 2912 static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable) 2913 { 2914 struct sh_eth_private *mdp = netdev_priv(ndev); 2915 unsigned long flags; 2916 2917 spin_lock_irqsave(&mdp->lock, flags); 2918 2919 /* Disable TX and RX */ 2920 sh_eth_rcv_snd_disable(ndev); 2921 2922 /* Modify RX Checksum setting */ 2923 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2924 2925 /* Enable TX and RX */ 2926 sh_eth_rcv_snd_enable(ndev); 2927 2928 spin_unlock_irqrestore(&mdp->lock, flags); 2929 } 2930 2931 static int sh_eth_set_features(struct net_device *ndev, 2932 netdev_features_t features) 2933 { 2934 netdev_features_t changed = ndev->features ^ features; 2935 struct sh_eth_private *mdp = netdev_priv(ndev); 2936 2937 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum) 2938 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2939 2940 ndev->features = features; 2941 2942 return 0; 2943 } 2944 2945 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2946 { 2947 if (!mdp->port) 2948 return TSU_VTAG0; 2949 else 2950 return TSU_VTAG1; 2951 } 2952 2953 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2954 __be16 proto, u16 vid) 2955 { 2956 struct sh_eth_private *mdp = netdev_priv(ndev); 2957 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2958 2959 if (unlikely(!mdp->cd->tsu)) 2960 return -EPERM; 2961 2962 /* No filtering if vid = 0 */ 2963 if (!vid) 2964 return 0; 2965 2966 mdp->vlan_num_ids++; 2967 2968 /* The controller has one VLAN tag HW filter. So, if the filter is 2969 * already enabled, the driver disables it and the filte 2970 */ 2971 if (mdp->vlan_num_ids > 1) { 2972 /* disable VLAN filter */ 2973 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2974 return 0; 2975 } 2976 2977 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2978 vtag_reg_index); 2979 2980 return 0; 2981 } 2982 2983 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2984 __be16 proto, u16 vid) 2985 { 2986 struct sh_eth_private *mdp = netdev_priv(ndev); 2987 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2988 2989 if (unlikely(!mdp->cd->tsu)) 2990 return -EPERM; 2991 2992 /* No filtering if vid = 0 */ 2993 if (!vid) 2994 return 0; 2995 2996 mdp->vlan_num_ids--; 2997 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2998 2999 return 0; 3000 } 3001 3002 /* SuperH's TSU register init function */ 3003 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 3004 { 3005 if (!mdp->cd->dual_port) { 3006 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3007 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 3008 TSU_FWSLC); /* Enable POST registers */ 3009 return; 3010 } 3011 3012 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 3013 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 3014 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 3015 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 3016 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 3017 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 3018 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 3019 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 3020 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 3021 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 3022 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 3023 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 3024 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 3025 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 3026 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3027 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 3028 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 3029 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 3030 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 3031 } 3032 3033 /* MDIO bus release function */ 3034 static int sh_mdio_release(struct sh_eth_private *mdp) 3035 { 3036 /* unregister mdio bus */ 3037 mdiobus_unregister(mdp->mii_bus); 3038 3039 /* free bitbang info */ 3040 free_mdio_bitbang(mdp->mii_bus); 3041 3042 return 0; 3043 } 3044 3045 static int sh_mdiobb_read_c22(struct mii_bus *bus, int phy, int reg) 3046 { 3047 int res; 3048 3049 pm_runtime_get_sync(bus->parent); 3050 res = mdiobb_read_c22(bus, phy, reg); 3051 pm_runtime_put(bus->parent); 3052 3053 return res; 3054 } 3055 3056 static int sh_mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, u16 val) 3057 { 3058 int res; 3059 3060 pm_runtime_get_sync(bus->parent); 3061 res = mdiobb_write_c22(bus, phy, reg, val); 3062 pm_runtime_put(bus->parent); 3063 3064 return res; 3065 } 3066 3067 static int sh_mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, int reg) 3068 { 3069 int res; 3070 3071 pm_runtime_get_sync(bus->parent); 3072 res = mdiobb_read_c45(bus, phy, devad, reg); 3073 pm_runtime_put(bus->parent); 3074 3075 return res; 3076 } 3077 3078 static int sh_mdiobb_write_c45(struct mii_bus *bus, int phy, int devad, 3079 int reg, u16 val) 3080 { 3081 int res; 3082 3083 pm_runtime_get_sync(bus->parent); 3084 res = mdiobb_write_c45(bus, phy, devad, reg, val); 3085 pm_runtime_put(bus->parent); 3086 3087 return res; 3088 } 3089 3090 /* MDIO bus init function */ 3091 static int sh_mdio_init(struct sh_eth_private *mdp, 3092 struct sh_eth_plat_data *pd) 3093 { 3094 int ret; 3095 struct bb_info *bitbang; 3096 struct platform_device *pdev = mdp->pdev; 3097 struct device *dev = &mdp->pdev->dev; 3098 struct phy_device *phydev; 3099 struct device_node *pn; 3100 3101 /* create bit control struct for PHY */ 3102 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 3103 if (!bitbang) 3104 return -ENOMEM; 3105 3106 /* bitbang init */ 3107 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 3108 bitbang->set_gate = pd->set_mdio_gate; 3109 bitbang->ctrl.ops = &bb_ops; 3110 3111 /* MII controller setting */ 3112 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 3113 if (!mdp->mii_bus) 3114 return -ENOMEM; 3115 3116 /* Wrap accessors with Runtime PM-aware ops */ 3117 mdp->mii_bus->read = sh_mdiobb_read_c22; 3118 mdp->mii_bus->write = sh_mdiobb_write_c22; 3119 mdp->mii_bus->read_c45 = sh_mdiobb_read_c45; 3120 mdp->mii_bus->write_c45 = sh_mdiobb_write_c45; 3121 3122 /* Hook up MII support for ethtool */ 3123 mdp->mii_bus->name = "sh_mii"; 3124 mdp->mii_bus->parent = dev; 3125 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 3126 pdev->name, pdev->id); 3127 3128 /* register MDIO bus */ 3129 if (pd->phy_irq > 0) 3130 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3131 3132 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3133 if (ret) 3134 goto out_free_bus; 3135 3136 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 3137 phydev = of_phy_find_device(pn); 3138 if (phydev) { 3139 phydev->mac_managed_pm = true; 3140 put_device(&phydev->mdio.dev); 3141 } 3142 of_node_put(pn); 3143 3144 return 0; 3145 3146 out_free_bus: 3147 free_mdio_bitbang(mdp->mii_bus); 3148 return ret; 3149 } 3150 3151 static const u16 *sh_eth_get_register_offset(int register_type) 3152 { 3153 const u16 *reg_offset = NULL; 3154 3155 switch (register_type) { 3156 case SH_ETH_REG_GIGABIT: 3157 reg_offset = sh_eth_offset_gigabit; 3158 break; 3159 case SH_ETH_REG_FAST_RCAR: 3160 reg_offset = sh_eth_offset_fast_rcar; 3161 break; 3162 case SH_ETH_REG_FAST_SH4: 3163 reg_offset = sh_eth_offset_fast_sh4; 3164 break; 3165 case SH_ETH_REG_FAST_SH3_SH2: 3166 reg_offset = sh_eth_offset_fast_sh3_sh2; 3167 break; 3168 } 3169 3170 return reg_offset; 3171 } 3172 3173 static const struct net_device_ops sh_eth_netdev_ops = { 3174 .ndo_open = sh_eth_open, 3175 .ndo_stop = sh_eth_close, 3176 .ndo_start_xmit = sh_eth_start_xmit, 3177 .ndo_get_stats = sh_eth_get_stats, 3178 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3179 .ndo_tx_timeout = sh_eth_tx_timeout, 3180 .ndo_eth_ioctl = phy_do_ioctl_running, 3181 .ndo_change_mtu = sh_eth_change_mtu, 3182 .ndo_validate_addr = eth_validate_addr, 3183 .ndo_set_mac_address = eth_mac_addr, 3184 .ndo_set_features = sh_eth_set_features, 3185 }; 3186 3187 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3188 .ndo_open = sh_eth_open, 3189 .ndo_stop = sh_eth_close, 3190 .ndo_start_xmit = sh_eth_start_xmit, 3191 .ndo_get_stats = sh_eth_get_stats, 3192 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3193 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3194 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3195 .ndo_tx_timeout = sh_eth_tx_timeout, 3196 .ndo_eth_ioctl = phy_do_ioctl_running, 3197 .ndo_change_mtu = sh_eth_change_mtu, 3198 .ndo_validate_addr = eth_validate_addr, 3199 .ndo_set_mac_address = eth_mac_addr, 3200 .ndo_set_features = sh_eth_set_features, 3201 }; 3202 3203 #ifdef CONFIG_OF 3204 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3205 { 3206 struct device_node *np = dev->of_node; 3207 struct sh_eth_plat_data *pdata; 3208 phy_interface_t interface; 3209 int ret; 3210 3211 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3212 if (!pdata) 3213 return NULL; 3214 3215 ret = of_get_phy_mode(np, &interface); 3216 if (ret) 3217 return NULL; 3218 pdata->phy_interface = interface; 3219 3220 of_get_mac_address(np, pdata->mac_addr); 3221 3222 pdata->no_ether_link = 3223 of_property_read_bool(np, "renesas,no-ether-link"); 3224 pdata->ether_link_active_low = 3225 of_property_read_bool(np, "renesas,ether-link-active-low"); 3226 3227 return pdata; 3228 } 3229 3230 static const struct of_device_id sh_eth_match_table[] = { 3231 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3232 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3233 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3234 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3235 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3236 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3237 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3238 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3239 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3240 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data }, 3241 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3242 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data }, 3243 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3244 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3245 { } 3246 }; 3247 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3248 #else 3249 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3250 { 3251 return NULL; 3252 } 3253 #endif 3254 3255 static int sh_eth_drv_probe(struct platform_device *pdev) 3256 { 3257 struct resource *res; 3258 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3259 const struct platform_device_id *id = platform_get_device_id(pdev); 3260 struct sh_eth_private *mdp; 3261 struct net_device *ndev; 3262 int ret; 3263 3264 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3265 if (!ndev) 3266 return -ENOMEM; 3267 3268 pm_runtime_enable(&pdev->dev); 3269 pm_runtime_get_sync(&pdev->dev); 3270 3271 ret = platform_get_irq(pdev, 0); 3272 if (ret < 0) 3273 goto out_release; 3274 ndev->irq = ret; 3275 3276 SET_NETDEV_DEV(ndev, &pdev->dev); 3277 3278 mdp = netdev_priv(ndev); 3279 mdp->num_tx_ring = TX_RING_SIZE; 3280 mdp->num_rx_ring = RX_RING_SIZE; 3281 mdp->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 3282 if (IS_ERR(mdp->addr)) { 3283 ret = PTR_ERR(mdp->addr); 3284 goto out_release; 3285 } 3286 3287 ndev->base_addr = res->start; 3288 3289 spin_lock_init(&mdp->lock); 3290 mdp->pdev = pdev; 3291 3292 if (pdev->dev.of_node) 3293 pd = sh_eth_parse_dt(&pdev->dev); 3294 if (!pd) { 3295 dev_err(&pdev->dev, "no platform data\n"); 3296 ret = -EINVAL; 3297 goto out_release; 3298 } 3299 3300 /* get PHY ID */ 3301 mdp->phy_id = pd->phy; 3302 mdp->phy_interface = pd->phy_interface; 3303 mdp->no_ether_link = pd->no_ether_link; 3304 mdp->ether_link_active_low = pd->ether_link_active_low; 3305 3306 /* set cpu data */ 3307 if (id) 3308 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3309 else 3310 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3311 3312 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3313 if (!mdp->reg_offset) { 3314 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3315 mdp->cd->register_type); 3316 ret = -EINVAL; 3317 goto out_release; 3318 } 3319 sh_eth_set_default_cpu_data(mdp->cd); 3320 3321 /* User's manual states max MTU should be 2048 but due to the 3322 * alignment calculations in sh_eth_ring_init() the practical 3323 * MTU is a bit less. Maybe this can be optimized some more. 3324 */ 3325 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3326 ndev->min_mtu = ETH_MIN_MTU; 3327 3328 if (mdp->cd->rx_csum) { 3329 ndev->features = NETIF_F_RXCSUM; 3330 ndev->hw_features = NETIF_F_RXCSUM; 3331 } 3332 3333 /* set function */ 3334 if (mdp->cd->tsu) 3335 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3336 else 3337 ndev->netdev_ops = &sh_eth_netdev_ops; 3338 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3339 ndev->watchdog_timeo = TX_TIMEOUT; 3340 3341 /* debug message level */ 3342 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3343 3344 /* read and set MAC address */ 3345 read_mac_address(ndev, pd->mac_addr); 3346 if (!is_valid_ether_addr(ndev->dev_addr)) { 3347 dev_warn(&pdev->dev, 3348 "no valid MAC address supplied, using a random one.\n"); 3349 eth_hw_addr_random(ndev); 3350 } 3351 3352 if (mdp->cd->tsu) { 3353 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3354 struct resource *rtsu; 3355 3356 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3357 if (!rtsu) { 3358 dev_err(&pdev->dev, "no TSU resource\n"); 3359 ret = -ENODEV; 3360 goto out_release; 3361 } 3362 /* We can only request the TSU region for the first port 3363 * of the two sharing this TSU for the probe to succeed... 3364 */ 3365 if (port == 0 && 3366 !devm_request_mem_region(&pdev->dev, rtsu->start, 3367 resource_size(rtsu), 3368 dev_name(&pdev->dev))) { 3369 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3370 ret = -EBUSY; 3371 goto out_release; 3372 } 3373 /* ioremap the TSU registers */ 3374 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3375 resource_size(rtsu)); 3376 if (!mdp->tsu_addr) { 3377 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3378 ret = -ENOMEM; 3379 goto out_release; 3380 } 3381 mdp->port = port; 3382 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 3383 3384 /* Need to init only the first port of the two sharing a TSU */ 3385 if (port == 0) { 3386 if (mdp->cd->chip_reset) 3387 mdp->cd->chip_reset(ndev); 3388 3389 /* TSU init (Init only)*/ 3390 sh_eth_tsu_init(mdp); 3391 } 3392 } 3393 3394 if (mdp->cd->rmiimode) 3395 sh_eth_write(ndev, 0x1, RMIIMODE); 3396 3397 /* MDIO bus init */ 3398 ret = sh_mdio_init(mdp, pd); 3399 if (ret) { 3400 dev_err_probe(&pdev->dev, ret, "MDIO init failed\n"); 3401 goto out_release; 3402 } 3403 3404 netif_napi_add(ndev, &mdp->napi, sh_eth_poll); 3405 3406 /* network device register */ 3407 ret = register_netdev(ndev); 3408 if (ret) 3409 goto out_napi_del; 3410 3411 if (mdp->cd->magic) 3412 device_set_wakeup_capable(&pdev->dev, 1); 3413 3414 /* print device information */ 3415 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3416 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3417 3418 pm_runtime_put(&pdev->dev); 3419 platform_set_drvdata(pdev, ndev); 3420 3421 return ret; 3422 3423 out_napi_del: 3424 netif_napi_del(&mdp->napi); 3425 sh_mdio_release(mdp); 3426 3427 out_release: 3428 /* net_dev free */ 3429 free_netdev(ndev); 3430 3431 pm_runtime_put(&pdev->dev); 3432 pm_runtime_disable(&pdev->dev); 3433 return ret; 3434 } 3435 3436 static void sh_eth_drv_remove(struct platform_device *pdev) 3437 { 3438 struct net_device *ndev = platform_get_drvdata(pdev); 3439 struct sh_eth_private *mdp = netdev_priv(ndev); 3440 3441 unregister_netdev(ndev); 3442 netif_napi_del(&mdp->napi); 3443 sh_mdio_release(mdp); 3444 pm_runtime_disable(&pdev->dev); 3445 free_netdev(ndev); 3446 } 3447 3448 static int sh_eth_wol_setup(struct net_device *ndev) 3449 { 3450 struct sh_eth_private *mdp = netdev_priv(ndev); 3451 3452 /* Only allow ECI interrupts */ 3453 synchronize_irq(ndev->irq); 3454 napi_disable(&mdp->napi); 3455 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3456 3457 /* Enable MagicPacket */ 3458 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3459 3460 return enable_irq_wake(ndev->irq); 3461 } 3462 3463 static int sh_eth_wol_restore(struct net_device *ndev) 3464 { 3465 struct sh_eth_private *mdp = netdev_priv(ndev); 3466 int ret; 3467 3468 napi_enable(&mdp->napi); 3469 3470 /* Disable MagicPacket */ 3471 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3472 3473 /* The device needs to be reset to restore MagicPacket logic 3474 * for next wakeup. If we close and open the device it will 3475 * both be reset and all registers restored. This is what 3476 * happens during suspend and resume without WoL enabled. 3477 */ 3478 sh_eth_close(ndev); 3479 ret = sh_eth_open(ndev); 3480 if (ret < 0) 3481 return ret; 3482 3483 return disable_irq_wake(ndev->irq); 3484 } 3485 3486 static int sh_eth_suspend(struct device *dev) 3487 { 3488 struct net_device *ndev = dev_get_drvdata(dev); 3489 struct sh_eth_private *mdp = netdev_priv(ndev); 3490 int ret; 3491 3492 if (!netif_running(ndev)) 3493 return 0; 3494 3495 netif_device_detach(ndev); 3496 3497 rtnl_lock(); 3498 if (mdp->wol_enabled) 3499 ret = sh_eth_wol_setup(ndev); 3500 else 3501 ret = sh_eth_close(ndev); 3502 rtnl_unlock(); 3503 3504 return ret; 3505 } 3506 3507 static int sh_eth_resume(struct device *dev) 3508 { 3509 struct net_device *ndev = dev_get_drvdata(dev); 3510 struct sh_eth_private *mdp = netdev_priv(ndev); 3511 int ret; 3512 3513 if (!netif_running(ndev)) 3514 return 0; 3515 3516 rtnl_lock(); 3517 if (mdp->wol_enabled) 3518 ret = sh_eth_wol_restore(ndev); 3519 else 3520 ret = sh_eth_open(ndev); 3521 rtnl_unlock(); 3522 3523 if (ret < 0) 3524 return ret; 3525 3526 netif_device_attach(ndev); 3527 3528 return ret; 3529 } 3530 3531 static DEFINE_SIMPLE_DEV_PM_OPS(sh_eth_dev_pm_ops, sh_eth_suspend, sh_eth_resume); 3532 3533 static const struct platform_device_id sh_eth_id_table[] = { 3534 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3535 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3536 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3537 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3538 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3539 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3540 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3541 { } 3542 }; 3543 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3544 3545 static struct platform_driver sh_eth_driver = { 3546 .probe = sh_eth_drv_probe, 3547 .remove = sh_eth_drv_remove, 3548 .id_table = sh_eth_id_table, 3549 .driver = { 3550 .name = CARDNAME, 3551 .pm = pm_sleep_ptr(&sh_eth_dev_pm_ops), 3552 .of_match_table = of_match_ptr(sh_eth_match_table), 3553 }, 3554 }; 3555 3556 module_platform_driver(sh_eth_driver); 3557 3558 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3559 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3560 MODULE_LICENSE("GPL v2"); 3561