1 /* SuperH Ethernet device driver 2 * 3 * Copyright (C) 2014 Renesas Electronics Corporation 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2014 Renesas Solutions Corp. 6 * Copyright (C) 2013-2017 Cogent Embedded, Inc. 7 * Copyright (C) 2014 Codethink Limited 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 */ 21 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/etherdevice.h> 28 #include <linux/delay.h> 29 #include <linux/platform_device.h> 30 #include <linux/mdio-bitbang.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/of_net.h> 36 #include <linux/phy.h> 37 #include <linux/cache.h> 38 #include <linux/io.h> 39 #include <linux/pm_runtime.h> 40 #include <linux/slab.h> 41 #include <linux/ethtool.h> 42 #include <linux/if_vlan.h> 43 #include <linux/sh_eth.h> 44 #include <linux/of_mdio.h> 45 46 #include "sh_eth.h" 47 48 #define SH_ETH_DEF_MSG_ENABLE \ 49 (NETIF_MSG_LINK | \ 50 NETIF_MSG_TIMER | \ 51 NETIF_MSG_RX_ERR| \ 52 NETIF_MSG_TX_ERR) 53 54 #define SH_ETH_OFFSET_INVALID ((u16)~0) 55 56 #define SH_ETH_OFFSET_DEFAULTS \ 57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID 58 59 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 60 SH_ETH_OFFSET_DEFAULTS, 61 62 [EDSR] = 0x0000, 63 [EDMR] = 0x0400, 64 [EDTRR] = 0x0408, 65 [EDRRR] = 0x0410, 66 [EESR] = 0x0428, 67 [EESIPR] = 0x0430, 68 [TDLAR] = 0x0010, 69 [TDFAR] = 0x0014, 70 [TDFXR] = 0x0018, 71 [TDFFR] = 0x001c, 72 [RDLAR] = 0x0030, 73 [RDFAR] = 0x0034, 74 [RDFXR] = 0x0038, 75 [RDFFR] = 0x003c, 76 [TRSCER] = 0x0438, 77 [RMFCR] = 0x0440, 78 [TFTR] = 0x0448, 79 [FDR] = 0x0450, 80 [RMCR] = 0x0458, 81 [RPADIR] = 0x0460, 82 [FCFTR] = 0x0468, 83 [CSMR] = 0x04E4, 84 85 [ECMR] = 0x0500, 86 [ECSR] = 0x0510, 87 [ECSIPR] = 0x0518, 88 [PIR] = 0x0520, 89 [PSR] = 0x0528, 90 [PIPR] = 0x052c, 91 [RFLR] = 0x0508, 92 [APR] = 0x0554, 93 [MPR] = 0x0558, 94 [PFTCR] = 0x055c, 95 [PFRCR] = 0x0560, 96 [TPAUSER] = 0x0564, 97 [GECMR] = 0x05b0, 98 [BCULR] = 0x05b4, 99 [MAHR] = 0x05c0, 100 [MALR] = 0x05c8, 101 [TROCR] = 0x0700, 102 [CDCR] = 0x0708, 103 [LCCR] = 0x0710, 104 [CEFCR] = 0x0740, 105 [FRECR] = 0x0748, 106 [TSFRCR] = 0x0750, 107 [TLFRCR] = 0x0758, 108 [RFCR] = 0x0760, 109 [CERCR] = 0x0768, 110 [CEECR] = 0x0770, 111 [MAFCR] = 0x0778, 112 [RMII_MII] = 0x0790, 113 114 [ARSTR] = 0x0000, 115 [TSU_CTRST] = 0x0004, 116 [TSU_FWEN0] = 0x0010, 117 [TSU_FWEN1] = 0x0014, 118 [TSU_FCM] = 0x0018, 119 [TSU_BSYSL0] = 0x0020, 120 [TSU_BSYSL1] = 0x0024, 121 [TSU_PRISL0] = 0x0028, 122 [TSU_PRISL1] = 0x002c, 123 [TSU_FWSL0] = 0x0030, 124 [TSU_FWSL1] = 0x0034, 125 [TSU_FWSLC] = 0x0038, 126 [TSU_QTAGM0] = 0x0040, 127 [TSU_QTAGM1] = 0x0044, 128 [TSU_FWSR] = 0x0050, 129 [TSU_FWINMK] = 0x0054, 130 [TSU_ADQT0] = 0x0048, 131 [TSU_ADQT1] = 0x004c, 132 [TSU_VTAG0] = 0x0058, 133 [TSU_VTAG1] = 0x005c, 134 [TSU_ADSBSY] = 0x0060, 135 [TSU_TEN] = 0x0064, 136 [TSU_POST1] = 0x0070, 137 [TSU_POST2] = 0x0074, 138 [TSU_POST3] = 0x0078, 139 [TSU_POST4] = 0x007c, 140 [TSU_ADRH0] = 0x0100, 141 142 [TXNLCR0] = 0x0080, 143 [TXALCR0] = 0x0084, 144 [RXNLCR0] = 0x0088, 145 [RXALCR0] = 0x008c, 146 [FWNLCR0] = 0x0090, 147 [FWALCR0] = 0x0094, 148 [TXNLCR1] = 0x00a0, 149 [TXALCR1] = 0x00a4, 150 [RXNLCR1] = 0x00a8, 151 [RXALCR1] = 0x00ac, 152 [FWNLCR1] = 0x00b0, 153 [FWALCR1] = 0x00b4, 154 }; 155 156 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = { 157 SH_ETH_OFFSET_DEFAULTS, 158 159 [EDSR] = 0x0000, 160 [EDMR] = 0x0400, 161 [EDTRR] = 0x0408, 162 [EDRRR] = 0x0410, 163 [EESR] = 0x0428, 164 [EESIPR] = 0x0430, 165 [TDLAR] = 0x0010, 166 [TDFAR] = 0x0014, 167 [TDFXR] = 0x0018, 168 [TDFFR] = 0x001c, 169 [RDLAR] = 0x0030, 170 [RDFAR] = 0x0034, 171 [RDFXR] = 0x0038, 172 [RDFFR] = 0x003c, 173 [TRSCER] = 0x0438, 174 [RMFCR] = 0x0440, 175 [TFTR] = 0x0448, 176 [FDR] = 0x0450, 177 [RMCR] = 0x0458, 178 [RPADIR] = 0x0460, 179 [FCFTR] = 0x0468, 180 [CSMR] = 0x04E4, 181 182 [ECMR] = 0x0500, 183 [RFLR] = 0x0508, 184 [ECSR] = 0x0510, 185 [ECSIPR] = 0x0518, 186 [PIR] = 0x0520, 187 [APR] = 0x0554, 188 [MPR] = 0x0558, 189 [PFTCR] = 0x055c, 190 [PFRCR] = 0x0560, 191 [TPAUSER] = 0x0564, 192 [MAHR] = 0x05c0, 193 [MALR] = 0x05c8, 194 [CEFCR] = 0x0740, 195 [FRECR] = 0x0748, 196 [TSFRCR] = 0x0750, 197 [TLFRCR] = 0x0758, 198 [RFCR] = 0x0760, 199 [MAFCR] = 0x0778, 200 201 [ARSTR] = 0x0000, 202 [TSU_CTRST] = 0x0004, 203 [TSU_FWSLC] = 0x0038, 204 [TSU_VTAG0] = 0x0058, 205 [TSU_ADSBSY] = 0x0060, 206 [TSU_TEN] = 0x0064, 207 [TSU_POST1] = 0x0070, 208 [TSU_POST2] = 0x0074, 209 [TSU_POST3] = 0x0078, 210 [TSU_POST4] = 0x007c, 211 [TSU_ADRH0] = 0x0100, 212 213 [TXNLCR0] = 0x0080, 214 [TXALCR0] = 0x0084, 215 [RXNLCR0] = 0x0088, 216 [RXALCR0] = 0x008C, 217 }; 218 219 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 220 SH_ETH_OFFSET_DEFAULTS, 221 222 [ECMR] = 0x0300, 223 [RFLR] = 0x0308, 224 [ECSR] = 0x0310, 225 [ECSIPR] = 0x0318, 226 [PIR] = 0x0320, 227 [PSR] = 0x0328, 228 [RDMLR] = 0x0340, 229 [IPGR] = 0x0350, 230 [APR] = 0x0354, 231 [MPR] = 0x0358, 232 [RFCF] = 0x0360, 233 [TPAUSER] = 0x0364, 234 [TPAUSECR] = 0x0368, 235 [MAHR] = 0x03c0, 236 [MALR] = 0x03c8, 237 [TROCR] = 0x03d0, 238 [CDCR] = 0x03d4, 239 [LCCR] = 0x03d8, 240 [CNDCR] = 0x03dc, 241 [CEFCR] = 0x03e4, 242 [FRECR] = 0x03e8, 243 [TSFRCR] = 0x03ec, 244 [TLFRCR] = 0x03f0, 245 [RFCR] = 0x03f4, 246 [MAFCR] = 0x03f8, 247 248 [EDMR] = 0x0200, 249 [EDTRR] = 0x0208, 250 [EDRRR] = 0x0210, 251 [TDLAR] = 0x0218, 252 [RDLAR] = 0x0220, 253 [EESR] = 0x0228, 254 [EESIPR] = 0x0230, 255 [TRSCER] = 0x0238, 256 [RMFCR] = 0x0240, 257 [TFTR] = 0x0248, 258 [FDR] = 0x0250, 259 [RMCR] = 0x0258, 260 [TFUCR] = 0x0264, 261 [RFOCR] = 0x0268, 262 [RMIIMODE] = 0x026c, 263 [FCFTR] = 0x0270, 264 [TRIMD] = 0x027c, 265 }; 266 267 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 268 SH_ETH_OFFSET_DEFAULTS, 269 270 [ECMR] = 0x0100, 271 [RFLR] = 0x0108, 272 [ECSR] = 0x0110, 273 [ECSIPR] = 0x0118, 274 [PIR] = 0x0120, 275 [PSR] = 0x0128, 276 [RDMLR] = 0x0140, 277 [IPGR] = 0x0150, 278 [APR] = 0x0154, 279 [MPR] = 0x0158, 280 [TPAUSER] = 0x0164, 281 [RFCF] = 0x0160, 282 [TPAUSECR] = 0x0168, 283 [BCFRR] = 0x016c, 284 [MAHR] = 0x01c0, 285 [MALR] = 0x01c8, 286 [TROCR] = 0x01d0, 287 [CDCR] = 0x01d4, 288 [LCCR] = 0x01d8, 289 [CNDCR] = 0x01dc, 290 [CEFCR] = 0x01e4, 291 [FRECR] = 0x01e8, 292 [TSFRCR] = 0x01ec, 293 [TLFRCR] = 0x01f0, 294 [RFCR] = 0x01f4, 295 [MAFCR] = 0x01f8, 296 [RTRATE] = 0x01fc, 297 298 [EDMR] = 0x0000, 299 [EDTRR] = 0x0008, 300 [EDRRR] = 0x0010, 301 [TDLAR] = 0x0018, 302 [RDLAR] = 0x0020, 303 [EESR] = 0x0028, 304 [EESIPR] = 0x0030, 305 [TRSCER] = 0x0038, 306 [RMFCR] = 0x0040, 307 [TFTR] = 0x0048, 308 [FDR] = 0x0050, 309 [RMCR] = 0x0058, 310 [TFUCR] = 0x0064, 311 [RFOCR] = 0x0068, 312 [FCFTR] = 0x0070, 313 [RPADIR] = 0x0078, 314 [TRIMD] = 0x007c, 315 [RBWAR] = 0x00c8, 316 [RDFAR] = 0x00cc, 317 [TBRAR] = 0x00d4, 318 [TDFAR] = 0x00d8, 319 }; 320 321 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 322 SH_ETH_OFFSET_DEFAULTS, 323 324 [EDMR] = 0x0000, 325 [EDTRR] = 0x0004, 326 [EDRRR] = 0x0008, 327 [TDLAR] = 0x000c, 328 [RDLAR] = 0x0010, 329 [EESR] = 0x0014, 330 [EESIPR] = 0x0018, 331 [TRSCER] = 0x001c, 332 [RMFCR] = 0x0020, 333 [TFTR] = 0x0024, 334 [FDR] = 0x0028, 335 [RMCR] = 0x002c, 336 [EDOCR] = 0x0030, 337 [FCFTR] = 0x0034, 338 [RPADIR] = 0x0038, 339 [TRIMD] = 0x003c, 340 [RBWAR] = 0x0040, 341 [RDFAR] = 0x0044, 342 [TBRAR] = 0x004c, 343 [TDFAR] = 0x0050, 344 345 [ECMR] = 0x0160, 346 [ECSR] = 0x0164, 347 [ECSIPR] = 0x0168, 348 [PIR] = 0x016c, 349 [MAHR] = 0x0170, 350 [MALR] = 0x0174, 351 [RFLR] = 0x0178, 352 [PSR] = 0x017c, 353 [TROCR] = 0x0180, 354 [CDCR] = 0x0184, 355 [LCCR] = 0x0188, 356 [CNDCR] = 0x018c, 357 [CEFCR] = 0x0194, 358 [FRECR] = 0x0198, 359 [TSFRCR] = 0x019c, 360 [TLFRCR] = 0x01a0, 361 [RFCR] = 0x01a4, 362 [MAFCR] = 0x01a8, 363 [IPGR] = 0x01b4, 364 [APR] = 0x01b8, 365 [MPR] = 0x01bc, 366 [TPAUSER] = 0x01c4, 367 [BCFR] = 0x01cc, 368 369 [ARSTR] = 0x0000, 370 [TSU_CTRST] = 0x0004, 371 [TSU_FWEN0] = 0x0010, 372 [TSU_FWEN1] = 0x0014, 373 [TSU_FCM] = 0x0018, 374 [TSU_BSYSL0] = 0x0020, 375 [TSU_BSYSL1] = 0x0024, 376 [TSU_PRISL0] = 0x0028, 377 [TSU_PRISL1] = 0x002c, 378 [TSU_FWSL0] = 0x0030, 379 [TSU_FWSL1] = 0x0034, 380 [TSU_FWSLC] = 0x0038, 381 [TSU_QTAGM0] = 0x0040, 382 [TSU_QTAGM1] = 0x0044, 383 [TSU_ADQT0] = 0x0048, 384 [TSU_ADQT1] = 0x004c, 385 [TSU_FWSR] = 0x0050, 386 [TSU_FWINMK] = 0x0054, 387 [TSU_ADSBSY] = 0x0060, 388 [TSU_TEN] = 0x0064, 389 [TSU_POST1] = 0x0070, 390 [TSU_POST2] = 0x0074, 391 [TSU_POST3] = 0x0078, 392 [TSU_POST4] = 0x007c, 393 394 [TXNLCR0] = 0x0080, 395 [TXALCR0] = 0x0084, 396 [RXNLCR0] = 0x0088, 397 [RXALCR0] = 0x008c, 398 [FWNLCR0] = 0x0090, 399 [FWALCR0] = 0x0094, 400 [TXNLCR1] = 0x00a0, 401 [TXALCR1] = 0x00a4, 402 [RXNLCR1] = 0x00a8, 403 [RXALCR1] = 0x00ac, 404 [FWNLCR1] = 0x00b0, 405 [FWALCR1] = 0x00b4, 406 407 [TSU_ADRH0] = 0x0100, 408 }; 409 410 static void sh_eth_rcv_snd_disable(struct net_device *ndev); 411 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev); 412 413 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index) 414 { 415 struct sh_eth_private *mdp = netdev_priv(ndev); 416 u16 offset = mdp->reg_offset[enum_index]; 417 418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 419 return; 420 421 iowrite32(data, mdp->addr + offset); 422 } 423 424 static u32 sh_eth_read(struct net_device *ndev, int enum_index) 425 { 426 struct sh_eth_private *mdp = netdev_priv(ndev); 427 u16 offset = mdp->reg_offset[enum_index]; 428 429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 430 return ~0U; 431 432 return ioread32(mdp->addr + offset); 433 } 434 435 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear, 436 u32 set) 437 { 438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set, 439 enum_index); 440 } 441 442 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data, 443 int enum_index) 444 { 445 u16 offset = mdp->reg_offset[enum_index]; 446 447 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 448 return; 449 450 iowrite32(data, mdp->tsu_addr + offset); 451 } 452 453 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index) 454 { 455 u16 offset = mdp->reg_offset[enum_index]; 456 457 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID)) 458 return ~0U; 459 460 return ioread32(mdp->tsu_addr + offset); 461 } 462 463 static void sh_eth_soft_swap(char *src, int len) 464 { 465 #ifdef __LITTLE_ENDIAN 466 u32 *p = (u32 *)src; 467 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32)); 468 469 for (; p < maxp; p++) 470 *p = swab32(*p); 471 #endif 472 } 473 474 static void sh_eth_select_mii(struct net_device *ndev) 475 { 476 struct sh_eth_private *mdp = netdev_priv(ndev); 477 u32 value; 478 479 switch (mdp->phy_interface) { 480 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID: 481 value = 0x3; 482 break; 483 case PHY_INTERFACE_MODE_GMII: 484 value = 0x2; 485 break; 486 case PHY_INTERFACE_MODE_MII: 487 value = 0x1; 488 break; 489 case PHY_INTERFACE_MODE_RMII: 490 value = 0x0; 491 break; 492 default: 493 netdev_warn(ndev, 494 "PHY interface mode was not setup. Set to MII.\n"); 495 value = 0x1; 496 break; 497 } 498 499 sh_eth_write(ndev, value, RMII_MII); 500 } 501 502 static void sh_eth_set_duplex(struct net_device *ndev) 503 { 504 struct sh_eth_private *mdp = netdev_priv(ndev); 505 506 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0); 507 } 508 509 static void sh_eth_chip_reset(struct net_device *ndev) 510 { 511 struct sh_eth_private *mdp = netdev_priv(ndev); 512 513 /* reset device */ 514 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR); 515 mdelay(1); 516 } 517 518 static int sh_eth_soft_reset(struct net_device *ndev) 519 { 520 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER); 521 mdelay(3); 522 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0); 523 524 return 0; 525 } 526 527 static int sh_eth_check_soft_reset(struct net_device *ndev) 528 { 529 int cnt; 530 531 for (cnt = 100; cnt > 0; cnt--) { 532 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER)) 533 return 0; 534 mdelay(1); 535 } 536 537 netdev_err(ndev, "Device reset failed\n"); 538 return -ETIMEDOUT; 539 } 540 541 static int sh_eth_soft_reset_gether(struct net_device *ndev) 542 { 543 struct sh_eth_private *mdp = netdev_priv(ndev); 544 int ret; 545 546 sh_eth_write(ndev, EDSR_ENALL, EDSR); 547 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER); 548 549 ret = sh_eth_check_soft_reset(ndev); 550 if (ret) 551 return ret; 552 553 /* Table Init */ 554 sh_eth_write(ndev, 0, TDLAR); 555 sh_eth_write(ndev, 0, TDFAR); 556 sh_eth_write(ndev, 0, TDFXR); 557 sh_eth_write(ndev, 0, TDFFR); 558 sh_eth_write(ndev, 0, RDLAR); 559 sh_eth_write(ndev, 0, RDFAR); 560 sh_eth_write(ndev, 0, RDFXR); 561 sh_eth_write(ndev, 0, RDFFR); 562 563 /* Reset HW CRC register */ 564 if (mdp->cd->hw_checksum) 565 sh_eth_write(ndev, 0, CSMR); 566 567 /* Select MII mode */ 568 if (mdp->cd->select_mii) 569 sh_eth_select_mii(ndev); 570 571 return ret; 572 } 573 574 static void sh_eth_set_rate_gether(struct net_device *ndev) 575 { 576 struct sh_eth_private *mdp = netdev_priv(ndev); 577 578 switch (mdp->speed) { 579 case 10: /* 10BASE */ 580 sh_eth_write(ndev, GECMR_10, GECMR); 581 break; 582 case 100:/* 100BASE */ 583 sh_eth_write(ndev, GECMR_100, GECMR); 584 break; 585 case 1000: /* 1000BASE */ 586 sh_eth_write(ndev, GECMR_1000, GECMR); 587 break; 588 } 589 } 590 591 #ifdef CONFIG_OF 592 /* R7S72100 */ 593 static struct sh_eth_cpu_data r7s72100_data = { 594 .soft_reset = sh_eth_soft_reset_gether, 595 596 .chip_reset = sh_eth_chip_reset, 597 .set_duplex = sh_eth_set_duplex, 598 599 .register_type = SH_ETH_REG_FAST_RZ, 600 601 .edtrr_trns = EDTRR_TRNS_GETHER, 602 .ecsr_value = ECSR_ICD, 603 .ecsipr_value = ECSIPR_ICDIP, 604 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP | 605 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP | 606 EESIPR_ECIIP | 607 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 608 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 609 EESIPR_RMAFIP | EESIPR_RRFIP | 610 EESIPR_RTLFIP | EESIPR_RTSFIP | 611 EESIPR_PREIP | EESIPR_CERFIP, 612 613 .tx_check = EESR_TC1 | EESR_FTC, 614 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 615 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 616 EESR_TDE, 617 .fdr_value = 0x0000070f, 618 619 .no_psr = 1, 620 .apr = 1, 621 .mpr = 1, 622 .tpauser = 1, 623 .hw_swap = 1, 624 .rpadir = 1, 625 .no_trimd = 1, 626 .no_ade = 1, 627 .xdfar_rw = 1, 628 .hw_checksum = 1, 629 .tsu = 1, 630 .no_tx_cntrs = 1, 631 }; 632 633 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 634 { 635 sh_eth_chip_reset(ndev); 636 637 sh_eth_select_mii(ndev); 638 } 639 640 /* R8A7740 */ 641 static struct sh_eth_cpu_data r8a7740_data = { 642 .soft_reset = sh_eth_soft_reset_gether, 643 644 .chip_reset = sh_eth_chip_reset_r8a7740, 645 .set_duplex = sh_eth_set_duplex, 646 .set_rate = sh_eth_set_rate_gether, 647 648 .register_type = SH_ETH_REG_GIGABIT, 649 650 .edtrr_trns = EDTRR_TRNS_GETHER, 651 .ecsr_value = ECSR_ICD | ECSR_MPD, 652 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 653 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 654 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 655 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 656 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 657 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 658 EESIPR_CEEFIP | EESIPR_CELFIP | 659 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 660 EESIPR_PREIP | EESIPR_CERFIP, 661 662 .tx_check = EESR_TC1 | EESR_FTC, 663 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 664 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 665 EESR_TDE, 666 .fdr_value = 0x0000070f, 667 668 .apr = 1, 669 .mpr = 1, 670 .tpauser = 1, 671 .bculr = 1, 672 .hw_swap = 1, 673 .rpadir = 1, 674 .no_trimd = 1, 675 .no_ade = 1, 676 .xdfar_rw = 1, 677 .hw_checksum = 1, 678 .tsu = 1, 679 .select_mii = 1, 680 .magic = 1, 681 .cexcr = 1, 682 }; 683 684 /* There is CPU dependent code */ 685 static void sh_eth_set_rate_rcar(struct net_device *ndev) 686 { 687 struct sh_eth_private *mdp = netdev_priv(ndev); 688 689 switch (mdp->speed) { 690 case 10: /* 10BASE */ 691 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0); 692 break; 693 case 100:/* 100BASE */ 694 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB); 695 break; 696 } 697 } 698 699 /* R-Car Gen1 */ 700 static struct sh_eth_cpu_data rcar_gen1_data = { 701 .soft_reset = sh_eth_soft_reset, 702 703 .set_duplex = sh_eth_set_duplex, 704 .set_rate = sh_eth_set_rate_rcar, 705 706 .register_type = SH_ETH_REG_FAST_RCAR, 707 708 .edtrr_trns = EDTRR_TRNS_ETHER, 709 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 710 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 711 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 712 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 713 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 714 EESIPR_RMAFIP | EESIPR_RRFIP | 715 EESIPR_RTLFIP | EESIPR_RTSFIP | 716 EESIPR_PREIP | EESIPR_CERFIP, 717 718 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 719 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 720 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 721 .fdr_value = 0x00000f0f, 722 723 .apr = 1, 724 .mpr = 1, 725 .tpauser = 1, 726 .hw_swap = 1, 727 .no_xdfar = 1, 728 }; 729 730 /* R-Car Gen2 and RZ/G1 */ 731 static struct sh_eth_cpu_data rcar_gen2_data = { 732 .soft_reset = sh_eth_soft_reset, 733 734 .set_duplex = sh_eth_set_duplex, 735 .set_rate = sh_eth_set_rate_rcar, 736 737 .register_type = SH_ETH_REG_FAST_RCAR, 738 739 .edtrr_trns = EDTRR_TRNS_ETHER, 740 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 741 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 742 ECSIPR_MPDIP, 743 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 744 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 745 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 746 EESIPR_RMAFIP | EESIPR_RRFIP | 747 EESIPR_RTLFIP | EESIPR_RTSFIP | 748 EESIPR_PREIP | EESIPR_CERFIP, 749 750 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 751 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 752 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 753 .fdr_value = 0x00000f0f, 754 755 .trscer_err_mask = DESC_I_RINT8, 756 757 .apr = 1, 758 .mpr = 1, 759 .tpauser = 1, 760 .hw_swap = 1, 761 .no_xdfar = 1, 762 .rmiimode = 1, 763 .magic = 1, 764 }; 765 766 /* R8A77980 */ 767 static struct sh_eth_cpu_data r8a77980_data = { 768 .soft_reset = sh_eth_soft_reset_gether, 769 770 .set_duplex = sh_eth_set_duplex, 771 .set_rate = sh_eth_set_rate_gether, 772 773 .register_type = SH_ETH_REG_GIGABIT, 774 775 .edtrr_trns = EDTRR_TRNS_GETHER, 776 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD, 777 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP | 778 ECSIPR_MPDIP, 779 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 780 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 781 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 782 EESIPR_RMAFIP | EESIPR_RRFIP | 783 EESIPR_RTLFIP | EESIPR_RTSFIP | 784 EESIPR_PREIP | EESIPR_CERFIP, 785 786 .tx_check = EESR_FTC | EESR_CD | EESR_TRO, 787 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 788 EESR_RFE | EESR_RDE | EESR_RFRMER | 789 EESR_TFE | EESR_TDE | EESR_ECI, 790 .fdr_value = 0x0000070f, 791 792 .apr = 1, 793 .mpr = 1, 794 .tpauser = 1, 795 .bculr = 1, 796 .hw_swap = 1, 797 .nbst = 1, 798 .rpadir = 1, 799 .no_trimd = 1, 800 .no_ade = 1, 801 .xdfar_rw = 1, 802 .hw_checksum = 1, 803 .select_mii = 1, 804 .magic = 1, 805 .cexcr = 1, 806 }; 807 #endif /* CONFIG_OF */ 808 809 static void sh_eth_set_rate_sh7724(struct net_device *ndev) 810 { 811 struct sh_eth_private *mdp = netdev_priv(ndev); 812 813 switch (mdp->speed) { 814 case 10: /* 10BASE */ 815 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0); 816 break; 817 case 100:/* 100BASE */ 818 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM); 819 break; 820 } 821 } 822 823 /* SH7724 */ 824 static struct sh_eth_cpu_data sh7724_data = { 825 .soft_reset = sh_eth_soft_reset, 826 827 .set_duplex = sh_eth_set_duplex, 828 .set_rate = sh_eth_set_rate_sh7724, 829 830 .register_type = SH_ETH_REG_FAST_SH4, 831 832 .edtrr_trns = EDTRR_TRNS_ETHER, 833 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 834 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 835 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP | 836 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 837 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 838 EESIPR_RMAFIP | EESIPR_RRFIP | 839 EESIPR_RTLFIP | EESIPR_RTSFIP | 840 EESIPR_PREIP | EESIPR_CERFIP, 841 842 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 843 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 844 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 845 846 .apr = 1, 847 .mpr = 1, 848 .tpauser = 1, 849 .hw_swap = 1, 850 .rpadir = 1, 851 }; 852 853 static void sh_eth_set_rate_sh7757(struct net_device *ndev) 854 { 855 struct sh_eth_private *mdp = netdev_priv(ndev); 856 857 switch (mdp->speed) { 858 case 10: /* 10BASE */ 859 sh_eth_write(ndev, 0, RTRATE); 860 break; 861 case 100:/* 100BASE */ 862 sh_eth_write(ndev, 1, RTRATE); 863 break; 864 } 865 } 866 867 /* SH7757 */ 868 static struct sh_eth_cpu_data sh7757_data = { 869 .soft_reset = sh_eth_soft_reset, 870 871 .set_duplex = sh_eth_set_duplex, 872 .set_rate = sh_eth_set_rate_sh7757, 873 874 .register_type = SH_ETH_REG_FAST_SH4, 875 876 .edtrr_trns = EDTRR_TRNS_ETHER, 877 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 878 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 879 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 880 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 881 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 882 EESIPR_CEEFIP | EESIPR_CELFIP | 883 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 884 EESIPR_PREIP | EESIPR_CERFIP, 885 886 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO, 887 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 888 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 889 890 .irq_flags = IRQF_SHARED, 891 .apr = 1, 892 .mpr = 1, 893 .tpauser = 1, 894 .hw_swap = 1, 895 .no_ade = 1, 896 .rpadir = 1, 897 .rtrate = 1, 898 .dual_port = 1, 899 }; 900 901 #define SH_GIGA_ETH_BASE 0xfee00000UL 902 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 903 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 904 static void sh_eth_chip_reset_giga(struct net_device *ndev) 905 { 906 u32 mahr[2], malr[2]; 907 int i; 908 909 /* save MAHR and MALR */ 910 for (i = 0; i < 2; i++) { 911 malr[i] = ioread32((void *)GIGA_MALR(i)); 912 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 913 } 914 915 sh_eth_chip_reset(ndev); 916 917 /* restore MAHR and MALR */ 918 for (i = 0; i < 2; i++) { 919 iowrite32(malr[i], (void *)GIGA_MALR(i)); 920 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 921 } 922 } 923 924 static void sh_eth_set_rate_giga(struct net_device *ndev) 925 { 926 struct sh_eth_private *mdp = netdev_priv(ndev); 927 928 switch (mdp->speed) { 929 case 10: /* 10BASE */ 930 sh_eth_write(ndev, 0x00000000, GECMR); 931 break; 932 case 100:/* 100BASE */ 933 sh_eth_write(ndev, 0x00000010, GECMR); 934 break; 935 case 1000: /* 1000BASE */ 936 sh_eth_write(ndev, 0x00000020, GECMR); 937 break; 938 } 939 } 940 941 /* SH7757(GETHERC) */ 942 static struct sh_eth_cpu_data sh7757_data_giga = { 943 .soft_reset = sh_eth_soft_reset_gether, 944 945 .chip_reset = sh_eth_chip_reset_giga, 946 .set_duplex = sh_eth_set_duplex, 947 .set_rate = sh_eth_set_rate_giga, 948 949 .register_type = SH_ETH_REG_GIGABIT, 950 951 .edtrr_trns = EDTRR_TRNS_GETHER, 952 .ecsr_value = ECSR_ICD | ECSR_MPD, 953 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 954 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 955 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 956 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 957 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 958 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 959 EESIPR_CEEFIP | EESIPR_CELFIP | 960 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 961 EESIPR_PREIP | EESIPR_CERFIP, 962 963 .tx_check = EESR_TC1 | EESR_FTC, 964 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 965 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 966 EESR_TDE, 967 .fdr_value = 0x0000072f, 968 969 .irq_flags = IRQF_SHARED, 970 .apr = 1, 971 .mpr = 1, 972 .tpauser = 1, 973 .bculr = 1, 974 .hw_swap = 1, 975 .rpadir = 1, 976 .no_trimd = 1, 977 .no_ade = 1, 978 .xdfar_rw = 1, 979 .tsu = 1, 980 .cexcr = 1, 981 .dual_port = 1, 982 }; 983 984 /* SH7734 */ 985 static struct sh_eth_cpu_data sh7734_data = { 986 .soft_reset = sh_eth_soft_reset_gether, 987 988 .chip_reset = sh_eth_chip_reset, 989 .set_duplex = sh_eth_set_duplex, 990 .set_rate = sh_eth_set_rate_gether, 991 992 .register_type = SH_ETH_REG_GIGABIT, 993 994 .edtrr_trns = EDTRR_TRNS_GETHER, 995 .ecsr_value = ECSR_ICD | ECSR_MPD, 996 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 997 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 998 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 999 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1000 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1001 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1002 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1003 EESIPR_PREIP | EESIPR_CERFIP, 1004 1005 .tx_check = EESR_TC1 | EESR_FTC, 1006 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1007 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 1008 EESR_TDE, 1009 1010 .apr = 1, 1011 .mpr = 1, 1012 .tpauser = 1, 1013 .bculr = 1, 1014 .hw_swap = 1, 1015 .no_trimd = 1, 1016 .no_ade = 1, 1017 .xdfar_rw = 1, 1018 .tsu = 1, 1019 .hw_checksum = 1, 1020 .select_mii = 1, 1021 .magic = 1, 1022 .cexcr = 1, 1023 }; 1024 1025 /* SH7763 */ 1026 static struct sh_eth_cpu_data sh7763_data = { 1027 .soft_reset = sh_eth_soft_reset_gether, 1028 1029 .chip_reset = sh_eth_chip_reset, 1030 .set_duplex = sh_eth_set_duplex, 1031 .set_rate = sh_eth_set_rate_gether, 1032 1033 .register_type = SH_ETH_REG_GIGABIT, 1034 1035 .edtrr_trns = EDTRR_TRNS_GETHER, 1036 .ecsr_value = ECSR_ICD | ECSR_MPD, 1037 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 1038 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1039 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1040 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1041 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP | 1042 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP | 1043 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1044 EESIPR_PREIP | EESIPR_CERFIP, 1045 1046 .tx_check = EESR_TC1 | EESR_FTC, 1047 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 1048 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE, 1049 1050 .apr = 1, 1051 .mpr = 1, 1052 .tpauser = 1, 1053 .bculr = 1, 1054 .hw_swap = 1, 1055 .no_trimd = 1, 1056 .no_ade = 1, 1057 .xdfar_rw = 1, 1058 .tsu = 1, 1059 .irq_flags = IRQF_SHARED, 1060 .magic = 1, 1061 .cexcr = 1, 1062 .dual_port = 1, 1063 }; 1064 1065 static struct sh_eth_cpu_data sh7619_data = { 1066 .soft_reset = sh_eth_soft_reset, 1067 1068 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1069 1070 .edtrr_trns = EDTRR_TRNS_ETHER, 1071 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1072 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1073 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1074 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1075 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1076 EESIPR_CEEFIP | EESIPR_CELFIP | 1077 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1078 EESIPR_PREIP | EESIPR_CERFIP, 1079 1080 .apr = 1, 1081 .mpr = 1, 1082 .tpauser = 1, 1083 .hw_swap = 1, 1084 }; 1085 1086 static struct sh_eth_cpu_data sh771x_data = { 1087 .soft_reset = sh_eth_soft_reset, 1088 1089 .register_type = SH_ETH_REG_FAST_SH3_SH2, 1090 1091 .edtrr_trns = EDTRR_TRNS_ETHER, 1092 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP | 1093 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP | 1094 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP | 1095 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP | 1096 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP | 1097 EESIPR_CEEFIP | EESIPR_CELFIP | 1098 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP | 1099 EESIPR_PREIP | EESIPR_CERFIP, 1100 .tsu = 1, 1101 .dual_port = 1, 1102 }; 1103 1104 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 1105 { 1106 if (!cd->ecsr_value) 1107 cd->ecsr_value = DEFAULT_ECSR_INIT; 1108 1109 if (!cd->ecsipr_value) 1110 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 1111 1112 if (!cd->fcftr_value) 1113 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | 1114 DEFAULT_FIFO_F_D_RFD; 1115 1116 if (!cd->fdr_value) 1117 cd->fdr_value = DEFAULT_FDR_INIT; 1118 1119 if (!cd->tx_check) 1120 cd->tx_check = DEFAULT_TX_CHECK; 1121 1122 if (!cd->eesr_err_check) 1123 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 1124 1125 if (!cd->trscer_err_mask) 1126 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK; 1127 } 1128 1129 static void sh_eth_set_receive_align(struct sk_buff *skb) 1130 { 1131 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1); 1132 1133 if (reserve) 1134 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve); 1135 } 1136 1137 /* Program the hardware MAC address from dev->dev_addr. */ 1138 static void update_mac_address(struct net_device *ndev) 1139 { 1140 sh_eth_write(ndev, 1141 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 1142 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 1143 sh_eth_write(ndev, 1144 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 1145 } 1146 1147 /* Get MAC address from SuperH MAC address register 1148 * 1149 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 1150 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 1151 * When you want use this device, you must set MAC address in bootloader. 1152 * 1153 */ 1154 static void read_mac_address(struct net_device *ndev, unsigned char *mac) 1155 { 1156 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 1157 memcpy(ndev->dev_addr, mac, ETH_ALEN); 1158 } else { 1159 u32 mahr = sh_eth_read(ndev, MAHR); 1160 u32 malr = sh_eth_read(ndev, MALR); 1161 1162 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 1163 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 1164 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 1165 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 1166 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 1167 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 1168 } 1169 } 1170 1171 struct bb_info { 1172 void (*set_gate)(void *addr); 1173 struct mdiobb_ctrl ctrl; 1174 void *addr; 1175 }; 1176 1177 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 1178 { 1179 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1180 u32 pir; 1181 1182 if (bitbang->set_gate) 1183 bitbang->set_gate(bitbang->addr); 1184 1185 pir = ioread32(bitbang->addr); 1186 if (set) 1187 pir |= mask; 1188 else 1189 pir &= ~mask; 1190 iowrite32(pir, bitbang->addr); 1191 } 1192 1193 /* Data I/O pin control */ 1194 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1195 { 1196 sh_mdio_ctrl(ctrl, PIR_MMD, bit); 1197 } 1198 1199 /* Set bit data*/ 1200 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 1201 { 1202 sh_mdio_ctrl(ctrl, PIR_MDO, bit); 1203 } 1204 1205 /* Get bit data*/ 1206 static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 1207 { 1208 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 1209 1210 if (bitbang->set_gate) 1211 bitbang->set_gate(bitbang->addr); 1212 1213 return (ioread32(bitbang->addr) & PIR_MDI) != 0; 1214 } 1215 1216 /* MDC pin control */ 1217 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 1218 { 1219 sh_mdio_ctrl(ctrl, PIR_MDC, bit); 1220 } 1221 1222 /* mdio bus control struct */ 1223 static struct mdiobb_ops bb_ops = { 1224 .owner = THIS_MODULE, 1225 .set_mdc = sh_mdc_ctrl, 1226 .set_mdio_dir = sh_mmd_ctrl, 1227 .set_mdio_data = sh_set_mdio, 1228 .get_mdio_data = sh_get_mdio, 1229 }; 1230 1231 /* free Tx skb function */ 1232 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only) 1233 { 1234 struct sh_eth_private *mdp = netdev_priv(ndev); 1235 struct sh_eth_txdesc *txdesc; 1236 int free_num = 0; 1237 int entry; 1238 bool sent; 1239 1240 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1241 entry = mdp->dirty_tx % mdp->num_tx_ring; 1242 txdesc = &mdp->tx_ring[entry]; 1243 sent = !(txdesc->status & cpu_to_le32(TD_TACT)); 1244 if (sent_only && !sent) 1245 break; 1246 /* TACT bit must be checked before all the following reads */ 1247 dma_rmb(); 1248 netif_info(mdp, tx_done, ndev, 1249 "tx entry %d status 0x%08x\n", 1250 entry, le32_to_cpu(txdesc->status)); 1251 /* Free the original skb. */ 1252 if (mdp->tx_skbuff[entry]) { 1253 dma_unmap_single(&mdp->pdev->dev, 1254 le32_to_cpu(txdesc->addr), 1255 le32_to_cpu(txdesc->len) >> 16, 1256 DMA_TO_DEVICE); 1257 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1258 mdp->tx_skbuff[entry] = NULL; 1259 free_num++; 1260 } 1261 txdesc->status = cpu_to_le32(TD_TFP); 1262 if (entry >= mdp->num_tx_ring - 1) 1263 txdesc->status |= cpu_to_le32(TD_TDLE); 1264 1265 if (sent) { 1266 ndev->stats.tx_packets++; 1267 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16; 1268 } 1269 } 1270 return free_num; 1271 } 1272 1273 /* free skb and descriptor buffer */ 1274 static void sh_eth_ring_free(struct net_device *ndev) 1275 { 1276 struct sh_eth_private *mdp = netdev_priv(ndev); 1277 int ringsize, i; 1278 1279 if (mdp->rx_ring) { 1280 for (i = 0; i < mdp->num_rx_ring; i++) { 1281 if (mdp->rx_skbuff[i]) { 1282 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i]; 1283 1284 dma_unmap_single(&mdp->pdev->dev, 1285 le32_to_cpu(rxdesc->addr), 1286 ALIGN(mdp->rx_buf_sz, 32), 1287 DMA_FROM_DEVICE); 1288 } 1289 } 1290 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1291 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring, 1292 mdp->rx_desc_dma); 1293 mdp->rx_ring = NULL; 1294 } 1295 1296 /* Free Rx skb ringbuffer */ 1297 if (mdp->rx_skbuff) { 1298 for (i = 0; i < mdp->num_rx_ring; i++) 1299 dev_kfree_skb(mdp->rx_skbuff[i]); 1300 } 1301 kfree(mdp->rx_skbuff); 1302 mdp->rx_skbuff = NULL; 1303 1304 if (mdp->tx_ring) { 1305 sh_eth_tx_free(ndev, false); 1306 1307 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1308 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring, 1309 mdp->tx_desc_dma); 1310 mdp->tx_ring = NULL; 1311 } 1312 1313 /* Free Tx skb ringbuffer */ 1314 kfree(mdp->tx_skbuff); 1315 mdp->tx_skbuff = NULL; 1316 } 1317 1318 /* format skb and descriptor buffer */ 1319 static void sh_eth_ring_format(struct net_device *ndev) 1320 { 1321 struct sh_eth_private *mdp = netdev_priv(ndev); 1322 int i; 1323 struct sk_buff *skb; 1324 struct sh_eth_rxdesc *rxdesc = NULL; 1325 struct sh_eth_txdesc *txdesc = NULL; 1326 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1327 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1328 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1329 dma_addr_t dma_addr; 1330 u32 buf_len; 1331 1332 mdp->cur_rx = 0; 1333 mdp->cur_tx = 0; 1334 mdp->dirty_rx = 0; 1335 mdp->dirty_tx = 0; 1336 1337 memset(mdp->rx_ring, 0, rx_ringsize); 1338 1339 /* build Rx ring buffer */ 1340 for (i = 0; i < mdp->num_rx_ring; i++) { 1341 /* skb */ 1342 mdp->rx_skbuff[i] = NULL; 1343 skb = netdev_alloc_skb(ndev, skbuff_size); 1344 if (skb == NULL) 1345 break; 1346 sh_eth_set_receive_align(skb); 1347 1348 /* The size of the buffer is a multiple of 32 bytes. */ 1349 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1350 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len, 1351 DMA_FROM_DEVICE); 1352 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1353 kfree_skb(skb); 1354 break; 1355 } 1356 mdp->rx_skbuff[i] = skb; 1357 1358 /* RX descriptor */ 1359 rxdesc = &mdp->rx_ring[i]; 1360 rxdesc->len = cpu_to_le32(buf_len << 16); 1361 rxdesc->addr = cpu_to_le32(dma_addr); 1362 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP); 1363 1364 /* Rx descriptor address set */ 1365 if (i == 0) { 1366 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1367 if (mdp->cd->xdfar_rw) 1368 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1369 } 1370 } 1371 1372 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1373 1374 /* Mark the last entry as wrapping the ring. */ 1375 if (rxdesc) 1376 rxdesc->status |= cpu_to_le32(RD_RDLE); 1377 1378 memset(mdp->tx_ring, 0, tx_ringsize); 1379 1380 /* build Tx ring buffer */ 1381 for (i = 0; i < mdp->num_tx_ring; i++) { 1382 mdp->tx_skbuff[i] = NULL; 1383 txdesc = &mdp->tx_ring[i]; 1384 txdesc->status = cpu_to_le32(TD_TFP); 1385 txdesc->len = cpu_to_le32(0); 1386 if (i == 0) { 1387 /* Tx descriptor address set */ 1388 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1389 if (mdp->cd->xdfar_rw) 1390 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1391 } 1392 } 1393 1394 txdesc->status |= cpu_to_le32(TD_TDLE); 1395 } 1396 1397 /* Get skb and descriptor buffer */ 1398 static int sh_eth_ring_init(struct net_device *ndev) 1399 { 1400 struct sh_eth_private *mdp = netdev_priv(ndev); 1401 int rx_ringsize, tx_ringsize; 1402 1403 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1404 * card needs room to do 8 byte alignment, +2 so we can reserve 1405 * the first 2 bytes, and +16 gets room for the status word from the 1406 * card. 1407 */ 1408 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1409 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1410 if (mdp->cd->rpadir) 1411 mdp->rx_buf_sz += NET_IP_ALIGN; 1412 1413 /* Allocate RX and TX skb rings */ 1414 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff), 1415 GFP_KERNEL); 1416 if (!mdp->rx_skbuff) 1417 return -ENOMEM; 1418 1419 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff), 1420 GFP_KERNEL); 1421 if (!mdp->tx_skbuff) 1422 goto ring_free; 1423 1424 /* Allocate all Rx descriptors. */ 1425 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1426 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize, 1427 &mdp->rx_desc_dma, GFP_KERNEL); 1428 if (!mdp->rx_ring) 1429 goto ring_free; 1430 1431 mdp->dirty_rx = 0; 1432 1433 /* Allocate all Tx descriptors. */ 1434 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1435 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize, 1436 &mdp->tx_desc_dma, GFP_KERNEL); 1437 if (!mdp->tx_ring) 1438 goto ring_free; 1439 return 0; 1440 1441 ring_free: 1442 /* Free Rx and Tx skb ring buffer and DMA buffer */ 1443 sh_eth_ring_free(ndev); 1444 1445 return -ENOMEM; 1446 } 1447 1448 static int sh_eth_dev_init(struct net_device *ndev) 1449 { 1450 struct sh_eth_private *mdp = netdev_priv(ndev); 1451 int ret; 1452 1453 /* Soft Reset */ 1454 ret = mdp->cd->soft_reset(ndev); 1455 if (ret) 1456 return ret; 1457 1458 if (mdp->cd->rmiimode) 1459 sh_eth_write(ndev, 0x1, RMIIMODE); 1460 1461 /* Descriptor format */ 1462 sh_eth_ring_format(ndev); 1463 if (mdp->cd->rpadir) 1464 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR); 1465 1466 /* all sh_eth int mask */ 1467 sh_eth_write(ndev, 0, EESIPR); 1468 1469 #if defined(__LITTLE_ENDIAN) 1470 if (mdp->cd->hw_swap) 1471 sh_eth_write(ndev, EDMR_EL, EDMR); 1472 else 1473 #endif 1474 sh_eth_write(ndev, 0, EDMR); 1475 1476 /* FIFO size set */ 1477 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1478 sh_eth_write(ndev, 0, TFTR); 1479 1480 /* Frame recv control (enable multiple-packets per rx irq) */ 1481 sh_eth_write(ndev, RMCR_RNC, RMCR); 1482 1483 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER); 1484 1485 /* DMA transfer burst mode */ 1486 if (mdp->cd->nbst) 1487 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST); 1488 1489 /* Burst cycle count upper-limit */ 1490 if (mdp->cd->bculr) 1491 sh_eth_write(ndev, 0x800, BCULR); 1492 1493 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1494 1495 if (!mdp->cd->no_trimd) 1496 sh_eth_write(ndev, 0, TRIMD); 1497 1498 /* Recv frame limit set register */ 1499 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1500 RFLR); 1501 1502 sh_eth_modify(ndev, EESR, 0, 0); 1503 mdp->irq_enabled = true; 1504 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1505 1506 /* PAUSE Prohibition */ 1507 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | 1508 ECMR_TE | ECMR_RE, ECMR); 1509 1510 if (mdp->cd->set_rate) 1511 mdp->cd->set_rate(ndev); 1512 1513 /* E-MAC Status Register clear */ 1514 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1515 1516 /* E-MAC Interrupt Enable register */ 1517 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1518 1519 /* Set MAC address */ 1520 update_mac_address(ndev); 1521 1522 /* mask reset */ 1523 if (mdp->cd->apr) 1524 sh_eth_write(ndev, 1, APR); 1525 if (mdp->cd->mpr) 1526 sh_eth_write(ndev, 1, MPR); 1527 if (mdp->cd->tpauser) 1528 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1529 1530 /* Setting the Rx mode will start the Rx process. */ 1531 sh_eth_write(ndev, EDRRR_R, EDRRR); 1532 1533 return ret; 1534 } 1535 1536 static void sh_eth_dev_exit(struct net_device *ndev) 1537 { 1538 struct sh_eth_private *mdp = netdev_priv(ndev); 1539 int i; 1540 1541 /* Deactivate all TX descriptors, so DMA should stop at next 1542 * packet boundary if it's currently running 1543 */ 1544 for (i = 0; i < mdp->num_tx_ring; i++) 1545 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT); 1546 1547 /* Disable TX FIFO egress to MAC */ 1548 sh_eth_rcv_snd_disable(ndev); 1549 1550 /* Stop RX DMA at next packet boundary */ 1551 sh_eth_write(ndev, 0, EDRRR); 1552 1553 /* Aside from TX DMA, we can't tell when the hardware is 1554 * really stopped, so we need to reset to make sure. 1555 * Before doing that, wait for long enough to *probably* 1556 * finish transmitting the last packet and poll stats. 1557 */ 1558 msleep(2); /* max frame time at 10 Mbps < 1250 us */ 1559 sh_eth_get_stats(ndev); 1560 mdp->cd->soft_reset(ndev); 1561 1562 /* Set MAC address again */ 1563 update_mac_address(ndev); 1564 } 1565 1566 /* Packet receive function */ 1567 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1568 { 1569 struct sh_eth_private *mdp = netdev_priv(ndev); 1570 struct sh_eth_rxdesc *rxdesc; 1571 1572 int entry = mdp->cur_rx % mdp->num_rx_ring; 1573 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1574 int limit; 1575 struct sk_buff *skb; 1576 u32 desc_status; 1577 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1; 1578 dma_addr_t dma_addr; 1579 u16 pkt_len; 1580 u32 buf_len; 1581 1582 boguscnt = min(boguscnt, *quota); 1583 limit = boguscnt; 1584 rxdesc = &mdp->rx_ring[entry]; 1585 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 1586 /* RACT bit must be checked before all the following reads */ 1587 dma_rmb(); 1588 desc_status = le32_to_cpu(rxdesc->status); 1589 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL; 1590 1591 if (--boguscnt < 0) 1592 break; 1593 1594 netif_info(mdp, rx_status, ndev, 1595 "rx entry %d status 0x%08x len %d\n", 1596 entry, desc_status, pkt_len); 1597 1598 if (!(desc_status & RDFEND)) 1599 ndev->stats.rx_length_errors++; 1600 1601 /* In case of almost all GETHER/ETHERs, the Receive Frame State 1602 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1603 * bit 0. However, in case of the R8A7740 and R7S72100 1604 * the RFS bits are from bit 25 to bit 16. So, the 1605 * driver needs right shifting by 16. 1606 */ 1607 if (mdp->cd->hw_checksum) 1608 desc_status >>= 16; 1609 1610 skb = mdp->rx_skbuff[entry]; 1611 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1612 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1613 ndev->stats.rx_errors++; 1614 if (desc_status & RD_RFS1) 1615 ndev->stats.rx_crc_errors++; 1616 if (desc_status & RD_RFS2) 1617 ndev->stats.rx_frame_errors++; 1618 if (desc_status & RD_RFS3) 1619 ndev->stats.rx_length_errors++; 1620 if (desc_status & RD_RFS4) 1621 ndev->stats.rx_length_errors++; 1622 if (desc_status & RD_RFS6) 1623 ndev->stats.rx_missed_errors++; 1624 if (desc_status & RD_RFS10) 1625 ndev->stats.rx_over_errors++; 1626 } else if (skb) { 1627 dma_addr = le32_to_cpu(rxdesc->addr); 1628 if (!mdp->cd->hw_swap) 1629 sh_eth_soft_swap( 1630 phys_to_virt(ALIGN(dma_addr, 4)), 1631 pkt_len + 2); 1632 mdp->rx_skbuff[entry] = NULL; 1633 if (mdp->cd->rpadir) 1634 skb_reserve(skb, NET_IP_ALIGN); 1635 dma_unmap_single(&mdp->pdev->dev, dma_addr, 1636 ALIGN(mdp->rx_buf_sz, 32), 1637 DMA_FROM_DEVICE); 1638 skb_put(skb, pkt_len); 1639 skb->protocol = eth_type_trans(skb, ndev); 1640 netif_receive_skb(skb); 1641 ndev->stats.rx_packets++; 1642 ndev->stats.rx_bytes += pkt_len; 1643 if (desc_status & RD_RFS8) 1644 ndev->stats.multicast++; 1645 } 1646 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1647 rxdesc = &mdp->rx_ring[entry]; 1648 } 1649 1650 /* Refill the Rx ring buffers. */ 1651 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1652 entry = mdp->dirty_rx % mdp->num_rx_ring; 1653 rxdesc = &mdp->rx_ring[entry]; 1654 /* The size of the buffer is 32 byte boundary. */ 1655 buf_len = ALIGN(mdp->rx_buf_sz, 32); 1656 rxdesc->len = cpu_to_le32(buf_len << 16); 1657 1658 if (mdp->rx_skbuff[entry] == NULL) { 1659 skb = netdev_alloc_skb(ndev, skbuff_size); 1660 if (skb == NULL) 1661 break; /* Better luck next round. */ 1662 sh_eth_set_receive_align(skb); 1663 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, 1664 buf_len, DMA_FROM_DEVICE); 1665 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 1666 kfree_skb(skb); 1667 break; 1668 } 1669 mdp->rx_skbuff[entry] = skb; 1670 1671 skb_checksum_none_assert(skb); 1672 rxdesc->addr = cpu_to_le32(dma_addr); 1673 } 1674 dma_wmb(); /* RACT bit must be set after all the above writes */ 1675 if (entry >= mdp->num_rx_ring - 1) 1676 rxdesc->status |= 1677 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE); 1678 else 1679 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP); 1680 } 1681 1682 /* Restart Rx engine if stopped. */ 1683 /* If we don't need to check status, don't. -KDU */ 1684 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1685 /* fix the values for the next receiving if RDE is set */ 1686 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) { 1687 u32 count = (sh_eth_read(ndev, RDFAR) - 1688 sh_eth_read(ndev, RDLAR)) >> 4; 1689 1690 mdp->cur_rx = count; 1691 mdp->dirty_rx = count; 1692 } 1693 sh_eth_write(ndev, EDRRR_R, EDRRR); 1694 } 1695 1696 *quota -= limit - boguscnt - 1; 1697 1698 return *quota <= 0; 1699 } 1700 1701 static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1702 { 1703 /* disable tx and rx */ 1704 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1705 } 1706 1707 static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1708 { 1709 /* enable tx and rx */ 1710 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1711 } 1712 1713 /* E-MAC interrupt handler */ 1714 static void sh_eth_emac_interrupt(struct net_device *ndev) 1715 { 1716 struct sh_eth_private *mdp = netdev_priv(ndev); 1717 u32 felic_stat; 1718 u32 link_stat; 1719 1720 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR); 1721 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1722 if (felic_stat & ECSR_ICD) 1723 ndev->stats.tx_carrier_errors++; 1724 if (felic_stat & ECSR_MPD) 1725 pm_wakeup_event(&mdp->pdev->dev, 0); 1726 if (felic_stat & ECSR_LCHNG) { 1727 /* Link Changed */ 1728 if (mdp->cd->no_psr || mdp->no_ether_link) 1729 return; 1730 link_stat = sh_eth_read(ndev, PSR); 1731 if (mdp->ether_link_active_low) 1732 link_stat = ~link_stat; 1733 if (!(link_stat & PHY_ST_LINK)) { 1734 sh_eth_rcv_snd_disable(ndev); 1735 } else { 1736 /* Link Up */ 1737 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0); 1738 /* clear int */ 1739 sh_eth_modify(ndev, ECSR, 0, 0); 1740 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP); 1741 /* enable tx and rx */ 1742 sh_eth_rcv_snd_enable(ndev); 1743 } 1744 } 1745 } 1746 1747 /* error control function */ 1748 static void sh_eth_error(struct net_device *ndev, u32 intr_status) 1749 { 1750 struct sh_eth_private *mdp = netdev_priv(ndev); 1751 u32 mask; 1752 1753 if (intr_status & EESR_TWB) { 1754 /* Unused write back interrupt */ 1755 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1756 ndev->stats.tx_aborted_errors++; 1757 netif_err(mdp, tx_err, ndev, "Transmit Abort\n"); 1758 } 1759 } 1760 1761 if (intr_status & EESR_RABT) { 1762 /* Receive Abort int */ 1763 if (intr_status & EESR_RFRMER) { 1764 /* Receive Frame Overflow int */ 1765 ndev->stats.rx_frame_errors++; 1766 } 1767 } 1768 1769 if (intr_status & EESR_TDE) { 1770 /* Transmit Descriptor Empty int */ 1771 ndev->stats.tx_fifo_errors++; 1772 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n"); 1773 } 1774 1775 if (intr_status & EESR_TFE) { 1776 /* FIFO under flow */ 1777 ndev->stats.tx_fifo_errors++; 1778 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n"); 1779 } 1780 1781 if (intr_status & EESR_RDE) { 1782 /* Receive Descriptor Empty int */ 1783 ndev->stats.rx_over_errors++; 1784 } 1785 1786 if (intr_status & EESR_RFE) { 1787 /* Receive FIFO Overflow int */ 1788 ndev->stats.rx_fifo_errors++; 1789 } 1790 1791 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1792 /* Address Error */ 1793 ndev->stats.tx_fifo_errors++; 1794 netif_err(mdp, tx_err, ndev, "Address Error\n"); 1795 } 1796 1797 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1798 if (mdp->cd->no_ade) 1799 mask &= ~EESR_ADE; 1800 if (intr_status & mask) { 1801 /* Tx error */ 1802 u32 edtrr = sh_eth_read(ndev, EDTRR); 1803 1804 /* dmesg */ 1805 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1806 intr_status, mdp->cur_tx, mdp->dirty_tx, 1807 (u32)ndev->state, edtrr); 1808 /* dirty buffer free */ 1809 sh_eth_tx_free(ndev, true); 1810 1811 /* SH7712 BUG */ 1812 if (edtrr ^ mdp->cd->edtrr_trns) { 1813 /* tx dma start */ 1814 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 1815 } 1816 /* wakeup */ 1817 netif_wake_queue(ndev); 1818 } 1819 } 1820 1821 static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1822 { 1823 struct net_device *ndev = netdev; 1824 struct sh_eth_private *mdp = netdev_priv(ndev); 1825 struct sh_eth_cpu_data *cd = mdp->cd; 1826 irqreturn_t ret = IRQ_NONE; 1827 u32 intr_status, intr_enable; 1828 1829 spin_lock(&mdp->lock); 1830 1831 /* Get interrupt status */ 1832 intr_status = sh_eth_read(ndev, EESR); 1833 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1834 * enabled since it's the one that comes thru regardless of the mask, 1835 * and we need to fully handle it in sh_eth_emac_interrupt() in order 1836 * to quench it as it doesn't get cleared by just writing 1 to the ECI 1837 * bit... 1838 */ 1839 intr_enable = sh_eth_read(ndev, EESIPR); 1840 intr_status &= intr_enable | EESIPR_ECIIP; 1841 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI | 1842 cd->eesr_err_check)) 1843 ret = IRQ_HANDLED; 1844 else 1845 goto out; 1846 1847 if (unlikely(!mdp->irq_enabled)) { 1848 sh_eth_write(ndev, 0, EESIPR); 1849 goto out; 1850 } 1851 1852 if (intr_status & EESR_RX_CHECK) { 1853 if (napi_schedule_prep(&mdp->napi)) { 1854 /* Mask Rx interrupts */ 1855 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1856 EESIPR); 1857 __napi_schedule(&mdp->napi); 1858 } else { 1859 netdev_warn(ndev, 1860 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n", 1861 intr_status, intr_enable); 1862 } 1863 } 1864 1865 /* Tx Check */ 1866 if (intr_status & cd->tx_check) { 1867 /* Clear Tx interrupts */ 1868 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1869 1870 sh_eth_tx_free(ndev, true); 1871 netif_wake_queue(ndev); 1872 } 1873 1874 /* E-MAC interrupt */ 1875 if (intr_status & EESR_ECI) 1876 sh_eth_emac_interrupt(ndev); 1877 1878 if (intr_status & cd->eesr_err_check) { 1879 /* Clear error interrupts */ 1880 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1881 1882 sh_eth_error(ndev, intr_status); 1883 } 1884 1885 out: 1886 spin_unlock(&mdp->lock); 1887 1888 return ret; 1889 } 1890 1891 static int sh_eth_poll(struct napi_struct *napi, int budget) 1892 { 1893 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1894 napi); 1895 struct net_device *ndev = napi->dev; 1896 int quota = budget; 1897 u32 intr_status; 1898 1899 for (;;) { 1900 intr_status = sh_eth_read(ndev, EESR); 1901 if (!(intr_status & EESR_RX_CHECK)) 1902 break; 1903 /* Clear Rx interrupts */ 1904 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1905 1906 if (sh_eth_rx(ndev, intr_status, "a)) 1907 goto out; 1908 } 1909 1910 napi_complete(napi); 1911 1912 /* Reenable Rx interrupts */ 1913 if (mdp->irq_enabled) 1914 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1915 out: 1916 return budget - quota; 1917 } 1918 1919 /* PHY state control function */ 1920 static void sh_eth_adjust_link(struct net_device *ndev) 1921 { 1922 struct sh_eth_private *mdp = netdev_priv(ndev); 1923 struct phy_device *phydev = ndev->phydev; 1924 int new_state = 0; 1925 1926 if (phydev->link) { 1927 if (phydev->duplex != mdp->duplex) { 1928 new_state = 1; 1929 mdp->duplex = phydev->duplex; 1930 if (mdp->cd->set_duplex) 1931 mdp->cd->set_duplex(ndev); 1932 } 1933 1934 if (phydev->speed != mdp->speed) { 1935 new_state = 1; 1936 mdp->speed = phydev->speed; 1937 if (mdp->cd->set_rate) 1938 mdp->cd->set_rate(ndev); 1939 } 1940 if (!mdp->link) { 1941 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0); 1942 new_state = 1; 1943 mdp->link = phydev->link; 1944 if (mdp->cd->no_psr || mdp->no_ether_link) 1945 sh_eth_rcv_snd_enable(ndev); 1946 } 1947 } else if (mdp->link) { 1948 new_state = 1; 1949 mdp->link = 0; 1950 mdp->speed = 0; 1951 mdp->duplex = -1; 1952 if (mdp->cd->no_psr || mdp->no_ether_link) 1953 sh_eth_rcv_snd_disable(ndev); 1954 } 1955 1956 if (new_state && netif_msg_link(mdp)) 1957 phy_print_status(phydev); 1958 } 1959 1960 /* PHY init function */ 1961 static int sh_eth_phy_init(struct net_device *ndev) 1962 { 1963 struct device_node *np = ndev->dev.parent->of_node; 1964 struct sh_eth_private *mdp = netdev_priv(ndev); 1965 struct phy_device *phydev; 1966 1967 mdp->link = 0; 1968 mdp->speed = 0; 1969 mdp->duplex = -1; 1970 1971 /* Try connect to PHY */ 1972 if (np) { 1973 struct device_node *pn; 1974 1975 pn = of_parse_phandle(np, "phy-handle", 0); 1976 phydev = of_phy_connect(ndev, pn, 1977 sh_eth_adjust_link, 0, 1978 mdp->phy_interface); 1979 1980 of_node_put(pn); 1981 if (!phydev) 1982 phydev = ERR_PTR(-ENOENT); 1983 } else { 1984 char phy_id[MII_BUS_ID_SIZE + 3]; 1985 1986 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1987 mdp->mii_bus->id, mdp->phy_id); 1988 1989 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1990 mdp->phy_interface); 1991 } 1992 1993 if (IS_ERR(phydev)) { 1994 netdev_err(ndev, "failed to connect PHY\n"); 1995 return PTR_ERR(phydev); 1996 } 1997 1998 /* mask with MAC supported features */ 1999 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) { 2000 int err = phy_set_max_speed(phydev, SPEED_100); 2001 if (err) { 2002 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n"); 2003 phy_disconnect(phydev); 2004 return err; 2005 } 2006 } 2007 2008 phy_attached_info(phydev); 2009 2010 return 0; 2011 } 2012 2013 /* PHY control start function */ 2014 static int sh_eth_phy_start(struct net_device *ndev) 2015 { 2016 int ret; 2017 2018 ret = sh_eth_phy_init(ndev); 2019 if (ret) 2020 return ret; 2021 2022 phy_start(ndev->phydev); 2023 2024 return 0; 2025 } 2026 2027 static int sh_eth_get_link_ksettings(struct net_device *ndev, 2028 struct ethtool_link_ksettings *cmd) 2029 { 2030 struct sh_eth_private *mdp = netdev_priv(ndev); 2031 unsigned long flags; 2032 2033 if (!ndev->phydev) 2034 return -ENODEV; 2035 2036 spin_lock_irqsave(&mdp->lock, flags); 2037 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2038 spin_unlock_irqrestore(&mdp->lock, flags); 2039 2040 return 0; 2041 } 2042 2043 static int sh_eth_set_link_ksettings(struct net_device *ndev, 2044 const struct ethtool_link_ksettings *cmd) 2045 { 2046 struct sh_eth_private *mdp = netdev_priv(ndev); 2047 unsigned long flags; 2048 int ret; 2049 2050 if (!ndev->phydev) 2051 return -ENODEV; 2052 2053 spin_lock_irqsave(&mdp->lock, flags); 2054 2055 /* disable tx and rx */ 2056 sh_eth_rcv_snd_disable(ndev); 2057 2058 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd); 2059 if (ret) 2060 goto error_exit; 2061 2062 if (cmd->base.duplex == DUPLEX_FULL) 2063 mdp->duplex = 1; 2064 else 2065 mdp->duplex = 0; 2066 2067 if (mdp->cd->set_duplex) 2068 mdp->cd->set_duplex(ndev); 2069 2070 error_exit: 2071 mdelay(1); 2072 2073 /* enable tx and rx */ 2074 sh_eth_rcv_snd_enable(ndev); 2075 2076 spin_unlock_irqrestore(&mdp->lock, flags); 2077 2078 return ret; 2079 } 2080 2081 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the 2082 * version must be bumped as well. Just adding registers up to that 2083 * limit is fine, as long as the existing register indices don't 2084 * change. 2085 */ 2086 #define SH_ETH_REG_DUMP_VERSION 1 2087 #define SH_ETH_REG_DUMP_MAX_REGS 256 2088 2089 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) 2090 { 2091 struct sh_eth_private *mdp = netdev_priv(ndev); 2092 struct sh_eth_cpu_data *cd = mdp->cd; 2093 u32 *valid_map; 2094 size_t len; 2095 2096 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS); 2097 2098 /* Dump starts with a bitmap that tells ethtool which 2099 * registers are defined for this chip. 2100 */ 2101 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32); 2102 if (buf) { 2103 valid_map = buf; 2104 buf += len; 2105 } else { 2106 valid_map = NULL; 2107 } 2108 2109 /* Add a register to the dump, if it has a defined offset. 2110 * This automatically skips most undefined registers, but for 2111 * some it is also necessary to check a capability flag in 2112 * struct sh_eth_cpu_data. 2113 */ 2114 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32) 2115 #define add_reg_from(reg, read_expr) do { \ 2116 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \ 2117 if (buf) { \ 2118 mark_reg_valid(reg); \ 2119 *buf++ = read_expr; \ 2120 } \ 2121 ++len; \ 2122 } \ 2123 } while (0) 2124 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg)) 2125 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg)) 2126 2127 add_reg(EDSR); 2128 add_reg(EDMR); 2129 add_reg(EDTRR); 2130 add_reg(EDRRR); 2131 add_reg(EESR); 2132 add_reg(EESIPR); 2133 add_reg(TDLAR); 2134 add_reg(TDFAR); 2135 add_reg(TDFXR); 2136 add_reg(TDFFR); 2137 add_reg(RDLAR); 2138 add_reg(RDFAR); 2139 add_reg(RDFXR); 2140 add_reg(RDFFR); 2141 add_reg(TRSCER); 2142 add_reg(RMFCR); 2143 add_reg(TFTR); 2144 add_reg(FDR); 2145 add_reg(RMCR); 2146 add_reg(TFUCR); 2147 add_reg(RFOCR); 2148 if (cd->rmiimode) 2149 add_reg(RMIIMODE); 2150 add_reg(FCFTR); 2151 if (cd->rpadir) 2152 add_reg(RPADIR); 2153 if (!cd->no_trimd) 2154 add_reg(TRIMD); 2155 add_reg(ECMR); 2156 add_reg(ECSR); 2157 add_reg(ECSIPR); 2158 add_reg(PIR); 2159 if (!cd->no_psr) 2160 add_reg(PSR); 2161 add_reg(RDMLR); 2162 add_reg(RFLR); 2163 add_reg(IPGR); 2164 if (cd->apr) 2165 add_reg(APR); 2166 if (cd->mpr) 2167 add_reg(MPR); 2168 add_reg(RFCR); 2169 add_reg(RFCF); 2170 if (cd->tpauser) 2171 add_reg(TPAUSER); 2172 add_reg(TPAUSECR); 2173 add_reg(GECMR); 2174 if (cd->bculr) 2175 add_reg(BCULR); 2176 add_reg(MAHR); 2177 add_reg(MALR); 2178 add_reg(TROCR); 2179 add_reg(CDCR); 2180 add_reg(LCCR); 2181 add_reg(CNDCR); 2182 add_reg(CEFCR); 2183 add_reg(FRECR); 2184 add_reg(TSFRCR); 2185 add_reg(TLFRCR); 2186 add_reg(CERCR); 2187 add_reg(CEECR); 2188 add_reg(MAFCR); 2189 if (cd->rtrate) 2190 add_reg(RTRATE); 2191 if (cd->hw_checksum) 2192 add_reg(CSMR); 2193 if (cd->select_mii) 2194 add_reg(RMII_MII); 2195 if (cd->tsu) { 2196 add_tsu_reg(ARSTR); 2197 add_tsu_reg(TSU_CTRST); 2198 add_tsu_reg(TSU_FWEN0); 2199 add_tsu_reg(TSU_FWEN1); 2200 add_tsu_reg(TSU_FCM); 2201 add_tsu_reg(TSU_BSYSL0); 2202 add_tsu_reg(TSU_BSYSL1); 2203 add_tsu_reg(TSU_PRISL0); 2204 add_tsu_reg(TSU_PRISL1); 2205 add_tsu_reg(TSU_FWSL0); 2206 add_tsu_reg(TSU_FWSL1); 2207 add_tsu_reg(TSU_FWSLC); 2208 add_tsu_reg(TSU_QTAGM0); 2209 add_tsu_reg(TSU_QTAGM1); 2210 add_tsu_reg(TSU_FWSR); 2211 add_tsu_reg(TSU_FWINMK); 2212 add_tsu_reg(TSU_ADQT0); 2213 add_tsu_reg(TSU_ADQT1); 2214 add_tsu_reg(TSU_VTAG0); 2215 add_tsu_reg(TSU_VTAG1); 2216 add_tsu_reg(TSU_ADSBSY); 2217 add_tsu_reg(TSU_TEN); 2218 add_tsu_reg(TSU_POST1); 2219 add_tsu_reg(TSU_POST2); 2220 add_tsu_reg(TSU_POST3); 2221 add_tsu_reg(TSU_POST4); 2222 /* This is the start of a table, not just a single register. */ 2223 if (buf) { 2224 unsigned int i; 2225 2226 mark_reg_valid(TSU_ADRH0); 2227 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++) 2228 *buf++ = ioread32(mdp->tsu_addr + 2229 mdp->reg_offset[TSU_ADRH0] + 2230 i * 4); 2231 } 2232 len += SH_ETH_TSU_CAM_ENTRIES * 2; 2233 } 2234 2235 #undef mark_reg_valid 2236 #undef add_reg_from 2237 #undef add_reg 2238 #undef add_tsu_reg 2239 2240 return len * 4; 2241 } 2242 2243 static int sh_eth_get_regs_len(struct net_device *ndev) 2244 { 2245 return __sh_eth_get_regs(ndev, NULL); 2246 } 2247 2248 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs, 2249 void *buf) 2250 { 2251 struct sh_eth_private *mdp = netdev_priv(ndev); 2252 2253 regs->version = SH_ETH_REG_DUMP_VERSION; 2254 2255 pm_runtime_get_sync(&mdp->pdev->dev); 2256 __sh_eth_get_regs(ndev, buf); 2257 pm_runtime_put_sync(&mdp->pdev->dev); 2258 } 2259 2260 static int sh_eth_nway_reset(struct net_device *ndev) 2261 { 2262 struct sh_eth_private *mdp = netdev_priv(ndev); 2263 unsigned long flags; 2264 int ret; 2265 2266 if (!ndev->phydev) 2267 return -ENODEV; 2268 2269 spin_lock_irqsave(&mdp->lock, flags); 2270 ret = phy_start_aneg(ndev->phydev); 2271 spin_unlock_irqrestore(&mdp->lock, flags); 2272 2273 return ret; 2274 } 2275 2276 static u32 sh_eth_get_msglevel(struct net_device *ndev) 2277 { 2278 struct sh_eth_private *mdp = netdev_priv(ndev); 2279 return mdp->msg_enable; 2280 } 2281 2282 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 2283 { 2284 struct sh_eth_private *mdp = netdev_priv(ndev); 2285 mdp->msg_enable = value; 2286 } 2287 2288 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 2289 "rx_current", "tx_current", 2290 "rx_dirty", "tx_dirty", 2291 }; 2292 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 2293 2294 static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 2295 { 2296 switch (sset) { 2297 case ETH_SS_STATS: 2298 return SH_ETH_STATS_LEN; 2299 default: 2300 return -EOPNOTSUPP; 2301 } 2302 } 2303 2304 static void sh_eth_get_ethtool_stats(struct net_device *ndev, 2305 struct ethtool_stats *stats, u64 *data) 2306 { 2307 struct sh_eth_private *mdp = netdev_priv(ndev); 2308 int i = 0; 2309 2310 /* device-specific stats */ 2311 data[i++] = mdp->cur_rx; 2312 data[i++] = mdp->cur_tx; 2313 data[i++] = mdp->dirty_rx; 2314 data[i++] = mdp->dirty_tx; 2315 } 2316 2317 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 2318 { 2319 switch (stringset) { 2320 case ETH_SS_STATS: 2321 memcpy(data, *sh_eth_gstrings_stats, 2322 sizeof(sh_eth_gstrings_stats)); 2323 break; 2324 } 2325 } 2326 2327 static void sh_eth_get_ringparam(struct net_device *ndev, 2328 struct ethtool_ringparam *ring) 2329 { 2330 struct sh_eth_private *mdp = netdev_priv(ndev); 2331 2332 ring->rx_max_pending = RX_RING_MAX; 2333 ring->tx_max_pending = TX_RING_MAX; 2334 ring->rx_pending = mdp->num_rx_ring; 2335 ring->tx_pending = mdp->num_tx_ring; 2336 } 2337 2338 static int sh_eth_set_ringparam(struct net_device *ndev, 2339 struct ethtool_ringparam *ring) 2340 { 2341 struct sh_eth_private *mdp = netdev_priv(ndev); 2342 int ret; 2343 2344 if (ring->tx_pending > TX_RING_MAX || 2345 ring->rx_pending > RX_RING_MAX || 2346 ring->tx_pending < TX_RING_MIN || 2347 ring->rx_pending < RX_RING_MIN) 2348 return -EINVAL; 2349 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 2350 return -EINVAL; 2351 2352 if (netif_running(ndev)) { 2353 netif_device_detach(ndev); 2354 netif_tx_disable(ndev); 2355 2356 /* Serialise with the interrupt handler and NAPI, then 2357 * disable interrupts. We have to clear the 2358 * irq_enabled flag first to ensure that interrupts 2359 * won't be re-enabled. 2360 */ 2361 mdp->irq_enabled = false; 2362 synchronize_irq(ndev->irq); 2363 napi_synchronize(&mdp->napi); 2364 sh_eth_write(ndev, 0x0000, EESIPR); 2365 2366 sh_eth_dev_exit(ndev); 2367 2368 /* Free all the skbuffs in the Rx queue and the DMA buffers. */ 2369 sh_eth_ring_free(ndev); 2370 } 2371 2372 /* Set new parameters */ 2373 mdp->num_rx_ring = ring->rx_pending; 2374 mdp->num_tx_ring = ring->tx_pending; 2375 2376 if (netif_running(ndev)) { 2377 ret = sh_eth_ring_init(ndev); 2378 if (ret < 0) { 2379 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", 2380 __func__); 2381 return ret; 2382 } 2383 ret = sh_eth_dev_init(ndev); 2384 if (ret < 0) { 2385 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", 2386 __func__); 2387 return ret; 2388 } 2389 2390 netif_device_attach(ndev); 2391 } 2392 2393 return 0; 2394 } 2395 2396 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2397 { 2398 struct sh_eth_private *mdp = netdev_priv(ndev); 2399 2400 wol->supported = 0; 2401 wol->wolopts = 0; 2402 2403 if (mdp->cd->magic) { 2404 wol->supported = WAKE_MAGIC; 2405 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0; 2406 } 2407 } 2408 2409 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 2410 { 2411 struct sh_eth_private *mdp = netdev_priv(ndev); 2412 2413 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC) 2414 return -EOPNOTSUPP; 2415 2416 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 2417 2418 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled); 2419 2420 return 0; 2421 } 2422 2423 static const struct ethtool_ops sh_eth_ethtool_ops = { 2424 .get_regs_len = sh_eth_get_regs_len, 2425 .get_regs = sh_eth_get_regs, 2426 .nway_reset = sh_eth_nway_reset, 2427 .get_msglevel = sh_eth_get_msglevel, 2428 .set_msglevel = sh_eth_set_msglevel, 2429 .get_link = ethtool_op_get_link, 2430 .get_strings = sh_eth_get_strings, 2431 .get_ethtool_stats = sh_eth_get_ethtool_stats, 2432 .get_sset_count = sh_eth_get_sset_count, 2433 .get_ringparam = sh_eth_get_ringparam, 2434 .set_ringparam = sh_eth_set_ringparam, 2435 .get_link_ksettings = sh_eth_get_link_ksettings, 2436 .set_link_ksettings = sh_eth_set_link_ksettings, 2437 .get_wol = sh_eth_get_wol, 2438 .set_wol = sh_eth_set_wol, 2439 }; 2440 2441 /* network device open function */ 2442 static int sh_eth_open(struct net_device *ndev) 2443 { 2444 struct sh_eth_private *mdp = netdev_priv(ndev); 2445 int ret; 2446 2447 pm_runtime_get_sync(&mdp->pdev->dev); 2448 2449 napi_enable(&mdp->napi); 2450 2451 ret = request_irq(ndev->irq, sh_eth_interrupt, 2452 mdp->cd->irq_flags, ndev->name, ndev); 2453 if (ret) { 2454 netdev_err(ndev, "Can not assign IRQ number\n"); 2455 goto out_napi_off; 2456 } 2457 2458 /* Descriptor set */ 2459 ret = sh_eth_ring_init(ndev); 2460 if (ret) 2461 goto out_free_irq; 2462 2463 /* device init */ 2464 ret = sh_eth_dev_init(ndev); 2465 if (ret) 2466 goto out_free_irq; 2467 2468 /* PHY control start*/ 2469 ret = sh_eth_phy_start(ndev); 2470 if (ret) 2471 goto out_free_irq; 2472 2473 netif_start_queue(ndev); 2474 2475 mdp->is_opened = 1; 2476 2477 return ret; 2478 2479 out_free_irq: 2480 free_irq(ndev->irq, ndev); 2481 out_napi_off: 2482 napi_disable(&mdp->napi); 2483 pm_runtime_put_sync(&mdp->pdev->dev); 2484 return ret; 2485 } 2486 2487 /* Timeout function */ 2488 static void sh_eth_tx_timeout(struct net_device *ndev) 2489 { 2490 struct sh_eth_private *mdp = netdev_priv(ndev); 2491 struct sh_eth_rxdesc *rxdesc; 2492 int i; 2493 2494 netif_stop_queue(ndev); 2495 2496 netif_err(mdp, timer, ndev, 2497 "transmit timed out, status %8.8x, resetting...\n", 2498 sh_eth_read(ndev, EESR)); 2499 2500 /* tx_errors count up */ 2501 ndev->stats.tx_errors++; 2502 2503 /* Free all the skbuffs in the Rx queue. */ 2504 for (i = 0; i < mdp->num_rx_ring; i++) { 2505 rxdesc = &mdp->rx_ring[i]; 2506 rxdesc->status = cpu_to_le32(0); 2507 rxdesc->addr = cpu_to_le32(0xBADF00D0); 2508 dev_kfree_skb(mdp->rx_skbuff[i]); 2509 mdp->rx_skbuff[i] = NULL; 2510 } 2511 for (i = 0; i < mdp->num_tx_ring; i++) { 2512 dev_kfree_skb(mdp->tx_skbuff[i]); 2513 mdp->tx_skbuff[i] = NULL; 2514 } 2515 2516 /* device init */ 2517 sh_eth_dev_init(ndev); 2518 2519 netif_start_queue(ndev); 2520 } 2521 2522 /* Packet transmit function */ 2523 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2524 { 2525 struct sh_eth_private *mdp = netdev_priv(ndev); 2526 struct sh_eth_txdesc *txdesc; 2527 dma_addr_t dma_addr; 2528 u32 entry; 2529 unsigned long flags; 2530 2531 spin_lock_irqsave(&mdp->lock, flags); 2532 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 2533 if (!sh_eth_tx_free(ndev, true)) { 2534 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n"); 2535 netif_stop_queue(ndev); 2536 spin_unlock_irqrestore(&mdp->lock, flags); 2537 return NETDEV_TX_BUSY; 2538 } 2539 } 2540 spin_unlock_irqrestore(&mdp->lock, flags); 2541 2542 if (skb_put_padto(skb, ETH_ZLEN)) 2543 return NETDEV_TX_OK; 2544 2545 entry = mdp->cur_tx % mdp->num_tx_ring; 2546 mdp->tx_skbuff[entry] = skb; 2547 txdesc = &mdp->tx_ring[entry]; 2548 /* soft swap. */ 2549 if (!mdp->cd->hw_swap) 2550 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2); 2551 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len, 2552 DMA_TO_DEVICE); 2553 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) { 2554 kfree_skb(skb); 2555 return NETDEV_TX_OK; 2556 } 2557 txdesc->addr = cpu_to_le32(dma_addr); 2558 txdesc->len = cpu_to_le32(skb->len << 16); 2559 2560 dma_wmb(); /* TACT bit must be set after all the above writes */ 2561 if (entry >= mdp->num_tx_ring - 1) 2562 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE); 2563 else 2564 txdesc->status |= cpu_to_le32(TD_TACT); 2565 2566 mdp->cur_tx++; 2567 2568 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns)) 2569 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR); 2570 2571 return NETDEV_TX_OK; 2572 } 2573 2574 /* The statistics registers have write-clear behaviour, which means we 2575 * will lose any increment between the read and write. We mitigate 2576 * this by only clearing when we read a non-zero value, so we will 2577 * never falsely report a total of zero. 2578 */ 2579 static void 2580 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg) 2581 { 2582 u32 delta = sh_eth_read(ndev, reg); 2583 2584 if (delta) { 2585 *stat += delta; 2586 sh_eth_write(ndev, 0, reg); 2587 } 2588 } 2589 2590 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2591 { 2592 struct sh_eth_private *mdp = netdev_priv(ndev); 2593 2594 if (mdp->cd->no_tx_cntrs) 2595 return &ndev->stats; 2596 2597 if (!mdp->is_opened) 2598 return &ndev->stats; 2599 2600 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR); 2601 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR); 2602 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR); 2603 2604 if (mdp->cd->cexcr) { 2605 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2606 CERCR); 2607 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2608 CEECR); 2609 } else { 2610 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, 2611 CNDCR); 2612 } 2613 2614 return &ndev->stats; 2615 } 2616 2617 /* device close function */ 2618 static int sh_eth_close(struct net_device *ndev) 2619 { 2620 struct sh_eth_private *mdp = netdev_priv(ndev); 2621 2622 netif_stop_queue(ndev); 2623 2624 /* Serialise with the interrupt handler and NAPI, then disable 2625 * interrupts. We have to clear the irq_enabled flag first to 2626 * ensure that interrupts won't be re-enabled. 2627 */ 2628 mdp->irq_enabled = false; 2629 synchronize_irq(ndev->irq); 2630 napi_disable(&mdp->napi); 2631 sh_eth_write(ndev, 0x0000, EESIPR); 2632 2633 sh_eth_dev_exit(ndev); 2634 2635 /* PHY Disconnect */ 2636 if (ndev->phydev) { 2637 phy_stop(ndev->phydev); 2638 phy_disconnect(ndev->phydev); 2639 } 2640 2641 free_irq(ndev->irq, ndev); 2642 2643 /* Free all the skbuffs in the Rx queue and the DMA buffer. */ 2644 sh_eth_ring_free(ndev); 2645 2646 pm_runtime_put_sync(&mdp->pdev->dev); 2647 2648 mdp->is_opened = 0; 2649 2650 return 0; 2651 } 2652 2653 /* ioctl to device function */ 2654 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) 2655 { 2656 struct phy_device *phydev = ndev->phydev; 2657 2658 if (!netif_running(ndev)) 2659 return -EINVAL; 2660 2661 if (!phydev) 2662 return -ENODEV; 2663 2664 return phy_mii_ioctl(phydev, rq, cmd); 2665 } 2666 2667 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu) 2668 { 2669 if (netif_running(ndev)) 2670 return -EBUSY; 2671 2672 ndev->mtu = new_mtu; 2673 netdev_update_features(ndev); 2674 2675 return 0; 2676 } 2677 2678 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2679 static u32 sh_eth_tsu_get_post_mask(int entry) 2680 { 2681 return 0x0f << (28 - ((entry % 8) * 4)); 2682 } 2683 2684 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2685 { 2686 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2687 } 2688 2689 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2690 int entry) 2691 { 2692 struct sh_eth_private *mdp = netdev_priv(ndev); 2693 int reg = TSU_POST1 + entry / 8; 2694 u32 tmp; 2695 2696 tmp = sh_eth_tsu_read(mdp, reg); 2697 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg); 2698 } 2699 2700 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2701 int entry) 2702 { 2703 struct sh_eth_private *mdp = netdev_priv(ndev); 2704 int reg = TSU_POST1 + entry / 8; 2705 u32 post_mask, ref_mask, tmp; 2706 2707 post_mask = sh_eth_tsu_get_post_mask(entry); 2708 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2709 2710 tmp = sh_eth_tsu_read(mdp, reg); 2711 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg); 2712 2713 /* If other port enables, the function returns "true" */ 2714 return tmp & ref_mask; 2715 } 2716 2717 static int sh_eth_tsu_busy(struct net_device *ndev) 2718 { 2719 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2720 struct sh_eth_private *mdp = netdev_priv(ndev); 2721 2722 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2723 udelay(10); 2724 timeout--; 2725 if (timeout <= 0) { 2726 netdev_err(ndev, "%s: timeout\n", __func__); 2727 return -ETIMEDOUT; 2728 } 2729 } 2730 2731 return 0; 2732 } 2733 2734 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2735 const u8 *addr) 2736 { 2737 u32 val; 2738 2739 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2740 iowrite32(val, reg); 2741 if (sh_eth_tsu_busy(ndev) < 0) 2742 return -EBUSY; 2743 2744 val = addr[4] << 8 | addr[5]; 2745 iowrite32(val, reg + 4); 2746 if (sh_eth_tsu_busy(ndev) < 0) 2747 return -EBUSY; 2748 2749 return 0; 2750 } 2751 2752 static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2753 { 2754 u32 val; 2755 2756 val = ioread32(reg); 2757 addr[0] = (val >> 24) & 0xff; 2758 addr[1] = (val >> 16) & 0xff; 2759 addr[2] = (val >> 8) & 0xff; 2760 addr[3] = val & 0xff; 2761 val = ioread32(reg + 4); 2762 addr[4] = (val >> 8) & 0xff; 2763 addr[5] = val & 0xff; 2764 } 2765 2766 2767 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2768 { 2769 struct sh_eth_private *mdp = netdev_priv(ndev); 2770 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2771 int i; 2772 u8 c_addr[ETH_ALEN]; 2773 2774 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2775 sh_eth_tsu_read_entry(reg_offset, c_addr); 2776 if (ether_addr_equal(addr, c_addr)) 2777 return i; 2778 } 2779 2780 return -ENOENT; 2781 } 2782 2783 static int sh_eth_tsu_find_empty(struct net_device *ndev) 2784 { 2785 u8 blank[ETH_ALEN]; 2786 int entry; 2787 2788 memset(blank, 0, sizeof(blank)); 2789 entry = sh_eth_tsu_find_entry(ndev, blank); 2790 return (entry < 0) ? -ENOMEM : entry; 2791 } 2792 2793 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2794 int entry) 2795 { 2796 struct sh_eth_private *mdp = netdev_priv(ndev); 2797 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2798 int ret; 2799 u8 blank[ETH_ALEN]; 2800 2801 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2802 ~(1 << (31 - entry)), TSU_TEN); 2803 2804 memset(blank, 0, sizeof(blank)); 2805 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2806 if (ret < 0) 2807 return ret; 2808 return 0; 2809 } 2810 2811 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2812 { 2813 struct sh_eth_private *mdp = netdev_priv(ndev); 2814 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2815 int i, ret; 2816 2817 if (!mdp->cd->tsu) 2818 return 0; 2819 2820 i = sh_eth_tsu_find_entry(ndev, addr); 2821 if (i < 0) { 2822 /* No entry found, create one */ 2823 i = sh_eth_tsu_find_empty(ndev); 2824 if (i < 0) 2825 return -ENOMEM; 2826 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2827 if (ret < 0) 2828 return ret; 2829 2830 /* Enable the entry */ 2831 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2832 (1 << (31 - i)), TSU_TEN); 2833 } 2834 2835 /* Entry found or created, enable POST */ 2836 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2837 2838 return 0; 2839 } 2840 2841 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2842 { 2843 struct sh_eth_private *mdp = netdev_priv(ndev); 2844 int i, ret; 2845 2846 if (!mdp->cd->tsu) 2847 return 0; 2848 2849 i = sh_eth_tsu_find_entry(ndev, addr); 2850 if (i) { 2851 /* Entry found */ 2852 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2853 goto done; 2854 2855 /* Disable the entry if both ports was disabled */ 2856 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2857 if (ret < 0) 2858 return ret; 2859 } 2860 done: 2861 return 0; 2862 } 2863 2864 static int sh_eth_tsu_purge_all(struct net_device *ndev) 2865 { 2866 struct sh_eth_private *mdp = netdev_priv(ndev); 2867 int i, ret; 2868 2869 if (!mdp->cd->tsu) 2870 return 0; 2871 2872 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2873 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2874 continue; 2875 2876 /* Disable the entry if both ports was disabled */ 2877 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2878 if (ret < 0) 2879 return ret; 2880 } 2881 2882 return 0; 2883 } 2884 2885 static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2886 { 2887 struct sh_eth_private *mdp = netdev_priv(ndev); 2888 u8 addr[ETH_ALEN]; 2889 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2890 int i; 2891 2892 if (!mdp->cd->tsu) 2893 return; 2894 2895 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2896 sh_eth_tsu_read_entry(reg_offset, addr); 2897 if (is_multicast_ether_addr(addr)) 2898 sh_eth_tsu_del_entry(ndev, addr); 2899 } 2900 } 2901 2902 /* Update promiscuous flag and multicast filter */ 2903 static void sh_eth_set_rx_mode(struct net_device *ndev) 2904 { 2905 struct sh_eth_private *mdp = netdev_priv(ndev); 2906 u32 ecmr_bits; 2907 int mcast_all = 0; 2908 unsigned long flags; 2909 2910 spin_lock_irqsave(&mdp->lock, flags); 2911 /* Initial condition is MCT = 1, PRM = 0. 2912 * Depending on ndev->flags, set PRM or clear MCT 2913 */ 2914 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM; 2915 if (mdp->cd->tsu) 2916 ecmr_bits |= ECMR_MCT; 2917 2918 if (!(ndev->flags & IFF_MULTICAST)) { 2919 sh_eth_tsu_purge_mcast(ndev); 2920 mcast_all = 1; 2921 } 2922 if (ndev->flags & IFF_ALLMULTI) { 2923 sh_eth_tsu_purge_mcast(ndev); 2924 ecmr_bits &= ~ECMR_MCT; 2925 mcast_all = 1; 2926 } 2927 2928 if (ndev->flags & IFF_PROMISC) { 2929 sh_eth_tsu_purge_all(ndev); 2930 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2931 } else if (mdp->cd->tsu) { 2932 struct netdev_hw_addr *ha; 2933 netdev_for_each_mc_addr(ha, ndev) { 2934 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2935 continue; 2936 2937 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2938 if (!mcast_all) { 2939 sh_eth_tsu_purge_mcast(ndev); 2940 ecmr_bits &= ~ECMR_MCT; 2941 mcast_all = 1; 2942 } 2943 } 2944 } 2945 } 2946 2947 /* update the ethernet mode */ 2948 sh_eth_write(ndev, ecmr_bits, ECMR); 2949 2950 spin_unlock_irqrestore(&mdp->lock, flags); 2951 } 2952 2953 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2954 { 2955 if (!mdp->port) 2956 return TSU_VTAG0; 2957 else 2958 return TSU_VTAG1; 2959 } 2960 2961 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2962 __be16 proto, u16 vid) 2963 { 2964 struct sh_eth_private *mdp = netdev_priv(ndev); 2965 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2966 2967 if (unlikely(!mdp->cd->tsu)) 2968 return -EPERM; 2969 2970 /* No filtering if vid = 0 */ 2971 if (!vid) 2972 return 0; 2973 2974 mdp->vlan_num_ids++; 2975 2976 /* The controller has one VLAN tag HW filter. So, if the filter is 2977 * already enabled, the driver disables it and the filte 2978 */ 2979 if (mdp->vlan_num_ids > 1) { 2980 /* disable VLAN filter */ 2981 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2982 return 0; 2983 } 2984 2985 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2986 vtag_reg_index); 2987 2988 return 0; 2989 } 2990 2991 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2992 __be16 proto, u16 vid) 2993 { 2994 struct sh_eth_private *mdp = netdev_priv(ndev); 2995 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2996 2997 if (unlikely(!mdp->cd->tsu)) 2998 return -EPERM; 2999 3000 /* No filtering if vid = 0 */ 3001 if (!vid) 3002 return 0; 3003 3004 mdp->vlan_num_ids--; 3005 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 3006 3007 return 0; 3008 } 3009 3010 /* SuperH's TSU register init function */ 3011 static void sh_eth_tsu_init(struct sh_eth_private *mdp) 3012 { 3013 if (!mdp->cd->dual_port) { 3014 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3015 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, 3016 TSU_FWSLC); /* Enable POST registers */ 3017 return; 3018 } 3019 3020 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 3021 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 3022 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 3023 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 3024 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 3025 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 3026 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 3027 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 3028 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 3029 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 3030 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 3031 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 3032 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 3033 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 3034 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 3035 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 3036 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 3037 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 3038 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 3039 } 3040 3041 /* MDIO bus release function */ 3042 static int sh_mdio_release(struct sh_eth_private *mdp) 3043 { 3044 /* unregister mdio bus */ 3045 mdiobus_unregister(mdp->mii_bus); 3046 3047 /* free bitbang info */ 3048 free_mdio_bitbang(mdp->mii_bus); 3049 3050 return 0; 3051 } 3052 3053 /* MDIO bus init function */ 3054 static int sh_mdio_init(struct sh_eth_private *mdp, 3055 struct sh_eth_plat_data *pd) 3056 { 3057 int ret; 3058 struct bb_info *bitbang; 3059 struct platform_device *pdev = mdp->pdev; 3060 struct device *dev = &mdp->pdev->dev; 3061 3062 /* create bit control struct for PHY */ 3063 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL); 3064 if (!bitbang) 3065 return -ENOMEM; 3066 3067 /* bitbang init */ 3068 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 3069 bitbang->set_gate = pd->set_mdio_gate; 3070 bitbang->ctrl.ops = &bb_ops; 3071 3072 /* MII controller setting */ 3073 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 3074 if (!mdp->mii_bus) 3075 return -ENOMEM; 3076 3077 /* Hook up MII support for ethtool */ 3078 mdp->mii_bus->name = "sh_mii"; 3079 mdp->mii_bus->parent = dev; 3080 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 3081 pdev->name, pdev->id); 3082 3083 /* register MDIO bus */ 3084 if (pd->phy_irq > 0) 3085 mdp->mii_bus->irq[pd->phy] = pd->phy_irq; 3086 3087 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node); 3088 if (ret) 3089 goto out_free_bus; 3090 3091 return 0; 3092 3093 out_free_bus: 3094 free_mdio_bitbang(mdp->mii_bus); 3095 return ret; 3096 } 3097 3098 static const u16 *sh_eth_get_register_offset(int register_type) 3099 { 3100 const u16 *reg_offset = NULL; 3101 3102 switch (register_type) { 3103 case SH_ETH_REG_GIGABIT: 3104 reg_offset = sh_eth_offset_gigabit; 3105 break; 3106 case SH_ETH_REG_FAST_RZ: 3107 reg_offset = sh_eth_offset_fast_rz; 3108 break; 3109 case SH_ETH_REG_FAST_RCAR: 3110 reg_offset = sh_eth_offset_fast_rcar; 3111 break; 3112 case SH_ETH_REG_FAST_SH4: 3113 reg_offset = sh_eth_offset_fast_sh4; 3114 break; 3115 case SH_ETH_REG_FAST_SH3_SH2: 3116 reg_offset = sh_eth_offset_fast_sh3_sh2; 3117 break; 3118 } 3119 3120 return reg_offset; 3121 } 3122 3123 static const struct net_device_ops sh_eth_netdev_ops = { 3124 .ndo_open = sh_eth_open, 3125 .ndo_stop = sh_eth_close, 3126 .ndo_start_xmit = sh_eth_start_xmit, 3127 .ndo_get_stats = sh_eth_get_stats, 3128 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3129 .ndo_tx_timeout = sh_eth_tx_timeout, 3130 .ndo_do_ioctl = sh_eth_do_ioctl, 3131 .ndo_change_mtu = sh_eth_change_mtu, 3132 .ndo_validate_addr = eth_validate_addr, 3133 .ndo_set_mac_address = eth_mac_addr, 3134 }; 3135 3136 static const struct net_device_ops sh_eth_netdev_ops_tsu = { 3137 .ndo_open = sh_eth_open, 3138 .ndo_stop = sh_eth_close, 3139 .ndo_start_xmit = sh_eth_start_xmit, 3140 .ndo_get_stats = sh_eth_get_stats, 3141 .ndo_set_rx_mode = sh_eth_set_rx_mode, 3142 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 3143 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 3144 .ndo_tx_timeout = sh_eth_tx_timeout, 3145 .ndo_do_ioctl = sh_eth_do_ioctl, 3146 .ndo_change_mtu = sh_eth_change_mtu, 3147 .ndo_validate_addr = eth_validate_addr, 3148 .ndo_set_mac_address = eth_mac_addr, 3149 }; 3150 3151 #ifdef CONFIG_OF 3152 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3153 { 3154 struct device_node *np = dev->of_node; 3155 struct sh_eth_plat_data *pdata; 3156 const char *mac_addr; 3157 3158 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 3159 if (!pdata) 3160 return NULL; 3161 3162 pdata->phy_interface = of_get_phy_mode(np); 3163 3164 mac_addr = of_get_mac_address(np); 3165 if (mac_addr) 3166 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 3167 3168 pdata->no_ether_link = 3169 of_property_read_bool(np, "renesas,no-ether-link"); 3170 pdata->ether_link_active_low = 3171 of_property_read_bool(np, "renesas,ether-link-active-low"); 3172 3173 return pdata; 3174 } 3175 3176 static const struct of_device_id sh_eth_match_table[] = { 3177 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data }, 3178 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data }, 3179 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data }, 3180 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data }, 3181 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data }, 3182 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data }, 3183 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data }, 3184 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data }, 3185 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data }, 3186 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data }, 3187 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data }, 3188 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data }, 3189 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data }, 3190 { } 3191 }; 3192 MODULE_DEVICE_TABLE(of, sh_eth_match_table); 3193 #else 3194 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev) 3195 { 3196 return NULL; 3197 } 3198 #endif 3199 3200 static int sh_eth_drv_probe(struct platform_device *pdev) 3201 { 3202 struct resource *res; 3203 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 3204 const struct platform_device_id *id = platform_get_device_id(pdev); 3205 struct sh_eth_private *mdp; 3206 struct net_device *ndev; 3207 int ret; 3208 3209 /* get base addr */ 3210 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3211 3212 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 3213 if (!ndev) 3214 return -ENOMEM; 3215 3216 pm_runtime_enable(&pdev->dev); 3217 pm_runtime_get_sync(&pdev->dev); 3218 3219 ret = platform_get_irq(pdev, 0); 3220 if (ret < 0) 3221 goto out_release; 3222 ndev->irq = ret; 3223 3224 SET_NETDEV_DEV(ndev, &pdev->dev); 3225 3226 mdp = netdev_priv(ndev); 3227 mdp->num_tx_ring = TX_RING_SIZE; 3228 mdp->num_rx_ring = RX_RING_SIZE; 3229 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 3230 if (IS_ERR(mdp->addr)) { 3231 ret = PTR_ERR(mdp->addr); 3232 goto out_release; 3233 } 3234 3235 ndev->base_addr = res->start; 3236 3237 spin_lock_init(&mdp->lock); 3238 mdp->pdev = pdev; 3239 3240 if (pdev->dev.of_node) 3241 pd = sh_eth_parse_dt(&pdev->dev); 3242 if (!pd) { 3243 dev_err(&pdev->dev, "no platform data\n"); 3244 ret = -EINVAL; 3245 goto out_release; 3246 } 3247 3248 /* get PHY ID */ 3249 mdp->phy_id = pd->phy; 3250 mdp->phy_interface = pd->phy_interface; 3251 mdp->no_ether_link = pd->no_ether_link; 3252 mdp->ether_link_active_low = pd->ether_link_active_low; 3253 3254 /* set cpu data */ 3255 if (id) 3256 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 3257 else 3258 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev); 3259 3260 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 3261 if (!mdp->reg_offset) { 3262 dev_err(&pdev->dev, "Unknown register type (%d)\n", 3263 mdp->cd->register_type); 3264 ret = -EINVAL; 3265 goto out_release; 3266 } 3267 sh_eth_set_default_cpu_data(mdp->cd); 3268 3269 /* User's manual states max MTU should be 2048 but due to the 3270 * alignment calculations in sh_eth_ring_init() the practical 3271 * MTU is a bit less. Maybe this can be optimized some more. 3272 */ 3273 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3274 ndev->min_mtu = ETH_MIN_MTU; 3275 3276 /* set function */ 3277 if (mdp->cd->tsu) 3278 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 3279 else 3280 ndev->netdev_ops = &sh_eth_netdev_ops; 3281 ndev->ethtool_ops = &sh_eth_ethtool_ops; 3282 ndev->watchdog_timeo = TX_TIMEOUT; 3283 3284 /* debug message level */ 3285 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 3286 3287 /* read and set MAC address */ 3288 read_mac_address(ndev, pd->mac_addr); 3289 if (!is_valid_ether_addr(ndev->dev_addr)) { 3290 dev_warn(&pdev->dev, 3291 "no valid MAC address supplied, using a random one.\n"); 3292 eth_hw_addr_random(ndev); 3293 } 3294 3295 if (mdp->cd->tsu) { 3296 int port = pdev->id < 0 ? 0 : pdev->id % 2; 3297 struct resource *rtsu; 3298 3299 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 3300 if (!rtsu) { 3301 dev_err(&pdev->dev, "no TSU resource\n"); 3302 ret = -ENODEV; 3303 goto out_release; 3304 } 3305 /* We can only request the TSU region for the first port 3306 * of the two sharing this TSU for the probe to succeed... 3307 */ 3308 if (port == 0 && 3309 !devm_request_mem_region(&pdev->dev, rtsu->start, 3310 resource_size(rtsu), 3311 dev_name(&pdev->dev))) { 3312 dev_err(&pdev->dev, "can't request TSU resource.\n"); 3313 ret = -EBUSY; 3314 goto out_release; 3315 } 3316 /* ioremap the TSU registers */ 3317 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start, 3318 resource_size(rtsu)); 3319 if (!mdp->tsu_addr) { 3320 dev_err(&pdev->dev, "TSU region ioremap() failed.\n"); 3321 ret = -ENOMEM; 3322 goto out_release; 3323 } 3324 mdp->port = port; 3325 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 3326 3327 /* Need to init only the first port of the two sharing a TSU */ 3328 if (port == 0) { 3329 if (mdp->cd->chip_reset) 3330 mdp->cd->chip_reset(ndev); 3331 3332 /* TSU init (Init only)*/ 3333 sh_eth_tsu_init(mdp); 3334 } 3335 } 3336 3337 if (mdp->cd->rmiimode) 3338 sh_eth_write(ndev, 0x1, RMIIMODE); 3339 3340 /* MDIO bus init */ 3341 ret = sh_mdio_init(mdp, pd); 3342 if (ret) { 3343 if (ret != -EPROBE_DEFER) 3344 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret); 3345 goto out_release; 3346 } 3347 3348 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 3349 3350 /* network device register */ 3351 ret = register_netdev(ndev); 3352 if (ret) 3353 goto out_napi_del; 3354 3355 if (mdp->cd->magic) 3356 device_set_wakeup_capable(&pdev->dev, 1); 3357 3358 /* print device information */ 3359 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n", 3360 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3361 3362 pm_runtime_put(&pdev->dev); 3363 platform_set_drvdata(pdev, ndev); 3364 3365 return ret; 3366 3367 out_napi_del: 3368 netif_napi_del(&mdp->napi); 3369 sh_mdio_release(mdp); 3370 3371 out_release: 3372 /* net_dev free */ 3373 free_netdev(ndev); 3374 3375 pm_runtime_put(&pdev->dev); 3376 pm_runtime_disable(&pdev->dev); 3377 return ret; 3378 } 3379 3380 static int sh_eth_drv_remove(struct platform_device *pdev) 3381 { 3382 struct net_device *ndev = platform_get_drvdata(pdev); 3383 struct sh_eth_private *mdp = netdev_priv(ndev); 3384 3385 unregister_netdev(ndev); 3386 netif_napi_del(&mdp->napi); 3387 sh_mdio_release(mdp); 3388 pm_runtime_disable(&pdev->dev); 3389 free_netdev(ndev); 3390 3391 return 0; 3392 } 3393 3394 #ifdef CONFIG_PM 3395 #ifdef CONFIG_PM_SLEEP 3396 static int sh_eth_wol_setup(struct net_device *ndev) 3397 { 3398 struct sh_eth_private *mdp = netdev_priv(ndev); 3399 3400 /* Only allow ECI interrupts */ 3401 synchronize_irq(ndev->irq); 3402 napi_disable(&mdp->napi); 3403 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR); 3404 3405 /* Enable MagicPacket */ 3406 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3407 3408 return enable_irq_wake(ndev->irq); 3409 } 3410 3411 static int sh_eth_wol_restore(struct net_device *ndev) 3412 { 3413 struct sh_eth_private *mdp = netdev_priv(ndev); 3414 int ret; 3415 3416 napi_enable(&mdp->napi); 3417 3418 /* Disable MagicPacket */ 3419 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0); 3420 3421 /* The device needs to be reset to restore MagicPacket logic 3422 * for next wakeup. If we close and open the device it will 3423 * both be reset and all registers restored. This is what 3424 * happens during suspend and resume without WoL enabled. 3425 */ 3426 ret = sh_eth_close(ndev); 3427 if (ret < 0) 3428 return ret; 3429 ret = sh_eth_open(ndev); 3430 if (ret < 0) 3431 return ret; 3432 3433 return disable_irq_wake(ndev->irq); 3434 } 3435 3436 static int sh_eth_suspend(struct device *dev) 3437 { 3438 struct net_device *ndev = dev_get_drvdata(dev); 3439 struct sh_eth_private *mdp = netdev_priv(ndev); 3440 int ret = 0; 3441 3442 if (!netif_running(ndev)) 3443 return 0; 3444 3445 netif_device_detach(ndev); 3446 3447 if (mdp->wol_enabled) 3448 ret = sh_eth_wol_setup(ndev); 3449 else 3450 ret = sh_eth_close(ndev); 3451 3452 return ret; 3453 } 3454 3455 static int sh_eth_resume(struct device *dev) 3456 { 3457 struct net_device *ndev = dev_get_drvdata(dev); 3458 struct sh_eth_private *mdp = netdev_priv(ndev); 3459 int ret = 0; 3460 3461 if (!netif_running(ndev)) 3462 return 0; 3463 3464 if (mdp->wol_enabled) 3465 ret = sh_eth_wol_restore(ndev); 3466 else 3467 ret = sh_eth_open(ndev); 3468 3469 if (ret < 0) 3470 return ret; 3471 3472 netif_device_attach(ndev); 3473 3474 return ret; 3475 } 3476 #endif 3477 3478 static int sh_eth_runtime_nop(struct device *dev) 3479 { 3480 /* Runtime PM callback shared between ->runtime_suspend() 3481 * and ->runtime_resume(). Simply returns success. 3482 * 3483 * This driver re-initializes all registers after 3484 * pm_runtime_get_sync() anyway so there is no need 3485 * to save and restore registers here. 3486 */ 3487 return 0; 3488 } 3489 3490 static const struct dev_pm_ops sh_eth_dev_pm_ops = { 3491 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume) 3492 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL) 3493 }; 3494 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 3495 #else 3496 #define SH_ETH_PM_OPS NULL 3497 #endif 3498 3499 static const struct platform_device_id sh_eth_id_table[] = { 3500 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 3501 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 3502 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 3503 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 3504 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 3505 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 3506 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 3507 { } 3508 }; 3509 MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 3510 3511 static struct platform_driver sh_eth_driver = { 3512 .probe = sh_eth_drv_probe, 3513 .remove = sh_eth_drv_remove, 3514 .id_table = sh_eth_id_table, 3515 .driver = { 3516 .name = CARDNAME, 3517 .pm = SH_ETH_PM_OPS, 3518 .of_match_table = of_match_ptr(sh_eth_match_table), 3519 }, 3520 }; 3521 3522 module_platform_driver(sh_eth_driver); 3523 3524 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 3525 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 3526 MODULE_LICENSE("GPL v2"); 3527