1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet Switch device driver 3 * 4 * Copyright (C) 2022 Renesas Electronics Corporation 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/etherdevice.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/of.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/rtnetlink.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <linux/sys_soc.h> 26 27 #include "rswitch.h" 28 29 static int rswitch_reg_wait(void __iomem *addr, u32 offs, u32 mask, u32 expected) 30 { 31 u32 val; 32 33 return readl_poll_timeout_atomic(addr + offs, val, (val & mask) == expected, 34 1, RSWITCH_TIMEOUT_US); 35 } 36 37 static void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set) 38 { 39 iowrite32((ioread32(addr + reg) & ~clear) | set, addr + reg); 40 } 41 42 /* Common Agent block (COMA) */ 43 static void rswitch_reset(struct rswitch_private *priv) 44 { 45 iowrite32(RRC_RR, priv->addr + RRC); 46 iowrite32(RRC_RR_CLR, priv->addr + RRC); 47 } 48 49 static void rswitch_clock_enable(struct rswitch_private *priv) 50 { 51 iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC); 52 } 53 54 static void rswitch_clock_disable(struct rswitch_private *priv) 55 { 56 iowrite32(RCDC_RCD, priv->addr + RCDC); 57 } 58 59 static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr, 60 unsigned int port) 61 { 62 u32 val = ioread32(coma_addr + RCEC); 63 64 if (val & RCEC_RCE) 65 return (val & BIT(port)) ? true : false; 66 else 67 return false; 68 } 69 70 static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, unsigned int port, 71 int enable) 72 { 73 u32 val; 74 75 if (enable) { 76 val = ioread32(coma_addr + RCEC); 77 iowrite32(val | RCEC_RCE | BIT(port), coma_addr + RCEC); 78 } else { 79 val = ioread32(coma_addr + RCDC); 80 iowrite32(val | BIT(port), coma_addr + RCDC); 81 } 82 } 83 84 static int rswitch_bpool_config(struct rswitch_private *priv) 85 { 86 u32 val; 87 88 val = ioread32(priv->addr + CABPIRM); 89 if (val & CABPIRM_BPR) 90 return 0; 91 92 iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM); 93 94 return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR); 95 } 96 97 static void rswitch_coma_init(struct rswitch_private *priv) 98 { 99 iowrite32(CABPPFLC_INIT_VALUE, priv->addr + CABPPFLC0); 100 } 101 102 /* R-Switch-2 block (TOP) */ 103 static void rswitch_top_init(struct rswitch_private *priv) 104 { 105 unsigned int i; 106 107 for (i = 0; i < RSWITCH_MAX_NUM_QUEUES; i++) 108 iowrite32((i / 16) << (GWCA_INDEX * 8), priv->addr + TPEMIMC7(i)); 109 } 110 111 /* Forwarding engine block (MFWD) */ 112 static void rswitch_fwd_init(struct rswitch_private *priv) 113 { 114 unsigned int i; 115 116 /* For ETHA */ 117 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 118 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i)); 119 iowrite32(0, priv->addr + FWPBFC(i)); 120 } 121 122 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 123 iowrite32(priv->rdev[i]->rx_queue->index, 124 priv->addr + FWPBFCSDC(GWCA_INDEX, i)); 125 iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i)); 126 } 127 128 /* For GWCA */ 129 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index)); 130 iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index)); 131 iowrite32(0, priv->addr + FWPBFC(priv->gwca.index)); 132 iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index)); 133 } 134 135 /* Gateway CPU agent block (GWCA) */ 136 static int rswitch_gwca_change_mode(struct rswitch_private *priv, 137 enum rswitch_gwca_mode mode) 138 { 139 int ret; 140 141 if (!rswitch_agent_clock_is_enabled(priv->addr, priv->gwca.index)) 142 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 1); 143 144 iowrite32(mode, priv->addr + GWMC); 145 146 ret = rswitch_reg_wait(priv->addr, GWMS, GWMS_OPS_MASK, mode); 147 148 if (mode == GWMC_OPC_DISABLE) 149 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 0); 150 151 return ret; 152 } 153 154 static int rswitch_gwca_mcast_table_reset(struct rswitch_private *priv) 155 { 156 iowrite32(GWMTIRM_MTIOG, priv->addr + GWMTIRM); 157 158 return rswitch_reg_wait(priv->addr, GWMTIRM, GWMTIRM_MTR, GWMTIRM_MTR); 159 } 160 161 static int rswitch_gwca_axi_ram_reset(struct rswitch_private *priv) 162 { 163 iowrite32(GWARIRM_ARIOG, priv->addr + GWARIRM); 164 165 return rswitch_reg_wait(priv->addr, GWARIRM, GWARIRM_ARR, GWARIRM_ARR); 166 } 167 168 static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool tx) 169 { 170 u32 *mask = tx ? priv->gwca.tx_irq_bits : priv->gwca.rx_irq_bits; 171 unsigned int i; 172 173 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 174 if (dis[i] & mask[i]) 175 return true; 176 } 177 178 return false; 179 } 180 181 static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis) 182 { 183 unsigned int i; 184 185 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 186 dis[i] = ioread32(priv->addr + GWDIS(i)); 187 dis[i] &= ioread32(priv->addr + GWDIE(i)); 188 } 189 } 190 191 static void rswitch_enadis_data_irq(struct rswitch_private *priv, 192 unsigned int index, bool enable) 193 { 194 u32 offs = enable ? GWDIE(index / 32) : GWDID(index / 32); 195 196 iowrite32(BIT(index % 32), priv->addr + offs); 197 } 198 199 static void rswitch_ack_data_irq(struct rswitch_private *priv, 200 unsigned int index) 201 { 202 u32 offs = GWDIS(index / 32); 203 204 iowrite32(BIT(index % 32), priv->addr + offs); 205 } 206 207 static unsigned int rswitch_next_queue_index(struct rswitch_gwca_queue *gq, 208 bool cur, unsigned int num) 209 { 210 unsigned int index = cur ? gq->cur : gq->dirty; 211 212 if (index + num >= gq->ring_size) 213 index = (index + num) % gq->ring_size; 214 else 215 index += num; 216 217 return index; 218 } 219 220 static unsigned int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq) 221 { 222 if (gq->cur >= gq->dirty) 223 return gq->cur - gq->dirty; 224 else 225 return gq->ring_size - gq->dirty + gq->cur; 226 } 227 228 static bool rswitch_is_queue_rxed(struct rswitch_gwca_queue *gq) 229 { 230 struct rswitch_ext_ts_desc *desc = &gq->rx_ring[gq->dirty]; 231 232 if ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) 233 return true; 234 235 return false; 236 } 237 238 static int rswitch_gwca_queue_alloc_rx_buf(struct rswitch_gwca_queue *gq, 239 unsigned int start_index, 240 unsigned int num) 241 { 242 unsigned int i, index; 243 244 for (i = 0; i < num; i++) { 245 index = (i + start_index) % gq->ring_size; 246 if (gq->rx_bufs[index]) 247 continue; 248 gq->rx_bufs[index] = netdev_alloc_frag(RSWITCH_BUF_SIZE); 249 if (!gq->rx_bufs[index]) 250 goto err; 251 } 252 253 return 0; 254 255 err: 256 for (; i-- > 0; ) { 257 index = (i + start_index) % gq->ring_size; 258 skb_free_frag(gq->rx_bufs[index]); 259 gq->rx_bufs[index] = NULL; 260 } 261 262 return -ENOMEM; 263 } 264 265 static void rswitch_gwca_queue_free(struct net_device *ndev, 266 struct rswitch_gwca_queue *gq) 267 { 268 unsigned int i; 269 270 if (!gq->dir_tx) { 271 dma_free_coherent(ndev->dev.parent, 272 sizeof(struct rswitch_ext_ts_desc) * 273 (gq->ring_size + 1), gq->rx_ring, gq->ring_dma); 274 gq->rx_ring = NULL; 275 276 for (i = 0; i < gq->ring_size; i++) 277 skb_free_frag(gq->rx_bufs[i]); 278 kfree(gq->rx_bufs); 279 gq->rx_bufs = NULL; 280 } else { 281 dma_free_coherent(ndev->dev.parent, 282 sizeof(struct rswitch_ext_desc) * 283 (gq->ring_size + 1), gq->tx_ring, gq->ring_dma); 284 gq->tx_ring = NULL; 285 kfree(gq->skbs); 286 gq->skbs = NULL; 287 kfree(gq->unmap_addrs); 288 gq->unmap_addrs = NULL; 289 } 290 } 291 292 static void rswitch_gwca_ts_queue_free(struct rswitch_private *priv) 293 { 294 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 295 296 dma_free_coherent(&priv->pdev->dev, 297 sizeof(struct rswitch_ts_desc) * (gq->ring_size + 1), 298 gq->ts_ring, gq->ring_dma); 299 gq->ts_ring = NULL; 300 } 301 302 static int rswitch_gwca_queue_alloc(struct net_device *ndev, 303 struct rswitch_private *priv, 304 struct rswitch_gwca_queue *gq, 305 bool dir_tx, unsigned int ring_size) 306 { 307 unsigned int i, bit; 308 309 gq->dir_tx = dir_tx; 310 gq->ring_size = ring_size; 311 gq->ndev = ndev; 312 313 if (!dir_tx) { 314 gq->rx_bufs = kcalloc(gq->ring_size, sizeof(*gq->rx_bufs), GFP_KERNEL); 315 if (!gq->rx_bufs) 316 return -ENOMEM; 317 if (rswitch_gwca_queue_alloc_rx_buf(gq, 0, gq->ring_size) < 0) 318 goto out; 319 320 gq->rx_ring = dma_alloc_coherent(ndev->dev.parent, 321 sizeof(struct rswitch_ext_ts_desc) * 322 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 323 } else { 324 gq->skbs = kcalloc(gq->ring_size, sizeof(*gq->skbs), GFP_KERNEL); 325 if (!gq->skbs) 326 return -ENOMEM; 327 gq->unmap_addrs = kcalloc(gq->ring_size, sizeof(*gq->unmap_addrs), GFP_KERNEL); 328 if (!gq->unmap_addrs) 329 goto out; 330 gq->tx_ring = dma_alloc_coherent(ndev->dev.parent, 331 sizeof(struct rswitch_ext_desc) * 332 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 333 } 334 335 if (!gq->rx_ring && !gq->tx_ring) 336 goto out; 337 338 i = gq->index / 32; 339 bit = BIT(gq->index % 32); 340 if (dir_tx) 341 priv->gwca.tx_irq_bits[i] |= bit; 342 else 343 priv->gwca.rx_irq_bits[i] |= bit; 344 345 return 0; 346 347 out: 348 rswitch_gwca_queue_free(ndev, gq); 349 350 return -ENOMEM; 351 } 352 353 static void rswitch_desc_set_dptr(struct rswitch_desc *desc, dma_addr_t addr) 354 { 355 desc->dptrl = cpu_to_le32(lower_32_bits(addr)); 356 desc->dptrh = upper_32_bits(addr) & 0xff; 357 } 358 359 static dma_addr_t rswitch_desc_get_dptr(const struct rswitch_desc *desc) 360 { 361 return __le32_to_cpu(desc->dptrl) | (u64)(desc->dptrh) << 32; 362 } 363 364 static int rswitch_gwca_queue_format(struct net_device *ndev, 365 struct rswitch_private *priv, 366 struct rswitch_gwca_queue *gq) 367 { 368 unsigned int ring_size = sizeof(struct rswitch_ext_desc) * gq->ring_size; 369 struct rswitch_ext_desc *desc; 370 struct rswitch_desc *linkfix; 371 dma_addr_t dma_addr; 372 unsigned int i; 373 374 memset(gq->tx_ring, 0, ring_size); 375 for (i = 0, desc = gq->tx_ring; i < gq->ring_size; i++, desc++) { 376 if (!gq->dir_tx) { 377 dma_addr = dma_map_single(ndev->dev.parent, 378 gq->rx_bufs[i] + RSWITCH_HEADROOM, 379 RSWITCH_MAP_BUF_SIZE, 380 DMA_FROM_DEVICE); 381 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 382 goto err; 383 384 desc->desc.info_ds = cpu_to_le16(RSWITCH_DESC_BUF_SIZE); 385 rswitch_desc_set_dptr(&desc->desc, dma_addr); 386 desc->desc.die_dt = DT_FEMPTY | DIE; 387 } else { 388 desc->desc.die_dt = DT_EEMPTY | DIE; 389 } 390 } 391 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 392 desc->desc.die_dt = DT_LINKFIX; 393 394 linkfix = &priv->gwca.linkfix_table[gq->index]; 395 linkfix->die_dt = DT_LINKFIX; 396 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 397 398 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DCP(GWCA_IPV_NUM) | GWDCC_DQT : 0) | GWDCC_EDE, 399 priv->addr + GWDCC_OFFS(gq->index)); 400 401 return 0; 402 403 err: 404 if (!gq->dir_tx) { 405 for (desc = gq->tx_ring; i-- > 0; desc++) { 406 dma_addr = rswitch_desc_get_dptr(&desc->desc); 407 dma_unmap_single(ndev->dev.parent, dma_addr, 408 RSWITCH_MAP_BUF_SIZE, DMA_FROM_DEVICE); 409 } 410 } 411 412 return -ENOMEM; 413 } 414 415 static void rswitch_gwca_ts_queue_fill(struct rswitch_private *priv, 416 unsigned int start_index, 417 unsigned int num) 418 { 419 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 420 struct rswitch_ts_desc *desc; 421 unsigned int i, index; 422 423 for (i = 0; i < num; i++) { 424 index = (i + start_index) % gq->ring_size; 425 desc = &gq->ts_ring[index]; 426 desc->desc.die_dt = DT_FEMPTY_ND | DIE; 427 } 428 } 429 430 static int rswitch_gwca_queue_ext_ts_fill(struct net_device *ndev, 431 struct rswitch_gwca_queue *gq, 432 unsigned int start_index, 433 unsigned int num) 434 { 435 struct rswitch_device *rdev = netdev_priv(ndev); 436 struct rswitch_ext_ts_desc *desc; 437 unsigned int i, index; 438 dma_addr_t dma_addr; 439 440 for (i = 0; i < num; i++) { 441 index = (i + start_index) % gq->ring_size; 442 desc = &gq->rx_ring[index]; 443 if (!gq->dir_tx) { 444 dma_addr = dma_map_single(ndev->dev.parent, 445 gq->rx_bufs[index] + RSWITCH_HEADROOM, 446 RSWITCH_MAP_BUF_SIZE, 447 DMA_FROM_DEVICE); 448 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 449 goto err; 450 451 desc->desc.info_ds = cpu_to_le16(RSWITCH_DESC_BUF_SIZE); 452 rswitch_desc_set_dptr(&desc->desc, dma_addr); 453 dma_wmb(); 454 desc->desc.die_dt = DT_FEMPTY | DIE; 455 desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index)); 456 } else { 457 desc->desc.die_dt = DT_EEMPTY | DIE; 458 } 459 } 460 461 return 0; 462 463 err: 464 if (!gq->dir_tx) { 465 for (; i-- > 0; ) { 466 index = (i + start_index) % gq->ring_size; 467 desc = &gq->rx_ring[index]; 468 dma_addr = rswitch_desc_get_dptr(&desc->desc); 469 dma_unmap_single(ndev->dev.parent, dma_addr, 470 RSWITCH_MAP_BUF_SIZE, DMA_FROM_DEVICE); 471 } 472 } 473 474 return -ENOMEM; 475 } 476 477 static int rswitch_gwca_queue_ext_ts_format(struct net_device *ndev, 478 struct rswitch_private *priv, 479 struct rswitch_gwca_queue *gq) 480 { 481 unsigned int ring_size = sizeof(struct rswitch_ext_ts_desc) * gq->ring_size; 482 struct rswitch_ext_ts_desc *desc; 483 struct rswitch_desc *linkfix; 484 int err; 485 486 memset(gq->rx_ring, 0, ring_size); 487 err = rswitch_gwca_queue_ext_ts_fill(ndev, gq, 0, gq->ring_size); 488 if (err < 0) 489 return err; 490 491 desc = &gq->rx_ring[gq->ring_size]; /* Last */ 492 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 493 desc->desc.die_dt = DT_LINKFIX; 494 495 linkfix = &priv->gwca.linkfix_table[gq->index]; 496 linkfix->die_dt = DT_LINKFIX; 497 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 498 499 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DCP(GWCA_IPV_NUM) | GWDCC_DQT : 0) | 500 GWDCC_ETS | GWDCC_EDE, 501 priv->addr + GWDCC_OFFS(gq->index)); 502 503 return 0; 504 } 505 506 static int rswitch_gwca_linkfix_alloc(struct rswitch_private *priv) 507 { 508 unsigned int i, num_queues = priv->gwca.num_queues; 509 struct rswitch_gwca *gwca = &priv->gwca; 510 struct device *dev = &priv->pdev->dev; 511 512 gwca->linkfix_table_size = sizeof(struct rswitch_desc) * num_queues; 513 gwca->linkfix_table = dma_alloc_coherent(dev, gwca->linkfix_table_size, 514 &gwca->linkfix_table_dma, GFP_KERNEL); 515 if (!gwca->linkfix_table) 516 return -ENOMEM; 517 for (i = 0; i < num_queues; i++) 518 gwca->linkfix_table[i].die_dt = DT_EOS; 519 520 return 0; 521 } 522 523 static void rswitch_gwca_linkfix_free(struct rswitch_private *priv) 524 { 525 struct rswitch_gwca *gwca = &priv->gwca; 526 527 if (gwca->linkfix_table) 528 dma_free_coherent(&priv->pdev->dev, gwca->linkfix_table_size, 529 gwca->linkfix_table, gwca->linkfix_table_dma); 530 gwca->linkfix_table = NULL; 531 } 532 533 static int rswitch_gwca_ts_queue_alloc(struct rswitch_private *priv) 534 { 535 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 536 struct rswitch_ts_desc *desc; 537 538 gq->ring_size = TS_RING_SIZE; 539 gq->ts_ring = dma_alloc_coherent(&priv->pdev->dev, 540 sizeof(struct rswitch_ts_desc) * 541 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 542 543 if (!gq->ts_ring) 544 return -ENOMEM; 545 546 rswitch_gwca_ts_queue_fill(priv, 0, TS_RING_SIZE); 547 desc = &gq->ts_ring[gq->ring_size]; 548 desc->desc.die_dt = DT_LINKFIX; 549 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 550 INIT_LIST_HEAD(&priv->gwca.ts_info_list); 551 552 return 0; 553 } 554 555 static struct rswitch_gwca_queue *rswitch_gwca_get(struct rswitch_private *priv) 556 { 557 struct rswitch_gwca_queue *gq; 558 unsigned int index; 559 560 index = find_first_zero_bit(priv->gwca.used, priv->gwca.num_queues); 561 if (index >= priv->gwca.num_queues) 562 return NULL; 563 set_bit(index, priv->gwca.used); 564 gq = &priv->gwca.queues[index]; 565 memset(gq, 0, sizeof(*gq)); 566 gq->index = index; 567 568 return gq; 569 } 570 571 static void rswitch_gwca_put(struct rswitch_private *priv, 572 struct rswitch_gwca_queue *gq) 573 { 574 clear_bit(gq->index, priv->gwca.used); 575 } 576 577 static int rswitch_txdmac_alloc(struct net_device *ndev) 578 { 579 struct rswitch_device *rdev = netdev_priv(ndev); 580 struct rswitch_private *priv = rdev->priv; 581 int err; 582 583 rdev->tx_queue = rswitch_gwca_get(priv); 584 if (!rdev->tx_queue) 585 return -EBUSY; 586 587 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->tx_queue, true, TX_RING_SIZE); 588 if (err < 0) { 589 rswitch_gwca_put(priv, rdev->tx_queue); 590 return err; 591 } 592 593 return 0; 594 } 595 596 static void rswitch_txdmac_free(struct net_device *ndev) 597 { 598 struct rswitch_device *rdev = netdev_priv(ndev); 599 600 rswitch_gwca_queue_free(ndev, rdev->tx_queue); 601 rswitch_gwca_put(rdev->priv, rdev->tx_queue); 602 } 603 604 static int rswitch_txdmac_init(struct rswitch_private *priv, unsigned int index) 605 { 606 struct rswitch_device *rdev = priv->rdev[index]; 607 608 return rswitch_gwca_queue_format(rdev->ndev, priv, rdev->tx_queue); 609 } 610 611 static int rswitch_rxdmac_alloc(struct net_device *ndev) 612 { 613 struct rswitch_device *rdev = netdev_priv(ndev); 614 struct rswitch_private *priv = rdev->priv; 615 int err; 616 617 rdev->rx_queue = rswitch_gwca_get(priv); 618 if (!rdev->rx_queue) 619 return -EBUSY; 620 621 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->rx_queue, false, RX_RING_SIZE); 622 if (err < 0) { 623 rswitch_gwca_put(priv, rdev->rx_queue); 624 return err; 625 } 626 627 return 0; 628 } 629 630 static void rswitch_rxdmac_free(struct net_device *ndev) 631 { 632 struct rswitch_device *rdev = netdev_priv(ndev); 633 634 rswitch_gwca_queue_free(ndev, rdev->rx_queue); 635 rswitch_gwca_put(rdev->priv, rdev->rx_queue); 636 } 637 638 static int rswitch_rxdmac_init(struct rswitch_private *priv, unsigned int index) 639 { 640 struct rswitch_device *rdev = priv->rdev[index]; 641 struct net_device *ndev = rdev->ndev; 642 643 return rswitch_gwca_queue_ext_ts_format(ndev, priv, rdev->rx_queue); 644 } 645 646 static int rswitch_gwca_hw_init(struct rswitch_private *priv) 647 { 648 unsigned int i; 649 int err; 650 651 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 652 if (err < 0) 653 return err; 654 err = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG); 655 if (err < 0) 656 return err; 657 658 err = rswitch_gwca_mcast_table_reset(priv); 659 if (err < 0) 660 return err; 661 err = rswitch_gwca_axi_ram_reset(priv); 662 if (err < 0) 663 return err; 664 665 iowrite32(GWVCC_VEM_SC_TAG, priv->addr + GWVCC); 666 iowrite32(0, priv->addr + GWTTFC); 667 iowrite32(lower_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC1); 668 iowrite32(upper_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC0); 669 iowrite32(lower_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC10); 670 iowrite32(upper_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC00); 671 iowrite32(GWMDNC_TSDMN(1) | GWMDNC_TXDMN(0x1e) | GWMDNC_RXDMN(0x1f), 672 priv->addr + GWMDNC); 673 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDCC0); 674 675 iowrite32(GWTPC_PPPL(GWCA_IPV_NUM), priv->addr + GWTPC0); 676 677 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 678 err = rswitch_rxdmac_init(priv, i); 679 if (err < 0) 680 return err; 681 err = rswitch_txdmac_init(priv, i); 682 if (err < 0) 683 return err; 684 } 685 686 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 687 if (err < 0) 688 return err; 689 return rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION); 690 } 691 692 static int rswitch_gwca_hw_deinit(struct rswitch_private *priv) 693 { 694 int err; 695 696 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 697 if (err < 0) 698 return err; 699 err = rswitch_gwca_change_mode(priv, GWMC_OPC_RESET); 700 if (err < 0) 701 return err; 702 703 return rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 704 } 705 706 static int rswitch_gwca_halt(struct rswitch_private *priv) 707 { 708 int err; 709 710 priv->gwca_halt = true; 711 err = rswitch_gwca_hw_deinit(priv); 712 dev_err(&priv->pdev->dev, "halted (%d)\n", err); 713 714 return err; 715 } 716 717 static struct sk_buff *rswitch_rx_handle_desc(struct net_device *ndev, 718 struct rswitch_gwca_queue *gq, 719 struct rswitch_ext_ts_desc *desc) 720 { 721 dma_addr_t dma_addr = rswitch_desc_get_dptr(&desc->desc); 722 u16 pkt_len = le16_to_cpu(desc->desc.info_ds) & RX_DS; 723 u8 die_dt = desc->desc.die_dt & DT_MASK; 724 struct sk_buff *skb = NULL; 725 726 dma_unmap_single(ndev->dev.parent, dma_addr, RSWITCH_MAP_BUF_SIZE, 727 DMA_FROM_DEVICE); 728 729 /* The RX descriptor order will be one of the following: 730 * - FSINGLE 731 * - FSTART -> FEND 732 * - FSTART -> FMID -> FEND 733 */ 734 735 /* Check whether the descriptor is unexpected order */ 736 switch (die_dt) { 737 case DT_FSTART: 738 case DT_FSINGLE: 739 if (gq->skb_fstart) { 740 dev_kfree_skb_any(gq->skb_fstart); 741 gq->skb_fstart = NULL; 742 ndev->stats.rx_dropped++; 743 } 744 break; 745 case DT_FMID: 746 case DT_FEND: 747 if (!gq->skb_fstart) { 748 ndev->stats.rx_dropped++; 749 return NULL; 750 } 751 break; 752 default: 753 break; 754 } 755 756 /* Handle the descriptor */ 757 switch (die_dt) { 758 case DT_FSTART: 759 case DT_FSINGLE: 760 skb = build_skb(gq->rx_bufs[gq->cur], RSWITCH_BUF_SIZE); 761 if (skb) { 762 skb_reserve(skb, RSWITCH_HEADROOM); 763 skb_put(skb, pkt_len); 764 gq->pkt_len = pkt_len; 765 if (die_dt == DT_FSTART) { 766 gq->skb_fstart = skb; 767 skb = NULL; 768 } 769 } 770 break; 771 case DT_FMID: 772 case DT_FEND: 773 skb_add_rx_frag(gq->skb_fstart, skb_shinfo(gq->skb_fstart)->nr_frags, 774 virt_to_page(gq->rx_bufs[gq->cur]), 775 offset_in_page(gq->rx_bufs[gq->cur]) + RSWITCH_HEADROOM, 776 pkt_len, RSWITCH_BUF_SIZE); 777 if (die_dt == DT_FEND) { 778 skb = gq->skb_fstart; 779 gq->skb_fstart = NULL; 780 } 781 gq->pkt_len += pkt_len; 782 break; 783 default: 784 netdev_err(ndev, "%s: unexpected value (%x)\n", __func__, die_dt); 785 break; 786 } 787 788 return skb; 789 } 790 791 static bool rswitch_rx(struct net_device *ndev, int *quota) 792 { 793 struct rswitch_device *rdev = netdev_priv(ndev); 794 struct rswitch_gwca_queue *gq = rdev->rx_queue; 795 struct rswitch_ext_ts_desc *desc; 796 int limit, boguscnt, ret; 797 struct sk_buff *skb; 798 unsigned int num; 799 u32 get_ts; 800 801 if (*quota <= 0) 802 return true; 803 804 boguscnt = min_t(int, gq->ring_size, *quota); 805 limit = boguscnt; 806 807 desc = &gq->rx_ring[gq->cur]; 808 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) { 809 dma_rmb(); 810 skb = rswitch_rx_handle_desc(ndev, gq, desc); 811 if (!skb) 812 goto out; 813 814 get_ts = rdev->priv->ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 815 if (get_ts) { 816 struct skb_shared_hwtstamps *shhwtstamps; 817 struct timespec64 ts; 818 819 shhwtstamps = skb_hwtstamps(skb); 820 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 821 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 822 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 823 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 824 } 825 skb->protocol = eth_type_trans(skb, ndev); 826 napi_gro_receive(&rdev->napi, skb); 827 rdev->ndev->stats.rx_packets++; 828 rdev->ndev->stats.rx_bytes += gq->pkt_len; 829 830 out: 831 gq->rx_bufs[gq->cur] = NULL; 832 gq->cur = rswitch_next_queue_index(gq, true, 1); 833 desc = &gq->rx_ring[gq->cur]; 834 835 if (--boguscnt <= 0) 836 break; 837 } 838 839 num = rswitch_get_num_cur_queues(gq); 840 ret = rswitch_gwca_queue_alloc_rx_buf(gq, gq->dirty, num); 841 if (ret < 0) 842 goto err; 843 ret = rswitch_gwca_queue_ext_ts_fill(ndev, gq, gq->dirty, num); 844 if (ret < 0) 845 goto err; 846 gq->dirty = rswitch_next_queue_index(gq, false, num); 847 848 *quota -= limit - boguscnt; 849 850 return boguscnt <= 0; 851 852 err: 853 rswitch_gwca_halt(rdev->priv); 854 855 return 0; 856 } 857 858 static void rswitch_tx_free(struct net_device *ndev) 859 { 860 struct rswitch_device *rdev = netdev_priv(ndev); 861 struct rswitch_gwca_queue *gq = rdev->tx_queue; 862 struct rswitch_ext_desc *desc; 863 struct sk_buff *skb; 864 865 desc = &gq->tx_ring[gq->dirty]; 866 while ((desc->desc.die_dt & DT_MASK) == DT_FEMPTY) { 867 dma_rmb(); 868 869 skb = gq->skbs[gq->dirty]; 870 if (skb) { 871 rdev->ndev->stats.tx_packets++; 872 rdev->ndev->stats.tx_bytes += skb->len; 873 dma_unmap_single(ndev->dev.parent, 874 gq->unmap_addrs[gq->dirty], 875 skb->len, DMA_TO_DEVICE); 876 dev_kfree_skb_any(gq->skbs[gq->dirty]); 877 gq->skbs[gq->dirty] = NULL; 878 } 879 880 desc->desc.die_dt = DT_EEMPTY; 881 gq->dirty = rswitch_next_queue_index(gq, false, 1); 882 desc = &gq->tx_ring[gq->dirty]; 883 } 884 } 885 886 static int rswitch_poll(struct napi_struct *napi, int budget) 887 { 888 struct net_device *ndev = napi->dev; 889 struct rswitch_private *priv; 890 struct rswitch_device *rdev; 891 unsigned long flags; 892 int quota = budget; 893 894 rdev = netdev_priv(ndev); 895 priv = rdev->priv; 896 897 retry: 898 rswitch_tx_free(ndev); 899 900 if (rswitch_rx(ndev, "a)) 901 goto out; 902 else if (rdev->priv->gwca_halt) 903 goto err; 904 else if (rswitch_is_queue_rxed(rdev->rx_queue)) 905 goto retry; 906 907 netif_wake_subqueue(ndev, 0); 908 909 if (napi_complete_done(napi, budget - quota)) { 910 spin_lock_irqsave(&priv->lock, flags); 911 if (test_bit(rdev->port, priv->opened_ports)) { 912 rswitch_enadis_data_irq(priv, rdev->tx_queue->index, true); 913 rswitch_enadis_data_irq(priv, rdev->rx_queue->index, true); 914 } 915 spin_unlock_irqrestore(&priv->lock, flags); 916 } 917 918 out: 919 return budget - quota; 920 921 err: 922 napi_complete(napi); 923 924 return 0; 925 } 926 927 static void rswitch_queue_interrupt(struct net_device *ndev) 928 { 929 struct rswitch_device *rdev = netdev_priv(ndev); 930 931 if (napi_schedule_prep(&rdev->napi)) { 932 spin_lock(&rdev->priv->lock); 933 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 934 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 935 spin_unlock(&rdev->priv->lock); 936 __napi_schedule(&rdev->napi); 937 } 938 } 939 940 static irqreturn_t rswitch_data_irq(struct rswitch_private *priv, u32 *dis) 941 { 942 struct rswitch_gwca_queue *gq; 943 unsigned int i, index, bit; 944 945 for (i = 0; i < priv->gwca.num_queues; i++) { 946 gq = &priv->gwca.queues[i]; 947 index = gq->index / 32; 948 bit = BIT(gq->index % 32); 949 if (!(dis[index] & bit)) 950 continue; 951 952 rswitch_ack_data_irq(priv, gq->index); 953 rswitch_queue_interrupt(gq->ndev); 954 } 955 956 return IRQ_HANDLED; 957 } 958 959 static irqreturn_t rswitch_gwca_irq(int irq, void *dev_id) 960 { 961 struct rswitch_private *priv = dev_id; 962 u32 dis[RSWITCH_NUM_IRQ_REGS]; 963 irqreturn_t ret = IRQ_NONE; 964 965 rswitch_get_data_irq_status(priv, dis); 966 967 if (rswitch_is_any_data_irq(priv, dis, true) || 968 rswitch_is_any_data_irq(priv, dis, false)) 969 ret = rswitch_data_irq(priv, dis); 970 971 return ret; 972 } 973 974 static int rswitch_gwca_request_irqs(struct rswitch_private *priv) 975 { 976 char *resource_name, *irq_name; 977 int i, ret, irq; 978 979 for (i = 0; i < GWCA_NUM_IRQS; i++) { 980 resource_name = kasprintf(GFP_KERNEL, GWCA_IRQ_RESOURCE_NAME, i); 981 if (!resource_name) 982 return -ENOMEM; 983 984 irq = platform_get_irq_byname(priv->pdev, resource_name); 985 kfree(resource_name); 986 if (irq < 0) 987 return irq; 988 989 irq_name = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL, 990 GWCA_IRQ_NAME, i); 991 if (!irq_name) 992 return -ENOMEM; 993 994 ret = devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_irq, 995 0, irq_name, priv); 996 if (ret < 0) 997 return ret; 998 } 999 1000 return 0; 1001 } 1002 1003 static void rswitch_ts(struct rswitch_private *priv) 1004 { 1005 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 1006 struct rswitch_gwca_ts_info *ts_info, *ts_info2; 1007 struct skb_shared_hwtstamps shhwtstamps; 1008 struct rswitch_ts_desc *desc; 1009 struct timespec64 ts; 1010 unsigned int num; 1011 u32 tag, port; 1012 1013 desc = &gq->ts_ring[gq->cur]; 1014 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY_ND) { 1015 dma_rmb(); 1016 1017 port = TS_DESC_DPN(__le32_to_cpu(desc->desc.dptrl)); 1018 tag = TS_DESC_TSUN(__le32_to_cpu(desc->desc.dptrl)); 1019 1020 list_for_each_entry_safe(ts_info, ts_info2, &priv->gwca.ts_info_list, list) { 1021 if (!(ts_info->port == port && ts_info->tag == tag)) 1022 continue; 1023 1024 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 1025 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 1026 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 1027 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 1028 skb_tstamp_tx(ts_info->skb, &shhwtstamps); 1029 dev_consume_skb_irq(ts_info->skb); 1030 list_del(&ts_info->list); 1031 kfree(ts_info); 1032 break; 1033 } 1034 1035 gq->cur = rswitch_next_queue_index(gq, true, 1); 1036 desc = &gq->ts_ring[gq->cur]; 1037 } 1038 1039 num = rswitch_get_num_cur_queues(gq); 1040 rswitch_gwca_ts_queue_fill(priv, gq->dirty, num); 1041 gq->dirty = rswitch_next_queue_index(gq, false, num); 1042 } 1043 1044 static irqreturn_t rswitch_gwca_ts_irq(int irq, void *dev_id) 1045 { 1046 struct rswitch_private *priv = dev_id; 1047 1048 if (ioread32(priv->addr + GWTSDIS) & GWCA_TS_IRQ_BIT) { 1049 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDIS); 1050 rswitch_ts(priv); 1051 1052 return IRQ_HANDLED; 1053 } 1054 1055 return IRQ_NONE; 1056 } 1057 1058 static int rswitch_gwca_ts_request_irqs(struct rswitch_private *priv) 1059 { 1060 int irq; 1061 1062 irq = platform_get_irq_byname(priv->pdev, GWCA_TS_IRQ_RESOURCE_NAME); 1063 if (irq < 0) 1064 return irq; 1065 1066 return devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_ts_irq, 1067 0, GWCA_TS_IRQ_NAME, priv); 1068 } 1069 1070 /* Ethernet TSN Agent block (ETHA) and Ethernet MAC IP block (RMAC) */ 1071 static int rswitch_etha_change_mode(struct rswitch_etha *etha, 1072 enum rswitch_etha_mode mode) 1073 { 1074 int ret; 1075 1076 if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index)) 1077 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1); 1078 1079 iowrite32(mode, etha->addr + EAMC); 1080 1081 ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode); 1082 1083 if (mode == EAMC_OPC_DISABLE) 1084 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0); 1085 1086 return ret; 1087 } 1088 1089 static void rswitch_etha_read_mac_address(struct rswitch_etha *etha) 1090 { 1091 u32 mrmac0 = ioread32(etha->addr + MRMAC0); 1092 u32 mrmac1 = ioread32(etha->addr + MRMAC1); 1093 u8 *mac = ða->mac_addr[0]; 1094 1095 mac[0] = (mrmac0 >> 8) & 0xFF; 1096 mac[1] = (mrmac0 >> 0) & 0xFF; 1097 mac[2] = (mrmac1 >> 24) & 0xFF; 1098 mac[3] = (mrmac1 >> 16) & 0xFF; 1099 mac[4] = (mrmac1 >> 8) & 0xFF; 1100 mac[5] = (mrmac1 >> 0) & 0xFF; 1101 } 1102 1103 static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac) 1104 { 1105 iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0); 1106 iowrite32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], 1107 etha->addr + MRMAC1); 1108 } 1109 1110 static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha) 1111 { 1112 iowrite32(MLVC_PLV, etha->addr + MLVC); 1113 1114 return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0); 1115 } 1116 1117 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac) 1118 { 1119 u32 pis, lsc; 1120 1121 rswitch_etha_write_mac_address(etha, mac); 1122 1123 switch (etha->phy_interface) { 1124 case PHY_INTERFACE_MODE_SGMII: 1125 pis = MPIC_PIS_GMII; 1126 break; 1127 case PHY_INTERFACE_MODE_USXGMII: 1128 case PHY_INTERFACE_MODE_5GBASER: 1129 pis = MPIC_PIS_XGMII; 1130 break; 1131 default: 1132 pis = FIELD_GET(MPIC_PIS, ioread32(etha->addr + MPIC)); 1133 break; 1134 } 1135 1136 switch (etha->speed) { 1137 case 100: 1138 lsc = MPIC_LSC_100M; 1139 break; 1140 case 1000: 1141 lsc = MPIC_LSC_1G; 1142 break; 1143 case 2500: 1144 lsc = MPIC_LSC_2_5G; 1145 break; 1146 default: 1147 lsc = FIELD_GET(MPIC_LSC, ioread32(etha->addr + MPIC)); 1148 break; 1149 } 1150 1151 rswitch_modify(etha->addr, MPIC, MPIC_PIS | MPIC_LSC, 1152 FIELD_PREP(MPIC_PIS, pis) | FIELD_PREP(MPIC_LSC, lsc)); 1153 } 1154 1155 static void rswitch_etha_enable_mii(struct rswitch_etha *etha) 1156 { 1157 rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, 1158 MPIC_PSMCS(etha->psmcs) | MPIC_PSMHT(0x06)); 1159 rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45); 1160 } 1161 1162 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac) 1163 { 1164 int err; 1165 1166 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 1167 if (err < 0) 1168 return err; 1169 err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG); 1170 if (err < 0) 1171 return err; 1172 1173 iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC); 1174 rswitch_rmac_setting(etha, mac); 1175 rswitch_etha_enable_mii(etha); 1176 1177 err = rswitch_etha_wait_link_verification(etha); 1178 if (err < 0) 1179 return err; 1180 1181 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 1182 if (err < 0) 1183 return err; 1184 1185 return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION); 1186 } 1187 1188 static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read, 1189 int phyad, int devad, int regad, int data) 1190 { 1191 int pop = read ? MDIO_READ_C45 : MDIO_WRITE_C45; 1192 u32 val; 1193 int ret; 1194 1195 if (devad == 0xffffffff) 1196 return -ENODEV; 1197 1198 writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); 1199 1200 val = MPSM_PSME | MPSM_MFF_C45; 1201 iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1202 1203 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1204 if (ret) 1205 return ret; 1206 1207 rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1208 1209 if (read) { 1210 writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1211 1212 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1213 if (ret) 1214 return ret; 1215 1216 ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; 1217 1218 rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1219 } else { 1220 iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val, 1221 etha->addr + MPSM); 1222 1223 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS); 1224 } 1225 1226 return ret; 1227 } 1228 1229 static int rswitch_etha_mii_read_c45(struct mii_bus *bus, int addr, int devad, 1230 int regad) 1231 { 1232 struct rswitch_etha *etha = bus->priv; 1233 1234 return rswitch_etha_set_access(etha, true, addr, devad, regad, 0); 1235 } 1236 1237 static int rswitch_etha_mii_write_c45(struct mii_bus *bus, int addr, int devad, 1238 int regad, u16 val) 1239 { 1240 struct rswitch_etha *etha = bus->priv; 1241 1242 return rswitch_etha_set_access(etha, false, addr, devad, regad, val); 1243 } 1244 1245 /* Call of_node_put(port) after done */ 1246 static struct device_node *rswitch_get_port_node(struct rswitch_device *rdev) 1247 { 1248 struct device_node *ports, *port; 1249 int err = 0; 1250 u32 index; 1251 1252 ports = of_get_child_by_name(rdev->ndev->dev.parent->of_node, 1253 "ethernet-ports"); 1254 if (!ports) 1255 return NULL; 1256 1257 for_each_child_of_node(ports, port) { 1258 err = of_property_read_u32(port, "reg", &index); 1259 if (err < 0) { 1260 port = NULL; 1261 goto out; 1262 } 1263 if (index == rdev->etha->index) { 1264 if (!of_device_is_available(port)) 1265 port = NULL; 1266 break; 1267 } 1268 } 1269 1270 out: 1271 of_node_put(ports); 1272 1273 return port; 1274 } 1275 1276 static int rswitch_etha_get_params(struct rswitch_device *rdev) 1277 { 1278 u32 max_speed; 1279 int err; 1280 1281 if (!rdev->np_port) 1282 return 0; /* ignored */ 1283 1284 err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface); 1285 if (err) 1286 return err; 1287 1288 err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed); 1289 if (!err) { 1290 rdev->etha->speed = max_speed; 1291 return 0; 1292 } 1293 1294 /* if no "max-speed" property, let's use default speed */ 1295 switch (rdev->etha->phy_interface) { 1296 case PHY_INTERFACE_MODE_MII: 1297 rdev->etha->speed = SPEED_100; 1298 break; 1299 case PHY_INTERFACE_MODE_SGMII: 1300 rdev->etha->speed = SPEED_1000; 1301 break; 1302 case PHY_INTERFACE_MODE_USXGMII: 1303 rdev->etha->speed = SPEED_2500; 1304 break; 1305 default: 1306 return -EINVAL; 1307 } 1308 1309 return 0; 1310 } 1311 1312 static int rswitch_mii_register(struct rswitch_device *rdev) 1313 { 1314 struct device_node *mdio_np; 1315 struct mii_bus *mii_bus; 1316 int err; 1317 1318 mii_bus = mdiobus_alloc(); 1319 if (!mii_bus) 1320 return -ENOMEM; 1321 1322 mii_bus->name = "rswitch_mii"; 1323 sprintf(mii_bus->id, "etha%d", rdev->etha->index); 1324 mii_bus->priv = rdev->etha; 1325 mii_bus->read_c45 = rswitch_etha_mii_read_c45; 1326 mii_bus->write_c45 = rswitch_etha_mii_write_c45; 1327 mii_bus->parent = &rdev->priv->pdev->dev; 1328 1329 mdio_np = of_get_child_by_name(rdev->np_port, "mdio"); 1330 err = of_mdiobus_register(mii_bus, mdio_np); 1331 if (err < 0) { 1332 mdiobus_free(mii_bus); 1333 goto out; 1334 } 1335 1336 rdev->etha->mii = mii_bus; 1337 1338 out: 1339 of_node_put(mdio_np); 1340 1341 return err; 1342 } 1343 1344 static void rswitch_mii_unregister(struct rswitch_device *rdev) 1345 { 1346 if (rdev->etha->mii) { 1347 mdiobus_unregister(rdev->etha->mii); 1348 mdiobus_free(rdev->etha->mii); 1349 rdev->etha->mii = NULL; 1350 } 1351 } 1352 1353 static void rswitch_adjust_link(struct net_device *ndev) 1354 { 1355 struct rswitch_device *rdev = netdev_priv(ndev); 1356 struct phy_device *phydev = ndev->phydev; 1357 1358 if (phydev->link != rdev->etha->link) { 1359 phy_print_status(phydev); 1360 if (phydev->link) 1361 phy_power_on(rdev->serdes); 1362 else if (rdev->serdes->power_count) 1363 phy_power_off(rdev->serdes); 1364 1365 rdev->etha->link = phydev->link; 1366 1367 if (!rdev->priv->etha_no_runtime_change && 1368 phydev->speed != rdev->etha->speed) { 1369 rdev->etha->speed = phydev->speed; 1370 1371 rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); 1372 phy_set_speed(rdev->serdes, rdev->etha->speed); 1373 } 1374 } 1375 } 1376 1377 static void rswitch_phy_remove_link_mode(struct rswitch_device *rdev, 1378 struct phy_device *phydev) 1379 { 1380 if (!rdev->priv->etha_no_runtime_change) 1381 return; 1382 1383 switch (rdev->etha->speed) { 1384 case SPEED_2500: 1385 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1386 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1387 break; 1388 case SPEED_1000: 1389 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1390 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1391 break; 1392 case SPEED_100: 1393 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1394 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1395 break; 1396 default: 1397 break; 1398 } 1399 1400 phy_set_max_speed(phydev, rdev->etha->speed); 1401 } 1402 1403 static int rswitch_phy_device_init(struct rswitch_device *rdev) 1404 { 1405 struct phy_device *phydev; 1406 struct device_node *phy; 1407 int err = -ENOENT; 1408 1409 if (!rdev->np_port) 1410 return -ENODEV; 1411 1412 phy = of_parse_phandle(rdev->np_port, "phy-handle", 0); 1413 if (!phy) 1414 return -ENODEV; 1415 1416 /* Set phydev->host_interfaces before calling of_phy_connect() to 1417 * configure the PHY with the information of host_interfaces. 1418 */ 1419 phydev = of_phy_find_device(phy); 1420 if (!phydev) 1421 goto out; 1422 __set_bit(rdev->etha->phy_interface, phydev->host_interfaces); 1423 phydev->mac_managed_pm = true; 1424 1425 phydev = of_phy_connect(rdev->ndev, phy, rswitch_adjust_link, 0, 1426 rdev->etha->phy_interface); 1427 if (!phydev) 1428 goto out; 1429 1430 phy_set_max_speed(phydev, SPEED_2500); 1431 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1432 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1433 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1434 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1435 rswitch_phy_remove_link_mode(rdev, phydev); 1436 1437 phy_attached_info(phydev); 1438 1439 err = 0; 1440 out: 1441 of_node_put(phy); 1442 1443 return err; 1444 } 1445 1446 static void rswitch_phy_device_deinit(struct rswitch_device *rdev) 1447 { 1448 if (rdev->ndev->phydev) 1449 phy_disconnect(rdev->ndev->phydev); 1450 } 1451 1452 static int rswitch_serdes_set_params(struct rswitch_device *rdev) 1453 { 1454 int err; 1455 1456 err = phy_set_mode_ext(rdev->serdes, PHY_MODE_ETHERNET, 1457 rdev->etha->phy_interface); 1458 if (err < 0) 1459 return err; 1460 1461 return phy_set_speed(rdev->serdes, rdev->etha->speed); 1462 } 1463 1464 static int rswitch_ether_port_init_one(struct rswitch_device *rdev) 1465 { 1466 int err; 1467 1468 if (!rdev->etha->operated) { 1469 err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); 1470 if (err < 0) 1471 return err; 1472 if (rdev->priv->etha_no_runtime_change) 1473 rdev->etha->operated = true; 1474 } 1475 1476 err = rswitch_mii_register(rdev); 1477 if (err < 0) 1478 return err; 1479 1480 err = rswitch_phy_device_init(rdev); 1481 if (err < 0) 1482 goto err_phy_device_init; 1483 1484 rdev->serdes = devm_of_phy_get(&rdev->priv->pdev->dev, rdev->np_port, NULL); 1485 if (IS_ERR(rdev->serdes)) { 1486 err = PTR_ERR(rdev->serdes); 1487 goto err_serdes_phy_get; 1488 } 1489 1490 err = rswitch_serdes_set_params(rdev); 1491 if (err < 0) 1492 goto err_serdes_set_params; 1493 1494 return 0; 1495 1496 err_serdes_set_params: 1497 err_serdes_phy_get: 1498 rswitch_phy_device_deinit(rdev); 1499 1500 err_phy_device_init: 1501 rswitch_mii_unregister(rdev); 1502 1503 return err; 1504 } 1505 1506 static void rswitch_ether_port_deinit_one(struct rswitch_device *rdev) 1507 { 1508 rswitch_phy_device_deinit(rdev); 1509 rswitch_mii_unregister(rdev); 1510 } 1511 1512 static int rswitch_ether_port_init_all(struct rswitch_private *priv) 1513 { 1514 unsigned int i; 1515 int err; 1516 1517 rswitch_for_each_enabled_port(priv, i) { 1518 err = rswitch_ether_port_init_one(priv->rdev[i]); 1519 if (err) 1520 goto err_init_one; 1521 } 1522 1523 rswitch_for_each_enabled_port(priv, i) { 1524 err = phy_init(priv->rdev[i]->serdes); 1525 if (err) 1526 goto err_serdes; 1527 } 1528 1529 return 0; 1530 1531 err_serdes: 1532 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1533 phy_exit(priv->rdev[i]->serdes); 1534 i = RSWITCH_NUM_PORTS; 1535 1536 err_init_one: 1537 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1538 rswitch_ether_port_deinit_one(priv->rdev[i]); 1539 1540 return err; 1541 } 1542 1543 static void rswitch_ether_port_deinit_all(struct rswitch_private *priv) 1544 { 1545 unsigned int i; 1546 1547 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1548 phy_exit(priv->rdev[i]->serdes); 1549 rswitch_ether_port_deinit_one(priv->rdev[i]); 1550 } 1551 } 1552 1553 static int rswitch_open(struct net_device *ndev) 1554 { 1555 struct rswitch_device *rdev = netdev_priv(ndev); 1556 unsigned long flags; 1557 1558 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) 1559 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDIE); 1560 1561 napi_enable(&rdev->napi); 1562 1563 spin_lock_irqsave(&rdev->priv->lock, flags); 1564 bitmap_set(rdev->priv->opened_ports, rdev->port, 1); 1565 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, true); 1566 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, true); 1567 spin_unlock_irqrestore(&rdev->priv->lock, flags); 1568 1569 phy_start(ndev->phydev); 1570 1571 netif_start_queue(ndev); 1572 1573 return 0; 1574 }; 1575 1576 static int rswitch_stop(struct net_device *ndev) 1577 { 1578 struct rswitch_device *rdev = netdev_priv(ndev); 1579 struct rswitch_gwca_ts_info *ts_info, *ts_info2; 1580 unsigned long flags; 1581 1582 netif_tx_stop_all_queues(ndev); 1583 1584 phy_stop(ndev->phydev); 1585 1586 spin_lock_irqsave(&rdev->priv->lock, flags); 1587 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 1588 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 1589 bitmap_clear(rdev->priv->opened_ports, rdev->port, 1); 1590 spin_unlock_irqrestore(&rdev->priv->lock, flags); 1591 1592 napi_disable(&rdev->napi); 1593 1594 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) 1595 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDID); 1596 1597 list_for_each_entry_safe(ts_info, ts_info2, &rdev->priv->gwca.ts_info_list, list) { 1598 if (ts_info->port != rdev->port) 1599 continue; 1600 dev_kfree_skb_irq(ts_info->skb); 1601 list_del(&ts_info->list); 1602 kfree(ts_info); 1603 } 1604 1605 return 0; 1606 }; 1607 1608 static bool rswitch_ext_desc_set_info1(struct rswitch_device *rdev, 1609 struct sk_buff *skb, 1610 struct rswitch_ext_desc *desc) 1611 { 1612 desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) | 1613 INFO1_IPV(GWCA_IPV_NUM) | INFO1_FMT); 1614 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 1615 struct rswitch_gwca_ts_info *ts_info; 1616 1617 ts_info = kzalloc(sizeof(*ts_info), GFP_ATOMIC); 1618 if (!ts_info) 1619 return false; 1620 1621 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1622 rdev->ts_tag++; 1623 desc->info1 |= cpu_to_le64(INFO1_TSUN(rdev->ts_tag) | INFO1_TXC); 1624 1625 ts_info->skb = skb_get(skb); 1626 ts_info->port = rdev->port; 1627 ts_info->tag = rdev->ts_tag; 1628 list_add_tail(&ts_info->list, &rdev->priv->gwca.ts_info_list); 1629 1630 skb_tx_timestamp(skb); 1631 } 1632 1633 return true; 1634 } 1635 1636 static bool rswitch_ext_desc_set(struct rswitch_device *rdev, 1637 struct sk_buff *skb, 1638 struct rswitch_ext_desc *desc, 1639 dma_addr_t dma_addr, u16 len, u8 die_dt) 1640 { 1641 rswitch_desc_set_dptr(&desc->desc, dma_addr); 1642 desc->desc.info_ds = cpu_to_le16(len); 1643 if (!rswitch_ext_desc_set_info1(rdev, skb, desc)) 1644 return false; 1645 1646 dma_wmb(); 1647 1648 desc->desc.die_dt = die_dt; 1649 1650 return true; 1651 } 1652 1653 static u8 rswitch_ext_desc_get_die_dt(unsigned int nr_desc, unsigned int index) 1654 { 1655 if (nr_desc == 1) 1656 return DT_FSINGLE | DIE; 1657 if (index == 0) 1658 return DT_FSTART; 1659 if (nr_desc - 1 == index) 1660 return DT_FEND | DIE; 1661 return DT_FMID; 1662 } 1663 1664 static u16 rswitch_ext_desc_get_len(u8 die_dt, unsigned int orig_len) 1665 { 1666 switch (die_dt & DT_MASK) { 1667 case DT_FSINGLE: 1668 case DT_FEND: 1669 return (orig_len % RSWITCH_DESC_BUF_SIZE) ?: RSWITCH_DESC_BUF_SIZE; 1670 case DT_FSTART: 1671 case DT_FMID: 1672 return RSWITCH_DESC_BUF_SIZE; 1673 default: 1674 return 0; 1675 } 1676 } 1677 1678 static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1679 { 1680 struct rswitch_device *rdev = netdev_priv(ndev); 1681 struct rswitch_gwca_queue *gq = rdev->tx_queue; 1682 dma_addr_t dma_addr, dma_addr_orig; 1683 netdev_tx_t ret = NETDEV_TX_OK; 1684 struct rswitch_ext_desc *desc; 1685 unsigned int i, nr_desc; 1686 u8 die_dt; 1687 u16 len; 1688 1689 nr_desc = (skb->len - 1) / RSWITCH_DESC_BUF_SIZE + 1; 1690 if (rswitch_get_num_cur_queues(gq) >= gq->ring_size - nr_desc) { 1691 netif_stop_subqueue(ndev, 0); 1692 return NETDEV_TX_BUSY; 1693 } 1694 1695 if (skb_put_padto(skb, ETH_ZLEN)) 1696 return ret; 1697 1698 dma_addr_orig = dma_map_single(ndev->dev.parent, skb->data, skb->len, DMA_TO_DEVICE); 1699 if (dma_mapping_error(ndev->dev.parent, dma_addr_orig)) 1700 goto err_kfree; 1701 1702 /* Stored the skb at the last descriptor to avoid skb free before hardware completes send */ 1703 gq->skbs[(gq->cur + nr_desc - 1) % gq->ring_size] = skb; 1704 gq->unmap_addrs[(gq->cur + nr_desc - 1) % gq->ring_size] = dma_addr_orig; 1705 1706 dma_wmb(); 1707 1708 /* DT_FSTART should be set at last. So, this is reverse order. */ 1709 for (i = nr_desc; i-- > 0; ) { 1710 desc = &gq->tx_ring[rswitch_next_queue_index(gq, true, i)]; 1711 die_dt = rswitch_ext_desc_get_die_dt(nr_desc, i); 1712 dma_addr = dma_addr_orig + i * RSWITCH_DESC_BUF_SIZE; 1713 len = rswitch_ext_desc_get_len(die_dt, skb->len); 1714 if (!rswitch_ext_desc_set(rdev, skb, desc, dma_addr, len, die_dt)) 1715 goto err_unmap; 1716 } 1717 1718 gq->cur = rswitch_next_queue_index(gq, true, nr_desc); 1719 rswitch_modify(rdev->addr, GWTRC(gq->index), 0, BIT(gq->index % 32)); 1720 1721 return ret; 1722 1723 err_unmap: 1724 gq->skbs[(gq->cur + nr_desc - 1) % gq->ring_size] = NULL; 1725 dma_unmap_single(ndev->dev.parent, dma_addr_orig, skb->len, DMA_TO_DEVICE); 1726 1727 err_kfree: 1728 dev_kfree_skb_any(skb); 1729 1730 return ret; 1731 } 1732 1733 static struct net_device_stats *rswitch_get_stats(struct net_device *ndev) 1734 { 1735 return &ndev->stats; 1736 } 1737 1738 static int rswitch_hwstamp_get(struct net_device *ndev, struct ifreq *req) 1739 { 1740 struct rswitch_device *rdev = netdev_priv(ndev); 1741 struct rcar_gen4_ptp_private *ptp_priv; 1742 struct hwtstamp_config config; 1743 1744 ptp_priv = rdev->priv->ptp_priv; 1745 1746 config.flags = 0; 1747 config.tx_type = ptp_priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1748 HWTSTAMP_TX_OFF; 1749 switch (ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE) { 1750 case RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT: 1751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1752 break; 1753 case RCAR_GEN4_RXTSTAMP_TYPE_ALL: 1754 config.rx_filter = HWTSTAMP_FILTER_ALL; 1755 break; 1756 default: 1757 config.rx_filter = HWTSTAMP_FILTER_NONE; 1758 break; 1759 } 1760 1761 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1762 } 1763 1764 static int rswitch_hwstamp_set(struct net_device *ndev, struct ifreq *req) 1765 { 1766 struct rswitch_device *rdev = netdev_priv(ndev); 1767 u32 tstamp_rx_ctrl = RCAR_GEN4_RXTSTAMP_ENABLED; 1768 struct hwtstamp_config config; 1769 u32 tstamp_tx_ctrl; 1770 1771 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1772 return -EFAULT; 1773 1774 if (config.flags) 1775 return -EINVAL; 1776 1777 switch (config.tx_type) { 1778 case HWTSTAMP_TX_OFF: 1779 tstamp_tx_ctrl = 0; 1780 break; 1781 case HWTSTAMP_TX_ON: 1782 tstamp_tx_ctrl = RCAR_GEN4_TXTSTAMP_ENABLED; 1783 break; 1784 default: 1785 return -ERANGE; 1786 } 1787 1788 switch (config.rx_filter) { 1789 case HWTSTAMP_FILTER_NONE: 1790 tstamp_rx_ctrl = 0; 1791 break; 1792 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1793 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 1794 break; 1795 default: 1796 config.rx_filter = HWTSTAMP_FILTER_ALL; 1797 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_ALL; 1798 break; 1799 } 1800 1801 rdev->priv->ptp_priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1802 rdev->priv->ptp_priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1803 1804 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1805 } 1806 1807 static int rswitch_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1808 { 1809 if (!netif_running(ndev)) 1810 return -EINVAL; 1811 1812 switch (cmd) { 1813 case SIOCGHWTSTAMP: 1814 return rswitch_hwstamp_get(ndev, req); 1815 case SIOCSHWTSTAMP: 1816 return rswitch_hwstamp_set(ndev, req); 1817 default: 1818 return phy_mii_ioctl(ndev->phydev, req, cmd); 1819 } 1820 } 1821 1822 static const struct net_device_ops rswitch_netdev_ops = { 1823 .ndo_open = rswitch_open, 1824 .ndo_stop = rswitch_stop, 1825 .ndo_start_xmit = rswitch_start_xmit, 1826 .ndo_get_stats = rswitch_get_stats, 1827 .ndo_eth_ioctl = rswitch_eth_ioctl, 1828 .ndo_validate_addr = eth_validate_addr, 1829 .ndo_set_mac_address = eth_mac_addr, 1830 }; 1831 1832 static int rswitch_get_ts_info(struct net_device *ndev, struct kernel_ethtool_ts_info *info) 1833 { 1834 struct rswitch_device *rdev = netdev_priv(ndev); 1835 1836 info->phc_index = ptp_clock_index(rdev->priv->ptp_priv->clock); 1837 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1838 SOF_TIMESTAMPING_TX_HARDWARE | 1839 SOF_TIMESTAMPING_RX_HARDWARE | 1840 SOF_TIMESTAMPING_RAW_HARDWARE; 1841 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 1842 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1843 1844 return 0; 1845 } 1846 1847 static const struct ethtool_ops rswitch_ethtool_ops = { 1848 .get_ts_info = rswitch_get_ts_info, 1849 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1850 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1851 }; 1852 1853 static const struct of_device_id renesas_eth_sw_of_table[] = { 1854 { .compatible = "renesas,r8a779f0-ether-switch", }, 1855 { } 1856 }; 1857 MODULE_DEVICE_TABLE(of, renesas_eth_sw_of_table); 1858 1859 static void rswitch_etha_init(struct rswitch_private *priv, unsigned int index) 1860 { 1861 struct rswitch_etha *etha = &priv->etha[index]; 1862 1863 memset(etha, 0, sizeof(*etha)); 1864 etha->index = index; 1865 etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE; 1866 etha->coma_addr = priv->addr; 1867 1868 /* MPIC.PSMCS = (clk [MHz] / (MDC frequency [MHz] * 2) - 1. 1869 * Calculating PSMCS value as MDC frequency = 2.5MHz. So, multiply 1870 * both the numerator and the denominator by 10. 1871 */ 1872 etha->psmcs = clk_get_rate(priv->clk) / 100000 / (25 * 2) - 1; 1873 } 1874 1875 static int rswitch_device_alloc(struct rswitch_private *priv, unsigned int index) 1876 { 1877 struct platform_device *pdev = priv->pdev; 1878 struct rswitch_device *rdev; 1879 struct net_device *ndev; 1880 int err; 1881 1882 if (index >= RSWITCH_NUM_PORTS) 1883 return -EINVAL; 1884 1885 ndev = alloc_etherdev_mqs(sizeof(struct rswitch_device), 1, 1); 1886 if (!ndev) 1887 return -ENOMEM; 1888 1889 SET_NETDEV_DEV(ndev, &pdev->dev); 1890 ether_setup(ndev); 1891 1892 rdev = netdev_priv(ndev); 1893 rdev->ndev = ndev; 1894 rdev->priv = priv; 1895 priv->rdev[index] = rdev; 1896 rdev->port = index; 1897 rdev->etha = &priv->etha[index]; 1898 rdev->addr = priv->addr; 1899 1900 ndev->base_addr = (unsigned long)rdev->addr; 1901 snprintf(ndev->name, IFNAMSIZ, "tsn%d", index); 1902 ndev->netdev_ops = &rswitch_netdev_ops; 1903 ndev->ethtool_ops = &rswitch_ethtool_ops; 1904 ndev->max_mtu = RSWITCH_MAX_MTU; 1905 ndev->min_mtu = ETH_MIN_MTU; 1906 1907 netif_napi_add(ndev, &rdev->napi, rswitch_poll); 1908 1909 rdev->np_port = rswitch_get_port_node(rdev); 1910 rdev->disabled = !rdev->np_port; 1911 err = of_get_ethdev_address(rdev->np_port, ndev); 1912 if (err) { 1913 if (is_valid_ether_addr(rdev->etha->mac_addr)) 1914 eth_hw_addr_set(ndev, rdev->etha->mac_addr); 1915 else 1916 eth_hw_addr_random(ndev); 1917 } 1918 1919 err = rswitch_etha_get_params(rdev); 1920 if (err < 0) 1921 goto out_get_params; 1922 1923 if (rdev->priv->gwca.speed < rdev->etha->speed) 1924 rdev->priv->gwca.speed = rdev->etha->speed; 1925 1926 err = rswitch_rxdmac_alloc(ndev); 1927 if (err < 0) 1928 goto out_rxdmac; 1929 1930 err = rswitch_txdmac_alloc(ndev); 1931 if (err < 0) 1932 goto out_txdmac; 1933 1934 return 0; 1935 1936 out_txdmac: 1937 rswitch_rxdmac_free(ndev); 1938 1939 out_rxdmac: 1940 out_get_params: 1941 of_node_put(rdev->np_port); 1942 netif_napi_del(&rdev->napi); 1943 free_netdev(ndev); 1944 1945 return err; 1946 } 1947 1948 static void rswitch_device_free(struct rswitch_private *priv, unsigned int index) 1949 { 1950 struct rswitch_device *rdev = priv->rdev[index]; 1951 struct net_device *ndev = rdev->ndev; 1952 1953 rswitch_txdmac_free(ndev); 1954 rswitch_rxdmac_free(ndev); 1955 of_node_put(rdev->np_port); 1956 netif_napi_del(&rdev->napi); 1957 free_netdev(ndev); 1958 } 1959 1960 static int rswitch_init(struct rswitch_private *priv) 1961 { 1962 unsigned int i; 1963 int err; 1964 1965 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1966 rswitch_etha_init(priv, i); 1967 1968 rswitch_clock_enable(priv); 1969 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1970 rswitch_etha_read_mac_address(&priv->etha[i]); 1971 1972 rswitch_reset(priv); 1973 1974 rswitch_clock_enable(priv); 1975 rswitch_top_init(priv); 1976 err = rswitch_bpool_config(priv); 1977 if (err < 0) 1978 return err; 1979 1980 rswitch_coma_init(priv); 1981 1982 err = rswitch_gwca_linkfix_alloc(priv); 1983 if (err < 0) 1984 return -ENOMEM; 1985 1986 err = rswitch_gwca_ts_queue_alloc(priv); 1987 if (err < 0) 1988 goto err_ts_queue_alloc; 1989 1990 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1991 err = rswitch_device_alloc(priv, i); 1992 if (err < 0) { 1993 for (; i-- > 0; ) 1994 rswitch_device_free(priv, i); 1995 goto err_device_alloc; 1996 } 1997 } 1998 1999 rswitch_fwd_init(priv); 2000 2001 err = rcar_gen4_ptp_register(priv->ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT, 2002 clk_get_rate(priv->clk)); 2003 if (err < 0) 2004 goto err_ptp_register; 2005 2006 err = rswitch_gwca_request_irqs(priv); 2007 if (err < 0) 2008 goto err_gwca_request_irq; 2009 2010 err = rswitch_gwca_ts_request_irqs(priv); 2011 if (err < 0) 2012 goto err_gwca_ts_request_irq; 2013 2014 err = rswitch_gwca_hw_init(priv); 2015 if (err < 0) 2016 goto err_gwca_hw_init; 2017 2018 err = rswitch_ether_port_init_all(priv); 2019 if (err) 2020 goto err_ether_port_init_all; 2021 2022 rswitch_for_each_enabled_port(priv, i) { 2023 err = register_netdev(priv->rdev[i]->ndev); 2024 if (err) { 2025 rswitch_for_each_enabled_port_continue_reverse(priv, i) 2026 unregister_netdev(priv->rdev[i]->ndev); 2027 goto err_register_netdev; 2028 } 2029 } 2030 2031 rswitch_for_each_enabled_port(priv, i) 2032 netdev_info(priv->rdev[i]->ndev, "MAC address %pM\n", 2033 priv->rdev[i]->ndev->dev_addr); 2034 2035 return 0; 2036 2037 err_register_netdev: 2038 rswitch_ether_port_deinit_all(priv); 2039 2040 err_ether_port_init_all: 2041 rswitch_gwca_hw_deinit(priv); 2042 2043 err_gwca_hw_init: 2044 err_gwca_ts_request_irq: 2045 err_gwca_request_irq: 2046 rcar_gen4_ptp_unregister(priv->ptp_priv); 2047 2048 err_ptp_register: 2049 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 2050 rswitch_device_free(priv, i); 2051 2052 err_device_alloc: 2053 rswitch_gwca_ts_queue_free(priv); 2054 2055 err_ts_queue_alloc: 2056 rswitch_gwca_linkfix_free(priv); 2057 2058 return err; 2059 } 2060 2061 static const struct soc_device_attribute rswitch_soc_no_speed_change[] = { 2062 { .soc_id = "r8a779f0", .revision = "ES1.0" }, 2063 { /* Sentinel */ } 2064 }; 2065 2066 static int renesas_eth_sw_probe(struct platform_device *pdev) 2067 { 2068 const struct soc_device_attribute *attr; 2069 struct rswitch_private *priv; 2070 struct resource *res; 2071 int ret; 2072 2073 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "secure_base"); 2074 if (!res) { 2075 dev_err(&pdev->dev, "invalid resource\n"); 2076 return -EINVAL; 2077 } 2078 2079 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 2080 if (!priv) 2081 return -ENOMEM; 2082 spin_lock_init(&priv->lock); 2083 2084 priv->clk = devm_clk_get(&pdev->dev, NULL); 2085 if (IS_ERR(priv->clk)) 2086 return PTR_ERR(priv->clk); 2087 2088 attr = soc_device_match(rswitch_soc_no_speed_change); 2089 if (attr) 2090 priv->etha_no_runtime_change = true; 2091 2092 priv->ptp_priv = rcar_gen4_ptp_alloc(pdev); 2093 if (!priv->ptp_priv) 2094 return -ENOMEM; 2095 2096 platform_set_drvdata(pdev, priv); 2097 priv->pdev = pdev; 2098 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2099 if (IS_ERR(priv->addr)) 2100 return PTR_ERR(priv->addr); 2101 2102 priv->ptp_priv->addr = priv->addr + RCAR_GEN4_GPTP_OFFSET_S4; 2103 2104 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 2105 if (ret < 0) { 2106 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2107 if (ret < 0) 2108 return ret; 2109 } 2110 2111 priv->gwca.index = AGENT_INDEX_GWCA; 2112 priv->gwca.num_queues = min(RSWITCH_NUM_PORTS * NUM_QUEUES_PER_NDEV, 2113 RSWITCH_MAX_NUM_QUEUES); 2114 priv->gwca.queues = devm_kcalloc(&pdev->dev, priv->gwca.num_queues, 2115 sizeof(*priv->gwca.queues), GFP_KERNEL); 2116 if (!priv->gwca.queues) 2117 return -ENOMEM; 2118 2119 pm_runtime_enable(&pdev->dev); 2120 pm_runtime_get_sync(&pdev->dev); 2121 2122 ret = rswitch_init(priv); 2123 if (ret < 0) { 2124 pm_runtime_put(&pdev->dev); 2125 pm_runtime_disable(&pdev->dev); 2126 return ret; 2127 } 2128 2129 device_set_wakeup_capable(&pdev->dev, 1); 2130 2131 return ret; 2132 } 2133 2134 static void rswitch_deinit(struct rswitch_private *priv) 2135 { 2136 unsigned int i; 2137 2138 rswitch_gwca_hw_deinit(priv); 2139 rcar_gen4_ptp_unregister(priv->ptp_priv); 2140 2141 rswitch_for_each_enabled_port(priv, i) { 2142 struct rswitch_device *rdev = priv->rdev[i]; 2143 2144 unregister_netdev(rdev->ndev); 2145 rswitch_ether_port_deinit_one(rdev); 2146 phy_exit(priv->rdev[i]->serdes); 2147 } 2148 2149 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 2150 rswitch_device_free(priv, i); 2151 2152 rswitch_gwca_ts_queue_free(priv); 2153 rswitch_gwca_linkfix_free(priv); 2154 2155 rswitch_clock_disable(priv); 2156 } 2157 2158 static void renesas_eth_sw_remove(struct platform_device *pdev) 2159 { 2160 struct rswitch_private *priv = platform_get_drvdata(pdev); 2161 2162 rswitch_deinit(priv); 2163 2164 pm_runtime_put(&pdev->dev); 2165 pm_runtime_disable(&pdev->dev); 2166 2167 platform_set_drvdata(pdev, NULL); 2168 } 2169 2170 static int renesas_eth_sw_suspend(struct device *dev) 2171 { 2172 struct rswitch_private *priv = dev_get_drvdata(dev); 2173 struct net_device *ndev; 2174 unsigned int i; 2175 2176 rswitch_for_each_enabled_port(priv, i) { 2177 ndev = priv->rdev[i]->ndev; 2178 if (netif_running(ndev)) { 2179 netif_device_detach(ndev); 2180 rswitch_stop(ndev); 2181 } 2182 if (priv->rdev[i]->serdes->init_count) 2183 phy_exit(priv->rdev[i]->serdes); 2184 } 2185 2186 return 0; 2187 } 2188 2189 static int renesas_eth_sw_resume(struct device *dev) 2190 { 2191 struct rswitch_private *priv = dev_get_drvdata(dev); 2192 struct net_device *ndev; 2193 unsigned int i; 2194 2195 rswitch_for_each_enabled_port(priv, i) { 2196 phy_init(priv->rdev[i]->serdes); 2197 ndev = priv->rdev[i]->ndev; 2198 if (netif_running(ndev)) { 2199 rswitch_open(ndev); 2200 netif_device_attach(ndev); 2201 } 2202 } 2203 2204 return 0; 2205 } 2206 2207 static DEFINE_SIMPLE_DEV_PM_OPS(renesas_eth_sw_pm_ops, renesas_eth_sw_suspend, 2208 renesas_eth_sw_resume); 2209 2210 static struct platform_driver renesas_eth_sw_driver_platform = { 2211 .probe = renesas_eth_sw_probe, 2212 .remove = renesas_eth_sw_remove, 2213 .driver = { 2214 .name = "renesas_eth_sw", 2215 .pm = pm_sleep_ptr(&renesas_eth_sw_pm_ops), 2216 .of_match_table = renesas_eth_sw_of_table, 2217 } 2218 }; 2219 module_platform_driver(renesas_eth_sw_driver_platform); 2220 MODULE_AUTHOR("Yoshihiro Shimoda"); 2221 MODULE_DESCRIPTION("Renesas Ethernet Switch device driver"); 2222 MODULE_LICENSE("GPL"); 2223