1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet Switch device driver 3 * 4 * Copyright (C) 2022 Renesas Electronics Corporation 5 */ 6 7 #include <linux/dma-mapping.h> 8 #include <linux/err.h> 9 #include <linux/etherdevice.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 #include <linux/phy/phy.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/rtnetlink.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 25 #include "rswitch.h" 26 27 static int rswitch_reg_wait(void __iomem *addr, u32 offs, u32 mask, u32 expected) 28 { 29 u32 val; 30 31 return readl_poll_timeout_atomic(addr + offs, val, (val & mask) == expected, 32 1, RSWITCH_TIMEOUT_US); 33 } 34 35 static void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set) 36 { 37 iowrite32((ioread32(addr + reg) & ~clear) | set, addr + reg); 38 } 39 40 /* Common Agent block (COMA) */ 41 static void rswitch_reset(struct rswitch_private *priv) 42 { 43 iowrite32(RRC_RR, priv->addr + RRC); 44 iowrite32(RRC_RR_CLR, priv->addr + RRC); 45 } 46 47 static void rswitch_clock_enable(struct rswitch_private *priv) 48 { 49 iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC); 50 } 51 52 static void rswitch_clock_disable(struct rswitch_private *priv) 53 { 54 iowrite32(RCDC_RCD, priv->addr + RCDC); 55 } 56 57 static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr, int port) 58 { 59 u32 val = ioread32(coma_addr + RCEC); 60 61 if (val & RCEC_RCE) 62 return (val & BIT(port)) ? true : false; 63 else 64 return false; 65 } 66 67 static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, int port, int enable) 68 { 69 u32 val; 70 71 if (enable) { 72 val = ioread32(coma_addr + RCEC); 73 iowrite32(val | RCEC_RCE | BIT(port), coma_addr + RCEC); 74 } else { 75 val = ioread32(coma_addr + RCDC); 76 iowrite32(val | BIT(port), coma_addr + RCDC); 77 } 78 } 79 80 static int rswitch_bpool_config(struct rswitch_private *priv) 81 { 82 u32 val; 83 84 val = ioread32(priv->addr + CABPIRM); 85 if (val & CABPIRM_BPR) 86 return 0; 87 88 iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM); 89 90 return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR); 91 } 92 93 /* R-Switch-2 block (TOP) */ 94 static void rswitch_top_init(struct rswitch_private *priv) 95 { 96 int i; 97 98 for (i = 0; i < RSWITCH_MAX_NUM_QUEUES; i++) 99 iowrite32((i / 16) << (GWCA_INDEX * 8), priv->addr + TPEMIMC7(i)); 100 } 101 102 /* Forwarding engine block (MFWD) */ 103 static void rswitch_fwd_init(struct rswitch_private *priv) 104 { 105 int i; 106 107 /* For ETHA */ 108 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 109 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i)); 110 iowrite32(0, priv->addr + FWPBFC(i)); 111 } 112 113 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 114 iowrite32(priv->rdev[i]->rx_queue->index, 115 priv->addr + FWPBFCSDC(GWCA_INDEX, i)); 116 iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i)); 117 } 118 119 /* For GWCA */ 120 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index)); 121 iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index)); 122 iowrite32(0, priv->addr + FWPBFC(priv->gwca.index)); 123 iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index)); 124 } 125 126 /* gPTP timer (gPTP) */ 127 static void rswitch_get_timestamp(struct rswitch_private *priv, 128 struct timespec64 *ts) 129 { 130 priv->ptp_priv->info.gettime64(&priv->ptp_priv->info, ts); 131 } 132 133 /* Gateway CPU agent block (GWCA) */ 134 static int rswitch_gwca_change_mode(struct rswitch_private *priv, 135 enum rswitch_gwca_mode mode) 136 { 137 int ret; 138 139 if (!rswitch_agent_clock_is_enabled(priv->addr, priv->gwca.index)) 140 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 1); 141 142 iowrite32(mode, priv->addr + GWMC); 143 144 ret = rswitch_reg_wait(priv->addr, GWMS, GWMS_OPS_MASK, mode); 145 146 if (mode == GWMC_OPC_DISABLE) 147 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 0); 148 149 return ret; 150 } 151 152 static int rswitch_gwca_mcast_table_reset(struct rswitch_private *priv) 153 { 154 iowrite32(GWMTIRM_MTIOG, priv->addr + GWMTIRM); 155 156 return rswitch_reg_wait(priv->addr, GWMTIRM, GWMTIRM_MTR, GWMTIRM_MTR); 157 } 158 159 static int rswitch_gwca_axi_ram_reset(struct rswitch_private *priv) 160 { 161 iowrite32(GWARIRM_ARIOG, priv->addr + GWARIRM); 162 163 return rswitch_reg_wait(priv->addr, GWARIRM, GWARIRM_ARR, GWARIRM_ARR); 164 } 165 166 static void rswitch_gwca_set_rate_limit(struct rswitch_private *priv, int rate) 167 { 168 u32 gwgrlulc, gwgrlc; 169 170 switch (rate) { 171 case 1000: 172 gwgrlulc = 0x0000005f; 173 gwgrlc = 0x00010260; 174 break; 175 default: 176 dev_err(&priv->pdev->dev, "%s: This rate is not supported (%d)\n", __func__, rate); 177 return; 178 } 179 180 iowrite32(gwgrlulc, priv->addr + GWGRLULC); 181 iowrite32(gwgrlc, priv->addr + GWGRLC); 182 } 183 184 static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool tx) 185 { 186 u32 *mask = tx ? priv->gwca.tx_irq_bits : priv->gwca.rx_irq_bits; 187 int i; 188 189 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 190 if (dis[i] & mask[i]) 191 return true; 192 } 193 194 return false; 195 } 196 197 static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis) 198 { 199 int i; 200 201 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 202 dis[i] = ioread32(priv->addr + GWDIS(i)); 203 dis[i] &= ioread32(priv->addr + GWDIE(i)); 204 } 205 } 206 207 static void rswitch_enadis_data_irq(struct rswitch_private *priv, int index, bool enable) 208 { 209 u32 offs = enable ? GWDIE(index / 32) : GWDID(index / 32); 210 211 iowrite32(BIT(index % 32), priv->addr + offs); 212 } 213 214 static void rswitch_ack_data_irq(struct rswitch_private *priv, int index) 215 { 216 u32 offs = GWDIS(index / 32); 217 218 iowrite32(BIT(index % 32), priv->addr + offs); 219 } 220 221 static int rswitch_next_queue_index(struct rswitch_gwca_queue *gq, bool cur, int num) 222 { 223 int index = cur ? gq->cur : gq->dirty; 224 225 if (index + num >= gq->ring_size) 226 index = (index + num) % gq->ring_size; 227 else 228 index += num; 229 230 return index; 231 } 232 233 static int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq) 234 { 235 if (gq->cur >= gq->dirty) 236 return gq->cur - gq->dirty; 237 else 238 return gq->ring_size - gq->dirty + gq->cur; 239 } 240 241 static bool rswitch_is_queue_rxed(struct rswitch_gwca_queue *gq) 242 { 243 struct rswitch_ext_ts_desc *desc = &gq->ts_ring[gq->dirty]; 244 245 if ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) 246 return true; 247 248 return false; 249 } 250 251 static int rswitch_gwca_queue_alloc_skb(struct rswitch_gwca_queue *gq, 252 int start_index, int num) 253 { 254 int i, index; 255 256 for (i = 0; i < num; i++) { 257 index = (i + start_index) % gq->ring_size; 258 if (gq->skbs[index]) 259 continue; 260 gq->skbs[index] = netdev_alloc_skb_ip_align(gq->ndev, 261 PKT_BUF_SZ + RSWITCH_ALIGN - 1); 262 if (!gq->skbs[index]) 263 goto err; 264 } 265 266 return 0; 267 268 err: 269 for (i--; i >= 0; i--) { 270 index = (i + start_index) % gq->ring_size; 271 dev_kfree_skb(gq->skbs[index]); 272 gq->skbs[index] = NULL; 273 } 274 275 return -ENOMEM; 276 } 277 278 static void rswitch_gwca_queue_free(struct net_device *ndev, 279 struct rswitch_gwca_queue *gq) 280 { 281 int i; 282 283 if (gq->gptp) { 284 dma_free_coherent(ndev->dev.parent, 285 sizeof(struct rswitch_ext_ts_desc) * 286 (gq->ring_size + 1), gq->ts_ring, gq->ring_dma); 287 gq->ts_ring = NULL; 288 } else { 289 dma_free_coherent(ndev->dev.parent, 290 sizeof(struct rswitch_ext_desc) * 291 (gq->ring_size + 1), gq->ring, gq->ring_dma); 292 gq->ring = NULL; 293 } 294 295 if (!gq->dir_tx) { 296 for (i = 0; i < gq->ring_size; i++) 297 dev_kfree_skb(gq->skbs[i]); 298 } 299 300 kfree(gq->skbs); 301 gq->skbs = NULL; 302 } 303 304 static int rswitch_gwca_queue_alloc(struct net_device *ndev, 305 struct rswitch_private *priv, 306 struct rswitch_gwca_queue *gq, 307 bool dir_tx, bool gptp, int ring_size) 308 { 309 int i, bit; 310 311 gq->dir_tx = dir_tx; 312 gq->gptp = gptp; 313 gq->ring_size = ring_size; 314 gq->ndev = ndev; 315 316 gq->skbs = kcalloc(gq->ring_size, sizeof(*gq->skbs), GFP_KERNEL); 317 if (!gq->skbs) 318 return -ENOMEM; 319 320 if (!dir_tx) 321 rswitch_gwca_queue_alloc_skb(gq, 0, gq->ring_size); 322 323 if (gptp) 324 gq->ts_ring = dma_alloc_coherent(ndev->dev.parent, 325 sizeof(struct rswitch_ext_ts_desc) * 326 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 327 else 328 gq->ring = dma_alloc_coherent(ndev->dev.parent, 329 sizeof(struct rswitch_ext_desc) * 330 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 331 if (!gq->ts_ring && !gq->ring) 332 goto out; 333 334 i = gq->index / 32; 335 bit = BIT(gq->index % 32); 336 if (dir_tx) 337 priv->gwca.tx_irq_bits[i] |= bit; 338 else 339 priv->gwca.rx_irq_bits[i] |= bit; 340 341 return 0; 342 343 out: 344 rswitch_gwca_queue_free(ndev, gq); 345 346 return -ENOMEM; 347 } 348 349 static void rswitch_desc_set_dptr(struct rswitch_desc *desc, dma_addr_t addr) 350 { 351 desc->dptrl = cpu_to_le32(lower_32_bits(addr)); 352 desc->dptrh = upper_32_bits(addr) & 0xff; 353 } 354 355 static dma_addr_t rswitch_desc_get_dptr(const struct rswitch_desc *desc) 356 { 357 return __le32_to_cpu(desc->dptrl) | (u64)(desc->dptrh) << 32; 358 } 359 360 static int rswitch_gwca_queue_format(struct net_device *ndev, 361 struct rswitch_private *priv, 362 struct rswitch_gwca_queue *gq) 363 { 364 int tx_ring_size = sizeof(struct rswitch_ext_desc) * gq->ring_size; 365 struct rswitch_ext_desc *desc; 366 struct rswitch_desc *linkfix; 367 dma_addr_t dma_addr; 368 int i; 369 370 memset(gq->ring, 0, tx_ring_size); 371 for (i = 0, desc = gq->ring; i < gq->ring_size; i++, desc++) { 372 if (!gq->dir_tx) { 373 dma_addr = dma_map_single(ndev->dev.parent, 374 gq->skbs[i]->data, PKT_BUF_SZ, 375 DMA_FROM_DEVICE); 376 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 377 goto err; 378 379 desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ); 380 rswitch_desc_set_dptr(&desc->desc, dma_addr); 381 desc->desc.die_dt = DT_FEMPTY | DIE; 382 } else { 383 desc->desc.die_dt = DT_EEMPTY | DIE; 384 } 385 } 386 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 387 desc->desc.die_dt = DT_LINKFIX; 388 389 linkfix = &priv->linkfix_table[gq->index]; 390 linkfix->die_dt = DT_LINKFIX; 391 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 392 393 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DQT : 0) | GWDCC_EDE, 394 priv->addr + GWDCC_OFFS(gq->index)); 395 396 return 0; 397 398 err: 399 if (!gq->dir_tx) { 400 for (i--, desc = gq->ring; i >= 0; i--, desc++) { 401 dma_addr = rswitch_desc_get_dptr(&desc->desc); 402 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, 403 DMA_FROM_DEVICE); 404 } 405 } 406 407 return -ENOMEM; 408 } 409 410 static int rswitch_gwca_queue_ts_fill(struct net_device *ndev, 411 struct rswitch_gwca_queue *gq, 412 int start_index, int num) 413 { 414 struct rswitch_device *rdev = netdev_priv(ndev); 415 struct rswitch_ext_ts_desc *desc; 416 dma_addr_t dma_addr; 417 int i, index; 418 419 for (i = 0; i < num; i++) { 420 index = (i + start_index) % gq->ring_size; 421 desc = &gq->ts_ring[index]; 422 if (!gq->dir_tx) { 423 dma_addr = dma_map_single(ndev->dev.parent, 424 gq->skbs[index]->data, PKT_BUF_SZ, 425 DMA_FROM_DEVICE); 426 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 427 goto err; 428 429 desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ); 430 rswitch_desc_set_dptr(&desc->desc, dma_addr); 431 dma_wmb(); 432 desc->desc.die_dt = DT_FEMPTY | DIE; 433 desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index)); 434 } else { 435 desc->desc.die_dt = DT_EEMPTY | DIE; 436 } 437 } 438 439 return 0; 440 441 err: 442 if (!gq->dir_tx) { 443 for (i--; i >= 0; i--) { 444 index = (i + start_index) % gq->ring_size; 445 desc = &gq->ts_ring[index]; 446 dma_addr = rswitch_desc_get_dptr(&desc->desc); 447 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, 448 DMA_FROM_DEVICE); 449 } 450 } 451 452 return -ENOMEM; 453 } 454 455 static int rswitch_gwca_queue_ts_format(struct net_device *ndev, 456 struct rswitch_private *priv, 457 struct rswitch_gwca_queue *gq) 458 { 459 int tx_ts_ring_size = sizeof(struct rswitch_ext_ts_desc) * gq->ring_size; 460 struct rswitch_ext_ts_desc *desc; 461 struct rswitch_desc *linkfix; 462 int err; 463 464 memset(gq->ts_ring, 0, tx_ts_ring_size); 465 err = rswitch_gwca_queue_ts_fill(ndev, gq, 0, gq->ring_size); 466 if (err < 0) 467 return err; 468 469 desc = &gq->ts_ring[gq->ring_size]; /* Last */ 470 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 471 desc->desc.die_dt = DT_LINKFIX; 472 473 linkfix = &priv->linkfix_table[gq->index]; 474 linkfix->die_dt = DT_LINKFIX; 475 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 476 477 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DQT : 0) | GWDCC_ETS | GWDCC_EDE, 478 priv->addr + GWDCC_OFFS(gq->index)); 479 480 return 0; 481 } 482 483 static int rswitch_gwca_desc_alloc(struct rswitch_private *priv) 484 { 485 int i, num_queues = priv->gwca.num_queues; 486 struct device *dev = &priv->pdev->dev; 487 488 priv->linkfix_table_size = sizeof(struct rswitch_desc) * num_queues; 489 priv->linkfix_table = dma_alloc_coherent(dev, priv->linkfix_table_size, 490 &priv->linkfix_table_dma, GFP_KERNEL); 491 if (!priv->linkfix_table) 492 return -ENOMEM; 493 for (i = 0; i < num_queues; i++) 494 priv->linkfix_table[i].die_dt = DT_EOS; 495 496 return 0; 497 } 498 499 static void rswitch_gwca_desc_free(struct rswitch_private *priv) 500 { 501 if (priv->linkfix_table) 502 dma_free_coherent(&priv->pdev->dev, priv->linkfix_table_size, 503 priv->linkfix_table, priv->linkfix_table_dma); 504 priv->linkfix_table = NULL; 505 } 506 507 static struct rswitch_gwca_queue *rswitch_gwca_get(struct rswitch_private *priv) 508 { 509 struct rswitch_gwca_queue *gq; 510 int index; 511 512 index = find_first_zero_bit(priv->gwca.used, priv->gwca.num_queues); 513 if (index >= priv->gwca.num_queues) 514 return NULL; 515 set_bit(index, priv->gwca.used); 516 gq = &priv->gwca.queues[index]; 517 memset(gq, 0, sizeof(*gq)); 518 gq->index = index; 519 520 return gq; 521 } 522 523 static void rswitch_gwca_put(struct rswitch_private *priv, 524 struct rswitch_gwca_queue *gq) 525 { 526 clear_bit(gq->index, priv->gwca.used); 527 } 528 529 static int rswitch_txdmac_alloc(struct net_device *ndev) 530 { 531 struct rswitch_device *rdev = netdev_priv(ndev); 532 struct rswitch_private *priv = rdev->priv; 533 int err; 534 535 rdev->tx_queue = rswitch_gwca_get(priv); 536 if (!rdev->tx_queue) 537 return -EBUSY; 538 539 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->tx_queue, true, false, 540 TX_RING_SIZE); 541 if (err < 0) { 542 rswitch_gwca_put(priv, rdev->tx_queue); 543 return err; 544 } 545 546 return 0; 547 } 548 549 static void rswitch_txdmac_free(struct net_device *ndev) 550 { 551 struct rswitch_device *rdev = netdev_priv(ndev); 552 553 rswitch_gwca_queue_free(ndev, rdev->tx_queue); 554 rswitch_gwca_put(rdev->priv, rdev->tx_queue); 555 } 556 557 static int rswitch_txdmac_init(struct rswitch_private *priv, int index) 558 { 559 struct rswitch_device *rdev = priv->rdev[index]; 560 561 return rswitch_gwca_queue_format(rdev->ndev, priv, rdev->tx_queue); 562 } 563 564 static int rswitch_rxdmac_alloc(struct net_device *ndev) 565 { 566 struct rswitch_device *rdev = netdev_priv(ndev); 567 struct rswitch_private *priv = rdev->priv; 568 int err; 569 570 rdev->rx_queue = rswitch_gwca_get(priv); 571 if (!rdev->rx_queue) 572 return -EBUSY; 573 574 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->rx_queue, false, true, 575 RX_RING_SIZE); 576 if (err < 0) { 577 rswitch_gwca_put(priv, rdev->rx_queue); 578 return err; 579 } 580 581 return 0; 582 } 583 584 static void rswitch_rxdmac_free(struct net_device *ndev) 585 { 586 struct rswitch_device *rdev = netdev_priv(ndev); 587 588 rswitch_gwca_queue_free(ndev, rdev->rx_queue); 589 rswitch_gwca_put(rdev->priv, rdev->rx_queue); 590 } 591 592 static int rswitch_rxdmac_init(struct rswitch_private *priv, int index) 593 { 594 struct rswitch_device *rdev = priv->rdev[index]; 595 struct net_device *ndev = rdev->ndev; 596 597 return rswitch_gwca_queue_ts_format(ndev, priv, rdev->rx_queue); 598 } 599 600 static int rswitch_gwca_hw_init(struct rswitch_private *priv) 601 { 602 int i, err; 603 604 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 605 if (err < 0) 606 return err; 607 err = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG); 608 if (err < 0) 609 return err; 610 611 err = rswitch_gwca_mcast_table_reset(priv); 612 if (err < 0) 613 return err; 614 err = rswitch_gwca_axi_ram_reset(priv); 615 if (err < 0) 616 return err; 617 618 iowrite32(GWVCC_VEM_SC_TAG, priv->addr + GWVCC); 619 iowrite32(0, priv->addr + GWTTFC); 620 iowrite32(lower_32_bits(priv->linkfix_table_dma), priv->addr + GWDCBAC1); 621 iowrite32(upper_32_bits(priv->linkfix_table_dma), priv->addr + GWDCBAC0); 622 rswitch_gwca_set_rate_limit(priv, priv->gwca.speed); 623 624 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 625 err = rswitch_rxdmac_init(priv, i); 626 if (err < 0) 627 return err; 628 err = rswitch_txdmac_init(priv, i); 629 if (err < 0) 630 return err; 631 } 632 633 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 634 if (err < 0) 635 return err; 636 return rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION); 637 } 638 639 static int rswitch_gwca_hw_deinit(struct rswitch_private *priv) 640 { 641 int err; 642 643 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 644 if (err < 0) 645 return err; 646 err = rswitch_gwca_change_mode(priv, GWMC_OPC_RESET); 647 if (err < 0) 648 return err; 649 650 return rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 651 } 652 653 static int rswitch_gwca_halt(struct rswitch_private *priv) 654 { 655 int err; 656 657 priv->gwca_halt = true; 658 err = rswitch_gwca_hw_deinit(priv); 659 dev_err(&priv->pdev->dev, "halted (%d)\n", err); 660 661 return err; 662 } 663 664 static bool rswitch_rx(struct net_device *ndev, int *quota) 665 { 666 struct rswitch_device *rdev = netdev_priv(ndev); 667 struct rswitch_gwca_queue *gq = rdev->rx_queue; 668 struct rswitch_ext_ts_desc *desc; 669 int limit, boguscnt, num, ret; 670 struct sk_buff *skb; 671 dma_addr_t dma_addr; 672 u16 pkt_len; 673 u32 get_ts; 674 675 boguscnt = min_t(int, gq->ring_size, *quota); 676 limit = boguscnt; 677 678 desc = &gq->ts_ring[gq->cur]; 679 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) { 680 if (--boguscnt < 0) 681 break; 682 dma_rmb(); 683 pkt_len = le16_to_cpu(desc->desc.info_ds) & RX_DS; 684 skb = gq->skbs[gq->cur]; 685 gq->skbs[gq->cur] = NULL; 686 dma_addr = rswitch_desc_get_dptr(&desc->desc); 687 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, DMA_FROM_DEVICE); 688 get_ts = rdev->priv->ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 689 if (get_ts) { 690 struct skb_shared_hwtstamps *shhwtstamps; 691 struct timespec64 ts; 692 693 shhwtstamps = skb_hwtstamps(skb); 694 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 695 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 696 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 697 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 698 } 699 skb_put(skb, pkt_len); 700 skb->protocol = eth_type_trans(skb, ndev); 701 netif_receive_skb(skb); 702 rdev->ndev->stats.rx_packets++; 703 rdev->ndev->stats.rx_bytes += pkt_len; 704 705 gq->cur = rswitch_next_queue_index(gq, true, 1); 706 desc = &gq->ts_ring[gq->cur]; 707 } 708 709 num = rswitch_get_num_cur_queues(gq); 710 ret = rswitch_gwca_queue_alloc_skb(gq, gq->dirty, num); 711 if (ret < 0) 712 goto err; 713 ret = rswitch_gwca_queue_ts_fill(ndev, gq, gq->dirty, num); 714 if (ret < 0) 715 goto err; 716 gq->dirty = rswitch_next_queue_index(gq, false, num); 717 718 *quota -= limit - (++boguscnt); 719 720 return boguscnt <= 0; 721 722 err: 723 rswitch_gwca_halt(rdev->priv); 724 725 return 0; 726 } 727 728 static int rswitch_tx_free(struct net_device *ndev, bool free_txed_only) 729 { 730 struct rswitch_device *rdev = netdev_priv(ndev); 731 struct rswitch_gwca_queue *gq = rdev->tx_queue; 732 struct rswitch_ext_desc *desc; 733 dma_addr_t dma_addr; 734 struct sk_buff *skb; 735 int free_num = 0; 736 int size; 737 738 for (; rswitch_get_num_cur_queues(gq) > 0; 739 gq->dirty = rswitch_next_queue_index(gq, false, 1)) { 740 desc = &gq->ring[gq->dirty]; 741 if (free_txed_only && (desc->desc.die_dt & DT_MASK) != DT_FEMPTY) 742 break; 743 744 dma_rmb(); 745 size = le16_to_cpu(desc->desc.info_ds) & TX_DS; 746 skb = gq->skbs[gq->dirty]; 747 if (skb) { 748 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 749 struct skb_shared_hwtstamps shhwtstamps; 750 struct timespec64 ts; 751 752 rswitch_get_timestamp(rdev->priv, &ts); 753 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 754 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 755 skb_tstamp_tx(skb, &shhwtstamps); 756 } 757 dma_addr = rswitch_desc_get_dptr(&desc->desc); 758 dma_unmap_single(ndev->dev.parent, dma_addr, 759 size, DMA_TO_DEVICE); 760 dev_kfree_skb_any(gq->skbs[gq->dirty]); 761 gq->skbs[gq->dirty] = NULL; 762 free_num++; 763 } 764 desc->desc.die_dt = DT_EEMPTY; 765 rdev->ndev->stats.tx_packets++; 766 rdev->ndev->stats.tx_bytes += size; 767 } 768 769 return free_num; 770 } 771 772 static int rswitch_poll(struct napi_struct *napi, int budget) 773 { 774 struct net_device *ndev = napi->dev; 775 struct rswitch_private *priv; 776 struct rswitch_device *rdev; 777 int quota = budget; 778 779 rdev = netdev_priv(ndev); 780 priv = rdev->priv; 781 782 retry: 783 rswitch_tx_free(ndev, true); 784 785 if (rswitch_rx(ndev, "a)) 786 goto out; 787 else if (rdev->priv->gwca_halt) 788 goto err; 789 else if (rswitch_is_queue_rxed(rdev->rx_queue)) 790 goto retry; 791 792 netif_wake_subqueue(ndev, 0); 793 794 napi_complete(napi); 795 796 rswitch_enadis_data_irq(priv, rdev->tx_queue->index, true); 797 rswitch_enadis_data_irq(priv, rdev->rx_queue->index, true); 798 799 out: 800 return budget - quota; 801 802 err: 803 napi_complete(napi); 804 805 return 0; 806 } 807 808 static void rswitch_queue_interrupt(struct net_device *ndev) 809 { 810 struct rswitch_device *rdev = netdev_priv(ndev); 811 812 if (napi_schedule_prep(&rdev->napi)) { 813 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 814 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 815 __napi_schedule(&rdev->napi); 816 } 817 } 818 819 static irqreturn_t rswitch_data_irq(struct rswitch_private *priv, u32 *dis) 820 { 821 struct rswitch_gwca_queue *gq; 822 int i, index, bit; 823 824 for (i = 0; i < priv->gwca.num_queues; i++) { 825 gq = &priv->gwca.queues[i]; 826 index = gq->index / 32; 827 bit = BIT(gq->index % 32); 828 if (!(dis[index] & bit)) 829 continue; 830 831 rswitch_ack_data_irq(priv, gq->index); 832 rswitch_queue_interrupt(gq->ndev); 833 } 834 835 return IRQ_HANDLED; 836 } 837 838 static irqreturn_t rswitch_gwca_irq(int irq, void *dev_id) 839 { 840 struct rswitch_private *priv = dev_id; 841 u32 dis[RSWITCH_NUM_IRQ_REGS]; 842 irqreturn_t ret = IRQ_NONE; 843 844 rswitch_get_data_irq_status(priv, dis); 845 846 if (rswitch_is_any_data_irq(priv, dis, true) || 847 rswitch_is_any_data_irq(priv, dis, false)) 848 ret = rswitch_data_irq(priv, dis); 849 850 return ret; 851 } 852 853 static int rswitch_gwca_request_irqs(struct rswitch_private *priv) 854 { 855 char *resource_name, *irq_name; 856 int i, ret, irq; 857 858 for (i = 0; i < GWCA_NUM_IRQS; i++) { 859 resource_name = kasprintf(GFP_KERNEL, GWCA_IRQ_RESOURCE_NAME, i); 860 if (!resource_name) 861 return -ENOMEM; 862 863 irq = platform_get_irq_byname(priv->pdev, resource_name); 864 kfree(resource_name); 865 if (irq < 0) 866 return irq; 867 868 irq_name = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL, 869 GWCA_IRQ_NAME, i); 870 if (!irq_name) 871 return -ENOMEM; 872 873 ret = devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_irq, 874 0, irq_name, priv); 875 if (ret < 0) 876 return ret; 877 } 878 879 return 0; 880 } 881 882 /* Ethernet TSN Agent block (ETHA) and Ethernet MAC IP block (RMAC) */ 883 static int rswitch_etha_change_mode(struct rswitch_etha *etha, 884 enum rswitch_etha_mode mode) 885 { 886 int ret; 887 888 if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index)) 889 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1); 890 891 iowrite32(mode, etha->addr + EAMC); 892 893 ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode); 894 895 if (mode == EAMC_OPC_DISABLE) 896 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0); 897 898 return ret; 899 } 900 901 static void rswitch_etha_read_mac_address(struct rswitch_etha *etha) 902 { 903 u32 mrmac0 = ioread32(etha->addr + MRMAC0); 904 u32 mrmac1 = ioread32(etha->addr + MRMAC1); 905 u8 *mac = ða->mac_addr[0]; 906 907 mac[0] = (mrmac0 >> 8) & 0xFF; 908 mac[1] = (mrmac0 >> 0) & 0xFF; 909 mac[2] = (mrmac1 >> 24) & 0xFF; 910 mac[3] = (mrmac1 >> 16) & 0xFF; 911 mac[4] = (mrmac1 >> 8) & 0xFF; 912 mac[5] = (mrmac1 >> 0) & 0xFF; 913 } 914 915 static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac) 916 { 917 iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0); 918 iowrite32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], 919 etha->addr + MRMAC1); 920 } 921 922 static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha) 923 { 924 iowrite32(MLVC_PLV, etha->addr + MLVC); 925 926 return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0); 927 } 928 929 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac) 930 { 931 u32 val; 932 933 rswitch_etha_write_mac_address(etha, mac); 934 935 switch (etha->speed) { 936 case 100: 937 val = MPIC_LSC_100M; 938 break; 939 case 1000: 940 val = MPIC_LSC_1G; 941 break; 942 case 2500: 943 val = MPIC_LSC_2_5G; 944 break; 945 default: 946 return; 947 } 948 949 iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC); 950 } 951 952 static void rswitch_etha_enable_mii(struct rswitch_etha *etha) 953 { 954 rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, 955 MPIC_PSMCS(0x05) | MPIC_PSMHT(0x06)); 956 rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45); 957 } 958 959 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac) 960 { 961 int err; 962 963 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 964 if (err < 0) 965 return err; 966 err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG); 967 if (err < 0) 968 return err; 969 970 iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC); 971 rswitch_rmac_setting(etha, mac); 972 rswitch_etha_enable_mii(etha); 973 974 err = rswitch_etha_wait_link_verification(etha); 975 if (err < 0) 976 return err; 977 978 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 979 if (err < 0) 980 return err; 981 982 return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION); 983 } 984 985 static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read, 986 int phyad, int devad, int regad, int data) 987 { 988 int pop = read ? MDIO_READ_C45 : MDIO_WRITE_C45; 989 u32 val; 990 int ret; 991 992 if (devad == 0xffffffff) 993 return -ENODEV; 994 995 writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); 996 997 val = MPSM_PSME | MPSM_MFF_C45; 998 iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 999 1000 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1001 if (ret) 1002 return ret; 1003 1004 rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1005 1006 if (read) { 1007 writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1008 1009 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1010 if (ret) 1011 return ret; 1012 1013 ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; 1014 1015 rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1016 } else { 1017 iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val, 1018 etha->addr + MPSM); 1019 1020 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS); 1021 } 1022 1023 return ret; 1024 } 1025 1026 static int rswitch_etha_mii_read_c45(struct mii_bus *bus, int addr, int devad, 1027 int regad) 1028 { 1029 struct rswitch_etha *etha = bus->priv; 1030 1031 return rswitch_etha_set_access(etha, true, addr, devad, regad, 0); 1032 } 1033 1034 static int rswitch_etha_mii_write_c45(struct mii_bus *bus, int addr, int devad, 1035 int regad, u16 val) 1036 { 1037 struct rswitch_etha *etha = bus->priv; 1038 1039 return rswitch_etha_set_access(etha, false, addr, devad, regad, val); 1040 } 1041 1042 /* Call of_node_put(port) after done */ 1043 static struct device_node *rswitch_get_port_node(struct rswitch_device *rdev) 1044 { 1045 struct device_node *ports, *port; 1046 int err = 0; 1047 u32 index; 1048 1049 ports = of_get_child_by_name(rdev->ndev->dev.parent->of_node, 1050 "ethernet-ports"); 1051 if (!ports) 1052 return NULL; 1053 1054 for_each_child_of_node(ports, port) { 1055 err = of_property_read_u32(port, "reg", &index); 1056 if (err < 0) { 1057 port = NULL; 1058 goto out; 1059 } 1060 if (index == rdev->etha->index) { 1061 if (!of_device_is_available(port)) 1062 port = NULL; 1063 break; 1064 } 1065 } 1066 1067 out: 1068 of_node_put(ports); 1069 1070 return port; 1071 } 1072 1073 static int rswitch_etha_get_params(struct rswitch_device *rdev) 1074 { 1075 u32 max_speed; 1076 int err; 1077 1078 if (!rdev->np_port) 1079 return 0; /* ignored */ 1080 1081 err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface); 1082 if (err) 1083 return err; 1084 1085 err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed); 1086 if (!err) { 1087 rdev->etha->speed = max_speed; 1088 return 0; 1089 } 1090 1091 /* if no "max-speed" property, let's use default speed */ 1092 switch (rdev->etha->phy_interface) { 1093 case PHY_INTERFACE_MODE_MII: 1094 rdev->etha->speed = SPEED_100; 1095 break; 1096 case PHY_INTERFACE_MODE_SGMII: 1097 rdev->etha->speed = SPEED_1000; 1098 break; 1099 case PHY_INTERFACE_MODE_USXGMII: 1100 rdev->etha->speed = SPEED_2500; 1101 break; 1102 default: 1103 return -EINVAL; 1104 } 1105 1106 return 0; 1107 } 1108 1109 static int rswitch_mii_register(struct rswitch_device *rdev) 1110 { 1111 struct device_node *mdio_np; 1112 struct mii_bus *mii_bus; 1113 int err; 1114 1115 mii_bus = mdiobus_alloc(); 1116 if (!mii_bus) 1117 return -ENOMEM; 1118 1119 mii_bus->name = "rswitch_mii"; 1120 sprintf(mii_bus->id, "etha%d", rdev->etha->index); 1121 mii_bus->priv = rdev->etha; 1122 mii_bus->read_c45 = rswitch_etha_mii_read_c45; 1123 mii_bus->write_c45 = rswitch_etha_mii_write_c45; 1124 mii_bus->parent = &rdev->priv->pdev->dev; 1125 1126 mdio_np = of_get_child_by_name(rdev->np_port, "mdio"); 1127 err = of_mdiobus_register(mii_bus, mdio_np); 1128 if (err < 0) { 1129 mdiobus_free(mii_bus); 1130 goto out; 1131 } 1132 1133 rdev->etha->mii = mii_bus; 1134 1135 out: 1136 of_node_put(mdio_np); 1137 1138 return err; 1139 } 1140 1141 static void rswitch_mii_unregister(struct rswitch_device *rdev) 1142 { 1143 if (rdev->etha->mii) { 1144 mdiobus_unregister(rdev->etha->mii); 1145 mdiobus_free(rdev->etha->mii); 1146 rdev->etha->mii = NULL; 1147 } 1148 } 1149 1150 static void rswitch_adjust_link(struct net_device *ndev) 1151 { 1152 struct rswitch_device *rdev = netdev_priv(ndev); 1153 struct phy_device *phydev = ndev->phydev; 1154 1155 /* Current hardware has a restriction not to change speed at runtime */ 1156 if (phydev->link != rdev->etha->link) { 1157 phy_print_status(phydev); 1158 if (phydev->link) 1159 phy_power_on(rdev->serdes); 1160 else 1161 phy_power_off(rdev->serdes); 1162 1163 rdev->etha->link = phydev->link; 1164 } 1165 } 1166 1167 static void rswitch_phy_remove_link_mode(struct rswitch_device *rdev, 1168 struct phy_device *phydev) 1169 { 1170 /* Current hardware has a restriction not to change speed at runtime */ 1171 switch (rdev->etha->speed) { 1172 case SPEED_2500: 1173 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1174 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1175 break; 1176 case SPEED_1000: 1177 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1178 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1179 break; 1180 case SPEED_100: 1181 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1182 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1183 break; 1184 default: 1185 break; 1186 } 1187 1188 phy_set_max_speed(phydev, rdev->etha->speed); 1189 } 1190 1191 static int rswitch_phy_device_init(struct rswitch_device *rdev) 1192 { 1193 struct phy_device *phydev; 1194 struct device_node *phy; 1195 int err = -ENOENT; 1196 1197 if (!rdev->np_port) 1198 return -ENODEV; 1199 1200 phy = of_parse_phandle(rdev->np_port, "phy-handle", 0); 1201 if (!phy) 1202 return -ENODEV; 1203 1204 /* Set phydev->host_interfaces before calling of_phy_connect() to 1205 * configure the PHY with the information of host_interfaces. 1206 */ 1207 phydev = of_phy_find_device(phy); 1208 if (!phydev) 1209 goto out; 1210 __set_bit(rdev->etha->phy_interface, phydev->host_interfaces); 1211 1212 phydev = of_phy_connect(rdev->ndev, phy, rswitch_adjust_link, 0, 1213 rdev->etha->phy_interface); 1214 if (!phydev) 1215 goto out; 1216 1217 phy_set_max_speed(phydev, SPEED_2500); 1218 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1219 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1220 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1221 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1222 rswitch_phy_remove_link_mode(rdev, phydev); 1223 1224 phy_attached_info(phydev); 1225 1226 err = 0; 1227 out: 1228 of_node_put(phy); 1229 1230 return err; 1231 } 1232 1233 static void rswitch_phy_device_deinit(struct rswitch_device *rdev) 1234 { 1235 if (rdev->ndev->phydev) { 1236 phy_disconnect(rdev->ndev->phydev); 1237 rdev->ndev->phydev = NULL; 1238 } 1239 } 1240 1241 static int rswitch_serdes_set_params(struct rswitch_device *rdev) 1242 { 1243 int err; 1244 1245 err = phy_set_mode_ext(rdev->serdes, PHY_MODE_ETHERNET, 1246 rdev->etha->phy_interface); 1247 if (err < 0) 1248 return err; 1249 1250 return phy_set_speed(rdev->serdes, rdev->etha->speed); 1251 } 1252 1253 static int rswitch_ether_port_init_one(struct rswitch_device *rdev) 1254 { 1255 int err; 1256 1257 if (!rdev->etha->operated) { 1258 err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); 1259 if (err < 0) 1260 return err; 1261 rdev->etha->operated = true; 1262 } 1263 1264 err = rswitch_mii_register(rdev); 1265 if (err < 0) 1266 return err; 1267 1268 err = rswitch_phy_device_init(rdev); 1269 if (err < 0) 1270 goto err_phy_device_init; 1271 1272 rdev->serdes = devm_of_phy_get(&rdev->priv->pdev->dev, rdev->np_port, NULL); 1273 if (IS_ERR(rdev->serdes)) { 1274 err = PTR_ERR(rdev->serdes); 1275 goto err_serdes_phy_get; 1276 } 1277 1278 err = rswitch_serdes_set_params(rdev); 1279 if (err < 0) 1280 goto err_serdes_set_params; 1281 1282 return 0; 1283 1284 err_serdes_set_params: 1285 err_serdes_phy_get: 1286 rswitch_phy_device_deinit(rdev); 1287 1288 err_phy_device_init: 1289 rswitch_mii_unregister(rdev); 1290 1291 return err; 1292 } 1293 1294 static void rswitch_ether_port_deinit_one(struct rswitch_device *rdev) 1295 { 1296 rswitch_phy_device_deinit(rdev); 1297 rswitch_mii_unregister(rdev); 1298 } 1299 1300 static int rswitch_ether_port_init_all(struct rswitch_private *priv) 1301 { 1302 int i, err; 1303 1304 rswitch_for_each_enabled_port(priv, i) { 1305 err = rswitch_ether_port_init_one(priv->rdev[i]); 1306 if (err) 1307 goto err_init_one; 1308 } 1309 1310 rswitch_for_each_enabled_port(priv, i) { 1311 err = phy_init(priv->rdev[i]->serdes); 1312 if (err) 1313 goto err_serdes; 1314 } 1315 1316 return 0; 1317 1318 err_serdes: 1319 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1320 phy_exit(priv->rdev[i]->serdes); 1321 i = RSWITCH_NUM_PORTS; 1322 1323 err_init_one: 1324 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1325 rswitch_ether_port_deinit_one(priv->rdev[i]); 1326 1327 return err; 1328 } 1329 1330 static void rswitch_ether_port_deinit_all(struct rswitch_private *priv) 1331 { 1332 int i; 1333 1334 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1335 phy_exit(priv->rdev[i]->serdes); 1336 rswitch_ether_port_deinit_one(priv->rdev[i]); 1337 } 1338 } 1339 1340 static int rswitch_open(struct net_device *ndev) 1341 { 1342 struct rswitch_device *rdev = netdev_priv(ndev); 1343 1344 phy_start(ndev->phydev); 1345 1346 napi_enable(&rdev->napi); 1347 netif_start_queue(ndev); 1348 1349 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, true); 1350 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, true); 1351 1352 return 0; 1353 }; 1354 1355 static int rswitch_stop(struct net_device *ndev) 1356 { 1357 struct rswitch_device *rdev = netdev_priv(ndev); 1358 1359 netif_tx_stop_all_queues(ndev); 1360 1361 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 1362 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 1363 1364 phy_stop(ndev->phydev); 1365 napi_disable(&rdev->napi); 1366 1367 return 0; 1368 }; 1369 1370 static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1371 { 1372 struct rswitch_device *rdev = netdev_priv(ndev); 1373 struct rswitch_gwca_queue *gq = rdev->tx_queue; 1374 struct rswitch_ext_desc *desc; 1375 int ret = NETDEV_TX_OK; 1376 dma_addr_t dma_addr; 1377 1378 if (rswitch_get_num_cur_queues(gq) >= gq->ring_size - 1) { 1379 netif_stop_subqueue(ndev, 0); 1380 return ret; 1381 } 1382 1383 if (skb_put_padto(skb, ETH_ZLEN)) 1384 return ret; 1385 1386 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, DMA_TO_DEVICE); 1387 if (dma_mapping_error(ndev->dev.parent, dma_addr)) { 1388 dev_kfree_skb_any(skb); 1389 return ret; 1390 } 1391 1392 gq->skbs[gq->cur] = skb; 1393 desc = &gq->ring[gq->cur]; 1394 rswitch_desc_set_dptr(&desc->desc, dma_addr); 1395 desc->desc.info_ds = cpu_to_le16(skb->len); 1396 1397 desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) | INFO1_FMT); 1398 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 1399 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1400 rdev->ts_tag++; 1401 desc->info1 |= cpu_to_le64(INFO1_TSUN(rdev->ts_tag) | INFO1_TXC); 1402 } 1403 skb_tx_timestamp(skb); 1404 1405 dma_wmb(); 1406 1407 desc->desc.die_dt = DT_FSINGLE | DIE; 1408 wmb(); /* gq->cur must be incremented after die_dt was set */ 1409 1410 gq->cur = rswitch_next_queue_index(gq, true, 1); 1411 rswitch_modify(rdev->addr, GWTRC(gq->index), 0, BIT(gq->index % 32)); 1412 1413 return ret; 1414 } 1415 1416 static struct net_device_stats *rswitch_get_stats(struct net_device *ndev) 1417 { 1418 return &ndev->stats; 1419 } 1420 1421 static int rswitch_hwstamp_get(struct net_device *ndev, struct ifreq *req) 1422 { 1423 struct rswitch_device *rdev = netdev_priv(ndev); 1424 struct rcar_gen4_ptp_private *ptp_priv; 1425 struct hwtstamp_config config; 1426 1427 ptp_priv = rdev->priv->ptp_priv; 1428 1429 config.flags = 0; 1430 config.tx_type = ptp_priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1431 HWTSTAMP_TX_OFF; 1432 switch (ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE) { 1433 case RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT: 1434 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1435 break; 1436 case RCAR_GEN4_RXTSTAMP_TYPE_ALL: 1437 config.rx_filter = HWTSTAMP_FILTER_ALL; 1438 break; 1439 default: 1440 config.rx_filter = HWTSTAMP_FILTER_NONE; 1441 break; 1442 } 1443 1444 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1445 } 1446 1447 static int rswitch_hwstamp_set(struct net_device *ndev, struct ifreq *req) 1448 { 1449 struct rswitch_device *rdev = netdev_priv(ndev); 1450 u32 tstamp_rx_ctrl = RCAR_GEN4_RXTSTAMP_ENABLED; 1451 struct hwtstamp_config config; 1452 u32 tstamp_tx_ctrl; 1453 1454 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1455 return -EFAULT; 1456 1457 if (config.flags) 1458 return -EINVAL; 1459 1460 switch (config.tx_type) { 1461 case HWTSTAMP_TX_OFF: 1462 tstamp_tx_ctrl = 0; 1463 break; 1464 case HWTSTAMP_TX_ON: 1465 tstamp_tx_ctrl = RCAR_GEN4_TXTSTAMP_ENABLED; 1466 break; 1467 default: 1468 return -ERANGE; 1469 } 1470 1471 switch (config.rx_filter) { 1472 case HWTSTAMP_FILTER_NONE: 1473 tstamp_rx_ctrl = 0; 1474 break; 1475 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1476 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 1477 break; 1478 default: 1479 config.rx_filter = HWTSTAMP_FILTER_ALL; 1480 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_ALL; 1481 break; 1482 } 1483 1484 rdev->priv->ptp_priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1485 rdev->priv->ptp_priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1486 1487 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1488 } 1489 1490 static int rswitch_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1491 { 1492 if (!netif_running(ndev)) 1493 return -EINVAL; 1494 1495 switch (cmd) { 1496 case SIOCGHWTSTAMP: 1497 return rswitch_hwstamp_get(ndev, req); 1498 case SIOCSHWTSTAMP: 1499 return rswitch_hwstamp_set(ndev, req); 1500 default: 1501 return phy_mii_ioctl(ndev->phydev, req, cmd); 1502 } 1503 } 1504 1505 static const struct net_device_ops rswitch_netdev_ops = { 1506 .ndo_open = rswitch_open, 1507 .ndo_stop = rswitch_stop, 1508 .ndo_start_xmit = rswitch_start_xmit, 1509 .ndo_get_stats = rswitch_get_stats, 1510 .ndo_eth_ioctl = rswitch_eth_ioctl, 1511 .ndo_validate_addr = eth_validate_addr, 1512 .ndo_set_mac_address = eth_mac_addr, 1513 }; 1514 1515 static int rswitch_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) 1516 { 1517 struct rswitch_device *rdev = netdev_priv(ndev); 1518 1519 info->phc_index = ptp_clock_index(rdev->priv->ptp_priv->clock); 1520 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1521 SOF_TIMESTAMPING_RX_SOFTWARE | 1522 SOF_TIMESTAMPING_SOFTWARE | 1523 SOF_TIMESTAMPING_TX_HARDWARE | 1524 SOF_TIMESTAMPING_RX_HARDWARE | 1525 SOF_TIMESTAMPING_RAW_HARDWARE; 1526 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 1527 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1528 1529 return 0; 1530 } 1531 1532 static const struct ethtool_ops rswitch_ethtool_ops = { 1533 .get_ts_info = rswitch_get_ts_info, 1534 }; 1535 1536 static const struct of_device_id renesas_eth_sw_of_table[] = { 1537 { .compatible = "renesas,r8a779f0-ether-switch", }, 1538 { } 1539 }; 1540 MODULE_DEVICE_TABLE(of, renesas_eth_sw_of_table); 1541 1542 static void rswitch_etha_init(struct rswitch_private *priv, int index) 1543 { 1544 struct rswitch_etha *etha = &priv->etha[index]; 1545 1546 memset(etha, 0, sizeof(*etha)); 1547 etha->index = index; 1548 etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE; 1549 etha->coma_addr = priv->addr; 1550 } 1551 1552 static int rswitch_device_alloc(struct rswitch_private *priv, int index) 1553 { 1554 struct platform_device *pdev = priv->pdev; 1555 struct rswitch_device *rdev; 1556 struct net_device *ndev; 1557 int err; 1558 1559 if (index >= RSWITCH_NUM_PORTS) 1560 return -EINVAL; 1561 1562 ndev = alloc_etherdev_mqs(sizeof(struct rswitch_device), 1, 1); 1563 if (!ndev) 1564 return -ENOMEM; 1565 1566 SET_NETDEV_DEV(ndev, &pdev->dev); 1567 ether_setup(ndev); 1568 1569 rdev = netdev_priv(ndev); 1570 rdev->ndev = ndev; 1571 rdev->priv = priv; 1572 priv->rdev[index] = rdev; 1573 rdev->port = index; 1574 rdev->etha = &priv->etha[index]; 1575 rdev->addr = priv->addr; 1576 1577 ndev->base_addr = (unsigned long)rdev->addr; 1578 snprintf(ndev->name, IFNAMSIZ, "tsn%d", index); 1579 ndev->netdev_ops = &rswitch_netdev_ops; 1580 ndev->ethtool_ops = &rswitch_ethtool_ops; 1581 1582 netif_napi_add(ndev, &rdev->napi, rswitch_poll); 1583 1584 rdev->np_port = rswitch_get_port_node(rdev); 1585 rdev->disabled = !rdev->np_port; 1586 err = of_get_ethdev_address(rdev->np_port, ndev); 1587 of_node_put(rdev->np_port); 1588 if (err) { 1589 if (is_valid_ether_addr(rdev->etha->mac_addr)) 1590 eth_hw_addr_set(ndev, rdev->etha->mac_addr); 1591 else 1592 eth_hw_addr_random(ndev); 1593 } 1594 1595 err = rswitch_etha_get_params(rdev); 1596 if (err < 0) 1597 goto out_get_params; 1598 1599 if (rdev->priv->gwca.speed < rdev->etha->speed) 1600 rdev->priv->gwca.speed = rdev->etha->speed; 1601 1602 err = rswitch_rxdmac_alloc(ndev); 1603 if (err < 0) 1604 goto out_rxdmac; 1605 1606 err = rswitch_txdmac_alloc(ndev); 1607 if (err < 0) 1608 goto out_txdmac; 1609 1610 return 0; 1611 1612 out_txdmac: 1613 rswitch_rxdmac_free(ndev); 1614 1615 out_rxdmac: 1616 out_get_params: 1617 netif_napi_del(&rdev->napi); 1618 free_netdev(ndev); 1619 1620 return err; 1621 } 1622 1623 static void rswitch_device_free(struct rswitch_private *priv, int index) 1624 { 1625 struct rswitch_device *rdev = priv->rdev[index]; 1626 struct net_device *ndev = rdev->ndev; 1627 1628 rswitch_txdmac_free(ndev); 1629 rswitch_rxdmac_free(ndev); 1630 netif_napi_del(&rdev->napi); 1631 free_netdev(ndev); 1632 } 1633 1634 static int rswitch_init(struct rswitch_private *priv) 1635 { 1636 int i, err; 1637 1638 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1639 rswitch_etha_init(priv, i); 1640 1641 rswitch_clock_enable(priv); 1642 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1643 rswitch_etha_read_mac_address(&priv->etha[i]); 1644 1645 rswitch_reset(priv); 1646 1647 rswitch_clock_enable(priv); 1648 rswitch_top_init(priv); 1649 err = rswitch_bpool_config(priv); 1650 if (err < 0) 1651 return err; 1652 1653 err = rswitch_gwca_desc_alloc(priv); 1654 if (err < 0) 1655 return -ENOMEM; 1656 1657 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1658 err = rswitch_device_alloc(priv, i); 1659 if (err < 0) { 1660 for (i--; i >= 0; i--) 1661 rswitch_device_free(priv, i); 1662 goto err_device_alloc; 1663 } 1664 } 1665 1666 rswitch_fwd_init(priv); 1667 1668 err = rcar_gen4_ptp_register(priv->ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT_S4, 1669 RCAR_GEN4_PTP_CLOCK_S4); 1670 if (err < 0) 1671 goto err_ptp_register; 1672 1673 err = rswitch_gwca_request_irqs(priv); 1674 if (err < 0) 1675 goto err_gwca_request_irq; 1676 1677 err = rswitch_gwca_hw_init(priv); 1678 if (err < 0) 1679 goto err_gwca_hw_init; 1680 1681 err = rswitch_ether_port_init_all(priv); 1682 if (err) 1683 goto err_ether_port_init_all; 1684 1685 rswitch_for_each_enabled_port(priv, i) { 1686 err = register_netdev(priv->rdev[i]->ndev); 1687 if (err) { 1688 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1689 unregister_netdev(priv->rdev[i]->ndev); 1690 goto err_register_netdev; 1691 } 1692 } 1693 1694 rswitch_for_each_enabled_port(priv, i) 1695 netdev_info(priv->rdev[i]->ndev, "MAC address %pM\n", 1696 priv->rdev[i]->ndev->dev_addr); 1697 1698 return 0; 1699 1700 err_register_netdev: 1701 rswitch_ether_port_deinit_all(priv); 1702 1703 err_ether_port_init_all: 1704 rswitch_gwca_hw_deinit(priv); 1705 1706 err_gwca_hw_init: 1707 err_gwca_request_irq: 1708 rcar_gen4_ptp_unregister(priv->ptp_priv); 1709 1710 err_ptp_register: 1711 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1712 rswitch_device_free(priv, i); 1713 1714 err_device_alloc: 1715 rswitch_gwca_desc_free(priv); 1716 1717 return err; 1718 } 1719 1720 static int renesas_eth_sw_probe(struct platform_device *pdev) 1721 { 1722 struct rswitch_private *priv; 1723 struct resource *res; 1724 int ret; 1725 1726 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "secure_base"); 1727 if (!res) { 1728 dev_err(&pdev->dev, "invalid resource\n"); 1729 return -EINVAL; 1730 } 1731 1732 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1733 if (!priv) 1734 return -ENOMEM; 1735 1736 priv->ptp_priv = rcar_gen4_ptp_alloc(pdev); 1737 if (!priv->ptp_priv) 1738 return -ENOMEM; 1739 1740 platform_set_drvdata(pdev, priv); 1741 priv->pdev = pdev; 1742 priv->addr = devm_ioremap_resource(&pdev->dev, res); 1743 if (IS_ERR(priv->addr)) 1744 return PTR_ERR(priv->addr); 1745 1746 priv->ptp_priv->addr = priv->addr + RCAR_GEN4_GPTP_OFFSET_S4; 1747 1748 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 1749 if (ret < 0) { 1750 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1751 if (ret < 0) 1752 return ret; 1753 } 1754 1755 priv->gwca.index = AGENT_INDEX_GWCA; 1756 priv->gwca.num_queues = min(RSWITCH_NUM_PORTS * NUM_QUEUES_PER_NDEV, 1757 RSWITCH_MAX_NUM_QUEUES); 1758 priv->gwca.queues = devm_kcalloc(&pdev->dev, priv->gwca.num_queues, 1759 sizeof(*priv->gwca.queues), GFP_KERNEL); 1760 if (!priv->gwca.queues) 1761 return -ENOMEM; 1762 1763 pm_runtime_enable(&pdev->dev); 1764 pm_runtime_get_sync(&pdev->dev); 1765 1766 ret = rswitch_init(priv); 1767 if (ret < 0) { 1768 pm_runtime_put(&pdev->dev); 1769 pm_runtime_disable(&pdev->dev); 1770 return ret; 1771 } 1772 1773 device_set_wakeup_capable(&pdev->dev, 1); 1774 1775 return ret; 1776 } 1777 1778 static void rswitch_deinit(struct rswitch_private *priv) 1779 { 1780 int i; 1781 1782 rswitch_gwca_hw_deinit(priv); 1783 rcar_gen4_ptp_unregister(priv->ptp_priv); 1784 1785 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1786 struct rswitch_device *rdev = priv->rdev[i]; 1787 1788 phy_exit(priv->rdev[i]->serdes); 1789 rswitch_ether_port_deinit_one(rdev); 1790 unregister_netdev(rdev->ndev); 1791 rswitch_device_free(priv, i); 1792 } 1793 1794 rswitch_gwca_desc_free(priv); 1795 1796 rswitch_clock_disable(priv); 1797 } 1798 1799 static int renesas_eth_sw_remove(struct platform_device *pdev) 1800 { 1801 struct rswitch_private *priv = platform_get_drvdata(pdev); 1802 1803 rswitch_deinit(priv); 1804 1805 pm_runtime_put(&pdev->dev); 1806 pm_runtime_disable(&pdev->dev); 1807 1808 platform_set_drvdata(pdev, NULL); 1809 1810 return 0; 1811 } 1812 1813 static struct platform_driver renesas_eth_sw_driver_platform = { 1814 .probe = renesas_eth_sw_probe, 1815 .remove = renesas_eth_sw_remove, 1816 .driver = { 1817 .name = "renesas_eth_sw", 1818 .of_match_table = renesas_eth_sw_of_table, 1819 } 1820 }; 1821 module_platform_driver(renesas_eth_sw_driver_platform); 1822 MODULE_AUTHOR("Yoshihiro Shimoda"); 1823 MODULE_DESCRIPTION("Renesas Ethernet Switch device driver"); 1824 MODULE_LICENSE("GPL"); 1825