1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet Switch device driver 3 * 4 * Copyright (C) 2022 Renesas Electronics Corporation 5 */ 6 7 #include <linux/dma-mapping.h> 8 #include <linux/err.h> 9 #include <linux/etherdevice.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/of.h> 15 #include <linux/of_mdio.h> 16 #include <linux/of_net.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/rtnetlink.h> 21 #include <linux/slab.h> 22 #include <linux/spinlock.h> 23 #include <linux/sys_soc.h> 24 25 #include "rswitch.h" 26 27 static int rswitch_reg_wait(void __iomem *addr, u32 offs, u32 mask, u32 expected) 28 { 29 u32 val; 30 31 return readl_poll_timeout_atomic(addr + offs, val, (val & mask) == expected, 32 1, RSWITCH_TIMEOUT_US); 33 } 34 35 static void rswitch_modify(void __iomem *addr, enum rswitch_reg reg, u32 clear, u32 set) 36 { 37 iowrite32((ioread32(addr + reg) & ~clear) | set, addr + reg); 38 } 39 40 /* Common Agent block (COMA) */ 41 static void rswitch_reset(struct rswitch_private *priv) 42 { 43 iowrite32(RRC_RR, priv->addr + RRC); 44 iowrite32(RRC_RR_CLR, priv->addr + RRC); 45 } 46 47 static void rswitch_clock_enable(struct rswitch_private *priv) 48 { 49 iowrite32(RCEC_ACE_DEFAULT | RCEC_RCE, priv->addr + RCEC); 50 } 51 52 static void rswitch_clock_disable(struct rswitch_private *priv) 53 { 54 iowrite32(RCDC_RCD, priv->addr + RCDC); 55 } 56 57 static bool rswitch_agent_clock_is_enabled(void __iomem *coma_addr, int port) 58 { 59 u32 val = ioread32(coma_addr + RCEC); 60 61 if (val & RCEC_RCE) 62 return (val & BIT(port)) ? true : false; 63 else 64 return false; 65 } 66 67 static void rswitch_agent_clock_ctrl(void __iomem *coma_addr, int port, int enable) 68 { 69 u32 val; 70 71 if (enable) { 72 val = ioread32(coma_addr + RCEC); 73 iowrite32(val | RCEC_RCE | BIT(port), coma_addr + RCEC); 74 } else { 75 val = ioread32(coma_addr + RCDC); 76 iowrite32(val | BIT(port), coma_addr + RCDC); 77 } 78 } 79 80 static int rswitch_bpool_config(struct rswitch_private *priv) 81 { 82 u32 val; 83 84 val = ioread32(priv->addr + CABPIRM); 85 if (val & CABPIRM_BPR) 86 return 0; 87 88 iowrite32(CABPIRM_BPIOG, priv->addr + CABPIRM); 89 90 return rswitch_reg_wait(priv->addr, CABPIRM, CABPIRM_BPR, CABPIRM_BPR); 91 } 92 93 static void rswitch_coma_init(struct rswitch_private *priv) 94 { 95 iowrite32(CABPPFLC_INIT_VALUE, priv->addr + CABPPFLC0); 96 } 97 98 /* R-Switch-2 block (TOP) */ 99 static void rswitch_top_init(struct rswitch_private *priv) 100 { 101 int i; 102 103 for (i = 0; i < RSWITCH_MAX_NUM_QUEUES; i++) 104 iowrite32((i / 16) << (GWCA_INDEX * 8), priv->addr + TPEMIMC7(i)); 105 } 106 107 /* Forwarding engine block (MFWD) */ 108 static void rswitch_fwd_init(struct rswitch_private *priv) 109 { 110 int i; 111 112 /* For ETHA */ 113 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 114 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i)); 115 iowrite32(0, priv->addr + FWPBFC(i)); 116 } 117 118 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 119 iowrite32(priv->rdev[i]->rx_queue->index, 120 priv->addr + FWPBFCSDC(GWCA_INDEX, i)); 121 iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i)); 122 } 123 124 /* For GWCA */ 125 iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index)); 126 iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index)); 127 iowrite32(0, priv->addr + FWPBFC(priv->gwca.index)); 128 iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index)); 129 } 130 131 /* Gateway CPU agent block (GWCA) */ 132 static int rswitch_gwca_change_mode(struct rswitch_private *priv, 133 enum rswitch_gwca_mode mode) 134 { 135 int ret; 136 137 if (!rswitch_agent_clock_is_enabled(priv->addr, priv->gwca.index)) 138 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 1); 139 140 iowrite32(mode, priv->addr + GWMC); 141 142 ret = rswitch_reg_wait(priv->addr, GWMS, GWMS_OPS_MASK, mode); 143 144 if (mode == GWMC_OPC_DISABLE) 145 rswitch_agent_clock_ctrl(priv->addr, priv->gwca.index, 0); 146 147 return ret; 148 } 149 150 static int rswitch_gwca_mcast_table_reset(struct rswitch_private *priv) 151 { 152 iowrite32(GWMTIRM_MTIOG, priv->addr + GWMTIRM); 153 154 return rswitch_reg_wait(priv->addr, GWMTIRM, GWMTIRM_MTR, GWMTIRM_MTR); 155 } 156 157 static int rswitch_gwca_axi_ram_reset(struct rswitch_private *priv) 158 { 159 iowrite32(GWARIRM_ARIOG, priv->addr + GWARIRM); 160 161 return rswitch_reg_wait(priv->addr, GWARIRM, GWARIRM_ARR, GWARIRM_ARR); 162 } 163 164 static bool rswitch_is_any_data_irq(struct rswitch_private *priv, u32 *dis, bool tx) 165 { 166 u32 *mask = tx ? priv->gwca.tx_irq_bits : priv->gwca.rx_irq_bits; 167 int i; 168 169 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 170 if (dis[i] & mask[i]) 171 return true; 172 } 173 174 return false; 175 } 176 177 static void rswitch_get_data_irq_status(struct rswitch_private *priv, u32 *dis) 178 { 179 int i; 180 181 for (i = 0; i < RSWITCH_NUM_IRQ_REGS; i++) { 182 dis[i] = ioread32(priv->addr + GWDIS(i)); 183 dis[i] &= ioread32(priv->addr + GWDIE(i)); 184 } 185 } 186 187 static void rswitch_enadis_data_irq(struct rswitch_private *priv, int index, bool enable) 188 { 189 u32 offs = enable ? GWDIE(index / 32) : GWDID(index / 32); 190 191 iowrite32(BIT(index % 32), priv->addr + offs); 192 } 193 194 static void rswitch_ack_data_irq(struct rswitch_private *priv, int index) 195 { 196 u32 offs = GWDIS(index / 32); 197 198 iowrite32(BIT(index % 32), priv->addr + offs); 199 } 200 201 static int rswitch_next_queue_index(struct rswitch_gwca_queue *gq, bool cur, int num) 202 { 203 int index = cur ? gq->cur : gq->dirty; 204 205 if (index + num >= gq->ring_size) 206 index = (index + num) % gq->ring_size; 207 else 208 index += num; 209 210 return index; 211 } 212 213 static int rswitch_get_num_cur_queues(struct rswitch_gwca_queue *gq) 214 { 215 if (gq->cur >= gq->dirty) 216 return gq->cur - gq->dirty; 217 else 218 return gq->ring_size - gq->dirty + gq->cur; 219 } 220 221 static bool rswitch_is_queue_rxed(struct rswitch_gwca_queue *gq) 222 { 223 struct rswitch_ext_ts_desc *desc = &gq->rx_ring[gq->dirty]; 224 225 if ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) 226 return true; 227 228 return false; 229 } 230 231 static int rswitch_gwca_queue_alloc_skb(struct rswitch_gwca_queue *gq, 232 int start_index, int num) 233 { 234 int i, index; 235 236 for (i = 0; i < num; i++) { 237 index = (i + start_index) % gq->ring_size; 238 if (gq->skbs[index]) 239 continue; 240 gq->skbs[index] = netdev_alloc_skb_ip_align(gq->ndev, 241 PKT_BUF_SZ + RSWITCH_ALIGN - 1); 242 if (!gq->skbs[index]) 243 goto err; 244 } 245 246 return 0; 247 248 err: 249 for (i--; i >= 0; i--) { 250 index = (i + start_index) % gq->ring_size; 251 dev_kfree_skb(gq->skbs[index]); 252 gq->skbs[index] = NULL; 253 } 254 255 return -ENOMEM; 256 } 257 258 static void rswitch_gwca_queue_free(struct net_device *ndev, 259 struct rswitch_gwca_queue *gq) 260 { 261 int i; 262 263 if (!gq->dir_tx) { 264 dma_free_coherent(ndev->dev.parent, 265 sizeof(struct rswitch_ext_ts_desc) * 266 (gq->ring_size + 1), gq->rx_ring, gq->ring_dma); 267 gq->rx_ring = NULL; 268 269 for (i = 0; i < gq->ring_size; i++) 270 dev_kfree_skb(gq->skbs[i]); 271 } else { 272 dma_free_coherent(ndev->dev.parent, 273 sizeof(struct rswitch_ext_desc) * 274 (gq->ring_size + 1), gq->tx_ring, gq->ring_dma); 275 gq->tx_ring = NULL; 276 } 277 278 kfree(gq->skbs); 279 gq->skbs = NULL; 280 } 281 282 static void rswitch_gwca_ts_queue_free(struct rswitch_private *priv) 283 { 284 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 285 286 dma_free_coherent(&priv->pdev->dev, 287 sizeof(struct rswitch_ts_desc) * (gq->ring_size + 1), 288 gq->ts_ring, gq->ring_dma); 289 gq->ts_ring = NULL; 290 } 291 292 static int rswitch_gwca_queue_alloc(struct net_device *ndev, 293 struct rswitch_private *priv, 294 struct rswitch_gwca_queue *gq, 295 bool dir_tx, int ring_size) 296 { 297 int i, bit; 298 299 gq->dir_tx = dir_tx; 300 gq->ring_size = ring_size; 301 gq->ndev = ndev; 302 303 gq->skbs = kcalloc(gq->ring_size, sizeof(*gq->skbs), GFP_KERNEL); 304 if (!gq->skbs) 305 return -ENOMEM; 306 307 if (!dir_tx) { 308 rswitch_gwca_queue_alloc_skb(gq, 0, gq->ring_size); 309 310 gq->rx_ring = dma_alloc_coherent(ndev->dev.parent, 311 sizeof(struct rswitch_ext_ts_desc) * 312 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 313 } else { 314 gq->tx_ring = dma_alloc_coherent(ndev->dev.parent, 315 sizeof(struct rswitch_ext_desc) * 316 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 317 } 318 319 if (!gq->rx_ring && !gq->tx_ring) 320 goto out; 321 322 i = gq->index / 32; 323 bit = BIT(gq->index % 32); 324 if (dir_tx) 325 priv->gwca.tx_irq_bits[i] |= bit; 326 else 327 priv->gwca.rx_irq_bits[i] |= bit; 328 329 return 0; 330 331 out: 332 rswitch_gwca_queue_free(ndev, gq); 333 334 return -ENOMEM; 335 } 336 337 static void rswitch_desc_set_dptr(struct rswitch_desc *desc, dma_addr_t addr) 338 { 339 desc->dptrl = cpu_to_le32(lower_32_bits(addr)); 340 desc->dptrh = upper_32_bits(addr) & 0xff; 341 } 342 343 static dma_addr_t rswitch_desc_get_dptr(const struct rswitch_desc *desc) 344 { 345 return __le32_to_cpu(desc->dptrl) | (u64)(desc->dptrh) << 32; 346 } 347 348 static int rswitch_gwca_queue_format(struct net_device *ndev, 349 struct rswitch_private *priv, 350 struct rswitch_gwca_queue *gq) 351 { 352 int ring_size = sizeof(struct rswitch_ext_desc) * gq->ring_size; 353 struct rswitch_ext_desc *desc; 354 struct rswitch_desc *linkfix; 355 dma_addr_t dma_addr; 356 int i; 357 358 memset(gq->tx_ring, 0, ring_size); 359 for (i = 0, desc = gq->tx_ring; i < gq->ring_size; i++, desc++) { 360 if (!gq->dir_tx) { 361 dma_addr = dma_map_single(ndev->dev.parent, 362 gq->skbs[i]->data, PKT_BUF_SZ, 363 DMA_FROM_DEVICE); 364 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 365 goto err; 366 367 desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ); 368 rswitch_desc_set_dptr(&desc->desc, dma_addr); 369 desc->desc.die_dt = DT_FEMPTY | DIE; 370 } else { 371 desc->desc.die_dt = DT_EEMPTY | DIE; 372 } 373 } 374 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 375 desc->desc.die_dt = DT_LINKFIX; 376 377 linkfix = &priv->gwca.linkfix_table[gq->index]; 378 linkfix->die_dt = DT_LINKFIX; 379 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 380 381 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DCP(GWCA_IPV_NUM) | GWDCC_DQT : 0) | GWDCC_EDE, 382 priv->addr + GWDCC_OFFS(gq->index)); 383 384 return 0; 385 386 err: 387 if (!gq->dir_tx) { 388 for (i--, desc = gq->tx_ring; i >= 0; i--, desc++) { 389 dma_addr = rswitch_desc_get_dptr(&desc->desc); 390 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, 391 DMA_FROM_DEVICE); 392 } 393 } 394 395 return -ENOMEM; 396 } 397 398 static void rswitch_gwca_ts_queue_fill(struct rswitch_private *priv, 399 int start_index, int num) 400 { 401 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 402 struct rswitch_ts_desc *desc; 403 int i, index; 404 405 for (i = 0; i < num; i++) { 406 index = (i + start_index) % gq->ring_size; 407 desc = &gq->ts_ring[index]; 408 desc->desc.die_dt = DT_FEMPTY_ND | DIE; 409 } 410 } 411 412 static int rswitch_gwca_queue_ext_ts_fill(struct net_device *ndev, 413 struct rswitch_gwca_queue *gq, 414 int start_index, int num) 415 { 416 struct rswitch_device *rdev = netdev_priv(ndev); 417 struct rswitch_ext_ts_desc *desc; 418 dma_addr_t dma_addr; 419 int i, index; 420 421 for (i = 0; i < num; i++) { 422 index = (i + start_index) % gq->ring_size; 423 desc = &gq->rx_ring[index]; 424 if (!gq->dir_tx) { 425 dma_addr = dma_map_single(ndev->dev.parent, 426 gq->skbs[index]->data, PKT_BUF_SZ, 427 DMA_FROM_DEVICE); 428 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 429 goto err; 430 431 desc->desc.info_ds = cpu_to_le16(PKT_BUF_SZ); 432 rswitch_desc_set_dptr(&desc->desc, dma_addr); 433 dma_wmb(); 434 desc->desc.die_dt = DT_FEMPTY | DIE; 435 desc->info1 = cpu_to_le64(INFO1_SPN(rdev->etha->index)); 436 } else { 437 desc->desc.die_dt = DT_EEMPTY | DIE; 438 } 439 } 440 441 return 0; 442 443 err: 444 if (!gq->dir_tx) { 445 for (i--; i >= 0; i--) { 446 index = (i + start_index) % gq->ring_size; 447 desc = &gq->rx_ring[index]; 448 dma_addr = rswitch_desc_get_dptr(&desc->desc); 449 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, 450 DMA_FROM_DEVICE); 451 } 452 } 453 454 return -ENOMEM; 455 } 456 457 static int rswitch_gwca_queue_ext_ts_format(struct net_device *ndev, 458 struct rswitch_private *priv, 459 struct rswitch_gwca_queue *gq) 460 { 461 int ring_size = sizeof(struct rswitch_ext_ts_desc) * gq->ring_size; 462 struct rswitch_ext_ts_desc *desc; 463 struct rswitch_desc *linkfix; 464 int err; 465 466 memset(gq->rx_ring, 0, ring_size); 467 err = rswitch_gwca_queue_ext_ts_fill(ndev, gq, 0, gq->ring_size); 468 if (err < 0) 469 return err; 470 471 desc = &gq->rx_ring[gq->ring_size]; /* Last */ 472 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 473 desc->desc.die_dt = DT_LINKFIX; 474 475 linkfix = &priv->gwca.linkfix_table[gq->index]; 476 linkfix->die_dt = DT_LINKFIX; 477 rswitch_desc_set_dptr(linkfix, gq->ring_dma); 478 479 iowrite32(GWDCC_BALR | (gq->dir_tx ? GWDCC_DCP(GWCA_IPV_NUM) | GWDCC_DQT : 0) | 480 GWDCC_ETS | GWDCC_EDE, 481 priv->addr + GWDCC_OFFS(gq->index)); 482 483 return 0; 484 } 485 486 static int rswitch_gwca_linkfix_alloc(struct rswitch_private *priv) 487 { 488 int i, num_queues = priv->gwca.num_queues; 489 struct rswitch_gwca *gwca = &priv->gwca; 490 struct device *dev = &priv->pdev->dev; 491 492 gwca->linkfix_table_size = sizeof(struct rswitch_desc) * num_queues; 493 gwca->linkfix_table = dma_alloc_coherent(dev, gwca->linkfix_table_size, 494 &gwca->linkfix_table_dma, GFP_KERNEL); 495 if (!gwca->linkfix_table) 496 return -ENOMEM; 497 for (i = 0; i < num_queues; i++) 498 gwca->linkfix_table[i].die_dt = DT_EOS; 499 500 return 0; 501 } 502 503 static void rswitch_gwca_linkfix_free(struct rswitch_private *priv) 504 { 505 struct rswitch_gwca *gwca = &priv->gwca; 506 507 if (gwca->linkfix_table) 508 dma_free_coherent(&priv->pdev->dev, gwca->linkfix_table_size, 509 gwca->linkfix_table, gwca->linkfix_table_dma); 510 gwca->linkfix_table = NULL; 511 } 512 513 static int rswitch_gwca_ts_queue_alloc(struct rswitch_private *priv) 514 { 515 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 516 struct rswitch_ts_desc *desc; 517 518 gq->ring_size = TS_RING_SIZE; 519 gq->ts_ring = dma_alloc_coherent(&priv->pdev->dev, 520 sizeof(struct rswitch_ts_desc) * 521 (gq->ring_size + 1), &gq->ring_dma, GFP_KERNEL); 522 523 if (!gq->ts_ring) 524 return -ENOMEM; 525 526 rswitch_gwca_ts_queue_fill(priv, 0, TS_RING_SIZE); 527 desc = &gq->ts_ring[gq->ring_size]; 528 desc->desc.die_dt = DT_LINKFIX; 529 rswitch_desc_set_dptr(&desc->desc, gq->ring_dma); 530 INIT_LIST_HEAD(&priv->gwca.ts_info_list); 531 532 return 0; 533 } 534 535 static struct rswitch_gwca_queue *rswitch_gwca_get(struct rswitch_private *priv) 536 { 537 struct rswitch_gwca_queue *gq; 538 int index; 539 540 index = find_first_zero_bit(priv->gwca.used, priv->gwca.num_queues); 541 if (index >= priv->gwca.num_queues) 542 return NULL; 543 set_bit(index, priv->gwca.used); 544 gq = &priv->gwca.queues[index]; 545 memset(gq, 0, sizeof(*gq)); 546 gq->index = index; 547 548 return gq; 549 } 550 551 static void rswitch_gwca_put(struct rswitch_private *priv, 552 struct rswitch_gwca_queue *gq) 553 { 554 clear_bit(gq->index, priv->gwca.used); 555 } 556 557 static int rswitch_txdmac_alloc(struct net_device *ndev) 558 { 559 struct rswitch_device *rdev = netdev_priv(ndev); 560 struct rswitch_private *priv = rdev->priv; 561 int err; 562 563 rdev->tx_queue = rswitch_gwca_get(priv); 564 if (!rdev->tx_queue) 565 return -EBUSY; 566 567 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->tx_queue, true, TX_RING_SIZE); 568 if (err < 0) { 569 rswitch_gwca_put(priv, rdev->tx_queue); 570 return err; 571 } 572 573 return 0; 574 } 575 576 static void rswitch_txdmac_free(struct net_device *ndev) 577 { 578 struct rswitch_device *rdev = netdev_priv(ndev); 579 580 rswitch_gwca_queue_free(ndev, rdev->tx_queue); 581 rswitch_gwca_put(rdev->priv, rdev->tx_queue); 582 } 583 584 static int rswitch_txdmac_init(struct rswitch_private *priv, int index) 585 { 586 struct rswitch_device *rdev = priv->rdev[index]; 587 588 return rswitch_gwca_queue_format(rdev->ndev, priv, rdev->tx_queue); 589 } 590 591 static int rswitch_rxdmac_alloc(struct net_device *ndev) 592 { 593 struct rswitch_device *rdev = netdev_priv(ndev); 594 struct rswitch_private *priv = rdev->priv; 595 int err; 596 597 rdev->rx_queue = rswitch_gwca_get(priv); 598 if (!rdev->rx_queue) 599 return -EBUSY; 600 601 err = rswitch_gwca_queue_alloc(ndev, priv, rdev->rx_queue, false, RX_RING_SIZE); 602 if (err < 0) { 603 rswitch_gwca_put(priv, rdev->rx_queue); 604 return err; 605 } 606 607 return 0; 608 } 609 610 static void rswitch_rxdmac_free(struct net_device *ndev) 611 { 612 struct rswitch_device *rdev = netdev_priv(ndev); 613 614 rswitch_gwca_queue_free(ndev, rdev->rx_queue); 615 rswitch_gwca_put(rdev->priv, rdev->rx_queue); 616 } 617 618 static int rswitch_rxdmac_init(struct rswitch_private *priv, int index) 619 { 620 struct rswitch_device *rdev = priv->rdev[index]; 621 struct net_device *ndev = rdev->ndev; 622 623 return rswitch_gwca_queue_ext_ts_format(ndev, priv, rdev->rx_queue); 624 } 625 626 static int rswitch_gwca_hw_init(struct rswitch_private *priv) 627 { 628 int i, err; 629 630 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 631 if (err < 0) 632 return err; 633 err = rswitch_gwca_change_mode(priv, GWMC_OPC_CONFIG); 634 if (err < 0) 635 return err; 636 637 err = rswitch_gwca_mcast_table_reset(priv); 638 if (err < 0) 639 return err; 640 err = rswitch_gwca_axi_ram_reset(priv); 641 if (err < 0) 642 return err; 643 644 iowrite32(GWVCC_VEM_SC_TAG, priv->addr + GWVCC); 645 iowrite32(0, priv->addr + GWTTFC); 646 iowrite32(lower_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC1); 647 iowrite32(upper_32_bits(priv->gwca.linkfix_table_dma), priv->addr + GWDCBAC0); 648 iowrite32(lower_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC10); 649 iowrite32(upper_32_bits(priv->gwca.ts_queue.ring_dma), priv->addr + GWTDCAC00); 650 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDCC0); 651 652 iowrite32(GWTPC_PPPL(GWCA_IPV_NUM), priv->addr + GWTPC0); 653 654 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 655 err = rswitch_rxdmac_init(priv, i); 656 if (err < 0) 657 return err; 658 err = rswitch_txdmac_init(priv, i); 659 if (err < 0) 660 return err; 661 } 662 663 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 664 if (err < 0) 665 return err; 666 return rswitch_gwca_change_mode(priv, GWMC_OPC_OPERATION); 667 } 668 669 static int rswitch_gwca_hw_deinit(struct rswitch_private *priv) 670 { 671 int err; 672 673 err = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 674 if (err < 0) 675 return err; 676 err = rswitch_gwca_change_mode(priv, GWMC_OPC_RESET); 677 if (err < 0) 678 return err; 679 680 return rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE); 681 } 682 683 static int rswitch_gwca_halt(struct rswitch_private *priv) 684 { 685 int err; 686 687 priv->gwca_halt = true; 688 err = rswitch_gwca_hw_deinit(priv); 689 dev_err(&priv->pdev->dev, "halted (%d)\n", err); 690 691 return err; 692 } 693 694 static bool rswitch_rx(struct net_device *ndev, int *quota) 695 { 696 struct rswitch_device *rdev = netdev_priv(ndev); 697 struct rswitch_gwca_queue *gq = rdev->rx_queue; 698 struct rswitch_ext_ts_desc *desc; 699 int limit, boguscnt, num, ret; 700 struct sk_buff *skb; 701 dma_addr_t dma_addr; 702 u16 pkt_len; 703 u32 get_ts; 704 705 if (*quota <= 0) 706 return true; 707 708 boguscnt = min_t(int, gq->ring_size, *quota); 709 limit = boguscnt; 710 711 desc = &gq->rx_ring[gq->cur]; 712 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY) { 713 dma_rmb(); 714 pkt_len = le16_to_cpu(desc->desc.info_ds) & RX_DS; 715 skb = gq->skbs[gq->cur]; 716 gq->skbs[gq->cur] = NULL; 717 dma_addr = rswitch_desc_get_dptr(&desc->desc); 718 dma_unmap_single(ndev->dev.parent, dma_addr, PKT_BUF_SZ, DMA_FROM_DEVICE); 719 get_ts = rdev->priv->ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 720 if (get_ts) { 721 struct skb_shared_hwtstamps *shhwtstamps; 722 struct timespec64 ts; 723 724 shhwtstamps = skb_hwtstamps(skb); 725 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 726 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 727 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 728 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 729 } 730 skb_put(skb, pkt_len); 731 skb->protocol = eth_type_trans(skb, ndev); 732 napi_gro_receive(&rdev->napi, skb); 733 rdev->ndev->stats.rx_packets++; 734 rdev->ndev->stats.rx_bytes += pkt_len; 735 736 gq->cur = rswitch_next_queue_index(gq, true, 1); 737 desc = &gq->rx_ring[gq->cur]; 738 739 if (--boguscnt <= 0) 740 break; 741 } 742 743 num = rswitch_get_num_cur_queues(gq); 744 ret = rswitch_gwca_queue_alloc_skb(gq, gq->dirty, num); 745 if (ret < 0) 746 goto err; 747 ret = rswitch_gwca_queue_ext_ts_fill(ndev, gq, gq->dirty, num); 748 if (ret < 0) 749 goto err; 750 gq->dirty = rswitch_next_queue_index(gq, false, num); 751 752 *quota -= limit - boguscnt; 753 754 return boguscnt <= 0; 755 756 err: 757 rswitch_gwca_halt(rdev->priv); 758 759 return 0; 760 } 761 762 static int rswitch_tx_free(struct net_device *ndev, bool free_txed_only) 763 { 764 struct rswitch_device *rdev = netdev_priv(ndev); 765 struct rswitch_gwca_queue *gq = rdev->tx_queue; 766 struct rswitch_ext_desc *desc; 767 dma_addr_t dma_addr; 768 struct sk_buff *skb; 769 int free_num = 0; 770 int size; 771 772 for (; rswitch_get_num_cur_queues(gq) > 0; 773 gq->dirty = rswitch_next_queue_index(gq, false, 1)) { 774 desc = &gq->tx_ring[gq->dirty]; 775 if (free_txed_only && (desc->desc.die_dt & DT_MASK) != DT_FEMPTY) 776 break; 777 778 dma_rmb(); 779 size = le16_to_cpu(desc->desc.info_ds) & TX_DS; 780 skb = gq->skbs[gq->dirty]; 781 if (skb) { 782 dma_addr = rswitch_desc_get_dptr(&desc->desc); 783 dma_unmap_single(ndev->dev.parent, dma_addr, 784 size, DMA_TO_DEVICE); 785 dev_kfree_skb_any(gq->skbs[gq->dirty]); 786 gq->skbs[gq->dirty] = NULL; 787 free_num++; 788 } 789 desc->desc.die_dt = DT_EEMPTY; 790 rdev->ndev->stats.tx_packets++; 791 rdev->ndev->stats.tx_bytes += size; 792 } 793 794 return free_num; 795 } 796 797 static int rswitch_poll(struct napi_struct *napi, int budget) 798 { 799 struct net_device *ndev = napi->dev; 800 struct rswitch_private *priv; 801 struct rswitch_device *rdev; 802 int quota = budget; 803 804 rdev = netdev_priv(ndev); 805 priv = rdev->priv; 806 807 retry: 808 rswitch_tx_free(ndev, true); 809 810 if (rswitch_rx(ndev, "a)) 811 goto out; 812 else if (rdev->priv->gwca_halt) 813 goto err; 814 else if (rswitch_is_queue_rxed(rdev->rx_queue)) 815 goto retry; 816 817 netif_wake_subqueue(ndev, 0); 818 819 napi_complete(napi); 820 821 rswitch_enadis_data_irq(priv, rdev->tx_queue->index, true); 822 rswitch_enadis_data_irq(priv, rdev->rx_queue->index, true); 823 824 out: 825 return budget - quota; 826 827 err: 828 napi_complete(napi); 829 830 return 0; 831 } 832 833 static void rswitch_queue_interrupt(struct net_device *ndev) 834 { 835 struct rswitch_device *rdev = netdev_priv(ndev); 836 837 if (napi_schedule_prep(&rdev->napi)) { 838 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 839 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 840 __napi_schedule(&rdev->napi); 841 } 842 } 843 844 static irqreturn_t rswitch_data_irq(struct rswitch_private *priv, u32 *dis) 845 { 846 struct rswitch_gwca_queue *gq; 847 int i, index, bit; 848 849 for (i = 0; i < priv->gwca.num_queues; i++) { 850 gq = &priv->gwca.queues[i]; 851 index = gq->index / 32; 852 bit = BIT(gq->index % 32); 853 if (!(dis[index] & bit)) 854 continue; 855 856 rswitch_ack_data_irq(priv, gq->index); 857 rswitch_queue_interrupt(gq->ndev); 858 } 859 860 return IRQ_HANDLED; 861 } 862 863 static irqreturn_t rswitch_gwca_irq(int irq, void *dev_id) 864 { 865 struct rswitch_private *priv = dev_id; 866 u32 dis[RSWITCH_NUM_IRQ_REGS]; 867 irqreturn_t ret = IRQ_NONE; 868 869 rswitch_get_data_irq_status(priv, dis); 870 871 if (rswitch_is_any_data_irq(priv, dis, true) || 872 rswitch_is_any_data_irq(priv, dis, false)) 873 ret = rswitch_data_irq(priv, dis); 874 875 return ret; 876 } 877 878 static int rswitch_gwca_request_irqs(struct rswitch_private *priv) 879 { 880 char *resource_name, *irq_name; 881 int i, ret, irq; 882 883 for (i = 0; i < GWCA_NUM_IRQS; i++) { 884 resource_name = kasprintf(GFP_KERNEL, GWCA_IRQ_RESOURCE_NAME, i); 885 if (!resource_name) 886 return -ENOMEM; 887 888 irq = platform_get_irq_byname(priv->pdev, resource_name); 889 kfree(resource_name); 890 if (irq < 0) 891 return irq; 892 893 irq_name = devm_kasprintf(&priv->pdev->dev, GFP_KERNEL, 894 GWCA_IRQ_NAME, i); 895 if (!irq_name) 896 return -ENOMEM; 897 898 ret = devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_irq, 899 0, irq_name, priv); 900 if (ret < 0) 901 return ret; 902 } 903 904 return 0; 905 } 906 907 static void rswitch_ts(struct rswitch_private *priv) 908 { 909 struct rswitch_gwca_queue *gq = &priv->gwca.ts_queue; 910 struct rswitch_gwca_ts_info *ts_info, *ts_info2; 911 struct skb_shared_hwtstamps shhwtstamps; 912 struct rswitch_ts_desc *desc; 913 struct timespec64 ts; 914 u32 tag, port; 915 int num; 916 917 desc = &gq->ts_ring[gq->cur]; 918 while ((desc->desc.die_dt & DT_MASK) != DT_FEMPTY_ND) { 919 dma_rmb(); 920 921 port = TS_DESC_DPN(__le32_to_cpu(desc->desc.dptrl)); 922 tag = TS_DESC_TSUN(__le32_to_cpu(desc->desc.dptrl)); 923 924 list_for_each_entry_safe(ts_info, ts_info2, &priv->gwca.ts_info_list, list) { 925 if (!(ts_info->port == port && ts_info->tag == tag)) 926 continue; 927 928 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 929 ts.tv_sec = __le32_to_cpu(desc->ts_sec); 930 ts.tv_nsec = __le32_to_cpu(desc->ts_nsec & cpu_to_le32(0x3fffffff)); 931 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 932 skb_tstamp_tx(ts_info->skb, &shhwtstamps); 933 dev_consume_skb_irq(ts_info->skb); 934 list_del(&ts_info->list); 935 kfree(ts_info); 936 break; 937 } 938 939 gq->cur = rswitch_next_queue_index(gq, true, 1); 940 desc = &gq->ts_ring[gq->cur]; 941 } 942 943 num = rswitch_get_num_cur_queues(gq); 944 rswitch_gwca_ts_queue_fill(priv, gq->dirty, num); 945 gq->dirty = rswitch_next_queue_index(gq, false, num); 946 } 947 948 static irqreturn_t rswitch_gwca_ts_irq(int irq, void *dev_id) 949 { 950 struct rswitch_private *priv = dev_id; 951 952 if (ioread32(priv->addr + GWTSDIS) & GWCA_TS_IRQ_BIT) { 953 iowrite32(GWCA_TS_IRQ_BIT, priv->addr + GWTSDIS); 954 rswitch_ts(priv); 955 956 return IRQ_HANDLED; 957 } 958 959 return IRQ_NONE; 960 } 961 962 static int rswitch_gwca_ts_request_irqs(struct rswitch_private *priv) 963 { 964 int irq; 965 966 irq = platform_get_irq_byname(priv->pdev, GWCA_TS_IRQ_RESOURCE_NAME); 967 if (irq < 0) 968 return irq; 969 970 return devm_request_irq(&priv->pdev->dev, irq, rswitch_gwca_ts_irq, 971 0, GWCA_TS_IRQ_NAME, priv); 972 } 973 974 /* Ethernet TSN Agent block (ETHA) and Ethernet MAC IP block (RMAC) */ 975 static int rswitch_etha_change_mode(struct rswitch_etha *etha, 976 enum rswitch_etha_mode mode) 977 { 978 int ret; 979 980 if (!rswitch_agent_clock_is_enabled(etha->coma_addr, etha->index)) 981 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 1); 982 983 iowrite32(mode, etha->addr + EAMC); 984 985 ret = rswitch_reg_wait(etha->addr, EAMS, EAMS_OPS_MASK, mode); 986 987 if (mode == EAMC_OPC_DISABLE) 988 rswitch_agent_clock_ctrl(etha->coma_addr, etha->index, 0); 989 990 return ret; 991 } 992 993 static void rswitch_etha_read_mac_address(struct rswitch_etha *etha) 994 { 995 u32 mrmac0 = ioread32(etha->addr + MRMAC0); 996 u32 mrmac1 = ioread32(etha->addr + MRMAC1); 997 u8 *mac = ða->mac_addr[0]; 998 999 mac[0] = (mrmac0 >> 8) & 0xFF; 1000 mac[1] = (mrmac0 >> 0) & 0xFF; 1001 mac[2] = (mrmac1 >> 24) & 0xFF; 1002 mac[3] = (mrmac1 >> 16) & 0xFF; 1003 mac[4] = (mrmac1 >> 8) & 0xFF; 1004 mac[5] = (mrmac1 >> 0) & 0xFF; 1005 } 1006 1007 static void rswitch_etha_write_mac_address(struct rswitch_etha *etha, const u8 *mac) 1008 { 1009 iowrite32((mac[0] << 8) | mac[1], etha->addr + MRMAC0); 1010 iowrite32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5], 1011 etha->addr + MRMAC1); 1012 } 1013 1014 static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha) 1015 { 1016 iowrite32(MLVC_PLV, etha->addr + MLVC); 1017 1018 return rswitch_reg_wait(etha->addr, MLVC, MLVC_PLV, 0); 1019 } 1020 1021 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac) 1022 { 1023 u32 val; 1024 1025 rswitch_etha_write_mac_address(etha, mac); 1026 1027 switch (etha->speed) { 1028 case 100: 1029 val = MPIC_LSC_100M; 1030 break; 1031 case 1000: 1032 val = MPIC_LSC_1G; 1033 break; 1034 case 2500: 1035 val = MPIC_LSC_2_5G; 1036 break; 1037 default: 1038 return; 1039 } 1040 1041 iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC); 1042 } 1043 1044 static void rswitch_etha_enable_mii(struct rswitch_etha *etha) 1045 { 1046 rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK, 1047 MPIC_PSMCS(0x05) | MPIC_PSMHT(0x06)); 1048 rswitch_modify(etha->addr, MPSM, 0, MPSM_MFF_C45); 1049 } 1050 1051 static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac) 1052 { 1053 int err; 1054 1055 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 1056 if (err < 0) 1057 return err; 1058 err = rswitch_etha_change_mode(etha, EAMC_OPC_CONFIG); 1059 if (err < 0) 1060 return err; 1061 1062 iowrite32(EAVCC_VEM_SC_TAG, etha->addr + EAVCC); 1063 rswitch_rmac_setting(etha, mac); 1064 rswitch_etha_enable_mii(etha); 1065 1066 err = rswitch_etha_wait_link_verification(etha); 1067 if (err < 0) 1068 return err; 1069 1070 err = rswitch_etha_change_mode(etha, EAMC_OPC_DISABLE); 1071 if (err < 0) 1072 return err; 1073 1074 return rswitch_etha_change_mode(etha, EAMC_OPC_OPERATION); 1075 } 1076 1077 static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read, 1078 int phyad, int devad, int regad, int data) 1079 { 1080 int pop = read ? MDIO_READ_C45 : MDIO_WRITE_C45; 1081 u32 val; 1082 int ret; 1083 1084 if (devad == 0xffffffff) 1085 return -ENODEV; 1086 1087 writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); 1088 1089 val = MPSM_PSME | MPSM_MFF_C45; 1090 iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1091 1092 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1093 if (ret) 1094 return ret; 1095 1096 rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); 1097 1098 if (read) { 1099 writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); 1100 1101 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1102 if (ret) 1103 return ret; 1104 1105 ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; 1106 1107 rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); 1108 } else { 1109 iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val, 1110 etha->addr + MPSM); 1111 1112 ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS); 1113 } 1114 1115 return ret; 1116 } 1117 1118 static int rswitch_etha_mii_read_c45(struct mii_bus *bus, int addr, int devad, 1119 int regad) 1120 { 1121 struct rswitch_etha *etha = bus->priv; 1122 1123 return rswitch_etha_set_access(etha, true, addr, devad, regad, 0); 1124 } 1125 1126 static int rswitch_etha_mii_write_c45(struct mii_bus *bus, int addr, int devad, 1127 int regad, u16 val) 1128 { 1129 struct rswitch_etha *etha = bus->priv; 1130 1131 return rswitch_etha_set_access(etha, false, addr, devad, regad, val); 1132 } 1133 1134 /* Call of_node_put(port) after done */ 1135 static struct device_node *rswitch_get_port_node(struct rswitch_device *rdev) 1136 { 1137 struct device_node *ports, *port; 1138 int err = 0; 1139 u32 index; 1140 1141 ports = of_get_child_by_name(rdev->ndev->dev.parent->of_node, 1142 "ethernet-ports"); 1143 if (!ports) 1144 return NULL; 1145 1146 for_each_child_of_node(ports, port) { 1147 err = of_property_read_u32(port, "reg", &index); 1148 if (err < 0) { 1149 port = NULL; 1150 goto out; 1151 } 1152 if (index == rdev->etha->index) { 1153 if (!of_device_is_available(port)) 1154 port = NULL; 1155 break; 1156 } 1157 } 1158 1159 out: 1160 of_node_put(ports); 1161 1162 return port; 1163 } 1164 1165 static int rswitch_etha_get_params(struct rswitch_device *rdev) 1166 { 1167 u32 max_speed; 1168 int err; 1169 1170 if (!rdev->np_port) 1171 return 0; /* ignored */ 1172 1173 err = of_get_phy_mode(rdev->np_port, &rdev->etha->phy_interface); 1174 if (err) 1175 return err; 1176 1177 err = of_property_read_u32(rdev->np_port, "max-speed", &max_speed); 1178 if (!err) { 1179 rdev->etha->speed = max_speed; 1180 return 0; 1181 } 1182 1183 /* if no "max-speed" property, let's use default speed */ 1184 switch (rdev->etha->phy_interface) { 1185 case PHY_INTERFACE_MODE_MII: 1186 rdev->etha->speed = SPEED_100; 1187 break; 1188 case PHY_INTERFACE_MODE_SGMII: 1189 rdev->etha->speed = SPEED_1000; 1190 break; 1191 case PHY_INTERFACE_MODE_USXGMII: 1192 rdev->etha->speed = SPEED_2500; 1193 break; 1194 default: 1195 return -EINVAL; 1196 } 1197 1198 return 0; 1199 } 1200 1201 static int rswitch_mii_register(struct rswitch_device *rdev) 1202 { 1203 struct device_node *mdio_np; 1204 struct mii_bus *mii_bus; 1205 int err; 1206 1207 mii_bus = mdiobus_alloc(); 1208 if (!mii_bus) 1209 return -ENOMEM; 1210 1211 mii_bus->name = "rswitch_mii"; 1212 sprintf(mii_bus->id, "etha%d", rdev->etha->index); 1213 mii_bus->priv = rdev->etha; 1214 mii_bus->read_c45 = rswitch_etha_mii_read_c45; 1215 mii_bus->write_c45 = rswitch_etha_mii_write_c45; 1216 mii_bus->parent = &rdev->priv->pdev->dev; 1217 1218 mdio_np = of_get_child_by_name(rdev->np_port, "mdio"); 1219 err = of_mdiobus_register(mii_bus, mdio_np); 1220 if (err < 0) { 1221 mdiobus_free(mii_bus); 1222 goto out; 1223 } 1224 1225 rdev->etha->mii = mii_bus; 1226 1227 out: 1228 of_node_put(mdio_np); 1229 1230 return err; 1231 } 1232 1233 static void rswitch_mii_unregister(struct rswitch_device *rdev) 1234 { 1235 if (rdev->etha->mii) { 1236 mdiobus_unregister(rdev->etha->mii); 1237 mdiobus_free(rdev->etha->mii); 1238 rdev->etha->mii = NULL; 1239 } 1240 } 1241 1242 static void rswitch_adjust_link(struct net_device *ndev) 1243 { 1244 struct rswitch_device *rdev = netdev_priv(ndev); 1245 struct phy_device *phydev = ndev->phydev; 1246 1247 if (phydev->link != rdev->etha->link) { 1248 phy_print_status(phydev); 1249 if (phydev->link) 1250 phy_power_on(rdev->serdes); 1251 else 1252 phy_power_off(rdev->serdes); 1253 1254 rdev->etha->link = phydev->link; 1255 1256 if (!rdev->priv->etha_no_runtime_change && 1257 phydev->speed != rdev->etha->speed) { 1258 rdev->etha->speed = phydev->speed; 1259 1260 rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); 1261 phy_set_speed(rdev->serdes, rdev->etha->speed); 1262 } 1263 } 1264 } 1265 1266 static void rswitch_phy_remove_link_mode(struct rswitch_device *rdev, 1267 struct phy_device *phydev) 1268 { 1269 if (!rdev->priv->etha_no_runtime_change) 1270 return; 1271 1272 switch (rdev->etha->speed) { 1273 case SPEED_2500: 1274 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1275 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1276 break; 1277 case SPEED_1000: 1278 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1279 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Full_BIT); 1280 break; 1281 case SPEED_100: 1282 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_2500baseX_Full_BIT); 1283 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Full_BIT); 1284 break; 1285 default: 1286 break; 1287 } 1288 1289 phy_set_max_speed(phydev, rdev->etha->speed); 1290 } 1291 1292 static int rswitch_phy_device_init(struct rswitch_device *rdev) 1293 { 1294 struct phy_device *phydev; 1295 struct device_node *phy; 1296 int err = -ENOENT; 1297 1298 if (!rdev->np_port) 1299 return -ENODEV; 1300 1301 phy = of_parse_phandle(rdev->np_port, "phy-handle", 0); 1302 if (!phy) 1303 return -ENODEV; 1304 1305 /* Set phydev->host_interfaces before calling of_phy_connect() to 1306 * configure the PHY with the information of host_interfaces. 1307 */ 1308 phydev = of_phy_find_device(phy); 1309 if (!phydev) 1310 goto out; 1311 __set_bit(rdev->etha->phy_interface, phydev->host_interfaces); 1312 1313 phydev = of_phy_connect(rdev->ndev, phy, rswitch_adjust_link, 0, 1314 rdev->etha->phy_interface); 1315 if (!phydev) 1316 goto out; 1317 1318 phy_set_max_speed(phydev, SPEED_2500); 1319 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1320 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1321 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1322 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1323 rswitch_phy_remove_link_mode(rdev, phydev); 1324 1325 phy_attached_info(phydev); 1326 1327 err = 0; 1328 out: 1329 of_node_put(phy); 1330 1331 return err; 1332 } 1333 1334 static void rswitch_phy_device_deinit(struct rswitch_device *rdev) 1335 { 1336 if (rdev->ndev->phydev) 1337 phy_disconnect(rdev->ndev->phydev); 1338 } 1339 1340 static int rswitch_serdes_set_params(struct rswitch_device *rdev) 1341 { 1342 int err; 1343 1344 err = phy_set_mode_ext(rdev->serdes, PHY_MODE_ETHERNET, 1345 rdev->etha->phy_interface); 1346 if (err < 0) 1347 return err; 1348 1349 return phy_set_speed(rdev->serdes, rdev->etha->speed); 1350 } 1351 1352 static int rswitch_ether_port_init_one(struct rswitch_device *rdev) 1353 { 1354 int err; 1355 1356 if (!rdev->etha->operated) { 1357 err = rswitch_etha_hw_init(rdev->etha, rdev->ndev->dev_addr); 1358 if (err < 0) 1359 return err; 1360 if (rdev->priv->etha_no_runtime_change) 1361 rdev->etha->operated = true; 1362 } 1363 1364 err = rswitch_mii_register(rdev); 1365 if (err < 0) 1366 return err; 1367 1368 err = rswitch_phy_device_init(rdev); 1369 if (err < 0) 1370 goto err_phy_device_init; 1371 1372 rdev->serdes = devm_of_phy_get(&rdev->priv->pdev->dev, rdev->np_port, NULL); 1373 if (IS_ERR(rdev->serdes)) { 1374 err = PTR_ERR(rdev->serdes); 1375 goto err_serdes_phy_get; 1376 } 1377 1378 err = rswitch_serdes_set_params(rdev); 1379 if (err < 0) 1380 goto err_serdes_set_params; 1381 1382 return 0; 1383 1384 err_serdes_set_params: 1385 err_serdes_phy_get: 1386 rswitch_phy_device_deinit(rdev); 1387 1388 err_phy_device_init: 1389 rswitch_mii_unregister(rdev); 1390 1391 return err; 1392 } 1393 1394 static void rswitch_ether_port_deinit_one(struct rswitch_device *rdev) 1395 { 1396 rswitch_phy_device_deinit(rdev); 1397 rswitch_mii_unregister(rdev); 1398 } 1399 1400 static int rswitch_ether_port_init_all(struct rswitch_private *priv) 1401 { 1402 int i, err; 1403 1404 rswitch_for_each_enabled_port(priv, i) { 1405 err = rswitch_ether_port_init_one(priv->rdev[i]); 1406 if (err) 1407 goto err_init_one; 1408 } 1409 1410 rswitch_for_each_enabled_port(priv, i) { 1411 err = phy_init(priv->rdev[i]->serdes); 1412 if (err) 1413 goto err_serdes; 1414 } 1415 1416 return 0; 1417 1418 err_serdes: 1419 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1420 phy_exit(priv->rdev[i]->serdes); 1421 i = RSWITCH_NUM_PORTS; 1422 1423 err_init_one: 1424 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1425 rswitch_ether_port_deinit_one(priv->rdev[i]); 1426 1427 return err; 1428 } 1429 1430 static void rswitch_ether_port_deinit_all(struct rswitch_private *priv) 1431 { 1432 int i; 1433 1434 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1435 phy_exit(priv->rdev[i]->serdes); 1436 rswitch_ether_port_deinit_one(priv->rdev[i]); 1437 } 1438 } 1439 1440 static int rswitch_open(struct net_device *ndev) 1441 { 1442 struct rswitch_device *rdev = netdev_priv(ndev); 1443 1444 phy_start(ndev->phydev); 1445 1446 napi_enable(&rdev->napi); 1447 netif_start_queue(ndev); 1448 1449 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, true); 1450 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, true); 1451 1452 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) 1453 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDIE); 1454 1455 bitmap_set(rdev->priv->opened_ports, rdev->port, 1); 1456 1457 return 0; 1458 }; 1459 1460 static int rswitch_stop(struct net_device *ndev) 1461 { 1462 struct rswitch_device *rdev = netdev_priv(ndev); 1463 struct rswitch_gwca_ts_info *ts_info, *ts_info2; 1464 1465 netif_tx_stop_all_queues(ndev); 1466 bitmap_clear(rdev->priv->opened_ports, rdev->port, 1); 1467 1468 if (bitmap_empty(rdev->priv->opened_ports, RSWITCH_NUM_PORTS)) 1469 iowrite32(GWCA_TS_IRQ_BIT, rdev->priv->addr + GWTSDID); 1470 1471 list_for_each_entry_safe(ts_info, ts_info2, &rdev->priv->gwca.ts_info_list, list) { 1472 if (ts_info->port != rdev->port) 1473 continue; 1474 dev_kfree_skb_irq(ts_info->skb); 1475 list_del(&ts_info->list); 1476 kfree(ts_info); 1477 } 1478 1479 rswitch_enadis_data_irq(rdev->priv, rdev->tx_queue->index, false); 1480 rswitch_enadis_data_irq(rdev->priv, rdev->rx_queue->index, false); 1481 1482 phy_stop(ndev->phydev); 1483 napi_disable(&rdev->napi); 1484 1485 return 0; 1486 }; 1487 1488 static netdev_tx_t rswitch_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1489 { 1490 struct rswitch_device *rdev = netdev_priv(ndev); 1491 struct rswitch_gwca_queue *gq = rdev->tx_queue; 1492 struct rswitch_ext_desc *desc; 1493 int ret = NETDEV_TX_OK; 1494 dma_addr_t dma_addr; 1495 1496 if (rswitch_get_num_cur_queues(gq) >= gq->ring_size - 1) { 1497 netif_stop_subqueue(ndev, 0); 1498 return NETDEV_TX_BUSY; 1499 } 1500 1501 if (skb_put_padto(skb, ETH_ZLEN)) 1502 return ret; 1503 1504 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, DMA_TO_DEVICE); 1505 if (dma_mapping_error(ndev->dev.parent, dma_addr)) { 1506 dev_kfree_skb_any(skb); 1507 return ret; 1508 } 1509 1510 gq->skbs[gq->cur] = skb; 1511 desc = &gq->tx_ring[gq->cur]; 1512 rswitch_desc_set_dptr(&desc->desc, dma_addr); 1513 desc->desc.info_ds = cpu_to_le16(skb->len); 1514 1515 desc->info1 = cpu_to_le64(INFO1_DV(BIT(rdev->etha->index)) | 1516 INFO1_IPV(GWCA_IPV_NUM) | INFO1_FMT); 1517 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 1518 struct rswitch_gwca_ts_info *ts_info; 1519 1520 ts_info = kzalloc(sizeof(*ts_info), GFP_ATOMIC); 1521 if (!ts_info) { 1522 dma_unmap_single(ndev->dev.parent, dma_addr, skb->len, DMA_TO_DEVICE); 1523 return -ENOMEM; 1524 } 1525 1526 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1527 rdev->ts_tag++; 1528 desc->info1 |= cpu_to_le64(INFO1_TSUN(rdev->ts_tag) | INFO1_TXC); 1529 1530 ts_info->skb = skb_get(skb); 1531 ts_info->port = rdev->port; 1532 ts_info->tag = rdev->ts_tag; 1533 list_add_tail(&ts_info->list, &rdev->priv->gwca.ts_info_list); 1534 1535 skb_tx_timestamp(skb); 1536 } 1537 1538 dma_wmb(); 1539 1540 desc->desc.die_dt = DT_FSINGLE | DIE; 1541 wmb(); /* gq->cur must be incremented after die_dt was set */ 1542 1543 gq->cur = rswitch_next_queue_index(gq, true, 1); 1544 rswitch_modify(rdev->addr, GWTRC(gq->index), 0, BIT(gq->index % 32)); 1545 1546 return ret; 1547 } 1548 1549 static struct net_device_stats *rswitch_get_stats(struct net_device *ndev) 1550 { 1551 return &ndev->stats; 1552 } 1553 1554 static int rswitch_hwstamp_get(struct net_device *ndev, struct ifreq *req) 1555 { 1556 struct rswitch_device *rdev = netdev_priv(ndev); 1557 struct rcar_gen4_ptp_private *ptp_priv; 1558 struct hwtstamp_config config; 1559 1560 ptp_priv = rdev->priv->ptp_priv; 1561 1562 config.flags = 0; 1563 config.tx_type = ptp_priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1564 HWTSTAMP_TX_OFF; 1565 switch (ptp_priv->tstamp_rx_ctrl & RCAR_GEN4_RXTSTAMP_TYPE) { 1566 case RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT: 1567 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1568 break; 1569 case RCAR_GEN4_RXTSTAMP_TYPE_ALL: 1570 config.rx_filter = HWTSTAMP_FILTER_ALL; 1571 break; 1572 default: 1573 config.rx_filter = HWTSTAMP_FILTER_NONE; 1574 break; 1575 } 1576 1577 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1578 } 1579 1580 static int rswitch_hwstamp_set(struct net_device *ndev, struct ifreq *req) 1581 { 1582 struct rswitch_device *rdev = netdev_priv(ndev); 1583 u32 tstamp_rx_ctrl = RCAR_GEN4_RXTSTAMP_ENABLED; 1584 struct hwtstamp_config config; 1585 u32 tstamp_tx_ctrl; 1586 1587 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1588 return -EFAULT; 1589 1590 if (config.flags) 1591 return -EINVAL; 1592 1593 switch (config.tx_type) { 1594 case HWTSTAMP_TX_OFF: 1595 tstamp_tx_ctrl = 0; 1596 break; 1597 case HWTSTAMP_TX_ON: 1598 tstamp_tx_ctrl = RCAR_GEN4_TXTSTAMP_ENABLED; 1599 break; 1600 default: 1601 return -ERANGE; 1602 } 1603 1604 switch (config.rx_filter) { 1605 case HWTSTAMP_FILTER_NONE: 1606 tstamp_rx_ctrl = 0; 1607 break; 1608 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1609 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_V2_L2_EVENT; 1610 break; 1611 default: 1612 config.rx_filter = HWTSTAMP_FILTER_ALL; 1613 tstamp_rx_ctrl |= RCAR_GEN4_RXTSTAMP_TYPE_ALL; 1614 break; 1615 } 1616 1617 rdev->priv->ptp_priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1618 rdev->priv->ptp_priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1619 1620 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? -EFAULT : 0; 1621 } 1622 1623 static int rswitch_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1624 { 1625 if (!netif_running(ndev)) 1626 return -EINVAL; 1627 1628 switch (cmd) { 1629 case SIOCGHWTSTAMP: 1630 return rswitch_hwstamp_get(ndev, req); 1631 case SIOCSHWTSTAMP: 1632 return rswitch_hwstamp_set(ndev, req); 1633 default: 1634 return phy_mii_ioctl(ndev->phydev, req, cmd); 1635 } 1636 } 1637 1638 static const struct net_device_ops rswitch_netdev_ops = { 1639 .ndo_open = rswitch_open, 1640 .ndo_stop = rswitch_stop, 1641 .ndo_start_xmit = rswitch_start_xmit, 1642 .ndo_get_stats = rswitch_get_stats, 1643 .ndo_eth_ioctl = rswitch_eth_ioctl, 1644 .ndo_validate_addr = eth_validate_addr, 1645 .ndo_set_mac_address = eth_mac_addr, 1646 }; 1647 1648 static int rswitch_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) 1649 { 1650 struct rswitch_device *rdev = netdev_priv(ndev); 1651 1652 info->phc_index = ptp_clock_index(rdev->priv->ptp_priv->clock); 1653 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 1654 SOF_TIMESTAMPING_RX_SOFTWARE | 1655 SOF_TIMESTAMPING_SOFTWARE | 1656 SOF_TIMESTAMPING_TX_HARDWARE | 1657 SOF_TIMESTAMPING_RX_HARDWARE | 1658 SOF_TIMESTAMPING_RAW_HARDWARE; 1659 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 1660 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1661 1662 return 0; 1663 } 1664 1665 static const struct ethtool_ops rswitch_ethtool_ops = { 1666 .get_ts_info = rswitch_get_ts_info, 1667 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1668 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1669 }; 1670 1671 static const struct of_device_id renesas_eth_sw_of_table[] = { 1672 { .compatible = "renesas,r8a779f0-ether-switch", }, 1673 { } 1674 }; 1675 MODULE_DEVICE_TABLE(of, renesas_eth_sw_of_table); 1676 1677 static void rswitch_etha_init(struct rswitch_private *priv, int index) 1678 { 1679 struct rswitch_etha *etha = &priv->etha[index]; 1680 1681 memset(etha, 0, sizeof(*etha)); 1682 etha->index = index; 1683 etha->addr = priv->addr + RSWITCH_ETHA_OFFSET + index * RSWITCH_ETHA_SIZE; 1684 etha->coma_addr = priv->addr; 1685 } 1686 1687 static int rswitch_device_alloc(struct rswitch_private *priv, int index) 1688 { 1689 struct platform_device *pdev = priv->pdev; 1690 struct rswitch_device *rdev; 1691 struct net_device *ndev; 1692 int err; 1693 1694 if (index >= RSWITCH_NUM_PORTS) 1695 return -EINVAL; 1696 1697 ndev = alloc_etherdev_mqs(sizeof(struct rswitch_device), 1, 1); 1698 if (!ndev) 1699 return -ENOMEM; 1700 1701 SET_NETDEV_DEV(ndev, &pdev->dev); 1702 ether_setup(ndev); 1703 1704 rdev = netdev_priv(ndev); 1705 rdev->ndev = ndev; 1706 rdev->priv = priv; 1707 priv->rdev[index] = rdev; 1708 rdev->port = index; 1709 rdev->etha = &priv->etha[index]; 1710 rdev->addr = priv->addr; 1711 1712 ndev->base_addr = (unsigned long)rdev->addr; 1713 snprintf(ndev->name, IFNAMSIZ, "tsn%d", index); 1714 ndev->netdev_ops = &rswitch_netdev_ops; 1715 ndev->ethtool_ops = &rswitch_ethtool_ops; 1716 1717 netif_napi_add(ndev, &rdev->napi, rswitch_poll); 1718 1719 rdev->np_port = rswitch_get_port_node(rdev); 1720 rdev->disabled = !rdev->np_port; 1721 err = of_get_ethdev_address(rdev->np_port, ndev); 1722 of_node_put(rdev->np_port); 1723 if (err) { 1724 if (is_valid_ether_addr(rdev->etha->mac_addr)) 1725 eth_hw_addr_set(ndev, rdev->etha->mac_addr); 1726 else 1727 eth_hw_addr_random(ndev); 1728 } 1729 1730 err = rswitch_etha_get_params(rdev); 1731 if (err < 0) 1732 goto out_get_params; 1733 1734 if (rdev->priv->gwca.speed < rdev->etha->speed) 1735 rdev->priv->gwca.speed = rdev->etha->speed; 1736 1737 err = rswitch_rxdmac_alloc(ndev); 1738 if (err < 0) 1739 goto out_rxdmac; 1740 1741 err = rswitch_txdmac_alloc(ndev); 1742 if (err < 0) 1743 goto out_txdmac; 1744 1745 return 0; 1746 1747 out_txdmac: 1748 rswitch_rxdmac_free(ndev); 1749 1750 out_rxdmac: 1751 out_get_params: 1752 netif_napi_del(&rdev->napi); 1753 free_netdev(ndev); 1754 1755 return err; 1756 } 1757 1758 static void rswitch_device_free(struct rswitch_private *priv, int index) 1759 { 1760 struct rswitch_device *rdev = priv->rdev[index]; 1761 struct net_device *ndev = rdev->ndev; 1762 1763 rswitch_txdmac_free(ndev); 1764 rswitch_rxdmac_free(ndev); 1765 netif_napi_del(&rdev->napi); 1766 free_netdev(ndev); 1767 } 1768 1769 static int rswitch_init(struct rswitch_private *priv) 1770 { 1771 int i, err; 1772 1773 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1774 rswitch_etha_init(priv, i); 1775 1776 rswitch_clock_enable(priv); 1777 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1778 rswitch_etha_read_mac_address(&priv->etha[i]); 1779 1780 rswitch_reset(priv); 1781 1782 rswitch_clock_enable(priv); 1783 rswitch_top_init(priv); 1784 err = rswitch_bpool_config(priv); 1785 if (err < 0) 1786 return err; 1787 1788 rswitch_coma_init(priv); 1789 1790 err = rswitch_gwca_linkfix_alloc(priv); 1791 if (err < 0) 1792 return -ENOMEM; 1793 1794 err = rswitch_gwca_ts_queue_alloc(priv); 1795 if (err < 0) 1796 goto err_ts_queue_alloc; 1797 1798 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1799 err = rswitch_device_alloc(priv, i); 1800 if (err < 0) { 1801 for (i--; i >= 0; i--) 1802 rswitch_device_free(priv, i); 1803 goto err_device_alloc; 1804 } 1805 } 1806 1807 rswitch_fwd_init(priv); 1808 1809 err = rcar_gen4_ptp_register(priv->ptp_priv, RCAR_GEN4_PTP_REG_LAYOUT_S4, 1810 RCAR_GEN4_PTP_CLOCK_S4); 1811 if (err < 0) 1812 goto err_ptp_register; 1813 1814 err = rswitch_gwca_request_irqs(priv); 1815 if (err < 0) 1816 goto err_gwca_request_irq; 1817 1818 err = rswitch_gwca_ts_request_irqs(priv); 1819 if (err < 0) 1820 goto err_gwca_ts_request_irq; 1821 1822 err = rswitch_gwca_hw_init(priv); 1823 if (err < 0) 1824 goto err_gwca_hw_init; 1825 1826 err = rswitch_ether_port_init_all(priv); 1827 if (err) 1828 goto err_ether_port_init_all; 1829 1830 rswitch_for_each_enabled_port(priv, i) { 1831 err = register_netdev(priv->rdev[i]->ndev); 1832 if (err) { 1833 rswitch_for_each_enabled_port_continue_reverse(priv, i) 1834 unregister_netdev(priv->rdev[i]->ndev); 1835 goto err_register_netdev; 1836 } 1837 } 1838 1839 rswitch_for_each_enabled_port(priv, i) 1840 netdev_info(priv->rdev[i]->ndev, "MAC address %pM\n", 1841 priv->rdev[i]->ndev->dev_addr); 1842 1843 return 0; 1844 1845 err_register_netdev: 1846 rswitch_ether_port_deinit_all(priv); 1847 1848 err_ether_port_init_all: 1849 rswitch_gwca_hw_deinit(priv); 1850 1851 err_gwca_hw_init: 1852 err_gwca_ts_request_irq: 1853 err_gwca_request_irq: 1854 rcar_gen4_ptp_unregister(priv->ptp_priv); 1855 1856 err_ptp_register: 1857 for (i = 0; i < RSWITCH_NUM_PORTS; i++) 1858 rswitch_device_free(priv, i); 1859 1860 err_device_alloc: 1861 rswitch_gwca_ts_queue_free(priv); 1862 1863 err_ts_queue_alloc: 1864 rswitch_gwca_linkfix_free(priv); 1865 1866 return err; 1867 } 1868 1869 static const struct soc_device_attribute rswitch_soc_no_speed_change[] = { 1870 { .soc_id = "r8a779f0", .revision = "ES1.0" }, 1871 { /* Sentinel */ } 1872 }; 1873 1874 static int renesas_eth_sw_probe(struct platform_device *pdev) 1875 { 1876 const struct soc_device_attribute *attr; 1877 struct rswitch_private *priv; 1878 struct resource *res; 1879 int ret; 1880 1881 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "secure_base"); 1882 if (!res) { 1883 dev_err(&pdev->dev, "invalid resource\n"); 1884 return -EINVAL; 1885 } 1886 1887 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1888 if (!priv) 1889 return -ENOMEM; 1890 1891 attr = soc_device_match(rswitch_soc_no_speed_change); 1892 if (attr) 1893 priv->etha_no_runtime_change = true; 1894 1895 priv->ptp_priv = rcar_gen4_ptp_alloc(pdev); 1896 if (!priv->ptp_priv) 1897 return -ENOMEM; 1898 1899 platform_set_drvdata(pdev, priv); 1900 priv->pdev = pdev; 1901 priv->addr = devm_ioremap_resource(&pdev->dev, res); 1902 if (IS_ERR(priv->addr)) 1903 return PTR_ERR(priv->addr); 1904 1905 priv->ptp_priv->addr = priv->addr + RCAR_GEN4_GPTP_OFFSET_S4; 1906 1907 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 1908 if (ret < 0) { 1909 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1910 if (ret < 0) 1911 return ret; 1912 } 1913 1914 priv->gwca.index = AGENT_INDEX_GWCA; 1915 priv->gwca.num_queues = min(RSWITCH_NUM_PORTS * NUM_QUEUES_PER_NDEV, 1916 RSWITCH_MAX_NUM_QUEUES); 1917 priv->gwca.queues = devm_kcalloc(&pdev->dev, priv->gwca.num_queues, 1918 sizeof(*priv->gwca.queues), GFP_KERNEL); 1919 if (!priv->gwca.queues) 1920 return -ENOMEM; 1921 1922 pm_runtime_enable(&pdev->dev); 1923 pm_runtime_get_sync(&pdev->dev); 1924 1925 ret = rswitch_init(priv); 1926 if (ret < 0) { 1927 pm_runtime_put(&pdev->dev); 1928 pm_runtime_disable(&pdev->dev); 1929 return ret; 1930 } 1931 1932 device_set_wakeup_capable(&pdev->dev, 1); 1933 1934 return ret; 1935 } 1936 1937 static void rswitch_deinit(struct rswitch_private *priv) 1938 { 1939 int i; 1940 1941 rswitch_gwca_hw_deinit(priv); 1942 rcar_gen4_ptp_unregister(priv->ptp_priv); 1943 1944 for (i = 0; i < RSWITCH_NUM_PORTS; i++) { 1945 struct rswitch_device *rdev = priv->rdev[i]; 1946 1947 phy_exit(priv->rdev[i]->serdes); 1948 rswitch_ether_port_deinit_one(rdev); 1949 unregister_netdev(rdev->ndev); 1950 rswitch_device_free(priv, i); 1951 } 1952 1953 rswitch_gwca_ts_queue_free(priv); 1954 rswitch_gwca_linkfix_free(priv); 1955 1956 rswitch_clock_disable(priv); 1957 } 1958 1959 static int renesas_eth_sw_remove(struct platform_device *pdev) 1960 { 1961 struct rswitch_private *priv = platform_get_drvdata(pdev); 1962 1963 rswitch_deinit(priv); 1964 1965 pm_runtime_put(&pdev->dev); 1966 pm_runtime_disable(&pdev->dev); 1967 1968 platform_set_drvdata(pdev, NULL); 1969 1970 return 0; 1971 } 1972 1973 static struct platform_driver renesas_eth_sw_driver_platform = { 1974 .probe = renesas_eth_sw_probe, 1975 .remove = renesas_eth_sw_remove, 1976 .driver = { 1977 .name = "renesas_eth_sw", 1978 .of_match_table = renesas_eth_sw_of_table, 1979 } 1980 }; 1981 module_platform_driver(renesas_eth_sw_driver_platform); 1982 MODULE_AUTHOR("Yoshihiro Shimoda"); 1983 MODULE_DESCRIPTION("Renesas Ethernet Switch device driver"); 1984 MODULE_LICENSE("GPL"); 1985