xref: /linux/drivers/net/ethernet/renesas/ravb.h (revision eb01fe7abbe2d0b38824d2a93fdb4cc3eaf2ccc1) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Renesas Ethernet AVB device driver
3  *
4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
5  * Copyright (C) 2015 Renesas Solutions Corp.
6  * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7  *
8  * Based on the SuperH Ethernet driver
9  */
10 
11 #ifndef __RAVB_H__
12 #define __RAVB_H__
13 
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/kernel.h>
17 #include <linux/mdio-bitbang.h>
18 #include <linux/netdevice.h>
19 #include <linux/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/ptp_clock_kernel.h>
22 
23 #define BE_TX_RING_SIZE	64	/* TX ring size for Best Effort */
24 #define BE_RX_RING_SIZE	1024	/* RX ring size for Best Effort */
25 #define NC_TX_RING_SIZE	64	/* TX ring size for Network Control */
26 #define NC_RX_RING_SIZE	64	/* RX ring size for Network Control */
27 #define BE_TX_RING_MIN	64
28 #define BE_RX_RING_MIN	64
29 #define BE_TX_RING_MAX	1024
30 #define BE_RX_RING_MAX	2048
31 
32 #define PKT_BUF_SZ	1538
33 
34 /* Driver's parameters */
35 #define RAVB_ALIGN	128
36 
37 /* Hardware time stamp */
38 #define RAVB_TXTSTAMP_VALID	0x00000001	/* TX timestamp valid */
39 #define RAVB_TXTSTAMP_ENABLED	0x00000010	/* Enable TX timestamping */
40 
41 #define RAVB_RXTSTAMP_VALID	0x00000001	/* RX timestamp valid */
42 #define RAVB_RXTSTAMP_TYPE	0x00000006	/* RX type mask */
43 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
44 #define RAVB_RXTSTAMP_TYPE_ALL	0x00000006
45 #define RAVB_RXTSTAMP_ENABLED	0x00000010	/* Enable RX timestamping */
46 
47 enum ravb_reg {
48 	/* AVB-DMAC registers */
49 	CCC	= 0x0000,
50 	DBAT	= 0x0004,
51 	DLR	= 0x0008,
52 	CSR	= 0x000C,
53 	CDAR0	= 0x0010,
54 	CDAR1	= 0x0014,
55 	CDAR2	= 0x0018,
56 	CDAR3	= 0x001C,
57 	CDAR4	= 0x0020,
58 	CDAR5	= 0x0024,
59 	CDAR6	= 0x0028,
60 	CDAR7	= 0x002C,
61 	CDAR8	= 0x0030,
62 	CDAR9	= 0x0034,
63 	CDAR10	= 0x0038,
64 	CDAR11	= 0x003C,
65 	CDAR12	= 0x0040,
66 	CDAR13	= 0x0044,
67 	CDAR14	= 0x0048,
68 	CDAR15	= 0x004C,
69 	CDAR16	= 0x0050,
70 	CDAR17	= 0x0054,
71 	CDAR18	= 0x0058,
72 	CDAR19	= 0x005C,
73 	CDAR20	= 0x0060,
74 	CDAR21	= 0x0064,
75 	ESR	= 0x0088,
76 	APSR	= 0x008C,	/* R-Car Gen3 only */
77 	RCR	= 0x0090,
78 	RQC0	= 0x0094,
79 	RQC1	= 0x0098,
80 	RQC2	= 0x009C,
81 	RQC3	= 0x00A0,
82 	RQC4	= 0x00A4,
83 	RPC	= 0x00B0,
84 	RTC	= 0x00B4,	/* R-Car Gen3 and RZ/G2L only */
85 	UFCW	= 0x00BC,
86 	UFCS	= 0x00C0,
87 	UFCV0	= 0x00C4,
88 	UFCV1	= 0x00C8,
89 	UFCV2	= 0x00CC,
90 	UFCV3	= 0x00D0,
91 	UFCV4	= 0x00D4,
92 	UFCD0	= 0x00E0,
93 	UFCD1	= 0x00E4,
94 	UFCD2	= 0x00E8,
95 	UFCD3	= 0x00EC,
96 	UFCD4	= 0x00F0,
97 	SFO	= 0x00FC,
98 	SFP0	= 0x0100,
99 	SFP1	= 0x0104,
100 	SFP2	= 0x0108,
101 	SFP3	= 0x010C,
102 	SFP4	= 0x0110,
103 	SFP5	= 0x0114,
104 	SFP6	= 0x0118,
105 	SFP7	= 0x011C,
106 	SFP8	= 0x0120,
107 	SFP9	= 0x0124,
108 	SFP10	= 0x0128,
109 	SFP11	= 0x012C,
110 	SFP12	= 0x0130,
111 	SFP13	= 0x0134,
112 	SFP14	= 0x0138,
113 	SFP15	= 0x013C,
114 	SFP16	= 0x0140,
115 	SFP17	= 0x0144,
116 	SFP18	= 0x0148,
117 	SFP19	= 0x014C,
118 	SFP20	= 0x0150,
119 	SFP21	= 0x0154,
120 	SFP22	= 0x0158,
121 	SFP23	= 0x015C,
122 	SFP24	= 0x0160,
123 	SFP25	= 0x0164,
124 	SFP26	= 0x0168,
125 	SFP27	= 0x016C,
126 	SFP28	= 0x0170,
127 	SFP29	= 0x0174,
128 	SFP30	= 0x0178,
129 	SFP31	= 0x017C,
130 	SFM0	= 0x01C0,
131 	SFM1	= 0x01C4,
132 	TGC	= 0x0300,
133 	TCCR	= 0x0304,
134 	TSR	= 0x0308,
135 	TFA0	= 0x0310,
136 	TFA1	= 0x0314,
137 	TFA2	= 0x0318,
138 	CIVR0	= 0x0320,
139 	CIVR1	= 0x0324,
140 	CDVR0	= 0x0328,
141 	CDVR1	= 0x032C,
142 	CUL0	= 0x0330,
143 	CUL1	= 0x0334,
144 	CLL0	= 0x0338,
145 	CLL1	= 0x033C,
146 	DIC	= 0x0350,
147 	DIS	= 0x0354,
148 	EIC	= 0x0358,
149 	EIS	= 0x035C,
150 	RIC0	= 0x0360,
151 	RIS0	= 0x0364,
152 	RIC1	= 0x0368,
153 	RIS1	= 0x036C,
154 	RIC2	= 0x0370,
155 	RIS2	= 0x0374,
156 	TIC	= 0x0378,
157 	TIS	= 0x037C,
158 	ISS	= 0x0380,
159 	CIE	= 0x0384,	/* R-Car Gen3 only */
160 	GCCR	= 0x0390,
161 	GMTT	= 0x0394,
162 	GPTC	= 0x0398,
163 	GTI	= 0x039C,
164 	GTO0	= 0x03A0,
165 	GTO1	= 0x03A4,
166 	GTO2	= 0x03A8,
167 	GIC	= 0x03AC,
168 	GIS	= 0x03B0,
169 	GCPT	= 0x03B4,	/* Documented for R-Car Gen3 only */
170 	GCT0	= 0x03B8,
171 	GCT1	= 0x03BC,
172 	GCT2	= 0x03C0,
173 	GIE	= 0x03CC,	/* R-Car Gen3 only */
174 	GID	= 0x03D0,	/* R-Car Gen3 only */
175 	DIL	= 0x0440,	/* R-Car Gen3 only */
176 	RIE0	= 0x0460,	/* R-Car Gen3 only */
177 	RID0	= 0x0464,	/* R-Car Gen3 only */
178 	RIE2	= 0x0470,	/* R-Car Gen3 only */
179 	RID2	= 0x0474,	/* R-Car Gen3 only */
180 	TIE	= 0x0478,	/* R-Car Gen3 only */
181 	TID	= 0x047c,	/* R-Car Gen3 only */
182 
183 	/* E-MAC registers */
184 	ECMR	= 0x0500,
185 	RFLR	= 0x0508,
186 	ECSR	= 0x0510,
187 	ECSIPR	= 0x0518,
188 	PIR	= 0x0520,
189 	PSR	= 0x0528,
190 	PIPR	= 0x052c,
191 	CXR31	= 0x0530,	/* RZ/G2L only */
192 	CXR35	= 0x0540,	/* RZ/G2L only */
193 	MPR	= 0x0558,
194 	PFTCR	= 0x055c,
195 	PFRCR	= 0x0560,
196 	GECMR	= 0x05b0,
197 	MAHR	= 0x05c0,
198 	MALR	= 0x05c8,
199 	TROCR	= 0x0700,	/* R-Car Gen3 and RZ/G2L only */
200 	CXR41	= 0x0708,	/* RZ/G2L only */
201 	CXR42	= 0x0710,	/* RZ/G2L only */
202 	CEFCR	= 0x0740,
203 	FRECR	= 0x0748,
204 	TSFRCR	= 0x0750,
205 	TLFRCR	= 0x0758,
206 	RFCR	= 0x0760,
207 	MAFCR	= 0x0778,
208 
209 	/* TOE registers (RZ/G2L only) */
210 	CSR0    = 0x0800,
211 	CSR1    = 0x0804,
212 	CSR2    = 0x0808,
213 };
214 
215 
216 /* Register bits of the Ethernet AVB */
217 /* CCC */
218 enum CCC_BIT {
219 	CCC_OPC		= 0x00000003,
220 	CCC_OPC_RESET	= 0x00000000,
221 	CCC_OPC_CONFIG	= 0x00000001,
222 	CCC_OPC_OPERATION = 0x00000002,
223 	CCC_GAC		= 0x00000080,
224 	CCC_DTSR	= 0x00000100,
225 	CCC_CSEL	= 0x00030000,
226 	CCC_CSEL_HPB	= 0x00010000,
227 	CCC_CSEL_ETH_TX	= 0x00020000,
228 	CCC_CSEL_GMII_REF = 0x00030000,
229 	CCC_LBME	= 0x01000000,
230 };
231 
232 /* CSR */
233 enum CSR_BIT {
234 	CSR_OPS		= 0x0000000F,
235 	CSR_OPS_RESET	= 0x00000001,
236 	CSR_OPS_CONFIG	= 0x00000002,
237 	CSR_OPS_OPERATION = 0x00000004,
238 	CSR_OPS_STANDBY	= 0x00000008,	/* Documented for R-Car Gen3 only */
239 	CSR_DTS		= 0x00000100,
240 	CSR_TPO0	= 0x00010000,
241 	CSR_TPO1	= 0x00020000,
242 	CSR_TPO2	= 0x00040000,
243 	CSR_TPO3	= 0x00080000,
244 	CSR_RPO		= 0x00100000,
245 };
246 
247 /* ESR */
248 enum ESR_BIT {
249 	ESR_EQN		= 0x0000001F,
250 	ESR_ET		= 0x00000F00,
251 	ESR_EIL		= 0x00001000,
252 };
253 
254 /* APSR (R-Car Gen3 only) */
255 enum APSR_BIT {
256 	APSR_MEMS	= 0x00000002,	/* Undocumented */
257 	APSR_CMSW	= 0x00000010,
258 	APSR_RDM	= 0x00002000,
259 	APSR_TDM	= 0x00004000,
260 };
261 
262 /* RCR */
263 enum RCR_BIT {
264 	RCR_EFFS	= 0x00000001,
265 	RCR_ENCF	= 0x00000002,
266 	RCR_ESF		= 0x0000000C,
267 	RCR_ETS0	= 0x00000010,
268 	RCR_ETS2	= 0x00000020,
269 	RCR_RFCL	= 0x1FFF0000,
270 };
271 
272 /* RQC0/1/2/3/4 */
273 enum RQC_BIT {
274 	RQC_RSM0	= 0x00000003,
275 	RQC_UFCC0	= 0x00000030,
276 	RQC_RSM1	= 0x00000300,
277 	RQC_UFCC1	= 0x00003000,
278 	RQC_RSM2	= 0x00030000,
279 	RQC_UFCC2	= 0x00300000,
280 	RQC_RSM3	= 0x03000000,
281 	RQC_UFCC3	= 0x30000000,
282 };
283 
284 /* RPC */
285 enum RPC_BIT {
286 	RPC_PCNT	= 0x00000700,
287 	RPC_DCNT	= 0x00FF0000,
288 };
289 
290 /* UFCW */
291 enum UFCW_BIT {
292 	UFCW_WL0	= 0x0000003F,
293 	UFCW_WL1	= 0x00003F00,
294 	UFCW_WL2	= 0x003F0000,
295 	UFCW_WL3	= 0x3F000000,
296 };
297 
298 /* UFCS */
299 enum UFCS_BIT {
300 	UFCS_SL0	= 0x0000003F,
301 	UFCS_SL1	= 0x00003F00,
302 	UFCS_SL2	= 0x003F0000,
303 	UFCS_SL3	= 0x3F000000,
304 };
305 
306 /* UFCV0/1/2/3/4 */
307 enum UFCV_BIT {
308 	UFCV_CV0	= 0x0000003F,
309 	UFCV_CV1	= 0x00003F00,
310 	UFCV_CV2	= 0x003F0000,
311 	UFCV_CV3	= 0x3F000000,
312 };
313 
314 /* UFCD0/1/2/3/4 */
315 enum UFCD_BIT {
316 	UFCD_DV0	= 0x0000003F,
317 	UFCD_DV1	= 0x00003F00,
318 	UFCD_DV2	= 0x003F0000,
319 	UFCD_DV3	= 0x3F000000,
320 };
321 
322 /* SFO */
323 enum SFO_BIT {
324 	SFO_FBP		= 0x0000003F,
325 };
326 
327 /* RTC */
328 enum RTC_BIT {
329 	RTC_MFL0	= 0x00000FFF,
330 	RTC_MFL1	= 0x0FFF0000,
331 };
332 
333 /* TGC */
334 enum TGC_BIT {
335 	TGC_TSM0	= 0x00000001,
336 	TGC_TSM1	= 0x00000002,
337 	TGC_TSM2	= 0x00000004,
338 	TGC_TSM3	= 0x00000008,
339 	TGC_TQP		= 0x00000030,
340 	TGC_TQP_NONAVB	= 0x00000000,
341 	TGC_TQP_AVBMODE1 = 0x00000010,
342 	TGC_TQP_AVBMODE2 = 0x00000030,
343 	TGC_TBD0	= 0x00000300,
344 	TGC_TBD1	= 0x00003000,
345 	TGC_TBD2	= 0x00030000,
346 	TGC_TBD3	= 0x00300000,
347 };
348 
349 /* TCCR */
350 enum TCCR_BIT {
351 	TCCR_TSRQ0	= 0x00000001,
352 	TCCR_TSRQ1	= 0x00000002,
353 	TCCR_TSRQ2	= 0x00000004,
354 	TCCR_TSRQ3	= 0x00000008,
355 	TCCR_TFEN	= 0x00000100,
356 	TCCR_TFR	= 0x00000200,
357 };
358 
359 /* TSR */
360 enum TSR_BIT {
361 	TSR_CCS0	= 0x00000003,
362 	TSR_CCS1	= 0x0000000C,
363 	TSR_TFFL	= 0x00000700,
364 };
365 
366 /* TFA2 */
367 enum TFA2_BIT {
368 	TFA2_TSV	= 0x0000FFFF,
369 	TFA2_TST	= 0x03FF0000,
370 };
371 
372 /* DIC */
373 enum DIC_BIT {
374 	DIC_DPE1	= 0x00000002,
375 	DIC_DPE2	= 0x00000004,
376 	DIC_DPE3	= 0x00000008,
377 	DIC_DPE4	= 0x00000010,
378 	DIC_DPE5	= 0x00000020,
379 	DIC_DPE6	= 0x00000040,
380 	DIC_DPE7	= 0x00000080,
381 	DIC_DPE8	= 0x00000100,
382 	DIC_DPE9	= 0x00000200,
383 	DIC_DPE10	= 0x00000400,
384 	DIC_DPE11	= 0x00000800,
385 	DIC_DPE12	= 0x00001000,
386 	DIC_DPE13	= 0x00002000,
387 	DIC_DPE14	= 0x00004000,
388 	DIC_DPE15	= 0x00008000,
389 };
390 
391 /* DIS */
392 enum DIS_BIT {
393 	DIS_DPF1	= 0x00000002,
394 	DIS_DPF2	= 0x00000004,
395 	DIS_DPF3	= 0x00000008,
396 	DIS_DPF4	= 0x00000010,
397 	DIS_DPF5	= 0x00000020,
398 	DIS_DPF6	= 0x00000040,
399 	DIS_DPF7	= 0x00000080,
400 	DIS_DPF8	= 0x00000100,
401 	DIS_DPF9	= 0x00000200,
402 	DIS_DPF10	= 0x00000400,
403 	DIS_DPF11	= 0x00000800,
404 	DIS_DPF12	= 0x00001000,
405 	DIS_DPF13	= 0x00002000,
406 	DIS_DPF14	= 0x00004000,
407 	DIS_DPF15	= 0x00008000,
408 };
409 
410 /* EIC */
411 enum EIC_BIT {
412 	EIC_MREE	= 0x00000001,
413 	EIC_MTEE	= 0x00000002,
414 	EIC_QEE		= 0x00000004,
415 	EIC_SEE		= 0x00000008,
416 	EIC_CLLE0	= 0x00000010,
417 	EIC_CLLE1	= 0x00000020,
418 	EIC_CULE0	= 0x00000040,
419 	EIC_CULE1	= 0x00000080,
420 	EIC_TFFE	= 0x00000100,
421 };
422 
423 /* EIS */
424 enum EIS_BIT {
425 	EIS_MREF	= 0x00000001,
426 	EIS_MTEF	= 0x00000002,
427 	EIS_QEF		= 0x00000004,
428 	EIS_SEF		= 0x00000008,
429 	EIS_CLLF0	= 0x00000010,
430 	EIS_CLLF1	= 0x00000020,
431 	EIS_CULF0	= 0x00000040,
432 	EIS_CULF1	= 0x00000080,
433 	EIS_TFFF	= 0x00000100,
434 	EIS_QFS		= 0x00010000,
435 	EIS_RESERVED	= (GENMASK(31, 17) | GENMASK(15, 11)),
436 };
437 
438 /* RIC0 */
439 enum RIC0_BIT {
440 	RIC0_FRE0	= 0x00000001,
441 	RIC0_FRE1	= 0x00000002,
442 	RIC0_FRE2	= 0x00000004,
443 	RIC0_FRE3	= 0x00000008,
444 	RIC0_FRE4	= 0x00000010,
445 	RIC0_FRE5	= 0x00000020,
446 	RIC0_FRE6	= 0x00000040,
447 	RIC0_FRE7	= 0x00000080,
448 	RIC0_FRE8	= 0x00000100,
449 	RIC0_FRE9	= 0x00000200,
450 	RIC0_FRE10	= 0x00000400,
451 	RIC0_FRE11	= 0x00000800,
452 	RIC0_FRE12	= 0x00001000,
453 	RIC0_FRE13	= 0x00002000,
454 	RIC0_FRE14	= 0x00004000,
455 	RIC0_FRE15	= 0x00008000,
456 	RIC0_FRE16	= 0x00010000,
457 	RIC0_FRE17	= 0x00020000,
458 };
459 
460 /* RIC0 */
461 enum RIS0_BIT {
462 	RIS0_FRF0	= 0x00000001,
463 	RIS0_FRF1	= 0x00000002,
464 	RIS0_FRF2	= 0x00000004,
465 	RIS0_FRF3	= 0x00000008,
466 	RIS0_FRF4	= 0x00000010,
467 	RIS0_FRF5	= 0x00000020,
468 	RIS0_FRF6	= 0x00000040,
469 	RIS0_FRF7	= 0x00000080,
470 	RIS0_FRF8	= 0x00000100,
471 	RIS0_FRF9	= 0x00000200,
472 	RIS0_FRF10	= 0x00000400,
473 	RIS0_FRF11	= 0x00000800,
474 	RIS0_FRF12	= 0x00001000,
475 	RIS0_FRF13	= 0x00002000,
476 	RIS0_FRF14	= 0x00004000,
477 	RIS0_FRF15	= 0x00008000,
478 	RIS0_FRF16	= 0x00010000,
479 	RIS0_FRF17	= 0x00020000,
480 	RIS0_RESERVED	= GENMASK(31, 18),
481 };
482 
483 /* RIC1 */
484 enum RIC1_BIT {
485 	RIC1_RFWE	= 0x80000000,
486 };
487 
488 /* RIS1 */
489 enum RIS1_BIT {
490 	RIS1_RFWF	= 0x80000000,
491 };
492 
493 /* RIC2 */
494 enum RIC2_BIT {
495 	RIC2_QFE0	= 0x00000001,
496 	RIC2_QFE1	= 0x00000002,
497 	RIC2_QFE2	= 0x00000004,
498 	RIC2_QFE3	= 0x00000008,
499 	RIC2_QFE4	= 0x00000010,
500 	RIC2_QFE5	= 0x00000020,
501 	RIC2_QFE6	= 0x00000040,
502 	RIC2_QFE7	= 0x00000080,
503 	RIC2_QFE8	= 0x00000100,
504 	RIC2_QFE9	= 0x00000200,
505 	RIC2_QFE10	= 0x00000400,
506 	RIC2_QFE11	= 0x00000800,
507 	RIC2_QFE12	= 0x00001000,
508 	RIC2_QFE13	= 0x00002000,
509 	RIC2_QFE14	= 0x00004000,
510 	RIC2_QFE15	= 0x00008000,
511 	RIC2_QFE16	= 0x00010000,
512 	RIC2_QFE17	= 0x00020000,
513 	RIC2_RFFE	= 0x80000000,
514 };
515 
516 /* RIS2 */
517 enum RIS2_BIT {
518 	RIS2_QFF0	= 0x00000001,
519 	RIS2_QFF1	= 0x00000002,
520 	RIS2_QFF2	= 0x00000004,
521 	RIS2_QFF3	= 0x00000008,
522 	RIS2_QFF4	= 0x00000010,
523 	RIS2_QFF5	= 0x00000020,
524 	RIS2_QFF6	= 0x00000040,
525 	RIS2_QFF7	= 0x00000080,
526 	RIS2_QFF8	= 0x00000100,
527 	RIS2_QFF9	= 0x00000200,
528 	RIS2_QFF10	= 0x00000400,
529 	RIS2_QFF11	= 0x00000800,
530 	RIS2_QFF12	= 0x00001000,
531 	RIS2_QFF13	= 0x00002000,
532 	RIS2_QFF14	= 0x00004000,
533 	RIS2_QFF15	= 0x00008000,
534 	RIS2_QFF16	= 0x00010000,
535 	RIS2_QFF17	= 0x00020000,
536 	RIS2_RFFF	= 0x80000000,
537 	RIS2_RESERVED	= GENMASK(30, 18),
538 };
539 
540 /* TIC */
541 enum TIC_BIT {
542 	TIC_FTE0	= 0x00000001,	/* Documented for R-Car Gen3 only */
543 	TIC_FTE1	= 0x00000002,	/* Documented for R-Car Gen3 only */
544 	TIC_TFUE	= 0x00000100,
545 	TIC_TFWE	= 0x00000200,
546 };
547 
548 /* TIS */
549 enum TIS_BIT {
550 	TIS_FTF0	= 0x00000001,	/* Documented for R-Car Gen3 only */
551 	TIS_FTF1	= 0x00000002,	/* Documented for R-Car Gen3 only */
552 	TIS_TFUF	= 0x00000100,
553 	TIS_TFWF	= 0x00000200,
554 	TIS_RESERVED	= (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))
555 };
556 
557 /* ISS */
558 enum ISS_BIT {
559 	ISS_FRS		= 0x00000001,	/* Documented for R-Car Gen3 only */
560 	ISS_FTS		= 0x00000004,	/* Documented for R-Car Gen3 only */
561 	ISS_ES		= 0x00000040,
562 	ISS_MS		= 0x00000080,
563 	ISS_TFUS	= 0x00000100,
564 	ISS_TFWS	= 0x00000200,
565 	ISS_RFWS	= 0x00001000,
566 	ISS_CGIS	= 0x00002000,
567 	ISS_DPS1	= 0x00020000,
568 	ISS_DPS2	= 0x00040000,
569 	ISS_DPS3	= 0x00080000,
570 	ISS_DPS4	= 0x00100000,
571 	ISS_DPS5	= 0x00200000,
572 	ISS_DPS6	= 0x00400000,
573 	ISS_DPS7	= 0x00800000,
574 	ISS_DPS8	= 0x01000000,
575 	ISS_DPS9	= 0x02000000,
576 	ISS_DPS10	= 0x04000000,
577 	ISS_DPS11	= 0x08000000,
578 	ISS_DPS12	= 0x10000000,
579 	ISS_DPS13	= 0x20000000,
580 	ISS_DPS14	= 0x40000000,
581 	ISS_DPS15	= 0x80000000,
582 };
583 
584 /* CIE (R-Car Gen3 only) */
585 enum CIE_BIT {
586 	CIE_CRIE	= 0x00000001,
587 	CIE_CTIE	= 0x00000100,
588 	CIE_RQFM	= 0x00010000,
589 	CIE_CL0M	= 0x00020000,
590 	CIE_RFWL	= 0x00040000,
591 	CIE_RFFL	= 0x00080000,
592 };
593 
594 /* GCCR */
595 enum GCCR_BIT {
596 	GCCR_TCR	= 0x00000003,
597 	GCCR_TCR_NOREQ	= 0x00000000, /* No request */
598 	GCCR_TCR_RESET	= 0x00000001, /* gPTP/AVTP presentation timer reset */
599 	GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */
600 	GCCR_LTO	= 0x00000004,
601 	GCCR_LTI	= 0x00000008,
602 	GCCR_LPTC	= 0x00000010,
603 	GCCR_LMTT	= 0x00000020,
604 	GCCR_TCSS	= 0x00000300,
605 	GCCR_TCSS_GPTP	= 0x00000000,	/* gPTP timer value */
606 	GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */
607 	GCCR_TCSS_AVTP	= 0x00000200,	/* AVTP presentation time value */
608 };
609 
610 /* GTI */
611 enum GTI_BIT {
612 	GTI_TIV		= 0x0FFFFFFF,
613 };
614 
615 #define GTI_TIV_MAX	GTI_TIV
616 #define GTI_TIV_MIN	0x20
617 
618 /* GIC */
619 enum GIC_BIT {
620 	GIC_PTCE	= 0x00000001,	/* Documented for R-Car Gen3 only */
621 	GIC_PTME	= 0x00000004,
622 };
623 
624 /* GIS */
625 enum GIS_BIT {
626 	GIS_PTCF	= 0x00000001,	/* Documented for R-Car Gen3 only */
627 	GIS_PTMF	= 0x00000004,
628 	GIS_RESERVED	= GENMASK(15, 10),
629 };
630 
631 /* GIE (R-Car Gen3 only) */
632 enum GIE_BIT {
633 	GIE_PTCS	= 0x00000001,
634 	GIE_PTOS	= 0x00000002,
635 	GIE_PTMS0	= 0x00000004,
636 	GIE_PTMS1	= 0x00000008,
637 	GIE_PTMS2	= 0x00000010,
638 	GIE_PTMS3	= 0x00000020,
639 	GIE_PTMS4	= 0x00000040,
640 	GIE_PTMS5	= 0x00000080,
641 	GIE_PTMS6	= 0x00000100,
642 	GIE_PTMS7	= 0x00000200,
643 	GIE_ATCS0	= 0x00010000,
644 	GIE_ATCS1	= 0x00020000,
645 	GIE_ATCS2	= 0x00040000,
646 	GIE_ATCS3	= 0x00080000,
647 	GIE_ATCS4	= 0x00100000,
648 	GIE_ATCS5	= 0x00200000,
649 	GIE_ATCS6	= 0x00400000,
650 	GIE_ATCS7	= 0x00800000,
651 	GIE_ATCS8	= 0x01000000,
652 	GIE_ATCS9	= 0x02000000,
653 	GIE_ATCS10	= 0x04000000,
654 	GIE_ATCS11	= 0x08000000,
655 	GIE_ATCS12	= 0x10000000,
656 	GIE_ATCS13	= 0x20000000,
657 	GIE_ATCS14	= 0x40000000,
658 	GIE_ATCS15	= 0x80000000,
659 };
660 
661 /* GID (R-Car Gen3 only) */
662 enum GID_BIT {
663 	GID_PTCD	= 0x00000001,
664 	GID_PTOD	= 0x00000002,
665 	GID_PTMD0	= 0x00000004,
666 	GID_PTMD1	= 0x00000008,
667 	GID_PTMD2	= 0x00000010,
668 	GID_PTMD3	= 0x00000020,
669 	GID_PTMD4	= 0x00000040,
670 	GID_PTMD5	= 0x00000080,
671 	GID_PTMD6	= 0x00000100,
672 	GID_PTMD7	= 0x00000200,
673 	GID_ATCD0	= 0x00010000,
674 	GID_ATCD1	= 0x00020000,
675 	GID_ATCD2	= 0x00040000,
676 	GID_ATCD3	= 0x00080000,
677 	GID_ATCD4	= 0x00100000,
678 	GID_ATCD5	= 0x00200000,
679 	GID_ATCD6	= 0x00400000,
680 	GID_ATCD7	= 0x00800000,
681 	GID_ATCD8	= 0x01000000,
682 	GID_ATCD9	= 0x02000000,
683 	GID_ATCD10	= 0x04000000,
684 	GID_ATCD11	= 0x08000000,
685 	GID_ATCD12	= 0x10000000,
686 	GID_ATCD13	= 0x20000000,
687 	GID_ATCD14	= 0x40000000,
688 	GID_ATCD15	= 0x80000000,
689 };
690 
691 /* RIE0 (R-Car Gen3 only) */
692 enum RIE0_BIT {
693 	RIE0_FRS0	= 0x00000001,
694 	RIE0_FRS1	= 0x00000002,
695 	RIE0_FRS2	= 0x00000004,
696 	RIE0_FRS3	= 0x00000008,
697 	RIE0_FRS4	= 0x00000010,
698 	RIE0_FRS5	= 0x00000020,
699 	RIE0_FRS6	= 0x00000040,
700 	RIE0_FRS7	= 0x00000080,
701 	RIE0_FRS8	= 0x00000100,
702 	RIE0_FRS9	= 0x00000200,
703 	RIE0_FRS10	= 0x00000400,
704 	RIE0_FRS11	= 0x00000800,
705 	RIE0_FRS12	= 0x00001000,
706 	RIE0_FRS13	= 0x00002000,
707 	RIE0_FRS14	= 0x00004000,
708 	RIE0_FRS15	= 0x00008000,
709 	RIE0_FRS16	= 0x00010000,
710 	RIE0_FRS17	= 0x00020000,
711 };
712 
713 /* RID0 (R-Car Gen3 only) */
714 enum RID0_BIT {
715 	RID0_FRD0	= 0x00000001,
716 	RID0_FRD1	= 0x00000002,
717 	RID0_FRD2	= 0x00000004,
718 	RID0_FRD3	= 0x00000008,
719 	RID0_FRD4	= 0x00000010,
720 	RID0_FRD5	= 0x00000020,
721 	RID0_FRD6	= 0x00000040,
722 	RID0_FRD7	= 0x00000080,
723 	RID0_FRD8	= 0x00000100,
724 	RID0_FRD9	= 0x00000200,
725 	RID0_FRD10	= 0x00000400,
726 	RID0_FRD11	= 0x00000800,
727 	RID0_FRD12	= 0x00001000,
728 	RID0_FRD13	= 0x00002000,
729 	RID0_FRD14	= 0x00004000,
730 	RID0_FRD15	= 0x00008000,
731 	RID0_FRD16	= 0x00010000,
732 	RID0_FRD17	= 0x00020000,
733 };
734 
735 /* RIE2 (R-Car Gen3 only) */
736 enum RIE2_BIT {
737 	RIE2_QFS0	= 0x00000001,
738 	RIE2_QFS1	= 0x00000002,
739 	RIE2_QFS2	= 0x00000004,
740 	RIE2_QFS3	= 0x00000008,
741 	RIE2_QFS4	= 0x00000010,
742 	RIE2_QFS5	= 0x00000020,
743 	RIE2_QFS6	= 0x00000040,
744 	RIE2_QFS7	= 0x00000080,
745 	RIE2_QFS8	= 0x00000100,
746 	RIE2_QFS9	= 0x00000200,
747 	RIE2_QFS10	= 0x00000400,
748 	RIE2_QFS11	= 0x00000800,
749 	RIE2_QFS12	= 0x00001000,
750 	RIE2_QFS13	= 0x00002000,
751 	RIE2_QFS14	= 0x00004000,
752 	RIE2_QFS15	= 0x00008000,
753 	RIE2_QFS16	= 0x00010000,
754 	RIE2_QFS17	= 0x00020000,
755 	RIE2_RFFS	= 0x80000000,
756 };
757 
758 /* RID2 (R-Car Gen3 only) */
759 enum RID2_BIT {
760 	RID2_QFD0	= 0x00000001,
761 	RID2_QFD1	= 0x00000002,
762 	RID2_QFD2	= 0x00000004,
763 	RID2_QFD3	= 0x00000008,
764 	RID2_QFD4	= 0x00000010,
765 	RID2_QFD5	= 0x00000020,
766 	RID2_QFD6	= 0x00000040,
767 	RID2_QFD7	= 0x00000080,
768 	RID2_QFD8	= 0x00000100,
769 	RID2_QFD9	= 0x00000200,
770 	RID2_QFD10	= 0x00000400,
771 	RID2_QFD11	= 0x00000800,
772 	RID2_QFD12	= 0x00001000,
773 	RID2_QFD13	= 0x00002000,
774 	RID2_QFD14	= 0x00004000,
775 	RID2_QFD15	= 0x00008000,
776 	RID2_QFD16	= 0x00010000,
777 	RID2_QFD17	= 0x00020000,
778 	RID2_RFFD	= 0x80000000,
779 };
780 
781 /* TIE (R-Car Gen3 only) */
782 enum TIE_BIT {
783 	TIE_FTS0	= 0x00000001,
784 	TIE_FTS1	= 0x00000002,
785 	TIE_FTS2	= 0x00000004,
786 	TIE_FTS3	= 0x00000008,
787 	TIE_TFUS	= 0x00000100,
788 	TIE_TFWS	= 0x00000200,
789 	TIE_MFUS	= 0x00000400,
790 	TIE_MFWS	= 0x00000800,
791 	TIE_TDPS0	= 0x00010000,
792 	TIE_TDPS1	= 0x00020000,
793 	TIE_TDPS2	= 0x00040000,
794 	TIE_TDPS3	= 0x00080000,
795 };
796 
797 /* TID (R-Car Gen3 only) */
798 enum TID_BIT {
799 	TID_FTD0	= 0x00000001,
800 	TID_FTD1	= 0x00000002,
801 	TID_FTD2	= 0x00000004,
802 	TID_FTD3	= 0x00000008,
803 	TID_TFUD	= 0x00000100,
804 	TID_TFWD	= 0x00000200,
805 	TID_MFUD	= 0x00000400,
806 	TID_MFWD	= 0x00000800,
807 	TID_TDPD0	= 0x00010000,
808 	TID_TDPD1	= 0x00020000,
809 	TID_TDPD2	= 0x00040000,
810 	TID_TDPD3	= 0x00080000,
811 };
812 
813 /* ECMR */
814 enum ECMR_BIT {
815 	ECMR_PRM	= 0x00000001,
816 	ECMR_DM		= 0x00000002,
817 	ECMR_TE		= 0x00000020,
818 	ECMR_RE		= 0x00000040,
819 	ECMR_MPDE	= 0x00000200,
820 	ECMR_TXF	= 0x00010000,	/* Documented for R-Car Gen3 only */
821 	ECMR_RXF	= 0x00020000,
822 	ECMR_PFR	= 0x00040000,
823 	ECMR_ZPF	= 0x00080000,	/* Documented for R-Car Gen3 and RZ/G2L */
824 	ECMR_RZPF	= 0x00100000,
825 	ECMR_DPAD	= 0x00200000,
826 	ECMR_RCSC	= 0x00800000,
827 	ECMR_RCPT	= 0x02000000,	/* Documented for RZ/G2L only */
828 	ECMR_TRCCM	= 0x04000000,
829 };
830 
831 /* ECSR */
832 enum ECSR_BIT {
833 	ECSR_ICD	= 0x00000001,
834 	ECSR_MPD	= 0x00000002,
835 	ECSR_LCHNG	= 0x00000004,
836 	ECSR_PHYI	= 0x00000008,
837 	ECSR_PFRI	= 0x00000010,	/* Documented for R-Car Gen3 and RZ/G2L */
838 };
839 
840 /* ECSIPR */
841 enum ECSIPR_BIT {
842 	ECSIPR_ICDIP	= 0x00000001,
843 	ECSIPR_MPDIP	= 0x00000002,
844 	ECSIPR_LCHNGIP	= 0x00000004,
845 };
846 
847 /* PIR */
848 enum PIR_BIT {
849 	PIR_MDC		= 0x00000001,
850 	PIR_MMD		= 0x00000002,
851 	PIR_MDO		= 0x00000004,
852 	PIR_MDI		= 0x00000008,
853 };
854 
855 /* PSR */
856 enum PSR_BIT {
857 	PSR_LMON	= 0x00000001,
858 };
859 
860 /* PIPR */
861 enum PIPR_BIT {
862 	PIPR_PHYIP	= 0x00000001,
863 };
864 
865 /* MPR */
866 enum MPR_BIT {
867 	MPR_MP		= 0x0000ffff,
868 };
869 
870 /* GECMR */
871 enum GECMR_BIT {
872 	GECMR_SPEED		= 0x00000001,
873 	GECMR_SPEED_100		= 0x00000000,
874 	GECMR_SPEED_1000	= 0x00000001,
875 	GBETH_GECMR_SPEED	= 0x00000030,
876 	GBETH_GECMR_SPEED_10	= 0x00000000,
877 	GBETH_GECMR_SPEED_100	= 0x00000010,
878 	GBETH_GECMR_SPEED_1000	= 0x00000020,
879 };
880 
881 /* The Ethernet AVB descriptor definitions. */
882 struct ravb_desc {
883 	__le16 ds;	/* Descriptor size */
884 	u8 cc;		/* Content control MSBs (reserved) */
885 	u8 die_dt;	/* Descriptor interrupt enable and type */
886 	__le32 dptr;	/* Descriptor pointer */
887 };
888 
889 #define DPTR_ALIGN	4	/* Required descriptor pointer alignment */
890 
891 enum DIE_DT {
892 	/* Frame data */
893 	DT_FMID		= 0x40,
894 	DT_FSTART	= 0x50,
895 	DT_FEND		= 0x60,
896 	DT_FSINGLE	= 0x70,
897 	/* Chain control */
898 	DT_LINK		= 0x80,
899 	DT_LINKFIX	= 0x90,
900 	DT_EOS		= 0xa0,
901 	/* HW/SW arbitration */
902 	DT_FEMPTY	= 0xc0,
903 	DT_FEMPTY_IS	= 0xd0,
904 	DT_FEMPTY_IC	= 0xe0,
905 	DT_FEMPTY_ND	= 0xf0,
906 	DT_LEMPTY	= 0x20,
907 	DT_EEMPTY	= 0x30,
908 };
909 
910 struct ravb_rx_desc {
911 	__le16 ds_cc;	/* Descriptor size and content control LSBs */
912 	u8 msc;		/* MAC status code */
913 	u8 die_dt;	/* Descriptor interrupt enable and type */
914 	__le32 dptr;	/* Descpriptor pointer */
915 };
916 
917 struct ravb_ex_rx_desc {
918 	__le16 ds_cc;	/* Descriptor size and content control lower bits */
919 	u8 msc;		/* MAC status code */
920 	u8 die_dt;	/* Descriptor interrupt enable and type */
921 	__le32 dptr;	/* Descpriptor pointer */
922 	__le32 ts_n;	/* Timestampe nsec */
923 	__le32 ts_sl;	/* Timestamp low */
924 	__le16 ts_sh;	/* Timestamp high */
925 	__le16 res;	/* Reserved bits */
926 };
927 
928 enum RX_DS_CC_BIT {
929 	RX_DS		= 0x0fff, /* Data size */
930 	RX_TR		= 0x1000, /* Truncation indication */
931 	RX_EI		= 0x2000, /* Error indication */
932 	RX_PS		= 0xc000, /* Padding selection */
933 };
934 
935 /* E-MAC status code */
936 enum MSC_BIT {
937 	MSC_CRC		= 0x01, /* Frame CRC error */
938 	MSC_RFE		= 0x02, /* Frame reception error (flagged by PHY) */
939 	MSC_RTSF	= 0x04, /* Frame length error (frame too short) */
940 	MSC_RTLF	= 0x08, /* Frame length error (frame too long) */
941 	MSC_FRE		= 0x10, /* Fraction error (not a multiple of 8 bits) */
942 	MSC_CRL		= 0x20, /* Carrier lost */
943 	MSC_CEEF	= 0x40, /* Carrier extension error */
944 	MSC_MC		= 0x80, /* Multicast frame reception */
945 };
946 
947 struct ravb_tx_desc {
948 	__le16 ds_tagl;	/* Descriptor size and frame tag LSBs */
949 	u8 tagh_tsr;	/* Frame tag MSBs and timestamp storage request bit */
950 	u8 die_dt;	/* Descriptor interrupt enable and type */
951 	__le32 dptr;	/* Descpriptor pointer */
952 };
953 
954 enum TX_DS_TAGL_BIT {
955 	TX_DS		= 0x0fff, /* Data size */
956 	TX_TAGL		= 0xf000, /* Frame tag LSBs */
957 };
958 
959 enum TX_TAGH_TSR_BIT {
960 	TX_TAGH		= 0x3f, /* Frame tag MSBs */
961 	TX_TSR		= 0x40, /* Timestamp storage request */
962 };
963 enum RAVB_QUEUE {
964 	RAVB_BE = 0,	/* Best Effort Queue */
965 	RAVB_NC,	/* Network Control Queue */
966 };
967 
968 enum CXR31_BIT {
969 	CXR31_SEL_LINK0	= 0x00000001,
970 	CXR31_SEL_LINK1	= 0x00000008,
971 };
972 
973 enum CXR35_BIT {
974 	CXR35_SEL_XMII		= 0x00000003,
975 	CXR35_SEL_XMII_RGMII	= 0x00000000,
976 	CXR35_SEL_XMII_MII	= 0x00000002,
977 	CXR35_HALFCYC_CLKSW	= 0xffff0000,
978 };
979 
980 enum CSR0_BIT {
981 	CSR0_TPE	= 0x00000010,
982 	CSR0_RPE	= 0x00000020,
983 };
984 
985 enum CSR1_BIT {
986 	CSR1_TIP4	= 0x00000001,
987 	CSR1_TTCP4	= 0x00000010,
988 	CSR1_TUDP4	= 0x00000020,
989 	CSR1_TICMP4	= 0x00000040,
990 	CSR1_TTCP6	= 0x00100000,
991 	CSR1_TUDP6	= 0x00200000,
992 	CSR1_TICMP6	= 0x00400000,
993 	CSR1_THOP	= 0x01000000,
994 	CSR1_TROUT	= 0x02000000,
995 	CSR1_TAHD	= 0x04000000,
996 	CSR1_TDHD	= 0x08000000,
997 };
998 
999 enum CSR2_BIT {
1000 	CSR2_RIP4	= 0x00000001,
1001 	CSR2_RTCP4	= 0x00000010,
1002 	CSR2_RUDP4	= 0x00000020,
1003 	CSR2_RICMP4	= 0x00000040,
1004 	CSR2_RTCP6	= 0x00100000,
1005 	CSR2_RUDP6	= 0x00200000,
1006 	CSR2_RICMP6	= 0x00400000,
1007 	CSR2_RHOP	= 0x01000000,
1008 	CSR2_RROUT	= 0x02000000,
1009 	CSR2_RAHD	= 0x04000000,
1010 	CSR2_RDHD	= 0x08000000,
1011 };
1012 
1013 #define DBAT_ENTRY_NUM	22
1014 #define RX_QUEUE_OFFSET	4
1015 #define NUM_RX_QUEUE	2
1016 #define NUM_TX_QUEUE	2
1017 
1018 struct ravb_tstamp_skb {
1019 	struct list_head list;
1020 	struct sk_buff *skb;
1021 	u16 tag;
1022 };
1023 
1024 struct ravb_ptp_perout {
1025 	u32 target;
1026 	u32 period;
1027 };
1028 
1029 #define N_EXT_TS	1
1030 #define N_PER_OUT	1
1031 
1032 struct ravb_ptp {
1033 	struct ptp_clock *clock;
1034 	struct ptp_clock_info info;
1035 	u32 default_addend;
1036 	u32 current_addend;
1037 	int extts[N_EXT_TS];
1038 	struct ravb_ptp_perout perout[N_PER_OUT];
1039 };
1040 
1041 struct ravb_hw_info {
1042 	bool (*receive)(struct net_device *ndev, int *quota, int q);
1043 	void (*set_rate)(struct net_device *ndev);
1044 	int (*set_feature)(struct net_device *ndev, netdev_features_t features);
1045 	int (*dmac_init)(struct net_device *ndev);
1046 	void (*emac_init)(struct net_device *ndev);
1047 	const char (*gstrings_stats)[ETH_GSTRING_LEN];
1048 	size_t gstrings_size;
1049 	netdev_features_t net_hw_features;
1050 	netdev_features_t net_features;
1051 	int stats_len;
1052 	u32 tccr_mask;
1053 	u32 rx_max_frame_size;
1054 	u32 rx_max_desc_use;
1055 	u32 rx_desc_size;
1056 	unsigned aligned_tx: 1;
1057 
1058 	/* hardware features */
1059 	unsigned internal_delay:1;	/* AVB-DMAC has internal delays */
1060 	unsigned tx_counters:1;		/* E-MAC has TX counters */
1061 	unsigned carrier_counters:1;	/* E-MAC has carrier counters */
1062 	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple irqs */
1063 	unsigned irq_en_dis:1;		/* Has separate irq enable and disable regs */
1064 	unsigned err_mgmt_irqs:1;	/* Line1 (Err) and Line2 (Mgmt) irqs are separate */
1065 	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
1066 	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
1067 	unsigned gptp_ref_clk:1;	/* gPTP has separate reference clock */
1068 	unsigned nc_queues:1;		/* AVB-DMAC has RX and TX NC queues */
1069 	unsigned magic_pkt:1;		/* E-MAC supports magic packet detection */
1070 	unsigned half_duplex:1;		/* E-MAC supports half duplex mode */
1071 };
1072 
1073 struct ravb_private {
1074 	struct net_device *ndev;
1075 	struct platform_device *pdev;
1076 	void __iomem *addr;
1077 	struct clk *clk;
1078 	struct clk *refclk;
1079 	struct clk *gptp_clk;
1080 	struct mdiobb_ctrl mdiobb;
1081 	u32 num_rx_ring[NUM_RX_QUEUE];
1082 	u32 num_tx_ring[NUM_TX_QUEUE];
1083 	u32 desc_bat_size;
1084 	dma_addr_t desc_bat_dma;
1085 	struct ravb_desc *desc_bat;
1086 	dma_addr_t rx_desc_dma[NUM_RX_QUEUE];
1087 	dma_addr_t tx_desc_dma[NUM_TX_QUEUE];
1088 	union {
1089 		struct ravb_rx_desc *desc;
1090 		struct ravb_ex_rx_desc *ex_desc;
1091 		void *raw;
1092 	} rx_ring[NUM_RX_QUEUE];
1093 	struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE];
1094 	void *tx_align[NUM_TX_QUEUE];
1095 	struct sk_buff *rx_1st_skb;
1096 	struct sk_buff **rx_skb[NUM_RX_QUEUE];
1097 	struct sk_buff **tx_skb[NUM_TX_QUEUE];
1098 	u32 rx_over_errors;
1099 	u32 rx_fifo_errors;
1100 	struct net_device_stats stats[NUM_RX_QUEUE];
1101 	u32 tstamp_tx_ctrl;
1102 	u32 tstamp_rx_ctrl;
1103 	struct list_head ts_skb_list;
1104 	u32 ts_skb_tag;
1105 	struct ravb_ptp ptp;
1106 	spinlock_t lock;		/* Register access lock */
1107 	u32 cur_rx[NUM_RX_QUEUE];	/* Consumer ring indices */
1108 	u32 dirty_rx[NUM_RX_QUEUE];	/* Producer ring indices */
1109 	u32 cur_tx[NUM_TX_QUEUE];
1110 	u32 dirty_tx[NUM_TX_QUEUE];
1111 	struct napi_struct napi[NUM_RX_QUEUE];
1112 	struct work_struct work;
1113 	/* MII transceiver section. */
1114 	struct mii_bus *mii_bus;	/* MDIO bus control */
1115 	int link;
1116 	phy_interface_t phy_interface;
1117 	int msg_enable;
1118 	int speed;
1119 	int emac_irq;
1120 
1121 	unsigned no_avb_link:1;
1122 	unsigned avb_link_active_low:1;
1123 	unsigned wol_enabled:1;
1124 	unsigned rxcidm:1;		/* RX Clock Internal Delay Mode */
1125 	unsigned txcidm:1;		/* TX Clock Internal Delay Mode */
1126 	unsigned rgmii_override:1;	/* Deprecated rgmii-*id behavior */
1127 	unsigned int num_tx_desc;	/* TX descriptors per packet */
1128 
1129 	int duplex;
1130 
1131 	const struct ravb_hw_info *info;
1132 	struct reset_control *rstc;
1133 
1134 	u32 gti_tiv;
1135 };
1136 
1137 static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
1138 {
1139 	struct ravb_private *priv = netdev_priv(ndev);
1140 
1141 	return ioread32(priv->addr + reg);
1142 }
1143 
1144 static inline void ravb_write(struct net_device *ndev, u32 data,
1145 			      enum ravb_reg reg)
1146 {
1147 	struct ravb_private *priv = netdev_priv(ndev);
1148 
1149 	iowrite32(data, priv->addr + reg);
1150 }
1151 
1152 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
1153 		 u32 set);
1154 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
1155 
1156 void ravb_ptp_interrupt(struct net_device *ndev);
1157 void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev);
1158 void ravb_ptp_stop(struct net_device *ndev);
1159 
1160 #endif	/* #ifndef __RAVB_H__ */
1161