xref: /linux/drivers/net/ethernet/renesas/ravb.h (revision 661fb4e68cf62bf52eacfcd9b3b0d93fe4260c5b) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Renesas Ethernet AVB device driver
3  *
4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
5  * Copyright (C) 2015 Renesas Solutions Corp.
6  * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7  *
8  * Based on the SuperH Ethernet driver
9  */
10 
11 #ifndef __RAVB_H__
12 #define __RAVB_H__
13 
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/kernel.h>
17 #include <linux/mdio-bitbang.h>
18 #include <linux/netdevice.h>
19 #include <linux/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/ptp_clock_kernel.h>
22 #include <net/page_pool/types.h>
23 
24 #define BE_TX_RING_SIZE	64	/* TX ring size for Best Effort */
25 #define BE_RX_RING_SIZE	1024	/* RX ring size for Best Effort */
26 #define NC_TX_RING_SIZE	64	/* TX ring size for Network Control */
27 #define NC_RX_RING_SIZE	64	/* RX ring size for Network Control */
28 #define BE_TX_RING_MIN	64
29 #define BE_RX_RING_MIN	64
30 #define BE_TX_RING_MAX	1024
31 #define BE_RX_RING_MAX	2048
32 
33 #define PKT_BUF_SZ	1538
34 
35 /* Driver's parameters */
36 #define RAVB_ALIGN	128
37 
38 /* Hardware time stamp */
39 #define RAVB_TXTSTAMP_VALID	0x00000001	/* TX timestamp valid */
40 #define RAVB_TXTSTAMP_ENABLED	0x00000010	/* Enable TX timestamping */
41 
42 #define RAVB_RXTSTAMP_VALID	0x00000001	/* RX timestamp valid */
43 #define RAVB_RXTSTAMP_TYPE	0x00000006	/* RX type mask */
44 #define RAVB_RXTSTAMP_TYPE_V2_L2_EVENT 0x00000002
45 #define RAVB_RXTSTAMP_TYPE_ALL	0x00000006
46 #define RAVB_RXTSTAMP_ENABLED	0x00000010	/* Enable RX timestamping */
47 
48 enum ravb_reg {
49 	/* AVB-DMAC registers */
50 	CCC	= 0x0000,
51 	DBAT	= 0x0004,
52 	DLR	= 0x0008,
53 	CSR	= 0x000C,
54 	CDAR0	= 0x0010,
55 	CDAR1	= 0x0014,
56 	CDAR2	= 0x0018,
57 	CDAR3	= 0x001C,
58 	CDAR4	= 0x0020,
59 	CDAR5	= 0x0024,
60 	CDAR6	= 0x0028,
61 	CDAR7	= 0x002C,
62 	CDAR8	= 0x0030,
63 	CDAR9	= 0x0034,
64 	CDAR10	= 0x0038,
65 	CDAR11	= 0x003C,
66 	CDAR12	= 0x0040,
67 	CDAR13	= 0x0044,
68 	CDAR14	= 0x0048,
69 	CDAR15	= 0x004C,
70 	CDAR16	= 0x0050,
71 	CDAR17	= 0x0054,
72 	CDAR18	= 0x0058,
73 	CDAR19	= 0x005C,
74 	CDAR20	= 0x0060,
75 	CDAR21	= 0x0064,
76 	ESR	= 0x0088,
77 	APSR	= 0x008C,	/* R-Car Gen3 only */
78 	RCR	= 0x0090,
79 	RQC0	= 0x0094,
80 	RQC1	= 0x0098,
81 	RQC2	= 0x009C,
82 	RQC3	= 0x00A0,
83 	RQC4	= 0x00A4,
84 	RPC	= 0x00B0,
85 	RTC	= 0x00B4,	/* R-Car Gen3 and RZ/G2L only */
86 	UFCW	= 0x00BC,
87 	UFCS	= 0x00C0,
88 	UFCV0	= 0x00C4,
89 	UFCV1	= 0x00C8,
90 	UFCV2	= 0x00CC,
91 	UFCV3	= 0x00D0,
92 	UFCV4	= 0x00D4,
93 	UFCD0	= 0x00E0,
94 	UFCD1	= 0x00E4,
95 	UFCD2	= 0x00E8,
96 	UFCD3	= 0x00EC,
97 	UFCD4	= 0x00F0,
98 	SFO	= 0x00FC,
99 	SFP0	= 0x0100,
100 	SFP1	= 0x0104,
101 	SFP2	= 0x0108,
102 	SFP3	= 0x010C,
103 	SFP4	= 0x0110,
104 	SFP5	= 0x0114,
105 	SFP6	= 0x0118,
106 	SFP7	= 0x011C,
107 	SFP8	= 0x0120,
108 	SFP9	= 0x0124,
109 	SFP10	= 0x0128,
110 	SFP11	= 0x012C,
111 	SFP12	= 0x0130,
112 	SFP13	= 0x0134,
113 	SFP14	= 0x0138,
114 	SFP15	= 0x013C,
115 	SFP16	= 0x0140,
116 	SFP17	= 0x0144,
117 	SFP18	= 0x0148,
118 	SFP19	= 0x014C,
119 	SFP20	= 0x0150,
120 	SFP21	= 0x0154,
121 	SFP22	= 0x0158,
122 	SFP23	= 0x015C,
123 	SFP24	= 0x0160,
124 	SFP25	= 0x0164,
125 	SFP26	= 0x0168,
126 	SFP27	= 0x016C,
127 	SFP28	= 0x0170,
128 	SFP29	= 0x0174,
129 	SFP30	= 0x0178,
130 	SFP31	= 0x017C,
131 	SFM0	= 0x01C0,
132 	SFM1	= 0x01C4,
133 	TGC	= 0x0300,
134 	TCCR	= 0x0304,
135 	TSR	= 0x0308,
136 	TFA0	= 0x0310,
137 	TFA1	= 0x0314,
138 	TFA2	= 0x0318,
139 	CIVR0	= 0x0320,
140 	CIVR1	= 0x0324,
141 	CDVR0	= 0x0328,
142 	CDVR1	= 0x032C,
143 	CUL0	= 0x0330,
144 	CUL1	= 0x0334,
145 	CLL0	= 0x0338,
146 	CLL1	= 0x033C,
147 	DIC	= 0x0350,
148 	DIS	= 0x0354,
149 	EIC	= 0x0358,
150 	EIS	= 0x035C,
151 	RIC0	= 0x0360,
152 	RIS0	= 0x0364,
153 	RIC1	= 0x0368,
154 	RIS1	= 0x036C,
155 	RIC2	= 0x0370,
156 	RIS2	= 0x0374,
157 	TIC	= 0x0378,
158 	TIS	= 0x037C,
159 	ISS	= 0x0380,
160 	CIE	= 0x0384,	/* R-Car Gen3 only */
161 	GCCR	= 0x0390,
162 	GMTT	= 0x0394,
163 	GPTC	= 0x0398,
164 	GTI	= 0x039C,
165 	GTO0	= 0x03A0,
166 	GTO1	= 0x03A4,
167 	GTO2	= 0x03A8,
168 	GIC	= 0x03AC,
169 	GIS	= 0x03B0,
170 	GCPT	= 0x03B4,	/* Documented for R-Car Gen3 only */
171 	GCT0	= 0x03B8,
172 	GCT1	= 0x03BC,
173 	GCT2	= 0x03C0,
174 	GIE	= 0x03CC,	/* R-Car Gen3 only */
175 	GID	= 0x03D0,	/* R-Car Gen3 only */
176 	DIL	= 0x0440,	/* R-Car Gen3 only */
177 	RIE0	= 0x0460,	/* R-Car Gen3 only */
178 	RID0	= 0x0464,	/* R-Car Gen3 only */
179 	RIE2	= 0x0470,	/* R-Car Gen3 only */
180 	RID2	= 0x0474,	/* R-Car Gen3 only */
181 	TIE	= 0x0478,	/* R-Car Gen3 only */
182 	TID	= 0x047c,	/* R-Car Gen3 only */
183 
184 	/* E-MAC registers */
185 	ECMR	= 0x0500,
186 	RFLR	= 0x0508,
187 	ECSR	= 0x0510,
188 	ECSIPR	= 0x0518,
189 	PIR	= 0x0520,
190 	PSR	= 0x0528,
191 	PIPR	= 0x052c,
192 	CXR31	= 0x0530,	/* RZ/G2L only */
193 	CXR35	= 0x0540,	/* RZ/G2L only */
194 	MPR	= 0x0558,
195 	PFTCR	= 0x055c,
196 	PFRCR	= 0x0560,
197 	GECMR	= 0x05b0,
198 	MAHR	= 0x05c0,
199 	MALR	= 0x05c8,
200 	TROCR	= 0x0700,	/* R-Car Gen3 and RZ/G2L only */
201 	CXR41	= 0x0708,	/* RZ/G2L only */
202 	CXR42	= 0x0710,	/* RZ/G2L only */
203 	CEFCR	= 0x0740,
204 	FRECR	= 0x0748,
205 	TSFRCR	= 0x0750,
206 	TLFRCR	= 0x0758,
207 	RFCR	= 0x0760,
208 	MAFCR	= 0x0778,
209 
210 	/* TOE registers (RZ/G2L only) */
211 	CSR0    = 0x0800,
212 	CSR1    = 0x0804,
213 	CSR2    = 0x0808,
214 };
215 
216 
217 /* Register bits of the Ethernet AVB */
218 /* CCC */
219 enum CCC_BIT {
220 	CCC_OPC		= 0x00000003,
221 	CCC_OPC_RESET	= 0x00000000,
222 	CCC_OPC_CONFIG	= 0x00000001,
223 	CCC_OPC_OPERATION = 0x00000002,
224 	CCC_GAC		= 0x00000080,
225 	CCC_DTSR	= 0x00000100,
226 	CCC_CSEL	= 0x00030000,
227 	CCC_CSEL_HPB	= 0x00010000,
228 	CCC_CSEL_ETH_TX	= 0x00020000,
229 	CCC_CSEL_GMII_REF = 0x00030000,
230 	CCC_LBME	= 0x01000000,
231 };
232 
233 /* CSR */
234 enum CSR_BIT {
235 	CSR_OPS		= 0x0000000F,
236 	CSR_OPS_RESET	= 0x00000001,
237 	CSR_OPS_CONFIG	= 0x00000002,
238 	CSR_OPS_OPERATION = 0x00000004,
239 	CSR_OPS_STANDBY	= 0x00000008,	/* Documented for R-Car Gen3 only */
240 	CSR_DTS		= 0x00000100,
241 	CSR_TPO0	= 0x00010000,
242 	CSR_TPO1	= 0x00020000,
243 	CSR_TPO2	= 0x00040000,
244 	CSR_TPO3	= 0x00080000,
245 	CSR_RPO		= 0x00100000,
246 };
247 
248 /* ESR */
249 enum ESR_BIT {
250 	ESR_EQN		= 0x0000001F,
251 	ESR_ET		= 0x00000F00,
252 	ESR_EIL		= 0x00001000,
253 };
254 
255 /* APSR (R-Car Gen3 only) */
256 enum APSR_BIT {
257 	APSR_MEMS	= 0x00000002,	/* Undocumented */
258 	APSR_CMSW	= 0x00000010,
259 	APSR_RDM	= 0x00002000,
260 	APSR_TDM	= 0x00004000,
261 	APSR_MIISELECT	= 0x01000000,	/* R-Car V4M only */
262 };
263 
264 /* RCR */
265 enum RCR_BIT {
266 	RCR_EFFS	= 0x00000001,
267 	RCR_ENCF	= 0x00000002,
268 	RCR_ESF		= 0x0000000C,
269 	RCR_ETS0	= 0x00000010,
270 	RCR_ETS2	= 0x00000020,
271 	RCR_RFCL	= 0x1FFF0000,
272 };
273 
274 /* RQC0/1/2/3/4 */
275 enum RQC_BIT {
276 	RQC_RSM0	= 0x00000003,
277 	RQC_UFCC0	= 0x00000030,
278 	RQC_RSM1	= 0x00000300,
279 	RQC_UFCC1	= 0x00003000,
280 	RQC_RSM2	= 0x00030000,
281 	RQC_UFCC2	= 0x00300000,
282 	RQC_RSM3	= 0x03000000,
283 	RQC_UFCC3	= 0x30000000,
284 };
285 
286 /* RPC */
287 enum RPC_BIT {
288 	RPC_PCNT	= 0x00000700,
289 	RPC_DCNT	= 0x00FF0000,
290 };
291 
292 /* UFCW */
293 enum UFCW_BIT {
294 	UFCW_WL0	= 0x0000003F,
295 	UFCW_WL1	= 0x00003F00,
296 	UFCW_WL2	= 0x003F0000,
297 	UFCW_WL3	= 0x3F000000,
298 };
299 
300 /* UFCS */
301 enum UFCS_BIT {
302 	UFCS_SL0	= 0x0000003F,
303 	UFCS_SL1	= 0x00003F00,
304 	UFCS_SL2	= 0x003F0000,
305 	UFCS_SL3	= 0x3F000000,
306 };
307 
308 /* UFCV0/1/2/3/4 */
309 enum UFCV_BIT {
310 	UFCV_CV0	= 0x0000003F,
311 	UFCV_CV1	= 0x00003F00,
312 	UFCV_CV2	= 0x003F0000,
313 	UFCV_CV3	= 0x3F000000,
314 };
315 
316 /* UFCD0/1/2/3/4 */
317 enum UFCD_BIT {
318 	UFCD_DV0	= 0x0000003F,
319 	UFCD_DV1	= 0x00003F00,
320 	UFCD_DV2	= 0x003F0000,
321 	UFCD_DV3	= 0x3F000000,
322 };
323 
324 /* SFO */
325 enum SFO_BIT {
326 	SFO_FBP		= 0x0000003F,
327 };
328 
329 /* RTC */
330 enum RTC_BIT {
331 	RTC_MFL0	= 0x00000FFF,
332 	RTC_MFL1	= 0x0FFF0000,
333 };
334 
335 /* TGC */
336 enum TGC_BIT {
337 	TGC_TSM0	= 0x00000001,
338 	TGC_TSM1	= 0x00000002,
339 	TGC_TSM2	= 0x00000004,
340 	TGC_TSM3	= 0x00000008,
341 	TGC_TQP		= 0x00000030,
342 	TGC_TQP_NONAVB	= 0x00000000,
343 	TGC_TQP_AVBMODE1 = 0x00000010,
344 	TGC_TQP_AVBMODE2 = 0x00000030,
345 	TGC_TBD0	= 0x00000300,
346 	TGC_TBD1	= 0x00003000,
347 	TGC_TBD2	= 0x00030000,
348 	TGC_TBD3	= 0x00300000,
349 };
350 
351 /* TCCR */
352 enum TCCR_BIT {
353 	TCCR_TSRQ0	= 0x00000001,
354 	TCCR_TSRQ1	= 0x00000002,
355 	TCCR_TSRQ2	= 0x00000004,
356 	TCCR_TSRQ3	= 0x00000008,
357 	TCCR_TFEN	= 0x00000100,
358 	TCCR_TFR	= 0x00000200,
359 };
360 
361 /* TSR */
362 enum TSR_BIT {
363 	TSR_CCS0	= 0x00000003,
364 	TSR_CCS1	= 0x0000000C,
365 	TSR_TFFL	= 0x00000700,
366 };
367 
368 /* TFA2 */
369 enum TFA2_BIT {
370 	TFA2_TSV	= 0x0000FFFF,
371 	TFA2_TST	= 0x03FF0000,
372 };
373 
374 /* DIC */
375 enum DIC_BIT {
376 	DIC_DPE1	= 0x00000002,
377 	DIC_DPE2	= 0x00000004,
378 	DIC_DPE3	= 0x00000008,
379 	DIC_DPE4	= 0x00000010,
380 	DIC_DPE5	= 0x00000020,
381 	DIC_DPE6	= 0x00000040,
382 	DIC_DPE7	= 0x00000080,
383 	DIC_DPE8	= 0x00000100,
384 	DIC_DPE9	= 0x00000200,
385 	DIC_DPE10	= 0x00000400,
386 	DIC_DPE11	= 0x00000800,
387 	DIC_DPE12	= 0x00001000,
388 	DIC_DPE13	= 0x00002000,
389 	DIC_DPE14	= 0x00004000,
390 	DIC_DPE15	= 0x00008000,
391 };
392 
393 /* DIS */
394 enum DIS_BIT {
395 	DIS_DPF1	= 0x00000002,
396 	DIS_DPF2	= 0x00000004,
397 	DIS_DPF3	= 0x00000008,
398 	DIS_DPF4	= 0x00000010,
399 	DIS_DPF5	= 0x00000020,
400 	DIS_DPF6	= 0x00000040,
401 	DIS_DPF7	= 0x00000080,
402 	DIS_DPF8	= 0x00000100,
403 	DIS_DPF9	= 0x00000200,
404 	DIS_DPF10	= 0x00000400,
405 	DIS_DPF11	= 0x00000800,
406 	DIS_DPF12	= 0x00001000,
407 	DIS_DPF13	= 0x00002000,
408 	DIS_DPF14	= 0x00004000,
409 	DIS_DPF15	= 0x00008000,
410 };
411 
412 /* EIC */
413 enum EIC_BIT {
414 	EIC_MREE	= 0x00000001,
415 	EIC_MTEE	= 0x00000002,
416 	EIC_QEE		= 0x00000004,
417 	EIC_SEE		= 0x00000008,
418 	EIC_CLLE0	= 0x00000010,
419 	EIC_CLLE1	= 0x00000020,
420 	EIC_CULE0	= 0x00000040,
421 	EIC_CULE1	= 0x00000080,
422 	EIC_TFFE	= 0x00000100,
423 };
424 
425 /* EIS */
426 enum EIS_BIT {
427 	EIS_MREF	= 0x00000001,
428 	EIS_MTEF	= 0x00000002,
429 	EIS_QEF		= 0x00000004,
430 	EIS_SEF		= 0x00000008,
431 	EIS_CLLF0	= 0x00000010,
432 	EIS_CLLF1	= 0x00000020,
433 	EIS_CULF0	= 0x00000040,
434 	EIS_CULF1	= 0x00000080,
435 	EIS_TFFF	= 0x00000100,
436 	EIS_QFS		= 0x00010000,
437 	EIS_RESERVED	= (GENMASK(31, 17) | GENMASK(15, 11)),
438 };
439 
440 /* RIC0 */
441 enum RIC0_BIT {
442 	RIC0_FRE0	= 0x00000001,
443 	RIC0_FRE1	= 0x00000002,
444 	RIC0_FRE2	= 0x00000004,
445 	RIC0_FRE3	= 0x00000008,
446 	RIC0_FRE4	= 0x00000010,
447 	RIC0_FRE5	= 0x00000020,
448 	RIC0_FRE6	= 0x00000040,
449 	RIC0_FRE7	= 0x00000080,
450 	RIC0_FRE8	= 0x00000100,
451 	RIC0_FRE9	= 0x00000200,
452 	RIC0_FRE10	= 0x00000400,
453 	RIC0_FRE11	= 0x00000800,
454 	RIC0_FRE12	= 0x00001000,
455 	RIC0_FRE13	= 0x00002000,
456 	RIC0_FRE14	= 0x00004000,
457 	RIC0_FRE15	= 0x00008000,
458 	RIC0_FRE16	= 0x00010000,
459 	RIC0_FRE17	= 0x00020000,
460 };
461 
462 /* RIC0 */
463 enum RIS0_BIT {
464 	RIS0_FRF0	= 0x00000001,
465 	RIS0_FRF1	= 0x00000002,
466 	RIS0_FRF2	= 0x00000004,
467 	RIS0_FRF3	= 0x00000008,
468 	RIS0_FRF4	= 0x00000010,
469 	RIS0_FRF5	= 0x00000020,
470 	RIS0_FRF6	= 0x00000040,
471 	RIS0_FRF7	= 0x00000080,
472 	RIS0_FRF8	= 0x00000100,
473 	RIS0_FRF9	= 0x00000200,
474 	RIS0_FRF10	= 0x00000400,
475 	RIS0_FRF11	= 0x00000800,
476 	RIS0_FRF12	= 0x00001000,
477 	RIS0_FRF13	= 0x00002000,
478 	RIS0_FRF14	= 0x00004000,
479 	RIS0_FRF15	= 0x00008000,
480 	RIS0_FRF16	= 0x00010000,
481 	RIS0_FRF17	= 0x00020000,
482 	RIS0_RESERVED	= GENMASK(31, 18),
483 };
484 
485 /* RIC1 */
486 enum RIC1_BIT {
487 	RIC1_RFWE	= 0x80000000,
488 };
489 
490 /* RIS1 */
491 enum RIS1_BIT {
492 	RIS1_RFWF	= 0x80000000,
493 };
494 
495 /* RIC2 */
496 enum RIC2_BIT {
497 	RIC2_QFE0	= 0x00000001,
498 	RIC2_QFE1	= 0x00000002,
499 	RIC2_QFE2	= 0x00000004,
500 	RIC2_QFE3	= 0x00000008,
501 	RIC2_QFE4	= 0x00000010,
502 	RIC2_QFE5	= 0x00000020,
503 	RIC2_QFE6	= 0x00000040,
504 	RIC2_QFE7	= 0x00000080,
505 	RIC2_QFE8	= 0x00000100,
506 	RIC2_QFE9	= 0x00000200,
507 	RIC2_QFE10	= 0x00000400,
508 	RIC2_QFE11	= 0x00000800,
509 	RIC2_QFE12	= 0x00001000,
510 	RIC2_QFE13	= 0x00002000,
511 	RIC2_QFE14	= 0x00004000,
512 	RIC2_QFE15	= 0x00008000,
513 	RIC2_QFE16	= 0x00010000,
514 	RIC2_QFE17	= 0x00020000,
515 	RIC2_RFFE	= 0x80000000,
516 };
517 
518 /* RIS2 */
519 enum RIS2_BIT {
520 	RIS2_QFF0	= 0x00000001,
521 	RIS2_QFF1	= 0x00000002,
522 	RIS2_QFF2	= 0x00000004,
523 	RIS2_QFF3	= 0x00000008,
524 	RIS2_QFF4	= 0x00000010,
525 	RIS2_QFF5	= 0x00000020,
526 	RIS2_QFF6	= 0x00000040,
527 	RIS2_QFF7	= 0x00000080,
528 	RIS2_QFF8	= 0x00000100,
529 	RIS2_QFF9	= 0x00000200,
530 	RIS2_QFF10	= 0x00000400,
531 	RIS2_QFF11	= 0x00000800,
532 	RIS2_QFF12	= 0x00001000,
533 	RIS2_QFF13	= 0x00002000,
534 	RIS2_QFF14	= 0x00004000,
535 	RIS2_QFF15	= 0x00008000,
536 	RIS2_QFF16	= 0x00010000,
537 	RIS2_QFF17	= 0x00020000,
538 	RIS2_RFFF	= 0x80000000,
539 	RIS2_RESERVED	= GENMASK(30, 18),
540 };
541 
542 /* TIC */
543 enum TIC_BIT {
544 	TIC_FTE0	= 0x00000001,	/* Documented for R-Car Gen3 only */
545 	TIC_FTE1	= 0x00000002,	/* Documented for R-Car Gen3 only */
546 	TIC_TFUE	= 0x00000100,
547 	TIC_TFWE	= 0x00000200,
548 };
549 
550 /* TIS */
551 enum TIS_BIT {
552 	TIS_FTF0	= 0x00000001,	/* Documented for R-Car Gen3 only */
553 	TIS_FTF1	= 0x00000002,	/* Documented for R-Car Gen3 only */
554 	TIS_TFUF	= 0x00000100,
555 	TIS_TFWF	= 0x00000200,
556 	TIS_RESERVED	= (GENMASK(31, 20) | GENMASK(15, 12) | GENMASK(7, 4))
557 };
558 
559 /* ISS */
560 enum ISS_BIT {
561 	ISS_FRS		= 0x00000001,	/* Documented for R-Car Gen3 only */
562 	ISS_FTS		= 0x00000004,	/* Documented for R-Car Gen3 only */
563 	ISS_ES		= 0x00000040,
564 	ISS_MS		= 0x00000080,
565 	ISS_TFUS	= 0x00000100,
566 	ISS_TFWS	= 0x00000200,
567 	ISS_RFWS	= 0x00001000,
568 	ISS_CGIS	= 0x00002000,
569 	ISS_DPS1	= 0x00020000,
570 	ISS_DPS2	= 0x00040000,
571 	ISS_DPS3	= 0x00080000,
572 	ISS_DPS4	= 0x00100000,
573 	ISS_DPS5	= 0x00200000,
574 	ISS_DPS6	= 0x00400000,
575 	ISS_DPS7	= 0x00800000,
576 	ISS_DPS8	= 0x01000000,
577 	ISS_DPS9	= 0x02000000,
578 	ISS_DPS10	= 0x04000000,
579 	ISS_DPS11	= 0x08000000,
580 	ISS_DPS12	= 0x10000000,
581 	ISS_DPS13	= 0x20000000,
582 	ISS_DPS14	= 0x40000000,
583 	ISS_DPS15	= 0x80000000,
584 };
585 
586 /* CIE (R-Car Gen3 only) */
587 enum CIE_BIT {
588 	CIE_CRIE	= 0x00000001,
589 	CIE_CTIE	= 0x00000100,
590 	CIE_RQFM	= 0x00010000,
591 	CIE_CL0M	= 0x00020000,
592 	CIE_RFWL	= 0x00040000,
593 	CIE_RFFL	= 0x00080000,
594 };
595 
596 /* GCCR */
597 enum GCCR_BIT {
598 	GCCR_TCR	= 0x00000003,
599 	GCCR_TCR_NOREQ	= 0x00000000, /* No request */
600 	GCCR_TCR_RESET	= 0x00000001, /* gPTP/AVTP presentation timer reset */
601 	GCCR_TCR_CAPTURE = 0x00000003, /* Capture value set in GCCR.TCSS */
602 	GCCR_LTO	= 0x00000004,
603 	GCCR_LTI	= 0x00000008,
604 	GCCR_LPTC	= 0x00000010,
605 	GCCR_LMTT	= 0x00000020,
606 	GCCR_TCSS	= 0x00000300,
607 	GCCR_TCSS_GPTP	= 0x00000000,	/* gPTP timer value */
608 	GCCR_TCSS_ADJGPTP = 0x00000100, /* Adjusted gPTP timer value */
609 	GCCR_TCSS_AVTP	= 0x00000200,	/* AVTP presentation time value */
610 };
611 
612 /* GTI */
613 enum GTI_BIT {
614 	GTI_TIV		= 0x0FFFFFFF,
615 };
616 
617 #define GTI_TIV_MAX	GTI_TIV
618 #define GTI_TIV_MIN	0x20
619 
620 /* GIC */
621 enum GIC_BIT {
622 	GIC_PTCE	= 0x00000001,	/* Documented for R-Car Gen3 only */
623 	GIC_PTME	= 0x00000004,
624 };
625 
626 /* GIS */
627 enum GIS_BIT {
628 	GIS_PTCF	= 0x00000001,	/* Documented for R-Car Gen3 only */
629 	GIS_PTMF	= 0x00000004,
630 	GIS_RESERVED	= GENMASK(15, 10),
631 };
632 
633 /* GIE (R-Car Gen3 only) */
634 enum GIE_BIT {
635 	GIE_PTCS	= 0x00000001,
636 	GIE_PTOS	= 0x00000002,
637 	GIE_PTMS0	= 0x00000004,
638 	GIE_PTMS1	= 0x00000008,
639 	GIE_PTMS2	= 0x00000010,
640 	GIE_PTMS3	= 0x00000020,
641 	GIE_PTMS4	= 0x00000040,
642 	GIE_PTMS5	= 0x00000080,
643 	GIE_PTMS6	= 0x00000100,
644 	GIE_PTMS7	= 0x00000200,
645 	GIE_ATCS0	= 0x00010000,
646 	GIE_ATCS1	= 0x00020000,
647 	GIE_ATCS2	= 0x00040000,
648 	GIE_ATCS3	= 0x00080000,
649 	GIE_ATCS4	= 0x00100000,
650 	GIE_ATCS5	= 0x00200000,
651 	GIE_ATCS6	= 0x00400000,
652 	GIE_ATCS7	= 0x00800000,
653 	GIE_ATCS8	= 0x01000000,
654 	GIE_ATCS9	= 0x02000000,
655 	GIE_ATCS10	= 0x04000000,
656 	GIE_ATCS11	= 0x08000000,
657 	GIE_ATCS12	= 0x10000000,
658 	GIE_ATCS13	= 0x20000000,
659 	GIE_ATCS14	= 0x40000000,
660 	GIE_ATCS15	= 0x80000000,
661 };
662 
663 /* GID (R-Car Gen3 only) */
664 enum GID_BIT {
665 	GID_PTCD	= 0x00000001,
666 	GID_PTOD	= 0x00000002,
667 	GID_PTMD0	= 0x00000004,
668 	GID_PTMD1	= 0x00000008,
669 	GID_PTMD2	= 0x00000010,
670 	GID_PTMD3	= 0x00000020,
671 	GID_PTMD4	= 0x00000040,
672 	GID_PTMD5	= 0x00000080,
673 	GID_PTMD6	= 0x00000100,
674 	GID_PTMD7	= 0x00000200,
675 	GID_ATCD0	= 0x00010000,
676 	GID_ATCD1	= 0x00020000,
677 	GID_ATCD2	= 0x00040000,
678 	GID_ATCD3	= 0x00080000,
679 	GID_ATCD4	= 0x00100000,
680 	GID_ATCD5	= 0x00200000,
681 	GID_ATCD6	= 0x00400000,
682 	GID_ATCD7	= 0x00800000,
683 	GID_ATCD8	= 0x01000000,
684 	GID_ATCD9	= 0x02000000,
685 	GID_ATCD10	= 0x04000000,
686 	GID_ATCD11	= 0x08000000,
687 	GID_ATCD12	= 0x10000000,
688 	GID_ATCD13	= 0x20000000,
689 	GID_ATCD14	= 0x40000000,
690 	GID_ATCD15	= 0x80000000,
691 };
692 
693 /* RIE0 (R-Car Gen3 only) */
694 enum RIE0_BIT {
695 	RIE0_FRS0	= 0x00000001,
696 	RIE0_FRS1	= 0x00000002,
697 	RIE0_FRS2	= 0x00000004,
698 	RIE0_FRS3	= 0x00000008,
699 	RIE0_FRS4	= 0x00000010,
700 	RIE0_FRS5	= 0x00000020,
701 	RIE0_FRS6	= 0x00000040,
702 	RIE0_FRS7	= 0x00000080,
703 	RIE0_FRS8	= 0x00000100,
704 	RIE0_FRS9	= 0x00000200,
705 	RIE0_FRS10	= 0x00000400,
706 	RIE0_FRS11	= 0x00000800,
707 	RIE0_FRS12	= 0x00001000,
708 	RIE0_FRS13	= 0x00002000,
709 	RIE0_FRS14	= 0x00004000,
710 	RIE0_FRS15	= 0x00008000,
711 	RIE0_FRS16	= 0x00010000,
712 	RIE0_FRS17	= 0x00020000,
713 };
714 
715 /* RID0 (R-Car Gen3 only) */
716 enum RID0_BIT {
717 	RID0_FRD0	= 0x00000001,
718 	RID0_FRD1	= 0x00000002,
719 	RID0_FRD2	= 0x00000004,
720 	RID0_FRD3	= 0x00000008,
721 	RID0_FRD4	= 0x00000010,
722 	RID0_FRD5	= 0x00000020,
723 	RID0_FRD6	= 0x00000040,
724 	RID0_FRD7	= 0x00000080,
725 	RID0_FRD8	= 0x00000100,
726 	RID0_FRD9	= 0x00000200,
727 	RID0_FRD10	= 0x00000400,
728 	RID0_FRD11	= 0x00000800,
729 	RID0_FRD12	= 0x00001000,
730 	RID0_FRD13	= 0x00002000,
731 	RID0_FRD14	= 0x00004000,
732 	RID0_FRD15	= 0x00008000,
733 	RID0_FRD16	= 0x00010000,
734 	RID0_FRD17	= 0x00020000,
735 };
736 
737 /* RIE2 (R-Car Gen3 only) */
738 enum RIE2_BIT {
739 	RIE2_QFS0	= 0x00000001,
740 	RIE2_QFS1	= 0x00000002,
741 	RIE2_QFS2	= 0x00000004,
742 	RIE2_QFS3	= 0x00000008,
743 	RIE2_QFS4	= 0x00000010,
744 	RIE2_QFS5	= 0x00000020,
745 	RIE2_QFS6	= 0x00000040,
746 	RIE2_QFS7	= 0x00000080,
747 	RIE2_QFS8	= 0x00000100,
748 	RIE2_QFS9	= 0x00000200,
749 	RIE2_QFS10	= 0x00000400,
750 	RIE2_QFS11	= 0x00000800,
751 	RIE2_QFS12	= 0x00001000,
752 	RIE2_QFS13	= 0x00002000,
753 	RIE2_QFS14	= 0x00004000,
754 	RIE2_QFS15	= 0x00008000,
755 	RIE2_QFS16	= 0x00010000,
756 	RIE2_QFS17	= 0x00020000,
757 	RIE2_RFFS	= 0x80000000,
758 };
759 
760 /* RID2 (R-Car Gen3 only) */
761 enum RID2_BIT {
762 	RID2_QFD0	= 0x00000001,
763 	RID2_QFD1	= 0x00000002,
764 	RID2_QFD2	= 0x00000004,
765 	RID2_QFD3	= 0x00000008,
766 	RID2_QFD4	= 0x00000010,
767 	RID2_QFD5	= 0x00000020,
768 	RID2_QFD6	= 0x00000040,
769 	RID2_QFD7	= 0x00000080,
770 	RID2_QFD8	= 0x00000100,
771 	RID2_QFD9	= 0x00000200,
772 	RID2_QFD10	= 0x00000400,
773 	RID2_QFD11	= 0x00000800,
774 	RID2_QFD12	= 0x00001000,
775 	RID2_QFD13	= 0x00002000,
776 	RID2_QFD14	= 0x00004000,
777 	RID2_QFD15	= 0x00008000,
778 	RID2_QFD16	= 0x00010000,
779 	RID2_QFD17	= 0x00020000,
780 	RID2_RFFD	= 0x80000000,
781 };
782 
783 /* TIE (R-Car Gen3 only) */
784 enum TIE_BIT {
785 	TIE_FTS0	= 0x00000001,
786 	TIE_FTS1	= 0x00000002,
787 	TIE_FTS2	= 0x00000004,
788 	TIE_FTS3	= 0x00000008,
789 	TIE_TFUS	= 0x00000100,
790 	TIE_TFWS	= 0x00000200,
791 	TIE_MFUS	= 0x00000400,
792 	TIE_MFWS	= 0x00000800,
793 	TIE_TDPS0	= 0x00010000,
794 	TIE_TDPS1	= 0x00020000,
795 	TIE_TDPS2	= 0x00040000,
796 	TIE_TDPS3	= 0x00080000,
797 };
798 
799 /* TID (R-Car Gen3 only) */
800 enum TID_BIT {
801 	TID_FTD0	= 0x00000001,
802 	TID_FTD1	= 0x00000002,
803 	TID_FTD2	= 0x00000004,
804 	TID_FTD3	= 0x00000008,
805 	TID_TFUD	= 0x00000100,
806 	TID_TFWD	= 0x00000200,
807 	TID_MFUD	= 0x00000400,
808 	TID_MFWD	= 0x00000800,
809 	TID_TDPD0	= 0x00010000,
810 	TID_TDPD1	= 0x00020000,
811 	TID_TDPD2	= 0x00040000,
812 	TID_TDPD3	= 0x00080000,
813 };
814 
815 /* ECMR */
816 enum ECMR_BIT {
817 	ECMR_PRM	= 0x00000001,
818 	ECMR_DM		= 0x00000002,
819 	ECMR_TE		= 0x00000020,
820 	ECMR_RE		= 0x00000040,
821 	ECMR_MPDE	= 0x00000200,
822 	ECMR_TXF	= 0x00010000,	/* Documented for R-Car Gen3 only */
823 	ECMR_RXF	= 0x00020000,
824 	ECMR_PFR	= 0x00040000,
825 	ECMR_ZPF	= 0x00080000,	/* Documented for R-Car Gen3 and RZ/G2L */
826 	ECMR_RZPF	= 0x00100000,
827 	ECMR_DPAD	= 0x00200000,
828 	ECMR_RCSC	= 0x00800000,
829 	ECMR_RCPT	= 0x02000000,	/* Documented for RZ/G2L only */
830 	ECMR_TRCCM	= 0x04000000,
831 };
832 
833 /* ECSR */
834 enum ECSR_BIT {
835 	ECSR_ICD	= 0x00000001,
836 	ECSR_MPD	= 0x00000002,
837 	ECSR_LCHNG	= 0x00000004,
838 	ECSR_PHYI	= 0x00000008,
839 	ECSR_PFRI	= 0x00000010,	/* Documented for R-Car Gen3 and RZ/G2L */
840 };
841 
842 /* ECSIPR */
843 enum ECSIPR_BIT {
844 	ECSIPR_ICDIP	= 0x00000001,
845 	ECSIPR_MPDIP	= 0x00000002,
846 	ECSIPR_LCHNGIP	= 0x00000004,
847 };
848 
849 /* PIR */
850 enum PIR_BIT {
851 	PIR_MDC		= 0x00000001,
852 	PIR_MMD		= 0x00000002,
853 	PIR_MDO		= 0x00000004,
854 	PIR_MDI		= 0x00000008,
855 };
856 
857 /* PSR */
858 enum PSR_BIT {
859 	PSR_LMON	= 0x00000001,
860 };
861 
862 /* PIPR */
863 enum PIPR_BIT {
864 	PIPR_PHYIP	= 0x00000001,
865 };
866 
867 /* MPR */
868 enum MPR_BIT {
869 	MPR_MP		= 0x0000ffff,
870 };
871 
872 /* GECMR */
873 enum GECMR_BIT {
874 	GECMR_SPEED		= 0x00000001,
875 	GECMR_SPEED_100		= 0x00000000,
876 	GECMR_SPEED_1000	= 0x00000001,
877 	GBETH_GECMR_SPEED	= 0x00000030,
878 	GBETH_GECMR_SPEED_10	= 0x00000000,
879 	GBETH_GECMR_SPEED_100	= 0x00000010,
880 	GBETH_GECMR_SPEED_1000	= 0x00000020,
881 };
882 
883 /* The Ethernet AVB descriptor definitions. */
884 struct ravb_desc {
885 	__le16 ds;	/* Descriptor size */
886 	u8 cc;		/* Content control MSBs (reserved) */
887 	u8 die_dt;	/* Descriptor interrupt enable and type */
888 	__le32 dptr;	/* Descriptor pointer */
889 };
890 
891 #define DPTR_ALIGN	4	/* Required descriptor pointer alignment */
892 
893 enum DIE_DT {
894 	/* Frame data */
895 	DT_FMID		= 0x40,
896 	DT_FSTART	= 0x50,
897 	DT_FEND		= 0x60,
898 	DT_FSINGLE	= 0x70,
899 	/* Chain control */
900 	DT_LINK		= 0x80,
901 	DT_LINKFIX	= 0x90,
902 	DT_EOS		= 0xa0,
903 	/* HW/SW arbitration */
904 	DT_FEMPTY	= 0xc0,
905 	DT_FEMPTY_IS	= 0xd0,
906 	DT_FEMPTY_IC	= 0xe0,
907 	DT_FEMPTY_ND	= 0xf0,
908 	DT_LEMPTY	= 0x20,
909 	DT_EEMPTY	= 0x30,
910 };
911 
912 struct ravb_rx_desc {
913 	__le16 ds_cc;	/* Descriptor size and content control LSBs */
914 	u8 msc;		/* MAC status code */
915 	u8 die_dt;	/* Descriptor interrupt enable and type */
916 	__le32 dptr;	/* Descpriptor pointer */
917 };
918 
919 struct ravb_ex_rx_desc {
920 	__le16 ds_cc;	/* Descriptor size and content control lower bits */
921 	u8 msc;		/* MAC status code */
922 	u8 die_dt;	/* Descriptor interrupt enable and type */
923 	__le32 dptr;	/* Descpriptor pointer */
924 	__le32 ts_n;	/* Timestampe nsec */
925 	__le32 ts_sl;	/* Timestamp low */
926 	__le16 ts_sh;	/* Timestamp high */
927 	__le16 res;	/* Reserved bits */
928 };
929 
930 enum RX_DS_CC_BIT {
931 	RX_DS		= 0x0fff, /* Data size */
932 	RX_TR		= 0x1000, /* Truncation indication */
933 	RX_EI		= 0x2000, /* Error indication */
934 	RX_PS		= 0xc000, /* Padding selection */
935 };
936 
937 /* E-MAC status code */
938 enum MSC_BIT {
939 	MSC_CRC		= 0x01, /* Frame CRC error */
940 	MSC_RFE		= 0x02, /* Frame reception error (flagged by PHY) */
941 	MSC_RTSF	= 0x04, /* Frame length error (frame too short) */
942 	MSC_RTLF	= 0x08, /* Frame length error (frame too long) */
943 	MSC_FRE		= 0x10, /* Fraction error (not a multiple of 8 bits) */
944 	MSC_CRL		= 0x20, /* Carrier lost */
945 	MSC_CEEF	= 0x40, /* Carrier extension error */
946 	MSC_MC		= 0x80, /* Multicast frame reception */
947 };
948 
949 struct ravb_tx_desc {
950 	__le16 ds_tagl;	/* Descriptor size and frame tag LSBs */
951 	u8 tagh_tsr;	/* Frame tag MSBs and timestamp storage request bit */
952 	u8 die_dt;	/* Descriptor interrupt enable and type */
953 	__le32 dptr;	/* Descpriptor pointer */
954 };
955 
956 enum TX_DS_TAGL_BIT {
957 	TX_DS		= 0x0fff, /* Data size */
958 	TX_TAGL		= 0xf000, /* Frame tag LSBs */
959 };
960 
961 enum TX_TAGH_TSR_BIT {
962 	TX_TAGH		= 0x3f, /* Frame tag MSBs */
963 	TX_TSR		= 0x40, /* Timestamp storage request */
964 };
965 enum RAVB_QUEUE {
966 	RAVB_BE = 0,	/* Best Effort Queue */
967 	RAVB_NC,	/* Network Control Queue */
968 };
969 
970 enum CXR31_BIT {
971 	CXR31_SEL_LINK0	= 0x00000001,
972 	CXR31_SEL_LINK1	= 0x00000008,
973 };
974 
975 enum CXR35_BIT {
976 	CXR35_SEL_XMII		= 0x00000003,
977 	CXR35_SEL_XMII_RGMII	= 0x00000000,
978 	CXR35_SEL_XMII_MII	= 0x00000002,
979 	CXR35_HALFCYC_CLKSW	= 0xffff0000,
980 };
981 
982 enum CSR0_BIT {
983 	CSR0_TPE	= 0x00000010,
984 	CSR0_RPE	= 0x00000020,
985 };
986 
987 enum CSR1_BIT {
988 	CSR1_TIP4	= 0x00000001,
989 	CSR1_TTCP4	= 0x00000010,
990 	CSR1_TUDP4	= 0x00000020,
991 	CSR1_TICMP4	= 0x00000040,
992 	CSR1_TTCP6	= 0x00100000,
993 	CSR1_TUDP6	= 0x00200000,
994 	CSR1_TICMP6	= 0x00400000,
995 	CSR1_THOP	= 0x01000000,
996 	CSR1_TROUT	= 0x02000000,
997 	CSR1_TAHD	= 0x04000000,
998 	CSR1_TDHD	= 0x08000000,
999 };
1000 
1001 enum CSR2_BIT {
1002 	CSR2_RIP4	= 0x00000001,
1003 	CSR2_RTCP4	= 0x00000010,
1004 	CSR2_RUDP4	= 0x00000020,
1005 	CSR2_RICMP4	= 0x00000040,
1006 	CSR2_RTCP6	= 0x00100000,
1007 	CSR2_RUDP6	= 0x00200000,
1008 	CSR2_RICMP6	= 0x00400000,
1009 	CSR2_RHOP	= 0x01000000,
1010 	CSR2_RROUT	= 0x02000000,
1011 	CSR2_RAHD	= 0x04000000,
1012 	CSR2_RDHD	= 0x08000000,
1013 };
1014 
1015 #define DBAT_ENTRY_NUM	22
1016 #define RX_QUEUE_OFFSET	4
1017 #define NUM_RX_QUEUE	2
1018 #define NUM_TX_QUEUE	2
1019 
1020 struct ravb_tstamp_skb {
1021 	struct list_head list;
1022 	struct sk_buff *skb;
1023 	u16 tag;
1024 };
1025 
1026 struct ravb_ptp_perout {
1027 	u32 target;
1028 	u32 period;
1029 };
1030 
1031 #define N_EXT_TS	1
1032 #define N_PER_OUT	1
1033 
1034 struct ravb_ptp {
1035 	struct ptp_clock *clock;
1036 	struct ptp_clock_info info;
1037 	u32 default_addend;
1038 	u32 current_addend;
1039 	int extts[N_EXT_TS];
1040 	struct ravb_ptp_perout perout[N_PER_OUT];
1041 };
1042 
1043 struct ravb_hw_info {
1044 	int (*receive)(struct net_device *ndev, int budget, int q);
1045 	void (*set_rate)(struct net_device *ndev);
1046 	int (*set_feature)(struct net_device *ndev, netdev_features_t features);
1047 	int (*dmac_init)(struct net_device *ndev);
1048 	void (*emac_init)(struct net_device *ndev);
1049 	const char (*gstrings_stats)[ETH_GSTRING_LEN];
1050 	size_t gstrings_size;
1051 	netdev_features_t net_hw_features;
1052 	netdev_features_t net_features;
1053 	int stats_len;
1054 	u32 tccr_mask;
1055 	u32 rx_max_frame_size;
1056 	u32 rx_buffer_size;
1057 	u32 rx_desc_size;
1058 	unsigned aligned_tx: 1;
1059 	unsigned coalesce_irqs:1;	/* Needs software IRQ coalescing */
1060 
1061 	/* hardware features */
1062 	unsigned internal_delay:1;	/* AVB-DMAC has internal delays */
1063 	unsigned tx_counters:1;		/* E-MAC has TX counters */
1064 	unsigned carrier_counters:1;	/* E-MAC has carrier counters */
1065 	unsigned multi_irqs:1;		/* AVB-DMAC and E-MAC has multiple irqs */
1066 	unsigned irq_en_dis:1;		/* Has separate irq enable and disable regs */
1067 	unsigned err_mgmt_irqs:1;	/* Line1 (Err) and Line2 (Mgmt) irqs are separate */
1068 	unsigned gptp:1;		/* AVB-DMAC has gPTP support */
1069 	unsigned ccc_gac:1;		/* AVB-DMAC has gPTP support active in config mode */
1070 	unsigned gptp_ref_clk:1;	/* gPTP has separate reference clock */
1071 	unsigned nc_queues:1;		/* AVB-DMAC has RX and TX NC queues */
1072 	unsigned magic_pkt:1;		/* E-MAC supports magic packet detection */
1073 	unsigned half_duplex:1;		/* E-MAC supports half duplex mode */
1074 };
1075 
1076 struct ravb_rx_buffer {
1077 	struct page *page;
1078 	unsigned int offset;
1079 };
1080 
1081 struct ravb_private {
1082 	struct net_device *ndev;
1083 	struct platform_device *pdev;
1084 	void __iomem *addr;
1085 	struct clk *clk;
1086 	struct clk *refclk;
1087 	struct clk *gptp_clk;
1088 	struct mdiobb_ctrl mdiobb;
1089 	u32 num_rx_ring[NUM_RX_QUEUE];
1090 	u32 num_tx_ring[NUM_TX_QUEUE];
1091 	u32 desc_bat_size;
1092 	dma_addr_t desc_bat_dma;
1093 	struct ravb_desc *desc_bat;
1094 	dma_addr_t rx_desc_dma[NUM_RX_QUEUE];
1095 	dma_addr_t tx_desc_dma[NUM_TX_QUEUE];
1096 	union {
1097 		struct ravb_rx_desc *desc;
1098 		struct ravb_ex_rx_desc *ex_desc;
1099 		void *raw;
1100 	} rx_ring[NUM_RX_QUEUE];
1101 	struct ravb_tx_desc *tx_ring[NUM_TX_QUEUE];
1102 	void *tx_align[NUM_TX_QUEUE];
1103 	struct sk_buff *rx_1st_skb;
1104 	struct page_pool *rx_pool[NUM_RX_QUEUE];
1105 	struct ravb_rx_buffer *rx_buffers[NUM_RX_QUEUE];
1106 	struct sk_buff **tx_skb[NUM_TX_QUEUE];
1107 	u32 rx_over_errors;
1108 	u32 rx_fifo_errors;
1109 	struct net_device_stats stats[NUM_RX_QUEUE];
1110 	u32 tstamp_tx_ctrl;
1111 	u32 tstamp_rx_ctrl;
1112 	struct list_head ts_skb_list;
1113 	u32 ts_skb_tag;
1114 	struct ravb_ptp ptp;
1115 	spinlock_t lock;		/* Register access lock */
1116 	u32 cur_rx[NUM_RX_QUEUE];	/* Consumer ring indices */
1117 	u32 dirty_rx[NUM_RX_QUEUE];	/* Producer ring indices */
1118 	u32 cur_tx[NUM_TX_QUEUE];
1119 	u32 dirty_tx[NUM_TX_QUEUE];
1120 	struct napi_struct napi[NUM_RX_QUEUE];
1121 	struct work_struct work;
1122 	/* MII transceiver section. */
1123 	struct mii_bus *mii_bus;	/* MDIO bus control */
1124 	int link;
1125 	phy_interface_t phy_interface;
1126 	int msg_enable;
1127 	int speed;
1128 	int emac_irq;
1129 
1130 	unsigned no_avb_link:1;
1131 	unsigned avb_link_active_low:1;
1132 	unsigned wol_enabled:1;
1133 	unsigned rxcidm:1;		/* RX Clock Internal Delay Mode */
1134 	unsigned txcidm:1;		/* TX Clock Internal Delay Mode */
1135 	unsigned rgmii_override:1;	/* Deprecated rgmii-*id behavior */
1136 	unsigned int num_tx_desc;	/* TX descriptors per packet */
1137 
1138 	int duplex;
1139 
1140 	const struct ravb_hw_info *info;
1141 	struct reset_control *rstc;
1142 
1143 	u32 gti_tiv;
1144 };
1145 
1146 static inline u32 ravb_read(struct net_device *ndev, enum ravb_reg reg)
1147 {
1148 	struct ravb_private *priv = netdev_priv(ndev);
1149 
1150 	return ioread32(priv->addr + reg);
1151 }
1152 
1153 static inline void ravb_write(struct net_device *ndev, u32 data,
1154 			      enum ravb_reg reg)
1155 {
1156 	struct ravb_private *priv = netdev_priv(ndev);
1157 
1158 	iowrite32(data, priv->addr + reg);
1159 }
1160 
1161 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
1162 		 u32 set);
1163 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value);
1164 
1165 void ravb_ptp_interrupt(struct net_device *ndev);
1166 void ravb_ptp_init(struct net_device *ndev, struct platform_device *pdev);
1167 void ravb_ptp_stop(struct net_device *ndev);
1168 
1169 #endif	/* #ifndef __RAVB_H__ */
1170