1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * rtase is the Linux device driver released for Realtek Automotive Switch 4 * controllers with PCI-Express interface. 5 * 6 * Copyright(c) 2024 Realtek Semiconductor Corp. 7 */ 8 9 #ifndef RTASE_H 10 #define RTASE_H 11 12 #define RTASE_HW_VER_MASK 0x7C800000 13 14 #define RTASE_RX_DMA_BURST_256 4 15 #define RTASE_TX_DMA_BURST_UNLIMITED 7 16 17 #define RTASE_RX_BUF_SIZE (PAGE_SIZE - \ 18 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 19 #define RTASE_MAX_JUMBO_SIZE (RTASE_RX_BUF_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN) 20 21 /* 3 means InterFrameGap = the shortest one */ 22 #define RTASE_INTERFRAMEGAP 0x03 23 24 #define RTASE_REGS_SIZE 256 25 #define RTASE_PCI_REGS_SIZE 0x100 26 27 #define RTASE_MULTICAST_FILTER_MASK GENMASK(30, 26) 28 29 #define RTASE_VLAN_FILTER_ENTRY_NUM 32 30 #define RTASE_NUM_TX_QUEUE 8 31 #define RTASE_NUM_RX_QUEUE 4 32 33 #define RTASE_TXQ_CTRL 1 34 #define RTASE_FUNC_TXQ_NUM 1 35 #define RTASE_FUNC_RXQ_NUM 1 36 #define RTASE_INTERRUPT_NUM 1 37 38 #define RTASE_MITI_TIME_COUNT_MASK GENMASK(3, 0) 39 #define RTASE_MITI_TIME_UNIT_MASK GENMASK(7, 4) 40 #define RTASE_MITI_DEFAULT_TIME 128 41 #define RTASE_MITI_MAX_TIME 491520 42 #define RTASE_MITI_PKT_NUM_COUNT_MASK GENMASK(11, 8) 43 #define RTASE_MITI_PKT_NUM_UNIT_MASK GENMASK(13, 12) 44 #define RTASE_MITI_DEFAULT_PKT_NUM 64 45 #define RTASE_MITI_MAX_PKT_NUM_IDX 3 46 #define RTASE_MITI_MAX_PKT_NUM_UNIT 16 47 #define RTASE_MITI_MAX_PKT_NUM 240 48 #define RTASE_MITI_COUNT_BIT_NUM 4 49 50 #define RTASE_NUM_MSIX 4 51 52 #define RTASE_DWORD_MOD 16 53 54 /*****************************************************************************/ 55 enum rtase_registers { 56 RTASE_MAC0 = 0x0000, 57 RTASE_MAC4 = 0x0004, 58 RTASE_MAR0 = 0x0008, 59 RTASE_MAR1 = 0x000C, 60 RTASE_DTCCR0 = 0x0010, 61 RTASE_DTCCR4 = 0x0014, 62 #define RTASE_COUNTER_RESET BIT(0) 63 #define RTASE_COUNTER_DUMP BIT(3) 64 65 RTASE_FCR = 0x0018, 66 #define RTASE_FCR_RXQ_MASK GENMASK(5, 4) 67 68 RTASE_LBK_CTRL = 0x001A, 69 #define RTASE_LBK_ATLD BIT(1) 70 #define RTASE_LBK_CLR BIT(0) 71 72 RTASE_TX_DESC_ADDR0 = 0x0020, 73 RTASE_TX_DESC_ADDR4 = 0x0024, 74 RTASE_TX_DESC_COMMAND = 0x0028, 75 #define RTASE_TX_DESC_CMD_CS BIT(15) 76 #define RTASE_TX_DESC_CMD_WE BIT(14) 77 78 RTASE_BOOT_CTL = 0x6004, 79 RTASE_CLKSW_SET = 0x6018, 80 81 RTASE_CHIP_CMD = 0x0037, 82 #define RTASE_STOP_REQ BIT(7) 83 #define RTASE_STOP_REQ_DONE BIT(6) 84 #define RTASE_RE BIT(3) 85 #define RTASE_TE BIT(2) 86 87 RTASE_IMR0 = 0x0038, 88 RTASE_ISR0 = 0x003C, 89 #define RTASE_TOK7 BIT(30) 90 #define RTASE_TOK6 BIT(28) 91 #define RTASE_TOK5 BIT(26) 92 #define RTASE_TOK4 BIT(24) 93 #define RTASE_FOVW BIT(6) 94 #define RTASE_RDU BIT(4) 95 #define RTASE_TOK BIT(2) 96 #define RTASE_ROK BIT(0) 97 98 RTASE_IMR1 = 0x0800, 99 RTASE_ISR1 = 0x0802, 100 #define RTASE_Q_TOK BIT(4) 101 #define RTASE_Q_RDU BIT(1) 102 #define RTASE_Q_ROK BIT(0) 103 104 RTASE_EPHY_ISR = 0x6014, 105 RTASE_EPHY_IMR = 0x6016, 106 107 RTASE_TX_CONFIG_0 = 0x0040, 108 #define RTASE_TX_INTER_FRAME_GAP_MASK GENMASK(25, 24) 109 /* DMA burst value (0-7) is shift this many bits */ 110 #define RTASE_TX_DMA_MASK GENMASK(10, 8) 111 112 RTASE_RX_CONFIG_0 = 0x0044, 113 #define RTASE_RX_SINGLE_FETCH BIT(14) 114 #define RTASE_RX_SINGLE_TAG BIT(13) 115 #define RTASE_RX_MX_DMA_MASK GENMASK(10, 8) 116 #define RTASE_ACPT_FLOW BIT(7) 117 #define RTASE_ACCEPT_ERR BIT(5) 118 #define RTASE_ACCEPT_RUNT BIT(4) 119 #define RTASE_ACCEPT_BROADCAST BIT(3) 120 #define RTASE_ACCEPT_MULTICAST BIT(2) 121 #define RTASE_ACCEPT_MYPHYS BIT(1) 122 #define RTASE_ACCEPT_ALLPHYS BIT(0) 123 #define RTASE_ACCEPT_MASK (RTASE_ACPT_FLOW | RTASE_ACCEPT_ERR | \ 124 RTASE_ACCEPT_RUNT | RTASE_ACCEPT_BROADCAST | \ 125 RTASE_ACCEPT_MULTICAST | RTASE_ACCEPT_MYPHYS | \ 126 RTASE_ACCEPT_ALLPHYS) 127 128 RTASE_RX_CONFIG_1 = 0x0046, 129 #define RTASE_RX_MAX_FETCH_DESC_MASK GENMASK(15, 11) 130 #define RTASE_RX_NEW_DESC_FORMAT_EN BIT(8) 131 #define RTASE_OUTER_VLAN_DETAG_EN BIT(7) 132 #define RTASE_INNER_VLAN_DETAG_EN BIT(6) 133 #define RTASE_PCIE_NEW_FLOW BIT(2) 134 #define RTASE_PCIE_RELOAD_EN BIT(0) 135 136 RTASE_EEM = 0x0050, 137 #define RTASE_EEM_UNLOCK 0xC0 138 139 RTASE_TDFNR = 0x0057, 140 RTASE_TPPOLL = 0x0090, 141 RTASE_PDR = 0x00B0, 142 RTASE_FIFOR = 0x00D3, 143 #define RTASE_TX_FIFO_EMPTY BIT(5) 144 #define RTASE_RX_FIFO_EMPTY BIT(4) 145 146 RTASE_RMS = 0x00DA, 147 RTASE_CPLUS_CMD = 0x00E0, 148 #define RTASE_FORCE_RXFLOW_EN BIT(11) 149 #define RTASE_FORCE_TXFLOW_EN BIT(10) 150 #define RTASE_RX_CHKSUM BIT(5) 151 152 RTASE_Q0_RX_DESC_ADDR0 = 0x00E4, 153 RTASE_Q0_RX_DESC_ADDR4 = 0x00E8, 154 RTASE_Q1_RX_DESC_ADDR0 = 0x4000, 155 RTASE_Q1_RX_DESC_ADDR4 = 0x4004, 156 RTASE_MTPS = 0x00EC, 157 #define RTASE_TAG_NUM_SEL_MASK GENMASK(10, 8) 158 159 RTASE_MISC = 0x00F2, 160 #define RTASE_RX_DV_GATE_EN BIT(3) 161 162 RTASE_TFUN_CTRL = 0x0400, 163 #define RTASE_TX_NEW_DESC_FORMAT_EN BIT(0) 164 165 RTASE_TX_CONFIG_1 = 0x203E, 166 #define RTASE_TC_MODE_MASK GENMASK(11, 10) 167 168 RTASE_TOKSEL = 0x2046, 169 RTASE_RFIFONFULL = 0x4406, 170 RTASE_INT_MITI_TX = 0x0A00, 171 RTASE_INT_MITI_RX = 0x0A80, 172 173 RTASE_VLAN_ENTRY_0 = 0xAC80, 174 }; 175 176 enum rtase_desc_status_bit { 177 RTASE_DESC_OWN = BIT(31), /* Descriptor is owned by NIC */ 178 RTASE_RING_END = BIT(30), /* End of descriptor ring */ 179 }; 180 181 enum rtase_sw_flag_content { 182 RTASE_SWF_MSI_ENABLED = BIT(1), 183 RTASE_SWF_MSIX_ENABLED = BIT(2), 184 }; 185 186 #define RSVD_MASK 0x3FFFC000 187 188 struct rtase_tx_desc { 189 __le32 opts1; 190 __le32 opts2; 191 __le64 addr; 192 __le32 opts3; 193 __le32 reserved1; 194 __le32 reserved2; 195 __le32 reserved3; 196 } __packed; 197 198 /*------ offset 0 of tx descriptor ------*/ 199 #define RTASE_TX_FIRST_FRAG BIT(29) /* Tx First segment of a packet */ 200 #define RTASE_TX_LAST_FRAG BIT(28) /* Tx Final segment of a packet */ 201 #define RTASE_GIANT_SEND_V4 BIT(26) /* TCP Giant Send Offload V4 (GSOv4) */ 202 #define RTASE_GIANT_SEND_V6 BIT(25) /* TCP Giant Send Offload V6 (GSOv6) */ 203 #define RTASE_TX_VLAN_TAG BIT(17) /* Add VLAN tag */ 204 205 /*------ offset 4 of tx descriptor ------*/ 206 #define RTASE_TX_UDPCS_C BIT(31) /* Calculate UDP/IP checksum */ 207 #define RTASE_TX_TCPCS_C BIT(30) /* Calculate TCP/IP checksum */ 208 #define RTASE_TX_IPCS_C BIT(29) /* Calculate IP checksum */ 209 #define RTASE_TX_IPV6F_C BIT(28) /* Indicate it is an IPv6 packet */ 210 211 union rtase_rx_desc { 212 struct { 213 __le64 header_buf_addr; 214 __le32 reserved1; 215 __le32 opts_header_len; 216 __le64 addr; 217 __le32 reserved2; 218 __le32 opts1; 219 } __packed desc_cmd; 220 221 struct { 222 __le32 reserved1; 223 __le32 reserved2; 224 __le32 rss; 225 __le32 opts4; 226 __le32 reserved3; 227 __le32 opts3; 228 __le32 opts2; 229 __le32 opts1; 230 } __packed desc_status; 231 } __packed; 232 233 /*------ offset 28 of rx descriptor ------*/ 234 #define RTASE_RX_FIRST_FRAG BIT(25) /* Rx First segment of a packet */ 235 #define RTASE_RX_LAST_FRAG BIT(24) /* Rx Final segment of a packet */ 236 #define RTASE_RX_RES BIT(20) 237 #define RTASE_RX_RUNT BIT(19) 238 #define RTASE_RX_RWT BIT(18) 239 #define RTASE_RX_CRC BIT(16) 240 #define RTASE_RX_V6F BIT(31) 241 #define RTASE_RX_V4F BIT(30) 242 #define RTASE_RX_UDPT BIT(29) 243 #define RTASE_RX_TCPT BIT(28) 244 #define RTASE_RX_IPF BIT(26) /* IP checksum failed */ 245 #define RTASE_RX_UDPF BIT(25) /* UDP/IP checksum failed */ 246 #define RTASE_RX_TCPF BIT(24) /* TCP/IP checksum failed */ 247 #define RTASE_RX_VLAN_TAG BIT(16) /* VLAN tag available */ 248 249 #define RTASE_NUM_DESC 1024 250 #define RTASE_TX_BUDGET_DEFAULT 256 251 #define RTASE_TX_RING_DESC_SIZE (RTASE_NUM_DESC * sizeof(struct rtase_tx_desc)) 252 #define RTASE_RX_RING_DESC_SIZE (RTASE_NUM_DESC * sizeof(union rtase_rx_desc)) 253 #define RTASE_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 254 #define RTASE_TX_START_THRS (2 * RTASE_TX_STOP_THRS) 255 #define RTASE_VLAN_TAG_MASK GENMASK(15, 0) 256 #define RTASE_RX_PKT_SIZE_MASK GENMASK(13, 0) 257 258 #define RTASE_IVEC_NAME_SIZE (IFNAMSIZ + 10) 259 260 struct rtase_int_vector { 261 struct rtase_private *tp; 262 unsigned int irq; 263 char name[RTASE_IVEC_NAME_SIZE]; 264 u16 index; 265 u16 imr_addr; 266 u16 isr_addr; 267 u32 imr; 268 struct list_head ring_list; 269 struct napi_struct napi; 270 int (*poll)(struct napi_struct *napi, int budget); 271 }; 272 273 struct rtase_ring { 274 struct rtase_int_vector *ivec; 275 void *desc; 276 dma_addr_t phy_addr; 277 u32 cur_idx; 278 u32 dirty_idx; 279 u16 index; 280 281 struct sk_buff *skbuff[RTASE_NUM_DESC]; 282 void *data_buf[RTASE_NUM_DESC]; 283 union { 284 u32 len[RTASE_NUM_DESC]; 285 dma_addr_t data_phy_addr[RTASE_NUM_DESC]; 286 } mis; 287 288 struct list_head ring_entry; 289 int (*ring_handler)(struct rtase_ring *ring, int budget); 290 u64 alloc_fail; 291 }; 292 293 struct rtase_stats { 294 u64 tx_dropped; 295 u64 rx_dropped; 296 u64 multicast; 297 u64 rx_errors; 298 u64 rx_length_errors; 299 u64 rx_crc_errors; 300 }; 301 302 struct rtase_private { 303 void __iomem *mmio_addr; 304 u32 sw_flag; 305 306 struct pci_dev *pdev; 307 struct net_device *dev; 308 u32 rx_buf_sz; 309 310 struct page_pool *page_pool; 311 struct rtase_ring tx_ring[RTASE_NUM_TX_QUEUE]; 312 struct rtase_ring rx_ring[RTASE_NUM_RX_QUEUE]; 313 struct rtase_counters *tally_vaddr; 314 dma_addr_t tally_paddr; 315 316 u32 vlan_filter_ctrl; 317 u16 vlan_filter_vid[RTASE_VLAN_FILTER_ENTRY_NUM]; 318 319 struct msix_entry msix_entry[RTASE_NUM_MSIX]; 320 struct rtase_int_vector int_vector[RTASE_NUM_MSIX]; 321 322 struct rtase_stats stats; 323 324 u16 tx_queue_ctrl; 325 u16 func_tx_queue_num; 326 u16 func_rx_queue_num; 327 u16 int_nums; 328 u16 tx_int_mit; 329 u16 rx_int_mit; 330 }; 331 332 #define RTASE_LSO_64K 64000 333 334 #define RTASE_NIC_MAX_PHYS_BUF_COUNT_LSO2 (16 * 4) 335 336 #define RTASE_TCPHO_MASK GENMASK(24, 18) 337 338 #define RTASE_MSS_MASK GENMASK(28, 18) 339 340 #endif /* RTASE_H */ 341