1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169_phy_config.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/phy.h> 14 15 #include "r8169.h" 16 17 typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp, 18 struct phy_device *phydev); 19 20 static void r8168d_modify_extpage(struct phy_device *phydev, int extpage, 21 int reg, u16 mask, u16 val) 22 { 23 int oldpage = phy_select_page(phydev, 0x0007); 24 25 __phy_write(phydev, 0x1e, extpage); 26 __phy_modify(phydev, reg, mask, val); 27 28 phy_restore_page(phydev, oldpage, 0); 29 } 30 31 static void r8168d_phy_param(struct phy_device *phydev, u16 parm, 32 u16 mask, u16 val) 33 { 34 int oldpage = phy_select_page(phydev, 0x0005); 35 36 __phy_write(phydev, 0x05, parm); 37 __phy_modify(phydev, 0x06, mask, val); 38 39 phy_restore_page(phydev, oldpage, 0); 40 } 41 42 static void r8168g_phy_param(struct phy_device *phydev, u16 parm, 43 u16 mask, u16 val) 44 { 45 int oldpage = phy_select_page(phydev, 0x0a43); 46 47 __phy_write(phydev, 0x13, parm); 48 __phy_modify(phydev, 0x14, mask, val); 49 50 phy_restore_page(phydev, oldpage, 0); 51 } 52 53 struct phy_reg { 54 u16 reg; 55 u16 val; 56 }; 57 58 static void __rtl_writephy_batch(struct phy_device *phydev, 59 const struct phy_reg *regs, int len) 60 { 61 phy_lock_mdio_bus(phydev); 62 63 while (len-- > 0) { 64 __phy_write(phydev, regs->reg, regs->val); 65 regs++; 66 } 67 68 phy_unlock_mdio_bus(phydev); 69 } 70 71 #define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a)) 72 73 static void rtl8168f_config_eee_phy(struct phy_device *phydev) 74 { 75 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8)); 76 r8168d_phy_param(phydev, 0x8b85, 0, BIT(13)); 77 } 78 79 static void rtl8168g_config_eee_phy(struct phy_device *phydev) 80 { 81 phy_modify_paged(phydev, 0x0a43, 0x11, 0, BIT(4)); 82 } 83 84 static void rtl8168h_config_eee_phy(struct phy_device *phydev) 85 { 86 rtl8168g_config_eee_phy(phydev); 87 88 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 89 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 90 } 91 92 static void rtl8125_common_config_eee_phy(struct phy_device *phydev) 93 { 94 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 95 phy_modify_paged(phydev, 0xa42, 0x14, 0x0080, 0x0000); 96 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0200, 0x0000); 97 } 98 99 static void rtl8125a_config_eee_phy(struct phy_device *phydev) 100 { 101 rtl8168g_config_eee_phy(phydev); 102 /* disable EEE at 2.5Gbps */ 103 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 104 rtl8125_common_config_eee_phy(phydev); 105 } 106 107 static void rtl8125b_config_eee_phy(struct phy_device *phydev) 108 { 109 rtl8168g_config_eee_phy(phydev); 110 rtl8125_common_config_eee_phy(phydev); 111 } 112 113 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp, 114 struct phy_device *phydev) 115 { 116 static const struct phy_reg phy_reg_init[] = { 117 { 0x1f, 0x0001 }, 118 { 0x06, 0x006e }, 119 { 0x08, 0x0708 }, 120 { 0x15, 0x4000 }, 121 { 0x18, 0x65c7 }, 122 123 { 0x1f, 0x0001 }, 124 { 0x03, 0x00a1 }, 125 { 0x02, 0x0008 }, 126 { 0x01, 0x0120 }, 127 { 0x00, 0x1000 }, 128 { 0x04, 0x0800 }, 129 { 0x04, 0x0000 }, 130 131 { 0x03, 0xff41 }, 132 { 0x02, 0xdf60 }, 133 { 0x01, 0x0140 }, 134 { 0x00, 0x0077 }, 135 { 0x04, 0x7800 }, 136 { 0x04, 0x7000 }, 137 138 { 0x03, 0x802f }, 139 { 0x02, 0x4f02 }, 140 { 0x01, 0x0409 }, 141 { 0x00, 0xf0f9 }, 142 { 0x04, 0x9800 }, 143 { 0x04, 0x9000 }, 144 145 { 0x03, 0xdf01 }, 146 { 0x02, 0xdf20 }, 147 { 0x01, 0xff95 }, 148 { 0x00, 0xba00 }, 149 { 0x04, 0xa800 }, 150 { 0x04, 0xa000 }, 151 152 { 0x03, 0xff41 }, 153 { 0x02, 0xdf20 }, 154 { 0x01, 0x0140 }, 155 { 0x00, 0x00bb }, 156 { 0x04, 0xb800 }, 157 { 0x04, 0xb000 }, 158 159 { 0x03, 0xdf41 }, 160 { 0x02, 0xdc60 }, 161 { 0x01, 0x6340 }, 162 { 0x00, 0x007d }, 163 { 0x04, 0xd800 }, 164 { 0x04, 0xd000 }, 165 166 { 0x03, 0xdf01 }, 167 { 0x02, 0xdf20 }, 168 { 0x01, 0x100a }, 169 { 0x00, 0xa0ff }, 170 { 0x04, 0xf800 }, 171 { 0x04, 0xf000 }, 172 173 { 0x1f, 0x0000 }, 174 { 0x0b, 0x0000 }, 175 { 0x00, 0x9200 } 176 }; 177 178 rtl_writephy_batch(phydev, phy_reg_init); 179 } 180 181 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp, 182 struct phy_device *phydev) 183 { 184 phy_write_paged(phydev, 0x0002, 0x01, 0x90d0); 185 } 186 187 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, 188 struct phy_device *phydev) 189 { 190 static const struct phy_reg phy_reg_init[] = { 191 { 0x1f, 0x0001 }, 192 { 0x04, 0x0000 }, 193 { 0x03, 0x00a1 }, 194 { 0x02, 0x0008 }, 195 { 0x01, 0x0120 }, 196 { 0x00, 0x1000 }, 197 { 0x04, 0x0800 }, 198 { 0x04, 0x9000 }, 199 { 0x03, 0x802f }, 200 { 0x02, 0x4f02 }, 201 { 0x01, 0x0409 }, 202 { 0x00, 0xf099 }, 203 { 0x04, 0x9800 }, 204 { 0x04, 0xa000 }, 205 { 0x03, 0xdf01 }, 206 { 0x02, 0xdf20 }, 207 { 0x01, 0xff95 }, 208 { 0x00, 0xba00 }, 209 { 0x04, 0xa800 }, 210 { 0x04, 0xf000 }, 211 { 0x03, 0xdf01 }, 212 { 0x02, 0xdf20 }, 213 { 0x01, 0x101a }, 214 { 0x00, 0xa0ff }, 215 { 0x04, 0xf800 }, 216 { 0x04, 0x0000 }, 217 { 0x1f, 0x0000 }, 218 219 { 0x1f, 0x0001 }, 220 { 0x10, 0xf41b }, 221 { 0x14, 0xfb54 }, 222 { 0x18, 0xf5c7 }, 223 { 0x1f, 0x0000 }, 224 225 { 0x1f, 0x0001 }, 226 { 0x17, 0x0cc0 }, 227 { 0x1f, 0x0000 } 228 }; 229 230 rtl_writephy_batch(phydev, phy_reg_init); 231 } 232 233 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp, 234 struct phy_device *phydev) 235 { 236 static const struct phy_reg phy_reg_init[] = { 237 { 0x1f, 0x0001 }, 238 { 0x04, 0x0000 }, 239 { 0x03, 0x00a1 }, 240 { 0x02, 0x0008 }, 241 { 0x01, 0x0120 }, 242 { 0x00, 0x1000 }, 243 { 0x04, 0x0800 }, 244 { 0x04, 0x9000 }, 245 { 0x03, 0x802f }, 246 { 0x02, 0x4f02 }, 247 { 0x01, 0x0409 }, 248 { 0x00, 0xf099 }, 249 { 0x04, 0x9800 }, 250 { 0x04, 0xa000 }, 251 { 0x03, 0xdf01 }, 252 { 0x02, 0xdf20 }, 253 { 0x01, 0xff95 }, 254 { 0x00, 0xba00 }, 255 { 0x04, 0xa800 }, 256 { 0x04, 0xf000 }, 257 { 0x03, 0xdf01 }, 258 { 0x02, 0xdf20 }, 259 { 0x01, 0x101a }, 260 { 0x00, 0xa0ff }, 261 { 0x04, 0xf800 }, 262 { 0x04, 0x0000 }, 263 { 0x1f, 0x0000 }, 264 265 { 0x1f, 0x0001 }, 266 { 0x0b, 0x8480 }, 267 { 0x1f, 0x0000 }, 268 269 { 0x1f, 0x0001 }, 270 { 0x18, 0x67c7 }, 271 { 0x04, 0x2000 }, 272 { 0x03, 0x002f }, 273 { 0x02, 0x4360 }, 274 { 0x01, 0x0109 }, 275 { 0x00, 0x3022 }, 276 { 0x04, 0x2800 }, 277 { 0x1f, 0x0000 }, 278 279 { 0x1f, 0x0001 }, 280 { 0x17, 0x0cc0 }, 281 { 0x1f, 0x0000 } 282 }; 283 284 rtl_writephy_batch(phydev, phy_reg_init); 285 } 286 287 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp, 288 struct phy_device *phydev) 289 { 290 phy_write(phydev, 0x1f, 0x0001); 291 phy_set_bits(phydev, 0x16, BIT(0)); 292 phy_write(phydev, 0x10, 0xf41b); 293 phy_write(phydev, 0x1f, 0x0000); 294 } 295 296 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp, 297 struct phy_device *phydev) 298 { 299 phy_write_paged(phydev, 0x0001, 0x10, 0xf41b); 300 } 301 302 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp, 303 struct phy_device *phydev) 304 { 305 phy_write(phydev, 0x1d, 0x0f00); 306 phy_write_paged(phydev, 0x0002, 0x0c, 0x1ec8); 307 } 308 309 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp, 310 struct phy_device *phydev) 311 { 312 phy_set_bits(phydev, 0x14, BIT(5)); 313 phy_set_bits(phydev, 0x0d, BIT(5)); 314 phy_write_paged(phydev, 0x0001, 0x1d, 0x3d98); 315 } 316 317 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp, 318 struct phy_device *phydev) 319 { 320 static const struct phy_reg phy_reg_init[] = { 321 { 0x1f, 0x0001 }, 322 { 0x12, 0x2300 }, 323 { 0x1f, 0x0002 }, 324 { 0x00, 0x88d4 }, 325 { 0x01, 0x82b1 }, 326 { 0x03, 0x7002 }, 327 { 0x08, 0x9e30 }, 328 { 0x09, 0x01f0 }, 329 { 0x0a, 0x5500 }, 330 { 0x0c, 0x00c8 }, 331 { 0x1f, 0x0003 }, 332 { 0x12, 0xc096 }, 333 { 0x16, 0x000a }, 334 { 0x1f, 0x0000 }, 335 { 0x1f, 0x0000 }, 336 { 0x09, 0x2000 }, 337 { 0x09, 0x0000 } 338 }; 339 340 rtl_writephy_batch(phydev, phy_reg_init); 341 342 phy_set_bits(phydev, 0x14, BIT(5)); 343 phy_set_bits(phydev, 0x0d, BIT(5)); 344 } 345 346 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp, 347 struct phy_device *phydev) 348 { 349 static const struct phy_reg phy_reg_init[] = { 350 { 0x1f, 0x0001 }, 351 { 0x12, 0x2300 }, 352 { 0x03, 0x802f }, 353 { 0x02, 0x4f02 }, 354 { 0x01, 0x0409 }, 355 { 0x00, 0xf099 }, 356 { 0x04, 0x9800 }, 357 { 0x04, 0x9000 }, 358 { 0x1d, 0x3d98 }, 359 { 0x1f, 0x0002 }, 360 { 0x0c, 0x7eb8 }, 361 { 0x06, 0x0761 }, 362 { 0x1f, 0x0003 }, 363 { 0x16, 0x0f0a }, 364 { 0x1f, 0x0000 } 365 }; 366 367 rtl_writephy_batch(phydev, phy_reg_init); 368 369 phy_set_bits(phydev, 0x16, BIT(0)); 370 phy_set_bits(phydev, 0x14, BIT(5)); 371 phy_set_bits(phydev, 0x0d, BIT(5)); 372 } 373 374 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp, 375 struct phy_device *phydev) 376 { 377 static const struct phy_reg phy_reg_init[] = { 378 { 0x1f, 0x0001 }, 379 { 0x12, 0x2300 }, 380 { 0x1d, 0x3d98 }, 381 { 0x1f, 0x0002 }, 382 { 0x0c, 0x7eb8 }, 383 { 0x06, 0x5461 }, 384 { 0x1f, 0x0003 }, 385 { 0x16, 0x0f0a }, 386 { 0x1f, 0x0000 } 387 }; 388 389 rtl_writephy_batch(phydev, phy_reg_init); 390 391 phy_set_bits(phydev, 0x16, BIT(0)); 392 phy_set_bits(phydev, 0x14, BIT(5)); 393 phy_set_bits(phydev, 0x0d, BIT(5)); 394 } 395 396 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 397 /* Channel Estimation */ 398 { 0x1f, 0x0001 }, 399 { 0x06, 0x4064 }, 400 { 0x07, 0x2863 }, 401 { 0x08, 0x059c }, 402 { 0x09, 0x26b4 }, 403 { 0x0a, 0x6a19 }, 404 { 0x0b, 0xdcc8 }, 405 { 0x10, 0xf06d }, 406 { 0x14, 0x7f68 }, 407 { 0x18, 0x7fd9 }, 408 { 0x1c, 0xf0ff }, 409 { 0x1d, 0x3d9c }, 410 { 0x1f, 0x0003 }, 411 { 0x12, 0xf49f }, 412 { 0x13, 0x070b }, 413 { 0x1a, 0x05ad }, 414 { 0x14, 0x94c0 }, 415 416 /* 417 * Tx Error Issue 418 * Enhance line driver power 419 */ 420 { 0x1f, 0x0002 }, 421 { 0x06, 0x5561 }, 422 { 0x1f, 0x0005 }, 423 { 0x05, 0x8332 }, 424 { 0x06, 0x5561 }, 425 426 /* 427 * Can not link to 1Gbps with bad cable 428 * Decrease SNR threshold form 21.07dB to 19.04dB 429 */ 430 { 0x1f, 0x0001 }, 431 { 0x17, 0x0cc0 }, 432 433 { 0x1f, 0x0000 }, 434 { 0x0d, 0xf880 } 435 }; 436 437 static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp, 438 struct phy_device *phydev, 439 u16 val) 440 { 441 u16 reg_val; 442 443 phy_write(phydev, 0x1f, 0x0005); 444 phy_write(phydev, 0x05, 0x001b); 445 reg_val = phy_read(phydev, 0x06); 446 phy_write(phydev, 0x1f, 0x0000); 447 448 if (reg_val != val) 449 phydev_warn(phydev, "chipset not ready for firmware\n"); 450 else 451 r8169_apply_firmware(tp); 452 } 453 454 static void rtl8168d_1_common(struct phy_device *phydev) 455 { 456 u16 val; 457 458 phy_write_paged(phydev, 0x0002, 0x05, 0x669a); 459 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x669a); 460 phy_write(phydev, 0x1f, 0x0002); 461 462 val = phy_read(phydev, 0x0d); 463 464 if ((val & 0x00ff) != 0x006c) { 465 static const u16 set[] = { 466 0x0065, 0x0066, 0x0067, 0x0068, 467 0x0069, 0x006a, 0x006b, 0x006c 468 }; 469 int i; 470 471 val &= 0xff00; 472 for (i = 0; i < ARRAY_SIZE(set); i++) 473 phy_write(phydev, 0x0d, val | set[i]); 474 } 475 } 476 477 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp, 478 struct phy_device *phydev) 479 { 480 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 481 482 /* 483 * Rx Error Issue 484 * Fine Tune Switching regulator parameter 485 */ 486 phy_write(phydev, 0x1f, 0x0002); 487 phy_modify(phydev, 0x0b, 0x00ef, 0x0010); 488 phy_modify(phydev, 0x0c, 0x5d00, 0xa200); 489 490 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 491 rtl8168d_1_common(phydev); 492 } else { 493 phy_write_paged(phydev, 0x0002, 0x05, 0x6662); 494 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x6662); 495 } 496 497 /* RSET couple improve */ 498 phy_write(phydev, 0x1f, 0x0002); 499 phy_set_bits(phydev, 0x0d, 0x0300); 500 phy_set_bits(phydev, 0x0f, 0x0010); 501 502 /* Fine tune PLL performance */ 503 phy_write(phydev, 0x1f, 0x0002); 504 phy_modify(phydev, 0x02, 0x0600, 0x0100); 505 phy_clear_bits(phydev, 0x03, 0xe000); 506 phy_write(phydev, 0x1f, 0x0000); 507 508 rtl8168d_apply_firmware_cond(tp, phydev, 0xbf00); 509 } 510 511 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp, 512 struct phy_device *phydev) 513 { 514 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 515 516 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 517 rtl8168d_1_common(phydev); 518 } else { 519 phy_write_paged(phydev, 0x0002, 0x05, 0x2642); 520 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x2642); 521 } 522 523 /* Fine tune PLL performance */ 524 phy_write(phydev, 0x1f, 0x0002); 525 phy_modify(phydev, 0x02, 0x0600, 0x0100); 526 phy_clear_bits(phydev, 0x03, 0xe000); 527 phy_write(phydev, 0x1f, 0x0000); 528 529 /* Switching regulator Slew rate */ 530 phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0017); 531 532 rtl8168d_apply_firmware_cond(tp, phydev, 0xb300); 533 } 534 535 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp, 536 struct phy_device *phydev) 537 { 538 phy_write_paged(phydev, 0x0001, 0x17, 0x0cc0); 539 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0xffff, 0x0040); 540 phy_set_bits(phydev, 0x0d, BIT(5)); 541 } 542 543 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp, 544 struct phy_device *phydev) 545 { 546 static const struct phy_reg phy_reg_init[] = { 547 /* Channel estimation fine tune */ 548 { 0x1f, 0x0001 }, 549 { 0x0b, 0x6c20 }, 550 { 0x07, 0x2872 }, 551 { 0x1c, 0xefff }, 552 { 0x1f, 0x0003 }, 553 { 0x14, 0x6420 }, 554 { 0x1f, 0x0000 }, 555 }; 556 557 r8169_apply_firmware(tp); 558 559 /* Enable Delay cap */ 560 r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896); 561 562 rtl_writephy_batch(phydev, phy_reg_init); 563 564 /* Update PFM & 10M TX idle timer */ 565 r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919); 566 567 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 568 569 /* DCO enable for 10M IDLE Power */ 570 r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006); 571 572 /* For impedance matching */ 573 phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000); 574 575 /* PHY auto speed down */ 576 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050); 577 phy_set_bits(phydev, 0x14, BIT(15)); 578 579 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 580 r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000); 581 582 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000); 583 phy_write_paged(phydev, 0x0006, 0x00, 0x5a00); 584 585 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000); 586 } 587 588 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp, 589 struct phy_device *phydev) 590 { 591 r8169_apply_firmware(tp); 592 593 /* Enable Delay cap */ 594 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 595 596 /* Channel estimation fine tune */ 597 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 598 599 /* Green Setting */ 600 r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222); 601 r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000); 602 r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000); 603 604 /* For 4-corner performance improve */ 605 phy_write(phydev, 0x1f, 0x0005); 606 phy_write(phydev, 0x05, 0x8b80); 607 phy_set_bits(phydev, 0x17, 0x0006); 608 phy_write(phydev, 0x1f, 0x0000); 609 610 /* PHY auto speed down */ 611 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 612 phy_set_bits(phydev, 0x14, BIT(15)); 613 614 /* improve 10M EEE waveform */ 615 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 616 617 /* Improve 2-pair detection performance */ 618 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 619 620 rtl8168f_config_eee_phy(phydev); 621 622 /* Green feature */ 623 phy_write(phydev, 0x1f, 0x0003); 624 phy_set_bits(phydev, 0x19, BIT(0)); 625 phy_set_bits(phydev, 0x10, BIT(10)); 626 phy_write(phydev, 0x1f, 0x0000); 627 phy_modify_paged(phydev, 0x0005, 0x01, 0, BIT(8)); 628 } 629 630 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp, 631 struct phy_device *phydev) 632 { 633 /* For 4-corner performance improve */ 634 r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006); 635 636 /* PHY auto speed down */ 637 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 638 phy_set_bits(phydev, 0x14, BIT(15)); 639 640 /* Improve 10M EEE waveform */ 641 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 642 643 rtl8168f_config_eee_phy(phydev); 644 } 645 646 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp, 647 struct phy_device *phydev) 648 { 649 r8169_apply_firmware(tp); 650 651 /* Channel estimation fine tune */ 652 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 653 654 /* Modify green table for giga & fnet */ 655 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 656 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 657 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 658 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 659 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 660 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb); 661 662 /* Modify green table for 10M */ 663 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 664 665 /* Disable hiimpedance detection (RTCT) */ 666 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 667 668 rtl8168f_hw_phy_config(tp, phydev); 669 670 /* Improve 2-pair detection performance */ 671 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 672 } 673 674 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp, 675 struct phy_device *phydev) 676 { 677 r8169_apply_firmware(tp); 678 679 rtl8168f_hw_phy_config(tp, phydev); 680 } 681 682 static void rtl8411_hw_phy_config(struct rtl8169_private *tp, 683 struct phy_device *phydev) 684 { 685 r8169_apply_firmware(tp); 686 687 rtl8168f_hw_phy_config(tp, phydev); 688 689 /* Improve 2-pair detection performance */ 690 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 691 692 /* Channel estimation fine tune */ 693 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 694 695 /* Modify green table for giga & fnet */ 696 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 697 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 698 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 699 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 700 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 701 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa); 702 703 /* Modify green table for 10M */ 704 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 705 706 /* Disable hiimpedance detection (RTCT) */ 707 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 708 709 /* Modify green table for giga */ 710 r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000); 711 r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000); 712 r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000); 713 r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100); 714 r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000); 715 r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000); 716 r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000); 717 718 /* uc same-seed solution */ 719 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000); 720 721 /* Green feature */ 722 phy_write(phydev, 0x1f, 0x0003); 723 phy_clear_bits(phydev, 0x19, BIT(0)); 724 phy_clear_bits(phydev, 0x10, BIT(10)); 725 phy_write(phydev, 0x1f, 0x0000); 726 } 727 728 static void rtl8168g_disable_aldps(struct phy_device *phydev) 729 { 730 phy_modify_paged(phydev, 0x0a43, 0x10, BIT(2), 0); 731 } 732 733 static void rtl8168g_enable_gphy_10m(struct phy_device *phydev) 734 { 735 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11)); 736 } 737 738 static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev) 739 { 740 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 741 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 742 r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000); 743 phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003); 744 } 745 746 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp, 747 struct phy_device *phydev) 748 { 749 int ret; 750 751 r8169_apply_firmware(tp); 752 753 ret = phy_read_paged(phydev, 0x0a46, 0x10); 754 if (ret & BIT(8)) 755 phy_modify_paged(phydev, 0x0bcc, 0x12, BIT(15), 0); 756 else 757 phy_modify_paged(phydev, 0x0bcc, 0x12, 0, BIT(15)); 758 759 ret = phy_read_paged(phydev, 0x0a46, 0x13); 760 if (ret & BIT(8)) 761 phy_modify_paged(phydev, 0x0c41, 0x15, 0, BIT(1)); 762 else 763 phy_modify_paged(phydev, 0x0c41, 0x15, BIT(1), 0); 764 765 /* Enable PHY auto speed down */ 766 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 767 768 rtl8168g_phy_adjust_10m_aldps(phydev); 769 770 /* EEE auto-fallback function */ 771 phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 772 773 /* Enable UC LPF tune function */ 774 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 775 776 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 777 778 /* Improve SWR Efficiency */ 779 phy_write(phydev, 0x1f, 0x0bcd); 780 phy_write(phydev, 0x14, 0x5065); 781 phy_write(phydev, 0x14, 0xd065); 782 phy_write(phydev, 0x1f, 0x0bc8); 783 phy_write(phydev, 0x11, 0x5655); 784 phy_write(phydev, 0x1f, 0x0bcd); 785 phy_write(phydev, 0x14, 0x1065); 786 phy_write(phydev, 0x14, 0x9065); 787 phy_write(phydev, 0x14, 0x1065); 788 phy_write(phydev, 0x1f, 0x0000); 789 790 rtl8168g_disable_aldps(phydev); 791 rtl8168g_config_eee_phy(phydev); 792 } 793 794 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp, 795 struct phy_device *phydev) 796 { 797 r8169_apply_firmware(tp); 798 rtl8168g_config_eee_phy(phydev); 799 } 800 801 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp, 802 struct phy_device *phydev) 803 { 804 u16 ioffset, rlen; 805 u32 data; 806 807 r8169_apply_firmware(tp); 808 809 /* CHIN EST parameter update */ 810 r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a); 811 812 /* enable R-tune & PGA-retune function */ 813 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 814 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 815 816 rtl8168g_enable_gphy_10m(phydev); 817 818 ioffset = rtl8168h_2_get_adc_bias_ioffset(tp); 819 if (ioffset != 0xffff) 820 phy_write_paged(phydev, 0x0bcf, 0x16, ioffset); 821 822 /* Modify rlen (TX LPF corner frequency) level */ 823 data = phy_read_paged(phydev, 0x0bcd, 0x16); 824 data &= 0x000f; 825 rlen = 0; 826 if (data > 3) 827 rlen = data - 3; 828 data = rlen | (rlen << 4) | (rlen << 8) | (rlen << 12); 829 phy_write_paged(phydev, 0x0bcd, 0x17, data); 830 831 /* disable phy pfm mode */ 832 phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 833 834 /* disable 10m pll off */ 835 phy_modify_paged(phydev, 0x0a43, 0x10, BIT(0), 0); 836 837 rtl8168g_disable_aldps(phydev); 838 rtl8168g_config_eee_phy(phydev); 839 } 840 841 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp, 842 struct phy_device *phydev) 843 { 844 rtl8168g_phy_adjust_10m_aldps(phydev); 845 846 /* Enable UC LPF tune function */ 847 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 848 849 /* Set rg_sel_sdm_rate */ 850 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 851 852 /* Channel estimation parameters */ 853 r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00); 854 r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00); 855 r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500); 856 r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00); 857 r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800); 858 r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00); 859 r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400); 860 r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500); 861 r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800); 862 r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00); 863 r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500); 864 r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100); 865 r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200); 866 r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400); 867 r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00); 868 r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00); 869 r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00); 870 r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00); 871 r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00); 872 r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00); 873 r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400); 874 875 /* Force PWM-mode */ 876 phy_write(phydev, 0x1f, 0x0bcd); 877 phy_write(phydev, 0x14, 0x5065); 878 phy_write(phydev, 0x14, 0xd065); 879 phy_write(phydev, 0x1f, 0x0bc8); 880 phy_write(phydev, 0x12, 0x00ed); 881 phy_write(phydev, 0x1f, 0x0bcd); 882 phy_write(phydev, 0x14, 0x1065); 883 phy_write(phydev, 0x14, 0x9065); 884 phy_write(phydev, 0x14, 0x1065); 885 phy_write(phydev, 0x1f, 0x0000); 886 887 rtl8168g_disable_aldps(phydev); 888 rtl8168g_config_eee_phy(phydev); 889 } 890 891 static void rtl8117_hw_phy_config(struct rtl8169_private *tp, 892 struct phy_device *phydev) 893 { 894 /* CHN EST parameters adjust - fnet */ 895 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800); 896 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00); 897 r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000); 898 899 r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000); 900 r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00); 901 r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600); 902 r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000); 903 r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800); 904 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000); 905 r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000); 906 r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00); 907 r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800); 908 r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000); 909 r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300); 910 r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800); 911 r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200); 912 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800); 913 r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800); 914 r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00); 915 r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300); 916 r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300); 917 918 r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800); 919 920 rtl8168g_enable_gphy_10m(phydev); 921 922 r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400); 923 924 rtl8168g_disable_aldps(phydev); 925 rtl8168h_config_eee_phy(phydev); 926 } 927 928 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp, 929 struct phy_device *phydev) 930 { 931 static const struct phy_reg phy_reg_init[] = { 932 { 0x1f, 0x0003 }, 933 { 0x08, 0x441d }, 934 { 0x01, 0x9100 }, 935 { 0x1f, 0x0000 } 936 }; 937 938 phy_set_bits(phydev, 0x11, BIT(12)); 939 phy_set_bits(phydev, 0x19, BIT(13)); 940 phy_set_bits(phydev, 0x10, BIT(15)); 941 942 rtl_writephy_batch(phydev, phy_reg_init); 943 } 944 945 static void rtl8401_hw_phy_config(struct rtl8169_private *tp, 946 struct phy_device *phydev) 947 { 948 phy_set_bits(phydev, 0x11, BIT(12)); 949 phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0003); 950 } 951 952 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp, 953 struct phy_device *phydev) 954 { 955 /* Disable ALDPS before ram code */ 956 phy_write(phydev, 0x18, 0x0310); 957 msleep(100); 958 959 r8169_apply_firmware(tp); 960 961 phy_write_paged(phydev, 0x0005, 0x1a, 0x0000); 962 phy_write_paged(phydev, 0x0004, 0x1c, 0x0000); 963 phy_write_paged(phydev, 0x0001, 0x15, 0x7701); 964 } 965 966 static void rtl8402_hw_phy_config(struct rtl8169_private *tp, 967 struct phy_device *phydev) 968 { 969 /* Disable ALDPS before setting firmware */ 970 phy_write(phydev, 0x18, 0x0310); 971 msleep(20); 972 973 r8169_apply_firmware(tp); 974 975 /* EEE setting */ 976 phy_write(phydev, 0x1f, 0x0004); 977 phy_write(phydev, 0x10, 0x401f); 978 phy_write(phydev, 0x19, 0x7030); 979 phy_write(phydev, 0x1f, 0x0000); 980 } 981 982 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp, 983 struct phy_device *phydev) 984 { 985 static const struct phy_reg phy_reg_init[] = { 986 { 0x1f, 0x0004 }, 987 { 0x10, 0xc07f }, 988 { 0x19, 0x7030 }, 989 { 0x1f, 0x0000 } 990 }; 991 992 /* Disable ALDPS before ram code */ 993 phy_write(phydev, 0x18, 0x0310); 994 msleep(100); 995 996 r8169_apply_firmware(tp); 997 998 rtl_writephy_batch(phydev, phy_reg_init); 999 } 1000 1001 static void rtl8125_legacy_force_mode(struct phy_device *phydev) 1002 { 1003 phy_modify_paged(phydev, 0xa5b, 0x12, BIT(15), 0); 1004 } 1005 1006 static void rtl8125a_2_hw_phy_config(struct rtl8169_private *tp, 1007 struct phy_device *phydev) 1008 { 1009 int i; 1010 1011 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 1012 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 1013 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 1014 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 1015 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 1016 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 1017 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 1018 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 1019 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 1020 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 1021 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 1022 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 1023 1024 phy_write(phydev, 0x1f, 0x0b87); 1025 phy_write(phydev, 0x16, 0x80a2); 1026 phy_write(phydev, 0x17, 0x0153); 1027 phy_write(phydev, 0x16, 0x809c); 1028 phy_write(phydev, 0x17, 0x0153); 1029 phy_write(phydev, 0x1f, 0x0000); 1030 1031 phy_write(phydev, 0x1f, 0x0a43); 1032 phy_write(phydev, 0x13, 0x81B3); 1033 phy_write(phydev, 0x14, 0x0043); 1034 phy_write(phydev, 0x14, 0x00A7); 1035 phy_write(phydev, 0x14, 0x00D6); 1036 phy_write(phydev, 0x14, 0x00EC); 1037 phy_write(phydev, 0x14, 0x00F6); 1038 phy_write(phydev, 0x14, 0x00FB); 1039 phy_write(phydev, 0x14, 0x00FD); 1040 phy_write(phydev, 0x14, 0x00FF); 1041 phy_write(phydev, 0x14, 0x00BB); 1042 phy_write(phydev, 0x14, 0x0058); 1043 phy_write(phydev, 0x14, 0x0029); 1044 phy_write(phydev, 0x14, 0x0013); 1045 phy_write(phydev, 0x14, 0x0009); 1046 phy_write(phydev, 0x14, 0x0004); 1047 phy_write(phydev, 0x14, 0x0002); 1048 for (i = 0; i < 25; i++) 1049 phy_write(phydev, 0x14, 0x0000); 1050 phy_write(phydev, 0x1f, 0x0000); 1051 1052 r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F); 1053 r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843); 1054 1055 r8169_apply_firmware(tp); 1056 1057 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 1058 1059 r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100); 1060 1061 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 1062 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 1063 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 1064 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 1065 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 1066 rtl8168g_enable_gphy_10m(phydev); 1067 1068 rtl8168g_disable_aldps(phydev); 1069 rtl8125a_config_eee_phy(phydev); 1070 } 1071 1072 static void rtl8125b_hw_phy_config(struct rtl8169_private *tp, 1073 struct phy_device *phydev) 1074 { 1075 r8169_apply_firmware(tp); 1076 rtl8168g_enable_gphy_10m(phydev); 1077 1078 phy_modify_paged(phydev, 0xac4, 0x13, 0x00f0, 0x0090); 1079 phy_modify_paged(phydev, 0xad3, 0x10, 0x0003, 0x0001); 1080 1081 phy_write(phydev, 0x1f, 0x0b87); 1082 phy_write(phydev, 0x16, 0x80f5); 1083 phy_write(phydev, 0x17, 0x760e); 1084 phy_write(phydev, 0x16, 0x8107); 1085 phy_write(phydev, 0x17, 0x360e); 1086 phy_write(phydev, 0x16, 0x8551); 1087 phy_modify(phydev, 0x17, 0xff00, 0x0800); 1088 phy_write(phydev, 0x1f, 0x0000); 1089 1090 phy_modify_paged(phydev, 0xbf0, 0x10, 0xe000, 0xa000); 1091 phy_modify_paged(phydev, 0xbf4, 0x13, 0x0f00, 0x0300); 1092 1093 r8168g_phy_param(phydev, 0x8044, 0xffff, 0x2417); 1094 r8168g_phy_param(phydev, 0x804a, 0xffff, 0x2417); 1095 r8168g_phy_param(phydev, 0x8050, 0xffff, 0x2417); 1096 r8168g_phy_param(phydev, 0x8056, 0xffff, 0x2417); 1097 r8168g_phy_param(phydev, 0x805c, 0xffff, 0x2417); 1098 r8168g_phy_param(phydev, 0x8062, 0xffff, 0x2417); 1099 r8168g_phy_param(phydev, 0x8068, 0xffff, 0x2417); 1100 r8168g_phy_param(phydev, 0x806e, 0xffff, 0x2417); 1101 r8168g_phy_param(phydev, 0x8074, 0xffff, 0x2417); 1102 r8168g_phy_param(phydev, 0x807a, 0xffff, 0x2417); 1103 1104 phy_modify_paged(phydev, 0xa4c, 0x15, 0x0000, 0x0040); 1105 phy_modify_paged(phydev, 0xbf8, 0x12, 0xe000, 0xa000); 1106 1107 rtl8125_legacy_force_mode(phydev); 1108 rtl8168g_disable_aldps(phydev); 1109 rtl8125b_config_eee_phy(phydev); 1110 } 1111 1112 static void rtl8125d_hw_phy_config(struct rtl8169_private *tp, 1113 struct phy_device *phydev) 1114 { 1115 r8169_apply_firmware(tp); 1116 rtl8168g_enable_gphy_10m(phydev); 1117 rtl8125_legacy_force_mode(phydev); 1118 rtl8168g_disable_aldps(phydev); 1119 rtl8125b_config_eee_phy(phydev); 1120 } 1121 1122 static void rtl8126a_hw_phy_config(struct rtl8169_private *tp, 1123 struct phy_device *phydev) 1124 { 1125 r8169_apply_firmware(tp); 1126 rtl8168g_enable_gphy_10m(phydev); 1127 rtl8125_legacy_force_mode(phydev); 1128 rtl8168g_disable_aldps(phydev); 1129 rtl8125_common_config_eee_phy(phydev); 1130 } 1131 1132 void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev, 1133 enum mac_version ver) 1134 { 1135 static const rtl_phy_cfg_fct phy_configs[] = { 1136 /* PCI devices. */ 1137 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 1138 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 1139 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 1140 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 1141 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 1142 /* PCI-E devices. */ 1143 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 1144 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 1145 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 1146 [RTL_GIGA_MAC_VER_10] = NULL, 1147 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 1148 [RTL_GIGA_MAC_VER_14] = rtl8401_hw_phy_config, 1149 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 1150 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 1151 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 1152 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 1153 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 1154 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config, 1155 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 1156 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 1157 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 1158 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 1159 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 1160 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 1161 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 1162 [RTL_GIGA_MAC_VER_31] = NULL, 1163 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 1164 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 1165 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 1166 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 1167 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 1168 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 1169 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 1170 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 1171 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 1172 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 1173 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 1174 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 1175 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 1176 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 1177 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 1178 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config, 1179 [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config, 1180 [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config, 1181 [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config, 1182 [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config, 1183 [RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config, 1184 [RTL_GIGA_MAC_VER_66] = rtl8126a_hw_phy_config, 1185 }; 1186 1187 if (phy_configs[ver]) 1188 phy_configs[ver](tp, phydev); 1189 } 1190