1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169_phy_config.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/phy.h> 14 15 #include "r8169.h" 16 17 typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp, 18 struct phy_device *phydev); 19 20 static void r8168d_modify_extpage(struct phy_device *phydev, int extpage, 21 int reg, u16 mask, u16 val) 22 { 23 int oldpage = phy_select_page(phydev, 0x0007); 24 25 __phy_write(phydev, 0x1e, extpage); 26 __phy_modify(phydev, reg, mask, val); 27 28 phy_restore_page(phydev, oldpage, 0); 29 } 30 31 static void r8168d_phy_param(struct phy_device *phydev, u16 parm, 32 u16 mask, u16 val) 33 { 34 int oldpage = phy_select_page(phydev, 0x0005); 35 36 __phy_write(phydev, 0x05, parm); 37 __phy_modify(phydev, 0x06, mask, val); 38 39 phy_restore_page(phydev, oldpage, 0); 40 } 41 42 static void r8168g_phy_param(struct phy_device *phydev, u16 parm, 43 u16 mask, u16 val) 44 { 45 int oldpage = phy_select_page(phydev, 0x0a43); 46 47 __phy_write(phydev, 0x13, parm); 48 __phy_modify(phydev, 0x14, mask, val); 49 50 phy_restore_page(phydev, oldpage, 0); 51 } 52 53 struct phy_reg { 54 u16 reg; 55 u16 val; 56 }; 57 58 static void __rtl_writephy_batch(struct phy_device *phydev, 59 const struct phy_reg *regs, int len) 60 { 61 phy_lock_mdio_bus(phydev); 62 63 while (len-- > 0) { 64 __phy_write(phydev, regs->reg, regs->val); 65 regs++; 66 } 67 68 phy_unlock_mdio_bus(phydev); 69 } 70 71 #define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a)) 72 73 static void rtl8168f_config_eee_phy(struct phy_device *phydev) 74 { 75 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8)); 76 r8168d_phy_param(phydev, 0x8b85, 0, BIT(13)); 77 } 78 79 static void rtl8168g_config_eee_phy(struct phy_device *phydev) 80 { 81 phy_modify_paged(phydev, 0x0a43, 0x11, 0, BIT(4)); 82 } 83 84 static void rtl8168h_config_eee_phy(struct phy_device *phydev) 85 { 86 rtl8168g_config_eee_phy(phydev); 87 88 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 89 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 90 } 91 92 static void rtl8125a_config_eee_phy(struct phy_device *phydev) 93 { 94 rtl8168h_config_eee_phy(phydev); 95 96 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 97 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 98 } 99 100 static void rtl8125b_config_eee_phy(struct phy_device *phydev) 101 { 102 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 103 phy_modify_paged(phydev, 0xa42, 0x14, 0x0080, 0x0000); 104 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0200, 0x0000); 105 } 106 107 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp, 108 struct phy_device *phydev) 109 { 110 static const struct phy_reg phy_reg_init[] = { 111 { 0x1f, 0x0001 }, 112 { 0x06, 0x006e }, 113 { 0x08, 0x0708 }, 114 { 0x15, 0x4000 }, 115 { 0x18, 0x65c7 }, 116 117 { 0x1f, 0x0001 }, 118 { 0x03, 0x00a1 }, 119 { 0x02, 0x0008 }, 120 { 0x01, 0x0120 }, 121 { 0x00, 0x1000 }, 122 { 0x04, 0x0800 }, 123 { 0x04, 0x0000 }, 124 125 { 0x03, 0xff41 }, 126 { 0x02, 0xdf60 }, 127 { 0x01, 0x0140 }, 128 { 0x00, 0x0077 }, 129 { 0x04, 0x7800 }, 130 { 0x04, 0x7000 }, 131 132 { 0x03, 0x802f }, 133 { 0x02, 0x4f02 }, 134 { 0x01, 0x0409 }, 135 { 0x00, 0xf0f9 }, 136 { 0x04, 0x9800 }, 137 { 0x04, 0x9000 }, 138 139 { 0x03, 0xdf01 }, 140 { 0x02, 0xdf20 }, 141 { 0x01, 0xff95 }, 142 { 0x00, 0xba00 }, 143 { 0x04, 0xa800 }, 144 { 0x04, 0xa000 }, 145 146 { 0x03, 0xff41 }, 147 { 0x02, 0xdf20 }, 148 { 0x01, 0x0140 }, 149 { 0x00, 0x00bb }, 150 { 0x04, 0xb800 }, 151 { 0x04, 0xb000 }, 152 153 { 0x03, 0xdf41 }, 154 { 0x02, 0xdc60 }, 155 { 0x01, 0x6340 }, 156 { 0x00, 0x007d }, 157 { 0x04, 0xd800 }, 158 { 0x04, 0xd000 }, 159 160 { 0x03, 0xdf01 }, 161 { 0x02, 0xdf20 }, 162 { 0x01, 0x100a }, 163 { 0x00, 0xa0ff }, 164 { 0x04, 0xf800 }, 165 { 0x04, 0xf000 }, 166 167 { 0x1f, 0x0000 }, 168 { 0x0b, 0x0000 }, 169 { 0x00, 0x9200 } 170 }; 171 172 rtl_writephy_batch(phydev, phy_reg_init); 173 } 174 175 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp, 176 struct phy_device *phydev) 177 { 178 phy_write_paged(phydev, 0x0002, 0x01, 0x90d0); 179 } 180 181 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, 182 struct phy_device *phydev) 183 { 184 static const struct phy_reg phy_reg_init[] = { 185 { 0x1f, 0x0001 }, 186 { 0x04, 0x0000 }, 187 { 0x03, 0x00a1 }, 188 { 0x02, 0x0008 }, 189 { 0x01, 0x0120 }, 190 { 0x00, 0x1000 }, 191 { 0x04, 0x0800 }, 192 { 0x04, 0x9000 }, 193 { 0x03, 0x802f }, 194 { 0x02, 0x4f02 }, 195 { 0x01, 0x0409 }, 196 { 0x00, 0xf099 }, 197 { 0x04, 0x9800 }, 198 { 0x04, 0xa000 }, 199 { 0x03, 0xdf01 }, 200 { 0x02, 0xdf20 }, 201 { 0x01, 0xff95 }, 202 { 0x00, 0xba00 }, 203 { 0x04, 0xa800 }, 204 { 0x04, 0xf000 }, 205 { 0x03, 0xdf01 }, 206 { 0x02, 0xdf20 }, 207 { 0x01, 0x101a }, 208 { 0x00, 0xa0ff }, 209 { 0x04, 0xf800 }, 210 { 0x04, 0x0000 }, 211 { 0x1f, 0x0000 }, 212 213 { 0x1f, 0x0001 }, 214 { 0x10, 0xf41b }, 215 { 0x14, 0xfb54 }, 216 { 0x18, 0xf5c7 }, 217 { 0x1f, 0x0000 }, 218 219 { 0x1f, 0x0001 }, 220 { 0x17, 0x0cc0 }, 221 { 0x1f, 0x0000 } 222 }; 223 224 rtl_writephy_batch(phydev, phy_reg_init); 225 } 226 227 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp, 228 struct phy_device *phydev) 229 { 230 static const struct phy_reg phy_reg_init[] = { 231 { 0x1f, 0x0001 }, 232 { 0x04, 0x0000 }, 233 { 0x03, 0x00a1 }, 234 { 0x02, 0x0008 }, 235 { 0x01, 0x0120 }, 236 { 0x00, 0x1000 }, 237 { 0x04, 0x0800 }, 238 { 0x04, 0x9000 }, 239 { 0x03, 0x802f }, 240 { 0x02, 0x4f02 }, 241 { 0x01, 0x0409 }, 242 { 0x00, 0xf099 }, 243 { 0x04, 0x9800 }, 244 { 0x04, 0xa000 }, 245 { 0x03, 0xdf01 }, 246 { 0x02, 0xdf20 }, 247 { 0x01, 0xff95 }, 248 { 0x00, 0xba00 }, 249 { 0x04, 0xa800 }, 250 { 0x04, 0xf000 }, 251 { 0x03, 0xdf01 }, 252 { 0x02, 0xdf20 }, 253 { 0x01, 0x101a }, 254 { 0x00, 0xa0ff }, 255 { 0x04, 0xf800 }, 256 { 0x04, 0x0000 }, 257 { 0x1f, 0x0000 }, 258 259 { 0x1f, 0x0001 }, 260 { 0x0b, 0x8480 }, 261 { 0x1f, 0x0000 }, 262 263 { 0x1f, 0x0001 }, 264 { 0x18, 0x67c7 }, 265 { 0x04, 0x2000 }, 266 { 0x03, 0x002f }, 267 { 0x02, 0x4360 }, 268 { 0x01, 0x0109 }, 269 { 0x00, 0x3022 }, 270 { 0x04, 0x2800 }, 271 { 0x1f, 0x0000 }, 272 273 { 0x1f, 0x0001 }, 274 { 0x17, 0x0cc0 }, 275 { 0x1f, 0x0000 } 276 }; 277 278 rtl_writephy_batch(phydev, phy_reg_init); 279 } 280 281 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp, 282 struct phy_device *phydev) 283 { 284 phy_write(phydev, 0x1f, 0x0001); 285 phy_set_bits(phydev, 0x16, BIT(0)); 286 phy_write(phydev, 0x10, 0xf41b); 287 phy_write(phydev, 0x1f, 0x0000); 288 } 289 290 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp, 291 struct phy_device *phydev) 292 { 293 phy_write_paged(phydev, 0x0001, 0x10, 0xf41b); 294 } 295 296 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp, 297 struct phy_device *phydev) 298 { 299 phy_write(phydev, 0x1d, 0x0f00); 300 phy_write_paged(phydev, 0x0002, 0x0c, 0x1ec8); 301 } 302 303 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp, 304 struct phy_device *phydev) 305 { 306 phy_set_bits(phydev, 0x14, BIT(5)); 307 phy_set_bits(phydev, 0x0d, BIT(5)); 308 phy_write_paged(phydev, 0x0001, 0x1d, 0x3d98); 309 } 310 311 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp, 312 struct phy_device *phydev) 313 { 314 static const struct phy_reg phy_reg_init[] = { 315 { 0x1f, 0x0001 }, 316 { 0x12, 0x2300 }, 317 { 0x1f, 0x0002 }, 318 { 0x00, 0x88d4 }, 319 { 0x01, 0x82b1 }, 320 { 0x03, 0x7002 }, 321 { 0x08, 0x9e30 }, 322 { 0x09, 0x01f0 }, 323 { 0x0a, 0x5500 }, 324 { 0x0c, 0x00c8 }, 325 { 0x1f, 0x0003 }, 326 { 0x12, 0xc096 }, 327 { 0x16, 0x000a }, 328 { 0x1f, 0x0000 }, 329 { 0x1f, 0x0000 }, 330 { 0x09, 0x2000 }, 331 { 0x09, 0x0000 } 332 }; 333 334 rtl_writephy_batch(phydev, phy_reg_init); 335 336 phy_set_bits(phydev, 0x14, BIT(5)); 337 phy_set_bits(phydev, 0x0d, BIT(5)); 338 } 339 340 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp, 341 struct phy_device *phydev) 342 { 343 static const struct phy_reg phy_reg_init[] = { 344 { 0x1f, 0x0001 }, 345 { 0x12, 0x2300 }, 346 { 0x03, 0x802f }, 347 { 0x02, 0x4f02 }, 348 { 0x01, 0x0409 }, 349 { 0x00, 0xf099 }, 350 { 0x04, 0x9800 }, 351 { 0x04, 0x9000 }, 352 { 0x1d, 0x3d98 }, 353 { 0x1f, 0x0002 }, 354 { 0x0c, 0x7eb8 }, 355 { 0x06, 0x0761 }, 356 { 0x1f, 0x0003 }, 357 { 0x16, 0x0f0a }, 358 { 0x1f, 0x0000 } 359 }; 360 361 rtl_writephy_batch(phydev, phy_reg_init); 362 363 phy_set_bits(phydev, 0x16, BIT(0)); 364 phy_set_bits(phydev, 0x14, BIT(5)); 365 phy_set_bits(phydev, 0x0d, BIT(5)); 366 } 367 368 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp, 369 struct phy_device *phydev) 370 { 371 static const struct phy_reg phy_reg_init[] = { 372 { 0x1f, 0x0001 }, 373 { 0x12, 0x2300 }, 374 { 0x1d, 0x3d98 }, 375 { 0x1f, 0x0002 }, 376 { 0x0c, 0x7eb8 }, 377 { 0x06, 0x5461 }, 378 { 0x1f, 0x0003 }, 379 { 0x16, 0x0f0a }, 380 { 0x1f, 0x0000 } 381 }; 382 383 rtl_writephy_batch(phydev, phy_reg_init); 384 385 phy_set_bits(phydev, 0x16, BIT(0)); 386 phy_set_bits(phydev, 0x14, BIT(5)); 387 phy_set_bits(phydev, 0x0d, BIT(5)); 388 } 389 390 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 391 /* Channel Estimation */ 392 { 0x1f, 0x0001 }, 393 { 0x06, 0x4064 }, 394 { 0x07, 0x2863 }, 395 { 0x08, 0x059c }, 396 { 0x09, 0x26b4 }, 397 { 0x0a, 0x6a19 }, 398 { 0x0b, 0xdcc8 }, 399 { 0x10, 0xf06d }, 400 { 0x14, 0x7f68 }, 401 { 0x18, 0x7fd9 }, 402 { 0x1c, 0xf0ff }, 403 { 0x1d, 0x3d9c }, 404 { 0x1f, 0x0003 }, 405 { 0x12, 0xf49f }, 406 { 0x13, 0x070b }, 407 { 0x1a, 0x05ad }, 408 { 0x14, 0x94c0 }, 409 410 /* 411 * Tx Error Issue 412 * Enhance line driver power 413 */ 414 { 0x1f, 0x0002 }, 415 { 0x06, 0x5561 }, 416 { 0x1f, 0x0005 }, 417 { 0x05, 0x8332 }, 418 { 0x06, 0x5561 }, 419 420 /* 421 * Can not link to 1Gbps with bad cable 422 * Decrease SNR threshold form 21.07dB to 19.04dB 423 */ 424 { 0x1f, 0x0001 }, 425 { 0x17, 0x0cc0 }, 426 427 { 0x1f, 0x0000 }, 428 { 0x0d, 0xf880 } 429 }; 430 431 static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp, 432 struct phy_device *phydev, 433 u16 val) 434 { 435 u16 reg_val; 436 437 phy_write(phydev, 0x1f, 0x0005); 438 phy_write(phydev, 0x05, 0x001b); 439 reg_val = phy_read(phydev, 0x06); 440 phy_write(phydev, 0x1f, 0x0000); 441 442 if (reg_val != val) 443 phydev_warn(phydev, "chipset not ready for firmware\n"); 444 else 445 r8169_apply_firmware(tp); 446 } 447 448 static void rtl8168d_1_common(struct phy_device *phydev) 449 { 450 u16 val; 451 452 phy_write_paged(phydev, 0x0002, 0x05, 0x669a); 453 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x669a); 454 phy_write(phydev, 0x1f, 0x0002); 455 456 val = phy_read(phydev, 0x0d); 457 458 if ((val & 0x00ff) != 0x006c) { 459 static const u16 set[] = { 460 0x0065, 0x0066, 0x0067, 0x0068, 461 0x0069, 0x006a, 0x006b, 0x006c 462 }; 463 int i; 464 465 val &= 0xff00; 466 for (i = 0; i < ARRAY_SIZE(set); i++) 467 phy_write(phydev, 0x0d, val | set[i]); 468 } 469 } 470 471 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp, 472 struct phy_device *phydev) 473 { 474 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 475 476 /* 477 * Rx Error Issue 478 * Fine Tune Switching regulator parameter 479 */ 480 phy_write(phydev, 0x1f, 0x0002); 481 phy_modify(phydev, 0x0b, 0x00ef, 0x0010); 482 phy_modify(phydev, 0x0c, 0x5d00, 0xa200); 483 484 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 485 rtl8168d_1_common(phydev); 486 } else { 487 phy_write_paged(phydev, 0x0002, 0x05, 0x6662); 488 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x6662); 489 } 490 491 /* RSET couple improve */ 492 phy_write(phydev, 0x1f, 0x0002); 493 phy_set_bits(phydev, 0x0d, 0x0300); 494 phy_set_bits(phydev, 0x0f, 0x0010); 495 496 /* Fine tune PLL performance */ 497 phy_write(phydev, 0x1f, 0x0002); 498 phy_modify(phydev, 0x02, 0x0600, 0x0100); 499 phy_clear_bits(phydev, 0x03, 0xe000); 500 phy_write(phydev, 0x1f, 0x0000); 501 502 rtl8168d_apply_firmware_cond(tp, phydev, 0xbf00); 503 } 504 505 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp, 506 struct phy_device *phydev) 507 { 508 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 509 510 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 511 rtl8168d_1_common(phydev); 512 } else { 513 phy_write_paged(phydev, 0x0002, 0x05, 0x2642); 514 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x2642); 515 } 516 517 /* Fine tune PLL performance */ 518 phy_write(phydev, 0x1f, 0x0002); 519 phy_modify(phydev, 0x02, 0x0600, 0x0100); 520 phy_clear_bits(phydev, 0x03, 0xe000); 521 phy_write(phydev, 0x1f, 0x0000); 522 523 /* Switching regulator Slew rate */ 524 phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0017); 525 526 rtl8168d_apply_firmware_cond(tp, phydev, 0xb300); 527 } 528 529 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp, 530 struct phy_device *phydev) 531 { 532 phy_write_paged(phydev, 0x0001, 0x17, 0x0cc0); 533 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0xffff, 0x0040); 534 phy_set_bits(phydev, 0x0d, BIT(5)); 535 } 536 537 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp, 538 struct phy_device *phydev) 539 { 540 static const struct phy_reg phy_reg_init[] = { 541 /* Channel estimation fine tune */ 542 { 0x1f, 0x0001 }, 543 { 0x0b, 0x6c20 }, 544 { 0x07, 0x2872 }, 545 { 0x1c, 0xefff }, 546 { 0x1f, 0x0003 }, 547 { 0x14, 0x6420 }, 548 { 0x1f, 0x0000 }, 549 }; 550 551 r8169_apply_firmware(tp); 552 553 /* Enable Delay cap */ 554 r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896); 555 556 rtl_writephy_batch(phydev, phy_reg_init); 557 558 /* Update PFM & 10M TX idle timer */ 559 r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919); 560 561 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 562 563 /* DCO enable for 10M IDLE Power */ 564 r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006); 565 566 /* For impedance matching */ 567 phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000); 568 569 /* PHY auto speed down */ 570 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050); 571 phy_set_bits(phydev, 0x14, BIT(15)); 572 573 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 574 r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000); 575 576 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000); 577 phy_write_paged(phydev, 0x0006, 0x00, 0x5a00); 578 579 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000); 580 } 581 582 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp, 583 struct phy_device *phydev) 584 { 585 r8169_apply_firmware(tp); 586 587 /* Enable Delay cap */ 588 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 589 590 /* Channel estimation fine tune */ 591 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 592 593 /* Green Setting */ 594 r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222); 595 r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000); 596 r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000); 597 598 /* For 4-corner performance improve */ 599 phy_write(phydev, 0x1f, 0x0005); 600 phy_write(phydev, 0x05, 0x8b80); 601 phy_set_bits(phydev, 0x17, 0x0006); 602 phy_write(phydev, 0x1f, 0x0000); 603 604 /* PHY auto speed down */ 605 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 606 phy_set_bits(phydev, 0x14, BIT(15)); 607 608 /* improve 10M EEE waveform */ 609 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 610 611 /* Improve 2-pair detection performance */ 612 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 613 614 rtl8168f_config_eee_phy(phydev); 615 616 /* Green feature */ 617 phy_write(phydev, 0x1f, 0x0003); 618 phy_set_bits(phydev, 0x19, BIT(0)); 619 phy_set_bits(phydev, 0x10, BIT(10)); 620 phy_write(phydev, 0x1f, 0x0000); 621 phy_modify_paged(phydev, 0x0005, 0x01, 0, BIT(8)); 622 } 623 624 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp, 625 struct phy_device *phydev) 626 { 627 /* For 4-corner performance improve */ 628 r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006); 629 630 /* PHY auto speed down */ 631 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 632 phy_set_bits(phydev, 0x14, BIT(15)); 633 634 /* Improve 10M EEE waveform */ 635 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 636 637 rtl8168f_config_eee_phy(phydev); 638 } 639 640 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp, 641 struct phy_device *phydev) 642 { 643 r8169_apply_firmware(tp); 644 645 /* Channel estimation fine tune */ 646 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 647 648 /* Modify green table for giga & fnet */ 649 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 650 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 651 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 652 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 653 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 654 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb); 655 656 /* Modify green table for 10M */ 657 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 658 659 /* Disable hiimpedance detection (RTCT) */ 660 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 661 662 rtl8168f_hw_phy_config(tp, phydev); 663 664 /* Improve 2-pair detection performance */ 665 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 666 } 667 668 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp, 669 struct phy_device *phydev) 670 { 671 r8169_apply_firmware(tp); 672 673 rtl8168f_hw_phy_config(tp, phydev); 674 } 675 676 static void rtl8411_hw_phy_config(struct rtl8169_private *tp, 677 struct phy_device *phydev) 678 { 679 r8169_apply_firmware(tp); 680 681 rtl8168f_hw_phy_config(tp, phydev); 682 683 /* Improve 2-pair detection performance */ 684 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 685 686 /* Channel estimation fine tune */ 687 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 688 689 /* Modify green table for giga & fnet */ 690 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 691 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 692 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 693 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 694 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 695 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa); 696 697 /* Modify green table for 10M */ 698 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 699 700 /* Disable hiimpedance detection (RTCT) */ 701 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 702 703 /* Modify green table for giga */ 704 r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000); 705 r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000); 706 r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000); 707 r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100); 708 r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000); 709 r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000); 710 r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000); 711 712 /* uc same-seed solution */ 713 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000); 714 715 /* Green feature */ 716 phy_write(phydev, 0x1f, 0x0003); 717 phy_clear_bits(phydev, 0x19, BIT(0)); 718 phy_clear_bits(phydev, 0x10, BIT(10)); 719 phy_write(phydev, 0x1f, 0x0000); 720 } 721 722 static void rtl8168g_disable_aldps(struct phy_device *phydev) 723 { 724 phy_modify_paged(phydev, 0x0a43, 0x10, BIT(2), 0); 725 } 726 727 static void rtl8168g_enable_gphy_10m(struct phy_device *phydev) 728 { 729 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11)); 730 } 731 732 static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev) 733 { 734 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 735 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 736 r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000); 737 phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003); 738 } 739 740 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp, 741 struct phy_device *phydev) 742 { 743 int ret; 744 745 r8169_apply_firmware(tp); 746 747 ret = phy_read_paged(phydev, 0x0a46, 0x10); 748 if (ret & BIT(8)) 749 phy_modify_paged(phydev, 0x0bcc, 0x12, BIT(15), 0); 750 else 751 phy_modify_paged(phydev, 0x0bcc, 0x12, 0, BIT(15)); 752 753 ret = phy_read_paged(phydev, 0x0a46, 0x13); 754 if (ret & BIT(8)) 755 phy_modify_paged(phydev, 0x0c41, 0x15, 0, BIT(1)); 756 else 757 phy_modify_paged(phydev, 0x0c41, 0x15, BIT(1), 0); 758 759 /* Enable PHY auto speed down */ 760 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 761 762 rtl8168g_phy_adjust_10m_aldps(phydev); 763 764 /* EEE auto-fallback function */ 765 phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 766 767 /* Enable UC LPF tune function */ 768 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 769 770 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 771 772 /* Improve SWR Efficiency */ 773 phy_write(phydev, 0x1f, 0x0bcd); 774 phy_write(phydev, 0x14, 0x5065); 775 phy_write(phydev, 0x14, 0xd065); 776 phy_write(phydev, 0x1f, 0x0bc8); 777 phy_write(phydev, 0x11, 0x5655); 778 phy_write(phydev, 0x1f, 0x0bcd); 779 phy_write(phydev, 0x14, 0x1065); 780 phy_write(phydev, 0x14, 0x9065); 781 phy_write(phydev, 0x14, 0x1065); 782 phy_write(phydev, 0x1f, 0x0000); 783 784 rtl8168g_disable_aldps(phydev); 785 rtl8168g_config_eee_phy(phydev); 786 } 787 788 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp, 789 struct phy_device *phydev) 790 { 791 r8169_apply_firmware(tp); 792 rtl8168g_config_eee_phy(phydev); 793 } 794 795 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp, 796 struct phy_device *phydev) 797 { 798 u16 ioffset, rlen; 799 u32 data; 800 801 r8169_apply_firmware(tp); 802 803 /* CHIN EST parameter update */ 804 r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a); 805 806 /* enable R-tune & PGA-retune function */ 807 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 808 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 809 810 rtl8168g_enable_gphy_10m(phydev); 811 812 ioffset = rtl8168h_2_get_adc_bias_ioffset(tp); 813 if (ioffset != 0xffff) 814 phy_write_paged(phydev, 0x0bcf, 0x16, ioffset); 815 816 /* Modify rlen (TX LPF corner frequency) level */ 817 data = phy_read_paged(phydev, 0x0bcd, 0x16); 818 data &= 0x000f; 819 rlen = 0; 820 if (data > 3) 821 rlen = data - 3; 822 data = rlen | (rlen << 4) | (rlen << 8) | (rlen << 12); 823 phy_write_paged(phydev, 0x0bcd, 0x17, data); 824 825 /* disable phy pfm mode */ 826 phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 827 828 /* disable 10m pll off */ 829 phy_modify_paged(phydev, 0x0a43, 0x10, BIT(0), 0); 830 831 rtl8168g_disable_aldps(phydev); 832 rtl8168g_config_eee_phy(phydev); 833 } 834 835 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp, 836 struct phy_device *phydev) 837 { 838 rtl8168g_phy_adjust_10m_aldps(phydev); 839 840 /* Enable UC LPF tune function */ 841 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 842 843 /* Set rg_sel_sdm_rate */ 844 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 845 846 /* Channel estimation parameters */ 847 r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00); 848 r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00); 849 r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500); 850 r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00); 851 r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800); 852 r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00); 853 r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400); 854 r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500); 855 r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800); 856 r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00); 857 r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500); 858 r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100); 859 r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200); 860 r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400); 861 r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00); 862 r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00); 863 r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00); 864 r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00); 865 r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00); 866 r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00); 867 r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400); 868 869 /* Force PWM-mode */ 870 phy_write(phydev, 0x1f, 0x0bcd); 871 phy_write(phydev, 0x14, 0x5065); 872 phy_write(phydev, 0x14, 0xd065); 873 phy_write(phydev, 0x1f, 0x0bc8); 874 phy_write(phydev, 0x12, 0x00ed); 875 phy_write(phydev, 0x1f, 0x0bcd); 876 phy_write(phydev, 0x14, 0x1065); 877 phy_write(phydev, 0x14, 0x9065); 878 phy_write(phydev, 0x14, 0x1065); 879 phy_write(phydev, 0x1f, 0x0000); 880 881 rtl8168g_disable_aldps(phydev); 882 rtl8168g_config_eee_phy(phydev); 883 } 884 885 static void rtl8117_hw_phy_config(struct rtl8169_private *tp, 886 struct phy_device *phydev) 887 { 888 /* CHN EST parameters adjust - fnet */ 889 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800); 890 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00); 891 r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000); 892 893 r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000); 894 r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00); 895 r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600); 896 r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000); 897 r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800); 898 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000); 899 r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000); 900 r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00); 901 r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800); 902 r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000); 903 r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300); 904 r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800); 905 r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200); 906 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800); 907 r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800); 908 r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00); 909 r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300); 910 r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300); 911 912 r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800); 913 914 rtl8168g_enable_gphy_10m(phydev); 915 916 r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400); 917 918 rtl8168g_disable_aldps(phydev); 919 rtl8168h_config_eee_phy(phydev); 920 } 921 922 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp, 923 struct phy_device *phydev) 924 { 925 static const struct phy_reg phy_reg_init[] = { 926 { 0x1f, 0x0003 }, 927 { 0x08, 0x441d }, 928 { 0x01, 0x9100 }, 929 { 0x1f, 0x0000 } 930 }; 931 932 phy_set_bits(phydev, 0x11, BIT(12)); 933 phy_set_bits(phydev, 0x19, BIT(13)); 934 phy_set_bits(phydev, 0x10, BIT(15)); 935 936 rtl_writephy_batch(phydev, phy_reg_init); 937 } 938 939 static void rtl8401_hw_phy_config(struct rtl8169_private *tp, 940 struct phy_device *phydev) 941 { 942 phy_set_bits(phydev, 0x11, BIT(12)); 943 phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0003); 944 } 945 946 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp, 947 struct phy_device *phydev) 948 { 949 /* Disable ALDPS before ram code */ 950 phy_write(phydev, 0x18, 0x0310); 951 msleep(100); 952 953 r8169_apply_firmware(tp); 954 955 phy_write_paged(phydev, 0x0005, 0x1a, 0x0000); 956 phy_write_paged(phydev, 0x0004, 0x1c, 0x0000); 957 phy_write_paged(phydev, 0x0001, 0x15, 0x7701); 958 } 959 960 static void rtl8402_hw_phy_config(struct rtl8169_private *tp, 961 struct phy_device *phydev) 962 { 963 /* Disable ALDPS before setting firmware */ 964 phy_write(phydev, 0x18, 0x0310); 965 msleep(20); 966 967 r8169_apply_firmware(tp); 968 969 /* EEE setting */ 970 phy_write(phydev, 0x1f, 0x0004); 971 phy_write(phydev, 0x10, 0x401f); 972 phy_write(phydev, 0x19, 0x7030); 973 phy_write(phydev, 0x1f, 0x0000); 974 } 975 976 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp, 977 struct phy_device *phydev) 978 { 979 static const struct phy_reg phy_reg_init[] = { 980 { 0x1f, 0x0004 }, 981 { 0x10, 0xc07f }, 982 { 0x19, 0x7030 }, 983 { 0x1f, 0x0000 } 984 }; 985 986 /* Disable ALDPS before ram code */ 987 phy_write(phydev, 0x18, 0x0310); 988 msleep(100); 989 990 r8169_apply_firmware(tp); 991 992 rtl_writephy_batch(phydev, phy_reg_init); 993 } 994 995 static void rtl8125_legacy_force_mode(struct phy_device *phydev) 996 { 997 phy_modify_paged(phydev, 0xa5b, 0x12, BIT(15), 0); 998 } 999 1000 static void rtl8125a_2_hw_phy_config(struct rtl8169_private *tp, 1001 struct phy_device *phydev) 1002 { 1003 int i; 1004 1005 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 1006 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 1007 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 1008 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 1009 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 1010 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 1011 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 1012 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 1013 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 1014 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 1015 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 1016 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 1017 1018 phy_write(phydev, 0x1f, 0x0b87); 1019 phy_write(phydev, 0x16, 0x80a2); 1020 phy_write(phydev, 0x17, 0x0153); 1021 phy_write(phydev, 0x16, 0x809c); 1022 phy_write(phydev, 0x17, 0x0153); 1023 phy_write(phydev, 0x1f, 0x0000); 1024 1025 phy_write(phydev, 0x1f, 0x0a43); 1026 phy_write(phydev, 0x13, 0x81B3); 1027 phy_write(phydev, 0x14, 0x0043); 1028 phy_write(phydev, 0x14, 0x00A7); 1029 phy_write(phydev, 0x14, 0x00D6); 1030 phy_write(phydev, 0x14, 0x00EC); 1031 phy_write(phydev, 0x14, 0x00F6); 1032 phy_write(phydev, 0x14, 0x00FB); 1033 phy_write(phydev, 0x14, 0x00FD); 1034 phy_write(phydev, 0x14, 0x00FF); 1035 phy_write(phydev, 0x14, 0x00BB); 1036 phy_write(phydev, 0x14, 0x0058); 1037 phy_write(phydev, 0x14, 0x0029); 1038 phy_write(phydev, 0x14, 0x0013); 1039 phy_write(phydev, 0x14, 0x0009); 1040 phy_write(phydev, 0x14, 0x0004); 1041 phy_write(phydev, 0x14, 0x0002); 1042 for (i = 0; i < 25; i++) 1043 phy_write(phydev, 0x14, 0x0000); 1044 phy_write(phydev, 0x1f, 0x0000); 1045 1046 r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F); 1047 r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843); 1048 1049 r8169_apply_firmware(tp); 1050 1051 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 1052 1053 r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100); 1054 1055 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 1056 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 1057 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 1058 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 1059 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 1060 rtl8168g_enable_gphy_10m(phydev); 1061 1062 rtl8168g_disable_aldps(phydev); 1063 rtl8125a_config_eee_phy(phydev); 1064 } 1065 1066 static void rtl8125b_hw_phy_config(struct rtl8169_private *tp, 1067 struct phy_device *phydev) 1068 { 1069 r8169_apply_firmware(tp); 1070 1071 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 1072 phy_modify_paged(phydev, 0xac4, 0x13, 0x00f0, 0x0090); 1073 phy_modify_paged(phydev, 0xad3, 0x10, 0x0003, 0x0001); 1074 1075 phy_write(phydev, 0x1f, 0x0b87); 1076 phy_write(phydev, 0x16, 0x80f5); 1077 phy_write(phydev, 0x17, 0x760e); 1078 phy_write(phydev, 0x16, 0x8107); 1079 phy_write(phydev, 0x17, 0x360e); 1080 phy_write(phydev, 0x16, 0x8551); 1081 phy_modify(phydev, 0x17, 0xff00, 0x0800); 1082 phy_write(phydev, 0x1f, 0x0000); 1083 1084 phy_modify_paged(phydev, 0xbf0, 0x10, 0xe000, 0xa000); 1085 phy_modify_paged(phydev, 0xbf4, 0x13, 0x0f00, 0x0300); 1086 1087 r8168g_phy_param(phydev, 0x8044, 0xffff, 0x2417); 1088 r8168g_phy_param(phydev, 0x804a, 0xffff, 0x2417); 1089 r8168g_phy_param(phydev, 0x8050, 0xffff, 0x2417); 1090 r8168g_phy_param(phydev, 0x8056, 0xffff, 0x2417); 1091 r8168g_phy_param(phydev, 0x805c, 0xffff, 0x2417); 1092 r8168g_phy_param(phydev, 0x8062, 0xffff, 0x2417); 1093 r8168g_phy_param(phydev, 0x8068, 0xffff, 0x2417); 1094 r8168g_phy_param(phydev, 0x806e, 0xffff, 0x2417); 1095 r8168g_phy_param(phydev, 0x8074, 0xffff, 0x2417); 1096 r8168g_phy_param(phydev, 0x807a, 0xffff, 0x2417); 1097 1098 phy_modify_paged(phydev, 0xa4c, 0x15, 0x0000, 0x0040); 1099 phy_modify_paged(phydev, 0xbf8, 0x12, 0xe000, 0xa000); 1100 1101 rtl8125_legacy_force_mode(phydev); 1102 rtl8168g_disable_aldps(phydev); 1103 rtl8125b_config_eee_phy(phydev); 1104 } 1105 1106 static void rtl8125d_hw_phy_config(struct rtl8169_private *tp, 1107 struct phy_device *phydev) 1108 { 1109 r8169_apply_firmware(tp); 1110 rtl8125_legacy_force_mode(phydev); 1111 rtl8168g_disable_aldps(phydev); 1112 rtl8125b_config_eee_phy(phydev); 1113 } 1114 1115 static void rtl8126a_hw_phy_config(struct rtl8169_private *tp, 1116 struct phy_device *phydev) 1117 { 1118 r8169_apply_firmware(tp); 1119 } 1120 1121 void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev, 1122 enum mac_version ver) 1123 { 1124 static const rtl_phy_cfg_fct phy_configs[] = { 1125 /* PCI devices. */ 1126 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 1127 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 1128 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 1129 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 1130 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 1131 /* PCI-E devices. */ 1132 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 1133 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 1134 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 1135 [RTL_GIGA_MAC_VER_10] = NULL, 1136 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 1137 [RTL_GIGA_MAC_VER_14] = rtl8401_hw_phy_config, 1138 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 1139 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 1140 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 1141 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 1142 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 1143 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config, 1144 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 1145 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 1146 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 1147 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 1148 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 1149 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 1150 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 1151 [RTL_GIGA_MAC_VER_31] = NULL, 1152 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 1153 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 1154 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 1155 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 1156 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 1157 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 1158 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 1159 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 1160 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 1161 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 1162 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 1163 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 1164 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 1165 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 1166 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 1167 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config, 1168 [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config, 1169 [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config, 1170 [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config, 1171 [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config, 1172 [RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config, 1173 [RTL_GIGA_MAC_VER_66] = rtl8126a_hw_phy_config, 1174 }; 1175 1176 if (phy_configs[ver]) 1177 phy_configs[ver](tp, phydev); 1178 } 1179