1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169_phy_config.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/phy.h> 14 15 #include "r8169.h" 16 17 typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp, 18 struct phy_device *phydev); 19 20 static void r8168d_modify_extpage(struct phy_device *phydev, int extpage, 21 int reg, u16 mask, u16 val) 22 { 23 int oldpage = phy_select_page(phydev, 0x0007); 24 25 __phy_write(phydev, 0x1e, extpage); 26 __phy_modify(phydev, reg, mask, val); 27 28 phy_restore_page(phydev, oldpage, 0); 29 } 30 31 static void r8168d_phy_param(struct phy_device *phydev, u16 parm, 32 u16 mask, u16 val) 33 { 34 int oldpage = phy_select_page(phydev, 0x0005); 35 36 __phy_write(phydev, 0x05, parm); 37 __phy_modify(phydev, 0x06, mask, val); 38 39 phy_restore_page(phydev, oldpage, 0); 40 } 41 42 static void r8168g_phy_param(struct phy_device *phydev, u16 parm, 43 u16 mask, u16 val) 44 { 45 int oldpage = phy_select_page(phydev, 0x0a43); 46 47 __phy_write(phydev, 0x13, parm); 48 __phy_modify(phydev, 0x14, mask, val); 49 50 phy_restore_page(phydev, oldpage, 0); 51 } 52 53 struct phy_reg { 54 u16 reg; 55 u16 val; 56 }; 57 58 static void __rtl_writephy_batch(struct phy_device *phydev, 59 const struct phy_reg *regs, int len) 60 { 61 phy_lock_mdio_bus(phydev); 62 63 while (len-- > 0) { 64 __phy_write(phydev, regs->reg, regs->val); 65 regs++; 66 } 67 68 phy_unlock_mdio_bus(phydev); 69 } 70 71 #define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a)) 72 73 static void rtl8168f_config_eee_phy(struct phy_device *phydev) 74 { 75 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8)); 76 r8168d_phy_param(phydev, 0x8b85, 0, BIT(13)); 77 } 78 79 static void rtl8168g_config_eee_phy(struct phy_device *phydev) 80 { 81 phy_modify_paged(phydev, 0x0a43, 0x11, 0, BIT(4)); 82 } 83 84 static void rtl8168h_config_eee_phy(struct phy_device *phydev) 85 { 86 rtl8168g_config_eee_phy(phydev); 87 88 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 89 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 90 } 91 92 static void rtl8125_common_config_eee_phy(struct phy_device *phydev) 93 { 94 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 95 phy_modify_paged(phydev, 0xa42, 0x14, 0x0080, 0x0000); 96 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0200, 0x0000); 97 } 98 99 static void rtl8125_config_eee_phy(struct phy_device *phydev) 100 { 101 rtl8168g_config_eee_phy(phydev); 102 rtl8125_common_config_eee_phy(phydev); 103 } 104 105 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp, 106 struct phy_device *phydev) 107 { 108 static const struct phy_reg phy_reg_init[] = { 109 { 0x1f, 0x0001 }, 110 { 0x06, 0x006e }, 111 { 0x08, 0x0708 }, 112 { 0x15, 0x4000 }, 113 { 0x18, 0x65c7 }, 114 115 { 0x1f, 0x0001 }, 116 { 0x03, 0x00a1 }, 117 { 0x02, 0x0008 }, 118 { 0x01, 0x0120 }, 119 { 0x00, 0x1000 }, 120 { 0x04, 0x0800 }, 121 { 0x04, 0x0000 }, 122 123 { 0x03, 0xff41 }, 124 { 0x02, 0xdf60 }, 125 { 0x01, 0x0140 }, 126 { 0x00, 0x0077 }, 127 { 0x04, 0x7800 }, 128 { 0x04, 0x7000 }, 129 130 { 0x03, 0x802f }, 131 { 0x02, 0x4f02 }, 132 { 0x01, 0x0409 }, 133 { 0x00, 0xf0f9 }, 134 { 0x04, 0x9800 }, 135 { 0x04, 0x9000 }, 136 137 { 0x03, 0xdf01 }, 138 { 0x02, 0xdf20 }, 139 { 0x01, 0xff95 }, 140 { 0x00, 0xba00 }, 141 { 0x04, 0xa800 }, 142 { 0x04, 0xa000 }, 143 144 { 0x03, 0xff41 }, 145 { 0x02, 0xdf20 }, 146 { 0x01, 0x0140 }, 147 { 0x00, 0x00bb }, 148 { 0x04, 0xb800 }, 149 { 0x04, 0xb000 }, 150 151 { 0x03, 0xdf41 }, 152 { 0x02, 0xdc60 }, 153 { 0x01, 0x6340 }, 154 { 0x00, 0x007d }, 155 { 0x04, 0xd800 }, 156 { 0x04, 0xd000 }, 157 158 { 0x03, 0xdf01 }, 159 { 0x02, 0xdf20 }, 160 { 0x01, 0x100a }, 161 { 0x00, 0xa0ff }, 162 { 0x04, 0xf800 }, 163 { 0x04, 0xf000 }, 164 165 { 0x1f, 0x0000 }, 166 { 0x0b, 0x0000 }, 167 { 0x00, 0x9200 } 168 }; 169 170 rtl_writephy_batch(phydev, phy_reg_init); 171 } 172 173 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp, 174 struct phy_device *phydev) 175 { 176 phy_write_paged(phydev, 0x0002, 0x01, 0x90d0); 177 } 178 179 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, 180 struct phy_device *phydev) 181 { 182 static const struct phy_reg phy_reg_init[] = { 183 { 0x1f, 0x0001 }, 184 { 0x04, 0x0000 }, 185 { 0x03, 0x00a1 }, 186 { 0x02, 0x0008 }, 187 { 0x01, 0x0120 }, 188 { 0x00, 0x1000 }, 189 { 0x04, 0x0800 }, 190 { 0x04, 0x9000 }, 191 { 0x03, 0x802f }, 192 { 0x02, 0x4f02 }, 193 { 0x01, 0x0409 }, 194 { 0x00, 0xf099 }, 195 { 0x04, 0x9800 }, 196 { 0x04, 0xa000 }, 197 { 0x03, 0xdf01 }, 198 { 0x02, 0xdf20 }, 199 { 0x01, 0xff95 }, 200 { 0x00, 0xba00 }, 201 { 0x04, 0xa800 }, 202 { 0x04, 0xf000 }, 203 { 0x03, 0xdf01 }, 204 { 0x02, 0xdf20 }, 205 { 0x01, 0x101a }, 206 { 0x00, 0xa0ff }, 207 { 0x04, 0xf800 }, 208 { 0x04, 0x0000 }, 209 { 0x1f, 0x0000 }, 210 211 { 0x1f, 0x0001 }, 212 { 0x10, 0xf41b }, 213 { 0x14, 0xfb54 }, 214 { 0x18, 0xf5c7 }, 215 { 0x1f, 0x0000 }, 216 217 { 0x1f, 0x0001 }, 218 { 0x17, 0x0cc0 }, 219 { 0x1f, 0x0000 } 220 }; 221 222 rtl_writephy_batch(phydev, phy_reg_init); 223 } 224 225 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp, 226 struct phy_device *phydev) 227 { 228 static const struct phy_reg phy_reg_init[] = { 229 { 0x1f, 0x0001 }, 230 { 0x04, 0x0000 }, 231 { 0x03, 0x00a1 }, 232 { 0x02, 0x0008 }, 233 { 0x01, 0x0120 }, 234 { 0x00, 0x1000 }, 235 { 0x04, 0x0800 }, 236 { 0x04, 0x9000 }, 237 { 0x03, 0x802f }, 238 { 0x02, 0x4f02 }, 239 { 0x01, 0x0409 }, 240 { 0x00, 0xf099 }, 241 { 0x04, 0x9800 }, 242 { 0x04, 0xa000 }, 243 { 0x03, 0xdf01 }, 244 { 0x02, 0xdf20 }, 245 { 0x01, 0xff95 }, 246 { 0x00, 0xba00 }, 247 { 0x04, 0xa800 }, 248 { 0x04, 0xf000 }, 249 { 0x03, 0xdf01 }, 250 { 0x02, 0xdf20 }, 251 { 0x01, 0x101a }, 252 { 0x00, 0xa0ff }, 253 { 0x04, 0xf800 }, 254 { 0x04, 0x0000 }, 255 { 0x1f, 0x0000 }, 256 257 { 0x1f, 0x0001 }, 258 { 0x0b, 0x8480 }, 259 { 0x1f, 0x0000 }, 260 261 { 0x1f, 0x0001 }, 262 { 0x18, 0x67c7 }, 263 { 0x04, 0x2000 }, 264 { 0x03, 0x002f }, 265 { 0x02, 0x4360 }, 266 { 0x01, 0x0109 }, 267 { 0x00, 0x3022 }, 268 { 0x04, 0x2800 }, 269 { 0x1f, 0x0000 }, 270 271 { 0x1f, 0x0001 }, 272 { 0x17, 0x0cc0 }, 273 { 0x1f, 0x0000 } 274 }; 275 276 rtl_writephy_batch(phydev, phy_reg_init); 277 } 278 279 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp, 280 struct phy_device *phydev) 281 { 282 phy_write_paged(phydev, 0x0001, 0x10, 0xf41b); 283 } 284 285 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp, 286 struct phy_device *phydev) 287 { 288 phy_write(phydev, 0x1d, 0x0f00); 289 phy_write_paged(phydev, 0x0002, 0x0c, 0x1ec8); 290 } 291 292 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp, 293 struct phy_device *phydev) 294 { 295 phy_set_bits(phydev, 0x14, BIT(5)); 296 phy_set_bits(phydev, 0x0d, BIT(5)); 297 phy_write_paged(phydev, 0x0001, 0x1d, 0x3d98); 298 } 299 300 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp, 301 struct phy_device *phydev) 302 { 303 static const struct phy_reg phy_reg_init[] = { 304 { 0x1f, 0x0001 }, 305 { 0x12, 0x2300 }, 306 { 0x1f, 0x0002 }, 307 { 0x00, 0x88d4 }, 308 { 0x01, 0x82b1 }, 309 { 0x03, 0x7002 }, 310 { 0x08, 0x9e30 }, 311 { 0x09, 0x01f0 }, 312 { 0x0a, 0x5500 }, 313 { 0x0c, 0x00c8 }, 314 { 0x1f, 0x0003 }, 315 { 0x12, 0xc096 }, 316 { 0x16, 0x000a }, 317 { 0x1f, 0x0000 }, 318 { 0x1f, 0x0000 }, 319 { 0x09, 0x2000 }, 320 { 0x09, 0x0000 } 321 }; 322 323 rtl_writephy_batch(phydev, phy_reg_init); 324 325 phy_set_bits(phydev, 0x14, BIT(5)); 326 phy_set_bits(phydev, 0x0d, BIT(5)); 327 } 328 329 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp, 330 struct phy_device *phydev) 331 { 332 static const struct phy_reg phy_reg_init[] = { 333 { 0x1f, 0x0001 }, 334 { 0x12, 0x2300 }, 335 { 0x03, 0x802f }, 336 { 0x02, 0x4f02 }, 337 { 0x01, 0x0409 }, 338 { 0x00, 0xf099 }, 339 { 0x04, 0x9800 }, 340 { 0x04, 0x9000 }, 341 { 0x1d, 0x3d98 }, 342 { 0x1f, 0x0002 }, 343 { 0x0c, 0x7eb8 }, 344 { 0x06, 0x0761 }, 345 { 0x1f, 0x0003 }, 346 { 0x16, 0x0f0a }, 347 { 0x1f, 0x0000 } 348 }; 349 350 rtl_writephy_batch(phydev, phy_reg_init); 351 352 phy_set_bits(phydev, 0x16, BIT(0)); 353 phy_set_bits(phydev, 0x14, BIT(5)); 354 phy_set_bits(phydev, 0x0d, BIT(5)); 355 } 356 357 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp, 358 struct phy_device *phydev) 359 { 360 static const struct phy_reg phy_reg_init[] = { 361 { 0x1f, 0x0001 }, 362 { 0x12, 0x2300 }, 363 { 0x1d, 0x3d98 }, 364 { 0x1f, 0x0002 }, 365 { 0x0c, 0x7eb8 }, 366 { 0x06, 0x5461 }, 367 { 0x1f, 0x0003 }, 368 { 0x16, 0x0f0a }, 369 { 0x1f, 0x0000 } 370 }; 371 372 rtl_writephy_batch(phydev, phy_reg_init); 373 374 phy_set_bits(phydev, 0x16, BIT(0)); 375 phy_set_bits(phydev, 0x14, BIT(5)); 376 phy_set_bits(phydev, 0x0d, BIT(5)); 377 } 378 379 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 380 /* Channel Estimation */ 381 { 0x1f, 0x0001 }, 382 { 0x06, 0x4064 }, 383 { 0x07, 0x2863 }, 384 { 0x08, 0x059c }, 385 { 0x09, 0x26b4 }, 386 { 0x0a, 0x6a19 }, 387 { 0x0b, 0xdcc8 }, 388 { 0x10, 0xf06d }, 389 { 0x14, 0x7f68 }, 390 { 0x18, 0x7fd9 }, 391 { 0x1c, 0xf0ff }, 392 { 0x1d, 0x3d9c }, 393 { 0x1f, 0x0003 }, 394 { 0x12, 0xf49f }, 395 { 0x13, 0x070b }, 396 { 0x1a, 0x05ad }, 397 { 0x14, 0x94c0 }, 398 399 /* 400 * Tx Error Issue 401 * Enhance line driver power 402 */ 403 { 0x1f, 0x0002 }, 404 { 0x06, 0x5561 }, 405 { 0x1f, 0x0005 }, 406 { 0x05, 0x8332 }, 407 { 0x06, 0x5561 }, 408 409 /* 410 * Can not link to 1Gbps with bad cable 411 * Decrease SNR threshold form 21.07dB to 19.04dB 412 */ 413 { 0x1f, 0x0001 }, 414 { 0x17, 0x0cc0 }, 415 416 { 0x1f, 0x0000 }, 417 { 0x0d, 0xf880 } 418 }; 419 420 static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp, 421 struct phy_device *phydev, 422 u16 val) 423 { 424 u16 reg_val; 425 426 phy_write(phydev, 0x1f, 0x0005); 427 phy_write(phydev, 0x05, 0x001b); 428 reg_val = phy_read(phydev, 0x06); 429 phy_write(phydev, 0x1f, 0x0000); 430 431 if (reg_val != val) 432 phydev_warn(phydev, "chipset not ready for firmware\n"); 433 else 434 r8169_apply_firmware(tp); 435 } 436 437 static void rtl8168d_1_common(struct phy_device *phydev) 438 { 439 u16 val; 440 441 phy_write_paged(phydev, 0x0002, 0x05, 0x669a); 442 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x669a); 443 phy_write(phydev, 0x1f, 0x0002); 444 445 val = phy_read(phydev, 0x0d); 446 447 if ((val & 0x00ff) != 0x006c) { 448 static const u16 set[] = { 449 0x0065, 0x0066, 0x0067, 0x0068, 450 0x0069, 0x006a, 0x006b, 0x006c 451 }; 452 int i; 453 454 val &= 0xff00; 455 for (i = 0; i < ARRAY_SIZE(set); i++) 456 phy_write(phydev, 0x0d, val | set[i]); 457 } 458 } 459 460 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp, 461 struct phy_device *phydev) 462 { 463 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 464 465 /* 466 * Rx Error Issue 467 * Fine Tune Switching regulator parameter 468 */ 469 phy_write(phydev, 0x1f, 0x0002); 470 phy_modify(phydev, 0x0b, 0x00ef, 0x0010); 471 phy_modify(phydev, 0x0c, 0x5d00, 0xa200); 472 473 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 474 rtl8168d_1_common(phydev); 475 } else { 476 phy_write_paged(phydev, 0x0002, 0x05, 0x6662); 477 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x6662); 478 } 479 480 /* RSET couple improve */ 481 phy_write(phydev, 0x1f, 0x0002); 482 phy_set_bits(phydev, 0x0d, 0x0300); 483 phy_set_bits(phydev, 0x0f, 0x0010); 484 485 /* Fine tune PLL performance */ 486 phy_write(phydev, 0x1f, 0x0002); 487 phy_modify(phydev, 0x02, 0x0600, 0x0100); 488 phy_clear_bits(phydev, 0x03, 0xe000); 489 phy_write(phydev, 0x1f, 0x0000); 490 491 rtl8168d_apply_firmware_cond(tp, phydev, 0xbf00); 492 } 493 494 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp, 495 struct phy_device *phydev) 496 { 497 rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0); 498 499 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 500 rtl8168d_1_common(phydev); 501 } else { 502 phy_write_paged(phydev, 0x0002, 0x05, 0x2642); 503 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x2642); 504 } 505 506 /* Fine tune PLL performance */ 507 phy_write(phydev, 0x1f, 0x0002); 508 phy_modify(phydev, 0x02, 0x0600, 0x0100); 509 phy_clear_bits(phydev, 0x03, 0xe000); 510 phy_write(phydev, 0x1f, 0x0000); 511 512 /* Switching regulator Slew rate */ 513 phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0017); 514 515 rtl8168d_apply_firmware_cond(tp, phydev, 0xb300); 516 } 517 518 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp, 519 struct phy_device *phydev) 520 { 521 phy_write_paged(phydev, 0x0001, 0x17, 0x0cc0); 522 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0xffff, 0x0040); 523 phy_set_bits(phydev, 0x0d, BIT(5)); 524 } 525 526 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp, 527 struct phy_device *phydev) 528 { 529 static const struct phy_reg phy_reg_init[] = { 530 /* Channel estimation fine tune */ 531 { 0x1f, 0x0001 }, 532 { 0x0b, 0x6c20 }, 533 { 0x07, 0x2872 }, 534 { 0x1c, 0xefff }, 535 { 0x1f, 0x0003 }, 536 { 0x14, 0x6420 }, 537 { 0x1f, 0x0000 }, 538 }; 539 540 r8169_apply_firmware(tp); 541 542 /* Enable Delay cap */ 543 r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896); 544 545 rtl_writephy_batch(phydev, phy_reg_init); 546 547 /* Update PFM & 10M TX idle timer */ 548 r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919); 549 550 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 551 552 /* DCO enable for 10M IDLE Power */ 553 r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006); 554 555 /* For impedance matching */ 556 phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000); 557 558 /* PHY auto speed down */ 559 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050); 560 phy_set_bits(phydev, 0x14, BIT(15)); 561 562 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 563 r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000); 564 565 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000); 566 phy_write_paged(phydev, 0x0006, 0x00, 0x5a00); 567 568 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000); 569 } 570 571 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp, 572 struct phy_device *phydev) 573 { 574 r8169_apply_firmware(tp); 575 576 /* Enable Delay cap */ 577 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 578 579 /* Channel estimation fine tune */ 580 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 581 582 /* Green Setting */ 583 r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222); 584 r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000); 585 r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000); 586 587 /* For 4-corner performance improve */ 588 phy_write(phydev, 0x1f, 0x0005); 589 phy_write(phydev, 0x05, 0x8b80); 590 phy_set_bits(phydev, 0x17, 0x0006); 591 phy_write(phydev, 0x1f, 0x0000); 592 593 /* PHY auto speed down */ 594 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 595 phy_set_bits(phydev, 0x14, BIT(15)); 596 597 /* improve 10M EEE waveform */ 598 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 599 600 /* Improve 2-pair detection performance */ 601 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 602 603 rtl8168f_config_eee_phy(phydev); 604 605 /* Green feature */ 606 phy_write(phydev, 0x1f, 0x0003); 607 phy_set_bits(phydev, 0x19, BIT(0)); 608 phy_set_bits(phydev, 0x10, BIT(10)); 609 phy_write(phydev, 0x1f, 0x0000); 610 phy_modify_paged(phydev, 0x0005, 0x01, 0, BIT(8)); 611 } 612 613 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp, 614 struct phy_device *phydev) 615 { 616 /* For 4-corner performance improve */ 617 r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006); 618 619 /* PHY auto speed down */ 620 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 621 phy_set_bits(phydev, 0x14, BIT(15)); 622 623 /* Improve 10M EEE waveform */ 624 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 625 626 rtl8168f_config_eee_phy(phydev); 627 } 628 629 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp, 630 struct phy_device *phydev) 631 { 632 r8169_apply_firmware(tp); 633 634 /* Channel estimation fine tune */ 635 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 636 637 /* Modify green table for giga & fnet */ 638 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 639 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 640 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 641 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 642 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 643 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb); 644 645 /* Modify green table for 10M */ 646 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 647 648 /* Disable hiimpedance detection (RTCT) */ 649 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 650 651 rtl8168f_hw_phy_config(tp, phydev); 652 653 /* Improve 2-pair detection performance */ 654 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 655 } 656 657 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp, 658 struct phy_device *phydev) 659 { 660 r8169_apply_firmware(tp); 661 662 rtl8168f_hw_phy_config(tp, phydev); 663 } 664 665 static void rtl8411_hw_phy_config(struct rtl8169_private *tp, 666 struct phy_device *phydev) 667 { 668 r8169_apply_firmware(tp); 669 670 rtl8168f_hw_phy_config(tp, phydev); 671 672 /* Improve 2-pair detection performance */ 673 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 674 675 /* Channel estimation fine tune */ 676 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 677 678 /* Modify green table for giga & fnet */ 679 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 680 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 681 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 682 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 683 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 684 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa); 685 686 /* Modify green table for 10M */ 687 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 688 689 /* Disable hiimpedance detection (RTCT) */ 690 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 691 692 /* Modify green table for giga */ 693 r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000); 694 r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000); 695 r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000); 696 r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100); 697 r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000); 698 r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000); 699 r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000); 700 701 /* uc same-seed solution */ 702 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000); 703 704 /* Green feature */ 705 phy_write(phydev, 0x1f, 0x0003); 706 phy_clear_bits(phydev, 0x19, BIT(0)); 707 phy_clear_bits(phydev, 0x10, BIT(10)); 708 phy_write(phydev, 0x1f, 0x0000); 709 } 710 711 static void rtl8168g_disable_aldps(struct phy_device *phydev) 712 { 713 phy_modify_paged(phydev, 0x0a43, 0x10, BIT(2), 0); 714 } 715 716 static void rtl8168g_enable_gphy_10m(struct phy_device *phydev) 717 { 718 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11)); 719 } 720 721 static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev) 722 { 723 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 724 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 725 r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000); 726 phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003); 727 } 728 729 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp, 730 struct phy_device *phydev) 731 { 732 int ret; 733 734 r8169_apply_firmware(tp); 735 736 ret = phy_read_paged(phydev, 0x0a46, 0x10); 737 if (ret & BIT(8)) 738 phy_modify_paged(phydev, 0x0bcc, 0x12, BIT(15), 0); 739 else 740 phy_modify_paged(phydev, 0x0bcc, 0x12, 0, BIT(15)); 741 742 ret = phy_read_paged(phydev, 0x0a46, 0x13); 743 if (ret & BIT(8)) 744 phy_modify_paged(phydev, 0x0c41, 0x15, 0, BIT(1)); 745 else 746 phy_modify_paged(phydev, 0x0c41, 0x15, BIT(1), 0); 747 748 /* Enable PHY auto speed down */ 749 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 750 751 rtl8168g_phy_adjust_10m_aldps(phydev); 752 753 /* EEE auto-fallback function */ 754 phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 755 756 /* Enable UC LPF tune function */ 757 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 758 759 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 760 761 /* Improve SWR Efficiency */ 762 phy_write(phydev, 0x1f, 0x0bcd); 763 phy_write(phydev, 0x14, 0x5065); 764 phy_write(phydev, 0x14, 0xd065); 765 phy_write(phydev, 0x1f, 0x0bc8); 766 phy_write(phydev, 0x11, 0x5655); 767 phy_write(phydev, 0x1f, 0x0bcd); 768 phy_write(phydev, 0x14, 0x1065); 769 phy_write(phydev, 0x14, 0x9065); 770 phy_write(phydev, 0x14, 0x1065); 771 phy_write(phydev, 0x1f, 0x0000); 772 773 rtl8168g_disable_aldps(phydev); 774 rtl8168g_config_eee_phy(phydev); 775 } 776 777 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp, 778 struct phy_device *phydev) 779 { 780 r8169_apply_firmware(tp); 781 rtl8168g_config_eee_phy(phydev); 782 } 783 784 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp, 785 struct phy_device *phydev) 786 { 787 u16 ioffset, rlen; 788 u32 data; 789 790 r8169_apply_firmware(tp); 791 792 /* CHIN EST parameter update */ 793 r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a); 794 795 /* enable R-tune & PGA-retune function */ 796 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 797 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 798 799 rtl8168g_enable_gphy_10m(phydev); 800 801 ioffset = rtl8168h_2_get_adc_bias_ioffset(tp); 802 if (ioffset != 0xffff) 803 phy_write_paged(phydev, 0x0bcf, 0x16, ioffset); 804 805 /* Modify rlen (TX LPF corner frequency) level */ 806 data = phy_read_paged(phydev, 0x0bcd, 0x16); 807 data &= 0x000f; 808 rlen = 0; 809 if (data > 3) 810 rlen = data - 3; 811 data = rlen | (rlen << 4) | (rlen << 8) | (rlen << 12); 812 phy_write_paged(phydev, 0x0bcd, 0x17, data); 813 814 /* disable phy pfm mode */ 815 phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 816 817 /* disable 10m pll off */ 818 phy_modify_paged(phydev, 0x0a43, 0x10, BIT(0), 0); 819 820 rtl8168g_disable_aldps(phydev); 821 rtl8168g_config_eee_phy(phydev); 822 } 823 824 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp, 825 struct phy_device *phydev) 826 { 827 rtl8168g_phy_adjust_10m_aldps(phydev); 828 829 /* Enable UC LPF tune function */ 830 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 831 832 /* Set rg_sel_sdm_rate */ 833 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 834 835 /* Channel estimation parameters */ 836 r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00); 837 r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00); 838 r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500); 839 r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00); 840 r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800); 841 r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00); 842 r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400); 843 r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500); 844 r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800); 845 r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00); 846 r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500); 847 r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100); 848 r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200); 849 r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400); 850 r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00); 851 r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00); 852 r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00); 853 r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00); 854 r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00); 855 r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00); 856 r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400); 857 858 /* Force PWM-mode */ 859 phy_write(phydev, 0x1f, 0x0bcd); 860 phy_write(phydev, 0x14, 0x5065); 861 phy_write(phydev, 0x14, 0xd065); 862 phy_write(phydev, 0x1f, 0x0bc8); 863 phy_write(phydev, 0x12, 0x00ed); 864 phy_write(phydev, 0x1f, 0x0bcd); 865 phy_write(phydev, 0x14, 0x1065); 866 phy_write(phydev, 0x14, 0x9065); 867 phy_write(phydev, 0x14, 0x1065); 868 phy_write(phydev, 0x1f, 0x0000); 869 870 rtl8168g_disable_aldps(phydev); 871 rtl8168g_config_eee_phy(phydev); 872 } 873 874 static void rtl8117_hw_phy_config(struct rtl8169_private *tp, 875 struct phy_device *phydev) 876 { 877 /* CHN EST parameters adjust - fnet */ 878 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800); 879 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00); 880 r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000); 881 882 r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000); 883 r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00); 884 r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600); 885 r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000); 886 r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800); 887 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000); 888 r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000); 889 r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00); 890 r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800); 891 r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000); 892 r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300); 893 r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800); 894 r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200); 895 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800); 896 r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800); 897 r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00); 898 r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300); 899 r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300); 900 901 r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800); 902 903 rtl8168g_enable_gphy_10m(phydev); 904 905 r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400); 906 907 rtl8168g_disable_aldps(phydev); 908 rtl8168h_config_eee_phy(phydev); 909 } 910 911 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp, 912 struct phy_device *phydev) 913 { 914 static const struct phy_reg phy_reg_init[] = { 915 { 0x1f, 0x0003 }, 916 { 0x08, 0x441d }, 917 { 0x01, 0x9100 }, 918 { 0x1f, 0x0000 } 919 }; 920 921 phy_set_bits(phydev, 0x11, BIT(12)); 922 phy_set_bits(phydev, 0x19, BIT(13)); 923 phy_set_bits(phydev, 0x10, BIT(15)); 924 925 rtl_writephy_batch(phydev, phy_reg_init); 926 } 927 928 static void rtl8401_hw_phy_config(struct rtl8169_private *tp, 929 struct phy_device *phydev) 930 { 931 phy_set_bits(phydev, 0x11, BIT(12)); 932 phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0003); 933 } 934 935 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp, 936 struct phy_device *phydev) 937 { 938 /* Disable ALDPS before ram code */ 939 phy_write(phydev, 0x18, 0x0310); 940 msleep(100); 941 942 r8169_apply_firmware(tp); 943 944 phy_write_paged(phydev, 0x0005, 0x1a, 0x0000); 945 phy_write_paged(phydev, 0x0004, 0x1c, 0x0000); 946 phy_write_paged(phydev, 0x0001, 0x15, 0x7701); 947 } 948 949 static void rtl8402_hw_phy_config(struct rtl8169_private *tp, 950 struct phy_device *phydev) 951 { 952 /* Disable ALDPS before setting firmware */ 953 phy_write(phydev, 0x18, 0x0310); 954 msleep(20); 955 956 r8169_apply_firmware(tp); 957 958 /* EEE setting */ 959 phy_write(phydev, 0x1f, 0x0004); 960 phy_write(phydev, 0x10, 0x401f); 961 phy_write(phydev, 0x19, 0x7030); 962 phy_write(phydev, 0x1f, 0x0000); 963 } 964 965 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp, 966 struct phy_device *phydev) 967 { 968 static const struct phy_reg phy_reg_init[] = { 969 { 0x1f, 0x0004 }, 970 { 0x10, 0xc07f }, 971 { 0x19, 0x7030 }, 972 { 0x1f, 0x0000 } 973 }; 974 975 /* Disable ALDPS before ram code */ 976 phy_write(phydev, 0x18, 0x0310); 977 msleep(100); 978 979 r8169_apply_firmware(tp); 980 981 rtl_writephy_batch(phydev, phy_reg_init); 982 } 983 984 static void rtl8125_legacy_force_mode(struct phy_device *phydev) 985 { 986 phy_modify_paged(phydev, 0xa5b, 0x12, BIT(15), 0); 987 } 988 989 static void rtl8125a_2_hw_phy_config(struct rtl8169_private *tp, 990 struct phy_device *phydev) 991 { 992 int i; 993 994 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 995 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 996 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 997 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 998 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 999 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 1000 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 1001 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 1002 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 1003 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 1004 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 1005 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 1006 1007 phy_write(phydev, 0x1f, 0x0b87); 1008 phy_write(phydev, 0x16, 0x80a2); 1009 phy_write(phydev, 0x17, 0x0153); 1010 phy_write(phydev, 0x16, 0x809c); 1011 phy_write(phydev, 0x17, 0x0153); 1012 phy_write(phydev, 0x1f, 0x0000); 1013 1014 phy_write(phydev, 0x1f, 0x0a43); 1015 phy_write(phydev, 0x13, 0x81B3); 1016 phy_write(phydev, 0x14, 0x0043); 1017 phy_write(phydev, 0x14, 0x00A7); 1018 phy_write(phydev, 0x14, 0x00D6); 1019 phy_write(phydev, 0x14, 0x00EC); 1020 phy_write(phydev, 0x14, 0x00F6); 1021 phy_write(phydev, 0x14, 0x00FB); 1022 phy_write(phydev, 0x14, 0x00FD); 1023 phy_write(phydev, 0x14, 0x00FF); 1024 phy_write(phydev, 0x14, 0x00BB); 1025 phy_write(phydev, 0x14, 0x0058); 1026 phy_write(phydev, 0x14, 0x0029); 1027 phy_write(phydev, 0x14, 0x0013); 1028 phy_write(phydev, 0x14, 0x0009); 1029 phy_write(phydev, 0x14, 0x0004); 1030 phy_write(phydev, 0x14, 0x0002); 1031 for (i = 0; i < 25; i++) 1032 phy_write(phydev, 0x14, 0x0000); 1033 phy_write(phydev, 0x1f, 0x0000); 1034 1035 r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F); 1036 r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843); 1037 1038 r8169_apply_firmware(tp); 1039 1040 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 1041 1042 r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100); 1043 1044 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 1045 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 1046 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 1047 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 1048 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 1049 rtl8168g_enable_gphy_10m(phydev); 1050 1051 rtl8168g_disable_aldps(phydev); 1052 rtl8125_config_eee_phy(phydev); 1053 } 1054 1055 static void rtl8125b_hw_phy_config(struct rtl8169_private *tp, 1056 struct phy_device *phydev) 1057 { 1058 r8169_apply_firmware(tp); 1059 rtl8168g_enable_gphy_10m(phydev); 1060 1061 phy_modify_paged(phydev, 0xac4, 0x13, 0x00f0, 0x0090); 1062 phy_modify_paged(phydev, 0xad3, 0x10, 0x0003, 0x0001); 1063 1064 phy_write(phydev, 0x1f, 0x0b87); 1065 phy_write(phydev, 0x16, 0x80f5); 1066 phy_write(phydev, 0x17, 0x760e); 1067 phy_write(phydev, 0x16, 0x8107); 1068 phy_write(phydev, 0x17, 0x360e); 1069 phy_write(phydev, 0x16, 0x8551); 1070 phy_modify(phydev, 0x17, 0xff00, 0x0800); 1071 phy_write(phydev, 0x1f, 0x0000); 1072 1073 phy_modify_paged(phydev, 0xbf0, 0x10, 0xe000, 0xa000); 1074 phy_modify_paged(phydev, 0xbf4, 0x13, 0x0f00, 0x0300); 1075 1076 r8168g_phy_param(phydev, 0x8044, 0xffff, 0x2417); 1077 r8168g_phy_param(phydev, 0x804a, 0xffff, 0x2417); 1078 r8168g_phy_param(phydev, 0x8050, 0xffff, 0x2417); 1079 r8168g_phy_param(phydev, 0x8056, 0xffff, 0x2417); 1080 r8168g_phy_param(phydev, 0x805c, 0xffff, 0x2417); 1081 r8168g_phy_param(phydev, 0x8062, 0xffff, 0x2417); 1082 r8168g_phy_param(phydev, 0x8068, 0xffff, 0x2417); 1083 r8168g_phy_param(phydev, 0x806e, 0xffff, 0x2417); 1084 r8168g_phy_param(phydev, 0x8074, 0xffff, 0x2417); 1085 r8168g_phy_param(phydev, 0x807a, 0xffff, 0x2417); 1086 1087 phy_modify_paged(phydev, 0xa4c, 0x15, 0x0000, 0x0040); 1088 phy_modify_paged(phydev, 0xbf8, 0x12, 0xe000, 0xa000); 1089 1090 rtl8125_legacy_force_mode(phydev); 1091 rtl8168g_disable_aldps(phydev); 1092 rtl8125_config_eee_phy(phydev); 1093 } 1094 1095 static void rtl8125d_hw_phy_config(struct rtl8169_private *tp, 1096 struct phy_device *phydev) 1097 { 1098 r8169_apply_firmware(tp); 1099 rtl8168g_enable_gphy_10m(phydev); 1100 rtl8125_legacy_force_mode(phydev); 1101 rtl8168g_disable_aldps(phydev); 1102 rtl8125_config_eee_phy(phydev); 1103 } 1104 1105 static void rtl8125bp_hw_phy_config(struct rtl8169_private *tp, 1106 struct phy_device *phydev) 1107 { 1108 r8169_apply_firmware(tp); 1109 rtl8168g_enable_gphy_10m(phydev); 1110 1111 r8168g_phy_param(phydev, 0x8010, 0x0800, 0x0000); 1112 1113 phy_write(phydev, 0x1f, 0x0b87); 1114 phy_write(phydev, 0x16, 0x8088); 1115 phy_modify(phydev, 0x17, 0xff00, 0x9000); 1116 phy_write(phydev, 0x16, 0x808f); 1117 phy_modify(phydev, 0x17, 0xff00, 0x9000); 1118 phy_write(phydev, 0x1f, 0x0000); 1119 1120 r8168g_phy_param(phydev, 0x8174, 0x2000, 0x1800); 1121 1122 rtl8125_legacy_force_mode(phydev); 1123 rtl8168g_disable_aldps(phydev); 1124 rtl8125_config_eee_phy(phydev); 1125 } 1126 1127 static void rtl8126a_hw_phy_config(struct rtl8169_private *tp, 1128 struct phy_device *phydev) 1129 { 1130 r8169_apply_firmware(tp); 1131 rtl8168g_enable_gphy_10m(phydev); 1132 rtl8125_legacy_force_mode(phydev); 1133 rtl8168g_disable_aldps(phydev); 1134 rtl8125_common_config_eee_phy(phydev); 1135 } 1136 1137 void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev, 1138 enum mac_version ver) 1139 { 1140 static const rtl_phy_cfg_fct phy_configs[] = { 1141 /* PCI devices. */ 1142 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 1143 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 1144 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 1145 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 1146 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 1147 /* PCI-E devices. */ 1148 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 1149 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 1150 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 1151 [RTL_GIGA_MAC_VER_10] = NULL, 1152 [RTL_GIGA_MAC_VER_14] = rtl8401_hw_phy_config, 1153 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 1154 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 1155 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 1156 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 1157 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 1158 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config, 1159 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 1160 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 1161 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 1162 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 1163 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 1164 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 1165 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 1166 [RTL_GIGA_MAC_VER_31] = NULL, 1167 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 1168 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 1169 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 1170 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 1171 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 1172 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 1173 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 1174 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 1175 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 1176 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 1177 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 1178 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 1179 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 1180 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 1181 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 1182 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config, 1183 [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config, 1184 [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config, 1185 [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config, 1186 [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config, 1187 [RTL_GIGA_MAC_VER_65] = rtl8125d_hw_phy_config, 1188 [RTL_GIGA_MAC_VER_66] = rtl8125bp_hw_phy_config, 1189 [RTL_GIGA_MAC_VER_70] = rtl8126a_hw_phy_config, 1190 [RTL_GIGA_MAC_VER_71] = rtl8126a_hw_phy_config, 1191 }; 1192 1193 if (phy_configs[ver]) 1194 phy_configs[ver](tp, phydev); 1195 } 1196