1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <linux/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" 59 #define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw" 60 #define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw" 61 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 62 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 63 64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 66 67 #define R8169_REGS_SIZE 256 68 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 69 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 70 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 73 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 74 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 75 76 #define OCP_STD_PHY_BASE 0xa400 77 78 #define RTL_CFG_NO_GBIT 1 79 80 /* write/read MMIO register */ 81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 87 88 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 92 #define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN) 93 94 static const struct rtl_chip_info { 95 u16 mask; 96 u16 val; 97 enum mac_version mac_version; 98 const char *name; 99 const char *fw_name; 100 } rtl_chip_infos[] = { 101 /* 8126A family. */ 102 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 }, 103 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 }, 104 105 /* 8125BP family. */ 106 { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 }, 107 108 /* 8125D family. */ 109 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 }, 110 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 }, 111 112 /* 8125B family. */ 113 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63, "RTL8125B", FIRMWARE_8125B_2 }, 114 115 /* 8125A family. */ 116 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 }, 117 118 /* RTL8117 */ 119 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117" }, 120 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117", 121 FIRMWARE_8168FP_3 }, 122 123 /* 8168EP family. */ 124 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51, "RTL8168ep/8111ep" }, 125 126 /* 8168H family. */ 127 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46, "RTL8168h/8111h", 128 FIRMWARE_8168H_2 }, 129 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 130 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46, "RTL8168M", FIRMWARE_8168H_2 }, 131 132 /* 8168G family. */ 133 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44, "RTL8411b", FIRMWARE_8411_2 }, 134 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42, "RTL8168gu/8111gu", 135 FIRMWARE_8168G_3 }, 136 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40, "RTL8168g/8111g", 137 FIRMWARE_8168G_2 }, 138 139 /* 8168F family. */ 140 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38, "RTL8411", FIRMWARE_8411_1 }, 141 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36, "RTL8168f/8111f", 142 FIRMWARE_8168F_2 }, 143 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35, "RTL8168f/8111f", 144 FIRMWARE_8168F_1 }, 145 146 /* 8168E family. */ 147 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34, "RTL8168evl/8111evl", 148 FIRMWARE_8168E_3 }, 149 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32, "RTL8168e/8111e", 150 FIRMWARE_8168E_1 }, 151 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33, "RTL8168e/8111e", 152 FIRMWARE_8168E_2 }, 153 154 /* 8168D family. */ 155 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25, "RTL8168d/8111d", 156 FIRMWARE_8168D_1 }, 157 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26, "RTL8168d/8111d", 158 FIRMWARE_8168D_2 }, 159 160 /* 8168DP family. */ 161 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28, "RTL8168dp/8111dp" }, 162 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31, "RTL8168dp/8111dp" }, 163 164 /* 8168C family. */ 165 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23, "RTL8168cp/8111cp" }, 166 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18, "RTL8168cp/8111cp" }, 167 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24, "RTL8168cp/8111cp" }, 168 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19, "RTL8168c/8111c" }, 169 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20, "RTL8168c/8111c" }, 170 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21, "RTL8168c/8111c" }, 171 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22, "RTL8168c/8111c" }, 172 173 /* 8168B family. */ 174 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17, "RTL8168b/8111b" }, 175 /* This one is very old and rare, support has been removed. 176 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" }, 177 */ 178 179 /* 8101 family. */ 180 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39, "RTL8106e", FIRMWARE_8106E_1 }, 181 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37, "RTL8402", FIRMWARE_8402_1 }, 182 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29, "RTL8105e", FIRMWARE_8105E_1 }, 183 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30, "RTL8105e", FIRMWARE_8105E_1 }, 184 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08, "RTL8102e" }, 185 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08, "RTL8102e" }, 186 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07, "RTL8102e" }, 187 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07, "RTL8102e" }, 188 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14, "RTL8401" }, 189 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, 190 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, 191 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10, "RTL8101e/RTL8100e" }, 192 193 /* 8110 family. */ 194 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06, "RTL8169sc/8110sc" }, 195 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05, "RTL8169sc/8110sc" }, 196 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04, "RTL8169sb/8110sb" }, 197 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" }, 198 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" }, 199 200 /* Catch-all */ 201 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 202 }; 203 204 static const struct pci_device_id rtl8169_pci_tbl[] = { 205 { PCI_VDEVICE(REALTEK, 0x2502) }, 206 { PCI_VDEVICE(REALTEK, 0x2600) }, 207 { PCI_VDEVICE(REALTEK, 0x8129) }, 208 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 209 { PCI_VDEVICE(REALTEK, 0x8161) }, 210 { PCI_VDEVICE(REALTEK, 0x8162) }, 211 { PCI_VDEVICE(REALTEK, 0x8167) }, 212 { PCI_VDEVICE(REALTEK, 0x8168) }, 213 { PCI_VDEVICE(NCUBE, 0x8168) }, 214 { PCI_VDEVICE(REALTEK, 0x8169) }, 215 { PCI_VENDOR_ID_DLINK, 0x4300, 216 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 217 { PCI_VDEVICE(DLINK, 0x4300) }, 218 { PCI_VDEVICE(DLINK, 0x4302) }, 219 { PCI_VDEVICE(AT, 0xc107) }, 220 { PCI_VDEVICE(USR, 0x0116) }, 221 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 222 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 223 { PCI_VDEVICE(REALTEK, 0x8125) }, 224 { PCI_VDEVICE(REALTEK, 0x8126) }, 225 { PCI_VDEVICE(REALTEK, 0x3000) }, 226 { PCI_VDEVICE(REALTEK, 0x5000) }, 227 {} 228 }; 229 230 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 231 232 enum rtl_registers { 233 MAC0 = 0, /* Ethernet hardware address. */ 234 MAC4 = 4, 235 MAR0 = 8, /* Multicast filter. */ 236 CounterAddrLow = 0x10, 237 CounterAddrHigh = 0x14, 238 TxDescStartAddrLow = 0x20, 239 TxDescStartAddrHigh = 0x24, 240 TxHDescStartAddrLow = 0x28, 241 TxHDescStartAddrHigh = 0x2c, 242 FLASH = 0x30, 243 ERSR = 0x36, 244 ChipCmd = 0x37, 245 TxPoll = 0x38, 246 IntrMask = 0x3c, 247 IntrStatus = 0x3e, 248 249 TxConfig = 0x40, 250 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 251 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 252 253 RxConfig = 0x44, 254 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 255 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 256 #define RXCFG_FIFO_SHIFT 13 257 /* No threshold before first PCI xfer */ 258 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 259 #define RX_EARLY_OFF (1 << 11) 260 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 261 #define RXCFG_DMA_SHIFT 8 262 /* Unlimited maximum PCI burst. */ 263 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 264 265 Cfg9346 = 0x50, 266 Config0 = 0x51, 267 Config1 = 0x52, 268 Config2 = 0x53, 269 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 270 271 Config3 = 0x54, 272 Config4 = 0x55, 273 Config5 = 0x56, 274 PHYAR = 0x60, 275 PHYstatus = 0x6c, 276 RxMaxSize = 0xda, 277 CPlusCmd = 0xe0, 278 IntrMitigate = 0xe2, 279 280 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 281 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 282 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 283 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 284 285 #define RTL_COALESCE_T_MAX 0x0fU 286 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 287 288 RxDescAddrLow = 0xe4, 289 RxDescAddrHigh = 0xe8, 290 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 291 292 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 293 294 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 295 296 #define TxPacketMax (8064 >> 7) 297 #define EarlySize 0x27 298 299 FuncEvent = 0xf0, 300 FuncEventMask = 0xf4, 301 FuncPresetState = 0xf8, 302 IBCR0 = 0xf8, 303 IBCR2 = 0xf9, 304 IBIMR0 = 0xfa, 305 IBISR0 = 0xfb, 306 FuncForceEvent = 0xfc, 307 }; 308 309 enum rtl8168_8101_registers { 310 CSIDR = 0x64, 311 CSIAR = 0x68, 312 #define CSIAR_FLAG 0x80000000 313 #define CSIAR_WRITE_CMD 0x80000000 314 #define CSIAR_BYTE_ENABLE 0x0000f000 315 #define CSIAR_ADDR_MASK 0x00000fff 316 PMCH = 0x6f, 317 #define D3COLD_NO_PLL_DOWN BIT(7) 318 #define D3HOT_NO_PLL_DOWN BIT(6) 319 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 320 EPHYAR = 0x80, 321 #define EPHYAR_FLAG 0x80000000 322 #define EPHYAR_WRITE_CMD 0x80000000 323 #define EPHYAR_REG_MASK 0x1f 324 #define EPHYAR_REG_SHIFT 16 325 #define EPHYAR_DATA_MASK 0xffff 326 DLLPR = 0xd0, 327 #define PFM_EN (1 << 6) 328 #define TX_10M_PS_EN (1 << 7) 329 DBG_REG = 0xd1, 330 #define FIX_NAK_1 (1 << 4) 331 #define FIX_NAK_2 (1 << 3) 332 TWSI = 0xd2, 333 MCU = 0xd3, 334 #define NOW_IS_OOB (1 << 7) 335 #define TX_EMPTY (1 << 5) 336 #define RX_EMPTY (1 << 4) 337 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 338 #define EN_NDP (1 << 3) 339 #define EN_OOB_RESET (1 << 2) 340 #define LINK_LIST_RDY (1 << 1) 341 EFUSEAR = 0xdc, 342 #define EFUSEAR_FLAG 0x80000000 343 #define EFUSEAR_WRITE_CMD 0x80000000 344 #define EFUSEAR_READ_CMD 0x00000000 345 #define EFUSEAR_REG_MASK 0x03ff 346 #define EFUSEAR_REG_SHIFT 8 347 #define EFUSEAR_DATA_MASK 0xff 348 MISC_1 = 0xf2, 349 #define PFM_D3COLD_EN (1 << 6) 350 }; 351 352 enum rtl8168_registers { 353 LED_CTRL = 0x18, 354 LED_FREQ = 0x1a, 355 EEE_LED = 0x1b, 356 ERIDR = 0x70, 357 ERIAR = 0x74, 358 #define ERIAR_FLAG 0x80000000 359 #define ERIAR_WRITE_CMD 0x80000000 360 #define ERIAR_READ_CMD 0x00000000 361 #define ERIAR_ADDR_BYTE_ALIGN 4 362 #define ERIAR_TYPE_SHIFT 16 363 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 364 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 365 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 366 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 367 #define ERIAR_MASK_SHIFT 12 368 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 369 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 370 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 371 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 372 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 373 EPHY_RXER_NUM = 0x7c, 374 OCPDR = 0xb0, /* OCP GPHY access */ 375 #define OCPDR_WRITE_CMD 0x80000000 376 #define OCPDR_READ_CMD 0x00000000 377 #define OCPDR_REG_MASK 0x7f 378 #define OCPDR_GPHY_REG_SHIFT 16 379 #define OCPDR_DATA_MASK 0xffff 380 OCPAR = 0xb4, 381 #define OCPAR_FLAG 0x80000000 382 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 383 #define OCPAR_GPHY_READ_CMD 0x0000f060 384 GPHY_OCP = 0xb8, 385 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 386 MISC = 0xf0, /* 8168e only. */ 387 #define TXPLA_RST (1 << 29) 388 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 389 #define PWM_EN (1 << 22) 390 #define RXDV_GATED_EN (1 << 19) 391 #define EARLY_TALLY_EN (1 << 16) 392 }; 393 394 enum rtl8125_registers { 395 LEDSEL0 = 0x18, 396 INT_CFG0_8125 = 0x34, 397 #define INT_CFG0_ENABLE_8125 BIT(0) 398 #define INT_CFG0_CLKREQEN BIT(3) 399 IntrMask_8125 = 0x38, 400 IntrStatus_8125 = 0x3c, 401 INT_CFG1_8125 = 0x7a, 402 LEDSEL2 = 0x84, 403 LEDSEL1 = 0x86, 404 TxPoll_8125 = 0x90, 405 LEDSEL3 = 0x96, 406 MAC0_BKP = 0x19e0, 407 RSS_CTRL_8125 = 0x4500, 408 Q_NUM_CTRL_8125 = 0x4800, 409 EEE_TXIDLE_TIMER_8125 = 0x6048, 410 }; 411 412 #define LEDSEL_MASK_8125 0x23f 413 414 #define RX_VLAN_INNER_8125 BIT(22) 415 #define RX_VLAN_OUTER_8125 BIT(23) 416 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 417 418 #define RX_FETCH_DFLT_8125 (8 << 27) 419 420 enum rtl_register_content { 421 /* InterruptStatusBits */ 422 SYSErr = 0x8000, 423 PCSTimeout = 0x4000, 424 SWInt = 0x0100, 425 TxDescUnavail = 0x0080, 426 RxFIFOOver = 0x0040, 427 LinkChg = 0x0020, 428 RxOverflow = 0x0010, 429 TxErr = 0x0008, 430 TxOK = 0x0004, 431 RxErr = 0x0002, 432 RxOK = 0x0001, 433 434 /* RxStatusDesc */ 435 RxRWT = (1 << 22), 436 RxRES = (1 << 21), 437 RxRUNT = (1 << 20), 438 RxCRC = (1 << 19), 439 440 /* ChipCmdBits */ 441 StopReq = 0x80, 442 CmdReset = 0x10, 443 CmdRxEnb = 0x08, 444 CmdTxEnb = 0x04, 445 RxBufEmpty = 0x01, 446 447 /* TXPoll register p.5 */ 448 HPQ = 0x80, /* Poll cmd on the high prio queue */ 449 NPQ = 0x40, /* Poll cmd on the low prio queue */ 450 FSWInt = 0x01, /* Forced software interrupt */ 451 452 /* Cfg9346Bits */ 453 Cfg9346_Lock = 0x00, 454 Cfg9346_Unlock = 0xc0, 455 456 /* rx_mode_bits */ 457 AcceptErr = 0x20, 458 AcceptRunt = 0x10, 459 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 460 AcceptBroadcast = 0x08, 461 AcceptMulticast = 0x04, 462 AcceptMyPhys = 0x02, 463 AcceptAllPhys = 0x01, 464 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 465 #define RX_CONFIG_ACCEPT_MASK 0x3f 466 467 /* TxConfigBits */ 468 TxInterFrameGapShift = 24, 469 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 470 471 /* Config1 register p.24 */ 472 LEDS1 = (1 << 7), 473 LEDS0 = (1 << 6), 474 Speed_down = (1 << 4), 475 MEMMAP = (1 << 3), 476 IOMAP = (1 << 2), 477 VPD = (1 << 1), 478 PMEnable = (1 << 0), /* Power Management Enable */ 479 480 /* Config2 register p. 25 */ 481 ClkReqEn = (1 << 7), /* Clock Request Enable */ 482 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 483 PCI_Clock_66MHz = 0x01, 484 PCI_Clock_33MHz = 0x00, 485 486 /* Config3 register p.25 */ 487 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 488 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 489 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 490 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 491 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 492 493 /* Config4 register */ 494 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 495 496 /* Config5 register p.27 */ 497 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 498 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 499 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 500 Spi_en = (1 << 3), 501 LanWake = (1 << 1), /* LanWake enable/disable */ 502 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 503 ASPM_en = (1 << 0), /* ASPM enable */ 504 505 /* CPlusCmd p.31 */ 506 EnableBist = (1 << 15), // 8168 8101 507 Mac_dbgo_oe = (1 << 14), // 8168 8101 508 EnAnaPLL = (1 << 14), // 8169 509 Normal_mode = (1 << 13), // unused 510 Force_half_dup = (1 << 12), // 8168 8101 511 Force_rxflow_en = (1 << 11), // 8168 8101 512 Force_txflow_en = (1 << 10), // 8168 8101 513 Cxpl_dbg_sel = (1 << 9), // 8168 8101 514 ASF = (1 << 8), // 8168 8101 515 PktCntrDisable = (1 << 7), // 8168 8101 516 Mac_dbgo_sel = 0x001c, // 8168 517 RxVlan = (1 << 6), 518 RxChkSum = (1 << 5), 519 PCIDAC = (1 << 4), 520 PCIMulRW = (1 << 3), 521 #define INTT_MASK GENMASK(1, 0) 522 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 523 524 /* rtl8169_PHYstatus */ 525 TBI_Enable = 0x80, 526 TxFlowCtrl = 0x40, 527 RxFlowCtrl = 0x20, 528 _1000bpsF = 0x10, 529 _100bps = 0x08, 530 _10bps = 0x04, 531 LinkStatus = 0x02, 532 FullDup = 0x01, 533 534 /* ResetCounterCommand */ 535 CounterReset = 0x1, 536 537 /* DumpCounterCommand */ 538 CounterDump = 0x8, 539 540 /* magic enable v2 */ 541 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 542 }; 543 544 enum rtl_desc_bit { 545 /* First doubleword. */ 546 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 547 RingEnd = (1 << 30), /* End of descriptor ring */ 548 FirstFrag = (1 << 29), /* First segment of a packet */ 549 LastFrag = (1 << 28), /* Final segment of a packet */ 550 }; 551 552 /* Generic case. */ 553 enum rtl_tx_desc_bit { 554 /* First doubleword. */ 555 TD_LSO = (1 << 27), /* Large Send Offload */ 556 #define TD_MSS_MAX 0x07ffu /* MSS value */ 557 558 /* Second doubleword. */ 559 TxVlanTag = (1 << 17), /* Add VLAN tag */ 560 }; 561 562 /* 8169, 8168b and 810x except 8102e. */ 563 enum rtl_tx_desc_bit_0 { 564 /* First doubleword. */ 565 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 566 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 567 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 568 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 569 }; 570 571 /* 8102e, 8168c and beyond. */ 572 enum rtl_tx_desc_bit_1 { 573 /* First doubleword. */ 574 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 575 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 576 #define GTTCPHO_SHIFT 18 577 #define GTTCPHO_MAX 0x7f 578 579 /* Second doubleword. */ 580 #define TCPHO_SHIFT 18 581 #define TCPHO_MAX 0x3ff 582 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 583 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 584 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 585 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 586 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 587 }; 588 589 enum rtl_rx_desc_bit { 590 /* Rx private */ 591 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 592 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 593 594 #define RxProtoUDP (PID1) 595 #define RxProtoTCP (PID0) 596 #define RxProtoIP (PID1 | PID0) 597 #define RxProtoMask RxProtoIP 598 599 IPFail = (1 << 16), /* IP checksum failed */ 600 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 601 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 602 603 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 604 605 RxVlanTag = (1 << 16), /* VLAN tag available */ 606 }; 607 608 #define RTL_GSO_MAX_SIZE_V1 32000 609 #define RTL_GSO_MAX_SEGS_V1 24 610 #define RTL_GSO_MAX_SIZE_V2 64000 611 #define RTL_GSO_MAX_SEGS_V2 64 612 613 struct TxDesc { 614 __le32 opts1; 615 __le32 opts2; 616 __le64 addr; 617 }; 618 619 struct RxDesc { 620 __le32 opts1; 621 __le32 opts2; 622 __le64 addr; 623 }; 624 625 struct ring_info { 626 struct sk_buff *skb; 627 u32 len; 628 }; 629 630 struct rtl8169_counters { 631 __le64 tx_packets; 632 __le64 rx_packets; 633 __le64 tx_errors; 634 __le32 rx_errors; 635 __le16 rx_missed; 636 __le16 align_errors; 637 __le32 tx_one_collision; 638 __le32 tx_multi_collision; 639 __le64 rx_unicast; 640 __le64 rx_broadcast; 641 __le32 rx_multicast; 642 __le16 tx_aborted; 643 __le16 tx_underrun; 644 /* new since RTL8125 */ 645 __le64 tx_octets; 646 __le64 rx_octets; 647 __le64 rx_multicast64; 648 __le64 tx_unicast64; 649 __le64 tx_broadcast64; 650 __le64 tx_multicast64; 651 __le32 tx_pause_on; 652 __le32 tx_pause_off; 653 __le32 tx_pause_all; 654 __le32 tx_deferred; 655 __le32 tx_late_collision; 656 __le32 tx_all_collision; 657 __le32 tx_aborted32; 658 __le32 align_errors32; 659 __le32 rx_frame_too_long; 660 __le32 rx_runt; 661 __le32 rx_pause_on; 662 __le32 rx_pause_off; 663 __le32 rx_pause_all; 664 __le32 rx_unknown_opcode; 665 __le32 rx_mac_error; 666 __le32 tx_underrun32; 667 __le32 rx_mac_missed; 668 __le32 rx_tcam_dropped; 669 __le32 tdu; 670 __le32 rdu; 671 }; 672 673 struct rtl8169_tc_offsets { 674 bool inited; 675 __le64 tx_errors; 676 __le32 tx_multi_collision; 677 __le16 tx_aborted; 678 __le16 rx_missed; 679 }; 680 681 enum rtl_flag { 682 RTL_FLAG_TASK_RESET_PENDING, 683 RTL_FLAG_TASK_TX_TIMEOUT, 684 RTL_FLAG_MAX 685 }; 686 687 enum rtl_dash_type { 688 RTL_DASH_NONE, 689 RTL_DASH_DP, 690 RTL_DASH_EP, 691 RTL_DASH_25_BP, 692 }; 693 694 struct rtl8169_private { 695 void __iomem *mmio_addr; /* memory map physical address */ 696 struct pci_dev *pci_dev; 697 struct net_device *dev; 698 struct phy_device *phydev; 699 struct napi_struct napi; 700 enum mac_version mac_version; 701 enum rtl_dash_type dash_type; 702 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 703 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 704 u32 dirty_tx; 705 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 706 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 707 dma_addr_t TxPhyAddr; 708 dma_addr_t RxPhyAddr; 709 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 710 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 711 u16 cp_cmd; 712 u16 tx_lpi_timer; 713 u32 irq_mask; 714 int irq; 715 struct clk *clk; 716 717 struct { 718 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 719 struct work_struct work; 720 } wk; 721 722 raw_spinlock_t mac_ocp_lock; 723 struct mutex led_lock; /* serialize LED ctrl RMW access */ 724 725 unsigned supports_gmii:1; 726 unsigned aspm_manageable:1; 727 unsigned dash_enabled:1; 728 dma_addr_t counters_phys_addr; 729 struct rtl8169_counters *counters; 730 struct rtl8169_tc_offsets tc_offset; 731 u32 saved_wolopts; 732 733 const char *fw_name; 734 struct rtl_fw *rtl_fw; 735 736 struct r8169_led_classdev *leds; 737 738 u32 ocp_base; 739 }; 740 741 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 742 743 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 744 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 745 MODULE_SOFTDEP("pre: realtek"); 746 MODULE_LICENSE("GPL"); 747 MODULE_FIRMWARE(FIRMWARE_8168D_1); 748 MODULE_FIRMWARE(FIRMWARE_8168D_2); 749 MODULE_FIRMWARE(FIRMWARE_8168E_1); 750 MODULE_FIRMWARE(FIRMWARE_8168E_2); 751 MODULE_FIRMWARE(FIRMWARE_8168E_3); 752 MODULE_FIRMWARE(FIRMWARE_8105E_1); 753 MODULE_FIRMWARE(FIRMWARE_8168F_1); 754 MODULE_FIRMWARE(FIRMWARE_8168F_2); 755 MODULE_FIRMWARE(FIRMWARE_8402_1); 756 MODULE_FIRMWARE(FIRMWARE_8411_1); 757 MODULE_FIRMWARE(FIRMWARE_8411_2); 758 MODULE_FIRMWARE(FIRMWARE_8106E_1); 759 MODULE_FIRMWARE(FIRMWARE_8106E_2); 760 MODULE_FIRMWARE(FIRMWARE_8168G_2); 761 MODULE_FIRMWARE(FIRMWARE_8168G_3); 762 MODULE_FIRMWARE(FIRMWARE_8168H_2); 763 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 764 MODULE_FIRMWARE(FIRMWARE_8107E_2); 765 MODULE_FIRMWARE(FIRMWARE_8125A_3); 766 MODULE_FIRMWARE(FIRMWARE_8125B_2); 767 MODULE_FIRMWARE(FIRMWARE_8125D_1); 768 MODULE_FIRMWARE(FIRMWARE_8125D_2); 769 MODULE_FIRMWARE(FIRMWARE_8125BP_2); 770 MODULE_FIRMWARE(FIRMWARE_8126A_2); 771 MODULE_FIRMWARE(FIRMWARE_8126A_3); 772 773 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 774 { 775 return &tp->pci_dev->dev; 776 } 777 778 static void rtl_lock_config_regs(struct rtl8169_private *tp) 779 { 780 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 781 } 782 783 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 784 { 785 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 786 } 787 788 static void rtl_pci_commit(struct rtl8169_private *tp) 789 { 790 /* Read an arbitrary register to commit a preceding PCI write */ 791 RTL_R8(tp, ChipCmd); 792 } 793 794 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 795 { 796 u8 val; 797 798 val = RTL_R8(tp, Config2); 799 RTL_W8(tp, Config2, (val & ~clear) | set); 800 } 801 802 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 803 { 804 u8 val; 805 806 val = RTL_R8(tp, Config5); 807 RTL_W8(tp, Config5, (val & ~clear) | set); 808 } 809 810 static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg, 811 u8 bits, bool cond) 812 { 813 u8 val, old_val; 814 815 old_val = RTL_R8(tp, reg); 816 if (cond) 817 val = old_val | bits; 818 else 819 val = old_val & ~bits; 820 if (val != old_val) 821 RTL_W8(tp, reg, val); 822 } 823 824 static bool rtl_is_8125(struct rtl8169_private *tp) 825 { 826 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 827 } 828 829 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 830 { 831 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 832 tp->mac_version != RTL_GIGA_MAC_VER_39 && 833 tp->mac_version <= RTL_GIGA_MAC_VER_52; 834 } 835 836 static bool rtl_supports_eee(struct rtl8169_private *tp) 837 { 838 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 839 tp->mac_version != RTL_GIGA_MAC_VER_37 && 840 tp->mac_version != RTL_GIGA_MAC_VER_39; 841 } 842 843 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 844 { 845 int i; 846 847 for (i = 0; i < ETH_ALEN; i++) 848 mac[i] = RTL_R8(tp, reg + i); 849 } 850 851 struct rtl_cond { 852 bool (*check)(struct rtl8169_private *); 853 const char *msg; 854 }; 855 856 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 857 unsigned long usecs, int n, bool high) 858 { 859 int i; 860 861 for (i = 0; i < n; i++) { 862 if (c->check(tp) == high) 863 return true; 864 fsleep(usecs); 865 } 866 867 if (net_ratelimit()) 868 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 869 c->msg, !high, n, usecs); 870 return false; 871 } 872 873 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 874 const struct rtl_cond *c, 875 unsigned long d, int n) 876 { 877 return rtl_loop_wait(tp, c, d, n, true); 878 } 879 880 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 881 const struct rtl_cond *c, 882 unsigned long d, int n) 883 { 884 return rtl_loop_wait(tp, c, d, n, false); 885 } 886 887 #define DECLARE_RTL_COND(name) \ 888 static bool name ## _check(struct rtl8169_private *); \ 889 \ 890 static const struct rtl_cond name = { \ 891 .check = name ## _check, \ 892 .msg = #name \ 893 }; \ 894 \ 895 static bool name ## _check(struct rtl8169_private *tp) 896 897 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 898 { 899 struct device *dev = tp_to_dev(tp); 900 int ret; 901 902 ret = pm_runtime_resume_and_get(dev); 903 if (ret < 0) 904 return ret; 905 906 mutex_lock(&tp->led_lock); 907 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 908 mutex_unlock(&tp->led_lock); 909 910 pm_runtime_put_sync(dev); 911 912 return 0; 913 } 914 915 int rtl8168_get_led_mode(struct rtl8169_private *tp) 916 { 917 struct device *dev = tp_to_dev(tp); 918 int ret; 919 920 ret = pm_runtime_resume_and_get(dev); 921 if (ret < 0) 922 return ret; 923 924 ret = RTL_R16(tp, LED_CTRL); 925 926 pm_runtime_put_sync(dev); 927 928 return ret; 929 } 930 931 static int rtl8125_get_led_reg(int index) 932 { 933 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 934 935 return led_regs[index]; 936 } 937 938 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 939 { 940 int reg = rtl8125_get_led_reg(index); 941 struct device *dev = tp_to_dev(tp); 942 int ret; 943 u16 val; 944 945 ret = pm_runtime_resume_and_get(dev); 946 if (ret < 0) 947 return ret; 948 949 mutex_lock(&tp->led_lock); 950 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 951 RTL_W16(tp, reg, val | mode); 952 mutex_unlock(&tp->led_lock); 953 954 pm_runtime_put_sync(dev); 955 956 return 0; 957 } 958 959 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 960 { 961 int reg = rtl8125_get_led_reg(index); 962 struct device *dev = tp_to_dev(tp); 963 int ret; 964 965 ret = pm_runtime_resume_and_get(dev); 966 if (ret < 0) 967 return ret; 968 969 ret = RTL_R16(tp, reg); 970 971 pm_runtime_put_sync(dev); 972 973 return ret; 974 } 975 976 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 977 char *buf, int buf_len) 978 { 979 struct pci_dev *pdev = tp->pci_dev; 980 char pdom[8], pfun[8]; 981 int domain; 982 983 domain = pci_domain_nr(pdev->bus); 984 if (domain) 985 snprintf(pdom, sizeof(pdom), "P%d", domain); 986 else 987 pdom[0] = '\0'; 988 989 if (pdev->multifunction) 990 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 991 else 992 pfun[0] = '\0'; 993 994 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 995 PCI_SLOT(pdev->devfn), pfun, idx); 996 } 997 998 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 999 { 1000 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 1001 if (type == ERIAR_OOB && tp->mac_version == RTL_GIGA_MAC_VER_52) 1002 *cmd |= 0xf70 << 18; 1003 } 1004 1005 DECLARE_RTL_COND(rtl_eriar_cond) 1006 { 1007 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1008 } 1009 1010 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1011 u32 val, int type) 1012 { 1013 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 1014 1015 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 1016 return; 1017 1018 RTL_W32(tp, ERIDR, val); 1019 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1020 RTL_W32(tp, ERIAR, cmd); 1021 1022 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1023 } 1024 1025 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1026 u32 val) 1027 { 1028 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1029 } 1030 1031 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1032 { 1033 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 1034 1035 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1036 RTL_W32(tp, ERIAR, cmd); 1037 1038 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1039 RTL_R32(tp, ERIDR) : ~0; 1040 } 1041 1042 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1043 { 1044 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1045 } 1046 1047 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 1048 { 1049 u32 val = rtl_eri_read(tp, addr); 1050 1051 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 1052 } 1053 1054 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1055 { 1056 rtl_w0w1_eri(tp, addr, p, 0); 1057 } 1058 1059 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1060 { 1061 rtl_w0w1_eri(tp, addr, 0, m); 1062 } 1063 1064 static bool rtl_ocp_reg_failure(u32 reg) 1065 { 1066 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1067 } 1068 1069 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1070 { 1071 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1072 } 1073 1074 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1075 { 1076 if (rtl_ocp_reg_failure(reg)) 1077 return; 1078 1079 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1080 1081 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1082 } 1083 1084 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1085 { 1086 if (rtl_ocp_reg_failure(reg)) 1087 return 0; 1088 1089 RTL_W32(tp, GPHY_OCP, reg << 15); 1090 1091 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1092 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1093 } 1094 1095 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1096 { 1097 if (rtl_ocp_reg_failure(reg)) 1098 return; 1099 1100 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1101 } 1102 1103 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1104 { 1105 unsigned long flags; 1106 1107 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1108 __r8168_mac_ocp_write(tp, reg, data); 1109 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1110 } 1111 1112 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1113 { 1114 if (rtl_ocp_reg_failure(reg)) 1115 return 0; 1116 1117 RTL_W32(tp, OCPDR, reg << 15); 1118 1119 return RTL_R32(tp, OCPDR); 1120 } 1121 1122 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1123 { 1124 unsigned long flags; 1125 u16 val; 1126 1127 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1128 val = __r8168_mac_ocp_read(tp, reg); 1129 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1130 1131 return val; 1132 } 1133 1134 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1135 u16 set) 1136 { 1137 unsigned long flags; 1138 u16 data; 1139 1140 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1141 data = __r8168_mac_ocp_read(tp, reg); 1142 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1143 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1144 } 1145 1146 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1147 * PHY MCU interrupts before PHY power-down. 1148 */ 1149 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1150 { 1151 switch (tp->mac_version) { 1152 case RTL_GIGA_MAC_VER_40: 1153 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1154 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1155 else 1156 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1157 break; 1158 default: 1159 break; 1160 } 1161 }; 1162 1163 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1164 { 1165 if (reg == 0x1f) { 1166 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1167 return; 1168 } 1169 1170 if (tp->ocp_base != OCP_STD_PHY_BASE) 1171 reg -= 0x10; 1172 1173 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1174 rtl8168g_phy_suspend_quirk(tp, value); 1175 1176 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1177 } 1178 1179 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1180 { 1181 if (reg == 0x1f) 1182 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1183 1184 if (tp->ocp_base != OCP_STD_PHY_BASE) 1185 reg -= 0x10; 1186 1187 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1188 } 1189 1190 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1191 { 1192 if (reg == 0x1f) { 1193 tp->ocp_base = value << 4; 1194 return; 1195 } 1196 1197 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1198 } 1199 1200 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1201 { 1202 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1203 } 1204 1205 DECLARE_RTL_COND(rtl_phyar_cond) 1206 { 1207 return RTL_R32(tp, PHYAR) & 0x80000000; 1208 } 1209 1210 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1211 { 1212 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1213 1214 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1215 /* 1216 * According to hardware specs a 20us delay is required after write 1217 * complete indication, but before sending next command. 1218 */ 1219 udelay(20); 1220 } 1221 1222 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1223 { 1224 int value; 1225 1226 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1227 1228 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1229 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1230 1231 /* 1232 * According to hardware specs a 20us delay is required after read 1233 * complete indication, but before sending next command. 1234 */ 1235 udelay(20); 1236 1237 return value; 1238 } 1239 1240 DECLARE_RTL_COND(rtl_ocpar_cond) 1241 { 1242 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1243 } 1244 1245 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1246 1247 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1248 { 1249 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1250 } 1251 1252 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1253 { 1254 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1255 } 1256 1257 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1258 { 1259 r8168dp_2_mdio_start(tp); 1260 1261 r8169_mdio_write(tp, reg, value); 1262 1263 r8168dp_2_mdio_stop(tp); 1264 } 1265 1266 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1267 { 1268 int value; 1269 1270 /* Work around issue with chip reporting wrong PHY ID */ 1271 if (reg == MII_PHYSID2) 1272 return 0xc912; 1273 1274 r8168dp_2_mdio_start(tp); 1275 1276 value = r8169_mdio_read(tp, reg); 1277 1278 r8168dp_2_mdio_stop(tp); 1279 1280 return value; 1281 } 1282 1283 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1284 { 1285 switch (tp->mac_version) { 1286 case RTL_GIGA_MAC_VER_28: 1287 case RTL_GIGA_MAC_VER_31: 1288 r8168dp_2_mdio_write(tp, location, val); 1289 break; 1290 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 1291 r8168g_mdio_write(tp, location, val); 1292 break; 1293 default: 1294 r8169_mdio_write(tp, location, val); 1295 break; 1296 } 1297 } 1298 1299 static int rtl_readphy(struct rtl8169_private *tp, int location) 1300 { 1301 switch (tp->mac_version) { 1302 case RTL_GIGA_MAC_VER_28: 1303 case RTL_GIGA_MAC_VER_31: 1304 return r8168dp_2_mdio_read(tp, location); 1305 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 1306 return r8168g_mdio_read(tp, location); 1307 default: 1308 return r8169_mdio_read(tp, location); 1309 } 1310 } 1311 1312 DECLARE_RTL_COND(rtl_ephyar_cond) 1313 { 1314 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1315 } 1316 1317 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1318 { 1319 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1320 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1321 1322 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1323 1324 udelay(10); 1325 } 1326 1327 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1328 { 1329 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1330 1331 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1332 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1333 } 1334 1335 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1336 { 1337 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1338 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1339 RTL_R32(tp, OCPDR) : ~0; 1340 } 1341 1342 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1343 { 1344 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1345 } 1346 1347 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1348 u32 data) 1349 { 1350 RTL_W32(tp, OCPDR, data); 1351 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1352 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1353 } 1354 1355 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1356 u32 data) 1357 { 1358 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1359 data, ERIAR_OOB); 1360 } 1361 1362 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1363 { 1364 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1365 1366 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1367 } 1368 1369 #define OOB_CMD_RESET 0x00 1370 #define OOB_CMD_DRIVER_START 0x05 1371 #define OOB_CMD_DRIVER_STOP 0x06 1372 1373 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1374 { 1375 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1376 } 1377 1378 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1379 { 1380 u16 reg; 1381 1382 reg = rtl8168_get_ocp_reg(tp); 1383 1384 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1385 } 1386 1387 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1388 { 1389 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1390 } 1391 1392 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1393 { 1394 return RTL_R8(tp, IBISR0) & 0x20; 1395 } 1396 1397 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1398 { 1399 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1400 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1401 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1402 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1403 } 1404 1405 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1406 { 1407 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1408 if (tp->dash_enabled) 1409 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1410 } 1411 1412 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1413 { 1414 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1415 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1416 if (tp->dash_enabled) 1417 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1418 } 1419 1420 static void rtl8125bp_driver_start(struct rtl8169_private *tp) 1421 { 1422 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_START); 1423 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); 1424 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); 1425 } 1426 1427 static void rtl8168_driver_start(struct rtl8169_private *tp) 1428 { 1429 if (tp->dash_type == RTL_DASH_DP) 1430 rtl8168dp_driver_start(tp); 1431 else if (tp->dash_type == RTL_DASH_25_BP) 1432 rtl8125bp_driver_start(tp); 1433 else 1434 rtl8168ep_driver_start(tp); 1435 } 1436 1437 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1438 { 1439 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1440 if (tp->dash_enabled) 1441 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1442 } 1443 1444 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1445 { 1446 rtl8168ep_stop_cmac(tp); 1447 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1448 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1449 if (tp->dash_enabled) 1450 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1451 } 1452 1453 static void rtl8125bp_driver_stop(struct rtl8169_private *tp) 1454 { 1455 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_STOP); 1456 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); 1457 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); 1458 } 1459 1460 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1461 { 1462 if (tp->dash_type == RTL_DASH_DP) 1463 rtl8168dp_driver_stop(tp); 1464 else if (tp->dash_type == RTL_DASH_25_BP) 1465 rtl8125bp_driver_stop(tp); 1466 else 1467 rtl8168ep_driver_stop(tp); 1468 } 1469 1470 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1471 { 1472 u16 reg = rtl8168_get_ocp_reg(tp); 1473 1474 return r8168dp_ocp_read(tp, reg) & BIT(15); 1475 } 1476 1477 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1478 { 1479 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1480 } 1481 1482 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1483 { 1484 switch (tp->dash_type) { 1485 case RTL_DASH_DP: 1486 return r8168dp_check_dash(tp); 1487 case RTL_DASH_EP: 1488 case RTL_DASH_25_BP: 1489 return r8168ep_check_dash(tp); 1490 default: 1491 return false; 1492 } 1493 } 1494 1495 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1496 { 1497 switch (tp->mac_version) { 1498 case RTL_GIGA_MAC_VER_28: 1499 case RTL_GIGA_MAC_VER_31: 1500 return RTL_DASH_DP; 1501 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: 1502 return RTL_DASH_EP; 1503 case RTL_GIGA_MAC_VER_66: 1504 return RTL_DASH_25_BP; 1505 default: 1506 return RTL_DASH_NONE; 1507 } 1508 } 1509 1510 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1511 { 1512 if (tp->mac_version >= RTL_GIGA_MAC_VER_25 && 1513 tp->mac_version != RTL_GIGA_MAC_VER_28 && 1514 tp->mac_version != RTL_GIGA_MAC_VER_31 && 1515 tp->mac_version != RTL_GIGA_MAC_VER_38) 1516 r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, !enable); 1517 } 1518 1519 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1520 { 1521 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1522 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1523 } 1524 1525 DECLARE_RTL_COND(rtl_efusear_cond) 1526 { 1527 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1528 } 1529 1530 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1531 { 1532 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1533 1534 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1535 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1536 } 1537 1538 static u32 rtl_get_events(struct rtl8169_private *tp) 1539 { 1540 if (rtl_is_8125(tp)) 1541 return RTL_R32(tp, IntrStatus_8125); 1542 else 1543 return RTL_R16(tp, IntrStatus); 1544 } 1545 1546 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1547 { 1548 if (rtl_is_8125(tp)) 1549 RTL_W32(tp, IntrStatus_8125, bits); 1550 else 1551 RTL_W16(tp, IntrStatus, bits); 1552 } 1553 1554 static void rtl_irq_disable(struct rtl8169_private *tp) 1555 { 1556 if (rtl_is_8125(tp)) 1557 RTL_W32(tp, IntrMask_8125, 0); 1558 else 1559 RTL_W16(tp, IntrMask, 0); 1560 } 1561 1562 static void rtl_irq_enable(struct rtl8169_private *tp) 1563 { 1564 if (rtl_is_8125(tp)) 1565 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1566 else 1567 RTL_W16(tp, IntrMask, tp->irq_mask); 1568 } 1569 1570 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1571 { 1572 rtl_irq_disable(tp); 1573 rtl_ack_events(tp, 0xffffffff); 1574 rtl_pci_commit(tp); 1575 } 1576 1577 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1578 { 1579 struct phy_device *phydev = tp->phydev; 1580 1581 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1582 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1583 if (phydev->speed == SPEED_1000) { 1584 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1585 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1586 } else if (phydev->speed == SPEED_100) { 1587 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1588 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1589 } else { 1590 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1591 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1592 } 1593 rtl_reset_packet_filter(tp); 1594 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1595 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1596 if (phydev->speed == SPEED_1000) { 1597 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1598 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1599 } else { 1600 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1601 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1602 } 1603 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1604 if (phydev->speed == SPEED_10) { 1605 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1606 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1607 } else { 1608 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1609 } 1610 } 1611 } 1612 1613 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1614 1615 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1616 { 1617 struct rtl8169_private *tp = netdev_priv(dev); 1618 1619 wol->supported = WAKE_ANY; 1620 wol->wolopts = tp->saved_wolopts; 1621 } 1622 1623 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1624 { 1625 rtl_unlock_config_regs(tp); 1626 1627 if (rtl_is_8168evl_up(tp)) { 1628 if (wolopts & WAKE_MAGIC) 1629 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1630 else 1631 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1632 } else if (rtl_is_8125(tp)) { 1633 if (wolopts & WAKE_MAGIC) 1634 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1635 else 1636 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1637 } else { 1638 r8169_mod_reg8_cond(tp, Config3, MagicPacket, 1639 wolopts & WAKE_MAGIC); 1640 } 1641 1642 r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY); 1643 if (rtl_is_8125(tp)) 1644 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, 1645 wolopts & WAKE_PHY ? 0x13 : 0); 1646 r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST); 1647 r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST); 1648 r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST); 1649 r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts); 1650 1651 switch (tp->mac_version) { 1652 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1653 r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts); 1654 break; 1655 case RTL_GIGA_MAC_VER_34: 1656 case RTL_GIGA_MAC_VER_37: 1657 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST: 1658 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); 1659 break; 1660 default: 1661 break; 1662 } 1663 1664 rtl_lock_config_regs(tp); 1665 1666 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1667 1668 if (!tp->dash_enabled) { 1669 rtl_set_d3_pll_down(tp, !wolopts); 1670 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1671 } 1672 } 1673 1674 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1675 { 1676 struct rtl8169_private *tp = netdev_priv(dev); 1677 1678 if (wol->wolopts & ~WAKE_ANY) 1679 return -EINVAL; 1680 1681 tp->saved_wolopts = wol->wolopts; 1682 __rtl8169_set_wol(tp, tp->saved_wolopts); 1683 1684 return 0; 1685 } 1686 1687 static void rtl8169_get_drvinfo(struct net_device *dev, 1688 struct ethtool_drvinfo *info) 1689 { 1690 struct rtl8169_private *tp = netdev_priv(dev); 1691 struct rtl_fw *rtl_fw = tp->rtl_fw; 1692 1693 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1694 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1695 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1696 if (rtl_fw) 1697 strscpy(info->fw_version, rtl_fw->version, 1698 sizeof(info->fw_version)); 1699 } 1700 1701 static int rtl8169_get_regs_len(struct net_device *dev) 1702 { 1703 return R8169_REGS_SIZE; 1704 } 1705 1706 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1707 netdev_features_t features) 1708 { 1709 struct rtl8169_private *tp = netdev_priv(dev); 1710 1711 if (dev->mtu > TD_MSS_MAX) 1712 features &= ~NETIF_F_ALL_TSO; 1713 1714 if (dev->mtu > ETH_DATA_LEN && 1715 tp->mac_version > RTL_GIGA_MAC_VER_06) 1716 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1717 1718 return features; 1719 } 1720 1721 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1722 netdev_features_t features) 1723 { 1724 u32 rx_config = RTL_R32(tp, RxConfig); 1725 1726 if (features & NETIF_F_RXALL) 1727 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1728 else 1729 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1730 1731 if (rtl_is_8125(tp)) { 1732 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1733 rx_config |= RX_VLAN_8125; 1734 else 1735 rx_config &= ~RX_VLAN_8125; 1736 } 1737 1738 RTL_W32(tp, RxConfig, rx_config); 1739 } 1740 1741 static int rtl8169_set_features(struct net_device *dev, 1742 netdev_features_t features) 1743 { 1744 struct rtl8169_private *tp = netdev_priv(dev); 1745 1746 rtl_set_rx_config_features(tp, features); 1747 1748 if (features & NETIF_F_RXCSUM) 1749 tp->cp_cmd |= RxChkSum; 1750 else 1751 tp->cp_cmd &= ~RxChkSum; 1752 1753 if (!rtl_is_8125(tp)) { 1754 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1755 tp->cp_cmd |= RxVlan; 1756 else 1757 tp->cp_cmd &= ~RxVlan; 1758 } 1759 1760 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1761 rtl_pci_commit(tp); 1762 1763 return 0; 1764 } 1765 1766 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1767 { 1768 return (skb_vlan_tag_present(skb)) ? 1769 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1770 } 1771 1772 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1773 { 1774 u32 opts2 = le32_to_cpu(desc->opts2); 1775 1776 if (opts2 & RxVlanTag) 1777 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1778 } 1779 1780 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1781 void *p) 1782 { 1783 struct rtl8169_private *tp = netdev_priv(dev); 1784 u32 __iomem *data = tp->mmio_addr; 1785 u32 *dw = p; 1786 int i; 1787 1788 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1789 memcpy_fromio(dw++, data++, 4); 1790 } 1791 1792 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1793 "tx_packets", 1794 "rx_packets", 1795 "tx_errors", 1796 "rx_errors", 1797 "rx_missed", 1798 "align_errors", 1799 "tx_single_collisions", 1800 "tx_multi_collisions", 1801 "unicast", 1802 "broadcast", 1803 "multicast", 1804 "tx_aborted", 1805 "tx_underrun", 1806 }; 1807 1808 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1809 { 1810 switch (sset) { 1811 case ETH_SS_STATS: 1812 return ARRAY_SIZE(rtl8169_gstrings); 1813 default: 1814 return -EOPNOTSUPP; 1815 } 1816 } 1817 1818 DECLARE_RTL_COND(rtl_counters_cond) 1819 { 1820 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1821 } 1822 1823 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1824 { 1825 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1826 1827 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1828 rtl_pci_commit(tp); 1829 RTL_W32(tp, CounterAddrLow, cmd); 1830 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1831 1832 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1833 } 1834 1835 static void rtl8169_update_counters(struct rtl8169_private *tp) 1836 { 1837 u8 val = RTL_R8(tp, ChipCmd); 1838 1839 /* 1840 * Some chips are unable to dump tally counters when the receiver 1841 * is disabled. If 0xff chip may be in a PCI power-save state. 1842 */ 1843 if (val & CmdRxEnb && val != 0xff) 1844 rtl8169_do_counters(tp, CounterDump); 1845 } 1846 1847 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1848 { 1849 struct rtl8169_counters *counters = tp->counters; 1850 1851 /* 1852 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1853 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1854 * reset by a power cycle, while the counter values collected by the 1855 * driver are reset at every driver unload/load cycle. 1856 * 1857 * To make sure the HW values returned by @get_stats64 match the SW 1858 * values, we collect the initial values at first open(*) and use them 1859 * as offsets to normalize the values returned by @get_stats64. 1860 * 1861 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1862 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1863 * set at open time by rtl_hw_start. 1864 */ 1865 1866 if (tp->tc_offset.inited) 1867 return; 1868 1869 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1870 rtl8169_do_counters(tp, CounterReset); 1871 } else { 1872 rtl8169_update_counters(tp); 1873 tp->tc_offset.tx_errors = counters->tx_errors; 1874 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1875 tp->tc_offset.tx_aborted = counters->tx_aborted; 1876 tp->tc_offset.rx_missed = counters->rx_missed; 1877 } 1878 1879 tp->tc_offset.inited = true; 1880 } 1881 1882 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1883 struct ethtool_stats *stats, u64 *data) 1884 { 1885 struct rtl8169_private *tp = netdev_priv(dev); 1886 struct rtl8169_counters *counters; 1887 1888 counters = tp->counters; 1889 rtl8169_update_counters(tp); 1890 1891 data[0] = le64_to_cpu(counters->tx_packets); 1892 data[1] = le64_to_cpu(counters->rx_packets); 1893 data[2] = le64_to_cpu(counters->tx_errors); 1894 data[3] = le32_to_cpu(counters->rx_errors); 1895 data[4] = le16_to_cpu(counters->rx_missed); 1896 data[5] = le16_to_cpu(counters->align_errors); 1897 data[6] = le32_to_cpu(counters->tx_one_collision); 1898 data[7] = le32_to_cpu(counters->tx_multi_collision); 1899 data[8] = le64_to_cpu(counters->rx_unicast); 1900 data[9] = le64_to_cpu(counters->rx_broadcast); 1901 data[10] = le32_to_cpu(counters->rx_multicast); 1902 data[11] = le16_to_cpu(counters->tx_aborted); 1903 data[12] = le16_to_cpu(counters->tx_underrun); 1904 } 1905 1906 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1907 { 1908 switch(stringset) { 1909 case ETH_SS_STATS: 1910 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1911 break; 1912 } 1913 } 1914 1915 /* 1916 * Interrupt coalescing 1917 * 1918 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1919 * > 8169, 8168 and 810x line of chipsets 1920 * 1921 * 8169, 8168, and 8136(810x) serial chipsets support it. 1922 * 1923 * > 2 - the Tx timer unit at gigabit speed 1924 * 1925 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1926 * (0xe0) bit 1 and bit 0. 1927 * 1928 * For 8169 1929 * bit[1:0] \ speed 1000M 100M 10M 1930 * 0 0 320ns 2.56us 40.96us 1931 * 0 1 2.56us 20.48us 327.7us 1932 * 1 0 5.12us 40.96us 655.4us 1933 * 1 1 10.24us 81.92us 1.31ms 1934 * 1935 * For the other 1936 * bit[1:0] \ speed 1000M 100M 10M 1937 * 0 0 5us 2.56us 40.96us 1938 * 0 1 40us 20.48us 327.7us 1939 * 1 0 80us 40.96us 655.4us 1940 * 1 1 160us 81.92us 1.31ms 1941 */ 1942 1943 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1944 struct rtl_coalesce_info { 1945 u32 speed; 1946 u32 scale_nsecs[4]; 1947 }; 1948 1949 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1950 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1951 1952 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1953 { SPEED_1000, COALESCE_DELAY(320) }, 1954 { SPEED_100, COALESCE_DELAY(2560) }, 1955 { SPEED_10, COALESCE_DELAY(40960) }, 1956 { 0 }, 1957 }; 1958 1959 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1960 { SPEED_1000, COALESCE_DELAY(5000) }, 1961 { SPEED_100, COALESCE_DELAY(2560) }, 1962 { SPEED_10, COALESCE_DELAY(40960) }, 1963 { 0 }, 1964 }; 1965 #undef COALESCE_DELAY 1966 1967 /* get rx/tx scale vector corresponding to current speed */ 1968 static const struct rtl_coalesce_info * 1969 rtl_coalesce_info(struct rtl8169_private *tp) 1970 { 1971 const struct rtl_coalesce_info *ci; 1972 1973 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1974 ci = rtl_coalesce_info_8169; 1975 else 1976 ci = rtl_coalesce_info_8168_8136; 1977 1978 /* if speed is unknown assume highest one */ 1979 if (tp->phydev->speed == SPEED_UNKNOWN) 1980 return ci; 1981 1982 for (; ci->speed; ci++) { 1983 if (tp->phydev->speed == ci->speed) 1984 return ci; 1985 } 1986 1987 return ERR_PTR(-ELNRNG); 1988 } 1989 1990 static int rtl_get_coalesce(struct net_device *dev, 1991 struct ethtool_coalesce *ec, 1992 struct kernel_ethtool_coalesce *kernel_coal, 1993 struct netlink_ext_ack *extack) 1994 { 1995 struct rtl8169_private *tp = netdev_priv(dev); 1996 const struct rtl_coalesce_info *ci; 1997 u32 scale, c_us, c_fr; 1998 u16 intrmit; 1999 2000 if (rtl_is_8125(tp)) 2001 return -EOPNOTSUPP; 2002 2003 memset(ec, 0, sizeof(*ec)); 2004 2005 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 2006 ci = rtl_coalesce_info(tp); 2007 if (IS_ERR(ci)) 2008 return PTR_ERR(ci); 2009 2010 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 2011 2012 intrmit = RTL_R16(tp, IntrMitigate); 2013 2014 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 2015 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 2016 2017 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 2018 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 2019 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 2020 2021 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 2022 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 2023 2024 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 2025 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 2026 2027 return 0; 2028 } 2029 2030 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 2031 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 2032 u16 *cp01) 2033 { 2034 const struct rtl_coalesce_info *ci; 2035 u16 i; 2036 2037 ci = rtl_coalesce_info(tp); 2038 if (IS_ERR(ci)) 2039 return PTR_ERR(ci); 2040 2041 for (i = 0; i < 4; i++) { 2042 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 2043 *cp01 = i; 2044 return ci->scale_nsecs[i]; 2045 } 2046 } 2047 2048 return -ERANGE; 2049 } 2050 2051 static int rtl_set_coalesce(struct net_device *dev, 2052 struct ethtool_coalesce *ec, 2053 struct kernel_ethtool_coalesce *kernel_coal, 2054 struct netlink_ext_ack *extack) 2055 { 2056 struct rtl8169_private *tp = netdev_priv(dev); 2057 u32 tx_fr = ec->tx_max_coalesced_frames; 2058 u32 rx_fr = ec->rx_max_coalesced_frames; 2059 u32 coal_usec_max, units; 2060 u16 w = 0, cp01 = 0; 2061 int scale; 2062 2063 if (rtl_is_8125(tp)) 2064 return -EOPNOTSUPP; 2065 2066 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 2067 return -ERANGE; 2068 2069 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 2070 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 2071 if (scale < 0) 2072 return scale; 2073 2074 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 2075 * not only when usecs=0 because of e.g. the following scenario: 2076 * 2077 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2078 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2079 * - then user does `ethtool -C eth0 rx-usecs 100` 2080 * 2081 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2082 * if we want to ignore rx_frames then it has to be set to 0. 2083 */ 2084 if (rx_fr == 1) 2085 rx_fr = 0; 2086 if (tx_fr == 1) 2087 tx_fr = 0; 2088 2089 /* HW requires time limit to be set if frame limit is set */ 2090 if ((tx_fr && !ec->tx_coalesce_usecs) || 2091 (rx_fr && !ec->rx_coalesce_usecs)) 2092 return -EINVAL; 2093 2094 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2095 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2096 2097 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2098 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2099 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2100 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2101 2102 RTL_W16(tp, IntrMitigate, w); 2103 2104 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2105 if (rtl_is_8168evl_up(tp)) { 2106 if (!rx_fr && !tx_fr) 2107 /* disable packet counter */ 2108 tp->cp_cmd |= PktCntrDisable; 2109 else 2110 tp->cp_cmd &= ~PktCntrDisable; 2111 } 2112 2113 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2114 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2115 rtl_pci_commit(tp); 2116 2117 return 0; 2118 } 2119 2120 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2121 { 2122 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2123 2124 switch (tp->mac_version) { 2125 case RTL_GIGA_MAC_VER_46: 2126 case RTL_GIGA_MAC_VER_48: 2127 tp->tx_lpi_timer = timer_val; 2128 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2129 break; 2130 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2131 tp->tx_lpi_timer = timer_val; 2132 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2133 break; 2134 default: 2135 break; 2136 } 2137 } 2138 2139 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2140 { 2141 unsigned int speed = tp->phydev->speed; 2142 unsigned int timer = tp->tx_lpi_timer; 2143 2144 if (!timer || speed == SPEED_UNKNOWN) 2145 return 0; 2146 2147 /* tx_lpi_timer value is in bytes */ 2148 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2149 } 2150 2151 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2152 { 2153 struct rtl8169_private *tp = netdev_priv(dev); 2154 int ret; 2155 2156 if (!rtl_supports_eee(tp)) 2157 return -EOPNOTSUPP; 2158 2159 ret = phy_ethtool_get_eee(tp->phydev, data); 2160 if (ret) 2161 return ret; 2162 2163 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2164 2165 return 0; 2166 } 2167 2168 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2169 { 2170 struct rtl8169_private *tp = netdev_priv(dev); 2171 2172 if (!rtl_supports_eee(tp)) 2173 return -EOPNOTSUPP; 2174 2175 return phy_ethtool_set_eee(tp->phydev, data); 2176 } 2177 2178 static void rtl8169_get_ringparam(struct net_device *dev, 2179 struct ethtool_ringparam *data, 2180 struct kernel_ethtool_ringparam *kernel_data, 2181 struct netlink_ext_ack *extack) 2182 { 2183 data->rx_max_pending = NUM_RX_DESC; 2184 data->rx_pending = NUM_RX_DESC; 2185 data->tx_max_pending = NUM_TX_DESC; 2186 data->tx_pending = NUM_TX_DESC; 2187 } 2188 2189 static void rtl8169_get_pause_stats(struct net_device *dev, 2190 struct ethtool_pause_stats *pause_stats) 2191 { 2192 struct rtl8169_private *tp = netdev_priv(dev); 2193 2194 if (!rtl_is_8125(tp)) 2195 return; 2196 2197 rtl8169_update_counters(tp); 2198 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on); 2199 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on); 2200 } 2201 2202 static void rtl8169_get_pauseparam(struct net_device *dev, 2203 struct ethtool_pauseparam *data) 2204 { 2205 struct rtl8169_private *tp = netdev_priv(dev); 2206 bool tx_pause, rx_pause; 2207 2208 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2209 2210 data->autoneg = tp->phydev->autoneg; 2211 data->tx_pause = tx_pause ? 1 : 0; 2212 data->rx_pause = rx_pause ? 1 : 0; 2213 } 2214 2215 static int rtl8169_set_pauseparam(struct net_device *dev, 2216 struct ethtool_pauseparam *data) 2217 { 2218 struct rtl8169_private *tp = netdev_priv(dev); 2219 2220 if (dev->mtu > ETH_DATA_LEN) 2221 return -EOPNOTSUPP; 2222 2223 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2224 2225 return 0; 2226 } 2227 2228 static void rtl8169_get_eth_mac_stats(struct net_device *dev, 2229 struct ethtool_eth_mac_stats *mac_stats) 2230 { 2231 struct rtl8169_private *tp = netdev_priv(dev); 2232 2233 rtl8169_update_counters(tp); 2234 2235 mac_stats->FramesTransmittedOK = 2236 le64_to_cpu(tp->counters->tx_packets); 2237 mac_stats->SingleCollisionFrames = 2238 le32_to_cpu(tp->counters->tx_one_collision); 2239 mac_stats->MultipleCollisionFrames = 2240 le32_to_cpu(tp->counters->tx_multi_collision); 2241 mac_stats->FramesReceivedOK = 2242 le64_to_cpu(tp->counters->rx_packets); 2243 mac_stats->AlignmentErrors = 2244 le16_to_cpu(tp->counters->align_errors); 2245 mac_stats->FramesLostDueToIntMACXmitError = 2246 le64_to_cpu(tp->counters->tx_errors); 2247 mac_stats->BroadcastFramesReceivedOK = 2248 le64_to_cpu(tp->counters->rx_broadcast); 2249 mac_stats->MulticastFramesReceivedOK = 2250 le32_to_cpu(tp->counters->rx_multicast); 2251 2252 if (!rtl_is_8125(tp)) 2253 return; 2254 2255 mac_stats->AlignmentErrors = 2256 le32_to_cpu(tp->counters->align_errors32); 2257 mac_stats->OctetsTransmittedOK = 2258 le64_to_cpu(tp->counters->tx_octets); 2259 mac_stats->LateCollisions = 2260 le32_to_cpu(tp->counters->tx_late_collision); 2261 mac_stats->FramesAbortedDueToXSColls = 2262 le32_to_cpu(tp->counters->tx_aborted32); 2263 mac_stats->OctetsReceivedOK = 2264 le64_to_cpu(tp->counters->rx_octets); 2265 mac_stats->FramesLostDueToIntMACRcvError = 2266 le32_to_cpu(tp->counters->rx_mac_error); 2267 mac_stats->MulticastFramesXmittedOK = 2268 le64_to_cpu(tp->counters->tx_multicast64); 2269 mac_stats->BroadcastFramesXmittedOK = 2270 le64_to_cpu(tp->counters->tx_broadcast64); 2271 mac_stats->MulticastFramesReceivedOK = 2272 le64_to_cpu(tp->counters->rx_multicast64); 2273 mac_stats->FrameTooLongErrors = 2274 le32_to_cpu(tp->counters->rx_frame_too_long); 2275 } 2276 2277 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, 2278 struct ethtool_eth_ctrl_stats *ctrl_stats) 2279 { 2280 struct rtl8169_private *tp = netdev_priv(dev); 2281 2282 if (!rtl_is_8125(tp)) 2283 return; 2284 2285 rtl8169_update_counters(tp); 2286 2287 ctrl_stats->UnsupportedOpcodesReceived = 2288 le32_to_cpu(tp->counters->rx_unknown_opcode); 2289 } 2290 2291 static const struct ethtool_ops rtl8169_ethtool_ops = { 2292 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2293 ETHTOOL_COALESCE_MAX_FRAMES, 2294 .get_drvinfo = rtl8169_get_drvinfo, 2295 .get_regs_len = rtl8169_get_regs_len, 2296 .get_link = ethtool_op_get_link, 2297 .get_coalesce = rtl_get_coalesce, 2298 .set_coalesce = rtl_set_coalesce, 2299 .get_regs = rtl8169_get_regs, 2300 .get_wol = rtl8169_get_wol, 2301 .set_wol = rtl8169_set_wol, 2302 .get_strings = rtl8169_get_strings, 2303 .get_sset_count = rtl8169_get_sset_count, 2304 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2305 .get_ts_info = ethtool_op_get_ts_info, 2306 .nway_reset = phy_ethtool_nway_reset, 2307 .get_eee = rtl8169_get_eee, 2308 .set_eee = rtl8169_set_eee, 2309 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2310 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2311 .get_ringparam = rtl8169_get_ringparam, 2312 .get_pause_stats = rtl8169_get_pause_stats, 2313 .get_pauseparam = rtl8169_get_pauseparam, 2314 .set_pauseparam = rtl8169_set_pauseparam, 2315 .get_eth_mac_stats = rtl8169_get_eth_mac_stats, 2316 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, 2317 }; 2318 2319 static const struct rtl_chip_info *rtl8169_get_chip_version(u16 xid, bool gmii) 2320 { 2321 /* Chips combining a 1Gbps MAC with a 100Mbps PHY */ 2322 static const struct rtl_chip_info rtl8106eus_info = { 2323 .mac_version = RTL_GIGA_MAC_VER_43, 2324 .name = "RTL8106eus", 2325 .fw_name = FIRMWARE_8106E_2, 2326 }; 2327 static const struct rtl_chip_info rtl8107e_info = { 2328 .mac_version = RTL_GIGA_MAC_VER_48, 2329 .name = "RTL8107e", 2330 .fw_name = FIRMWARE_8107E_2, 2331 }; 2332 const struct rtl_chip_info *p = rtl_chip_infos; 2333 2334 while ((xid & p->mask) != p->val) 2335 p++; 2336 2337 if (p->mac_version == RTL_GIGA_MAC_VER_42 && !gmii) 2338 return &rtl8106eus_info; 2339 if (p->mac_version == RTL_GIGA_MAC_VER_46 && !gmii) 2340 return &rtl8107e_info; 2341 2342 return p; 2343 } 2344 2345 static void rtl_release_firmware(struct rtl8169_private *tp) 2346 { 2347 if (tp->rtl_fw) { 2348 rtl_fw_release_firmware(tp->rtl_fw); 2349 kfree(tp->rtl_fw); 2350 tp->rtl_fw = NULL; 2351 } 2352 } 2353 2354 void r8169_apply_firmware(struct rtl8169_private *tp) 2355 { 2356 int val; 2357 2358 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2359 if (tp->rtl_fw) { 2360 rtl_fw_write_firmware(tp, tp->rtl_fw); 2361 /* At least one firmware doesn't reset tp->ocp_base. */ 2362 tp->ocp_base = OCP_STD_PHY_BASE; 2363 2364 /* PHY soft reset may still be in progress */ 2365 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2366 !(val & BMCR_RESET), 2367 50000, 600000, true); 2368 } 2369 } 2370 2371 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2372 { 2373 /* Adjust EEE LED frequency */ 2374 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2375 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2376 2377 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2378 } 2379 2380 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2381 { 2382 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2383 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2384 } 2385 2386 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2387 { 2388 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2389 } 2390 2391 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2392 { 2393 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2394 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2395 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2396 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2397 } 2398 2399 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2400 { 2401 u16 data1, data2, ioffset; 2402 2403 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2404 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2405 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2406 2407 ioffset = (data2 >> 1) & 0x7ff8; 2408 ioffset |= data2 & 0x0007; 2409 if (data1 & BIT(7)) 2410 ioffset |= BIT(15); 2411 2412 return ioffset; 2413 } 2414 2415 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2416 { 2417 set_bit(flag, tp->wk.flags); 2418 if (!schedule_work(&tp->wk.work)) 2419 clear_bit(flag, tp->wk.flags); 2420 } 2421 2422 static void rtl8169_init_phy(struct rtl8169_private *tp) 2423 { 2424 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2425 2426 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2427 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2428 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2429 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2430 RTL_W8(tp, 0x82, 0x01); 2431 } 2432 2433 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2434 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2435 tp->pci_dev->subsystem_device == 0xe000) 2436 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2437 2438 /* We may have called phy_speed_down before */ 2439 phy_speed_up(tp->phydev); 2440 2441 genphy_soft_reset(tp->phydev); 2442 } 2443 2444 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2445 { 2446 rtl_unlock_config_regs(tp); 2447 2448 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2449 rtl_pci_commit(tp); 2450 2451 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2452 rtl_pci_commit(tp); 2453 2454 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2455 rtl_rar_exgmac_set(tp, addr); 2456 2457 rtl_lock_config_regs(tp); 2458 } 2459 2460 static int rtl_set_mac_address(struct net_device *dev, void *p) 2461 { 2462 struct rtl8169_private *tp = netdev_priv(dev); 2463 int ret; 2464 2465 ret = eth_mac_addr(dev, p); 2466 if (ret) 2467 return ret; 2468 2469 rtl_rar_set(tp, dev->dev_addr); 2470 2471 return 0; 2472 } 2473 2474 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2475 { 2476 switch (tp->mac_version) { 2477 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2478 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2479 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2480 break; 2481 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2482 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2483 case RTL_GIGA_MAC_VER_38: 2484 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2485 break; 2486 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2487 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2488 break; 2489 case RTL_GIGA_MAC_VER_61: 2490 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2491 break; 2492 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 2493 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2494 RX_PAUSE_SLOT_ON); 2495 break; 2496 default: 2497 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2498 break; 2499 } 2500 } 2501 2502 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2503 { 2504 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2505 } 2506 2507 static void rtl_jumbo_config(struct rtl8169_private *tp) 2508 { 2509 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2510 int readrq = 4096; 2511 2512 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 && 2513 tp->mac_version <= RTL_GIGA_MAC_VER_26) 2514 readrq = 512; 2515 2516 rtl_unlock_config_regs(tp); 2517 switch (tp->mac_version) { 2518 case RTL_GIGA_MAC_VER_17: 2519 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2520 break; 2521 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2522 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2523 r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo); 2524 break; 2525 case RTL_GIGA_MAC_VER_28: 2526 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2527 break; 2528 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2529 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); 2530 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2531 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2532 break; 2533 default: 2534 break; 2535 } 2536 rtl_lock_config_regs(tp); 2537 2538 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2539 pcie_set_readrq(tp->pci_dev, readrq); 2540 2541 /* Chip doesn't support pause in jumbo mode */ 2542 if (jumbo) { 2543 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2544 tp->phydev->advertising); 2545 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2546 tp->phydev->advertising); 2547 phy_start_aneg(tp->phydev); 2548 } 2549 } 2550 2551 DECLARE_RTL_COND(rtl_chipcmd_cond) 2552 { 2553 return RTL_R8(tp, ChipCmd) & CmdReset; 2554 } 2555 2556 static void rtl_hw_reset(struct rtl8169_private *tp) 2557 { 2558 RTL_W8(tp, ChipCmd, CmdReset); 2559 2560 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2561 } 2562 2563 static void rtl_request_firmware(struct rtl8169_private *tp) 2564 { 2565 struct rtl_fw *rtl_fw; 2566 2567 /* firmware loaded already or no firmware available */ 2568 if (tp->rtl_fw || !tp->fw_name) 2569 return; 2570 2571 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2572 if (!rtl_fw) 2573 return; 2574 2575 rtl_fw->phy_write = rtl_writephy; 2576 rtl_fw->phy_read = rtl_readphy; 2577 rtl_fw->mac_mcu_write = mac_mcu_write; 2578 rtl_fw->mac_mcu_read = mac_mcu_read; 2579 rtl_fw->fw_name = tp->fw_name; 2580 rtl_fw->dev = tp_to_dev(tp); 2581 2582 if (rtl_fw_request_firmware(rtl_fw)) 2583 kfree(rtl_fw); 2584 else 2585 tp->rtl_fw = rtl_fw; 2586 } 2587 2588 static void rtl_rx_close(struct rtl8169_private *tp) 2589 { 2590 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2591 } 2592 2593 DECLARE_RTL_COND(rtl_npq_cond) 2594 { 2595 return RTL_R8(tp, TxPoll) & NPQ; 2596 } 2597 2598 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2599 { 2600 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2601 } 2602 2603 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2604 { 2605 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2606 } 2607 2608 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2609 { 2610 /* IntrMitigate has new functionality on RTL8125 */ 2611 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2612 } 2613 2614 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2615 { 2616 switch (tp->mac_version) { 2617 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2618 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2619 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2620 break; 2621 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2622 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2623 break; 2624 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 2625 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2626 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2627 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2628 break; 2629 default: 2630 break; 2631 } 2632 } 2633 2634 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2635 { 2636 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2637 } 2638 2639 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2640 { 2641 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2642 fsleep(2000); 2643 rtl_wait_txrx_fifo_empty(tp); 2644 } 2645 2646 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2647 { 2648 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2649 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2650 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2651 2652 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2653 rtl_disable_rxdvgate(tp); 2654 } 2655 2656 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2657 { 2658 if (tp->dash_enabled) 2659 return; 2660 2661 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2662 tp->mac_version == RTL_GIGA_MAC_VER_33) 2663 rtl_ephy_write(tp, 0x19, 0xff64); 2664 2665 if (device_may_wakeup(tp_to_dev(tp))) { 2666 phy_speed_down(tp->phydev, false); 2667 rtl_wol_enable_rx(tp); 2668 } 2669 } 2670 2671 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2672 { 2673 u32 val = TX_DMA_BURST << TxDMAShift | 2674 InterFrameGap << TxInterFrameGapShift; 2675 2676 if (rtl_is_8168evl_up(tp)) 2677 val |= TXCFG_AUTO_FIFO; 2678 2679 RTL_W32(tp, TxConfig, val); 2680 } 2681 2682 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2683 { 2684 /* Low hurts. Let's disable the filtering. */ 2685 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2686 } 2687 2688 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2689 { 2690 /* 2691 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2692 * register to be written before TxDescAddrLow to work. 2693 * Switching from MMIO to I/O access fixes the issue as well. 2694 */ 2695 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2696 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2697 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2698 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2699 } 2700 2701 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2702 { 2703 u32 val; 2704 2705 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2706 val = 0x000fff00; 2707 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2708 val = 0x00ffff00; 2709 else 2710 return; 2711 2712 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2713 val |= 0xff; 2714 2715 RTL_W32(tp, 0x7c, val); 2716 } 2717 2718 static void rtl_set_rx_mode(struct net_device *dev) 2719 { 2720 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2721 /* Multicast hash filter */ 2722 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2723 struct rtl8169_private *tp = netdev_priv(dev); 2724 u32 tmp; 2725 2726 if (dev->flags & IFF_PROMISC) { 2727 rx_mode |= AcceptAllPhys; 2728 } else if (!(dev->flags & IFF_MULTICAST)) { 2729 rx_mode &= ~AcceptMulticast; 2730 } else if (dev->flags & IFF_ALLMULTI || 2731 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2732 /* accept all multicasts */ 2733 } else if (netdev_mc_empty(dev)) { 2734 rx_mode &= ~AcceptMulticast; 2735 } else { 2736 struct netdev_hw_addr *ha; 2737 2738 mc_filter[1] = mc_filter[0] = 0; 2739 netdev_for_each_mc_addr(ha, dev) { 2740 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2741 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2742 } 2743 2744 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2745 tmp = mc_filter[0]; 2746 mc_filter[0] = swab32(mc_filter[1]); 2747 mc_filter[1] = swab32(tmp); 2748 } 2749 } 2750 2751 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2752 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2753 2754 tmp = RTL_R32(tp, RxConfig); 2755 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2756 } 2757 2758 DECLARE_RTL_COND(rtl_csiar_cond) 2759 { 2760 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2761 } 2762 2763 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2764 { 2765 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2766 2767 RTL_W32(tp, CSIDR, value); 2768 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2769 CSIAR_BYTE_ENABLE | func << 16); 2770 2771 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2772 } 2773 2774 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2775 { 2776 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2777 2778 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2779 CSIAR_BYTE_ENABLE); 2780 2781 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2782 RTL_R32(tp, CSIDR) : ~0; 2783 } 2784 2785 static void rtl_csi_mod(struct rtl8169_private *tp, int addr, 2786 u32 mask, u32 set) 2787 { 2788 u32 val; 2789 2790 WARN(addr % 4, "Invalid CSI address %#x\n", addr); 2791 2792 netdev_notice_once(tp->dev, 2793 "No native access to PCI extended config space, falling back to CSI\n"); 2794 2795 val = rtl_csi_read(tp, addr); 2796 rtl_csi_write(tp, addr, (val & ~mask) | set); 2797 } 2798 2799 static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp) 2800 { 2801 struct pci_dev *pdev = tp->pci_dev; 2802 int rc; 2803 u8 val; 2804 2805 #define RTL_GEN3_RELATED_OFF 0x0890 2806 #define RTL_GEN3_ZRXDC_NONCOMPL 0x1 2807 if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) { 2808 rc = pci_read_config_byte(pdev, RTL_GEN3_RELATED_OFF, &val); 2809 if (rc == PCIBIOS_SUCCESSFUL) { 2810 val &= ~RTL_GEN3_ZRXDC_NONCOMPL; 2811 rc = pci_write_config_byte(pdev, RTL_GEN3_RELATED_OFF, 2812 val); 2813 if (rc == PCIBIOS_SUCCESSFUL) 2814 return; 2815 } 2816 } 2817 2818 rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, 0); 2819 } 2820 2821 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2822 { 2823 struct pci_dev *pdev = tp->pci_dev; 2824 2825 /* According to Realtek the value at config space address 0x070f 2826 * controls the L0s/L1 entrance latency. We try standard ECAM access 2827 * first and if it fails fall back to CSI. 2828 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2829 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2830 */ 2831 if (pdev->cfg_size > 0x070f && 2832 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2833 return; 2834 2835 rtl_csi_mod(tp, 0x070c, 0xff000000, val << 24); 2836 } 2837 2838 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2839 { 2840 /* L0 7us, L1 16us */ 2841 rtl_set_aspm_entry_latency(tp, 0x27); 2842 } 2843 2844 struct ephy_info { 2845 unsigned int offset; 2846 u16 mask; 2847 u16 bits; 2848 }; 2849 2850 static void __rtl_ephy_init(struct rtl8169_private *tp, 2851 const struct ephy_info *e, int len) 2852 { 2853 u16 w; 2854 2855 while (len-- > 0) { 2856 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2857 rtl_ephy_write(tp, e->offset, w); 2858 e++; 2859 } 2860 } 2861 2862 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2863 2864 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2865 { 2866 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2867 PCI_EXP_LNKCTL_CLKREQ_EN); 2868 } 2869 2870 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2871 { 2872 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2873 PCI_EXP_LNKCTL_CLKREQ_EN); 2874 } 2875 2876 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2877 { 2878 /* work around an issue when PCI reset occurs during L2/L3 state */ 2879 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2880 } 2881 2882 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2883 { 2884 /* Bits control which events trigger ASPM L1 exit: 2885 * Bit 12: rxdv 2886 * Bit 11: ltr_msg 2887 * Bit 10: txdma_poll 2888 * Bit 9: xadm 2889 * Bit 8: pktavi 2890 * Bit 7: txpla 2891 */ 2892 switch (tp->mac_version) { 2893 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2894 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2895 break; 2896 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2897 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2898 break; 2899 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 2900 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2901 break; 2902 default: 2903 break; 2904 } 2905 } 2906 2907 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2908 { 2909 switch (tp->mac_version) { 2910 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2911 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2912 break; 2913 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 2914 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2915 break; 2916 default: 2917 break; 2918 } 2919 } 2920 2921 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2922 { 2923 u8 val8; 2924 2925 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2926 return; 2927 2928 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2929 if (enable && tp->aspm_manageable) { 2930 /* On these chip versions ASPM can even harm 2931 * bus communication of other PCI devices. 2932 */ 2933 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2934 tp->mac_version == RTL_GIGA_MAC_VER_43) 2935 return; 2936 2937 rtl_mod_config5(tp, 0, ASPM_en); 2938 switch (tp->mac_version) { 2939 case RTL_GIGA_MAC_VER_70: 2940 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2941 RTL_W8(tp, INT_CFG0_8125, val8); 2942 break; 2943 default: 2944 rtl_mod_config2(tp, 0, ClkReqEn); 2945 break; 2946 } 2947 2948 switch (tp->mac_version) { 2949 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2950 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2951 /* reset ephy tx/rx disable timer */ 2952 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2953 /* chip can trigger L1.2 */ 2954 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2955 break; 2956 default: 2957 break; 2958 } 2959 } else { 2960 switch (tp->mac_version) { 2961 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2962 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2963 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2964 break; 2965 default: 2966 break; 2967 } 2968 2969 switch (tp->mac_version) { 2970 case RTL_GIGA_MAC_VER_70: 2971 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2972 RTL_W8(tp, INT_CFG0_8125, val8); 2973 break; 2974 default: 2975 rtl_mod_config2(tp, ClkReqEn, 0); 2976 break; 2977 } 2978 rtl_mod_config5(tp, ASPM_en, 0); 2979 } 2980 } 2981 2982 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2983 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2984 { 2985 /* Usage of dynamic vs. static FIFO is controlled by bit 2986 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2987 */ 2988 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2989 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2990 } 2991 2992 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2993 u8 low, u8 high) 2994 { 2995 /* FIFO thresholds for pause flow control */ 2996 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2997 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2998 } 2999 3000 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3001 { 3002 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3003 } 3004 3005 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3006 { 3007 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3008 3009 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3010 3011 rtl_disable_clock_request(tp); 3012 } 3013 3014 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3015 { 3016 static const struct ephy_info e_info_8168cp[] = { 3017 { 0x01, 0, 0x0001 }, 3018 { 0x02, 0x0800, 0x1000 }, 3019 { 0x03, 0, 0x0042 }, 3020 { 0x06, 0x0080, 0x0000 }, 3021 { 0x07, 0, 0x2000 } 3022 }; 3023 3024 rtl_set_def_aspm_entry_latency(tp); 3025 3026 rtl_ephy_init(tp, e_info_8168cp); 3027 3028 __rtl_hw_start_8168cp(tp); 3029 } 3030 3031 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3032 { 3033 rtl_set_def_aspm_entry_latency(tp); 3034 3035 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3036 } 3037 3038 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3039 { 3040 rtl_set_def_aspm_entry_latency(tp); 3041 3042 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3043 3044 /* Magic. */ 3045 RTL_W8(tp, DBG_REG, 0x20); 3046 } 3047 3048 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3049 { 3050 static const struct ephy_info e_info_8168c_1[] = { 3051 { 0x02, 0x0800, 0x1000 }, 3052 { 0x03, 0, 0x0002 }, 3053 { 0x06, 0x0080, 0x0000 } 3054 }; 3055 3056 rtl_set_def_aspm_entry_latency(tp); 3057 3058 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3059 3060 rtl_ephy_init(tp, e_info_8168c_1); 3061 3062 __rtl_hw_start_8168cp(tp); 3063 } 3064 3065 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3066 { 3067 static const struct ephy_info e_info_8168c_2[] = { 3068 { 0x01, 0, 0x0001 }, 3069 { 0x03, 0x0400, 0x0020 } 3070 }; 3071 3072 rtl_set_def_aspm_entry_latency(tp); 3073 3074 rtl_ephy_init(tp, e_info_8168c_2); 3075 3076 __rtl_hw_start_8168cp(tp); 3077 } 3078 3079 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3080 { 3081 rtl_set_def_aspm_entry_latency(tp); 3082 3083 __rtl_hw_start_8168cp(tp); 3084 } 3085 3086 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3087 { 3088 rtl_set_def_aspm_entry_latency(tp); 3089 3090 rtl_disable_clock_request(tp); 3091 } 3092 3093 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3094 { 3095 static const struct ephy_info e_info_8168d_4[] = { 3096 { 0x0b, 0x0000, 0x0048 }, 3097 { 0x19, 0x0020, 0x0050 }, 3098 { 0x0c, 0x0100, 0x0020 }, 3099 { 0x10, 0x0004, 0x0000 }, 3100 }; 3101 3102 rtl_set_def_aspm_entry_latency(tp); 3103 3104 rtl_ephy_init(tp, e_info_8168d_4); 3105 3106 rtl_enable_clock_request(tp); 3107 } 3108 3109 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3110 { 3111 static const struct ephy_info e_info_8168e_1[] = { 3112 { 0x00, 0x0200, 0x0100 }, 3113 { 0x00, 0x0000, 0x0004 }, 3114 { 0x06, 0x0002, 0x0001 }, 3115 { 0x06, 0x0000, 0x0030 }, 3116 { 0x07, 0x0000, 0x2000 }, 3117 { 0x00, 0x0000, 0x0020 }, 3118 { 0x03, 0x5800, 0x2000 }, 3119 { 0x03, 0x0000, 0x0001 }, 3120 { 0x01, 0x0800, 0x1000 }, 3121 { 0x07, 0x0000, 0x4000 }, 3122 { 0x1e, 0x0000, 0x2000 }, 3123 { 0x19, 0xffff, 0xfe6c }, 3124 { 0x0a, 0x0000, 0x0040 } 3125 }; 3126 3127 rtl_set_def_aspm_entry_latency(tp); 3128 3129 rtl_ephy_init(tp, e_info_8168e_1); 3130 3131 rtl_disable_clock_request(tp); 3132 3133 /* Reset tx FIFO pointer */ 3134 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3135 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3136 3137 rtl_mod_config5(tp, Spi_en, 0); 3138 } 3139 3140 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3141 { 3142 static const struct ephy_info e_info_8168e_2[] = { 3143 { 0x09, 0x0000, 0x0080 }, 3144 { 0x19, 0x0000, 0x0224 }, 3145 { 0x00, 0x0000, 0x0004 }, 3146 { 0x0c, 0x3df0, 0x0200 }, 3147 }; 3148 3149 rtl_set_def_aspm_entry_latency(tp); 3150 3151 rtl_ephy_init(tp, e_info_8168e_2); 3152 3153 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3154 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3155 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3156 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3157 rtl_reset_packet_filter(tp); 3158 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3159 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3160 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3161 3162 rtl_disable_clock_request(tp); 3163 3164 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3165 3166 rtl8168_config_eee_mac(tp); 3167 3168 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3169 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3170 rtl_mod_config5(tp, Spi_en, 0); 3171 } 3172 3173 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3174 { 3175 rtl_set_def_aspm_entry_latency(tp); 3176 3177 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3178 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3179 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3180 rtl_reset_packet_filter(tp); 3181 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3182 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3183 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3184 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3185 3186 rtl_disable_clock_request(tp); 3187 3188 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3189 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3190 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3191 rtl_mod_config5(tp, Spi_en, 0); 3192 3193 rtl8168_config_eee_mac(tp); 3194 } 3195 3196 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3197 { 3198 static const struct ephy_info e_info_8168f_1[] = { 3199 { 0x06, 0x00c0, 0x0020 }, 3200 { 0x08, 0x0001, 0x0002 }, 3201 { 0x09, 0x0000, 0x0080 }, 3202 { 0x19, 0x0000, 0x0224 }, 3203 { 0x00, 0x0000, 0x0008 }, 3204 { 0x0c, 0x3df0, 0x0200 }, 3205 }; 3206 3207 rtl_hw_start_8168f(tp); 3208 3209 rtl_ephy_init(tp, e_info_8168f_1); 3210 } 3211 3212 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3213 { 3214 static const struct ephy_info e_info_8168f_1[] = { 3215 { 0x06, 0x00c0, 0x0020 }, 3216 { 0x0f, 0xffff, 0x5200 }, 3217 { 0x19, 0x0000, 0x0224 }, 3218 { 0x00, 0x0000, 0x0008 }, 3219 { 0x0c, 0x3df0, 0x0200 }, 3220 }; 3221 3222 rtl_hw_start_8168f(tp); 3223 rtl_pcie_state_l2l3_disable(tp); 3224 3225 rtl_ephy_init(tp, e_info_8168f_1); 3226 } 3227 3228 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3229 { 3230 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3231 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3232 3233 rtl_set_def_aspm_entry_latency(tp); 3234 3235 rtl_reset_packet_filter(tp); 3236 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3237 3238 rtl_disable_rxdvgate(tp); 3239 3240 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3241 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3242 3243 rtl8168_config_eee_mac(tp); 3244 3245 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3246 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3247 3248 rtl_pcie_state_l2l3_disable(tp); 3249 } 3250 3251 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3252 { 3253 static const struct ephy_info e_info_8168g_1[] = { 3254 { 0x00, 0x0008, 0x0000 }, 3255 { 0x0c, 0x3ff0, 0x0820 }, 3256 { 0x1e, 0x0000, 0x0001 }, 3257 { 0x19, 0x8000, 0x0000 } 3258 }; 3259 3260 rtl_hw_start_8168g(tp); 3261 rtl_ephy_init(tp, e_info_8168g_1); 3262 } 3263 3264 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3265 { 3266 static const struct ephy_info e_info_8168g_2[] = { 3267 { 0x00, 0x0008, 0x0000 }, 3268 { 0x0c, 0x3ff0, 0x0820 }, 3269 { 0x19, 0xffff, 0x7c00 }, 3270 { 0x1e, 0xffff, 0x20eb }, 3271 { 0x0d, 0xffff, 0x1666 }, 3272 { 0x00, 0xffff, 0x10a3 }, 3273 { 0x06, 0xffff, 0xf050 }, 3274 { 0x04, 0x0000, 0x0010 }, 3275 { 0x1d, 0x4000, 0x0000 }, 3276 }; 3277 3278 rtl_hw_start_8168g(tp); 3279 rtl_ephy_init(tp, e_info_8168g_2); 3280 } 3281 3282 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3283 { 3284 static const u16 fix_data[] = { 3285 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3286 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3287 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3288 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3289 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3290 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3291 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3292 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3293 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3294 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3295 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3296 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3297 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3298 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3299 }; 3300 unsigned long flags; 3301 int i; 3302 3303 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3304 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3305 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3306 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3307 } 3308 3309 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3310 { 3311 static const struct ephy_info e_info_8411_2[] = { 3312 { 0x00, 0x0008, 0x0000 }, 3313 { 0x0c, 0x37d0, 0x0820 }, 3314 { 0x1e, 0x0000, 0x0001 }, 3315 { 0x19, 0x8021, 0x0000 }, 3316 { 0x1e, 0x0000, 0x2000 }, 3317 { 0x0d, 0x0100, 0x0200 }, 3318 { 0x00, 0x0000, 0x0080 }, 3319 { 0x06, 0x0000, 0x0010 }, 3320 { 0x04, 0x0000, 0x0010 }, 3321 { 0x1d, 0x0000, 0x4000 }, 3322 }; 3323 3324 rtl_hw_start_8168g(tp); 3325 3326 rtl_ephy_init(tp, e_info_8411_2); 3327 3328 /* The following Realtek-provided magic fixes an issue with the RX unit 3329 * getting confused after the PHY having been powered-down. 3330 */ 3331 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3332 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3333 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3334 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3335 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3336 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3337 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3338 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3339 mdelay(3); 3340 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3341 3342 rtl8411b_fix_phy_down(tp); 3343 3344 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3345 3346 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3347 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3348 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3349 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3350 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3351 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3352 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3353 } 3354 3355 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3356 { 3357 static const struct ephy_info e_info_8168h_1[] = { 3358 { 0x1e, 0x0800, 0x0001 }, 3359 { 0x1d, 0x0000, 0x0800 }, 3360 { 0x05, 0xffff, 0x2089 }, 3361 { 0x06, 0xffff, 0x5881 }, 3362 { 0x04, 0xffff, 0x854a }, 3363 { 0x01, 0xffff, 0x068b } 3364 }; 3365 int rg_saw_cnt; 3366 3367 rtl_ephy_init(tp, e_info_8168h_1); 3368 3369 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3370 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3371 3372 rtl_set_def_aspm_entry_latency(tp); 3373 3374 rtl_reset_packet_filter(tp); 3375 3376 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3377 3378 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3379 3380 rtl_disable_rxdvgate(tp); 3381 3382 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3383 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3384 3385 rtl8168_config_eee_mac(tp); 3386 3387 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3388 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3389 3390 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3391 3392 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3393 3394 rtl_pcie_state_l2l3_disable(tp); 3395 3396 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3397 if (rg_saw_cnt > 0) { 3398 u16 sw_cnt_1ms_ini; 3399 3400 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3401 sw_cnt_1ms_ini &= 0x0fff; 3402 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3403 } 3404 3405 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3406 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3407 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3408 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3409 3410 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3411 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3412 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3413 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3414 } 3415 3416 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3417 { 3418 rtl8168ep_stop_cmac(tp); 3419 3420 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3421 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3422 3423 rtl_set_def_aspm_entry_latency(tp); 3424 3425 rtl_reset_packet_filter(tp); 3426 3427 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3428 3429 rtl_disable_rxdvgate(tp); 3430 3431 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3432 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3433 3434 rtl8168_config_eee_mac(tp); 3435 3436 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3437 3438 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3439 3440 rtl_pcie_state_l2l3_disable(tp); 3441 } 3442 3443 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3444 { 3445 static const struct ephy_info e_info_8168ep_3[] = { 3446 { 0x00, 0x0000, 0x0080 }, 3447 { 0x0d, 0x0100, 0x0200 }, 3448 { 0x19, 0x8021, 0x0000 }, 3449 { 0x1e, 0x0000, 0x2000 }, 3450 }; 3451 3452 rtl_ephy_init(tp, e_info_8168ep_3); 3453 3454 rtl_hw_start_8168ep(tp); 3455 3456 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3457 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3458 3459 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3460 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3461 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3462 } 3463 3464 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3465 { 3466 static const struct ephy_info e_info_8117[] = { 3467 { 0x19, 0x0040, 0x1100 }, 3468 { 0x59, 0x0040, 0x1100 }, 3469 }; 3470 int rg_saw_cnt; 3471 3472 rtl8168ep_stop_cmac(tp); 3473 rtl_ephy_init(tp, e_info_8117); 3474 3475 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3476 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3477 3478 rtl_set_def_aspm_entry_latency(tp); 3479 3480 rtl_reset_packet_filter(tp); 3481 3482 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3483 3484 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3485 3486 rtl_disable_rxdvgate(tp); 3487 3488 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3489 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3490 3491 rtl8168_config_eee_mac(tp); 3492 3493 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3494 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3495 3496 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3497 3498 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3499 3500 rtl_pcie_state_l2l3_disable(tp); 3501 3502 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3503 if (rg_saw_cnt > 0) { 3504 u16 sw_cnt_1ms_ini; 3505 3506 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3507 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3508 } 3509 3510 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3511 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3512 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3513 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3514 3515 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3516 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3517 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3518 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3519 3520 /* firmware is for MAC only */ 3521 r8169_apply_firmware(tp); 3522 } 3523 3524 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3525 { 3526 static const struct ephy_info e_info_8102e_1[] = { 3527 { 0x01, 0, 0x6e65 }, 3528 { 0x02, 0, 0x091f }, 3529 { 0x03, 0, 0xc2f9 }, 3530 { 0x06, 0, 0xafb5 }, 3531 { 0x07, 0, 0x0e00 }, 3532 { 0x19, 0, 0xec80 }, 3533 { 0x01, 0, 0x2e65 }, 3534 { 0x01, 0, 0x6e65 } 3535 }; 3536 u8 cfg1; 3537 3538 rtl_set_def_aspm_entry_latency(tp); 3539 3540 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3541 3542 RTL_W8(tp, Config1, 3543 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3544 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3545 3546 cfg1 = RTL_R8(tp, Config1); 3547 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3548 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3549 3550 rtl_ephy_init(tp, e_info_8102e_1); 3551 } 3552 3553 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3554 { 3555 rtl_set_def_aspm_entry_latency(tp); 3556 3557 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3558 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3559 } 3560 3561 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3562 { 3563 rtl_hw_start_8102e_2(tp); 3564 3565 rtl_ephy_write(tp, 0x03, 0xc2f9); 3566 } 3567 3568 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3569 { 3570 static const struct ephy_info e_info_8401[] = { 3571 { 0x01, 0xffff, 0x6fe5 }, 3572 { 0x03, 0xffff, 0x0599 }, 3573 { 0x06, 0xffff, 0xaf25 }, 3574 { 0x07, 0xffff, 0x8e68 }, 3575 }; 3576 3577 rtl_ephy_init(tp, e_info_8401); 3578 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3579 } 3580 3581 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3582 { 3583 static const struct ephy_info e_info_8105e_1[] = { 3584 { 0x07, 0, 0x4000 }, 3585 { 0x19, 0, 0x0200 }, 3586 { 0x19, 0, 0x0020 }, 3587 { 0x1e, 0, 0x2000 }, 3588 { 0x03, 0, 0x0001 }, 3589 { 0x19, 0, 0x0100 }, 3590 { 0x19, 0, 0x0004 }, 3591 { 0x0a, 0, 0x0020 } 3592 }; 3593 3594 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3595 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3596 3597 /* Disable Early Tally Counter */ 3598 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3599 3600 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3601 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3602 3603 rtl_ephy_init(tp, e_info_8105e_1); 3604 3605 rtl_pcie_state_l2l3_disable(tp); 3606 } 3607 3608 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3609 { 3610 rtl_hw_start_8105e_1(tp); 3611 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3612 } 3613 3614 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3615 { 3616 static const struct ephy_info e_info_8402[] = { 3617 { 0x19, 0xffff, 0xff64 }, 3618 { 0x1e, 0, 0x4000 } 3619 }; 3620 3621 rtl_set_def_aspm_entry_latency(tp); 3622 3623 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3624 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3625 3626 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3627 3628 rtl_ephy_init(tp, e_info_8402); 3629 3630 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3631 rtl_reset_packet_filter(tp); 3632 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3633 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3634 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3635 3636 /* disable EEE */ 3637 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3638 3639 rtl_pcie_state_l2l3_disable(tp); 3640 } 3641 3642 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3643 { 3644 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3645 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3646 3647 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3648 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3649 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3650 3651 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3652 rtl_set_aspm_entry_latency(tp, 0x2f); 3653 3654 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3655 3656 /* disable EEE */ 3657 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3658 3659 rtl_pcie_state_l2l3_disable(tp); 3660 } 3661 3662 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3663 { 3664 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3665 } 3666 3667 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3668 { 3669 rtl_pcie_state_l2l3_disable(tp); 3670 3671 RTL_W16(tp, 0x382, 0x221b); 3672 RTL_W32(tp, RSS_CTRL_8125, 0); 3673 RTL_W16(tp, Q_NUM_CTRL_8125, 0); 3674 3675 /* disable UPS */ 3676 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3677 3678 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3679 3680 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3681 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3682 3683 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3684 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3685 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3686 3687 /* disable new tx descriptor format */ 3688 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3689 3690 if (tp->mac_version == RTL_GIGA_MAC_VER_70) 3691 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3692 3693 if (tp->mac_version == RTL_GIGA_MAC_VER_70) 3694 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3695 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3696 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3697 else 3698 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3699 3700 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3701 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3702 else 3703 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3704 3705 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3706 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3707 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3708 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3709 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3710 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3711 if (tp->mac_version == RTL_GIGA_MAC_VER_70) 3712 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3713 else 3714 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3715 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3716 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3717 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3718 3719 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3720 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3721 udelay(1); 3722 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3723 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3724 3725 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3726 3727 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3728 3729 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3730 rtl8125a_config_eee_mac(tp); 3731 else 3732 rtl8125b_config_eee_mac(tp); 3733 3734 rtl_disable_rxdvgate(tp); 3735 } 3736 3737 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3738 { 3739 static const struct ephy_info e_info_8125a_2[] = { 3740 { 0x04, 0xffff, 0xd000 }, 3741 { 0x0a, 0xffff, 0x8653 }, 3742 { 0x23, 0xffff, 0xab66 }, 3743 { 0x20, 0xffff, 0x9455 }, 3744 { 0x21, 0xffff, 0x99ff }, 3745 { 0x29, 0xffff, 0xfe04 }, 3746 3747 { 0x44, 0xffff, 0xd000 }, 3748 { 0x4a, 0xffff, 0x8653 }, 3749 { 0x63, 0xffff, 0xab66 }, 3750 { 0x60, 0xffff, 0x9455 }, 3751 { 0x61, 0xffff, 0x99ff }, 3752 { 0x69, 0xffff, 0xfe04 }, 3753 }; 3754 3755 rtl_set_def_aspm_entry_latency(tp); 3756 rtl_ephy_init(tp, e_info_8125a_2); 3757 rtl_hw_start_8125_common(tp); 3758 } 3759 3760 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3761 { 3762 static const struct ephy_info e_info_8125b[] = { 3763 { 0x0b, 0xffff, 0xa908 }, 3764 { 0x1e, 0xffff, 0x20eb }, 3765 { 0x4b, 0xffff, 0xa908 }, 3766 { 0x5e, 0xffff, 0x20eb }, 3767 { 0x22, 0x0030, 0x0020 }, 3768 { 0x62, 0x0030, 0x0020 }, 3769 }; 3770 3771 rtl_set_def_aspm_entry_latency(tp); 3772 rtl_ephy_init(tp, e_info_8125b); 3773 rtl_hw_start_8125_common(tp); 3774 } 3775 3776 static void rtl_hw_start_8125d(struct rtl8169_private *tp) 3777 { 3778 rtl_set_def_aspm_entry_latency(tp); 3779 rtl_hw_start_8125_common(tp); 3780 } 3781 3782 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3783 { 3784 rtl_disable_zrxdc_timeout(tp); 3785 rtl_set_def_aspm_entry_latency(tp); 3786 rtl_hw_start_8125_common(tp); 3787 } 3788 3789 static void rtl_hw_config(struct rtl8169_private *tp) 3790 { 3791 static const rtl_generic_fct hw_configs[] = { 3792 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3793 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3794 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3795 [RTL_GIGA_MAC_VER_10] = NULL, 3796 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3797 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3798 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3799 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3800 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3801 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3802 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3803 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3804 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3805 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3806 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3807 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3808 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3809 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3810 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3811 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3812 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3813 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3814 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3815 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3816 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3817 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3818 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3819 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3820 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3821 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3822 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3823 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3824 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3825 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3826 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3827 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3828 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3829 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, 3830 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, 3831 [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, 3832 }; 3833 3834 if (hw_configs[tp->mac_version]) 3835 hw_configs[tp->mac_version](tp); 3836 } 3837 3838 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3839 { 3840 int i; 3841 3842 RTL_W8(tp, INT_CFG0_8125, 0x00); 3843 3844 /* disable interrupt coalescing */ 3845 switch (tp->mac_version) { 3846 case RTL_GIGA_MAC_VER_61: 3847 case RTL_GIGA_MAC_VER_64: 3848 case RTL_GIGA_MAC_VER_66: 3849 for (i = 0xa00; i < 0xb00; i += 4) 3850 RTL_W32(tp, i, 0); 3851 break; 3852 case RTL_GIGA_MAC_VER_63: 3853 case RTL_GIGA_MAC_VER_70: 3854 for (i = 0xa00; i < 0xa80; i += 4) 3855 RTL_W32(tp, i, 0); 3856 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3857 break; 3858 default: 3859 break; 3860 } 3861 3862 /* enable extended tally counter */ 3863 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); 3864 3865 rtl_hw_config(tp); 3866 } 3867 3868 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3869 { 3870 if (rtl_is_8168evl_up(tp)) 3871 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3872 else 3873 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3874 3875 rtl_hw_config(tp); 3876 3877 /* disable interrupt coalescing */ 3878 RTL_W16(tp, IntrMitigate, 0x0000); 3879 } 3880 3881 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3882 { 3883 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3884 3885 tp->cp_cmd |= PCIMulRW; 3886 3887 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3888 tp->mac_version == RTL_GIGA_MAC_VER_03) 3889 tp->cp_cmd |= EnAnaPLL; 3890 3891 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3892 3893 rtl8169_set_magic_reg(tp); 3894 3895 /* disable interrupt coalescing */ 3896 RTL_W16(tp, IntrMitigate, 0x0000); 3897 } 3898 3899 static void rtl_hw_start(struct rtl8169_private *tp) 3900 { 3901 rtl_unlock_config_regs(tp); 3902 /* disable aspm and clock request before ephy access */ 3903 rtl_hw_aspm_clkreq_enable(tp, false); 3904 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3905 3906 rtl_set_eee_txidle_timer(tp); 3907 3908 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3909 rtl_hw_start_8169(tp); 3910 else if (rtl_is_8125(tp)) 3911 rtl_hw_start_8125(tp); 3912 else 3913 rtl_hw_start_8168(tp); 3914 3915 rtl_enable_exit_l1(tp); 3916 rtl_hw_aspm_clkreq_enable(tp, true); 3917 rtl_set_rx_max_size(tp); 3918 rtl_set_rx_tx_desc_registers(tp); 3919 rtl_lock_config_regs(tp); 3920 3921 rtl_jumbo_config(tp); 3922 3923 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3924 rtl_pci_commit(tp); 3925 3926 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3927 rtl_init_rxcfg(tp); 3928 rtl_set_tx_config_registers(tp); 3929 rtl_set_rx_config_features(tp, tp->dev->features); 3930 rtl_set_rx_mode(tp->dev); 3931 rtl_irq_enable(tp); 3932 } 3933 3934 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3935 { 3936 struct rtl8169_private *tp = netdev_priv(dev); 3937 3938 WRITE_ONCE(dev->mtu, new_mtu); 3939 netdev_update_features(dev); 3940 rtl_jumbo_config(tp); 3941 rtl_set_eee_txidle_timer(tp); 3942 3943 return 0; 3944 } 3945 3946 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3947 { 3948 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3949 3950 desc->opts2 = 0; 3951 /* Force memory writes to complete before releasing descriptor */ 3952 dma_wmb(); 3953 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3954 } 3955 3956 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3957 struct RxDesc *desc) 3958 { 3959 struct device *d = tp_to_dev(tp); 3960 int node = dev_to_node(d); 3961 dma_addr_t mapping; 3962 struct page *data; 3963 3964 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3965 if (!data) 3966 return NULL; 3967 3968 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3969 if (unlikely(dma_mapping_error(d, mapping))) { 3970 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3971 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3972 return NULL; 3973 } 3974 3975 desc->addr = cpu_to_le64(mapping); 3976 rtl8169_mark_to_asic(desc); 3977 3978 return data; 3979 } 3980 3981 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3982 { 3983 int i; 3984 3985 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3986 dma_unmap_page(tp_to_dev(tp), 3987 le64_to_cpu(tp->RxDescArray[i].addr), 3988 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3989 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3990 tp->Rx_databuff[i] = NULL; 3991 tp->RxDescArray[i].addr = 0; 3992 tp->RxDescArray[i].opts1 = 0; 3993 } 3994 } 3995 3996 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3997 { 3998 int i; 3999 4000 for (i = 0; i < NUM_RX_DESC; i++) { 4001 struct page *data; 4002 4003 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4004 if (!data) { 4005 rtl8169_rx_clear(tp); 4006 return -ENOMEM; 4007 } 4008 tp->Rx_databuff[i] = data; 4009 } 4010 4011 /* mark as last descriptor in the ring */ 4012 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4013 4014 return 0; 4015 } 4016 4017 static int rtl8169_init_ring(struct rtl8169_private *tp) 4018 { 4019 rtl8169_init_ring_indexes(tp); 4020 4021 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4022 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4023 4024 return rtl8169_rx_fill(tp); 4025 } 4026 4027 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4028 { 4029 struct ring_info *tx_skb = tp->tx_skb + entry; 4030 struct TxDesc *desc = tp->TxDescArray + entry; 4031 4032 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4033 DMA_TO_DEVICE); 4034 memset(desc, 0, sizeof(*desc)); 4035 memset(tx_skb, 0, sizeof(*tx_skb)); 4036 } 4037 4038 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4039 unsigned int n) 4040 { 4041 unsigned int i; 4042 4043 for (i = 0; i < n; i++) { 4044 unsigned int entry = (start + i) % NUM_TX_DESC; 4045 struct ring_info *tx_skb = tp->tx_skb + entry; 4046 unsigned int len = tx_skb->len; 4047 4048 if (len) { 4049 struct sk_buff *skb = tx_skb->skb; 4050 4051 rtl8169_unmap_tx_skb(tp, entry); 4052 if (skb) 4053 dev_consume_skb_any(skb); 4054 } 4055 } 4056 } 4057 4058 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4059 { 4060 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4061 netdev_reset_queue(tp->dev); 4062 } 4063 4064 static void rtl8169_cleanup(struct rtl8169_private *tp) 4065 { 4066 napi_disable(&tp->napi); 4067 4068 /* Give a racing hard_start_xmit a few cycles to complete. */ 4069 synchronize_net(); 4070 4071 /* Disable interrupts */ 4072 rtl8169_irq_mask_and_ack(tp); 4073 4074 rtl_rx_close(tp); 4075 4076 switch (tp->mac_version) { 4077 case RTL_GIGA_MAC_VER_28: 4078 case RTL_GIGA_MAC_VER_31: 4079 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4080 break; 4081 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4082 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4083 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4084 break; 4085 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 4086 rtl_enable_rxdvgate(tp); 4087 fsleep(2000); 4088 break; 4089 default: 4090 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4091 fsleep(100); 4092 break; 4093 } 4094 4095 rtl_hw_reset(tp); 4096 4097 rtl8169_tx_clear(tp); 4098 rtl8169_init_ring_indexes(tp); 4099 } 4100 4101 static void rtl_reset_work(struct rtl8169_private *tp) 4102 { 4103 int i; 4104 4105 netif_stop_queue(tp->dev); 4106 4107 rtl8169_cleanup(tp); 4108 4109 for (i = 0; i < NUM_RX_DESC; i++) 4110 rtl8169_mark_to_asic(tp->RxDescArray + i); 4111 4112 napi_enable(&tp->napi); 4113 rtl_hw_start(tp); 4114 } 4115 4116 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4117 { 4118 struct rtl8169_private *tp = netdev_priv(dev); 4119 4120 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4121 } 4122 4123 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4124 void *addr, unsigned int entry, bool desc_own) 4125 { 4126 struct TxDesc *txd = tp->TxDescArray + entry; 4127 struct device *d = tp_to_dev(tp); 4128 dma_addr_t mapping; 4129 u32 opts1; 4130 int ret; 4131 4132 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4133 ret = dma_mapping_error(d, mapping); 4134 if (unlikely(ret)) { 4135 if (net_ratelimit()) 4136 netdev_err(tp->dev, "Failed to map TX data!\n"); 4137 return ret; 4138 } 4139 4140 txd->addr = cpu_to_le64(mapping); 4141 txd->opts2 = cpu_to_le32(opts[1]); 4142 4143 opts1 = opts[0] | len; 4144 if (entry == NUM_TX_DESC - 1) 4145 opts1 |= RingEnd; 4146 if (desc_own) 4147 opts1 |= DescOwn; 4148 txd->opts1 = cpu_to_le32(opts1); 4149 4150 tp->tx_skb[entry].len = len; 4151 4152 return 0; 4153 } 4154 4155 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4156 const u32 *opts, unsigned int entry) 4157 { 4158 struct skb_shared_info *info = skb_shinfo(skb); 4159 unsigned int cur_frag; 4160 4161 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4162 const skb_frag_t *frag = info->frags + cur_frag; 4163 void *addr = skb_frag_address(frag); 4164 u32 len = skb_frag_size(frag); 4165 4166 entry = (entry + 1) % NUM_TX_DESC; 4167 4168 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4169 goto err_out; 4170 } 4171 4172 return 0; 4173 4174 err_out: 4175 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4176 return -EIO; 4177 } 4178 4179 static bool rtl_skb_is_udp(struct sk_buff *skb) 4180 { 4181 int no = skb_network_offset(skb); 4182 struct ipv6hdr *i6h, _i6h; 4183 struct iphdr *ih, _ih; 4184 4185 switch (vlan_get_protocol(skb)) { 4186 case htons(ETH_P_IP): 4187 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4188 return ih && ih->protocol == IPPROTO_UDP; 4189 case htons(ETH_P_IPV6): 4190 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4191 return i6h && i6h->nexthdr == IPPROTO_UDP; 4192 default: 4193 return false; 4194 } 4195 } 4196 4197 #define RTL_MIN_PATCH_LEN 47 4198 4199 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4200 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4201 struct sk_buff *skb) 4202 { 4203 unsigned int padto = 0, len = skb->len; 4204 4205 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) && 4206 skb_transport_header_was_set(skb)) { 4207 unsigned int trans_data_len = skb_tail_pointer(skb) - 4208 skb_transport_header(skb); 4209 4210 if (trans_data_len >= offsetof(struct udphdr, len) && 4211 trans_data_len < RTL_MIN_PATCH_LEN) { 4212 u16 dest = ntohs(udp_hdr(skb)->dest); 4213 4214 /* dest is a standard PTP port */ 4215 if (dest == 319 || dest == 320) 4216 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4217 } 4218 4219 if (trans_data_len < sizeof(struct udphdr)) 4220 padto = max_t(unsigned int, padto, 4221 len + sizeof(struct udphdr) - trans_data_len); 4222 } 4223 4224 return padto; 4225 } 4226 4227 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4228 struct sk_buff *skb) 4229 { 4230 unsigned int padto = 0; 4231 4232 switch (tp->mac_version) { 4233 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 4234 padto = rtl8125_quirk_udp_padto(tp, skb); 4235 break; 4236 default: 4237 break; 4238 } 4239 4240 switch (tp->mac_version) { 4241 case RTL_GIGA_MAC_VER_34: 4242 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 4243 padto = max_t(unsigned int, padto, ETH_ZLEN); 4244 break; 4245 default: 4246 break; 4247 } 4248 4249 return padto; 4250 } 4251 4252 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4253 { 4254 u32 mss = skb_shinfo(skb)->gso_size; 4255 4256 if (mss) { 4257 opts[0] |= TD_LSO; 4258 opts[0] |= mss << TD0_MSS_SHIFT; 4259 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4260 const struct iphdr *ip = ip_hdr(skb); 4261 4262 if (ip->protocol == IPPROTO_TCP) 4263 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4264 else if (ip->protocol == IPPROTO_UDP) 4265 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4266 else 4267 WARN_ON_ONCE(1); 4268 } 4269 } 4270 4271 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4272 struct sk_buff *skb, u32 *opts) 4273 { 4274 struct skb_shared_info *shinfo = skb_shinfo(skb); 4275 u32 mss = shinfo->gso_size; 4276 4277 if (mss) { 4278 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4279 opts[0] |= TD1_GTSENV4; 4280 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4281 if (skb_cow_head(skb, 0)) 4282 return false; 4283 4284 tcp_v6_gso_csum_prep(skb); 4285 opts[0] |= TD1_GTSENV6; 4286 } else { 4287 WARN_ON_ONCE(1); 4288 } 4289 4290 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4291 opts[1] |= mss << TD1_MSS_SHIFT; 4292 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4293 u8 ip_protocol; 4294 4295 switch (vlan_get_protocol(skb)) { 4296 case htons(ETH_P_IP): 4297 opts[1] |= TD1_IPv4_CS; 4298 ip_protocol = ip_hdr(skb)->protocol; 4299 break; 4300 4301 case htons(ETH_P_IPV6): 4302 opts[1] |= TD1_IPv6_CS; 4303 ip_protocol = ipv6_hdr(skb)->nexthdr; 4304 break; 4305 4306 default: 4307 ip_protocol = IPPROTO_RAW; 4308 break; 4309 } 4310 4311 if (ip_protocol == IPPROTO_TCP) 4312 opts[1] |= TD1_TCP_CS; 4313 else if (ip_protocol == IPPROTO_UDP) 4314 opts[1] |= TD1_UDP_CS; 4315 else 4316 WARN_ON_ONCE(1); 4317 4318 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4319 } else { 4320 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4321 4322 /* skb_padto would free the skb on error */ 4323 return !__skb_put_padto(skb, padto, false); 4324 } 4325 4326 return true; 4327 } 4328 4329 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4330 { 4331 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4332 } 4333 4334 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4335 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4336 { 4337 switch (tp->mac_version) { 4338 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4339 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4340 return false; 4341 default: 4342 return true; 4343 } 4344 } 4345 4346 static void rtl8169_doorbell(struct rtl8169_private *tp) 4347 { 4348 if (rtl_is_8125(tp)) 4349 RTL_W16(tp, TxPoll_8125, BIT(0)); 4350 else 4351 RTL_W8(tp, TxPoll, NPQ); 4352 } 4353 4354 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4355 struct net_device *dev) 4356 { 4357 struct rtl8169_private *tp = netdev_priv(dev); 4358 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4359 struct TxDesc *txd_first, *txd_last; 4360 bool stop_queue, door_bell; 4361 unsigned int frags; 4362 u32 opts[2]; 4363 4364 if (unlikely(!rtl_tx_slots_avail(tp))) { 4365 if (net_ratelimit()) 4366 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4367 netif_stop_queue(dev); 4368 return NETDEV_TX_BUSY; 4369 } 4370 4371 opts[1] = rtl8169_tx_vlan_tag(skb); 4372 opts[0] = 0; 4373 4374 if (!rtl_chip_supports_csum_v2(tp)) 4375 rtl8169_tso_csum_v1(skb, opts); 4376 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4377 goto err_dma_0; 4378 4379 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4380 entry, false))) 4381 goto err_dma_0; 4382 4383 txd_first = tp->TxDescArray + entry; 4384 4385 frags = skb_shinfo(skb)->nr_frags; 4386 if (frags) { 4387 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4388 goto err_dma_1; 4389 entry = (entry + frags) % NUM_TX_DESC; 4390 } 4391 4392 txd_last = tp->TxDescArray + entry; 4393 txd_last->opts1 |= cpu_to_le32(LastFrag); 4394 tp->tx_skb[entry].skb = skb; 4395 4396 skb_tx_timestamp(skb); 4397 4398 /* Force memory writes to complete before releasing descriptor */ 4399 dma_wmb(); 4400 4401 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4402 4403 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4404 4405 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4406 smp_wmb(); 4407 4408 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4409 4410 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4411 R8169_TX_STOP_THRS, 4412 R8169_TX_START_THRS); 4413 if (door_bell || stop_queue) 4414 rtl8169_doorbell(tp); 4415 4416 return NETDEV_TX_OK; 4417 4418 err_dma_1: 4419 rtl8169_unmap_tx_skb(tp, entry); 4420 err_dma_0: 4421 dev_kfree_skb_any(skb); 4422 dev->stats.tx_dropped++; 4423 return NETDEV_TX_OK; 4424 } 4425 4426 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4427 { 4428 struct skb_shared_info *info = skb_shinfo(skb); 4429 unsigned int nr_frags = info->nr_frags; 4430 4431 if (!nr_frags) 4432 return UINT_MAX; 4433 4434 return skb_frag_size(info->frags + nr_frags - 1); 4435 } 4436 4437 /* Workaround for hw issues with TSO on RTL8168evl */ 4438 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4439 netdev_features_t features) 4440 { 4441 /* IPv4 header has options field */ 4442 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4443 ip_hdrlen(skb) > sizeof(struct iphdr)) 4444 features &= ~NETIF_F_ALL_TSO; 4445 4446 /* IPv4 TCP header has options field */ 4447 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4448 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4449 features &= ~NETIF_F_ALL_TSO; 4450 4451 else if (rtl_last_frag_len(skb) <= 6) 4452 features &= ~NETIF_F_ALL_TSO; 4453 4454 return features; 4455 } 4456 4457 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4458 struct net_device *dev, 4459 netdev_features_t features) 4460 { 4461 struct rtl8169_private *tp = netdev_priv(dev); 4462 4463 if (skb_is_gso(skb)) { 4464 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4465 features = rtl8168evl_fix_tso(skb, features); 4466 4467 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4468 rtl_chip_supports_csum_v2(tp)) 4469 features &= ~NETIF_F_ALL_TSO; 4470 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4471 /* work around hw bug on some chip versions */ 4472 if (skb->len < ETH_ZLEN) 4473 features &= ~NETIF_F_CSUM_MASK; 4474 4475 if (rtl_quirk_packet_padto(tp, skb)) 4476 features &= ~NETIF_F_CSUM_MASK; 4477 4478 if (skb_transport_offset(skb) > TCPHO_MAX && 4479 rtl_chip_supports_csum_v2(tp)) 4480 features &= ~NETIF_F_CSUM_MASK; 4481 } 4482 4483 return vlan_features_check(skb, features); 4484 } 4485 4486 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4487 { 4488 struct rtl8169_private *tp = netdev_priv(dev); 4489 struct pci_dev *pdev = tp->pci_dev; 4490 int pci_status_errs; 4491 u16 pci_cmd; 4492 4493 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4494 4495 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4496 4497 if (net_ratelimit()) 4498 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4499 pci_cmd, pci_status_errs); 4500 4501 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4502 } 4503 4504 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4505 int budget) 4506 { 4507 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4508 struct sk_buff *skb; 4509 4510 dirty_tx = tp->dirty_tx; 4511 4512 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4513 unsigned int entry = dirty_tx % NUM_TX_DESC; 4514 u32 status; 4515 4516 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4517 if (status & DescOwn) 4518 break; 4519 4520 skb = tp->tx_skb[entry].skb; 4521 rtl8169_unmap_tx_skb(tp, entry); 4522 4523 if (skb) { 4524 pkts_compl++; 4525 bytes_compl += skb->len; 4526 napi_consume_skb(skb, budget); 4527 } 4528 dirty_tx++; 4529 } 4530 4531 if (tp->dirty_tx != dirty_tx) { 4532 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4533 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4534 4535 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4536 rtl_tx_slots_avail(tp), 4537 R8169_TX_START_THRS); 4538 /* 4539 * 8168 hack: TxPoll requests are lost when the Tx packets are 4540 * too close. Let's kick an extra TxPoll request when a burst 4541 * of start_xmit activity is detected (if it is not detected, 4542 * it is slow enough). -- FR 4543 * If skb is NULL then we come here again once a tx irq is 4544 * triggered after the last fragment is marked transmitted. 4545 */ 4546 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4547 rtl8169_doorbell(tp); 4548 } 4549 } 4550 4551 static inline int rtl8169_fragmented_frame(u32 status) 4552 { 4553 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4554 } 4555 4556 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4557 { 4558 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4559 4560 if (status == RxProtoTCP || status == RxProtoUDP) 4561 skb->ip_summed = CHECKSUM_UNNECESSARY; 4562 else 4563 skb_checksum_none_assert(skb); 4564 } 4565 4566 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4567 { 4568 struct device *d = tp_to_dev(tp); 4569 int count; 4570 4571 for (count = 0; count < budget; count++, tp->cur_rx++) { 4572 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4573 struct RxDesc *desc = tp->RxDescArray + entry; 4574 struct sk_buff *skb; 4575 const void *rx_buf; 4576 dma_addr_t addr; 4577 u32 status; 4578 4579 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4580 if (status & DescOwn) 4581 break; 4582 4583 /* This barrier is needed to keep us from reading 4584 * any other fields out of the Rx descriptor until 4585 * we know the status of DescOwn 4586 */ 4587 dma_rmb(); 4588 4589 if (unlikely(status & RxRES)) { 4590 if (net_ratelimit()) 4591 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4592 status); 4593 dev->stats.rx_errors++; 4594 if (status & (RxRWT | RxRUNT)) 4595 dev->stats.rx_length_errors++; 4596 if (status & RxCRC) 4597 dev->stats.rx_crc_errors++; 4598 4599 if (!(dev->features & NETIF_F_RXALL)) 4600 goto release_descriptor; 4601 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4602 goto release_descriptor; 4603 } 4604 4605 pkt_size = status & GENMASK(13, 0); 4606 if (likely(!(dev->features & NETIF_F_RXFCS))) 4607 pkt_size -= ETH_FCS_LEN; 4608 4609 /* The driver does not support incoming fragmented frames. 4610 * They are seen as a symptom of over-mtu sized frames. 4611 */ 4612 if (unlikely(rtl8169_fragmented_frame(status))) { 4613 dev->stats.rx_dropped++; 4614 dev->stats.rx_length_errors++; 4615 goto release_descriptor; 4616 } 4617 4618 skb = napi_alloc_skb(&tp->napi, pkt_size); 4619 if (unlikely(!skb)) { 4620 dev->stats.rx_dropped++; 4621 goto release_descriptor; 4622 } 4623 4624 addr = le64_to_cpu(desc->addr); 4625 rx_buf = page_address(tp->Rx_databuff[entry]); 4626 4627 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4628 prefetch(rx_buf); 4629 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4630 skb->tail += pkt_size; 4631 skb->len = pkt_size; 4632 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4633 4634 rtl8169_rx_csum(skb, status); 4635 skb->protocol = eth_type_trans(skb, dev); 4636 4637 rtl8169_rx_vlan_tag(desc, skb); 4638 4639 if (skb->pkt_type == PACKET_MULTICAST) 4640 dev->stats.multicast++; 4641 4642 napi_gro_receive(&tp->napi, skb); 4643 4644 dev_sw_netstats_rx_add(dev, pkt_size); 4645 release_descriptor: 4646 rtl8169_mark_to_asic(desc); 4647 } 4648 4649 return count; 4650 } 4651 4652 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4653 { 4654 struct rtl8169_private *tp = dev_instance; 4655 u32 status = rtl_get_events(tp); 4656 4657 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4658 return IRQ_NONE; 4659 4660 /* At least RTL8168fp may unexpectedly set the SYSErr bit */ 4661 if (unlikely(status & SYSErr && 4662 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { 4663 rtl8169_pcierr_interrupt(tp->dev); 4664 goto out; 4665 } 4666 4667 if (status & LinkChg) 4668 phy_mac_interrupt(tp->phydev); 4669 4670 rtl_irq_disable(tp); 4671 napi_schedule(&tp->napi); 4672 out: 4673 rtl_ack_events(tp, status); 4674 4675 return IRQ_HANDLED; 4676 } 4677 4678 static void rtl_task(struct work_struct *work) 4679 { 4680 struct rtl8169_private *tp = 4681 container_of(work, struct rtl8169_private, wk.work); 4682 int ret; 4683 4684 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4685 /* if chip isn't accessible, reset bus to revive it */ 4686 if (RTL_R32(tp, TxConfig) == ~0) { 4687 ret = pci_reset_bus(tp->pci_dev); 4688 if (ret < 0) { 4689 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4690 netif_device_detach(tp->dev); 4691 return; 4692 } 4693 } 4694 4695 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4696 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4697 PCIE_LINK_STATE_L0S); 4698 if (!ret) 4699 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4700 goto reset; 4701 } 4702 4703 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4704 reset: 4705 rtl_reset_work(tp); 4706 netif_wake_queue(tp->dev); 4707 } 4708 } 4709 4710 static int rtl8169_poll(struct napi_struct *napi, int budget) 4711 { 4712 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4713 struct net_device *dev = tp->dev; 4714 int work_done; 4715 4716 rtl_tx(dev, tp, budget); 4717 4718 work_done = rtl_rx(dev, tp, budget); 4719 4720 if (work_done < budget && napi_complete_done(napi, work_done)) 4721 rtl_irq_enable(tp); 4722 4723 return work_done; 4724 } 4725 4726 static void r8169_phylink_handler(struct net_device *ndev) 4727 { 4728 struct rtl8169_private *tp = netdev_priv(ndev); 4729 struct device *d = tp_to_dev(tp); 4730 4731 if (netif_carrier_ok(ndev)) { 4732 rtl_link_chg_patch(tp); 4733 pm_request_resume(d); 4734 } else { 4735 pm_runtime_idle(d); 4736 } 4737 4738 phy_print_status(tp->phydev); 4739 } 4740 4741 static int r8169_phy_connect(struct rtl8169_private *tp) 4742 { 4743 struct phy_device *phydev = tp->phydev; 4744 phy_interface_t phy_mode; 4745 int ret; 4746 4747 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4748 PHY_INTERFACE_MODE_MII; 4749 4750 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4751 phy_mode); 4752 if (ret) 4753 return ret; 4754 4755 if (!tp->supports_gmii) 4756 phy_set_max_speed(phydev, SPEED_100); 4757 4758 phy_attached_info(phydev); 4759 4760 return 0; 4761 } 4762 4763 static void rtl8169_down(struct rtl8169_private *tp) 4764 { 4765 disable_work_sync(&tp->wk.work); 4766 /* Clear all task flags */ 4767 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4768 4769 phy_stop(tp->phydev); 4770 4771 rtl8169_update_counters(tp); 4772 4773 pci_clear_master(tp->pci_dev); 4774 rtl_pci_commit(tp); 4775 4776 rtl8169_cleanup(tp); 4777 rtl_disable_exit_l1(tp); 4778 rtl_prepare_power_down(tp); 4779 4780 if (tp->dash_type != RTL_DASH_NONE) 4781 rtl8168_driver_stop(tp); 4782 } 4783 4784 static void rtl8169_up(struct rtl8169_private *tp) 4785 { 4786 if (tp->dash_type != RTL_DASH_NONE) 4787 rtl8168_driver_start(tp); 4788 4789 pci_set_master(tp->pci_dev); 4790 phy_init_hw(tp->phydev); 4791 phy_resume(tp->phydev); 4792 rtl8169_init_phy(tp); 4793 napi_enable(&tp->napi); 4794 enable_work(&tp->wk.work); 4795 rtl_reset_work(tp); 4796 4797 phy_start(tp->phydev); 4798 } 4799 4800 static int rtl8169_close(struct net_device *dev) 4801 { 4802 struct rtl8169_private *tp = netdev_priv(dev); 4803 struct pci_dev *pdev = tp->pci_dev; 4804 4805 pm_runtime_get_sync(&pdev->dev); 4806 4807 netif_stop_queue(dev); 4808 rtl8169_down(tp); 4809 rtl8169_rx_clear(tp); 4810 4811 free_irq(tp->irq, tp); 4812 4813 phy_disconnect(tp->phydev); 4814 4815 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4816 tp->RxPhyAddr); 4817 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4818 tp->TxPhyAddr); 4819 tp->TxDescArray = NULL; 4820 tp->RxDescArray = NULL; 4821 4822 pm_runtime_put_sync(&pdev->dev); 4823 4824 return 0; 4825 } 4826 4827 #ifdef CONFIG_NET_POLL_CONTROLLER 4828 static void rtl8169_netpoll(struct net_device *dev) 4829 { 4830 struct rtl8169_private *tp = netdev_priv(dev); 4831 4832 rtl8169_interrupt(tp->irq, tp); 4833 } 4834 #endif 4835 4836 static int rtl_open(struct net_device *dev) 4837 { 4838 struct rtl8169_private *tp = netdev_priv(dev); 4839 struct pci_dev *pdev = tp->pci_dev; 4840 unsigned long irqflags; 4841 int retval = -ENOMEM; 4842 4843 pm_runtime_get_sync(&pdev->dev); 4844 4845 /* 4846 * Rx and Tx descriptors needs 256 bytes alignment. 4847 * dma_alloc_coherent provides more. 4848 */ 4849 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4850 &tp->TxPhyAddr, GFP_KERNEL); 4851 if (!tp->TxDescArray) 4852 goto out; 4853 4854 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4855 &tp->RxPhyAddr, GFP_KERNEL); 4856 if (!tp->RxDescArray) 4857 goto err_free_tx_0; 4858 4859 retval = rtl8169_init_ring(tp); 4860 if (retval < 0) 4861 goto err_free_rx_1; 4862 4863 rtl_request_firmware(tp); 4864 4865 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4866 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4867 if (retval < 0) 4868 goto err_release_fw_2; 4869 4870 retval = r8169_phy_connect(tp); 4871 if (retval) 4872 goto err_free_irq; 4873 4874 rtl8169_up(tp); 4875 rtl8169_init_counter_offsets(tp); 4876 netif_start_queue(dev); 4877 out: 4878 pm_runtime_put_sync(&pdev->dev); 4879 4880 return retval; 4881 4882 err_free_irq: 4883 free_irq(tp->irq, tp); 4884 err_release_fw_2: 4885 rtl_release_firmware(tp); 4886 rtl8169_rx_clear(tp); 4887 err_free_rx_1: 4888 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4889 tp->RxPhyAddr); 4890 tp->RxDescArray = NULL; 4891 err_free_tx_0: 4892 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4893 tp->TxPhyAddr); 4894 tp->TxDescArray = NULL; 4895 goto out; 4896 } 4897 4898 static void 4899 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4900 { 4901 struct rtl8169_private *tp = netdev_priv(dev); 4902 struct pci_dev *pdev = tp->pci_dev; 4903 struct rtl8169_counters *counters = tp->counters; 4904 4905 pm_runtime_get_noresume(&pdev->dev); 4906 4907 netdev_stats_to_stats64(stats, &dev->stats); 4908 dev_fetch_sw_netstats(stats, dev->tstats); 4909 4910 /* 4911 * Fetch additional counter values missing in stats collected by driver 4912 * from tally counters. 4913 */ 4914 if (pm_runtime_active(&pdev->dev)) 4915 rtl8169_update_counters(tp); 4916 4917 /* 4918 * Subtract values fetched during initalization. 4919 * See rtl8169_init_counter_offsets for a description why we do that. 4920 */ 4921 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4922 le64_to_cpu(tp->tc_offset.tx_errors); 4923 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4924 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4925 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4926 le16_to_cpu(tp->tc_offset.tx_aborted); 4927 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4928 le16_to_cpu(tp->tc_offset.rx_missed); 4929 4930 pm_runtime_put_noidle(&pdev->dev); 4931 } 4932 4933 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4934 { 4935 netif_device_detach(tp->dev); 4936 4937 if (netif_running(tp->dev)) 4938 rtl8169_down(tp); 4939 } 4940 4941 static int rtl8169_runtime_resume(struct device *dev) 4942 { 4943 struct rtl8169_private *tp = dev_get_drvdata(dev); 4944 4945 rtl_rar_set(tp, tp->dev->dev_addr); 4946 __rtl8169_set_wol(tp, tp->saved_wolopts); 4947 4948 if (tp->TxDescArray) 4949 rtl8169_up(tp); 4950 4951 netif_device_attach(tp->dev); 4952 4953 return 0; 4954 } 4955 4956 static int rtl8169_suspend(struct device *device) 4957 { 4958 struct rtl8169_private *tp = dev_get_drvdata(device); 4959 4960 rtnl_lock(); 4961 rtl8169_net_suspend(tp); 4962 if (!device_may_wakeup(tp_to_dev(tp))) 4963 clk_disable_unprepare(tp->clk); 4964 rtnl_unlock(); 4965 4966 return 0; 4967 } 4968 4969 static int rtl8169_resume(struct device *device) 4970 { 4971 struct rtl8169_private *tp = dev_get_drvdata(device); 4972 4973 if (!device_may_wakeup(tp_to_dev(tp))) 4974 clk_prepare_enable(tp->clk); 4975 4976 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4977 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4978 rtl_init_rxcfg(tp); 4979 4980 return rtl8169_runtime_resume(device); 4981 } 4982 4983 static int rtl8169_runtime_suspend(struct device *device) 4984 { 4985 struct rtl8169_private *tp = dev_get_drvdata(device); 4986 4987 if (!tp->TxDescArray) { 4988 netif_device_detach(tp->dev); 4989 return 0; 4990 } 4991 4992 rtnl_lock(); 4993 __rtl8169_set_wol(tp, WAKE_PHY); 4994 rtl8169_net_suspend(tp); 4995 rtnl_unlock(); 4996 4997 return 0; 4998 } 4999 5000 static int rtl8169_runtime_idle(struct device *device) 5001 { 5002 struct rtl8169_private *tp = dev_get_drvdata(device); 5003 5004 if (tp->dash_enabled) 5005 return -EBUSY; 5006 5007 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5008 pm_schedule_suspend(device, 10000); 5009 5010 return -EBUSY; 5011 } 5012 5013 static const struct dev_pm_ops rtl8169_pm_ops = { 5014 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5015 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5016 rtl8169_runtime_idle) 5017 }; 5018 5019 static void rtl_shutdown(struct pci_dev *pdev) 5020 { 5021 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5022 5023 rtnl_lock(); 5024 rtl8169_net_suspend(tp); 5025 rtnl_unlock(); 5026 5027 /* Restore original MAC address */ 5028 rtl_rar_set(tp, tp->dev->perm_addr); 5029 5030 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) 5031 pci_prepare_to_sleep(pdev); 5032 } 5033 5034 static void rtl_remove_one(struct pci_dev *pdev) 5035 { 5036 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5037 5038 if (pci_dev_run_wake(pdev)) 5039 pm_runtime_get_noresume(&pdev->dev); 5040 5041 disable_work_sync(&tp->wk.work); 5042 5043 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5044 r8169_remove_leds(tp->leds); 5045 5046 unregister_netdev(tp->dev); 5047 5048 if (tp->dash_type != RTL_DASH_NONE) 5049 rtl8168_driver_stop(tp); 5050 5051 rtl_release_firmware(tp); 5052 5053 /* restore original MAC address */ 5054 rtl_rar_set(tp, tp->dev->perm_addr); 5055 } 5056 5057 static const struct net_device_ops rtl_netdev_ops = { 5058 .ndo_open = rtl_open, 5059 .ndo_stop = rtl8169_close, 5060 .ndo_get_stats64 = rtl8169_get_stats64, 5061 .ndo_start_xmit = rtl8169_start_xmit, 5062 .ndo_features_check = rtl8169_features_check, 5063 .ndo_tx_timeout = rtl8169_tx_timeout, 5064 .ndo_validate_addr = eth_validate_addr, 5065 .ndo_change_mtu = rtl8169_change_mtu, 5066 .ndo_fix_features = rtl8169_fix_features, 5067 .ndo_set_features = rtl8169_set_features, 5068 .ndo_set_mac_address = rtl_set_mac_address, 5069 .ndo_eth_ioctl = phy_do_ioctl_running, 5070 .ndo_set_rx_mode = rtl_set_rx_mode, 5071 #ifdef CONFIG_NET_POLL_CONTROLLER 5072 .ndo_poll_controller = rtl8169_netpoll, 5073 #endif 5074 5075 }; 5076 5077 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5078 { 5079 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5080 5081 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5082 tp->irq_mask |= SYSErr | RxFIFOOver; 5083 } 5084 5085 static int rtl_alloc_irq(struct rtl8169_private *tp) 5086 { 5087 unsigned int flags; 5088 5089 switch (tp->mac_version) { 5090 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5091 rtl_unlock_config_regs(tp); 5092 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5093 rtl_lock_config_regs(tp); 5094 fallthrough; 5095 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5096 flags = PCI_IRQ_INTX; 5097 break; 5098 default: 5099 flags = PCI_IRQ_ALL_TYPES; 5100 break; 5101 } 5102 5103 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5104 } 5105 5106 static void rtl_read_mac_address(struct rtl8169_private *tp, 5107 u8 mac_addr[ETH_ALEN]) 5108 { 5109 /* Get MAC address */ 5110 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5111 u32 value; 5112 5113 value = rtl_eri_read(tp, 0xe0); 5114 put_unaligned_le32(value, mac_addr); 5115 value = rtl_eri_read(tp, 0xe4); 5116 put_unaligned_le16(value, mac_addr + 4); 5117 } else if (rtl_is_8125(tp)) { 5118 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5119 } 5120 } 5121 5122 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5123 { 5124 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5125 } 5126 5127 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5128 { 5129 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5130 } 5131 5132 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5133 { 5134 struct rtl8169_private *tp = mii_bus->priv; 5135 5136 if (phyaddr > 0) 5137 return -ENODEV; 5138 5139 return rtl_readphy(tp, phyreg); 5140 } 5141 5142 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5143 int phyreg, u16 val) 5144 { 5145 struct rtl8169_private *tp = mii_bus->priv; 5146 5147 if (phyaddr > 0) 5148 return -ENODEV; 5149 5150 rtl_writephy(tp, phyreg, val); 5151 5152 return 0; 5153 } 5154 5155 static int r8169_mdio_read_reg_c45(struct mii_bus *mii_bus, int addr, 5156 int devnum, int regnum) 5157 { 5158 struct rtl8169_private *tp = mii_bus->priv; 5159 5160 if (addr > 0) 5161 return -ENODEV; 5162 5163 if (devnum == MDIO_MMD_VEND2 && regnum > MDIO_STAT2) 5164 return r8168_phy_ocp_read(tp, regnum); 5165 5166 return 0; 5167 } 5168 5169 static int r8169_mdio_write_reg_c45(struct mii_bus *mii_bus, int addr, 5170 int devnum, int regnum, u16 val) 5171 { 5172 struct rtl8169_private *tp = mii_bus->priv; 5173 5174 if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2) 5175 return -ENODEV; 5176 5177 r8168_phy_ocp_write(tp, regnum, val); 5178 5179 return 0; 5180 } 5181 5182 static int r8169_mdio_register(struct rtl8169_private *tp) 5183 { 5184 struct pci_dev *pdev = tp->pci_dev; 5185 struct mii_bus *new_bus; 5186 int ret; 5187 5188 /* On some boards with this chip version the BIOS is buggy and misses 5189 * to reset the PHY page selector. This results in the PHY ID read 5190 * accessing registers on a different page, returning a more or 5191 * less random value. Fix this by resetting the page selector first. 5192 */ 5193 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5194 tp->mac_version == RTL_GIGA_MAC_VER_26) 5195 r8169_mdio_write(tp, 0x1f, 0); 5196 5197 new_bus = devm_mdiobus_alloc(&pdev->dev); 5198 if (!new_bus) 5199 return -ENOMEM; 5200 5201 new_bus->name = "r8169"; 5202 new_bus->priv = tp; 5203 new_bus->parent = &pdev->dev; 5204 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5205 new_bus->phy_mask = GENMASK(31, 1); 5206 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5207 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5208 5209 new_bus->read = r8169_mdio_read_reg; 5210 new_bus->write = r8169_mdio_write_reg; 5211 5212 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) { 5213 new_bus->read_c45 = r8169_mdio_read_reg_c45; 5214 new_bus->write_c45 = r8169_mdio_write_reg_c45; 5215 } 5216 5217 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5218 if (ret) 5219 return ret; 5220 5221 tp->phydev = mdiobus_get_phy(new_bus, 0); 5222 if (!tp->phydev) { 5223 return -ENODEV; 5224 } else if (!tp->phydev->drv) { 5225 /* Most chip versions fail with the genphy driver. 5226 * Therefore ensure that the dedicated PHY driver is loaded. 5227 */ 5228 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5229 tp->phydev->phy_id); 5230 return -EUNATCH; 5231 } 5232 5233 tp->phydev->mac_managed_pm = true; 5234 if (rtl_supports_eee(tp)) 5235 phy_support_eee(tp->phydev); 5236 phy_support_asym_pause(tp->phydev); 5237 5238 /* mimic behavior of r8125/r8126 vendor drivers */ 5239 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 5240 phy_disable_eee_mode(tp->phydev, 5241 ETHTOOL_LINK_MODE_2500baseT_Full_BIT); 5242 phy_disable_eee_mode(tp->phydev, ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 5243 5244 /* PHY will be woken up in rtl_open() */ 5245 phy_suspend(tp->phydev); 5246 5247 return 0; 5248 } 5249 5250 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5251 { 5252 rtl_enable_rxdvgate(tp); 5253 5254 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5255 msleep(1); 5256 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5257 5258 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5259 r8168g_wait_ll_share_fifo_ready(tp); 5260 5261 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5262 r8168g_wait_ll_share_fifo_ready(tp); 5263 } 5264 5265 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5266 { 5267 rtl_enable_rxdvgate(tp); 5268 5269 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5270 msleep(1); 5271 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5272 5273 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5274 r8168g_wait_ll_share_fifo_ready(tp); 5275 5276 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5277 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5278 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5279 r8168g_wait_ll_share_fifo_ready(tp); 5280 } 5281 5282 static void rtl_hw_initialize(struct rtl8169_private *tp) 5283 { 5284 switch (tp->mac_version) { 5285 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: 5286 rtl8168ep_stop_cmac(tp); 5287 fallthrough; 5288 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5289 rtl_hw_init_8168g(tp); 5290 break; 5291 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 5292 rtl_hw_init_8125(tp); 5293 break; 5294 default: 5295 break; 5296 } 5297 } 5298 5299 static int rtl_jumbo_max(struct rtl8169_private *tp) 5300 { 5301 /* Non-GBit versions don't support jumbo frames */ 5302 if (!tp->supports_gmii) 5303 return 0; 5304 5305 switch (tp->mac_version) { 5306 /* RTL8169 */ 5307 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5308 return JUMBO_7K; 5309 /* RTL8168b */ 5310 case RTL_GIGA_MAC_VER_17: 5311 return JUMBO_4K; 5312 /* RTL8168c */ 5313 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5314 return JUMBO_6K; 5315 /* RTL8125/8126 */ 5316 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 5317 return JUMBO_16K; 5318 default: 5319 return JUMBO_9K; 5320 } 5321 } 5322 5323 static void rtl_init_mac_address(struct rtl8169_private *tp) 5324 { 5325 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5326 struct net_device *dev = tp->dev; 5327 int rc; 5328 5329 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5330 if (!rc) 5331 goto done; 5332 5333 rtl_read_mac_address(tp, mac_addr); 5334 if (is_valid_ether_addr(mac_addr)) 5335 goto done; 5336 5337 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5338 if (is_valid_ether_addr(mac_addr)) 5339 goto done; 5340 5341 eth_random_addr(mac_addr); 5342 dev->addr_assign_type = NET_ADDR_RANDOM; 5343 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5344 done: 5345 eth_hw_addr_set(dev, mac_addr); 5346 rtl_rar_set(tp, mac_addr); 5347 } 5348 5349 /* register is set if system vendor successfully tested ASPM 1.2 */ 5350 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5351 { 5352 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5353 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5354 return true; 5355 5356 return false; 5357 } 5358 5359 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5360 { 5361 const struct rtl_chip_info *chip; 5362 struct rtl8169_private *tp; 5363 int jumbo_max, region, rc; 5364 struct net_device *dev; 5365 u32 txconfig; 5366 u16 xid; 5367 5368 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5369 if (!dev) 5370 return -ENOMEM; 5371 5372 SET_NETDEV_DEV(dev, &pdev->dev); 5373 dev->netdev_ops = &rtl_netdev_ops; 5374 tp = netdev_priv(dev); 5375 tp->dev = dev; 5376 tp->pci_dev = pdev; 5377 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5378 tp->ocp_base = OCP_STD_PHY_BASE; 5379 5380 raw_spin_lock_init(&tp->mac_ocp_lock); 5381 mutex_init(&tp->led_lock); 5382 5383 /* Get the *optional* external "ether_clk" used on some boards */ 5384 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5385 if (IS_ERR(tp->clk)) 5386 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5387 5388 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5389 rc = pcim_enable_device(pdev); 5390 if (rc < 0) 5391 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5392 5393 if (pcim_set_mwi(pdev) < 0) 5394 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5395 5396 /* use first MMIO region */ 5397 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5398 if (region < 0) 5399 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5400 5401 tp->mmio_addr = pcim_iomap_region(pdev, region, KBUILD_MODNAME); 5402 if (IS_ERR(tp->mmio_addr)) 5403 return dev_err_probe(&pdev->dev, PTR_ERR(tp->mmio_addr), 5404 "cannot remap MMIO, aborting\n"); 5405 5406 txconfig = RTL_R32(tp, TxConfig); 5407 if (txconfig == ~0U) 5408 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5409 5410 xid = (txconfig >> 20) & 0xfcf; 5411 5412 /* Identify chip attached to board */ 5413 chip = rtl8169_get_chip_version(xid, tp->supports_gmii); 5414 if (chip->mac_version == RTL_GIGA_MAC_NONE) 5415 return dev_err_probe(&pdev->dev, -ENODEV, 5416 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5417 xid); 5418 tp->mac_version = chip->mac_version; 5419 tp->fw_name = chip->fw_name; 5420 5421 /* Disable ASPM L1 as that cause random device stop working 5422 * problems as well as full system hangs for some PCIe devices users. 5423 */ 5424 if (rtl_aspm_is_safe(tp)) 5425 rc = 0; 5426 else 5427 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5428 tp->aspm_manageable = !rc; 5429 5430 tp->dash_type = rtl_get_dash_type(tp); 5431 tp->dash_enabled = rtl_dash_is_enabled(tp); 5432 5433 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5434 5435 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5436 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5437 dev->features |= NETIF_F_HIGHDMA; 5438 5439 rtl_init_rxcfg(tp); 5440 5441 rtl8169_irq_mask_and_ack(tp); 5442 5443 rtl_hw_initialize(tp); 5444 5445 rtl_hw_reset(tp); 5446 5447 rc = rtl_alloc_irq(tp); 5448 if (rc < 0) 5449 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5450 5451 tp->irq = pci_irq_vector(pdev, 0); 5452 5453 INIT_WORK(&tp->wk.work, rtl_task); 5454 disable_work(&tp->wk.work); 5455 5456 rtl_init_mac_address(tp); 5457 5458 dev->ethtool_ops = &rtl8169_ethtool_ops; 5459 5460 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5461 5462 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5463 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5464 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5465 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5466 5467 /* 5468 * Pretend we are using VLANs; This bypasses a nasty bug where 5469 * Interrupts stop flowing on high load on 8110SCd controllers. 5470 */ 5471 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5472 /* Disallow toggling */ 5473 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5474 5475 if (rtl_chip_supports_csum_v2(tp)) 5476 dev->hw_features |= NETIF_F_IPV6_CSUM; 5477 5478 dev->features |= dev->hw_features; 5479 5480 if (rtl_chip_supports_csum_v2(tp)) { 5481 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5482 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5483 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5484 } else { 5485 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5486 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5487 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5488 } 5489 5490 /* There has been a number of reports that using SG/TSO results in 5491 * tx timeouts. However for a lot of people SG/TSO works fine. 5492 * It's not fully clear which chip versions are affected. Vendor 5493 * drivers enable SG/TSO for certain chip versions per default, 5494 * let's mimic this here. On other chip versions users can 5495 * use ethtool to enable SG/TSO, use at own risk! 5496 */ 5497 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5498 tp->mac_version != RTL_GIGA_MAC_VER_61) 5499 dev->features |= dev->hw_features; 5500 5501 dev->hw_features |= NETIF_F_RXALL; 5502 dev->hw_features |= NETIF_F_RXFCS; 5503 5504 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5505 5506 netdev_sw_irq_coalesce_default_on(dev); 5507 5508 /* configure chip for default features */ 5509 rtl8169_set_features(dev, dev->features); 5510 5511 if (!tp->dash_enabled) { 5512 rtl_set_d3_pll_down(tp, true); 5513 } else { 5514 rtl_set_d3_pll_down(tp, false); 5515 dev->ethtool->wol_enabled = 1; 5516 } 5517 5518 jumbo_max = rtl_jumbo_max(tp); 5519 if (jumbo_max) 5520 dev->max_mtu = jumbo_max; 5521 5522 rtl_set_irq_mask(tp); 5523 5524 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5525 &tp->counters_phys_addr, 5526 GFP_KERNEL); 5527 if (!tp->counters) 5528 return -ENOMEM; 5529 5530 pci_set_drvdata(pdev, tp); 5531 5532 rc = r8169_mdio_register(tp); 5533 if (rc) 5534 return rc; 5535 5536 rc = register_netdev(dev); 5537 if (rc) 5538 return rc; 5539 5540 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5541 if (rtl_is_8125(tp)) 5542 tp->leds = rtl8125_init_leds(dev); 5543 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5544 tp->leds = rtl8168_init_leds(dev); 5545 } 5546 5547 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5548 chip->name, dev->dev_addr, xid, tp->irq); 5549 5550 if (jumbo_max) 5551 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5552 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5553 "ok" : "ko"); 5554 5555 if (tp->dash_type != RTL_DASH_NONE) { 5556 netdev_info(dev, "DASH %s\n", 5557 tp->dash_enabled ? "enabled" : "disabled"); 5558 rtl8168_driver_start(tp); 5559 } 5560 5561 if (pci_dev_run_wake(pdev)) 5562 pm_runtime_put_sync(&pdev->dev); 5563 5564 return 0; 5565 } 5566 5567 static struct pci_driver rtl8169_pci_driver = { 5568 .name = KBUILD_MODNAME, 5569 .id_table = rtl8169_pci_tbl, 5570 .probe = rtl_init_one, 5571 .remove = rtl_remove_one, 5572 .shutdown = rtl_shutdown, 5573 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5574 }; 5575 5576 module_pci_driver(rtl8169_pci_driver); 5577