1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/hwmon.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/in.h> 23 #include <linux/io.h> 24 #include <linux/ip.h> 25 #include <linux/tcp.h> 26 #include <linux/interrupt.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/bitfield.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <linux/unaligned.h> 33 #include <net/ip6_checksum.h> 34 #include <net/netdev_queues.h> 35 36 #include "r8169.h" 37 #include "r8169_firmware.h" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 59 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" 60 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 61 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 62 63 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 65 66 #define R8169_REGS_SIZE 256 67 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 68 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 69 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 70 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 71 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 72 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 73 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 74 75 #define OCP_STD_PHY_BASE 0xa400 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 92 static const struct { 93 const char *name; 94 const char *fw_name; 95 } rtl_chip_infos[] = { 96 /* PCI devices. */ 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 102 /* PCI-E devices. */ 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 109 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 111 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 117 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 118 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 119 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 122 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 124 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 125 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 126 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 127 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 128 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 129 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 130 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 131 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 132 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 133 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 134 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 135 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 136 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 137 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 138 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 139 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 140 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 141 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 142 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 143 [RTL_GIGA_MAC_VER_64] = {"RTL8125D", FIRMWARE_8125D_1}, 144 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 145 [RTL_GIGA_MAC_VER_66] = {"RTL8126A", FIRMWARE_8126A_3}, 146 }; 147 148 static const struct pci_device_id rtl8169_pci_tbl[] = { 149 { PCI_VDEVICE(REALTEK, 0x2502) }, 150 { PCI_VDEVICE(REALTEK, 0x2600) }, 151 { PCI_VDEVICE(REALTEK, 0x8129) }, 152 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 153 { PCI_VDEVICE(REALTEK, 0x8161) }, 154 { PCI_VDEVICE(REALTEK, 0x8162) }, 155 { PCI_VDEVICE(REALTEK, 0x8167) }, 156 { PCI_VDEVICE(REALTEK, 0x8168) }, 157 { PCI_VDEVICE(NCUBE, 0x8168) }, 158 { PCI_VDEVICE(REALTEK, 0x8169) }, 159 { PCI_VENDOR_ID_DLINK, 0x4300, 160 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 161 { PCI_VDEVICE(DLINK, 0x4300) }, 162 { PCI_VDEVICE(DLINK, 0x4302) }, 163 { PCI_VDEVICE(AT, 0xc107) }, 164 { PCI_VDEVICE(USR, 0x0116) }, 165 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 166 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 167 { PCI_VDEVICE(REALTEK, 0x8125) }, 168 { PCI_VDEVICE(REALTEK, 0x8126) }, 169 { PCI_VDEVICE(REALTEK, 0x3000) }, 170 {} 171 }; 172 173 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 174 175 enum rtl_registers { 176 MAC0 = 0, /* Ethernet hardware address. */ 177 MAC4 = 4, 178 MAR0 = 8, /* Multicast filter. */ 179 CounterAddrLow = 0x10, 180 CounterAddrHigh = 0x14, 181 TxDescStartAddrLow = 0x20, 182 TxDescStartAddrHigh = 0x24, 183 TxHDescStartAddrLow = 0x28, 184 TxHDescStartAddrHigh = 0x2c, 185 FLASH = 0x30, 186 ERSR = 0x36, 187 ChipCmd = 0x37, 188 TxPoll = 0x38, 189 IntrMask = 0x3c, 190 IntrStatus = 0x3e, 191 192 TxConfig = 0x40, 193 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 194 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 195 196 RxConfig = 0x44, 197 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 198 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 199 #define RXCFG_FIFO_SHIFT 13 200 /* No threshold before first PCI xfer */ 201 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 202 #define RX_EARLY_OFF (1 << 11) 203 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 204 #define RXCFG_DMA_SHIFT 8 205 /* Unlimited maximum PCI burst. */ 206 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 207 208 Cfg9346 = 0x50, 209 Config0 = 0x51, 210 Config1 = 0x52, 211 Config2 = 0x53, 212 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 213 214 Config3 = 0x54, 215 Config4 = 0x55, 216 Config5 = 0x56, 217 PHYAR = 0x60, 218 PHYstatus = 0x6c, 219 RxMaxSize = 0xda, 220 CPlusCmd = 0xe0, 221 IntrMitigate = 0xe2, 222 223 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 224 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 225 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 226 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 227 228 #define RTL_COALESCE_T_MAX 0x0fU 229 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 230 231 RxDescAddrLow = 0xe4, 232 RxDescAddrHigh = 0xe8, 233 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 234 235 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 236 237 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 238 239 #define TxPacketMax (8064 >> 7) 240 #define EarlySize 0x27 241 242 FuncEvent = 0xf0, 243 FuncEventMask = 0xf4, 244 FuncPresetState = 0xf8, 245 IBCR0 = 0xf8, 246 IBCR2 = 0xf9, 247 IBIMR0 = 0xfa, 248 IBISR0 = 0xfb, 249 FuncForceEvent = 0xfc, 250 }; 251 252 enum rtl8168_8101_registers { 253 CSIDR = 0x64, 254 CSIAR = 0x68, 255 #define CSIAR_FLAG 0x80000000 256 #define CSIAR_WRITE_CMD 0x80000000 257 #define CSIAR_BYTE_ENABLE 0x0000f000 258 #define CSIAR_ADDR_MASK 0x00000fff 259 PMCH = 0x6f, 260 #define D3COLD_NO_PLL_DOWN BIT(7) 261 #define D3HOT_NO_PLL_DOWN BIT(6) 262 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 263 EPHYAR = 0x80, 264 #define EPHYAR_FLAG 0x80000000 265 #define EPHYAR_WRITE_CMD 0x80000000 266 #define EPHYAR_REG_MASK 0x1f 267 #define EPHYAR_REG_SHIFT 16 268 #define EPHYAR_DATA_MASK 0xffff 269 DLLPR = 0xd0, 270 #define PFM_EN (1 << 6) 271 #define TX_10M_PS_EN (1 << 7) 272 DBG_REG = 0xd1, 273 #define FIX_NAK_1 (1 << 4) 274 #define FIX_NAK_2 (1 << 3) 275 TWSI = 0xd2, 276 MCU = 0xd3, 277 #define NOW_IS_OOB (1 << 7) 278 #define TX_EMPTY (1 << 5) 279 #define RX_EMPTY (1 << 4) 280 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 281 #define EN_NDP (1 << 3) 282 #define EN_OOB_RESET (1 << 2) 283 #define LINK_LIST_RDY (1 << 1) 284 EFUSEAR = 0xdc, 285 #define EFUSEAR_FLAG 0x80000000 286 #define EFUSEAR_WRITE_CMD 0x80000000 287 #define EFUSEAR_READ_CMD 0x00000000 288 #define EFUSEAR_REG_MASK 0x03ff 289 #define EFUSEAR_REG_SHIFT 8 290 #define EFUSEAR_DATA_MASK 0xff 291 MISC_1 = 0xf2, 292 #define PFM_D3COLD_EN (1 << 6) 293 }; 294 295 enum rtl8168_registers { 296 LED_CTRL = 0x18, 297 LED_FREQ = 0x1a, 298 EEE_LED = 0x1b, 299 ERIDR = 0x70, 300 ERIAR = 0x74, 301 #define ERIAR_FLAG 0x80000000 302 #define ERIAR_WRITE_CMD 0x80000000 303 #define ERIAR_READ_CMD 0x00000000 304 #define ERIAR_ADDR_BYTE_ALIGN 4 305 #define ERIAR_TYPE_SHIFT 16 306 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 310 #define ERIAR_MASK_SHIFT 12 311 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 315 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 316 EPHY_RXER_NUM = 0x7c, 317 OCPDR = 0xb0, /* OCP GPHY access */ 318 #define OCPDR_WRITE_CMD 0x80000000 319 #define OCPDR_READ_CMD 0x00000000 320 #define OCPDR_REG_MASK 0x7f 321 #define OCPDR_GPHY_REG_SHIFT 16 322 #define OCPDR_DATA_MASK 0xffff 323 OCPAR = 0xb4, 324 #define OCPAR_FLAG 0x80000000 325 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 326 #define OCPAR_GPHY_READ_CMD 0x0000f060 327 GPHY_OCP = 0xb8, 328 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 329 MISC = 0xf0, /* 8168e only. */ 330 #define TXPLA_RST (1 << 29) 331 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 332 #define PWM_EN (1 << 22) 333 #define RXDV_GATED_EN (1 << 19) 334 #define EARLY_TALLY_EN (1 << 16) 335 }; 336 337 enum rtl8125_registers { 338 LEDSEL0 = 0x18, 339 INT_CFG0_8125 = 0x34, 340 #define INT_CFG0_ENABLE_8125 BIT(0) 341 #define INT_CFG0_CLKREQEN BIT(3) 342 IntrMask_8125 = 0x38, 343 IntrStatus_8125 = 0x3c, 344 INT_CFG1_8125 = 0x7a, 345 LEDSEL2 = 0x84, 346 LEDSEL1 = 0x86, 347 TxPoll_8125 = 0x90, 348 LEDSEL3 = 0x96, 349 MAC0_BKP = 0x19e0, 350 RSS_CTRL_8125 = 0x4500, 351 Q_NUM_CTRL_8125 = 0x4800, 352 EEE_TXIDLE_TIMER_8125 = 0x6048, 353 }; 354 355 #define LEDSEL_MASK_8125 0x23f 356 357 #define RX_VLAN_INNER_8125 BIT(22) 358 #define RX_VLAN_OUTER_8125 BIT(23) 359 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 360 361 #define RX_FETCH_DFLT_8125 (8 << 27) 362 363 enum rtl_register_content { 364 /* InterruptStatusBits */ 365 SYSErr = 0x8000, 366 PCSTimeout = 0x4000, 367 SWInt = 0x0100, 368 TxDescUnavail = 0x0080, 369 RxFIFOOver = 0x0040, 370 LinkChg = 0x0020, 371 RxOverflow = 0x0010, 372 TxErr = 0x0008, 373 TxOK = 0x0004, 374 RxErr = 0x0002, 375 RxOK = 0x0001, 376 377 /* RxStatusDesc */ 378 RxRWT = (1 << 22), 379 RxRES = (1 << 21), 380 RxRUNT = (1 << 20), 381 RxCRC = (1 << 19), 382 383 /* ChipCmdBits */ 384 StopReq = 0x80, 385 CmdReset = 0x10, 386 CmdRxEnb = 0x08, 387 CmdTxEnb = 0x04, 388 RxBufEmpty = 0x01, 389 390 /* TXPoll register p.5 */ 391 HPQ = 0x80, /* Poll cmd on the high prio queue */ 392 NPQ = 0x40, /* Poll cmd on the low prio queue */ 393 FSWInt = 0x01, /* Forced software interrupt */ 394 395 /* Cfg9346Bits */ 396 Cfg9346_Lock = 0x00, 397 Cfg9346_Unlock = 0xc0, 398 399 /* rx_mode_bits */ 400 AcceptErr = 0x20, 401 AcceptRunt = 0x10, 402 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 403 AcceptBroadcast = 0x08, 404 AcceptMulticast = 0x04, 405 AcceptMyPhys = 0x02, 406 AcceptAllPhys = 0x01, 407 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 408 #define RX_CONFIG_ACCEPT_MASK 0x3f 409 410 /* TxConfigBits */ 411 TxInterFrameGapShift = 24, 412 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 413 414 /* Config1 register p.24 */ 415 LEDS1 = (1 << 7), 416 LEDS0 = (1 << 6), 417 Speed_down = (1 << 4), 418 MEMMAP = (1 << 3), 419 IOMAP = (1 << 2), 420 VPD = (1 << 1), 421 PMEnable = (1 << 0), /* Power Management Enable */ 422 423 /* Config2 register p. 25 */ 424 ClkReqEn = (1 << 7), /* Clock Request Enable */ 425 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 426 PCI_Clock_66MHz = 0x01, 427 PCI_Clock_33MHz = 0x00, 428 429 /* Config3 register p.25 */ 430 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 431 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 432 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 433 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 434 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 435 436 /* Config4 register */ 437 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 438 439 /* Config5 register p.27 */ 440 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 441 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 442 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 443 Spi_en = (1 << 3), 444 LanWake = (1 << 1), /* LanWake enable/disable */ 445 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 446 ASPM_en = (1 << 0), /* ASPM enable */ 447 448 /* CPlusCmd p.31 */ 449 EnableBist = (1 << 15), // 8168 8101 450 Mac_dbgo_oe = (1 << 14), // 8168 8101 451 EnAnaPLL = (1 << 14), // 8169 452 Normal_mode = (1 << 13), // unused 453 Force_half_dup = (1 << 12), // 8168 8101 454 Force_rxflow_en = (1 << 11), // 8168 8101 455 Force_txflow_en = (1 << 10), // 8168 8101 456 Cxpl_dbg_sel = (1 << 9), // 8168 8101 457 ASF = (1 << 8), // 8168 8101 458 PktCntrDisable = (1 << 7), // 8168 8101 459 Mac_dbgo_sel = 0x001c, // 8168 460 RxVlan = (1 << 6), 461 RxChkSum = (1 << 5), 462 PCIDAC = (1 << 4), 463 PCIMulRW = (1 << 3), 464 #define INTT_MASK GENMASK(1, 0) 465 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 466 467 /* rtl8169_PHYstatus */ 468 TBI_Enable = 0x80, 469 TxFlowCtrl = 0x40, 470 RxFlowCtrl = 0x20, 471 _1000bpsF = 0x10, 472 _100bps = 0x08, 473 _10bps = 0x04, 474 LinkStatus = 0x02, 475 FullDup = 0x01, 476 477 /* ResetCounterCommand */ 478 CounterReset = 0x1, 479 480 /* DumpCounterCommand */ 481 CounterDump = 0x8, 482 483 /* magic enable v2 */ 484 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 485 }; 486 487 enum rtl_desc_bit { 488 /* First doubleword. */ 489 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 490 RingEnd = (1 << 30), /* End of descriptor ring */ 491 FirstFrag = (1 << 29), /* First segment of a packet */ 492 LastFrag = (1 << 28), /* Final segment of a packet */ 493 }; 494 495 /* Generic case. */ 496 enum rtl_tx_desc_bit { 497 /* First doubleword. */ 498 TD_LSO = (1 << 27), /* Large Send Offload */ 499 #define TD_MSS_MAX 0x07ffu /* MSS value */ 500 501 /* Second doubleword. */ 502 TxVlanTag = (1 << 17), /* Add VLAN tag */ 503 }; 504 505 /* 8169, 8168b and 810x except 8102e. */ 506 enum rtl_tx_desc_bit_0 { 507 /* First doubleword. */ 508 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 509 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 510 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 511 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 512 }; 513 514 /* 8102e, 8168c and beyond. */ 515 enum rtl_tx_desc_bit_1 { 516 /* First doubleword. */ 517 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 518 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 519 #define GTTCPHO_SHIFT 18 520 #define GTTCPHO_MAX 0x7f 521 522 /* Second doubleword. */ 523 #define TCPHO_SHIFT 18 524 #define TCPHO_MAX 0x3ff 525 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 526 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 527 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 528 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 529 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 530 }; 531 532 enum rtl_rx_desc_bit { 533 /* Rx private */ 534 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 535 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 536 537 #define RxProtoUDP (PID1) 538 #define RxProtoTCP (PID0) 539 #define RxProtoIP (PID1 | PID0) 540 #define RxProtoMask RxProtoIP 541 542 IPFail = (1 << 16), /* IP checksum failed */ 543 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 544 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 545 546 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 547 548 RxVlanTag = (1 << 16), /* VLAN tag available */ 549 }; 550 551 #define RTL_GSO_MAX_SIZE_V1 32000 552 #define RTL_GSO_MAX_SEGS_V1 24 553 #define RTL_GSO_MAX_SIZE_V2 64000 554 #define RTL_GSO_MAX_SEGS_V2 64 555 556 struct TxDesc { 557 __le32 opts1; 558 __le32 opts2; 559 __le64 addr; 560 }; 561 562 struct RxDesc { 563 __le32 opts1; 564 __le32 opts2; 565 __le64 addr; 566 }; 567 568 struct ring_info { 569 struct sk_buff *skb; 570 u32 len; 571 }; 572 573 struct rtl8169_counters { 574 __le64 tx_packets; 575 __le64 rx_packets; 576 __le64 tx_errors; 577 __le32 rx_errors; 578 __le16 rx_missed; 579 __le16 align_errors; 580 __le32 tx_one_collision; 581 __le32 tx_multi_collision; 582 __le64 rx_unicast; 583 __le64 rx_broadcast; 584 __le32 rx_multicast; 585 __le16 tx_aborted; 586 __le16 tx_underrun; 587 /* new since RTL8125 */ 588 __le64 tx_octets; 589 __le64 rx_octets; 590 __le64 rx_multicast64; 591 __le64 tx_unicast64; 592 __le64 tx_broadcast64; 593 __le64 tx_multicast64; 594 __le32 tx_pause_on; 595 __le32 tx_pause_off; 596 __le32 tx_pause_all; 597 __le32 tx_deferred; 598 __le32 tx_late_collision; 599 __le32 tx_all_collision; 600 __le32 tx_aborted32; 601 __le32 align_errors32; 602 __le32 rx_frame_too_long; 603 __le32 rx_runt; 604 __le32 rx_pause_on; 605 __le32 rx_pause_off; 606 __le32 rx_pause_all; 607 __le32 rx_unknown_opcode; 608 __le32 rx_mac_error; 609 __le32 tx_underrun32; 610 __le32 rx_mac_missed; 611 __le32 rx_tcam_dropped; 612 __le32 tdu; 613 __le32 rdu; 614 }; 615 616 struct rtl8169_tc_offsets { 617 bool inited; 618 __le64 tx_errors; 619 __le32 tx_multi_collision; 620 __le16 tx_aborted; 621 __le16 rx_missed; 622 }; 623 624 enum rtl_flag { 625 RTL_FLAG_TASK_RESET_PENDING, 626 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 627 RTL_FLAG_TASK_TX_TIMEOUT, 628 RTL_FLAG_MAX 629 }; 630 631 enum rtl_dash_type { 632 RTL_DASH_NONE, 633 RTL_DASH_DP, 634 RTL_DASH_EP, 635 }; 636 637 struct rtl8169_private { 638 void __iomem *mmio_addr; /* memory map physical address */ 639 struct pci_dev *pci_dev; 640 struct net_device *dev; 641 struct phy_device *phydev; 642 struct napi_struct napi; 643 enum mac_version mac_version; 644 enum rtl_dash_type dash_type; 645 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 646 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 647 u32 dirty_tx; 648 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 649 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 650 dma_addr_t TxPhyAddr; 651 dma_addr_t RxPhyAddr; 652 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 653 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 654 u16 cp_cmd; 655 u16 tx_lpi_timer; 656 u32 irq_mask; 657 int irq; 658 struct clk *clk; 659 660 struct { 661 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 662 struct work_struct work; 663 } wk; 664 665 raw_spinlock_t mac_ocp_lock; 666 struct mutex led_lock; /* serialize LED ctrl RMW access */ 667 668 unsigned supports_gmii:1; 669 unsigned aspm_manageable:1; 670 unsigned dash_enabled:1; 671 dma_addr_t counters_phys_addr; 672 struct rtl8169_counters *counters; 673 struct rtl8169_tc_offsets tc_offset; 674 u32 saved_wolopts; 675 676 const char *fw_name; 677 struct rtl_fw *rtl_fw; 678 679 struct r8169_led_classdev *leds; 680 681 u32 ocp_base; 682 }; 683 684 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 685 686 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 687 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 688 MODULE_SOFTDEP("pre: realtek"); 689 MODULE_LICENSE("GPL"); 690 MODULE_FIRMWARE(FIRMWARE_8168D_1); 691 MODULE_FIRMWARE(FIRMWARE_8168D_2); 692 MODULE_FIRMWARE(FIRMWARE_8168E_1); 693 MODULE_FIRMWARE(FIRMWARE_8168E_2); 694 MODULE_FIRMWARE(FIRMWARE_8168E_3); 695 MODULE_FIRMWARE(FIRMWARE_8105E_1); 696 MODULE_FIRMWARE(FIRMWARE_8168F_1); 697 MODULE_FIRMWARE(FIRMWARE_8168F_2); 698 MODULE_FIRMWARE(FIRMWARE_8402_1); 699 MODULE_FIRMWARE(FIRMWARE_8411_1); 700 MODULE_FIRMWARE(FIRMWARE_8411_2); 701 MODULE_FIRMWARE(FIRMWARE_8106E_1); 702 MODULE_FIRMWARE(FIRMWARE_8106E_2); 703 MODULE_FIRMWARE(FIRMWARE_8168G_2); 704 MODULE_FIRMWARE(FIRMWARE_8168G_3); 705 MODULE_FIRMWARE(FIRMWARE_8168H_2); 706 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 707 MODULE_FIRMWARE(FIRMWARE_8107E_2); 708 MODULE_FIRMWARE(FIRMWARE_8125A_3); 709 MODULE_FIRMWARE(FIRMWARE_8125B_2); 710 MODULE_FIRMWARE(FIRMWARE_8125D_1); 711 MODULE_FIRMWARE(FIRMWARE_8126A_2); 712 MODULE_FIRMWARE(FIRMWARE_8126A_3); 713 714 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 715 { 716 return &tp->pci_dev->dev; 717 } 718 719 static void rtl_lock_config_regs(struct rtl8169_private *tp) 720 { 721 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 722 } 723 724 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 725 { 726 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 727 } 728 729 static void rtl_pci_commit(struct rtl8169_private *tp) 730 { 731 /* Read an arbitrary register to commit a preceding PCI write */ 732 RTL_R8(tp, ChipCmd); 733 } 734 735 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 736 { 737 u8 val; 738 739 val = RTL_R8(tp, Config2); 740 RTL_W8(tp, Config2, (val & ~clear) | set); 741 } 742 743 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 744 { 745 u8 val; 746 747 val = RTL_R8(tp, Config5); 748 RTL_W8(tp, Config5, (val & ~clear) | set); 749 } 750 751 static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg, 752 u8 bits, bool cond) 753 { 754 u8 val, old_val; 755 756 old_val = RTL_R8(tp, reg); 757 if (cond) 758 val = old_val | bits; 759 else 760 val = old_val & ~bits; 761 if (val != old_val) 762 RTL_W8(tp, reg, val); 763 } 764 765 static bool rtl_is_8125(struct rtl8169_private *tp) 766 { 767 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 768 } 769 770 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 771 { 772 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 773 tp->mac_version != RTL_GIGA_MAC_VER_39 && 774 tp->mac_version <= RTL_GIGA_MAC_VER_53; 775 } 776 777 static bool rtl_supports_eee(struct rtl8169_private *tp) 778 { 779 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 780 tp->mac_version != RTL_GIGA_MAC_VER_37 && 781 tp->mac_version != RTL_GIGA_MAC_VER_39; 782 } 783 784 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 785 { 786 int i; 787 788 for (i = 0; i < ETH_ALEN; i++) 789 mac[i] = RTL_R8(tp, reg + i); 790 } 791 792 struct rtl_cond { 793 bool (*check)(struct rtl8169_private *); 794 const char *msg; 795 }; 796 797 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 798 unsigned long usecs, int n, bool high) 799 { 800 int i; 801 802 for (i = 0; i < n; i++) { 803 if (c->check(tp) == high) 804 return true; 805 fsleep(usecs); 806 } 807 808 if (net_ratelimit()) 809 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 810 c->msg, !high, n, usecs); 811 return false; 812 } 813 814 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 815 const struct rtl_cond *c, 816 unsigned long d, int n) 817 { 818 return rtl_loop_wait(tp, c, d, n, true); 819 } 820 821 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 822 const struct rtl_cond *c, 823 unsigned long d, int n) 824 { 825 return rtl_loop_wait(tp, c, d, n, false); 826 } 827 828 #define DECLARE_RTL_COND(name) \ 829 static bool name ## _check(struct rtl8169_private *); \ 830 \ 831 static const struct rtl_cond name = { \ 832 .check = name ## _check, \ 833 .msg = #name \ 834 }; \ 835 \ 836 static bool name ## _check(struct rtl8169_private *tp) 837 838 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 839 { 840 struct device *dev = tp_to_dev(tp); 841 int ret; 842 843 ret = pm_runtime_resume_and_get(dev); 844 if (ret < 0) 845 return ret; 846 847 mutex_lock(&tp->led_lock); 848 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 849 mutex_unlock(&tp->led_lock); 850 851 pm_runtime_put_sync(dev); 852 853 return 0; 854 } 855 856 int rtl8168_get_led_mode(struct rtl8169_private *tp) 857 { 858 struct device *dev = tp_to_dev(tp); 859 int ret; 860 861 ret = pm_runtime_resume_and_get(dev); 862 if (ret < 0) 863 return ret; 864 865 ret = RTL_R16(tp, LED_CTRL); 866 867 pm_runtime_put_sync(dev); 868 869 return ret; 870 } 871 872 static int rtl8125_get_led_reg(int index) 873 { 874 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 875 876 return led_regs[index]; 877 } 878 879 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 880 { 881 int reg = rtl8125_get_led_reg(index); 882 struct device *dev = tp_to_dev(tp); 883 int ret; 884 u16 val; 885 886 ret = pm_runtime_resume_and_get(dev); 887 if (ret < 0) 888 return ret; 889 890 mutex_lock(&tp->led_lock); 891 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 892 RTL_W16(tp, reg, val | mode); 893 mutex_unlock(&tp->led_lock); 894 895 pm_runtime_put_sync(dev); 896 897 return 0; 898 } 899 900 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 901 { 902 int reg = rtl8125_get_led_reg(index); 903 struct device *dev = tp_to_dev(tp); 904 int ret; 905 906 ret = pm_runtime_resume_and_get(dev); 907 if (ret < 0) 908 return ret; 909 910 ret = RTL_R16(tp, reg); 911 912 pm_runtime_put_sync(dev); 913 914 return ret; 915 } 916 917 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 918 char *buf, int buf_len) 919 { 920 struct pci_dev *pdev = tp->pci_dev; 921 char pdom[8], pfun[8]; 922 int domain; 923 924 domain = pci_domain_nr(pdev->bus); 925 if (domain) 926 snprintf(pdom, sizeof(pdom), "P%d", domain); 927 else 928 pdom[0] = '\0'; 929 930 if (pdev->multifunction) 931 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 932 else 933 pfun[0] = '\0'; 934 935 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 936 PCI_SLOT(pdev->devfn), pfun, idx); 937 } 938 939 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 940 { 941 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 942 if (type == ERIAR_OOB && 943 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 944 tp->mac_version == RTL_GIGA_MAC_VER_53)) 945 *cmd |= 0xf70 << 18; 946 } 947 948 DECLARE_RTL_COND(rtl_eriar_cond) 949 { 950 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 951 } 952 953 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 954 u32 val, int type) 955 { 956 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 957 958 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 959 return; 960 961 RTL_W32(tp, ERIDR, val); 962 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 963 RTL_W32(tp, ERIAR, cmd); 964 965 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 966 } 967 968 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 969 u32 val) 970 { 971 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 972 } 973 974 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 975 { 976 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 977 978 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 979 RTL_W32(tp, ERIAR, cmd); 980 981 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 982 RTL_R32(tp, ERIDR) : ~0; 983 } 984 985 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 986 { 987 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 988 } 989 990 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 991 { 992 u32 val = rtl_eri_read(tp, addr); 993 994 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 995 } 996 997 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 998 { 999 rtl_w0w1_eri(tp, addr, p, 0); 1000 } 1001 1002 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1003 { 1004 rtl_w0w1_eri(tp, addr, 0, m); 1005 } 1006 1007 static bool rtl_ocp_reg_failure(u32 reg) 1008 { 1009 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1010 } 1011 1012 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1013 { 1014 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1015 } 1016 1017 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1018 { 1019 if (rtl_ocp_reg_failure(reg)) 1020 return; 1021 1022 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1023 1024 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1025 } 1026 1027 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1028 { 1029 if (rtl_ocp_reg_failure(reg)) 1030 return 0; 1031 1032 RTL_W32(tp, GPHY_OCP, reg << 15); 1033 1034 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1035 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1036 } 1037 1038 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1039 { 1040 if (rtl_ocp_reg_failure(reg)) 1041 return; 1042 1043 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1044 } 1045 1046 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1047 { 1048 unsigned long flags; 1049 1050 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1051 __r8168_mac_ocp_write(tp, reg, data); 1052 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1053 } 1054 1055 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1056 { 1057 if (rtl_ocp_reg_failure(reg)) 1058 return 0; 1059 1060 RTL_W32(tp, OCPDR, reg << 15); 1061 1062 return RTL_R32(tp, OCPDR); 1063 } 1064 1065 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1066 { 1067 unsigned long flags; 1068 u16 val; 1069 1070 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1071 val = __r8168_mac_ocp_read(tp, reg); 1072 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1073 1074 return val; 1075 } 1076 1077 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1078 u16 set) 1079 { 1080 unsigned long flags; 1081 u16 data; 1082 1083 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1084 data = __r8168_mac_ocp_read(tp, reg); 1085 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1086 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1087 } 1088 1089 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1090 * PHY MCU interrupts before PHY power-down. 1091 */ 1092 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1093 { 1094 switch (tp->mac_version) { 1095 case RTL_GIGA_MAC_VER_40: 1096 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1097 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1098 else 1099 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1100 break; 1101 default: 1102 break; 1103 } 1104 }; 1105 1106 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1107 { 1108 if (reg == 0x1f) { 1109 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1110 return; 1111 } 1112 1113 if (tp->ocp_base != OCP_STD_PHY_BASE) 1114 reg -= 0x10; 1115 1116 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1117 rtl8168g_phy_suspend_quirk(tp, value); 1118 1119 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1120 } 1121 1122 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1123 { 1124 if (reg == 0x1f) 1125 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1126 1127 if (tp->ocp_base != OCP_STD_PHY_BASE) 1128 reg -= 0x10; 1129 1130 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1131 } 1132 1133 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1134 { 1135 if (reg == 0x1f) { 1136 tp->ocp_base = value << 4; 1137 return; 1138 } 1139 1140 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1141 } 1142 1143 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1144 { 1145 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1146 } 1147 1148 DECLARE_RTL_COND(rtl_phyar_cond) 1149 { 1150 return RTL_R32(tp, PHYAR) & 0x80000000; 1151 } 1152 1153 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1154 { 1155 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1156 1157 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1158 /* 1159 * According to hardware specs a 20us delay is required after write 1160 * complete indication, but before sending next command. 1161 */ 1162 udelay(20); 1163 } 1164 1165 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1166 { 1167 int value; 1168 1169 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1170 1171 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1172 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1173 1174 /* 1175 * According to hardware specs a 20us delay is required after read 1176 * complete indication, but before sending next command. 1177 */ 1178 udelay(20); 1179 1180 return value; 1181 } 1182 1183 DECLARE_RTL_COND(rtl_ocpar_cond) 1184 { 1185 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1186 } 1187 1188 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1189 1190 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1191 { 1192 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1193 } 1194 1195 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1196 { 1197 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1198 } 1199 1200 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1201 { 1202 r8168dp_2_mdio_start(tp); 1203 1204 r8169_mdio_write(tp, reg, value); 1205 1206 r8168dp_2_mdio_stop(tp); 1207 } 1208 1209 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1210 { 1211 int value; 1212 1213 /* Work around issue with chip reporting wrong PHY ID */ 1214 if (reg == MII_PHYSID2) 1215 return 0xc912; 1216 1217 r8168dp_2_mdio_start(tp); 1218 1219 value = r8169_mdio_read(tp, reg); 1220 1221 r8168dp_2_mdio_stop(tp); 1222 1223 return value; 1224 } 1225 1226 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1227 { 1228 switch (tp->mac_version) { 1229 case RTL_GIGA_MAC_VER_28: 1230 case RTL_GIGA_MAC_VER_31: 1231 r8168dp_2_mdio_write(tp, location, val); 1232 break; 1233 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1234 r8168g_mdio_write(tp, location, val); 1235 break; 1236 default: 1237 r8169_mdio_write(tp, location, val); 1238 break; 1239 } 1240 } 1241 1242 static int rtl_readphy(struct rtl8169_private *tp, int location) 1243 { 1244 switch (tp->mac_version) { 1245 case RTL_GIGA_MAC_VER_28: 1246 case RTL_GIGA_MAC_VER_31: 1247 return r8168dp_2_mdio_read(tp, location); 1248 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1249 return r8168g_mdio_read(tp, location); 1250 default: 1251 return r8169_mdio_read(tp, location); 1252 } 1253 } 1254 1255 DECLARE_RTL_COND(rtl_ephyar_cond) 1256 { 1257 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1258 } 1259 1260 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1261 { 1262 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1263 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1264 1265 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1266 1267 udelay(10); 1268 } 1269 1270 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1271 { 1272 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1273 1274 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1275 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1276 } 1277 1278 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1279 { 1280 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1281 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1282 RTL_R32(tp, OCPDR) : ~0; 1283 } 1284 1285 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1286 { 1287 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1288 } 1289 1290 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1291 u32 data) 1292 { 1293 RTL_W32(tp, OCPDR, data); 1294 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1295 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1296 } 1297 1298 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1299 u32 data) 1300 { 1301 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1302 data, ERIAR_OOB); 1303 } 1304 1305 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1306 { 1307 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1308 1309 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1310 } 1311 1312 #define OOB_CMD_RESET 0x00 1313 #define OOB_CMD_DRIVER_START 0x05 1314 #define OOB_CMD_DRIVER_STOP 0x06 1315 1316 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1317 { 1318 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1319 } 1320 1321 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1322 { 1323 u16 reg; 1324 1325 reg = rtl8168_get_ocp_reg(tp); 1326 1327 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1328 } 1329 1330 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1331 { 1332 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1333 } 1334 1335 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1336 { 1337 return RTL_R8(tp, IBISR0) & 0x20; 1338 } 1339 1340 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1341 { 1342 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1343 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1344 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1345 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1346 } 1347 1348 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1349 { 1350 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1351 if (tp->dash_enabled) 1352 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1353 } 1354 1355 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1356 { 1357 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1358 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1359 if (tp->dash_enabled) 1360 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1361 } 1362 1363 static void rtl8168_driver_start(struct rtl8169_private *tp) 1364 { 1365 if (tp->dash_type == RTL_DASH_DP) 1366 rtl8168dp_driver_start(tp); 1367 else 1368 rtl8168ep_driver_start(tp); 1369 } 1370 1371 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1372 { 1373 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1374 if (tp->dash_enabled) 1375 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1376 } 1377 1378 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1379 { 1380 rtl8168ep_stop_cmac(tp); 1381 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1382 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1383 if (tp->dash_enabled) 1384 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1385 } 1386 1387 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1388 { 1389 if (tp->dash_type == RTL_DASH_DP) 1390 rtl8168dp_driver_stop(tp); 1391 else 1392 rtl8168ep_driver_stop(tp); 1393 } 1394 1395 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1396 { 1397 u16 reg = rtl8168_get_ocp_reg(tp); 1398 1399 return r8168dp_ocp_read(tp, reg) & BIT(15); 1400 } 1401 1402 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1403 { 1404 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1405 } 1406 1407 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1408 { 1409 switch (tp->dash_type) { 1410 case RTL_DASH_DP: 1411 return r8168dp_check_dash(tp); 1412 case RTL_DASH_EP: 1413 return r8168ep_check_dash(tp); 1414 default: 1415 return false; 1416 } 1417 } 1418 1419 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1420 { 1421 switch (tp->mac_version) { 1422 case RTL_GIGA_MAC_VER_28: 1423 case RTL_GIGA_MAC_VER_31: 1424 return RTL_DASH_DP; 1425 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1426 return RTL_DASH_EP; 1427 default: 1428 return RTL_DASH_NONE; 1429 } 1430 } 1431 1432 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1433 { 1434 if (tp->mac_version >= RTL_GIGA_MAC_VER_25 && 1435 tp->mac_version != RTL_GIGA_MAC_VER_28 && 1436 tp->mac_version != RTL_GIGA_MAC_VER_31 && 1437 tp->mac_version != RTL_GIGA_MAC_VER_38) 1438 r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, !enable); 1439 } 1440 1441 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1442 { 1443 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1444 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1445 } 1446 1447 DECLARE_RTL_COND(rtl_efusear_cond) 1448 { 1449 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1450 } 1451 1452 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1453 { 1454 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1455 1456 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1457 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1458 } 1459 1460 static u32 rtl_get_events(struct rtl8169_private *tp) 1461 { 1462 if (rtl_is_8125(tp)) 1463 return RTL_R32(tp, IntrStatus_8125); 1464 else 1465 return RTL_R16(tp, IntrStatus); 1466 } 1467 1468 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1469 { 1470 if (rtl_is_8125(tp)) 1471 RTL_W32(tp, IntrStatus_8125, bits); 1472 else 1473 RTL_W16(tp, IntrStatus, bits); 1474 } 1475 1476 static void rtl_irq_disable(struct rtl8169_private *tp) 1477 { 1478 if (rtl_is_8125(tp)) 1479 RTL_W32(tp, IntrMask_8125, 0); 1480 else 1481 RTL_W16(tp, IntrMask, 0); 1482 } 1483 1484 static void rtl_irq_enable(struct rtl8169_private *tp) 1485 { 1486 if (rtl_is_8125(tp)) 1487 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1488 else 1489 RTL_W16(tp, IntrMask, tp->irq_mask); 1490 } 1491 1492 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1493 { 1494 rtl_irq_disable(tp); 1495 rtl_ack_events(tp, 0xffffffff); 1496 rtl_pci_commit(tp); 1497 } 1498 1499 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1500 { 1501 struct phy_device *phydev = tp->phydev; 1502 1503 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1504 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1505 if (phydev->speed == SPEED_1000) { 1506 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1507 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1508 } else if (phydev->speed == SPEED_100) { 1509 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1510 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1511 } else { 1512 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1513 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1514 } 1515 rtl_reset_packet_filter(tp); 1516 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1517 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1518 if (phydev->speed == SPEED_1000) { 1519 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1520 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1521 } else { 1522 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1523 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1524 } 1525 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1526 if (phydev->speed == SPEED_10) { 1527 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1528 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1529 } else { 1530 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1531 } 1532 } 1533 } 1534 1535 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1536 1537 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1538 { 1539 struct rtl8169_private *tp = netdev_priv(dev); 1540 1541 wol->supported = WAKE_ANY; 1542 wol->wolopts = tp->saved_wolopts; 1543 } 1544 1545 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1546 { 1547 rtl_unlock_config_regs(tp); 1548 1549 if (rtl_is_8168evl_up(tp)) { 1550 if (wolopts & WAKE_MAGIC) 1551 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1552 else 1553 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1554 } else if (rtl_is_8125(tp)) { 1555 if (wolopts & WAKE_MAGIC) 1556 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1557 else 1558 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1559 } else { 1560 r8169_mod_reg8_cond(tp, Config3, MagicPacket, 1561 wolopts & WAKE_MAGIC); 1562 } 1563 1564 r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY); 1565 if (rtl_is_8125(tp)) 1566 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, 1567 wolopts & WAKE_PHY ? 0x13 : 0); 1568 r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST); 1569 r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST); 1570 r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST); 1571 r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts); 1572 1573 switch (tp->mac_version) { 1574 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1575 r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts); 1576 break; 1577 case RTL_GIGA_MAC_VER_34: 1578 case RTL_GIGA_MAC_VER_37: 1579 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1580 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); 1581 break; 1582 default: 1583 break; 1584 } 1585 1586 rtl_lock_config_regs(tp); 1587 1588 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1589 1590 if (!tp->dash_enabled) { 1591 rtl_set_d3_pll_down(tp, !wolopts); 1592 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1593 } 1594 } 1595 1596 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1597 { 1598 struct rtl8169_private *tp = netdev_priv(dev); 1599 1600 if (wol->wolopts & ~WAKE_ANY) 1601 return -EINVAL; 1602 1603 tp->saved_wolopts = wol->wolopts; 1604 __rtl8169_set_wol(tp, tp->saved_wolopts); 1605 1606 return 0; 1607 } 1608 1609 static void rtl8169_get_drvinfo(struct net_device *dev, 1610 struct ethtool_drvinfo *info) 1611 { 1612 struct rtl8169_private *tp = netdev_priv(dev); 1613 struct rtl_fw *rtl_fw = tp->rtl_fw; 1614 1615 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1616 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1617 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1618 if (rtl_fw) 1619 strscpy(info->fw_version, rtl_fw->version, 1620 sizeof(info->fw_version)); 1621 } 1622 1623 static int rtl8169_get_regs_len(struct net_device *dev) 1624 { 1625 return R8169_REGS_SIZE; 1626 } 1627 1628 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1629 netdev_features_t features) 1630 { 1631 struct rtl8169_private *tp = netdev_priv(dev); 1632 1633 if (dev->mtu > TD_MSS_MAX) 1634 features &= ~NETIF_F_ALL_TSO; 1635 1636 if (dev->mtu > ETH_DATA_LEN && 1637 tp->mac_version > RTL_GIGA_MAC_VER_06) 1638 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1639 1640 return features; 1641 } 1642 1643 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1644 netdev_features_t features) 1645 { 1646 u32 rx_config = RTL_R32(tp, RxConfig); 1647 1648 if (features & NETIF_F_RXALL) 1649 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1650 else 1651 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1652 1653 if (rtl_is_8125(tp)) { 1654 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1655 rx_config |= RX_VLAN_8125; 1656 else 1657 rx_config &= ~RX_VLAN_8125; 1658 } 1659 1660 RTL_W32(tp, RxConfig, rx_config); 1661 } 1662 1663 static int rtl8169_set_features(struct net_device *dev, 1664 netdev_features_t features) 1665 { 1666 struct rtl8169_private *tp = netdev_priv(dev); 1667 1668 rtl_set_rx_config_features(tp, features); 1669 1670 if (features & NETIF_F_RXCSUM) 1671 tp->cp_cmd |= RxChkSum; 1672 else 1673 tp->cp_cmd &= ~RxChkSum; 1674 1675 if (!rtl_is_8125(tp)) { 1676 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1677 tp->cp_cmd |= RxVlan; 1678 else 1679 tp->cp_cmd &= ~RxVlan; 1680 } 1681 1682 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1683 rtl_pci_commit(tp); 1684 1685 return 0; 1686 } 1687 1688 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1689 { 1690 return (skb_vlan_tag_present(skb)) ? 1691 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1692 } 1693 1694 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1695 { 1696 u32 opts2 = le32_to_cpu(desc->opts2); 1697 1698 if (opts2 & RxVlanTag) 1699 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1700 } 1701 1702 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1703 void *p) 1704 { 1705 struct rtl8169_private *tp = netdev_priv(dev); 1706 u32 __iomem *data = tp->mmio_addr; 1707 u32 *dw = p; 1708 int i; 1709 1710 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1711 memcpy_fromio(dw++, data++, 4); 1712 } 1713 1714 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1715 "tx_packets", 1716 "rx_packets", 1717 "tx_errors", 1718 "rx_errors", 1719 "rx_missed", 1720 "align_errors", 1721 "tx_single_collisions", 1722 "tx_multi_collisions", 1723 "unicast", 1724 "broadcast", 1725 "multicast", 1726 "tx_aborted", 1727 "tx_underrun", 1728 }; 1729 1730 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1731 { 1732 switch (sset) { 1733 case ETH_SS_STATS: 1734 return ARRAY_SIZE(rtl8169_gstrings); 1735 default: 1736 return -EOPNOTSUPP; 1737 } 1738 } 1739 1740 DECLARE_RTL_COND(rtl_counters_cond) 1741 { 1742 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1743 } 1744 1745 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1746 { 1747 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1748 1749 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1750 rtl_pci_commit(tp); 1751 RTL_W32(tp, CounterAddrLow, cmd); 1752 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1753 1754 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1755 } 1756 1757 static void rtl8169_update_counters(struct rtl8169_private *tp) 1758 { 1759 u8 val = RTL_R8(tp, ChipCmd); 1760 1761 /* 1762 * Some chips are unable to dump tally counters when the receiver 1763 * is disabled. If 0xff chip may be in a PCI power-save state. 1764 */ 1765 if (val & CmdRxEnb && val != 0xff) 1766 rtl8169_do_counters(tp, CounterDump); 1767 } 1768 1769 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1770 { 1771 struct rtl8169_counters *counters = tp->counters; 1772 1773 /* 1774 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1775 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1776 * reset by a power cycle, while the counter values collected by the 1777 * driver are reset at every driver unload/load cycle. 1778 * 1779 * To make sure the HW values returned by @get_stats64 match the SW 1780 * values, we collect the initial values at first open(*) and use them 1781 * as offsets to normalize the values returned by @get_stats64. 1782 * 1783 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1784 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1785 * set at open time by rtl_hw_start. 1786 */ 1787 1788 if (tp->tc_offset.inited) 1789 return; 1790 1791 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1792 rtl8169_do_counters(tp, CounterReset); 1793 } else { 1794 rtl8169_update_counters(tp); 1795 tp->tc_offset.tx_errors = counters->tx_errors; 1796 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1797 tp->tc_offset.tx_aborted = counters->tx_aborted; 1798 tp->tc_offset.rx_missed = counters->rx_missed; 1799 } 1800 1801 tp->tc_offset.inited = true; 1802 } 1803 1804 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1805 struct ethtool_stats *stats, u64 *data) 1806 { 1807 struct rtl8169_private *tp = netdev_priv(dev); 1808 struct rtl8169_counters *counters; 1809 1810 counters = tp->counters; 1811 rtl8169_update_counters(tp); 1812 1813 data[0] = le64_to_cpu(counters->tx_packets); 1814 data[1] = le64_to_cpu(counters->rx_packets); 1815 data[2] = le64_to_cpu(counters->tx_errors); 1816 data[3] = le32_to_cpu(counters->rx_errors); 1817 data[4] = le16_to_cpu(counters->rx_missed); 1818 data[5] = le16_to_cpu(counters->align_errors); 1819 data[6] = le32_to_cpu(counters->tx_one_collision); 1820 data[7] = le32_to_cpu(counters->tx_multi_collision); 1821 data[8] = le64_to_cpu(counters->rx_unicast); 1822 data[9] = le64_to_cpu(counters->rx_broadcast); 1823 data[10] = le32_to_cpu(counters->rx_multicast); 1824 data[11] = le16_to_cpu(counters->tx_aborted); 1825 data[12] = le16_to_cpu(counters->tx_underrun); 1826 } 1827 1828 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1829 { 1830 switch(stringset) { 1831 case ETH_SS_STATS: 1832 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1833 break; 1834 } 1835 } 1836 1837 /* 1838 * Interrupt coalescing 1839 * 1840 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1841 * > 8169, 8168 and 810x line of chipsets 1842 * 1843 * 8169, 8168, and 8136(810x) serial chipsets support it. 1844 * 1845 * > 2 - the Tx timer unit at gigabit speed 1846 * 1847 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1848 * (0xe0) bit 1 and bit 0. 1849 * 1850 * For 8169 1851 * bit[1:0] \ speed 1000M 100M 10M 1852 * 0 0 320ns 2.56us 40.96us 1853 * 0 1 2.56us 20.48us 327.7us 1854 * 1 0 5.12us 40.96us 655.4us 1855 * 1 1 10.24us 81.92us 1.31ms 1856 * 1857 * For the other 1858 * bit[1:0] \ speed 1000M 100M 10M 1859 * 0 0 5us 2.56us 40.96us 1860 * 0 1 40us 20.48us 327.7us 1861 * 1 0 80us 40.96us 655.4us 1862 * 1 1 160us 81.92us 1.31ms 1863 */ 1864 1865 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1866 struct rtl_coalesce_info { 1867 u32 speed; 1868 u32 scale_nsecs[4]; 1869 }; 1870 1871 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1872 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1873 1874 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1875 { SPEED_1000, COALESCE_DELAY(320) }, 1876 { SPEED_100, COALESCE_DELAY(2560) }, 1877 { SPEED_10, COALESCE_DELAY(40960) }, 1878 { 0 }, 1879 }; 1880 1881 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1882 { SPEED_1000, COALESCE_DELAY(5000) }, 1883 { SPEED_100, COALESCE_DELAY(2560) }, 1884 { SPEED_10, COALESCE_DELAY(40960) }, 1885 { 0 }, 1886 }; 1887 #undef COALESCE_DELAY 1888 1889 /* get rx/tx scale vector corresponding to current speed */ 1890 static const struct rtl_coalesce_info * 1891 rtl_coalesce_info(struct rtl8169_private *tp) 1892 { 1893 const struct rtl_coalesce_info *ci; 1894 1895 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1896 ci = rtl_coalesce_info_8169; 1897 else 1898 ci = rtl_coalesce_info_8168_8136; 1899 1900 /* if speed is unknown assume highest one */ 1901 if (tp->phydev->speed == SPEED_UNKNOWN) 1902 return ci; 1903 1904 for (; ci->speed; ci++) { 1905 if (tp->phydev->speed == ci->speed) 1906 return ci; 1907 } 1908 1909 return ERR_PTR(-ELNRNG); 1910 } 1911 1912 static int rtl_get_coalesce(struct net_device *dev, 1913 struct ethtool_coalesce *ec, 1914 struct kernel_ethtool_coalesce *kernel_coal, 1915 struct netlink_ext_ack *extack) 1916 { 1917 struct rtl8169_private *tp = netdev_priv(dev); 1918 const struct rtl_coalesce_info *ci; 1919 u32 scale, c_us, c_fr; 1920 u16 intrmit; 1921 1922 if (rtl_is_8125(tp)) 1923 return -EOPNOTSUPP; 1924 1925 memset(ec, 0, sizeof(*ec)); 1926 1927 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1928 ci = rtl_coalesce_info(tp); 1929 if (IS_ERR(ci)) 1930 return PTR_ERR(ci); 1931 1932 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1933 1934 intrmit = RTL_R16(tp, IntrMitigate); 1935 1936 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1937 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1938 1939 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1940 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1941 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1942 1943 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1944 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1945 1946 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1947 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1948 1949 return 0; 1950 } 1951 1952 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1953 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1954 u16 *cp01) 1955 { 1956 const struct rtl_coalesce_info *ci; 1957 u16 i; 1958 1959 ci = rtl_coalesce_info(tp); 1960 if (IS_ERR(ci)) 1961 return PTR_ERR(ci); 1962 1963 for (i = 0; i < 4; i++) { 1964 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1965 *cp01 = i; 1966 return ci->scale_nsecs[i]; 1967 } 1968 } 1969 1970 return -ERANGE; 1971 } 1972 1973 static int rtl_set_coalesce(struct net_device *dev, 1974 struct ethtool_coalesce *ec, 1975 struct kernel_ethtool_coalesce *kernel_coal, 1976 struct netlink_ext_ack *extack) 1977 { 1978 struct rtl8169_private *tp = netdev_priv(dev); 1979 u32 tx_fr = ec->tx_max_coalesced_frames; 1980 u32 rx_fr = ec->rx_max_coalesced_frames; 1981 u32 coal_usec_max, units; 1982 u16 w = 0, cp01 = 0; 1983 int scale; 1984 1985 if (rtl_is_8125(tp)) 1986 return -EOPNOTSUPP; 1987 1988 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1989 return -ERANGE; 1990 1991 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1992 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1993 if (scale < 0) 1994 return scale; 1995 1996 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1997 * not only when usecs=0 because of e.g. the following scenario: 1998 * 1999 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2000 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2001 * - then user does `ethtool -C eth0 rx-usecs 100` 2002 * 2003 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2004 * if we want to ignore rx_frames then it has to be set to 0. 2005 */ 2006 if (rx_fr == 1) 2007 rx_fr = 0; 2008 if (tx_fr == 1) 2009 tx_fr = 0; 2010 2011 /* HW requires time limit to be set if frame limit is set */ 2012 if ((tx_fr && !ec->tx_coalesce_usecs) || 2013 (rx_fr && !ec->rx_coalesce_usecs)) 2014 return -EINVAL; 2015 2016 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2017 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2018 2019 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2020 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2021 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2022 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2023 2024 RTL_W16(tp, IntrMitigate, w); 2025 2026 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2027 if (rtl_is_8168evl_up(tp)) { 2028 if (!rx_fr && !tx_fr) 2029 /* disable packet counter */ 2030 tp->cp_cmd |= PktCntrDisable; 2031 else 2032 tp->cp_cmd &= ~PktCntrDisable; 2033 } 2034 2035 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2036 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2037 rtl_pci_commit(tp); 2038 2039 return 0; 2040 } 2041 2042 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2043 { 2044 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2045 2046 switch (tp->mac_version) { 2047 case RTL_GIGA_MAC_VER_46: 2048 case RTL_GIGA_MAC_VER_48: 2049 tp->tx_lpi_timer = timer_val; 2050 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2051 break; 2052 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2053 tp->tx_lpi_timer = timer_val; 2054 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2055 break; 2056 default: 2057 break; 2058 } 2059 } 2060 2061 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2062 { 2063 unsigned int speed = tp->phydev->speed; 2064 unsigned int timer = tp->tx_lpi_timer; 2065 2066 if (!timer || speed == SPEED_UNKNOWN) 2067 return 0; 2068 2069 /* tx_lpi_timer value is in bytes */ 2070 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2071 } 2072 2073 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2074 { 2075 struct rtl8169_private *tp = netdev_priv(dev); 2076 int ret; 2077 2078 if (!rtl_supports_eee(tp)) 2079 return -EOPNOTSUPP; 2080 2081 ret = phy_ethtool_get_eee(tp->phydev, data); 2082 if (ret) 2083 return ret; 2084 2085 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2086 2087 return 0; 2088 } 2089 2090 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2091 { 2092 struct rtl8169_private *tp = netdev_priv(dev); 2093 2094 if (!rtl_supports_eee(tp)) 2095 return -EOPNOTSUPP; 2096 2097 return phy_ethtool_set_eee(tp->phydev, data); 2098 } 2099 2100 static void rtl8169_get_ringparam(struct net_device *dev, 2101 struct ethtool_ringparam *data, 2102 struct kernel_ethtool_ringparam *kernel_data, 2103 struct netlink_ext_ack *extack) 2104 { 2105 data->rx_max_pending = NUM_RX_DESC; 2106 data->rx_pending = NUM_RX_DESC; 2107 data->tx_max_pending = NUM_TX_DESC; 2108 data->tx_pending = NUM_TX_DESC; 2109 } 2110 2111 static void rtl8169_get_pause_stats(struct net_device *dev, 2112 struct ethtool_pause_stats *pause_stats) 2113 { 2114 struct rtl8169_private *tp = netdev_priv(dev); 2115 2116 if (!rtl_is_8125(tp)) 2117 return; 2118 2119 rtl8169_update_counters(tp); 2120 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on); 2121 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on); 2122 } 2123 2124 static void rtl8169_get_pauseparam(struct net_device *dev, 2125 struct ethtool_pauseparam *data) 2126 { 2127 struct rtl8169_private *tp = netdev_priv(dev); 2128 bool tx_pause, rx_pause; 2129 2130 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2131 2132 data->autoneg = tp->phydev->autoneg; 2133 data->tx_pause = tx_pause ? 1 : 0; 2134 data->rx_pause = rx_pause ? 1 : 0; 2135 } 2136 2137 static int rtl8169_set_pauseparam(struct net_device *dev, 2138 struct ethtool_pauseparam *data) 2139 { 2140 struct rtl8169_private *tp = netdev_priv(dev); 2141 2142 if (dev->mtu > ETH_DATA_LEN) 2143 return -EOPNOTSUPP; 2144 2145 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2146 2147 return 0; 2148 } 2149 2150 static void rtl8169_get_eth_mac_stats(struct net_device *dev, 2151 struct ethtool_eth_mac_stats *mac_stats) 2152 { 2153 struct rtl8169_private *tp = netdev_priv(dev); 2154 2155 rtl8169_update_counters(tp); 2156 2157 mac_stats->FramesTransmittedOK = 2158 le64_to_cpu(tp->counters->tx_packets); 2159 mac_stats->SingleCollisionFrames = 2160 le32_to_cpu(tp->counters->tx_one_collision); 2161 mac_stats->MultipleCollisionFrames = 2162 le32_to_cpu(tp->counters->tx_multi_collision); 2163 mac_stats->FramesReceivedOK = 2164 le64_to_cpu(tp->counters->rx_packets); 2165 mac_stats->AlignmentErrors = 2166 le16_to_cpu(tp->counters->align_errors); 2167 mac_stats->FramesLostDueToIntMACXmitError = 2168 le64_to_cpu(tp->counters->tx_errors); 2169 mac_stats->BroadcastFramesReceivedOK = 2170 le64_to_cpu(tp->counters->rx_broadcast); 2171 mac_stats->MulticastFramesReceivedOK = 2172 le32_to_cpu(tp->counters->rx_multicast); 2173 2174 if (!rtl_is_8125(tp)) 2175 return; 2176 2177 mac_stats->AlignmentErrors = 2178 le32_to_cpu(tp->counters->align_errors32); 2179 mac_stats->OctetsTransmittedOK = 2180 le64_to_cpu(tp->counters->tx_octets); 2181 mac_stats->LateCollisions = 2182 le32_to_cpu(tp->counters->tx_late_collision); 2183 mac_stats->FramesAbortedDueToXSColls = 2184 le32_to_cpu(tp->counters->tx_aborted32); 2185 mac_stats->OctetsReceivedOK = 2186 le64_to_cpu(tp->counters->rx_octets); 2187 mac_stats->FramesLostDueToIntMACRcvError = 2188 le32_to_cpu(tp->counters->rx_mac_error); 2189 mac_stats->MulticastFramesXmittedOK = 2190 le64_to_cpu(tp->counters->tx_multicast64); 2191 mac_stats->BroadcastFramesXmittedOK = 2192 le64_to_cpu(tp->counters->tx_broadcast64); 2193 mac_stats->MulticastFramesReceivedOK = 2194 le64_to_cpu(tp->counters->rx_multicast64); 2195 mac_stats->FrameTooLongErrors = 2196 le32_to_cpu(tp->counters->rx_frame_too_long); 2197 } 2198 2199 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, 2200 struct ethtool_eth_ctrl_stats *ctrl_stats) 2201 { 2202 struct rtl8169_private *tp = netdev_priv(dev); 2203 2204 if (!rtl_is_8125(tp)) 2205 return; 2206 2207 rtl8169_update_counters(tp); 2208 2209 ctrl_stats->UnsupportedOpcodesReceived = 2210 le32_to_cpu(tp->counters->rx_unknown_opcode); 2211 } 2212 2213 static const struct ethtool_ops rtl8169_ethtool_ops = { 2214 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2215 ETHTOOL_COALESCE_MAX_FRAMES, 2216 .get_drvinfo = rtl8169_get_drvinfo, 2217 .get_regs_len = rtl8169_get_regs_len, 2218 .get_link = ethtool_op_get_link, 2219 .get_coalesce = rtl_get_coalesce, 2220 .set_coalesce = rtl_set_coalesce, 2221 .get_regs = rtl8169_get_regs, 2222 .get_wol = rtl8169_get_wol, 2223 .set_wol = rtl8169_set_wol, 2224 .get_strings = rtl8169_get_strings, 2225 .get_sset_count = rtl8169_get_sset_count, 2226 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2227 .get_ts_info = ethtool_op_get_ts_info, 2228 .nway_reset = phy_ethtool_nway_reset, 2229 .get_eee = rtl8169_get_eee, 2230 .set_eee = rtl8169_set_eee, 2231 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2232 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2233 .get_ringparam = rtl8169_get_ringparam, 2234 .get_pause_stats = rtl8169_get_pause_stats, 2235 .get_pauseparam = rtl8169_get_pauseparam, 2236 .set_pauseparam = rtl8169_set_pauseparam, 2237 .get_eth_mac_stats = rtl8169_get_eth_mac_stats, 2238 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, 2239 }; 2240 2241 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2242 { 2243 /* 2244 * The driver currently handles the 8168Bf and the 8168Be identically 2245 * but they can be identified more specifically through the test below 2246 * if needed: 2247 * 2248 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2249 * 2250 * Same thing for the 8101Eb and the 8101Ec: 2251 * 2252 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2253 */ 2254 static const struct rtl_mac_info { 2255 u16 mask; 2256 u16 val; 2257 enum mac_version ver; 2258 } mac_info[] = { 2259 /* 8126A family. */ 2260 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 }, 2261 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2262 2263 /* 8125D family. */ 2264 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, 2265 2266 /* 8125B family. */ 2267 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2268 2269 /* 8125A family. */ 2270 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2271 /* It seems only XID 609 made it to the mass market. 2272 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2273 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2274 */ 2275 2276 /* RTL8117 */ 2277 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2278 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2279 2280 /* 8168EP family. */ 2281 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2282 /* It seems this chip version never made it to 2283 * the wild. Let's disable detection. 2284 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2285 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2286 */ 2287 2288 /* 8168H family. */ 2289 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2290 /* It seems this chip version never made it to 2291 * the wild. Let's disable detection. 2292 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2293 */ 2294 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 2295 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, 2296 2297 /* 8168G family. */ 2298 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2299 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2300 /* It seems this chip version never made it to 2301 * the wild. Let's disable detection. 2302 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2303 */ 2304 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2305 2306 /* 8168F family. */ 2307 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2308 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2309 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2310 2311 /* 8168E family. */ 2312 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2313 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2314 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2315 2316 /* 8168D family. */ 2317 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2318 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2319 2320 /* 8168DP family. */ 2321 /* It seems this early RTL8168dp version never made it to 2322 * the wild. Support has been removed. 2323 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2324 */ 2325 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2326 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2327 2328 /* 8168C family. */ 2329 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2330 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2331 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2332 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2333 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2334 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2335 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2336 2337 /* 8168B family. */ 2338 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2339 /* This one is very old and rare, let's see if anybody complains. 2340 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2341 */ 2342 2343 /* 8101 family. */ 2344 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2345 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2346 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2347 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2348 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2349 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2350 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2351 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2352 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2353 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2354 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2355 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2356 2357 /* 8110 family. */ 2358 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2359 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2360 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2361 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2362 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2363 2364 /* Catch-all */ 2365 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2366 }; 2367 const struct rtl_mac_info *p = mac_info; 2368 enum mac_version ver; 2369 2370 while ((xid & p->mask) != p->val) 2371 p++; 2372 ver = p->ver; 2373 2374 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2375 if (ver == RTL_GIGA_MAC_VER_42) 2376 ver = RTL_GIGA_MAC_VER_43; 2377 else if (ver == RTL_GIGA_MAC_VER_46) 2378 ver = RTL_GIGA_MAC_VER_48; 2379 } 2380 2381 return ver; 2382 } 2383 2384 static void rtl_release_firmware(struct rtl8169_private *tp) 2385 { 2386 if (tp->rtl_fw) { 2387 rtl_fw_release_firmware(tp->rtl_fw); 2388 kfree(tp->rtl_fw); 2389 tp->rtl_fw = NULL; 2390 } 2391 } 2392 2393 void r8169_apply_firmware(struct rtl8169_private *tp) 2394 { 2395 int val; 2396 2397 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2398 if (tp->rtl_fw) { 2399 rtl_fw_write_firmware(tp, tp->rtl_fw); 2400 /* At least one firmware doesn't reset tp->ocp_base. */ 2401 tp->ocp_base = OCP_STD_PHY_BASE; 2402 2403 /* PHY soft reset may still be in progress */ 2404 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2405 !(val & BMCR_RESET), 2406 50000, 600000, true); 2407 } 2408 } 2409 2410 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2411 { 2412 /* Adjust EEE LED frequency */ 2413 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2414 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2415 2416 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2417 } 2418 2419 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2420 { 2421 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2422 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2423 } 2424 2425 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2426 { 2427 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2428 } 2429 2430 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2431 { 2432 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2433 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2434 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2435 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2436 } 2437 2438 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2439 { 2440 u16 data1, data2, ioffset; 2441 2442 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2443 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2444 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2445 2446 ioffset = (data2 >> 1) & 0x7ff8; 2447 ioffset |= data2 & 0x0007; 2448 if (data1 & BIT(7)) 2449 ioffset |= BIT(15); 2450 2451 return ioffset; 2452 } 2453 2454 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2455 { 2456 set_bit(flag, tp->wk.flags); 2457 if (!schedule_work(&tp->wk.work)) 2458 clear_bit(flag, tp->wk.flags); 2459 } 2460 2461 static void rtl8169_init_phy(struct rtl8169_private *tp) 2462 { 2463 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2464 2465 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2466 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2467 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2468 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2469 RTL_W8(tp, 0x82, 0x01); 2470 } 2471 2472 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2473 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2474 tp->pci_dev->subsystem_device == 0xe000) 2475 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2476 2477 /* We may have called phy_speed_down before */ 2478 phy_speed_up(tp->phydev); 2479 2480 genphy_soft_reset(tp->phydev); 2481 } 2482 2483 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2484 { 2485 rtl_unlock_config_regs(tp); 2486 2487 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2488 rtl_pci_commit(tp); 2489 2490 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2491 rtl_pci_commit(tp); 2492 2493 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2494 rtl_rar_exgmac_set(tp, addr); 2495 2496 rtl_lock_config_regs(tp); 2497 } 2498 2499 static int rtl_set_mac_address(struct net_device *dev, void *p) 2500 { 2501 struct rtl8169_private *tp = netdev_priv(dev); 2502 int ret; 2503 2504 ret = eth_mac_addr(dev, p); 2505 if (ret) 2506 return ret; 2507 2508 rtl_rar_set(tp, dev->dev_addr); 2509 2510 return 0; 2511 } 2512 2513 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2514 { 2515 switch (tp->mac_version) { 2516 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2517 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2518 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2519 break; 2520 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2521 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2522 case RTL_GIGA_MAC_VER_38: 2523 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2524 break; 2525 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2526 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2527 break; 2528 case RTL_GIGA_MAC_VER_61: 2529 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2530 break; 2531 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2532 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2533 RX_PAUSE_SLOT_ON); 2534 break; 2535 default: 2536 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2537 break; 2538 } 2539 } 2540 2541 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2542 { 2543 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2544 } 2545 2546 static void rtl_jumbo_config(struct rtl8169_private *tp) 2547 { 2548 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2549 int readrq = 4096; 2550 2551 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 && 2552 tp->mac_version <= RTL_GIGA_MAC_VER_26) 2553 readrq = 512; 2554 2555 rtl_unlock_config_regs(tp); 2556 switch (tp->mac_version) { 2557 case RTL_GIGA_MAC_VER_17: 2558 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2559 break; 2560 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2561 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2562 r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo); 2563 break; 2564 case RTL_GIGA_MAC_VER_28: 2565 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2566 break; 2567 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2568 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); 2569 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2570 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2571 break; 2572 default: 2573 break; 2574 } 2575 rtl_lock_config_regs(tp); 2576 2577 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2578 pcie_set_readrq(tp->pci_dev, readrq); 2579 2580 /* Chip doesn't support pause in jumbo mode */ 2581 if (jumbo) { 2582 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2583 tp->phydev->advertising); 2584 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2585 tp->phydev->advertising); 2586 phy_start_aneg(tp->phydev); 2587 } 2588 } 2589 2590 DECLARE_RTL_COND(rtl_chipcmd_cond) 2591 { 2592 return RTL_R8(tp, ChipCmd) & CmdReset; 2593 } 2594 2595 static void rtl_hw_reset(struct rtl8169_private *tp) 2596 { 2597 RTL_W8(tp, ChipCmd, CmdReset); 2598 2599 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2600 } 2601 2602 static void rtl_request_firmware(struct rtl8169_private *tp) 2603 { 2604 struct rtl_fw *rtl_fw; 2605 2606 /* firmware loaded already or no firmware available */ 2607 if (tp->rtl_fw || !tp->fw_name) 2608 return; 2609 2610 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2611 if (!rtl_fw) 2612 return; 2613 2614 rtl_fw->phy_write = rtl_writephy; 2615 rtl_fw->phy_read = rtl_readphy; 2616 rtl_fw->mac_mcu_write = mac_mcu_write; 2617 rtl_fw->mac_mcu_read = mac_mcu_read; 2618 rtl_fw->fw_name = tp->fw_name; 2619 rtl_fw->dev = tp_to_dev(tp); 2620 2621 if (rtl_fw_request_firmware(rtl_fw)) 2622 kfree(rtl_fw); 2623 else 2624 tp->rtl_fw = rtl_fw; 2625 } 2626 2627 static void rtl_rx_close(struct rtl8169_private *tp) 2628 { 2629 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2630 } 2631 2632 DECLARE_RTL_COND(rtl_npq_cond) 2633 { 2634 return RTL_R8(tp, TxPoll) & NPQ; 2635 } 2636 2637 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2638 { 2639 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2640 } 2641 2642 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2643 { 2644 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2645 } 2646 2647 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2648 { 2649 /* IntrMitigate has new functionality on RTL8125 */ 2650 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2651 } 2652 2653 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2654 { 2655 switch (tp->mac_version) { 2656 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2657 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2658 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2659 break; 2660 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2661 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2662 break; 2663 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2664 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2665 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2666 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2667 break; 2668 default: 2669 break; 2670 } 2671 } 2672 2673 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2674 { 2675 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2676 } 2677 2678 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2679 { 2680 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2681 fsleep(2000); 2682 rtl_wait_txrx_fifo_empty(tp); 2683 } 2684 2685 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2686 { 2687 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2688 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2689 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2690 2691 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2692 rtl_disable_rxdvgate(tp); 2693 } 2694 2695 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2696 { 2697 if (tp->dash_enabled) 2698 return; 2699 2700 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2701 tp->mac_version == RTL_GIGA_MAC_VER_33) 2702 rtl_ephy_write(tp, 0x19, 0xff64); 2703 2704 if (device_may_wakeup(tp_to_dev(tp))) { 2705 phy_speed_down(tp->phydev, false); 2706 rtl_wol_enable_rx(tp); 2707 } 2708 } 2709 2710 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2711 { 2712 u32 val = TX_DMA_BURST << TxDMAShift | 2713 InterFrameGap << TxInterFrameGapShift; 2714 2715 if (rtl_is_8168evl_up(tp)) 2716 val |= TXCFG_AUTO_FIFO; 2717 2718 RTL_W32(tp, TxConfig, val); 2719 } 2720 2721 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2722 { 2723 /* Low hurts. Let's disable the filtering. */ 2724 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2725 } 2726 2727 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2728 { 2729 /* 2730 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2731 * register to be written before TxDescAddrLow to work. 2732 * Switching from MMIO to I/O access fixes the issue as well. 2733 */ 2734 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2735 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2736 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2737 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2738 } 2739 2740 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2741 { 2742 u32 val; 2743 2744 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2745 val = 0x000fff00; 2746 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2747 val = 0x00ffff00; 2748 else 2749 return; 2750 2751 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2752 val |= 0xff; 2753 2754 RTL_W32(tp, 0x7c, val); 2755 } 2756 2757 static void rtl_set_rx_mode(struct net_device *dev) 2758 { 2759 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2760 /* Multicast hash filter */ 2761 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2762 struct rtl8169_private *tp = netdev_priv(dev); 2763 u32 tmp; 2764 2765 if (dev->flags & IFF_PROMISC) { 2766 rx_mode |= AcceptAllPhys; 2767 } else if (!(dev->flags & IFF_MULTICAST)) { 2768 rx_mode &= ~AcceptMulticast; 2769 } else if (dev->flags & IFF_ALLMULTI || 2770 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2771 /* accept all multicasts */ 2772 } else if (netdev_mc_empty(dev)) { 2773 rx_mode &= ~AcceptMulticast; 2774 } else { 2775 struct netdev_hw_addr *ha; 2776 2777 mc_filter[1] = mc_filter[0] = 0; 2778 netdev_for_each_mc_addr(ha, dev) { 2779 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2780 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2781 } 2782 2783 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2784 tmp = mc_filter[0]; 2785 mc_filter[0] = swab32(mc_filter[1]); 2786 mc_filter[1] = swab32(tmp); 2787 } 2788 } 2789 2790 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2791 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2792 2793 tmp = RTL_R32(tp, RxConfig); 2794 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2795 } 2796 2797 DECLARE_RTL_COND(rtl_csiar_cond) 2798 { 2799 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2800 } 2801 2802 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2803 { 2804 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2805 2806 RTL_W32(tp, CSIDR, value); 2807 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2808 CSIAR_BYTE_ENABLE | func << 16); 2809 2810 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2811 } 2812 2813 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2814 { 2815 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2816 2817 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2818 CSIAR_BYTE_ENABLE); 2819 2820 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2821 RTL_R32(tp, CSIDR) : ~0; 2822 } 2823 2824 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2825 { 2826 struct pci_dev *pdev = tp->pci_dev; 2827 u32 csi; 2828 2829 /* According to Realtek the value at config space address 0x070f 2830 * controls the L0s/L1 entrance latency. We try standard ECAM access 2831 * first and if it fails fall back to CSI. 2832 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2833 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2834 */ 2835 if (pdev->cfg_size > 0x070f && 2836 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2837 return; 2838 2839 netdev_notice_once(tp->dev, 2840 "No native access to PCI extended config space, falling back to CSI\n"); 2841 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2842 rtl_csi_write(tp, 0x070c, csi | val << 24); 2843 } 2844 2845 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2846 { 2847 /* L0 7us, L1 16us */ 2848 rtl_set_aspm_entry_latency(tp, 0x27); 2849 } 2850 2851 struct ephy_info { 2852 unsigned int offset; 2853 u16 mask; 2854 u16 bits; 2855 }; 2856 2857 static void __rtl_ephy_init(struct rtl8169_private *tp, 2858 const struct ephy_info *e, int len) 2859 { 2860 u16 w; 2861 2862 while (len-- > 0) { 2863 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2864 rtl_ephy_write(tp, e->offset, w); 2865 e++; 2866 } 2867 } 2868 2869 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2870 2871 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2872 { 2873 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2874 PCI_EXP_LNKCTL_CLKREQ_EN); 2875 } 2876 2877 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2878 { 2879 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2880 PCI_EXP_LNKCTL_CLKREQ_EN); 2881 } 2882 2883 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2884 { 2885 /* work around an issue when PCI reset occurs during L2/L3 state */ 2886 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2887 } 2888 2889 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2890 { 2891 /* Bits control which events trigger ASPM L1 exit: 2892 * Bit 12: rxdv 2893 * Bit 11: ltr_msg 2894 * Bit 10: txdma_poll 2895 * Bit 9: xadm 2896 * Bit 8: pktavi 2897 * Bit 7: txpla 2898 */ 2899 switch (tp->mac_version) { 2900 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2901 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2902 break; 2903 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2904 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2905 break; 2906 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2907 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2908 break; 2909 default: 2910 break; 2911 } 2912 } 2913 2914 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2915 { 2916 switch (tp->mac_version) { 2917 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2918 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2919 break; 2920 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2921 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2922 break; 2923 default: 2924 break; 2925 } 2926 } 2927 2928 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2929 { 2930 u8 val8; 2931 2932 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2933 return; 2934 2935 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2936 if (enable && tp->aspm_manageable) { 2937 /* On these chip versions ASPM can even harm 2938 * bus communication of other PCI devices. 2939 */ 2940 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2941 tp->mac_version == RTL_GIGA_MAC_VER_43) 2942 return; 2943 2944 rtl_mod_config5(tp, 0, ASPM_en); 2945 switch (tp->mac_version) { 2946 case RTL_GIGA_MAC_VER_65: 2947 case RTL_GIGA_MAC_VER_66: 2948 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2949 RTL_W8(tp, INT_CFG0_8125, val8); 2950 break; 2951 default: 2952 rtl_mod_config2(tp, 0, ClkReqEn); 2953 break; 2954 } 2955 2956 switch (tp->mac_version) { 2957 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2958 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2959 /* reset ephy tx/rx disable timer */ 2960 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2961 /* chip can trigger L1.2 */ 2962 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2963 break; 2964 default: 2965 break; 2966 } 2967 } else { 2968 switch (tp->mac_version) { 2969 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2970 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2971 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2972 break; 2973 default: 2974 break; 2975 } 2976 2977 switch (tp->mac_version) { 2978 case RTL_GIGA_MAC_VER_65: 2979 case RTL_GIGA_MAC_VER_66: 2980 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2981 RTL_W8(tp, INT_CFG0_8125, val8); 2982 break; 2983 default: 2984 rtl_mod_config2(tp, ClkReqEn, 0); 2985 break; 2986 } 2987 rtl_mod_config5(tp, ASPM_en, 0); 2988 } 2989 } 2990 2991 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2992 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2993 { 2994 /* Usage of dynamic vs. static FIFO is controlled by bit 2995 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2996 */ 2997 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2998 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2999 } 3000 3001 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3002 u8 low, u8 high) 3003 { 3004 /* FIFO thresholds for pause flow control */ 3005 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3006 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3007 } 3008 3009 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3010 { 3011 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3012 } 3013 3014 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3015 { 3016 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3017 3018 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3019 3020 rtl_disable_clock_request(tp); 3021 } 3022 3023 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3024 { 3025 static const struct ephy_info e_info_8168cp[] = { 3026 { 0x01, 0, 0x0001 }, 3027 { 0x02, 0x0800, 0x1000 }, 3028 { 0x03, 0, 0x0042 }, 3029 { 0x06, 0x0080, 0x0000 }, 3030 { 0x07, 0, 0x2000 } 3031 }; 3032 3033 rtl_set_def_aspm_entry_latency(tp); 3034 3035 rtl_ephy_init(tp, e_info_8168cp); 3036 3037 __rtl_hw_start_8168cp(tp); 3038 } 3039 3040 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3041 { 3042 rtl_set_def_aspm_entry_latency(tp); 3043 3044 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3045 } 3046 3047 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3048 { 3049 rtl_set_def_aspm_entry_latency(tp); 3050 3051 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3052 3053 /* Magic. */ 3054 RTL_W8(tp, DBG_REG, 0x20); 3055 } 3056 3057 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3058 { 3059 static const struct ephy_info e_info_8168c_1[] = { 3060 { 0x02, 0x0800, 0x1000 }, 3061 { 0x03, 0, 0x0002 }, 3062 { 0x06, 0x0080, 0x0000 } 3063 }; 3064 3065 rtl_set_def_aspm_entry_latency(tp); 3066 3067 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3068 3069 rtl_ephy_init(tp, e_info_8168c_1); 3070 3071 __rtl_hw_start_8168cp(tp); 3072 } 3073 3074 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3075 { 3076 static const struct ephy_info e_info_8168c_2[] = { 3077 { 0x01, 0, 0x0001 }, 3078 { 0x03, 0x0400, 0x0020 } 3079 }; 3080 3081 rtl_set_def_aspm_entry_latency(tp); 3082 3083 rtl_ephy_init(tp, e_info_8168c_2); 3084 3085 __rtl_hw_start_8168cp(tp); 3086 } 3087 3088 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3089 { 3090 rtl_set_def_aspm_entry_latency(tp); 3091 3092 __rtl_hw_start_8168cp(tp); 3093 } 3094 3095 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3096 { 3097 rtl_set_def_aspm_entry_latency(tp); 3098 3099 rtl_disable_clock_request(tp); 3100 } 3101 3102 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3103 { 3104 static const struct ephy_info e_info_8168d_4[] = { 3105 { 0x0b, 0x0000, 0x0048 }, 3106 { 0x19, 0x0020, 0x0050 }, 3107 { 0x0c, 0x0100, 0x0020 }, 3108 { 0x10, 0x0004, 0x0000 }, 3109 }; 3110 3111 rtl_set_def_aspm_entry_latency(tp); 3112 3113 rtl_ephy_init(tp, e_info_8168d_4); 3114 3115 rtl_enable_clock_request(tp); 3116 } 3117 3118 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3119 { 3120 static const struct ephy_info e_info_8168e_1[] = { 3121 { 0x00, 0x0200, 0x0100 }, 3122 { 0x00, 0x0000, 0x0004 }, 3123 { 0x06, 0x0002, 0x0001 }, 3124 { 0x06, 0x0000, 0x0030 }, 3125 { 0x07, 0x0000, 0x2000 }, 3126 { 0x00, 0x0000, 0x0020 }, 3127 { 0x03, 0x5800, 0x2000 }, 3128 { 0x03, 0x0000, 0x0001 }, 3129 { 0x01, 0x0800, 0x1000 }, 3130 { 0x07, 0x0000, 0x4000 }, 3131 { 0x1e, 0x0000, 0x2000 }, 3132 { 0x19, 0xffff, 0xfe6c }, 3133 { 0x0a, 0x0000, 0x0040 } 3134 }; 3135 3136 rtl_set_def_aspm_entry_latency(tp); 3137 3138 rtl_ephy_init(tp, e_info_8168e_1); 3139 3140 rtl_disable_clock_request(tp); 3141 3142 /* Reset tx FIFO pointer */ 3143 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3144 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3145 3146 rtl_mod_config5(tp, Spi_en, 0); 3147 } 3148 3149 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3150 { 3151 static const struct ephy_info e_info_8168e_2[] = { 3152 { 0x09, 0x0000, 0x0080 }, 3153 { 0x19, 0x0000, 0x0224 }, 3154 { 0x00, 0x0000, 0x0004 }, 3155 { 0x0c, 0x3df0, 0x0200 }, 3156 }; 3157 3158 rtl_set_def_aspm_entry_latency(tp); 3159 3160 rtl_ephy_init(tp, e_info_8168e_2); 3161 3162 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3163 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3164 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3165 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3166 rtl_reset_packet_filter(tp); 3167 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3168 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3169 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3170 3171 rtl_disable_clock_request(tp); 3172 3173 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3174 3175 rtl8168_config_eee_mac(tp); 3176 3177 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3178 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3179 rtl_mod_config5(tp, Spi_en, 0); 3180 } 3181 3182 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3183 { 3184 rtl_set_def_aspm_entry_latency(tp); 3185 3186 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3187 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3188 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3189 rtl_reset_packet_filter(tp); 3190 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3191 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3192 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3193 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3194 3195 rtl_disable_clock_request(tp); 3196 3197 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3198 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3199 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3200 rtl_mod_config5(tp, Spi_en, 0); 3201 3202 rtl8168_config_eee_mac(tp); 3203 } 3204 3205 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3206 { 3207 static const struct ephy_info e_info_8168f_1[] = { 3208 { 0x06, 0x00c0, 0x0020 }, 3209 { 0x08, 0x0001, 0x0002 }, 3210 { 0x09, 0x0000, 0x0080 }, 3211 { 0x19, 0x0000, 0x0224 }, 3212 { 0x00, 0x0000, 0x0008 }, 3213 { 0x0c, 0x3df0, 0x0200 }, 3214 }; 3215 3216 rtl_hw_start_8168f(tp); 3217 3218 rtl_ephy_init(tp, e_info_8168f_1); 3219 } 3220 3221 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3222 { 3223 static const struct ephy_info e_info_8168f_1[] = { 3224 { 0x06, 0x00c0, 0x0020 }, 3225 { 0x0f, 0xffff, 0x5200 }, 3226 { 0x19, 0x0000, 0x0224 }, 3227 { 0x00, 0x0000, 0x0008 }, 3228 { 0x0c, 0x3df0, 0x0200 }, 3229 }; 3230 3231 rtl_hw_start_8168f(tp); 3232 rtl_pcie_state_l2l3_disable(tp); 3233 3234 rtl_ephy_init(tp, e_info_8168f_1); 3235 } 3236 3237 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3238 { 3239 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3240 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3241 3242 rtl_set_def_aspm_entry_latency(tp); 3243 3244 rtl_reset_packet_filter(tp); 3245 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3246 3247 rtl_disable_rxdvgate(tp); 3248 3249 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3250 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3251 3252 rtl8168_config_eee_mac(tp); 3253 3254 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3255 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3256 3257 rtl_pcie_state_l2l3_disable(tp); 3258 } 3259 3260 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3261 { 3262 static const struct ephy_info e_info_8168g_1[] = { 3263 { 0x00, 0x0008, 0x0000 }, 3264 { 0x0c, 0x3ff0, 0x0820 }, 3265 { 0x1e, 0x0000, 0x0001 }, 3266 { 0x19, 0x8000, 0x0000 } 3267 }; 3268 3269 rtl_hw_start_8168g(tp); 3270 rtl_ephy_init(tp, e_info_8168g_1); 3271 } 3272 3273 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3274 { 3275 static const struct ephy_info e_info_8168g_2[] = { 3276 { 0x00, 0x0008, 0x0000 }, 3277 { 0x0c, 0x3ff0, 0x0820 }, 3278 { 0x19, 0xffff, 0x7c00 }, 3279 { 0x1e, 0xffff, 0x20eb }, 3280 { 0x0d, 0xffff, 0x1666 }, 3281 { 0x00, 0xffff, 0x10a3 }, 3282 { 0x06, 0xffff, 0xf050 }, 3283 { 0x04, 0x0000, 0x0010 }, 3284 { 0x1d, 0x4000, 0x0000 }, 3285 }; 3286 3287 rtl_hw_start_8168g(tp); 3288 rtl_ephy_init(tp, e_info_8168g_2); 3289 } 3290 3291 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3292 { 3293 static const u16 fix_data[] = { 3294 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3295 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3296 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3297 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3298 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3299 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3300 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3301 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3302 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3303 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3304 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3305 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3306 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3307 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3308 }; 3309 unsigned long flags; 3310 int i; 3311 3312 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3313 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3314 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3315 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3316 } 3317 3318 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3319 { 3320 static const struct ephy_info e_info_8411_2[] = { 3321 { 0x00, 0x0008, 0x0000 }, 3322 { 0x0c, 0x37d0, 0x0820 }, 3323 { 0x1e, 0x0000, 0x0001 }, 3324 { 0x19, 0x8021, 0x0000 }, 3325 { 0x1e, 0x0000, 0x2000 }, 3326 { 0x0d, 0x0100, 0x0200 }, 3327 { 0x00, 0x0000, 0x0080 }, 3328 { 0x06, 0x0000, 0x0010 }, 3329 { 0x04, 0x0000, 0x0010 }, 3330 { 0x1d, 0x0000, 0x4000 }, 3331 }; 3332 3333 rtl_hw_start_8168g(tp); 3334 3335 rtl_ephy_init(tp, e_info_8411_2); 3336 3337 /* The following Realtek-provided magic fixes an issue with the RX unit 3338 * getting confused after the PHY having been powered-down. 3339 */ 3340 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3341 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3342 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3343 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3344 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3345 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3346 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3347 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3348 mdelay(3); 3349 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3350 3351 rtl8411b_fix_phy_down(tp); 3352 3353 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3354 3355 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3356 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3357 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3358 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3359 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3360 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3361 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3362 } 3363 3364 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3365 { 3366 static const struct ephy_info e_info_8168h_1[] = { 3367 { 0x1e, 0x0800, 0x0001 }, 3368 { 0x1d, 0x0000, 0x0800 }, 3369 { 0x05, 0xffff, 0x2089 }, 3370 { 0x06, 0xffff, 0x5881 }, 3371 { 0x04, 0xffff, 0x854a }, 3372 { 0x01, 0xffff, 0x068b } 3373 }; 3374 int rg_saw_cnt; 3375 3376 rtl_ephy_init(tp, e_info_8168h_1); 3377 3378 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3379 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3380 3381 rtl_set_def_aspm_entry_latency(tp); 3382 3383 rtl_reset_packet_filter(tp); 3384 3385 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3386 3387 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3388 3389 rtl_disable_rxdvgate(tp); 3390 3391 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3392 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3393 3394 rtl8168_config_eee_mac(tp); 3395 3396 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3397 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3398 3399 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3400 3401 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3402 3403 rtl_pcie_state_l2l3_disable(tp); 3404 3405 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3406 if (rg_saw_cnt > 0) { 3407 u16 sw_cnt_1ms_ini; 3408 3409 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3410 sw_cnt_1ms_ini &= 0x0fff; 3411 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3412 } 3413 3414 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3415 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3416 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3417 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3418 3419 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3420 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3421 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3422 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3423 } 3424 3425 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3426 { 3427 rtl8168ep_stop_cmac(tp); 3428 3429 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3430 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3431 3432 rtl_set_def_aspm_entry_latency(tp); 3433 3434 rtl_reset_packet_filter(tp); 3435 3436 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3437 3438 rtl_disable_rxdvgate(tp); 3439 3440 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3441 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3442 3443 rtl8168_config_eee_mac(tp); 3444 3445 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3446 3447 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3448 3449 rtl_pcie_state_l2l3_disable(tp); 3450 } 3451 3452 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3453 { 3454 static const struct ephy_info e_info_8168ep_3[] = { 3455 { 0x00, 0x0000, 0x0080 }, 3456 { 0x0d, 0x0100, 0x0200 }, 3457 { 0x19, 0x8021, 0x0000 }, 3458 { 0x1e, 0x0000, 0x2000 }, 3459 }; 3460 3461 rtl_ephy_init(tp, e_info_8168ep_3); 3462 3463 rtl_hw_start_8168ep(tp); 3464 3465 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3466 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3467 3468 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3469 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3470 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3471 } 3472 3473 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3474 { 3475 static const struct ephy_info e_info_8117[] = { 3476 { 0x19, 0x0040, 0x1100 }, 3477 { 0x59, 0x0040, 0x1100 }, 3478 }; 3479 int rg_saw_cnt; 3480 3481 rtl8168ep_stop_cmac(tp); 3482 rtl_ephy_init(tp, e_info_8117); 3483 3484 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3485 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3486 3487 rtl_set_def_aspm_entry_latency(tp); 3488 3489 rtl_reset_packet_filter(tp); 3490 3491 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3492 3493 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3494 3495 rtl_disable_rxdvgate(tp); 3496 3497 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3498 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3499 3500 rtl8168_config_eee_mac(tp); 3501 3502 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3503 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3504 3505 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3506 3507 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3508 3509 rtl_pcie_state_l2l3_disable(tp); 3510 3511 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3512 if (rg_saw_cnt > 0) { 3513 u16 sw_cnt_1ms_ini; 3514 3515 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3516 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3517 } 3518 3519 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3520 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3521 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3522 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3523 3524 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3525 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3526 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3527 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3528 3529 /* firmware is for MAC only */ 3530 r8169_apply_firmware(tp); 3531 } 3532 3533 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3534 { 3535 static const struct ephy_info e_info_8102e_1[] = { 3536 { 0x01, 0, 0x6e65 }, 3537 { 0x02, 0, 0x091f }, 3538 { 0x03, 0, 0xc2f9 }, 3539 { 0x06, 0, 0xafb5 }, 3540 { 0x07, 0, 0x0e00 }, 3541 { 0x19, 0, 0xec80 }, 3542 { 0x01, 0, 0x2e65 }, 3543 { 0x01, 0, 0x6e65 } 3544 }; 3545 u8 cfg1; 3546 3547 rtl_set_def_aspm_entry_latency(tp); 3548 3549 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3550 3551 RTL_W8(tp, Config1, 3552 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3553 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3554 3555 cfg1 = RTL_R8(tp, Config1); 3556 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3557 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3558 3559 rtl_ephy_init(tp, e_info_8102e_1); 3560 } 3561 3562 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3563 { 3564 rtl_set_def_aspm_entry_latency(tp); 3565 3566 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3567 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3568 } 3569 3570 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3571 { 3572 rtl_hw_start_8102e_2(tp); 3573 3574 rtl_ephy_write(tp, 0x03, 0xc2f9); 3575 } 3576 3577 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3578 { 3579 static const struct ephy_info e_info_8401[] = { 3580 { 0x01, 0xffff, 0x6fe5 }, 3581 { 0x03, 0xffff, 0x0599 }, 3582 { 0x06, 0xffff, 0xaf25 }, 3583 { 0x07, 0xffff, 0x8e68 }, 3584 }; 3585 3586 rtl_ephy_init(tp, e_info_8401); 3587 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3588 } 3589 3590 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3591 { 3592 static const struct ephy_info e_info_8105e_1[] = { 3593 { 0x07, 0, 0x4000 }, 3594 { 0x19, 0, 0x0200 }, 3595 { 0x19, 0, 0x0020 }, 3596 { 0x1e, 0, 0x2000 }, 3597 { 0x03, 0, 0x0001 }, 3598 { 0x19, 0, 0x0100 }, 3599 { 0x19, 0, 0x0004 }, 3600 { 0x0a, 0, 0x0020 } 3601 }; 3602 3603 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3604 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3605 3606 /* Disable Early Tally Counter */ 3607 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3608 3609 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3610 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3611 3612 rtl_ephy_init(tp, e_info_8105e_1); 3613 3614 rtl_pcie_state_l2l3_disable(tp); 3615 } 3616 3617 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3618 { 3619 rtl_hw_start_8105e_1(tp); 3620 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3621 } 3622 3623 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3624 { 3625 static const struct ephy_info e_info_8402[] = { 3626 { 0x19, 0xffff, 0xff64 }, 3627 { 0x1e, 0, 0x4000 } 3628 }; 3629 3630 rtl_set_def_aspm_entry_latency(tp); 3631 3632 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3633 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3634 3635 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3636 3637 rtl_ephy_init(tp, e_info_8402); 3638 3639 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3640 rtl_reset_packet_filter(tp); 3641 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3642 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3643 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3644 3645 /* disable EEE */ 3646 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3647 3648 rtl_pcie_state_l2l3_disable(tp); 3649 } 3650 3651 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3652 { 3653 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3654 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3655 3656 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3657 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3658 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3659 3660 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3661 rtl_set_aspm_entry_latency(tp, 0x2f); 3662 3663 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3664 3665 /* disable EEE */ 3666 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3667 3668 rtl_pcie_state_l2l3_disable(tp); 3669 } 3670 3671 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3672 { 3673 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3674 } 3675 3676 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3677 { 3678 rtl_pcie_state_l2l3_disable(tp); 3679 3680 RTL_W16(tp, 0x382, 0x221b); 3681 RTL_W32(tp, RSS_CTRL_8125, 0); 3682 RTL_W16(tp, Q_NUM_CTRL_8125, 0); 3683 3684 /* disable UPS */ 3685 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3686 3687 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3688 3689 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3690 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3691 3692 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3693 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3694 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3695 3696 /* disable new tx descriptor format */ 3697 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3698 3699 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3700 tp->mac_version == RTL_GIGA_MAC_VER_66) 3701 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3702 3703 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3704 tp->mac_version == RTL_GIGA_MAC_VER_66) 3705 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3706 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3707 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3708 else 3709 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3710 3711 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3712 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3713 else 3714 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3715 3716 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3717 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3718 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3719 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3720 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3721 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3722 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3723 tp->mac_version == RTL_GIGA_MAC_VER_66) 3724 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3725 else 3726 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3727 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3728 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3729 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3730 3731 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3732 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3733 udelay(1); 3734 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3735 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3736 3737 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3738 3739 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3740 3741 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3742 rtl8125a_config_eee_mac(tp); 3743 else 3744 rtl8125b_config_eee_mac(tp); 3745 3746 rtl_disable_rxdvgate(tp); 3747 } 3748 3749 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3750 { 3751 static const struct ephy_info e_info_8125a_2[] = { 3752 { 0x04, 0xffff, 0xd000 }, 3753 { 0x0a, 0xffff, 0x8653 }, 3754 { 0x23, 0xffff, 0xab66 }, 3755 { 0x20, 0xffff, 0x9455 }, 3756 { 0x21, 0xffff, 0x99ff }, 3757 { 0x29, 0xffff, 0xfe04 }, 3758 3759 { 0x44, 0xffff, 0xd000 }, 3760 { 0x4a, 0xffff, 0x8653 }, 3761 { 0x63, 0xffff, 0xab66 }, 3762 { 0x60, 0xffff, 0x9455 }, 3763 { 0x61, 0xffff, 0x99ff }, 3764 { 0x69, 0xffff, 0xfe04 }, 3765 }; 3766 3767 rtl_set_def_aspm_entry_latency(tp); 3768 rtl_ephy_init(tp, e_info_8125a_2); 3769 rtl_hw_start_8125_common(tp); 3770 } 3771 3772 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3773 { 3774 static const struct ephy_info e_info_8125b[] = { 3775 { 0x0b, 0xffff, 0xa908 }, 3776 { 0x1e, 0xffff, 0x20eb }, 3777 { 0x4b, 0xffff, 0xa908 }, 3778 { 0x5e, 0xffff, 0x20eb }, 3779 { 0x22, 0x0030, 0x0020 }, 3780 { 0x62, 0x0030, 0x0020 }, 3781 }; 3782 3783 rtl_set_def_aspm_entry_latency(tp); 3784 rtl_ephy_init(tp, e_info_8125b); 3785 rtl_hw_start_8125_common(tp); 3786 } 3787 3788 static void rtl_hw_start_8125d(struct rtl8169_private *tp) 3789 { 3790 rtl_set_def_aspm_entry_latency(tp); 3791 rtl_hw_start_8125_common(tp); 3792 } 3793 3794 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3795 { 3796 rtl_set_def_aspm_entry_latency(tp); 3797 rtl_hw_start_8125_common(tp); 3798 } 3799 3800 static void rtl_hw_config(struct rtl8169_private *tp) 3801 { 3802 static const rtl_generic_fct hw_configs[] = { 3803 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3804 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3805 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3806 [RTL_GIGA_MAC_VER_10] = NULL, 3807 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3808 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3809 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3810 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3811 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3812 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3813 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3814 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3815 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3816 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3817 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3818 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3819 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3820 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3821 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3822 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3823 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3824 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3825 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3826 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3827 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3828 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3829 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3830 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3831 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3832 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3833 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3834 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3835 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3836 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3837 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3838 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3839 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3840 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3841 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3842 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, 3843 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3844 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a, 3845 }; 3846 3847 if (hw_configs[tp->mac_version]) 3848 hw_configs[tp->mac_version](tp); 3849 } 3850 3851 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3852 { 3853 int i; 3854 3855 RTL_W8(tp, INT_CFG0_8125, 0x00); 3856 3857 /* disable interrupt coalescing */ 3858 switch (tp->mac_version) { 3859 case RTL_GIGA_MAC_VER_61: 3860 case RTL_GIGA_MAC_VER_64: 3861 for (i = 0xa00; i < 0xb00; i += 4) 3862 RTL_W32(tp, i, 0); 3863 break; 3864 case RTL_GIGA_MAC_VER_63: 3865 case RTL_GIGA_MAC_VER_65: 3866 case RTL_GIGA_MAC_VER_66: 3867 for (i = 0xa00; i < 0xa80; i += 4) 3868 RTL_W32(tp, i, 0); 3869 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3870 break; 3871 default: 3872 break; 3873 } 3874 3875 /* enable extended tally counter */ 3876 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); 3877 3878 rtl_hw_config(tp); 3879 } 3880 3881 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3882 { 3883 if (rtl_is_8168evl_up(tp)) 3884 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3885 else 3886 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3887 3888 rtl_hw_config(tp); 3889 3890 /* disable interrupt coalescing */ 3891 RTL_W16(tp, IntrMitigate, 0x0000); 3892 } 3893 3894 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3895 { 3896 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3897 3898 tp->cp_cmd |= PCIMulRW; 3899 3900 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3901 tp->mac_version == RTL_GIGA_MAC_VER_03) 3902 tp->cp_cmd |= EnAnaPLL; 3903 3904 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3905 3906 rtl8169_set_magic_reg(tp); 3907 3908 /* disable interrupt coalescing */ 3909 RTL_W16(tp, IntrMitigate, 0x0000); 3910 } 3911 3912 static void rtl_hw_start(struct rtl8169_private *tp) 3913 { 3914 rtl_unlock_config_regs(tp); 3915 /* disable aspm and clock request before ephy access */ 3916 rtl_hw_aspm_clkreq_enable(tp, false); 3917 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3918 3919 rtl_set_eee_txidle_timer(tp); 3920 3921 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3922 rtl_hw_start_8169(tp); 3923 else if (rtl_is_8125(tp)) 3924 rtl_hw_start_8125(tp); 3925 else 3926 rtl_hw_start_8168(tp); 3927 3928 rtl_enable_exit_l1(tp); 3929 rtl_hw_aspm_clkreq_enable(tp, true); 3930 rtl_set_rx_max_size(tp); 3931 rtl_set_rx_tx_desc_registers(tp); 3932 rtl_lock_config_regs(tp); 3933 3934 rtl_jumbo_config(tp); 3935 3936 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3937 rtl_pci_commit(tp); 3938 3939 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3940 rtl_init_rxcfg(tp); 3941 rtl_set_tx_config_registers(tp); 3942 rtl_set_rx_config_features(tp, tp->dev->features); 3943 rtl_set_rx_mode(tp->dev); 3944 rtl_irq_enable(tp); 3945 } 3946 3947 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3948 { 3949 struct rtl8169_private *tp = netdev_priv(dev); 3950 3951 WRITE_ONCE(dev->mtu, new_mtu); 3952 netdev_update_features(dev); 3953 rtl_jumbo_config(tp); 3954 rtl_set_eee_txidle_timer(tp); 3955 3956 return 0; 3957 } 3958 3959 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3960 { 3961 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3962 3963 desc->opts2 = 0; 3964 /* Force memory writes to complete before releasing descriptor */ 3965 dma_wmb(); 3966 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3967 } 3968 3969 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3970 struct RxDesc *desc) 3971 { 3972 struct device *d = tp_to_dev(tp); 3973 int node = dev_to_node(d); 3974 dma_addr_t mapping; 3975 struct page *data; 3976 3977 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3978 if (!data) 3979 return NULL; 3980 3981 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3982 if (unlikely(dma_mapping_error(d, mapping))) { 3983 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3984 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3985 return NULL; 3986 } 3987 3988 desc->addr = cpu_to_le64(mapping); 3989 rtl8169_mark_to_asic(desc); 3990 3991 return data; 3992 } 3993 3994 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3995 { 3996 int i; 3997 3998 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3999 dma_unmap_page(tp_to_dev(tp), 4000 le64_to_cpu(tp->RxDescArray[i].addr), 4001 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4002 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4003 tp->Rx_databuff[i] = NULL; 4004 tp->RxDescArray[i].addr = 0; 4005 tp->RxDescArray[i].opts1 = 0; 4006 } 4007 } 4008 4009 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4010 { 4011 int i; 4012 4013 for (i = 0; i < NUM_RX_DESC; i++) { 4014 struct page *data; 4015 4016 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4017 if (!data) { 4018 rtl8169_rx_clear(tp); 4019 return -ENOMEM; 4020 } 4021 tp->Rx_databuff[i] = data; 4022 } 4023 4024 /* mark as last descriptor in the ring */ 4025 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4026 4027 return 0; 4028 } 4029 4030 static int rtl8169_init_ring(struct rtl8169_private *tp) 4031 { 4032 rtl8169_init_ring_indexes(tp); 4033 4034 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4035 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4036 4037 return rtl8169_rx_fill(tp); 4038 } 4039 4040 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4041 { 4042 struct ring_info *tx_skb = tp->tx_skb + entry; 4043 struct TxDesc *desc = tp->TxDescArray + entry; 4044 4045 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4046 DMA_TO_DEVICE); 4047 memset(desc, 0, sizeof(*desc)); 4048 memset(tx_skb, 0, sizeof(*tx_skb)); 4049 } 4050 4051 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4052 unsigned int n) 4053 { 4054 unsigned int i; 4055 4056 for (i = 0; i < n; i++) { 4057 unsigned int entry = (start + i) % NUM_TX_DESC; 4058 struct ring_info *tx_skb = tp->tx_skb + entry; 4059 unsigned int len = tx_skb->len; 4060 4061 if (len) { 4062 struct sk_buff *skb = tx_skb->skb; 4063 4064 rtl8169_unmap_tx_skb(tp, entry); 4065 if (skb) 4066 dev_consume_skb_any(skb); 4067 } 4068 } 4069 } 4070 4071 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4072 { 4073 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4074 netdev_reset_queue(tp->dev); 4075 } 4076 4077 static void rtl8169_cleanup(struct rtl8169_private *tp) 4078 { 4079 napi_disable(&tp->napi); 4080 4081 /* Give a racing hard_start_xmit a few cycles to complete. */ 4082 synchronize_net(); 4083 4084 /* Disable interrupts */ 4085 rtl8169_irq_mask_and_ack(tp); 4086 4087 rtl_rx_close(tp); 4088 4089 switch (tp->mac_version) { 4090 case RTL_GIGA_MAC_VER_28: 4091 case RTL_GIGA_MAC_VER_31: 4092 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4093 break; 4094 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4095 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4096 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4097 break; 4098 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 4099 rtl_enable_rxdvgate(tp); 4100 fsleep(2000); 4101 break; 4102 default: 4103 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4104 fsleep(100); 4105 break; 4106 } 4107 4108 rtl_hw_reset(tp); 4109 4110 rtl8169_tx_clear(tp); 4111 rtl8169_init_ring_indexes(tp); 4112 } 4113 4114 static void rtl_reset_work(struct rtl8169_private *tp) 4115 { 4116 int i; 4117 4118 netif_stop_queue(tp->dev); 4119 4120 rtl8169_cleanup(tp); 4121 4122 for (i = 0; i < NUM_RX_DESC; i++) 4123 rtl8169_mark_to_asic(tp->RxDescArray + i); 4124 4125 napi_enable(&tp->napi); 4126 rtl_hw_start(tp); 4127 } 4128 4129 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4130 { 4131 struct rtl8169_private *tp = netdev_priv(dev); 4132 4133 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4134 } 4135 4136 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4137 void *addr, unsigned int entry, bool desc_own) 4138 { 4139 struct TxDesc *txd = tp->TxDescArray + entry; 4140 struct device *d = tp_to_dev(tp); 4141 dma_addr_t mapping; 4142 u32 opts1; 4143 int ret; 4144 4145 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4146 ret = dma_mapping_error(d, mapping); 4147 if (unlikely(ret)) { 4148 if (net_ratelimit()) 4149 netdev_err(tp->dev, "Failed to map TX data!\n"); 4150 return ret; 4151 } 4152 4153 txd->addr = cpu_to_le64(mapping); 4154 txd->opts2 = cpu_to_le32(opts[1]); 4155 4156 opts1 = opts[0] | len; 4157 if (entry == NUM_TX_DESC - 1) 4158 opts1 |= RingEnd; 4159 if (desc_own) 4160 opts1 |= DescOwn; 4161 txd->opts1 = cpu_to_le32(opts1); 4162 4163 tp->tx_skb[entry].len = len; 4164 4165 return 0; 4166 } 4167 4168 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4169 const u32 *opts, unsigned int entry) 4170 { 4171 struct skb_shared_info *info = skb_shinfo(skb); 4172 unsigned int cur_frag; 4173 4174 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4175 const skb_frag_t *frag = info->frags + cur_frag; 4176 void *addr = skb_frag_address(frag); 4177 u32 len = skb_frag_size(frag); 4178 4179 entry = (entry + 1) % NUM_TX_DESC; 4180 4181 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4182 goto err_out; 4183 } 4184 4185 return 0; 4186 4187 err_out: 4188 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4189 return -EIO; 4190 } 4191 4192 static bool rtl_skb_is_udp(struct sk_buff *skb) 4193 { 4194 int no = skb_network_offset(skb); 4195 struct ipv6hdr *i6h, _i6h; 4196 struct iphdr *ih, _ih; 4197 4198 switch (vlan_get_protocol(skb)) { 4199 case htons(ETH_P_IP): 4200 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4201 return ih && ih->protocol == IPPROTO_UDP; 4202 case htons(ETH_P_IPV6): 4203 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4204 return i6h && i6h->nexthdr == IPPROTO_UDP; 4205 default: 4206 return false; 4207 } 4208 } 4209 4210 #define RTL_MIN_PATCH_LEN 47 4211 4212 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4213 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4214 struct sk_buff *skb) 4215 { 4216 unsigned int padto = 0, len = skb->len; 4217 4218 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) && 4219 skb_transport_header_was_set(skb)) { 4220 unsigned int trans_data_len = skb_tail_pointer(skb) - 4221 skb_transport_header(skb); 4222 4223 if (trans_data_len >= offsetof(struct udphdr, len) && 4224 trans_data_len < RTL_MIN_PATCH_LEN) { 4225 u16 dest = ntohs(udp_hdr(skb)->dest); 4226 4227 /* dest is a standard PTP port */ 4228 if (dest == 319 || dest == 320) 4229 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4230 } 4231 4232 if (trans_data_len < sizeof(struct udphdr)) 4233 padto = max_t(unsigned int, padto, 4234 len + sizeof(struct udphdr) - trans_data_len); 4235 } 4236 4237 return padto; 4238 } 4239 4240 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4241 struct sk_buff *skb) 4242 { 4243 unsigned int padto = 0; 4244 4245 switch (tp->mac_version) { 4246 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 4247 padto = rtl8125_quirk_udp_padto(tp, skb); 4248 break; 4249 default: 4250 break; 4251 } 4252 4253 switch (tp->mac_version) { 4254 case RTL_GIGA_MAC_VER_34: 4255 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 4256 padto = max_t(unsigned int, padto, ETH_ZLEN); 4257 break; 4258 default: 4259 break; 4260 } 4261 4262 return padto; 4263 } 4264 4265 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4266 { 4267 u32 mss = skb_shinfo(skb)->gso_size; 4268 4269 if (mss) { 4270 opts[0] |= TD_LSO; 4271 opts[0] |= mss << TD0_MSS_SHIFT; 4272 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4273 const struct iphdr *ip = ip_hdr(skb); 4274 4275 if (ip->protocol == IPPROTO_TCP) 4276 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4277 else if (ip->protocol == IPPROTO_UDP) 4278 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4279 else 4280 WARN_ON_ONCE(1); 4281 } 4282 } 4283 4284 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4285 struct sk_buff *skb, u32 *opts) 4286 { 4287 struct skb_shared_info *shinfo = skb_shinfo(skb); 4288 u32 mss = shinfo->gso_size; 4289 4290 if (mss) { 4291 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4292 opts[0] |= TD1_GTSENV4; 4293 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4294 if (skb_cow_head(skb, 0)) 4295 return false; 4296 4297 tcp_v6_gso_csum_prep(skb); 4298 opts[0] |= TD1_GTSENV6; 4299 } else { 4300 WARN_ON_ONCE(1); 4301 } 4302 4303 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4304 opts[1] |= mss << TD1_MSS_SHIFT; 4305 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4306 u8 ip_protocol; 4307 4308 switch (vlan_get_protocol(skb)) { 4309 case htons(ETH_P_IP): 4310 opts[1] |= TD1_IPv4_CS; 4311 ip_protocol = ip_hdr(skb)->protocol; 4312 break; 4313 4314 case htons(ETH_P_IPV6): 4315 opts[1] |= TD1_IPv6_CS; 4316 ip_protocol = ipv6_hdr(skb)->nexthdr; 4317 break; 4318 4319 default: 4320 ip_protocol = IPPROTO_RAW; 4321 break; 4322 } 4323 4324 if (ip_protocol == IPPROTO_TCP) 4325 opts[1] |= TD1_TCP_CS; 4326 else if (ip_protocol == IPPROTO_UDP) 4327 opts[1] |= TD1_UDP_CS; 4328 else 4329 WARN_ON_ONCE(1); 4330 4331 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4332 } else { 4333 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4334 4335 /* skb_padto would free the skb on error */ 4336 return !__skb_put_padto(skb, padto, false); 4337 } 4338 4339 return true; 4340 } 4341 4342 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4343 { 4344 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4345 } 4346 4347 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4348 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4349 { 4350 switch (tp->mac_version) { 4351 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4352 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4353 return false; 4354 default: 4355 return true; 4356 } 4357 } 4358 4359 static void rtl8169_doorbell(struct rtl8169_private *tp) 4360 { 4361 if (rtl_is_8125(tp)) 4362 RTL_W16(tp, TxPoll_8125, BIT(0)); 4363 else 4364 RTL_W8(tp, TxPoll, NPQ); 4365 } 4366 4367 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4368 struct net_device *dev) 4369 { 4370 struct rtl8169_private *tp = netdev_priv(dev); 4371 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4372 struct TxDesc *txd_first, *txd_last; 4373 bool stop_queue, door_bell; 4374 unsigned int frags; 4375 u32 opts[2]; 4376 4377 if (unlikely(!rtl_tx_slots_avail(tp))) { 4378 if (net_ratelimit()) 4379 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4380 netif_stop_queue(dev); 4381 return NETDEV_TX_BUSY; 4382 } 4383 4384 opts[1] = rtl8169_tx_vlan_tag(skb); 4385 opts[0] = 0; 4386 4387 if (!rtl_chip_supports_csum_v2(tp)) 4388 rtl8169_tso_csum_v1(skb, opts); 4389 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4390 goto err_dma_0; 4391 4392 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4393 entry, false))) 4394 goto err_dma_0; 4395 4396 txd_first = tp->TxDescArray + entry; 4397 4398 frags = skb_shinfo(skb)->nr_frags; 4399 if (frags) { 4400 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4401 goto err_dma_1; 4402 entry = (entry + frags) % NUM_TX_DESC; 4403 } 4404 4405 txd_last = tp->TxDescArray + entry; 4406 txd_last->opts1 |= cpu_to_le32(LastFrag); 4407 tp->tx_skb[entry].skb = skb; 4408 4409 skb_tx_timestamp(skb); 4410 4411 /* Force memory writes to complete before releasing descriptor */ 4412 dma_wmb(); 4413 4414 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4415 4416 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4417 4418 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4419 smp_wmb(); 4420 4421 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4422 4423 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4424 R8169_TX_STOP_THRS, 4425 R8169_TX_START_THRS); 4426 if (door_bell || stop_queue) 4427 rtl8169_doorbell(tp); 4428 4429 return NETDEV_TX_OK; 4430 4431 err_dma_1: 4432 rtl8169_unmap_tx_skb(tp, entry); 4433 err_dma_0: 4434 dev_kfree_skb_any(skb); 4435 dev->stats.tx_dropped++; 4436 return NETDEV_TX_OK; 4437 } 4438 4439 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4440 { 4441 struct skb_shared_info *info = skb_shinfo(skb); 4442 unsigned int nr_frags = info->nr_frags; 4443 4444 if (!nr_frags) 4445 return UINT_MAX; 4446 4447 return skb_frag_size(info->frags + nr_frags - 1); 4448 } 4449 4450 /* Workaround for hw issues with TSO on RTL8168evl */ 4451 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4452 netdev_features_t features) 4453 { 4454 /* IPv4 header has options field */ 4455 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4456 ip_hdrlen(skb) > sizeof(struct iphdr)) 4457 features &= ~NETIF_F_ALL_TSO; 4458 4459 /* IPv4 TCP header has options field */ 4460 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4461 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4462 features &= ~NETIF_F_ALL_TSO; 4463 4464 else if (rtl_last_frag_len(skb) <= 6) 4465 features &= ~NETIF_F_ALL_TSO; 4466 4467 return features; 4468 } 4469 4470 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4471 struct net_device *dev, 4472 netdev_features_t features) 4473 { 4474 struct rtl8169_private *tp = netdev_priv(dev); 4475 4476 if (skb_is_gso(skb)) { 4477 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4478 features = rtl8168evl_fix_tso(skb, features); 4479 4480 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4481 rtl_chip_supports_csum_v2(tp)) 4482 features &= ~NETIF_F_ALL_TSO; 4483 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4484 /* work around hw bug on some chip versions */ 4485 if (skb->len < ETH_ZLEN) 4486 features &= ~NETIF_F_CSUM_MASK; 4487 4488 if (rtl_quirk_packet_padto(tp, skb)) 4489 features &= ~NETIF_F_CSUM_MASK; 4490 4491 if (skb_transport_offset(skb) > TCPHO_MAX && 4492 rtl_chip_supports_csum_v2(tp)) 4493 features &= ~NETIF_F_CSUM_MASK; 4494 } 4495 4496 return vlan_features_check(skb, features); 4497 } 4498 4499 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4500 { 4501 struct rtl8169_private *tp = netdev_priv(dev); 4502 struct pci_dev *pdev = tp->pci_dev; 4503 int pci_status_errs; 4504 u16 pci_cmd; 4505 4506 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4507 4508 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4509 4510 if (net_ratelimit()) 4511 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4512 pci_cmd, pci_status_errs); 4513 4514 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4515 } 4516 4517 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4518 int budget) 4519 { 4520 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4521 struct sk_buff *skb; 4522 4523 dirty_tx = tp->dirty_tx; 4524 4525 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4526 unsigned int entry = dirty_tx % NUM_TX_DESC; 4527 u32 status; 4528 4529 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4530 if (status & DescOwn) 4531 break; 4532 4533 skb = tp->tx_skb[entry].skb; 4534 rtl8169_unmap_tx_skb(tp, entry); 4535 4536 if (skb) { 4537 pkts_compl++; 4538 bytes_compl += skb->len; 4539 napi_consume_skb(skb, budget); 4540 } 4541 dirty_tx++; 4542 } 4543 4544 if (tp->dirty_tx != dirty_tx) { 4545 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4546 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4547 4548 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4549 rtl_tx_slots_avail(tp), 4550 R8169_TX_START_THRS); 4551 /* 4552 * 8168 hack: TxPoll requests are lost when the Tx packets are 4553 * too close. Let's kick an extra TxPoll request when a burst 4554 * of start_xmit activity is detected (if it is not detected, 4555 * it is slow enough). -- FR 4556 * If skb is NULL then we come here again once a tx irq is 4557 * triggered after the last fragment is marked transmitted. 4558 */ 4559 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4560 rtl8169_doorbell(tp); 4561 } 4562 } 4563 4564 static inline int rtl8169_fragmented_frame(u32 status) 4565 { 4566 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4567 } 4568 4569 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4570 { 4571 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4572 4573 if (status == RxProtoTCP || status == RxProtoUDP) 4574 skb->ip_summed = CHECKSUM_UNNECESSARY; 4575 else 4576 skb_checksum_none_assert(skb); 4577 } 4578 4579 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4580 { 4581 struct device *d = tp_to_dev(tp); 4582 int count; 4583 4584 for (count = 0; count < budget; count++, tp->cur_rx++) { 4585 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4586 struct RxDesc *desc = tp->RxDescArray + entry; 4587 struct sk_buff *skb; 4588 const void *rx_buf; 4589 dma_addr_t addr; 4590 u32 status; 4591 4592 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4593 if (status & DescOwn) 4594 break; 4595 4596 /* This barrier is needed to keep us from reading 4597 * any other fields out of the Rx descriptor until 4598 * we know the status of DescOwn 4599 */ 4600 dma_rmb(); 4601 4602 if (unlikely(status & RxRES)) { 4603 if (net_ratelimit()) 4604 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4605 status); 4606 dev->stats.rx_errors++; 4607 if (status & (RxRWT | RxRUNT)) 4608 dev->stats.rx_length_errors++; 4609 if (status & RxCRC) 4610 dev->stats.rx_crc_errors++; 4611 4612 if (!(dev->features & NETIF_F_RXALL)) 4613 goto release_descriptor; 4614 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4615 goto release_descriptor; 4616 } 4617 4618 pkt_size = status & GENMASK(13, 0); 4619 if (likely(!(dev->features & NETIF_F_RXFCS))) 4620 pkt_size -= ETH_FCS_LEN; 4621 4622 /* The driver does not support incoming fragmented frames. 4623 * They are seen as a symptom of over-mtu sized frames. 4624 */ 4625 if (unlikely(rtl8169_fragmented_frame(status))) { 4626 dev->stats.rx_dropped++; 4627 dev->stats.rx_length_errors++; 4628 goto release_descriptor; 4629 } 4630 4631 skb = napi_alloc_skb(&tp->napi, pkt_size); 4632 if (unlikely(!skb)) { 4633 dev->stats.rx_dropped++; 4634 goto release_descriptor; 4635 } 4636 4637 addr = le64_to_cpu(desc->addr); 4638 rx_buf = page_address(tp->Rx_databuff[entry]); 4639 4640 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4641 prefetch(rx_buf); 4642 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4643 skb->tail += pkt_size; 4644 skb->len = pkt_size; 4645 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4646 4647 rtl8169_rx_csum(skb, status); 4648 skb->protocol = eth_type_trans(skb, dev); 4649 4650 rtl8169_rx_vlan_tag(desc, skb); 4651 4652 if (skb->pkt_type == PACKET_MULTICAST) 4653 dev->stats.multicast++; 4654 4655 napi_gro_receive(&tp->napi, skb); 4656 4657 dev_sw_netstats_rx_add(dev, pkt_size); 4658 release_descriptor: 4659 rtl8169_mark_to_asic(desc); 4660 } 4661 4662 return count; 4663 } 4664 4665 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4666 { 4667 struct rtl8169_private *tp = dev_instance; 4668 u32 status = rtl_get_events(tp); 4669 4670 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4671 return IRQ_NONE; 4672 4673 /* At least RTL8168fp may unexpectedly set the SYSErr bit */ 4674 if (unlikely(status & SYSErr && 4675 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { 4676 rtl8169_pcierr_interrupt(tp->dev); 4677 goto out; 4678 } 4679 4680 if (status & LinkChg) 4681 phy_mac_interrupt(tp->phydev); 4682 4683 if (unlikely(status & RxFIFOOver && 4684 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4685 netif_stop_queue(tp->dev); 4686 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4687 } 4688 4689 rtl_irq_disable(tp); 4690 napi_schedule(&tp->napi); 4691 out: 4692 rtl_ack_events(tp, status); 4693 4694 return IRQ_HANDLED; 4695 } 4696 4697 static void rtl_task(struct work_struct *work) 4698 { 4699 struct rtl8169_private *tp = 4700 container_of(work, struct rtl8169_private, wk.work); 4701 int ret; 4702 4703 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4704 /* if chip isn't accessible, reset bus to revive it */ 4705 if (RTL_R32(tp, TxConfig) == ~0) { 4706 ret = pci_reset_bus(tp->pci_dev); 4707 if (ret < 0) { 4708 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4709 netif_device_detach(tp->dev); 4710 return; 4711 } 4712 } 4713 4714 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4715 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4716 PCIE_LINK_STATE_L0S); 4717 if (!ret) 4718 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4719 goto reset; 4720 } 4721 4722 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4723 reset: 4724 rtl_reset_work(tp); 4725 netif_wake_queue(tp->dev); 4726 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4727 rtl_reset_work(tp); 4728 } 4729 } 4730 4731 static int rtl8169_poll(struct napi_struct *napi, int budget) 4732 { 4733 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4734 struct net_device *dev = tp->dev; 4735 int work_done; 4736 4737 rtl_tx(dev, tp, budget); 4738 4739 work_done = rtl_rx(dev, tp, budget); 4740 4741 if (work_done < budget && napi_complete_done(napi, work_done)) 4742 rtl_irq_enable(tp); 4743 4744 return work_done; 4745 } 4746 4747 static void r8169_phylink_handler(struct net_device *ndev) 4748 { 4749 struct rtl8169_private *tp = netdev_priv(ndev); 4750 struct device *d = tp_to_dev(tp); 4751 4752 if (netif_carrier_ok(ndev)) { 4753 rtl_link_chg_patch(tp); 4754 pm_request_resume(d); 4755 } else { 4756 pm_runtime_idle(d); 4757 } 4758 4759 phy_print_status(tp->phydev); 4760 } 4761 4762 static int r8169_phy_connect(struct rtl8169_private *tp) 4763 { 4764 struct phy_device *phydev = tp->phydev; 4765 phy_interface_t phy_mode; 4766 int ret; 4767 4768 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4769 PHY_INTERFACE_MODE_MII; 4770 4771 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4772 phy_mode); 4773 if (ret) 4774 return ret; 4775 4776 if (!tp->supports_gmii) 4777 phy_set_max_speed(phydev, SPEED_100); 4778 4779 phy_attached_info(phydev); 4780 4781 return 0; 4782 } 4783 4784 static void rtl8169_down(struct rtl8169_private *tp) 4785 { 4786 disable_work_sync(&tp->wk.work); 4787 /* Clear all task flags */ 4788 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4789 4790 phy_stop(tp->phydev); 4791 4792 rtl8169_update_counters(tp); 4793 4794 pci_clear_master(tp->pci_dev); 4795 rtl_pci_commit(tp); 4796 4797 rtl8169_cleanup(tp); 4798 rtl_disable_exit_l1(tp); 4799 rtl_prepare_power_down(tp); 4800 4801 if (tp->dash_type != RTL_DASH_NONE) 4802 rtl8168_driver_stop(tp); 4803 } 4804 4805 static void rtl8169_up(struct rtl8169_private *tp) 4806 { 4807 if (tp->dash_type != RTL_DASH_NONE) 4808 rtl8168_driver_start(tp); 4809 4810 pci_set_master(tp->pci_dev); 4811 phy_init_hw(tp->phydev); 4812 phy_resume(tp->phydev); 4813 rtl8169_init_phy(tp); 4814 napi_enable(&tp->napi); 4815 enable_work(&tp->wk.work); 4816 rtl_reset_work(tp); 4817 4818 phy_start(tp->phydev); 4819 } 4820 4821 static int rtl8169_close(struct net_device *dev) 4822 { 4823 struct rtl8169_private *tp = netdev_priv(dev); 4824 struct pci_dev *pdev = tp->pci_dev; 4825 4826 pm_runtime_get_sync(&pdev->dev); 4827 4828 netif_stop_queue(dev); 4829 rtl8169_down(tp); 4830 rtl8169_rx_clear(tp); 4831 4832 free_irq(tp->irq, tp); 4833 4834 phy_disconnect(tp->phydev); 4835 4836 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4837 tp->RxPhyAddr); 4838 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4839 tp->TxPhyAddr); 4840 tp->TxDescArray = NULL; 4841 tp->RxDescArray = NULL; 4842 4843 pm_runtime_put_sync(&pdev->dev); 4844 4845 return 0; 4846 } 4847 4848 #ifdef CONFIG_NET_POLL_CONTROLLER 4849 static void rtl8169_netpoll(struct net_device *dev) 4850 { 4851 struct rtl8169_private *tp = netdev_priv(dev); 4852 4853 rtl8169_interrupt(tp->irq, tp); 4854 } 4855 #endif 4856 4857 static int rtl_open(struct net_device *dev) 4858 { 4859 struct rtl8169_private *tp = netdev_priv(dev); 4860 struct pci_dev *pdev = tp->pci_dev; 4861 unsigned long irqflags; 4862 int retval = -ENOMEM; 4863 4864 pm_runtime_get_sync(&pdev->dev); 4865 4866 /* 4867 * Rx and Tx descriptors needs 256 bytes alignment. 4868 * dma_alloc_coherent provides more. 4869 */ 4870 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4871 &tp->TxPhyAddr, GFP_KERNEL); 4872 if (!tp->TxDescArray) 4873 goto out; 4874 4875 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4876 &tp->RxPhyAddr, GFP_KERNEL); 4877 if (!tp->RxDescArray) 4878 goto err_free_tx_0; 4879 4880 retval = rtl8169_init_ring(tp); 4881 if (retval < 0) 4882 goto err_free_rx_1; 4883 4884 rtl_request_firmware(tp); 4885 4886 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4887 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4888 if (retval < 0) 4889 goto err_release_fw_2; 4890 4891 retval = r8169_phy_connect(tp); 4892 if (retval) 4893 goto err_free_irq; 4894 4895 rtl8169_up(tp); 4896 rtl8169_init_counter_offsets(tp); 4897 netif_start_queue(dev); 4898 out: 4899 pm_runtime_put_sync(&pdev->dev); 4900 4901 return retval; 4902 4903 err_free_irq: 4904 free_irq(tp->irq, tp); 4905 err_release_fw_2: 4906 rtl_release_firmware(tp); 4907 rtl8169_rx_clear(tp); 4908 err_free_rx_1: 4909 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4910 tp->RxPhyAddr); 4911 tp->RxDescArray = NULL; 4912 err_free_tx_0: 4913 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4914 tp->TxPhyAddr); 4915 tp->TxDescArray = NULL; 4916 goto out; 4917 } 4918 4919 static void 4920 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4921 { 4922 struct rtl8169_private *tp = netdev_priv(dev); 4923 struct pci_dev *pdev = tp->pci_dev; 4924 struct rtl8169_counters *counters = tp->counters; 4925 4926 pm_runtime_get_noresume(&pdev->dev); 4927 4928 netdev_stats_to_stats64(stats, &dev->stats); 4929 dev_fetch_sw_netstats(stats, dev->tstats); 4930 4931 /* 4932 * Fetch additional counter values missing in stats collected by driver 4933 * from tally counters. 4934 */ 4935 if (pm_runtime_active(&pdev->dev)) 4936 rtl8169_update_counters(tp); 4937 4938 /* 4939 * Subtract values fetched during initalization. 4940 * See rtl8169_init_counter_offsets for a description why we do that. 4941 */ 4942 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4943 le64_to_cpu(tp->tc_offset.tx_errors); 4944 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4945 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4946 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4947 le16_to_cpu(tp->tc_offset.tx_aborted); 4948 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4949 le16_to_cpu(tp->tc_offset.rx_missed); 4950 4951 pm_runtime_put_noidle(&pdev->dev); 4952 } 4953 4954 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4955 { 4956 netif_device_detach(tp->dev); 4957 4958 if (netif_running(tp->dev)) 4959 rtl8169_down(tp); 4960 } 4961 4962 static int rtl8169_runtime_resume(struct device *dev) 4963 { 4964 struct rtl8169_private *tp = dev_get_drvdata(dev); 4965 4966 rtl_rar_set(tp, tp->dev->dev_addr); 4967 __rtl8169_set_wol(tp, tp->saved_wolopts); 4968 4969 if (tp->TxDescArray) 4970 rtl8169_up(tp); 4971 4972 netif_device_attach(tp->dev); 4973 4974 return 0; 4975 } 4976 4977 static int rtl8169_suspend(struct device *device) 4978 { 4979 struct rtl8169_private *tp = dev_get_drvdata(device); 4980 4981 rtnl_lock(); 4982 rtl8169_net_suspend(tp); 4983 if (!device_may_wakeup(tp_to_dev(tp))) 4984 clk_disable_unprepare(tp->clk); 4985 rtnl_unlock(); 4986 4987 return 0; 4988 } 4989 4990 static int rtl8169_resume(struct device *device) 4991 { 4992 struct rtl8169_private *tp = dev_get_drvdata(device); 4993 4994 if (!device_may_wakeup(tp_to_dev(tp))) 4995 clk_prepare_enable(tp->clk); 4996 4997 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4998 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4999 rtl_init_rxcfg(tp); 5000 5001 return rtl8169_runtime_resume(device); 5002 } 5003 5004 static int rtl8169_runtime_suspend(struct device *device) 5005 { 5006 struct rtl8169_private *tp = dev_get_drvdata(device); 5007 5008 if (!tp->TxDescArray) { 5009 netif_device_detach(tp->dev); 5010 return 0; 5011 } 5012 5013 rtnl_lock(); 5014 __rtl8169_set_wol(tp, WAKE_PHY); 5015 rtl8169_net_suspend(tp); 5016 rtnl_unlock(); 5017 5018 return 0; 5019 } 5020 5021 static int rtl8169_runtime_idle(struct device *device) 5022 { 5023 struct rtl8169_private *tp = dev_get_drvdata(device); 5024 5025 if (tp->dash_enabled) 5026 return -EBUSY; 5027 5028 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5029 pm_schedule_suspend(device, 10000); 5030 5031 return -EBUSY; 5032 } 5033 5034 static const struct dev_pm_ops rtl8169_pm_ops = { 5035 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5036 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5037 rtl8169_runtime_idle) 5038 }; 5039 5040 static void rtl_shutdown(struct pci_dev *pdev) 5041 { 5042 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5043 5044 rtnl_lock(); 5045 rtl8169_net_suspend(tp); 5046 rtnl_unlock(); 5047 5048 /* Restore original MAC address */ 5049 rtl_rar_set(tp, tp->dev->perm_addr); 5050 5051 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5052 pci_wake_from_d3(pdev, tp->saved_wolopts); 5053 pci_set_power_state(pdev, PCI_D3hot); 5054 } 5055 } 5056 5057 static void rtl_remove_one(struct pci_dev *pdev) 5058 { 5059 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5060 5061 if (pci_dev_run_wake(pdev)) 5062 pm_runtime_get_noresume(&pdev->dev); 5063 5064 disable_work_sync(&tp->wk.work); 5065 5066 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5067 r8169_remove_leds(tp->leds); 5068 5069 unregister_netdev(tp->dev); 5070 5071 if (tp->dash_type != RTL_DASH_NONE) 5072 rtl8168_driver_stop(tp); 5073 5074 rtl_release_firmware(tp); 5075 5076 /* restore original MAC address */ 5077 rtl_rar_set(tp, tp->dev->perm_addr); 5078 } 5079 5080 static const struct net_device_ops rtl_netdev_ops = { 5081 .ndo_open = rtl_open, 5082 .ndo_stop = rtl8169_close, 5083 .ndo_get_stats64 = rtl8169_get_stats64, 5084 .ndo_start_xmit = rtl8169_start_xmit, 5085 .ndo_features_check = rtl8169_features_check, 5086 .ndo_tx_timeout = rtl8169_tx_timeout, 5087 .ndo_validate_addr = eth_validate_addr, 5088 .ndo_change_mtu = rtl8169_change_mtu, 5089 .ndo_fix_features = rtl8169_fix_features, 5090 .ndo_set_features = rtl8169_set_features, 5091 .ndo_set_mac_address = rtl_set_mac_address, 5092 .ndo_eth_ioctl = phy_do_ioctl_running, 5093 .ndo_set_rx_mode = rtl_set_rx_mode, 5094 #ifdef CONFIG_NET_POLL_CONTROLLER 5095 .ndo_poll_controller = rtl8169_netpoll, 5096 #endif 5097 5098 }; 5099 5100 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5101 { 5102 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5103 5104 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5105 tp->irq_mask |= SYSErr | RxFIFOOver; 5106 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5107 /* special workaround needed */ 5108 tp->irq_mask |= RxFIFOOver; 5109 } 5110 5111 static int rtl_alloc_irq(struct rtl8169_private *tp) 5112 { 5113 unsigned int flags; 5114 5115 switch (tp->mac_version) { 5116 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5117 rtl_unlock_config_regs(tp); 5118 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5119 rtl_lock_config_regs(tp); 5120 fallthrough; 5121 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5122 flags = PCI_IRQ_INTX; 5123 break; 5124 default: 5125 flags = PCI_IRQ_ALL_TYPES; 5126 break; 5127 } 5128 5129 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5130 } 5131 5132 static void rtl_read_mac_address(struct rtl8169_private *tp, 5133 u8 mac_addr[ETH_ALEN]) 5134 { 5135 /* Get MAC address */ 5136 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5137 u32 value; 5138 5139 value = rtl_eri_read(tp, 0xe0); 5140 put_unaligned_le32(value, mac_addr); 5141 value = rtl_eri_read(tp, 0xe4); 5142 put_unaligned_le16(value, mac_addr + 4); 5143 } else if (rtl_is_8125(tp)) { 5144 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5145 } 5146 } 5147 5148 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5149 { 5150 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5151 } 5152 5153 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5154 { 5155 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5156 } 5157 5158 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5159 { 5160 struct rtl8169_private *tp = mii_bus->priv; 5161 5162 if (phyaddr > 0) 5163 return -ENODEV; 5164 5165 return rtl_readphy(tp, phyreg); 5166 } 5167 5168 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5169 int phyreg, u16 val) 5170 { 5171 struct rtl8169_private *tp = mii_bus->priv; 5172 5173 if (phyaddr > 0) 5174 return -ENODEV; 5175 5176 rtl_writephy(tp, phyreg, val); 5177 5178 return 0; 5179 } 5180 5181 static int r8169_mdio_register(struct rtl8169_private *tp) 5182 { 5183 struct pci_dev *pdev = tp->pci_dev; 5184 struct mii_bus *new_bus; 5185 int ret; 5186 5187 /* On some boards with this chip version the BIOS is buggy and misses 5188 * to reset the PHY page selector. This results in the PHY ID read 5189 * accessing registers on a different page, returning a more or 5190 * less random value. Fix this by resetting the page selector first. 5191 */ 5192 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5193 tp->mac_version == RTL_GIGA_MAC_VER_26) 5194 r8169_mdio_write(tp, 0x1f, 0); 5195 5196 new_bus = devm_mdiobus_alloc(&pdev->dev); 5197 if (!new_bus) 5198 return -ENOMEM; 5199 5200 new_bus->name = "r8169"; 5201 new_bus->priv = tp; 5202 new_bus->parent = &pdev->dev; 5203 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5204 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5205 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5206 5207 new_bus->read = r8169_mdio_read_reg; 5208 new_bus->write = r8169_mdio_write_reg; 5209 5210 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5211 if (ret) 5212 return ret; 5213 5214 tp->phydev = mdiobus_get_phy(new_bus, 0); 5215 if (!tp->phydev) { 5216 return -ENODEV; 5217 } else if (!tp->phydev->drv) { 5218 /* Most chip versions fail with the genphy driver. 5219 * Therefore ensure that the dedicated PHY driver is loaded. 5220 */ 5221 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5222 tp->phydev->phy_id); 5223 return -EUNATCH; 5224 } 5225 5226 tp->phydev->mac_managed_pm = true; 5227 if (rtl_supports_eee(tp)) 5228 phy_support_eee(tp->phydev); 5229 phy_support_asym_pause(tp->phydev); 5230 5231 /* mimic behavior of r8125/r8126 vendor drivers */ 5232 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 5233 phy_set_eee_broken(tp->phydev, 5234 ETHTOOL_LINK_MODE_2500baseT_Full_BIT); 5235 phy_set_eee_broken(tp->phydev, ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 5236 5237 /* PHY will be woken up in rtl_open() */ 5238 phy_suspend(tp->phydev); 5239 5240 return 0; 5241 } 5242 5243 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5244 { 5245 rtl_enable_rxdvgate(tp); 5246 5247 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5248 msleep(1); 5249 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5250 5251 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5252 r8168g_wait_ll_share_fifo_ready(tp); 5253 5254 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5255 r8168g_wait_ll_share_fifo_ready(tp); 5256 } 5257 5258 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5259 { 5260 rtl_enable_rxdvgate(tp); 5261 5262 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5263 msleep(1); 5264 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5265 5266 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5267 r8168g_wait_ll_share_fifo_ready(tp); 5268 5269 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5270 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5271 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5272 r8168g_wait_ll_share_fifo_ready(tp); 5273 } 5274 5275 static void rtl_hw_initialize(struct rtl8169_private *tp) 5276 { 5277 switch (tp->mac_version) { 5278 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5279 rtl8168ep_stop_cmac(tp); 5280 fallthrough; 5281 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5282 rtl_hw_init_8168g(tp); 5283 break; 5284 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 5285 rtl_hw_init_8125(tp); 5286 break; 5287 default: 5288 break; 5289 } 5290 } 5291 5292 static int rtl_jumbo_max(struct rtl8169_private *tp) 5293 { 5294 /* Non-GBit versions don't support jumbo frames */ 5295 if (!tp->supports_gmii) 5296 return 0; 5297 5298 switch (tp->mac_version) { 5299 /* RTL8169 */ 5300 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5301 return JUMBO_7K; 5302 /* RTL8168b */ 5303 case RTL_GIGA_MAC_VER_11: 5304 case RTL_GIGA_MAC_VER_17: 5305 return JUMBO_4K; 5306 /* RTL8168c */ 5307 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5308 return JUMBO_6K; 5309 default: 5310 return JUMBO_9K; 5311 } 5312 } 5313 5314 static void rtl_init_mac_address(struct rtl8169_private *tp) 5315 { 5316 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5317 struct net_device *dev = tp->dev; 5318 int rc; 5319 5320 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5321 if (!rc) 5322 goto done; 5323 5324 rtl_read_mac_address(tp, mac_addr); 5325 if (is_valid_ether_addr(mac_addr)) 5326 goto done; 5327 5328 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5329 if (is_valid_ether_addr(mac_addr)) 5330 goto done; 5331 5332 eth_random_addr(mac_addr); 5333 dev->addr_assign_type = NET_ADDR_RANDOM; 5334 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5335 done: 5336 eth_hw_addr_set(dev, mac_addr); 5337 rtl_rar_set(tp, mac_addr); 5338 } 5339 5340 /* register is set if system vendor successfully tested ASPM 1.2 */ 5341 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5342 { 5343 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5344 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5345 return true; 5346 5347 return false; 5348 } 5349 5350 static umode_t r8169_hwmon_is_visible(const void *drvdata, 5351 enum hwmon_sensor_types type, 5352 u32 attr, int channel) 5353 { 5354 return 0444; 5355 } 5356 5357 static int r8169_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 5358 u32 attr, int channel, long *val) 5359 { 5360 struct rtl8169_private *tp = dev_get_drvdata(dev); 5361 int val_raw; 5362 5363 val_raw = phy_read_paged(tp->phydev, 0xbd8, 0x12) & 0x3ff; 5364 if (val_raw >= 512) 5365 val_raw -= 1024; 5366 5367 *val = 1000 * val_raw / 2; 5368 5369 return 0; 5370 } 5371 5372 static const struct hwmon_ops r8169_hwmon_ops = { 5373 .is_visible = r8169_hwmon_is_visible, 5374 .read = r8169_hwmon_read, 5375 }; 5376 5377 static const struct hwmon_channel_info * const r8169_hwmon_info[] = { 5378 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 5379 NULL 5380 }; 5381 5382 static const struct hwmon_chip_info r8169_hwmon_chip_info = { 5383 .ops = &r8169_hwmon_ops, 5384 .info = r8169_hwmon_info, 5385 }; 5386 5387 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5388 { 5389 struct rtl8169_private *tp; 5390 int jumbo_max, region, rc; 5391 enum mac_version chipset; 5392 struct net_device *dev; 5393 u32 txconfig; 5394 u16 xid; 5395 5396 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5397 if (!dev) 5398 return -ENOMEM; 5399 5400 SET_NETDEV_DEV(dev, &pdev->dev); 5401 dev->netdev_ops = &rtl_netdev_ops; 5402 tp = netdev_priv(dev); 5403 tp->dev = dev; 5404 tp->pci_dev = pdev; 5405 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5406 tp->ocp_base = OCP_STD_PHY_BASE; 5407 5408 raw_spin_lock_init(&tp->mac_ocp_lock); 5409 mutex_init(&tp->led_lock); 5410 5411 /* Get the *optional* external "ether_clk" used on some boards */ 5412 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5413 if (IS_ERR(tp->clk)) 5414 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5415 5416 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5417 rc = pcim_enable_device(pdev); 5418 if (rc < 0) 5419 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5420 5421 if (pcim_set_mwi(pdev) < 0) 5422 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5423 5424 /* use first MMIO region */ 5425 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5426 if (region < 0) 5427 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5428 5429 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5430 if (rc < 0) 5431 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5432 5433 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5434 5435 txconfig = RTL_R32(tp, TxConfig); 5436 if (txconfig == ~0U) 5437 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5438 5439 xid = (txconfig >> 20) & 0xfcf; 5440 5441 /* Identify chip attached to board */ 5442 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5443 if (chipset == RTL_GIGA_MAC_NONE) 5444 return dev_err_probe(&pdev->dev, -ENODEV, 5445 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5446 xid); 5447 tp->mac_version = chipset; 5448 5449 /* Disable ASPM L1 as that cause random device stop working 5450 * problems as well as full system hangs for some PCIe devices users. 5451 */ 5452 if (rtl_aspm_is_safe(tp)) 5453 rc = 0; 5454 else 5455 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5456 tp->aspm_manageable = !rc; 5457 5458 tp->dash_type = rtl_get_dash_type(tp); 5459 tp->dash_enabled = rtl_dash_is_enabled(tp); 5460 5461 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5462 5463 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5464 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5465 dev->features |= NETIF_F_HIGHDMA; 5466 5467 rtl_init_rxcfg(tp); 5468 5469 rtl8169_irq_mask_and_ack(tp); 5470 5471 rtl_hw_initialize(tp); 5472 5473 rtl_hw_reset(tp); 5474 5475 rc = rtl_alloc_irq(tp); 5476 if (rc < 0) 5477 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5478 5479 tp->irq = pci_irq_vector(pdev, 0); 5480 5481 INIT_WORK(&tp->wk.work, rtl_task); 5482 disable_work(&tp->wk.work); 5483 5484 rtl_init_mac_address(tp); 5485 5486 dev->ethtool_ops = &rtl8169_ethtool_ops; 5487 5488 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5489 5490 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5491 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5492 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5493 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5494 5495 /* 5496 * Pretend we are using VLANs; This bypasses a nasty bug where 5497 * Interrupts stop flowing on high load on 8110SCd controllers. 5498 */ 5499 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5500 /* Disallow toggling */ 5501 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5502 5503 if (rtl_chip_supports_csum_v2(tp)) 5504 dev->hw_features |= NETIF_F_IPV6_CSUM; 5505 5506 dev->features |= dev->hw_features; 5507 5508 if (rtl_chip_supports_csum_v2(tp)) { 5509 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5510 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5511 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5512 } else { 5513 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5514 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5515 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5516 } 5517 5518 /* There has been a number of reports that using SG/TSO results in 5519 * tx timeouts. However for a lot of people SG/TSO works fine. 5520 * It's not fully clear which chip versions are affected. Vendor 5521 * drivers enable SG/TSO for certain chip versions per default, 5522 * let's mimic this here. On other chip versions users can 5523 * use ethtool to enable SG/TSO, use at own risk! 5524 */ 5525 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5526 tp->mac_version != RTL_GIGA_MAC_VER_61) 5527 dev->features |= dev->hw_features; 5528 5529 dev->hw_features |= NETIF_F_RXALL; 5530 dev->hw_features |= NETIF_F_RXFCS; 5531 5532 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5533 5534 netdev_sw_irq_coalesce_default_on(dev); 5535 5536 /* configure chip for default features */ 5537 rtl8169_set_features(dev, dev->features); 5538 5539 if (!tp->dash_enabled) { 5540 rtl_set_d3_pll_down(tp, true); 5541 } else { 5542 rtl_set_d3_pll_down(tp, false); 5543 dev->ethtool->wol_enabled = 1; 5544 } 5545 5546 jumbo_max = rtl_jumbo_max(tp); 5547 if (jumbo_max) 5548 dev->max_mtu = jumbo_max; 5549 5550 rtl_set_irq_mask(tp); 5551 5552 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5553 5554 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5555 &tp->counters_phys_addr, 5556 GFP_KERNEL); 5557 if (!tp->counters) 5558 return -ENOMEM; 5559 5560 pci_set_drvdata(pdev, tp); 5561 5562 rc = r8169_mdio_register(tp); 5563 if (rc) 5564 return rc; 5565 5566 /* The temperature sensor is available from RTl8125B */ 5567 if (IS_REACHABLE(CONFIG_HWMON) && tp->mac_version >= RTL_GIGA_MAC_VER_63) 5568 /* ignore errors */ 5569 devm_hwmon_device_register_with_info(&pdev->dev, "nic_temp", tp, 5570 &r8169_hwmon_chip_info, 5571 NULL); 5572 rc = register_netdev(dev); 5573 if (rc) 5574 return rc; 5575 5576 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5577 if (rtl_is_8125(tp)) 5578 tp->leds = rtl8125_init_leds(dev); 5579 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5580 tp->leds = rtl8168_init_leds(dev); 5581 } 5582 5583 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5584 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5585 5586 if (jumbo_max) 5587 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5588 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5589 "ok" : "ko"); 5590 5591 if (tp->dash_type != RTL_DASH_NONE) { 5592 netdev_info(dev, "DASH %s\n", 5593 tp->dash_enabled ? "enabled" : "disabled"); 5594 rtl8168_driver_start(tp); 5595 } 5596 5597 if (pci_dev_run_wake(pdev)) 5598 pm_runtime_put_sync(&pdev->dev); 5599 5600 return 0; 5601 } 5602 5603 static struct pci_driver rtl8169_pci_driver = { 5604 .name = KBUILD_MODNAME, 5605 .id_table = rtl8169_pci_tbl, 5606 .probe = rtl_init_one, 5607 .remove = rtl_remove_one, 5608 .shutdown = rtl_shutdown, 5609 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5610 }; 5611 5612 module_pci_driver(rtl8169_pci_driver); 5613