1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/hwmon.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/in.h> 23 #include <linux/io.h> 24 #include <linux/ip.h> 25 #include <linux/tcp.h> 26 #include <linux/interrupt.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/bitfield.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <linux/unaligned.h> 33 #include <net/ip6_checksum.h> 34 #include <net/netdev_queues.h> 35 36 #include "r8169.h" 37 #include "r8169_firmware.h" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 59 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" 60 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 61 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 62 63 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 65 66 #define R8169_REGS_SIZE 256 67 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 68 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 69 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 70 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 71 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 72 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 73 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 74 75 #define OCP_STD_PHY_BASE 0xa400 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 92 static const struct { 93 const char *name; 94 const char *fw_name; 95 } rtl_chip_infos[] = { 96 /* PCI devices. */ 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 102 /* PCI-E devices. */ 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 109 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 111 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 117 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 118 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 119 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 122 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 124 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 125 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 126 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 127 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 128 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 129 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 130 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 131 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 132 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 133 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 134 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 135 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 136 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 137 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 138 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 139 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 140 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 141 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 142 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 143 [RTL_GIGA_MAC_VER_64] = {"RTL8125D", FIRMWARE_8125D_1}, 144 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 145 [RTL_GIGA_MAC_VER_66] = {"RTL8126A", FIRMWARE_8126A_3}, 146 }; 147 148 static const struct pci_device_id rtl8169_pci_tbl[] = { 149 { PCI_VDEVICE(REALTEK, 0x2502) }, 150 { PCI_VDEVICE(REALTEK, 0x2600) }, 151 { PCI_VDEVICE(REALTEK, 0x8129) }, 152 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 153 { PCI_VDEVICE(REALTEK, 0x8161) }, 154 { PCI_VDEVICE(REALTEK, 0x8162) }, 155 { PCI_VDEVICE(REALTEK, 0x8167) }, 156 { PCI_VDEVICE(REALTEK, 0x8168) }, 157 { PCI_VDEVICE(NCUBE, 0x8168) }, 158 { PCI_VDEVICE(REALTEK, 0x8169) }, 159 { PCI_VENDOR_ID_DLINK, 0x4300, 160 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 161 { PCI_VDEVICE(DLINK, 0x4300) }, 162 { PCI_VDEVICE(DLINK, 0x4302) }, 163 { PCI_VDEVICE(AT, 0xc107) }, 164 { PCI_VDEVICE(USR, 0x0116) }, 165 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 166 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 167 { PCI_VDEVICE(REALTEK, 0x8125) }, 168 { PCI_VDEVICE(REALTEK, 0x8126) }, 169 { PCI_VDEVICE(REALTEK, 0x3000) }, 170 {} 171 }; 172 173 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 174 175 enum rtl_registers { 176 MAC0 = 0, /* Ethernet hardware address. */ 177 MAC4 = 4, 178 MAR0 = 8, /* Multicast filter. */ 179 CounterAddrLow = 0x10, 180 CounterAddrHigh = 0x14, 181 TxDescStartAddrLow = 0x20, 182 TxDescStartAddrHigh = 0x24, 183 TxHDescStartAddrLow = 0x28, 184 TxHDescStartAddrHigh = 0x2c, 185 FLASH = 0x30, 186 ERSR = 0x36, 187 ChipCmd = 0x37, 188 TxPoll = 0x38, 189 IntrMask = 0x3c, 190 IntrStatus = 0x3e, 191 192 TxConfig = 0x40, 193 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 194 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 195 196 RxConfig = 0x44, 197 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 198 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 199 #define RXCFG_FIFO_SHIFT 13 200 /* No threshold before first PCI xfer */ 201 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 202 #define RX_EARLY_OFF (1 << 11) 203 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 204 #define RXCFG_DMA_SHIFT 8 205 /* Unlimited maximum PCI burst. */ 206 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 207 208 Cfg9346 = 0x50, 209 Config0 = 0x51, 210 Config1 = 0x52, 211 Config2 = 0x53, 212 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 213 214 Config3 = 0x54, 215 Config4 = 0x55, 216 Config5 = 0x56, 217 PHYAR = 0x60, 218 PHYstatus = 0x6c, 219 RxMaxSize = 0xda, 220 CPlusCmd = 0xe0, 221 IntrMitigate = 0xe2, 222 223 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 224 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 225 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 226 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 227 228 #define RTL_COALESCE_T_MAX 0x0fU 229 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 230 231 RxDescAddrLow = 0xe4, 232 RxDescAddrHigh = 0xe8, 233 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 234 235 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 236 237 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 238 239 #define TxPacketMax (8064 >> 7) 240 #define EarlySize 0x27 241 242 FuncEvent = 0xf0, 243 FuncEventMask = 0xf4, 244 FuncPresetState = 0xf8, 245 IBCR0 = 0xf8, 246 IBCR2 = 0xf9, 247 IBIMR0 = 0xfa, 248 IBISR0 = 0xfb, 249 FuncForceEvent = 0xfc, 250 }; 251 252 enum rtl8168_8101_registers { 253 CSIDR = 0x64, 254 CSIAR = 0x68, 255 #define CSIAR_FLAG 0x80000000 256 #define CSIAR_WRITE_CMD 0x80000000 257 #define CSIAR_BYTE_ENABLE 0x0000f000 258 #define CSIAR_ADDR_MASK 0x00000fff 259 PMCH = 0x6f, 260 #define D3COLD_NO_PLL_DOWN BIT(7) 261 #define D3HOT_NO_PLL_DOWN BIT(6) 262 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 263 EPHYAR = 0x80, 264 #define EPHYAR_FLAG 0x80000000 265 #define EPHYAR_WRITE_CMD 0x80000000 266 #define EPHYAR_REG_MASK 0x1f 267 #define EPHYAR_REG_SHIFT 16 268 #define EPHYAR_DATA_MASK 0xffff 269 DLLPR = 0xd0, 270 #define PFM_EN (1 << 6) 271 #define TX_10M_PS_EN (1 << 7) 272 DBG_REG = 0xd1, 273 #define FIX_NAK_1 (1 << 4) 274 #define FIX_NAK_2 (1 << 3) 275 TWSI = 0xd2, 276 MCU = 0xd3, 277 #define NOW_IS_OOB (1 << 7) 278 #define TX_EMPTY (1 << 5) 279 #define RX_EMPTY (1 << 4) 280 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 281 #define EN_NDP (1 << 3) 282 #define EN_OOB_RESET (1 << 2) 283 #define LINK_LIST_RDY (1 << 1) 284 EFUSEAR = 0xdc, 285 #define EFUSEAR_FLAG 0x80000000 286 #define EFUSEAR_WRITE_CMD 0x80000000 287 #define EFUSEAR_READ_CMD 0x00000000 288 #define EFUSEAR_REG_MASK 0x03ff 289 #define EFUSEAR_REG_SHIFT 8 290 #define EFUSEAR_DATA_MASK 0xff 291 MISC_1 = 0xf2, 292 #define PFM_D3COLD_EN (1 << 6) 293 }; 294 295 enum rtl8168_registers { 296 LED_CTRL = 0x18, 297 LED_FREQ = 0x1a, 298 EEE_LED = 0x1b, 299 ERIDR = 0x70, 300 ERIAR = 0x74, 301 #define ERIAR_FLAG 0x80000000 302 #define ERIAR_WRITE_CMD 0x80000000 303 #define ERIAR_READ_CMD 0x00000000 304 #define ERIAR_ADDR_BYTE_ALIGN 4 305 #define ERIAR_TYPE_SHIFT 16 306 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 310 #define ERIAR_MASK_SHIFT 12 311 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 315 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 316 EPHY_RXER_NUM = 0x7c, 317 OCPDR = 0xb0, /* OCP GPHY access */ 318 #define OCPDR_WRITE_CMD 0x80000000 319 #define OCPDR_READ_CMD 0x00000000 320 #define OCPDR_REG_MASK 0x7f 321 #define OCPDR_GPHY_REG_SHIFT 16 322 #define OCPDR_DATA_MASK 0xffff 323 OCPAR = 0xb4, 324 #define OCPAR_FLAG 0x80000000 325 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 326 #define OCPAR_GPHY_READ_CMD 0x0000f060 327 GPHY_OCP = 0xb8, 328 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 329 MISC = 0xf0, /* 8168e only. */ 330 #define TXPLA_RST (1 << 29) 331 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 332 #define PWM_EN (1 << 22) 333 #define RXDV_GATED_EN (1 << 19) 334 #define EARLY_TALLY_EN (1 << 16) 335 }; 336 337 enum rtl8125_registers { 338 LEDSEL0 = 0x18, 339 INT_CFG0_8125 = 0x34, 340 #define INT_CFG0_ENABLE_8125 BIT(0) 341 #define INT_CFG0_CLKREQEN BIT(3) 342 IntrMask_8125 = 0x38, 343 IntrStatus_8125 = 0x3c, 344 INT_CFG1_8125 = 0x7a, 345 LEDSEL2 = 0x84, 346 LEDSEL1 = 0x86, 347 TxPoll_8125 = 0x90, 348 LEDSEL3 = 0x96, 349 MAC0_BKP = 0x19e0, 350 EEE_TXIDLE_TIMER_8125 = 0x6048, 351 }; 352 353 #define LEDSEL_MASK_8125 0x23f 354 355 #define RX_VLAN_INNER_8125 BIT(22) 356 #define RX_VLAN_OUTER_8125 BIT(23) 357 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 358 359 #define RX_FETCH_DFLT_8125 (8 << 27) 360 361 enum rtl_register_content { 362 /* InterruptStatusBits */ 363 SYSErr = 0x8000, 364 PCSTimeout = 0x4000, 365 SWInt = 0x0100, 366 TxDescUnavail = 0x0080, 367 RxFIFOOver = 0x0040, 368 LinkChg = 0x0020, 369 RxOverflow = 0x0010, 370 TxErr = 0x0008, 371 TxOK = 0x0004, 372 RxErr = 0x0002, 373 RxOK = 0x0001, 374 375 /* RxStatusDesc */ 376 RxRWT = (1 << 22), 377 RxRES = (1 << 21), 378 RxRUNT = (1 << 20), 379 RxCRC = (1 << 19), 380 381 /* ChipCmdBits */ 382 StopReq = 0x80, 383 CmdReset = 0x10, 384 CmdRxEnb = 0x08, 385 CmdTxEnb = 0x04, 386 RxBufEmpty = 0x01, 387 388 /* TXPoll register p.5 */ 389 HPQ = 0x80, /* Poll cmd on the high prio queue */ 390 NPQ = 0x40, /* Poll cmd on the low prio queue */ 391 FSWInt = 0x01, /* Forced software interrupt */ 392 393 /* Cfg9346Bits */ 394 Cfg9346_Lock = 0x00, 395 Cfg9346_Unlock = 0xc0, 396 397 /* rx_mode_bits */ 398 AcceptErr = 0x20, 399 AcceptRunt = 0x10, 400 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 401 AcceptBroadcast = 0x08, 402 AcceptMulticast = 0x04, 403 AcceptMyPhys = 0x02, 404 AcceptAllPhys = 0x01, 405 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 406 #define RX_CONFIG_ACCEPT_MASK 0x3f 407 408 /* TxConfigBits */ 409 TxInterFrameGapShift = 24, 410 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 411 412 /* Config1 register p.24 */ 413 LEDS1 = (1 << 7), 414 LEDS0 = (1 << 6), 415 Speed_down = (1 << 4), 416 MEMMAP = (1 << 3), 417 IOMAP = (1 << 2), 418 VPD = (1 << 1), 419 PMEnable = (1 << 0), /* Power Management Enable */ 420 421 /* Config2 register p. 25 */ 422 ClkReqEn = (1 << 7), /* Clock Request Enable */ 423 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 424 PCI_Clock_66MHz = 0x01, 425 PCI_Clock_33MHz = 0x00, 426 427 /* Config3 register p.25 */ 428 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 429 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 430 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 431 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 432 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 433 434 /* Config4 register */ 435 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 436 437 /* Config5 register p.27 */ 438 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 439 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 440 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 441 Spi_en = (1 << 3), 442 LanWake = (1 << 1), /* LanWake enable/disable */ 443 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 444 ASPM_en = (1 << 0), /* ASPM enable */ 445 446 /* CPlusCmd p.31 */ 447 EnableBist = (1 << 15), // 8168 8101 448 Mac_dbgo_oe = (1 << 14), // 8168 8101 449 EnAnaPLL = (1 << 14), // 8169 450 Normal_mode = (1 << 13), // unused 451 Force_half_dup = (1 << 12), // 8168 8101 452 Force_rxflow_en = (1 << 11), // 8168 8101 453 Force_txflow_en = (1 << 10), // 8168 8101 454 Cxpl_dbg_sel = (1 << 9), // 8168 8101 455 ASF = (1 << 8), // 8168 8101 456 PktCntrDisable = (1 << 7), // 8168 8101 457 Mac_dbgo_sel = 0x001c, // 8168 458 RxVlan = (1 << 6), 459 RxChkSum = (1 << 5), 460 PCIDAC = (1 << 4), 461 PCIMulRW = (1 << 3), 462 #define INTT_MASK GENMASK(1, 0) 463 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 464 465 /* rtl8169_PHYstatus */ 466 TBI_Enable = 0x80, 467 TxFlowCtrl = 0x40, 468 RxFlowCtrl = 0x20, 469 _1000bpsF = 0x10, 470 _100bps = 0x08, 471 _10bps = 0x04, 472 LinkStatus = 0x02, 473 FullDup = 0x01, 474 475 /* ResetCounterCommand */ 476 CounterReset = 0x1, 477 478 /* DumpCounterCommand */ 479 CounterDump = 0x8, 480 481 /* magic enable v2 */ 482 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 483 }; 484 485 enum rtl_desc_bit { 486 /* First doubleword. */ 487 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 488 RingEnd = (1 << 30), /* End of descriptor ring */ 489 FirstFrag = (1 << 29), /* First segment of a packet */ 490 LastFrag = (1 << 28), /* Final segment of a packet */ 491 }; 492 493 /* Generic case. */ 494 enum rtl_tx_desc_bit { 495 /* First doubleword. */ 496 TD_LSO = (1 << 27), /* Large Send Offload */ 497 #define TD_MSS_MAX 0x07ffu /* MSS value */ 498 499 /* Second doubleword. */ 500 TxVlanTag = (1 << 17), /* Add VLAN tag */ 501 }; 502 503 /* 8169, 8168b and 810x except 8102e. */ 504 enum rtl_tx_desc_bit_0 { 505 /* First doubleword. */ 506 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 507 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 508 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 509 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 510 }; 511 512 /* 8102e, 8168c and beyond. */ 513 enum rtl_tx_desc_bit_1 { 514 /* First doubleword. */ 515 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 516 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 517 #define GTTCPHO_SHIFT 18 518 #define GTTCPHO_MAX 0x7f 519 520 /* Second doubleword. */ 521 #define TCPHO_SHIFT 18 522 #define TCPHO_MAX 0x3ff 523 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 524 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 525 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 526 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 527 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 528 }; 529 530 enum rtl_rx_desc_bit { 531 /* Rx private */ 532 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 533 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 534 535 #define RxProtoUDP (PID1) 536 #define RxProtoTCP (PID0) 537 #define RxProtoIP (PID1 | PID0) 538 #define RxProtoMask RxProtoIP 539 540 IPFail = (1 << 16), /* IP checksum failed */ 541 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 542 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 543 544 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 545 546 RxVlanTag = (1 << 16), /* VLAN tag available */ 547 }; 548 549 #define RTL_GSO_MAX_SIZE_V1 32000 550 #define RTL_GSO_MAX_SEGS_V1 24 551 #define RTL_GSO_MAX_SIZE_V2 64000 552 #define RTL_GSO_MAX_SEGS_V2 64 553 554 struct TxDesc { 555 __le32 opts1; 556 __le32 opts2; 557 __le64 addr; 558 }; 559 560 struct RxDesc { 561 __le32 opts1; 562 __le32 opts2; 563 __le64 addr; 564 }; 565 566 struct ring_info { 567 struct sk_buff *skb; 568 u32 len; 569 }; 570 571 struct rtl8169_counters { 572 __le64 tx_packets; 573 __le64 rx_packets; 574 __le64 tx_errors; 575 __le32 rx_errors; 576 __le16 rx_missed; 577 __le16 align_errors; 578 __le32 tx_one_collision; 579 __le32 tx_multi_collision; 580 __le64 rx_unicast; 581 __le64 rx_broadcast; 582 __le32 rx_multicast; 583 __le16 tx_aborted; 584 __le16 tx_underrun; 585 /* new since RTL8125 */ 586 __le64 tx_octets; 587 __le64 rx_octets; 588 __le64 rx_multicast64; 589 __le64 tx_unicast64; 590 __le64 tx_broadcast64; 591 __le64 tx_multicast64; 592 __le32 tx_pause_on; 593 __le32 tx_pause_off; 594 __le32 tx_pause_all; 595 __le32 tx_deferred; 596 __le32 tx_late_collision; 597 __le32 tx_all_collision; 598 __le32 tx_aborted32; 599 __le32 align_errors32; 600 __le32 rx_frame_too_long; 601 __le32 rx_runt; 602 __le32 rx_pause_on; 603 __le32 rx_pause_off; 604 __le32 rx_pause_all; 605 __le32 rx_unknown_opcode; 606 __le32 rx_mac_error; 607 __le32 tx_underrun32; 608 __le32 rx_mac_missed; 609 __le32 rx_tcam_dropped; 610 __le32 tdu; 611 __le32 rdu; 612 }; 613 614 struct rtl8169_tc_offsets { 615 bool inited; 616 __le64 tx_errors; 617 __le32 tx_multi_collision; 618 __le16 tx_aborted; 619 __le16 rx_missed; 620 }; 621 622 enum rtl_flag { 623 RTL_FLAG_TASK_RESET_PENDING, 624 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 625 RTL_FLAG_TASK_TX_TIMEOUT, 626 RTL_FLAG_MAX 627 }; 628 629 enum rtl_dash_type { 630 RTL_DASH_NONE, 631 RTL_DASH_DP, 632 RTL_DASH_EP, 633 }; 634 635 struct rtl8169_private { 636 void __iomem *mmio_addr; /* memory map physical address */ 637 struct pci_dev *pci_dev; 638 struct net_device *dev; 639 struct phy_device *phydev; 640 struct napi_struct napi; 641 enum mac_version mac_version; 642 enum rtl_dash_type dash_type; 643 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 644 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 645 u32 dirty_tx; 646 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 647 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 648 dma_addr_t TxPhyAddr; 649 dma_addr_t RxPhyAddr; 650 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 651 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 652 u16 cp_cmd; 653 u16 tx_lpi_timer; 654 u32 irq_mask; 655 int irq; 656 struct clk *clk; 657 658 struct { 659 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 660 struct work_struct work; 661 } wk; 662 663 raw_spinlock_t config25_lock; 664 raw_spinlock_t mac_ocp_lock; 665 struct mutex led_lock; /* serialize LED ctrl RMW access */ 666 667 raw_spinlock_t cfg9346_usage_lock; 668 int cfg9346_usage_count; 669 670 unsigned supports_gmii:1; 671 unsigned aspm_manageable:1; 672 unsigned dash_enabled:1; 673 dma_addr_t counters_phys_addr; 674 struct rtl8169_counters *counters; 675 struct rtl8169_tc_offsets tc_offset; 676 u32 saved_wolopts; 677 678 const char *fw_name; 679 struct rtl_fw *rtl_fw; 680 681 struct r8169_led_classdev *leds; 682 683 u32 ocp_base; 684 }; 685 686 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 687 688 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 689 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 690 MODULE_SOFTDEP("pre: realtek"); 691 MODULE_LICENSE("GPL"); 692 MODULE_FIRMWARE(FIRMWARE_8168D_1); 693 MODULE_FIRMWARE(FIRMWARE_8168D_2); 694 MODULE_FIRMWARE(FIRMWARE_8168E_1); 695 MODULE_FIRMWARE(FIRMWARE_8168E_2); 696 MODULE_FIRMWARE(FIRMWARE_8168E_3); 697 MODULE_FIRMWARE(FIRMWARE_8105E_1); 698 MODULE_FIRMWARE(FIRMWARE_8168F_1); 699 MODULE_FIRMWARE(FIRMWARE_8168F_2); 700 MODULE_FIRMWARE(FIRMWARE_8402_1); 701 MODULE_FIRMWARE(FIRMWARE_8411_1); 702 MODULE_FIRMWARE(FIRMWARE_8411_2); 703 MODULE_FIRMWARE(FIRMWARE_8106E_1); 704 MODULE_FIRMWARE(FIRMWARE_8106E_2); 705 MODULE_FIRMWARE(FIRMWARE_8168G_2); 706 MODULE_FIRMWARE(FIRMWARE_8168G_3); 707 MODULE_FIRMWARE(FIRMWARE_8168H_2); 708 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 709 MODULE_FIRMWARE(FIRMWARE_8107E_2); 710 MODULE_FIRMWARE(FIRMWARE_8125A_3); 711 MODULE_FIRMWARE(FIRMWARE_8125B_2); 712 MODULE_FIRMWARE(FIRMWARE_8125D_1); 713 MODULE_FIRMWARE(FIRMWARE_8126A_2); 714 MODULE_FIRMWARE(FIRMWARE_8126A_3); 715 716 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 717 { 718 return &tp->pci_dev->dev; 719 } 720 721 static void rtl_lock_config_regs(struct rtl8169_private *tp) 722 { 723 unsigned long flags; 724 725 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 726 if (!--tp->cfg9346_usage_count) 727 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 728 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 729 } 730 731 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 732 { 733 unsigned long flags; 734 735 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 736 if (!tp->cfg9346_usage_count++) 737 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 738 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 739 } 740 741 static void rtl_pci_commit(struct rtl8169_private *tp) 742 { 743 /* Read an arbitrary register to commit a preceding PCI write */ 744 RTL_R8(tp, ChipCmd); 745 } 746 747 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 748 { 749 unsigned long flags; 750 u8 val; 751 752 raw_spin_lock_irqsave(&tp->config25_lock, flags); 753 val = RTL_R8(tp, Config2); 754 RTL_W8(tp, Config2, (val & ~clear) | set); 755 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 756 } 757 758 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 759 { 760 unsigned long flags; 761 u8 val; 762 763 raw_spin_lock_irqsave(&tp->config25_lock, flags); 764 val = RTL_R8(tp, Config5); 765 RTL_W8(tp, Config5, (val & ~clear) | set); 766 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 767 } 768 769 static bool rtl_is_8125(struct rtl8169_private *tp) 770 { 771 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 772 } 773 774 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 775 { 776 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 777 tp->mac_version != RTL_GIGA_MAC_VER_39 && 778 tp->mac_version <= RTL_GIGA_MAC_VER_53; 779 } 780 781 static bool rtl_supports_eee(struct rtl8169_private *tp) 782 { 783 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 784 tp->mac_version != RTL_GIGA_MAC_VER_37 && 785 tp->mac_version != RTL_GIGA_MAC_VER_39; 786 } 787 788 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 789 { 790 int i; 791 792 for (i = 0; i < ETH_ALEN; i++) 793 mac[i] = RTL_R8(tp, reg + i); 794 } 795 796 struct rtl_cond { 797 bool (*check)(struct rtl8169_private *); 798 const char *msg; 799 }; 800 801 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 802 unsigned long usecs, int n, bool high) 803 { 804 int i; 805 806 for (i = 0; i < n; i++) { 807 if (c->check(tp) == high) 808 return true; 809 fsleep(usecs); 810 } 811 812 if (net_ratelimit()) 813 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 814 c->msg, !high, n, usecs); 815 return false; 816 } 817 818 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 819 const struct rtl_cond *c, 820 unsigned long d, int n) 821 { 822 return rtl_loop_wait(tp, c, d, n, true); 823 } 824 825 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 826 const struct rtl_cond *c, 827 unsigned long d, int n) 828 { 829 return rtl_loop_wait(tp, c, d, n, false); 830 } 831 832 #define DECLARE_RTL_COND(name) \ 833 static bool name ## _check(struct rtl8169_private *); \ 834 \ 835 static const struct rtl_cond name = { \ 836 .check = name ## _check, \ 837 .msg = #name \ 838 }; \ 839 \ 840 static bool name ## _check(struct rtl8169_private *tp) 841 842 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 843 { 844 struct device *dev = tp_to_dev(tp); 845 int ret; 846 847 ret = pm_runtime_resume_and_get(dev); 848 if (ret < 0) 849 return ret; 850 851 mutex_lock(&tp->led_lock); 852 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 853 mutex_unlock(&tp->led_lock); 854 855 pm_runtime_put_sync(dev); 856 857 return 0; 858 } 859 860 int rtl8168_get_led_mode(struct rtl8169_private *tp) 861 { 862 struct device *dev = tp_to_dev(tp); 863 int ret; 864 865 ret = pm_runtime_resume_and_get(dev); 866 if (ret < 0) 867 return ret; 868 869 ret = RTL_R16(tp, LED_CTRL); 870 871 pm_runtime_put_sync(dev); 872 873 return ret; 874 } 875 876 static int rtl8125_get_led_reg(int index) 877 { 878 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 879 880 return led_regs[index]; 881 } 882 883 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 884 { 885 int reg = rtl8125_get_led_reg(index); 886 struct device *dev = tp_to_dev(tp); 887 int ret; 888 u16 val; 889 890 ret = pm_runtime_resume_and_get(dev); 891 if (ret < 0) 892 return ret; 893 894 mutex_lock(&tp->led_lock); 895 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 896 RTL_W16(tp, reg, val | mode); 897 mutex_unlock(&tp->led_lock); 898 899 pm_runtime_put_sync(dev); 900 901 return 0; 902 } 903 904 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 905 { 906 int reg = rtl8125_get_led_reg(index); 907 struct device *dev = tp_to_dev(tp); 908 int ret; 909 910 ret = pm_runtime_resume_and_get(dev); 911 if (ret < 0) 912 return ret; 913 914 ret = RTL_R16(tp, reg); 915 916 pm_runtime_put_sync(dev); 917 918 return ret; 919 } 920 921 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 922 char *buf, int buf_len) 923 { 924 struct pci_dev *pdev = tp->pci_dev; 925 char pdom[8], pfun[8]; 926 int domain; 927 928 domain = pci_domain_nr(pdev->bus); 929 if (domain) 930 snprintf(pdom, sizeof(pdom), "P%d", domain); 931 else 932 pdom[0] = '\0'; 933 934 if (pdev->multifunction) 935 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 936 else 937 pfun[0] = '\0'; 938 939 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 940 PCI_SLOT(pdev->devfn), pfun, idx); 941 } 942 943 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 944 { 945 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 946 if (type == ERIAR_OOB && 947 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 948 tp->mac_version == RTL_GIGA_MAC_VER_53)) 949 *cmd |= 0xf70 << 18; 950 } 951 952 DECLARE_RTL_COND(rtl_eriar_cond) 953 { 954 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 955 } 956 957 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 958 u32 val, int type) 959 { 960 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 961 962 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 963 return; 964 965 RTL_W32(tp, ERIDR, val); 966 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 967 RTL_W32(tp, ERIAR, cmd); 968 969 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 970 } 971 972 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 973 u32 val) 974 { 975 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 976 } 977 978 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 979 { 980 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 981 982 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 983 RTL_W32(tp, ERIAR, cmd); 984 985 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 986 RTL_R32(tp, ERIDR) : ~0; 987 } 988 989 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 990 { 991 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 992 } 993 994 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 995 { 996 u32 val = rtl_eri_read(tp, addr); 997 998 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 999 } 1000 1001 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1002 { 1003 rtl_w0w1_eri(tp, addr, p, 0); 1004 } 1005 1006 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1007 { 1008 rtl_w0w1_eri(tp, addr, 0, m); 1009 } 1010 1011 static bool rtl_ocp_reg_failure(u32 reg) 1012 { 1013 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1014 } 1015 1016 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1017 { 1018 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1019 } 1020 1021 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1022 { 1023 if (rtl_ocp_reg_failure(reg)) 1024 return; 1025 1026 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1027 1028 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1029 } 1030 1031 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1032 { 1033 if (rtl_ocp_reg_failure(reg)) 1034 return 0; 1035 1036 RTL_W32(tp, GPHY_OCP, reg << 15); 1037 1038 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1039 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1040 } 1041 1042 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1043 { 1044 if (rtl_ocp_reg_failure(reg)) 1045 return; 1046 1047 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1048 } 1049 1050 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1051 { 1052 unsigned long flags; 1053 1054 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1055 __r8168_mac_ocp_write(tp, reg, data); 1056 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1057 } 1058 1059 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1060 { 1061 if (rtl_ocp_reg_failure(reg)) 1062 return 0; 1063 1064 RTL_W32(tp, OCPDR, reg << 15); 1065 1066 return RTL_R32(tp, OCPDR); 1067 } 1068 1069 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1070 { 1071 unsigned long flags; 1072 u16 val; 1073 1074 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1075 val = __r8168_mac_ocp_read(tp, reg); 1076 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1077 1078 return val; 1079 } 1080 1081 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1082 u16 set) 1083 { 1084 unsigned long flags; 1085 u16 data; 1086 1087 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1088 data = __r8168_mac_ocp_read(tp, reg); 1089 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1090 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1091 } 1092 1093 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1094 * PHY MCU interrupts before PHY power-down. 1095 */ 1096 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1097 { 1098 switch (tp->mac_version) { 1099 case RTL_GIGA_MAC_VER_40: 1100 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1101 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1102 else 1103 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1104 break; 1105 default: 1106 break; 1107 } 1108 }; 1109 1110 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1111 { 1112 if (reg == 0x1f) { 1113 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1114 return; 1115 } 1116 1117 if (tp->ocp_base != OCP_STD_PHY_BASE) 1118 reg -= 0x10; 1119 1120 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1121 rtl8168g_phy_suspend_quirk(tp, value); 1122 1123 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1124 } 1125 1126 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1127 { 1128 if (reg == 0x1f) 1129 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1130 1131 if (tp->ocp_base != OCP_STD_PHY_BASE) 1132 reg -= 0x10; 1133 1134 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1135 } 1136 1137 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1138 { 1139 if (reg == 0x1f) { 1140 tp->ocp_base = value << 4; 1141 return; 1142 } 1143 1144 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1145 } 1146 1147 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1148 { 1149 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1150 } 1151 1152 DECLARE_RTL_COND(rtl_phyar_cond) 1153 { 1154 return RTL_R32(tp, PHYAR) & 0x80000000; 1155 } 1156 1157 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1158 { 1159 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1160 1161 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1162 /* 1163 * According to hardware specs a 20us delay is required after write 1164 * complete indication, but before sending next command. 1165 */ 1166 udelay(20); 1167 } 1168 1169 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1170 { 1171 int value; 1172 1173 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1174 1175 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1176 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1177 1178 /* 1179 * According to hardware specs a 20us delay is required after read 1180 * complete indication, but before sending next command. 1181 */ 1182 udelay(20); 1183 1184 return value; 1185 } 1186 1187 DECLARE_RTL_COND(rtl_ocpar_cond) 1188 { 1189 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1190 } 1191 1192 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1193 1194 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1195 { 1196 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1197 } 1198 1199 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1200 { 1201 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1202 } 1203 1204 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1205 { 1206 r8168dp_2_mdio_start(tp); 1207 1208 r8169_mdio_write(tp, reg, value); 1209 1210 r8168dp_2_mdio_stop(tp); 1211 } 1212 1213 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1214 { 1215 int value; 1216 1217 /* Work around issue with chip reporting wrong PHY ID */ 1218 if (reg == MII_PHYSID2) 1219 return 0xc912; 1220 1221 r8168dp_2_mdio_start(tp); 1222 1223 value = r8169_mdio_read(tp, reg); 1224 1225 r8168dp_2_mdio_stop(tp); 1226 1227 return value; 1228 } 1229 1230 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1231 { 1232 switch (tp->mac_version) { 1233 case RTL_GIGA_MAC_VER_28: 1234 case RTL_GIGA_MAC_VER_31: 1235 r8168dp_2_mdio_write(tp, location, val); 1236 break; 1237 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1238 r8168g_mdio_write(tp, location, val); 1239 break; 1240 default: 1241 r8169_mdio_write(tp, location, val); 1242 break; 1243 } 1244 } 1245 1246 static int rtl_readphy(struct rtl8169_private *tp, int location) 1247 { 1248 switch (tp->mac_version) { 1249 case RTL_GIGA_MAC_VER_28: 1250 case RTL_GIGA_MAC_VER_31: 1251 return r8168dp_2_mdio_read(tp, location); 1252 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1253 return r8168g_mdio_read(tp, location); 1254 default: 1255 return r8169_mdio_read(tp, location); 1256 } 1257 } 1258 1259 DECLARE_RTL_COND(rtl_ephyar_cond) 1260 { 1261 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1262 } 1263 1264 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1265 { 1266 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1267 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1268 1269 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1270 1271 udelay(10); 1272 } 1273 1274 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1275 { 1276 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1277 1278 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1279 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1280 } 1281 1282 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1283 { 1284 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1285 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1286 RTL_R32(tp, OCPDR) : ~0; 1287 } 1288 1289 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1290 { 1291 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1292 } 1293 1294 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1295 u32 data) 1296 { 1297 RTL_W32(tp, OCPDR, data); 1298 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1299 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1300 } 1301 1302 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1303 u32 data) 1304 { 1305 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1306 data, ERIAR_OOB); 1307 } 1308 1309 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1310 { 1311 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1312 1313 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1314 } 1315 1316 #define OOB_CMD_RESET 0x00 1317 #define OOB_CMD_DRIVER_START 0x05 1318 #define OOB_CMD_DRIVER_STOP 0x06 1319 1320 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1321 { 1322 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1323 } 1324 1325 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1326 { 1327 u16 reg; 1328 1329 reg = rtl8168_get_ocp_reg(tp); 1330 1331 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1332 } 1333 1334 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1335 { 1336 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1337 } 1338 1339 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1340 { 1341 return RTL_R8(tp, IBISR0) & 0x20; 1342 } 1343 1344 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1345 { 1346 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1347 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1348 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1349 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1350 } 1351 1352 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1353 { 1354 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1355 if (tp->dash_enabled) 1356 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1357 } 1358 1359 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1360 { 1361 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1362 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1363 if (tp->dash_enabled) 1364 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1365 } 1366 1367 static void rtl8168_driver_start(struct rtl8169_private *tp) 1368 { 1369 if (tp->dash_type == RTL_DASH_DP) 1370 rtl8168dp_driver_start(tp); 1371 else 1372 rtl8168ep_driver_start(tp); 1373 } 1374 1375 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1376 { 1377 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1378 if (tp->dash_enabled) 1379 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1380 } 1381 1382 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1383 { 1384 rtl8168ep_stop_cmac(tp); 1385 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1386 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1387 if (tp->dash_enabled) 1388 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1389 } 1390 1391 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1392 { 1393 if (tp->dash_type == RTL_DASH_DP) 1394 rtl8168dp_driver_stop(tp); 1395 else 1396 rtl8168ep_driver_stop(tp); 1397 } 1398 1399 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1400 { 1401 u16 reg = rtl8168_get_ocp_reg(tp); 1402 1403 return r8168dp_ocp_read(tp, reg) & BIT(15); 1404 } 1405 1406 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1407 { 1408 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1409 } 1410 1411 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1412 { 1413 switch (tp->dash_type) { 1414 case RTL_DASH_DP: 1415 return r8168dp_check_dash(tp); 1416 case RTL_DASH_EP: 1417 return r8168ep_check_dash(tp); 1418 default: 1419 return false; 1420 } 1421 } 1422 1423 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1424 { 1425 switch (tp->mac_version) { 1426 case RTL_GIGA_MAC_VER_28: 1427 case RTL_GIGA_MAC_VER_31: 1428 return RTL_DASH_DP; 1429 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1430 return RTL_DASH_EP; 1431 default: 1432 return RTL_DASH_NONE; 1433 } 1434 } 1435 1436 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1437 { 1438 switch (tp->mac_version) { 1439 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1440 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1441 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1442 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1443 if (enable) 1444 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1445 else 1446 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1447 break; 1448 default: 1449 break; 1450 } 1451 } 1452 1453 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1454 { 1455 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1456 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1457 } 1458 1459 DECLARE_RTL_COND(rtl_efusear_cond) 1460 { 1461 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1462 } 1463 1464 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1465 { 1466 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1467 1468 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1469 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1470 } 1471 1472 static u32 rtl_get_events(struct rtl8169_private *tp) 1473 { 1474 if (rtl_is_8125(tp)) 1475 return RTL_R32(tp, IntrStatus_8125); 1476 else 1477 return RTL_R16(tp, IntrStatus); 1478 } 1479 1480 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1481 { 1482 if (rtl_is_8125(tp)) 1483 RTL_W32(tp, IntrStatus_8125, bits); 1484 else 1485 RTL_W16(tp, IntrStatus, bits); 1486 } 1487 1488 static void rtl_irq_disable(struct rtl8169_private *tp) 1489 { 1490 if (rtl_is_8125(tp)) 1491 RTL_W32(tp, IntrMask_8125, 0); 1492 else 1493 RTL_W16(tp, IntrMask, 0); 1494 } 1495 1496 static void rtl_irq_enable(struct rtl8169_private *tp) 1497 { 1498 if (rtl_is_8125(tp)) 1499 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1500 else 1501 RTL_W16(tp, IntrMask, tp->irq_mask); 1502 } 1503 1504 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1505 { 1506 rtl_irq_disable(tp); 1507 rtl_ack_events(tp, 0xffffffff); 1508 rtl_pci_commit(tp); 1509 } 1510 1511 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1512 { 1513 struct phy_device *phydev = tp->phydev; 1514 1515 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1516 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1517 if (phydev->speed == SPEED_1000) { 1518 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1519 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1520 } else if (phydev->speed == SPEED_100) { 1521 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1522 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1523 } else { 1524 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1525 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1526 } 1527 rtl_reset_packet_filter(tp); 1528 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1529 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1530 if (phydev->speed == SPEED_1000) { 1531 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1532 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1533 } else { 1534 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1535 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1536 } 1537 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1538 if (phydev->speed == SPEED_10) { 1539 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1540 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1541 } else { 1542 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1543 } 1544 } 1545 } 1546 1547 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1548 1549 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1550 { 1551 struct rtl8169_private *tp = netdev_priv(dev); 1552 1553 wol->supported = WAKE_ANY; 1554 wol->wolopts = tp->saved_wolopts; 1555 } 1556 1557 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1558 { 1559 static const struct { 1560 u32 opt; 1561 u16 reg; 1562 u8 mask; 1563 } cfg[] = { 1564 { WAKE_PHY, Config3, LinkUp }, 1565 { WAKE_UCAST, Config5, UWF }, 1566 { WAKE_BCAST, Config5, BWF }, 1567 { WAKE_MCAST, Config5, MWF }, 1568 { WAKE_ANY, Config5, LanWake }, 1569 { WAKE_MAGIC, Config3, MagicPacket } 1570 }; 1571 unsigned int i, tmp = ARRAY_SIZE(cfg); 1572 unsigned long flags; 1573 u8 options; 1574 1575 rtl_unlock_config_regs(tp); 1576 1577 if (rtl_is_8168evl_up(tp)) { 1578 tmp--; 1579 if (wolopts & WAKE_MAGIC) 1580 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1581 else 1582 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1583 } else if (rtl_is_8125(tp)) { 1584 tmp--; 1585 if (wolopts & WAKE_MAGIC) 1586 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1587 else 1588 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1589 } 1590 1591 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1592 for (i = 0; i < tmp; i++) { 1593 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1594 if (wolopts & cfg[i].opt) 1595 options |= cfg[i].mask; 1596 RTL_W8(tp, cfg[i].reg, options); 1597 } 1598 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1599 1600 switch (tp->mac_version) { 1601 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1602 options = RTL_R8(tp, Config1) & ~PMEnable; 1603 if (wolopts) 1604 options |= PMEnable; 1605 RTL_W8(tp, Config1, options); 1606 break; 1607 case RTL_GIGA_MAC_VER_34: 1608 case RTL_GIGA_MAC_VER_37: 1609 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1610 if (wolopts) 1611 rtl_mod_config2(tp, 0, PME_SIGNAL); 1612 else 1613 rtl_mod_config2(tp, PME_SIGNAL, 0); 1614 break; 1615 default: 1616 break; 1617 } 1618 1619 rtl_lock_config_regs(tp); 1620 1621 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1622 1623 if (!tp->dash_enabled) { 1624 rtl_set_d3_pll_down(tp, !wolopts); 1625 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1626 } 1627 } 1628 1629 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1630 { 1631 struct rtl8169_private *tp = netdev_priv(dev); 1632 1633 if (wol->wolopts & ~WAKE_ANY) 1634 return -EINVAL; 1635 1636 tp->saved_wolopts = wol->wolopts; 1637 __rtl8169_set_wol(tp, tp->saved_wolopts); 1638 1639 return 0; 1640 } 1641 1642 static void rtl8169_get_drvinfo(struct net_device *dev, 1643 struct ethtool_drvinfo *info) 1644 { 1645 struct rtl8169_private *tp = netdev_priv(dev); 1646 struct rtl_fw *rtl_fw = tp->rtl_fw; 1647 1648 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1649 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1650 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1651 if (rtl_fw) 1652 strscpy(info->fw_version, rtl_fw->version, 1653 sizeof(info->fw_version)); 1654 } 1655 1656 static int rtl8169_get_regs_len(struct net_device *dev) 1657 { 1658 return R8169_REGS_SIZE; 1659 } 1660 1661 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1662 netdev_features_t features) 1663 { 1664 struct rtl8169_private *tp = netdev_priv(dev); 1665 1666 if (dev->mtu > TD_MSS_MAX) 1667 features &= ~NETIF_F_ALL_TSO; 1668 1669 if (dev->mtu > ETH_DATA_LEN && 1670 tp->mac_version > RTL_GIGA_MAC_VER_06) 1671 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1672 1673 return features; 1674 } 1675 1676 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1677 netdev_features_t features) 1678 { 1679 u32 rx_config = RTL_R32(tp, RxConfig); 1680 1681 if (features & NETIF_F_RXALL) 1682 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1683 else 1684 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1685 1686 if (rtl_is_8125(tp)) { 1687 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1688 rx_config |= RX_VLAN_8125; 1689 else 1690 rx_config &= ~RX_VLAN_8125; 1691 } 1692 1693 RTL_W32(tp, RxConfig, rx_config); 1694 } 1695 1696 static int rtl8169_set_features(struct net_device *dev, 1697 netdev_features_t features) 1698 { 1699 struct rtl8169_private *tp = netdev_priv(dev); 1700 1701 rtl_set_rx_config_features(tp, features); 1702 1703 if (features & NETIF_F_RXCSUM) 1704 tp->cp_cmd |= RxChkSum; 1705 else 1706 tp->cp_cmd &= ~RxChkSum; 1707 1708 if (!rtl_is_8125(tp)) { 1709 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1710 tp->cp_cmd |= RxVlan; 1711 else 1712 tp->cp_cmd &= ~RxVlan; 1713 } 1714 1715 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1716 rtl_pci_commit(tp); 1717 1718 return 0; 1719 } 1720 1721 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1722 { 1723 return (skb_vlan_tag_present(skb)) ? 1724 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1725 } 1726 1727 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1728 { 1729 u32 opts2 = le32_to_cpu(desc->opts2); 1730 1731 if (opts2 & RxVlanTag) 1732 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1733 } 1734 1735 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1736 void *p) 1737 { 1738 struct rtl8169_private *tp = netdev_priv(dev); 1739 u32 __iomem *data = tp->mmio_addr; 1740 u32 *dw = p; 1741 int i; 1742 1743 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1744 memcpy_fromio(dw++, data++, 4); 1745 } 1746 1747 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1748 "tx_packets", 1749 "rx_packets", 1750 "tx_errors", 1751 "rx_errors", 1752 "rx_missed", 1753 "align_errors", 1754 "tx_single_collisions", 1755 "tx_multi_collisions", 1756 "unicast", 1757 "broadcast", 1758 "multicast", 1759 "tx_aborted", 1760 "tx_underrun", 1761 }; 1762 1763 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1764 { 1765 switch (sset) { 1766 case ETH_SS_STATS: 1767 return ARRAY_SIZE(rtl8169_gstrings); 1768 default: 1769 return -EOPNOTSUPP; 1770 } 1771 } 1772 1773 DECLARE_RTL_COND(rtl_counters_cond) 1774 { 1775 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1776 } 1777 1778 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1779 { 1780 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1781 1782 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1783 rtl_pci_commit(tp); 1784 RTL_W32(tp, CounterAddrLow, cmd); 1785 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1786 1787 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1788 } 1789 1790 static void rtl8169_update_counters(struct rtl8169_private *tp) 1791 { 1792 u8 val = RTL_R8(tp, ChipCmd); 1793 1794 /* 1795 * Some chips are unable to dump tally counters when the receiver 1796 * is disabled. If 0xff chip may be in a PCI power-save state. 1797 */ 1798 if (val & CmdRxEnb && val != 0xff) 1799 rtl8169_do_counters(tp, CounterDump); 1800 } 1801 1802 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1803 { 1804 struct rtl8169_counters *counters = tp->counters; 1805 1806 /* 1807 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1808 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1809 * reset by a power cycle, while the counter values collected by the 1810 * driver are reset at every driver unload/load cycle. 1811 * 1812 * To make sure the HW values returned by @get_stats64 match the SW 1813 * values, we collect the initial values at first open(*) and use them 1814 * as offsets to normalize the values returned by @get_stats64. 1815 * 1816 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1817 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1818 * set at open time by rtl_hw_start. 1819 */ 1820 1821 if (tp->tc_offset.inited) 1822 return; 1823 1824 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1825 rtl8169_do_counters(tp, CounterReset); 1826 } else { 1827 rtl8169_update_counters(tp); 1828 tp->tc_offset.tx_errors = counters->tx_errors; 1829 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1830 tp->tc_offset.tx_aborted = counters->tx_aborted; 1831 tp->tc_offset.rx_missed = counters->rx_missed; 1832 } 1833 1834 tp->tc_offset.inited = true; 1835 } 1836 1837 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1838 struct ethtool_stats *stats, u64 *data) 1839 { 1840 struct rtl8169_private *tp = netdev_priv(dev); 1841 struct rtl8169_counters *counters; 1842 1843 counters = tp->counters; 1844 rtl8169_update_counters(tp); 1845 1846 data[0] = le64_to_cpu(counters->tx_packets); 1847 data[1] = le64_to_cpu(counters->rx_packets); 1848 data[2] = le64_to_cpu(counters->tx_errors); 1849 data[3] = le32_to_cpu(counters->rx_errors); 1850 data[4] = le16_to_cpu(counters->rx_missed); 1851 data[5] = le16_to_cpu(counters->align_errors); 1852 data[6] = le32_to_cpu(counters->tx_one_collision); 1853 data[7] = le32_to_cpu(counters->tx_multi_collision); 1854 data[8] = le64_to_cpu(counters->rx_unicast); 1855 data[9] = le64_to_cpu(counters->rx_broadcast); 1856 data[10] = le32_to_cpu(counters->rx_multicast); 1857 data[11] = le16_to_cpu(counters->tx_aborted); 1858 data[12] = le16_to_cpu(counters->tx_underrun); 1859 } 1860 1861 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1862 { 1863 switch(stringset) { 1864 case ETH_SS_STATS: 1865 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1866 break; 1867 } 1868 } 1869 1870 /* 1871 * Interrupt coalescing 1872 * 1873 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1874 * > 8169, 8168 and 810x line of chipsets 1875 * 1876 * 8169, 8168, and 8136(810x) serial chipsets support it. 1877 * 1878 * > 2 - the Tx timer unit at gigabit speed 1879 * 1880 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1881 * (0xe0) bit 1 and bit 0. 1882 * 1883 * For 8169 1884 * bit[1:0] \ speed 1000M 100M 10M 1885 * 0 0 320ns 2.56us 40.96us 1886 * 0 1 2.56us 20.48us 327.7us 1887 * 1 0 5.12us 40.96us 655.4us 1888 * 1 1 10.24us 81.92us 1.31ms 1889 * 1890 * For the other 1891 * bit[1:0] \ speed 1000M 100M 10M 1892 * 0 0 5us 2.56us 40.96us 1893 * 0 1 40us 20.48us 327.7us 1894 * 1 0 80us 40.96us 655.4us 1895 * 1 1 160us 81.92us 1.31ms 1896 */ 1897 1898 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1899 struct rtl_coalesce_info { 1900 u32 speed; 1901 u32 scale_nsecs[4]; 1902 }; 1903 1904 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1905 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1906 1907 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1908 { SPEED_1000, COALESCE_DELAY(320) }, 1909 { SPEED_100, COALESCE_DELAY(2560) }, 1910 { SPEED_10, COALESCE_DELAY(40960) }, 1911 { 0 }, 1912 }; 1913 1914 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1915 { SPEED_1000, COALESCE_DELAY(5000) }, 1916 { SPEED_100, COALESCE_DELAY(2560) }, 1917 { SPEED_10, COALESCE_DELAY(40960) }, 1918 { 0 }, 1919 }; 1920 #undef COALESCE_DELAY 1921 1922 /* get rx/tx scale vector corresponding to current speed */ 1923 static const struct rtl_coalesce_info * 1924 rtl_coalesce_info(struct rtl8169_private *tp) 1925 { 1926 const struct rtl_coalesce_info *ci; 1927 1928 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1929 ci = rtl_coalesce_info_8169; 1930 else 1931 ci = rtl_coalesce_info_8168_8136; 1932 1933 /* if speed is unknown assume highest one */ 1934 if (tp->phydev->speed == SPEED_UNKNOWN) 1935 return ci; 1936 1937 for (; ci->speed; ci++) { 1938 if (tp->phydev->speed == ci->speed) 1939 return ci; 1940 } 1941 1942 return ERR_PTR(-ELNRNG); 1943 } 1944 1945 static int rtl_get_coalesce(struct net_device *dev, 1946 struct ethtool_coalesce *ec, 1947 struct kernel_ethtool_coalesce *kernel_coal, 1948 struct netlink_ext_ack *extack) 1949 { 1950 struct rtl8169_private *tp = netdev_priv(dev); 1951 const struct rtl_coalesce_info *ci; 1952 u32 scale, c_us, c_fr; 1953 u16 intrmit; 1954 1955 if (rtl_is_8125(tp)) 1956 return -EOPNOTSUPP; 1957 1958 memset(ec, 0, sizeof(*ec)); 1959 1960 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1961 ci = rtl_coalesce_info(tp); 1962 if (IS_ERR(ci)) 1963 return PTR_ERR(ci); 1964 1965 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1966 1967 intrmit = RTL_R16(tp, IntrMitigate); 1968 1969 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1970 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1971 1972 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1973 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1974 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1975 1976 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1977 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1978 1979 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1980 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1981 1982 return 0; 1983 } 1984 1985 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1986 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1987 u16 *cp01) 1988 { 1989 const struct rtl_coalesce_info *ci; 1990 u16 i; 1991 1992 ci = rtl_coalesce_info(tp); 1993 if (IS_ERR(ci)) 1994 return PTR_ERR(ci); 1995 1996 for (i = 0; i < 4; i++) { 1997 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1998 *cp01 = i; 1999 return ci->scale_nsecs[i]; 2000 } 2001 } 2002 2003 return -ERANGE; 2004 } 2005 2006 static int rtl_set_coalesce(struct net_device *dev, 2007 struct ethtool_coalesce *ec, 2008 struct kernel_ethtool_coalesce *kernel_coal, 2009 struct netlink_ext_ack *extack) 2010 { 2011 struct rtl8169_private *tp = netdev_priv(dev); 2012 u32 tx_fr = ec->tx_max_coalesced_frames; 2013 u32 rx_fr = ec->rx_max_coalesced_frames; 2014 u32 coal_usec_max, units; 2015 u16 w = 0, cp01 = 0; 2016 int scale; 2017 2018 if (rtl_is_8125(tp)) 2019 return -EOPNOTSUPP; 2020 2021 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 2022 return -ERANGE; 2023 2024 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 2025 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 2026 if (scale < 0) 2027 return scale; 2028 2029 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 2030 * not only when usecs=0 because of e.g. the following scenario: 2031 * 2032 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2033 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2034 * - then user does `ethtool -C eth0 rx-usecs 100` 2035 * 2036 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2037 * if we want to ignore rx_frames then it has to be set to 0. 2038 */ 2039 if (rx_fr == 1) 2040 rx_fr = 0; 2041 if (tx_fr == 1) 2042 tx_fr = 0; 2043 2044 /* HW requires time limit to be set if frame limit is set */ 2045 if ((tx_fr && !ec->tx_coalesce_usecs) || 2046 (rx_fr && !ec->rx_coalesce_usecs)) 2047 return -EINVAL; 2048 2049 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2050 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2051 2052 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2053 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2054 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2055 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2056 2057 RTL_W16(tp, IntrMitigate, w); 2058 2059 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2060 if (rtl_is_8168evl_up(tp)) { 2061 if (!rx_fr && !tx_fr) 2062 /* disable packet counter */ 2063 tp->cp_cmd |= PktCntrDisable; 2064 else 2065 tp->cp_cmd &= ~PktCntrDisable; 2066 } 2067 2068 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2069 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2070 rtl_pci_commit(tp); 2071 2072 return 0; 2073 } 2074 2075 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2076 { 2077 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2078 2079 switch (tp->mac_version) { 2080 case RTL_GIGA_MAC_VER_46: 2081 case RTL_GIGA_MAC_VER_48: 2082 tp->tx_lpi_timer = timer_val; 2083 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2084 break; 2085 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2086 tp->tx_lpi_timer = timer_val; 2087 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2088 break; 2089 default: 2090 break; 2091 } 2092 } 2093 2094 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2095 { 2096 unsigned int speed = tp->phydev->speed; 2097 unsigned int timer = tp->tx_lpi_timer; 2098 2099 if (!timer || speed == SPEED_UNKNOWN) 2100 return 0; 2101 2102 /* tx_lpi_timer value is in bytes */ 2103 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2104 } 2105 2106 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2107 { 2108 struct rtl8169_private *tp = netdev_priv(dev); 2109 int ret; 2110 2111 if (!rtl_supports_eee(tp)) 2112 return -EOPNOTSUPP; 2113 2114 ret = phy_ethtool_get_eee(tp->phydev, data); 2115 if (ret) 2116 return ret; 2117 2118 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2119 2120 return 0; 2121 } 2122 2123 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2124 { 2125 struct rtl8169_private *tp = netdev_priv(dev); 2126 2127 if (!rtl_supports_eee(tp)) 2128 return -EOPNOTSUPP; 2129 2130 return phy_ethtool_set_eee(tp->phydev, data); 2131 } 2132 2133 static void rtl8169_get_ringparam(struct net_device *dev, 2134 struct ethtool_ringparam *data, 2135 struct kernel_ethtool_ringparam *kernel_data, 2136 struct netlink_ext_ack *extack) 2137 { 2138 data->rx_max_pending = NUM_RX_DESC; 2139 data->rx_pending = NUM_RX_DESC; 2140 data->tx_max_pending = NUM_TX_DESC; 2141 data->tx_pending = NUM_TX_DESC; 2142 } 2143 2144 static void rtl8169_get_pause_stats(struct net_device *dev, 2145 struct ethtool_pause_stats *pause_stats) 2146 { 2147 struct rtl8169_private *tp = netdev_priv(dev); 2148 2149 if (!rtl_is_8125(tp)) 2150 return; 2151 2152 rtl8169_update_counters(tp); 2153 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on); 2154 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on); 2155 } 2156 2157 static void rtl8169_get_pauseparam(struct net_device *dev, 2158 struct ethtool_pauseparam *data) 2159 { 2160 struct rtl8169_private *tp = netdev_priv(dev); 2161 bool tx_pause, rx_pause; 2162 2163 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2164 2165 data->autoneg = tp->phydev->autoneg; 2166 data->tx_pause = tx_pause ? 1 : 0; 2167 data->rx_pause = rx_pause ? 1 : 0; 2168 } 2169 2170 static int rtl8169_set_pauseparam(struct net_device *dev, 2171 struct ethtool_pauseparam *data) 2172 { 2173 struct rtl8169_private *tp = netdev_priv(dev); 2174 2175 if (dev->mtu > ETH_DATA_LEN) 2176 return -EOPNOTSUPP; 2177 2178 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2179 2180 return 0; 2181 } 2182 2183 static void rtl8169_get_eth_mac_stats(struct net_device *dev, 2184 struct ethtool_eth_mac_stats *mac_stats) 2185 { 2186 struct rtl8169_private *tp = netdev_priv(dev); 2187 2188 rtl8169_update_counters(tp); 2189 2190 mac_stats->FramesTransmittedOK = 2191 le64_to_cpu(tp->counters->tx_packets); 2192 mac_stats->SingleCollisionFrames = 2193 le32_to_cpu(tp->counters->tx_one_collision); 2194 mac_stats->MultipleCollisionFrames = 2195 le32_to_cpu(tp->counters->tx_multi_collision); 2196 mac_stats->FramesReceivedOK = 2197 le64_to_cpu(tp->counters->rx_packets); 2198 mac_stats->AlignmentErrors = 2199 le16_to_cpu(tp->counters->align_errors); 2200 mac_stats->FramesLostDueToIntMACXmitError = 2201 le64_to_cpu(tp->counters->tx_errors); 2202 mac_stats->BroadcastFramesReceivedOK = 2203 le64_to_cpu(tp->counters->rx_broadcast); 2204 mac_stats->MulticastFramesReceivedOK = 2205 le32_to_cpu(tp->counters->rx_multicast); 2206 2207 if (!rtl_is_8125(tp)) 2208 return; 2209 2210 mac_stats->AlignmentErrors = 2211 le32_to_cpu(tp->counters->align_errors32); 2212 mac_stats->OctetsTransmittedOK = 2213 le64_to_cpu(tp->counters->tx_octets); 2214 mac_stats->LateCollisions = 2215 le32_to_cpu(tp->counters->tx_late_collision); 2216 mac_stats->FramesAbortedDueToXSColls = 2217 le32_to_cpu(tp->counters->tx_aborted32); 2218 mac_stats->OctetsReceivedOK = 2219 le64_to_cpu(tp->counters->rx_octets); 2220 mac_stats->FramesLostDueToIntMACRcvError = 2221 le32_to_cpu(tp->counters->rx_mac_error); 2222 mac_stats->MulticastFramesXmittedOK = 2223 le64_to_cpu(tp->counters->tx_multicast64); 2224 mac_stats->BroadcastFramesXmittedOK = 2225 le64_to_cpu(tp->counters->tx_broadcast64); 2226 mac_stats->MulticastFramesReceivedOK = 2227 le64_to_cpu(tp->counters->rx_multicast64); 2228 mac_stats->FrameTooLongErrors = 2229 le32_to_cpu(tp->counters->rx_frame_too_long); 2230 } 2231 2232 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, 2233 struct ethtool_eth_ctrl_stats *ctrl_stats) 2234 { 2235 struct rtl8169_private *tp = netdev_priv(dev); 2236 2237 if (!rtl_is_8125(tp)) 2238 return; 2239 2240 rtl8169_update_counters(tp); 2241 2242 ctrl_stats->UnsupportedOpcodesReceived = 2243 le32_to_cpu(tp->counters->rx_unknown_opcode); 2244 } 2245 2246 static const struct ethtool_ops rtl8169_ethtool_ops = { 2247 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2248 ETHTOOL_COALESCE_MAX_FRAMES, 2249 .get_drvinfo = rtl8169_get_drvinfo, 2250 .get_regs_len = rtl8169_get_regs_len, 2251 .get_link = ethtool_op_get_link, 2252 .get_coalesce = rtl_get_coalesce, 2253 .set_coalesce = rtl_set_coalesce, 2254 .get_regs = rtl8169_get_regs, 2255 .get_wol = rtl8169_get_wol, 2256 .set_wol = rtl8169_set_wol, 2257 .get_strings = rtl8169_get_strings, 2258 .get_sset_count = rtl8169_get_sset_count, 2259 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2260 .get_ts_info = ethtool_op_get_ts_info, 2261 .nway_reset = phy_ethtool_nway_reset, 2262 .get_eee = rtl8169_get_eee, 2263 .set_eee = rtl8169_set_eee, 2264 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2265 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2266 .get_ringparam = rtl8169_get_ringparam, 2267 .get_pause_stats = rtl8169_get_pause_stats, 2268 .get_pauseparam = rtl8169_get_pauseparam, 2269 .set_pauseparam = rtl8169_set_pauseparam, 2270 .get_eth_mac_stats = rtl8169_get_eth_mac_stats, 2271 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, 2272 }; 2273 2274 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2275 { 2276 /* 2277 * The driver currently handles the 8168Bf and the 8168Be identically 2278 * but they can be identified more specifically through the test below 2279 * if needed: 2280 * 2281 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2282 * 2283 * Same thing for the 8101Eb and the 8101Ec: 2284 * 2285 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2286 */ 2287 static const struct rtl_mac_info { 2288 u16 mask; 2289 u16 val; 2290 enum mac_version ver; 2291 } mac_info[] = { 2292 /* 8126A family. */ 2293 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 }, 2294 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2295 2296 /* 8125D family. */ 2297 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, 2298 2299 /* 8125B family. */ 2300 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2301 2302 /* 8125A family. */ 2303 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2304 /* It seems only XID 609 made it to the mass market. 2305 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2306 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2307 */ 2308 2309 /* RTL8117 */ 2310 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2311 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2312 2313 /* 8168EP family. */ 2314 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2315 /* It seems this chip version never made it to 2316 * the wild. Let's disable detection. 2317 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2318 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2319 */ 2320 2321 /* 8168H family. */ 2322 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2323 /* It seems this chip version never made it to 2324 * the wild. Let's disable detection. 2325 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2326 */ 2327 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 2328 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, 2329 2330 /* 8168G family. */ 2331 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2332 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2333 /* It seems this chip version never made it to 2334 * the wild. Let's disable detection. 2335 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2336 */ 2337 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2338 2339 /* 8168F family. */ 2340 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2341 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2342 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2343 2344 /* 8168E family. */ 2345 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2346 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2347 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2348 2349 /* 8168D family. */ 2350 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2351 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2352 2353 /* 8168DP family. */ 2354 /* It seems this early RTL8168dp version never made it to 2355 * the wild. Support has been removed. 2356 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2357 */ 2358 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2359 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2360 2361 /* 8168C family. */ 2362 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2363 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2364 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2365 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2366 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2367 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2368 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2369 2370 /* 8168B family. */ 2371 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2372 /* This one is very old and rare, let's see if anybody complains. 2373 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2374 */ 2375 2376 /* 8101 family. */ 2377 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2378 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2379 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2380 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2381 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2382 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2383 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2384 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2385 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2386 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2387 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2388 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2389 2390 /* 8110 family. */ 2391 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2392 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2393 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2394 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2395 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2396 2397 /* Catch-all */ 2398 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2399 }; 2400 const struct rtl_mac_info *p = mac_info; 2401 enum mac_version ver; 2402 2403 while ((xid & p->mask) != p->val) 2404 p++; 2405 ver = p->ver; 2406 2407 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2408 if (ver == RTL_GIGA_MAC_VER_42) 2409 ver = RTL_GIGA_MAC_VER_43; 2410 else if (ver == RTL_GIGA_MAC_VER_46) 2411 ver = RTL_GIGA_MAC_VER_48; 2412 } 2413 2414 return ver; 2415 } 2416 2417 static void rtl_release_firmware(struct rtl8169_private *tp) 2418 { 2419 if (tp->rtl_fw) { 2420 rtl_fw_release_firmware(tp->rtl_fw); 2421 kfree(tp->rtl_fw); 2422 tp->rtl_fw = NULL; 2423 } 2424 } 2425 2426 void r8169_apply_firmware(struct rtl8169_private *tp) 2427 { 2428 int val; 2429 2430 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2431 if (tp->rtl_fw) { 2432 rtl_fw_write_firmware(tp, tp->rtl_fw); 2433 /* At least one firmware doesn't reset tp->ocp_base. */ 2434 tp->ocp_base = OCP_STD_PHY_BASE; 2435 2436 /* PHY soft reset may still be in progress */ 2437 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2438 !(val & BMCR_RESET), 2439 50000, 600000, true); 2440 } 2441 } 2442 2443 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2444 { 2445 /* Adjust EEE LED frequency */ 2446 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2447 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2448 2449 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2450 } 2451 2452 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2453 { 2454 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2455 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2456 } 2457 2458 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2459 { 2460 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2461 } 2462 2463 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2464 { 2465 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2466 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2467 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2468 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2469 } 2470 2471 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2472 { 2473 u16 data1, data2, ioffset; 2474 2475 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2476 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2477 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2478 2479 ioffset = (data2 >> 1) & 0x7ff8; 2480 ioffset |= data2 & 0x0007; 2481 if (data1 & BIT(7)) 2482 ioffset |= BIT(15); 2483 2484 return ioffset; 2485 } 2486 2487 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2488 { 2489 set_bit(flag, tp->wk.flags); 2490 if (!schedule_work(&tp->wk.work)) 2491 clear_bit(flag, tp->wk.flags); 2492 } 2493 2494 static void rtl8169_init_phy(struct rtl8169_private *tp) 2495 { 2496 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2497 2498 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2499 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2500 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2501 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2502 RTL_W8(tp, 0x82, 0x01); 2503 } 2504 2505 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2506 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2507 tp->pci_dev->subsystem_device == 0xe000) 2508 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2509 2510 /* We may have called phy_speed_down before */ 2511 phy_speed_up(tp->phydev); 2512 2513 genphy_soft_reset(tp->phydev); 2514 } 2515 2516 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2517 { 2518 rtl_unlock_config_regs(tp); 2519 2520 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2521 rtl_pci_commit(tp); 2522 2523 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2524 rtl_pci_commit(tp); 2525 2526 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2527 rtl_rar_exgmac_set(tp, addr); 2528 2529 rtl_lock_config_regs(tp); 2530 } 2531 2532 static int rtl_set_mac_address(struct net_device *dev, void *p) 2533 { 2534 struct rtl8169_private *tp = netdev_priv(dev); 2535 int ret; 2536 2537 ret = eth_mac_addr(dev, p); 2538 if (ret) 2539 return ret; 2540 2541 rtl_rar_set(tp, dev->dev_addr); 2542 2543 return 0; 2544 } 2545 2546 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2547 { 2548 switch (tp->mac_version) { 2549 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2550 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2551 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2552 break; 2553 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2554 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2555 case RTL_GIGA_MAC_VER_38: 2556 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2557 break; 2558 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2559 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2560 break; 2561 case RTL_GIGA_MAC_VER_61: 2562 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2563 break; 2564 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2565 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2566 RX_PAUSE_SLOT_ON); 2567 break; 2568 default: 2569 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2570 break; 2571 } 2572 } 2573 2574 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2575 { 2576 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2577 } 2578 2579 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2580 { 2581 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2582 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2583 } 2584 2585 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2586 { 2587 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2588 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2589 } 2590 2591 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2592 { 2593 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2594 } 2595 2596 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2597 { 2598 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2599 } 2600 2601 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2602 { 2603 RTL_W8(tp, MaxTxPacketSize, 0x24); 2604 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2605 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2606 } 2607 2608 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2609 { 2610 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2611 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2612 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2613 } 2614 2615 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2616 { 2617 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2618 } 2619 2620 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2621 { 2622 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2623 } 2624 2625 static void rtl_jumbo_config(struct rtl8169_private *tp) 2626 { 2627 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2628 int readrq = 4096; 2629 2630 rtl_unlock_config_regs(tp); 2631 switch (tp->mac_version) { 2632 case RTL_GIGA_MAC_VER_17: 2633 if (jumbo) { 2634 readrq = 512; 2635 r8168b_1_hw_jumbo_enable(tp); 2636 } else { 2637 r8168b_1_hw_jumbo_disable(tp); 2638 } 2639 break; 2640 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2641 if (jumbo) { 2642 readrq = 512; 2643 r8168c_hw_jumbo_enable(tp); 2644 } else { 2645 r8168c_hw_jumbo_disable(tp); 2646 } 2647 break; 2648 case RTL_GIGA_MAC_VER_28: 2649 if (jumbo) 2650 r8168dp_hw_jumbo_enable(tp); 2651 else 2652 r8168dp_hw_jumbo_disable(tp); 2653 break; 2654 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2655 if (jumbo) 2656 r8168e_hw_jumbo_enable(tp); 2657 else 2658 r8168e_hw_jumbo_disable(tp); 2659 break; 2660 default: 2661 break; 2662 } 2663 rtl_lock_config_regs(tp); 2664 2665 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2666 pcie_set_readrq(tp->pci_dev, readrq); 2667 2668 /* Chip doesn't support pause in jumbo mode */ 2669 if (jumbo) { 2670 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2671 tp->phydev->advertising); 2672 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2673 tp->phydev->advertising); 2674 phy_start_aneg(tp->phydev); 2675 } 2676 } 2677 2678 DECLARE_RTL_COND(rtl_chipcmd_cond) 2679 { 2680 return RTL_R8(tp, ChipCmd) & CmdReset; 2681 } 2682 2683 static void rtl_hw_reset(struct rtl8169_private *tp) 2684 { 2685 RTL_W8(tp, ChipCmd, CmdReset); 2686 2687 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2688 } 2689 2690 static void rtl_request_firmware(struct rtl8169_private *tp) 2691 { 2692 struct rtl_fw *rtl_fw; 2693 2694 /* firmware loaded already or no firmware available */ 2695 if (tp->rtl_fw || !tp->fw_name) 2696 return; 2697 2698 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2699 if (!rtl_fw) 2700 return; 2701 2702 rtl_fw->phy_write = rtl_writephy; 2703 rtl_fw->phy_read = rtl_readphy; 2704 rtl_fw->mac_mcu_write = mac_mcu_write; 2705 rtl_fw->mac_mcu_read = mac_mcu_read; 2706 rtl_fw->fw_name = tp->fw_name; 2707 rtl_fw->dev = tp_to_dev(tp); 2708 2709 if (rtl_fw_request_firmware(rtl_fw)) 2710 kfree(rtl_fw); 2711 else 2712 tp->rtl_fw = rtl_fw; 2713 } 2714 2715 static void rtl_rx_close(struct rtl8169_private *tp) 2716 { 2717 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2718 } 2719 2720 DECLARE_RTL_COND(rtl_npq_cond) 2721 { 2722 return RTL_R8(tp, TxPoll) & NPQ; 2723 } 2724 2725 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2726 { 2727 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2728 } 2729 2730 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2731 { 2732 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2733 } 2734 2735 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2736 { 2737 /* IntrMitigate has new functionality on RTL8125 */ 2738 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2739 } 2740 2741 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2742 { 2743 switch (tp->mac_version) { 2744 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2745 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2746 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2747 break; 2748 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2749 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2750 break; 2751 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2752 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2753 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2754 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2755 break; 2756 default: 2757 break; 2758 } 2759 } 2760 2761 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2762 { 2763 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2764 } 2765 2766 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2767 { 2768 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2769 fsleep(2000); 2770 rtl_wait_txrx_fifo_empty(tp); 2771 } 2772 2773 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2774 { 2775 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2776 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2777 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2778 2779 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2780 rtl_disable_rxdvgate(tp); 2781 } 2782 2783 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2784 { 2785 if (tp->dash_enabled) 2786 return; 2787 2788 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2789 tp->mac_version == RTL_GIGA_MAC_VER_33) 2790 rtl_ephy_write(tp, 0x19, 0xff64); 2791 2792 if (device_may_wakeup(tp_to_dev(tp))) { 2793 phy_speed_down(tp->phydev, false); 2794 rtl_wol_enable_rx(tp); 2795 } 2796 } 2797 2798 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2799 { 2800 u32 val = TX_DMA_BURST << TxDMAShift | 2801 InterFrameGap << TxInterFrameGapShift; 2802 2803 if (rtl_is_8168evl_up(tp)) 2804 val |= TXCFG_AUTO_FIFO; 2805 2806 RTL_W32(tp, TxConfig, val); 2807 } 2808 2809 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2810 { 2811 /* Low hurts. Let's disable the filtering. */ 2812 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2813 } 2814 2815 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2816 { 2817 /* 2818 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2819 * register to be written before TxDescAddrLow to work. 2820 * Switching from MMIO to I/O access fixes the issue as well. 2821 */ 2822 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2823 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2824 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2825 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2826 } 2827 2828 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2829 { 2830 u32 val; 2831 2832 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2833 val = 0x000fff00; 2834 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2835 val = 0x00ffff00; 2836 else 2837 return; 2838 2839 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2840 val |= 0xff; 2841 2842 RTL_W32(tp, 0x7c, val); 2843 } 2844 2845 static void rtl_set_rx_mode(struct net_device *dev) 2846 { 2847 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2848 /* Multicast hash filter */ 2849 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2850 struct rtl8169_private *tp = netdev_priv(dev); 2851 u32 tmp; 2852 2853 if (dev->flags & IFF_PROMISC) { 2854 rx_mode |= AcceptAllPhys; 2855 } else if (!(dev->flags & IFF_MULTICAST)) { 2856 rx_mode &= ~AcceptMulticast; 2857 } else if (dev->flags & IFF_ALLMULTI || 2858 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2859 /* accept all multicasts */ 2860 } else if (netdev_mc_empty(dev)) { 2861 rx_mode &= ~AcceptMulticast; 2862 } else { 2863 struct netdev_hw_addr *ha; 2864 2865 mc_filter[1] = mc_filter[0] = 0; 2866 netdev_for_each_mc_addr(ha, dev) { 2867 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2868 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2869 } 2870 2871 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2872 tmp = mc_filter[0]; 2873 mc_filter[0] = swab32(mc_filter[1]); 2874 mc_filter[1] = swab32(tmp); 2875 } 2876 } 2877 2878 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2879 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2880 2881 tmp = RTL_R32(tp, RxConfig); 2882 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2883 } 2884 2885 DECLARE_RTL_COND(rtl_csiar_cond) 2886 { 2887 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2888 } 2889 2890 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2891 { 2892 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2893 2894 RTL_W32(tp, CSIDR, value); 2895 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2896 CSIAR_BYTE_ENABLE | func << 16); 2897 2898 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2899 } 2900 2901 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2902 { 2903 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2904 2905 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2906 CSIAR_BYTE_ENABLE); 2907 2908 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2909 RTL_R32(tp, CSIDR) : ~0; 2910 } 2911 2912 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2913 { 2914 struct pci_dev *pdev = tp->pci_dev; 2915 u32 csi; 2916 2917 /* According to Realtek the value at config space address 0x070f 2918 * controls the L0s/L1 entrance latency. We try standard ECAM access 2919 * first and if it fails fall back to CSI. 2920 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2921 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2922 */ 2923 if (pdev->cfg_size > 0x070f && 2924 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2925 return; 2926 2927 netdev_notice_once(tp->dev, 2928 "No native access to PCI extended config space, falling back to CSI\n"); 2929 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2930 rtl_csi_write(tp, 0x070c, csi | val << 24); 2931 } 2932 2933 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2934 { 2935 /* L0 7us, L1 16us */ 2936 rtl_set_aspm_entry_latency(tp, 0x27); 2937 } 2938 2939 struct ephy_info { 2940 unsigned int offset; 2941 u16 mask; 2942 u16 bits; 2943 }; 2944 2945 static void __rtl_ephy_init(struct rtl8169_private *tp, 2946 const struct ephy_info *e, int len) 2947 { 2948 u16 w; 2949 2950 while (len-- > 0) { 2951 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2952 rtl_ephy_write(tp, e->offset, w); 2953 e++; 2954 } 2955 } 2956 2957 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2958 2959 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2960 { 2961 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2962 PCI_EXP_LNKCTL_CLKREQ_EN); 2963 } 2964 2965 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2966 { 2967 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2968 PCI_EXP_LNKCTL_CLKREQ_EN); 2969 } 2970 2971 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2972 { 2973 /* work around an issue when PCI reset occurs during L2/L3 state */ 2974 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2975 } 2976 2977 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2978 { 2979 /* Bits control which events trigger ASPM L1 exit: 2980 * Bit 12: rxdv 2981 * Bit 11: ltr_msg 2982 * Bit 10: txdma_poll 2983 * Bit 9: xadm 2984 * Bit 8: pktavi 2985 * Bit 7: txpla 2986 */ 2987 switch (tp->mac_version) { 2988 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2989 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2990 break; 2991 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2992 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2993 break; 2994 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2995 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2996 break; 2997 default: 2998 break; 2999 } 3000 } 3001 3002 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 3003 { 3004 switch (tp->mac_version) { 3005 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3006 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 3007 break; 3008 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 3009 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 3010 break; 3011 default: 3012 break; 3013 } 3014 } 3015 3016 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 3017 { 3018 u8 val8; 3019 3020 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 3021 return; 3022 3023 /* Don't enable ASPM in the chip if OS can't control ASPM */ 3024 if (enable && tp->aspm_manageable) { 3025 /* On these chip versions ASPM can even harm 3026 * bus communication of other PCI devices. 3027 */ 3028 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 3029 tp->mac_version == RTL_GIGA_MAC_VER_43) 3030 return; 3031 3032 rtl_mod_config5(tp, 0, ASPM_en); 3033 switch (tp->mac_version) { 3034 case RTL_GIGA_MAC_VER_65: 3035 case RTL_GIGA_MAC_VER_66: 3036 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 3037 RTL_W8(tp, INT_CFG0_8125, val8); 3038 break; 3039 default: 3040 rtl_mod_config2(tp, 0, ClkReqEn); 3041 break; 3042 } 3043 3044 switch (tp->mac_version) { 3045 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 3046 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 3047 /* reset ephy tx/rx disable timer */ 3048 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 3049 /* chip can trigger L1.2 */ 3050 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 3051 break; 3052 default: 3053 break; 3054 } 3055 } else { 3056 switch (tp->mac_version) { 3057 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 3058 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 3059 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 3060 break; 3061 default: 3062 break; 3063 } 3064 3065 switch (tp->mac_version) { 3066 case RTL_GIGA_MAC_VER_65: 3067 case RTL_GIGA_MAC_VER_66: 3068 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 3069 RTL_W8(tp, INT_CFG0_8125, val8); 3070 break; 3071 default: 3072 rtl_mod_config2(tp, ClkReqEn, 0); 3073 break; 3074 } 3075 rtl_mod_config5(tp, ASPM_en, 0); 3076 } 3077 } 3078 3079 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 3080 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 3081 { 3082 /* Usage of dynamic vs. static FIFO is controlled by bit 3083 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 3084 */ 3085 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 3086 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 3087 } 3088 3089 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3090 u8 low, u8 high) 3091 { 3092 /* FIFO thresholds for pause flow control */ 3093 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3094 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3095 } 3096 3097 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3098 { 3099 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3100 } 3101 3102 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3103 { 3104 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3105 3106 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3107 3108 rtl_disable_clock_request(tp); 3109 } 3110 3111 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3112 { 3113 static const struct ephy_info e_info_8168cp[] = { 3114 { 0x01, 0, 0x0001 }, 3115 { 0x02, 0x0800, 0x1000 }, 3116 { 0x03, 0, 0x0042 }, 3117 { 0x06, 0x0080, 0x0000 }, 3118 { 0x07, 0, 0x2000 } 3119 }; 3120 3121 rtl_set_def_aspm_entry_latency(tp); 3122 3123 rtl_ephy_init(tp, e_info_8168cp); 3124 3125 __rtl_hw_start_8168cp(tp); 3126 } 3127 3128 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3129 { 3130 rtl_set_def_aspm_entry_latency(tp); 3131 3132 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3133 } 3134 3135 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3136 { 3137 rtl_set_def_aspm_entry_latency(tp); 3138 3139 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3140 3141 /* Magic. */ 3142 RTL_W8(tp, DBG_REG, 0x20); 3143 } 3144 3145 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3146 { 3147 static const struct ephy_info e_info_8168c_1[] = { 3148 { 0x02, 0x0800, 0x1000 }, 3149 { 0x03, 0, 0x0002 }, 3150 { 0x06, 0x0080, 0x0000 } 3151 }; 3152 3153 rtl_set_def_aspm_entry_latency(tp); 3154 3155 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3156 3157 rtl_ephy_init(tp, e_info_8168c_1); 3158 3159 __rtl_hw_start_8168cp(tp); 3160 } 3161 3162 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3163 { 3164 static const struct ephy_info e_info_8168c_2[] = { 3165 { 0x01, 0, 0x0001 }, 3166 { 0x03, 0x0400, 0x0020 } 3167 }; 3168 3169 rtl_set_def_aspm_entry_latency(tp); 3170 3171 rtl_ephy_init(tp, e_info_8168c_2); 3172 3173 __rtl_hw_start_8168cp(tp); 3174 } 3175 3176 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3177 { 3178 rtl_set_def_aspm_entry_latency(tp); 3179 3180 __rtl_hw_start_8168cp(tp); 3181 } 3182 3183 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3184 { 3185 rtl_set_def_aspm_entry_latency(tp); 3186 3187 rtl_disable_clock_request(tp); 3188 } 3189 3190 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3191 { 3192 static const struct ephy_info e_info_8168d_4[] = { 3193 { 0x0b, 0x0000, 0x0048 }, 3194 { 0x19, 0x0020, 0x0050 }, 3195 { 0x0c, 0x0100, 0x0020 }, 3196 { 0x10, 0x0004, 0x0000 }, 3197 }; 3198 3199 rtl_set_def_aspm_entry_latency(tp); 3200 3201 rtl_ephy_init(tp, e_info_8168d_4); 3202 3203 rtl_enable_clock_request(tp); 3204 } 3205 3206 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3207 { 3208 static const struct ephy_info e_info_8168e_1[] = { 3209 { 0x00, 0x0200, 0x0100 }, 3210 { 0x00, 0x0000, 0x0004 }, 3211 { 0x06, 0x0002, 0x0001 }, 3212 { 0x06, 0x0000, 0x0030 }, 3213 { 0x07, 0x0000, 0x2000 }, 3214 { 0x00, 0x0000, 0x0020 }, 3215 { 0x03, 0x5800, 0x2000 }, 3216 { 0x03, 0x0000, 0x0001 }, 3217 { 0x01, 0x0800, 0x1000 }, 3218 { 0x07, 0x0000, 0x4000 }, 3219 { 0x1e, 0x0000, 0x2000 }, 3220 { 0x19, 0xffff, 0xfe6c }, 3221 { 0x0a, 0x0000, 0x0040 } 3222 }; 3223 3224 rtl_set_def_aspm_entry_latency(tp); 3225 3226 rtl_ephy_init(tp, e_info_8168e_1); 3227 3228 rtl_disable_clock_request(tp); 3229 3230 /* Reset tx FIFO pointer */ 3231 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3232 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3233 3234 rtl_mod_config5(tp, Spi_en, 0); 3235 } 3236 3237 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3238 { 3239 static const struct ephy_info e_info_8168e_2[] = { 3240 { 0x09, 0x0000, 0x0080 }, 3241 { 0x19, 0x0000, 0x0224 }, 3242 { 0x00, 0x0000, 0x0004 }, 3243 { 0x0c, 0x3df0, 0x0200 }, 3244 }; 3245 3246 rtl_set_def_aspm_entry_latency(tp); 3247 3248 rtl_ephy_init(tp, e_info_8168e_2); 3249 3250 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3251 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3252 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3253 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3254 rtl_reset_packet_filter(tp); 3255 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3256 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3257 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3258 3259 rtl_disable_clock_request(tp); 3260 3261 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3262 3263 rtl8168_config_eee_mac(tp); 3264 3265 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3266 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3267 rtl_mod_config5(tp, Spi_en, 0); 3268 } 3269 3270 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3271 { 3272 rtl_set_def_aspm_entry_latency(tp); 3273 3274 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3275 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3276 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3277 rtl_reset_packet_filter(tp); 3278 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3279 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3280 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3281 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3282 3283 rtl_disable_clock_request(tp); 3284 3285 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3286 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3287 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3288 rtl_mod_config5(tp, Spi_en, 0); 3289 3290 rtl8168_config_eee_mac(tp); 3291 } 3292 3293 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3294 { 3295 static const struct ephy_info e_info_8168f_1[] = { 3296 { 0x06, 0x00c0, 0x0020 }, 3297 { 0x08, 0x0001, 0x0002 }, 3298 { 0x09, 0x0000, 0x0080 }, 3299 { 0x19, 0x0000, 0x0224 }, 3300 { 0x00, 0x0000, 0x0008 }, 3301 { 0x0c, 0x3df0, 0x0200 }, 3302 }; 3303 3304 rtl_hw_start_8168f(tp); 3305 3306 rtl_ephy_init(tp, e_info_8168f_1); 3307 } 3308 3309 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3310 { 3311 static const struct ephy_info e_info_8168f_1[] = { 3312 { 0x06, 0x00c0, 0x0020 }, 3313 { 0x0f, 0xffff, 0x5200 }, 3314 { 0x19, 0x0000, 0x0224 }, 3315 { 0x00, 0x0000, 0x0008 }, 3316 { 0x0c, 0x3df0, 0x0200 }, 3317 }; 3318 3319 rtl_hw_start_8168f(tp); 3320 rtl_pcie_state_l2l3_disable(tp); 3321 3322 rtl_ephy_init(tp, e_info_8168f_1); 3323 } 3324 3325 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3326 { 3327 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3328 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3329 3330 rtl_set_def_aspm_entry_latency(tp); 3331 3332 rtl_reset_packet_filter(tp); 3333 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3334 3335 rtl_disable_rxdvgate(tp); 3336 3337 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3338 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3339 3340 rtl8168_config_eee_mac(tp); 3341 3342 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3343 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3344 3345 rtl_pcie_state_l2l3_disable(tp); 3346 } 3347 3348 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3349 { 3350 static const struct ephy_info e_info_8168g_1[] = { 3351 { 0x00, 0x0008, 0x0000 }, 3352 { 0x0c, 0x3ff0, 0x0820 }, 3353 { 0x1e, 0x0000, 0x0001 }, 3354 { 0x19, 0x8000, 0x0000 } 3355 }; 3356 3357 rtl_hw_start_8168g(tp); 3358 rtl_ephy_init(tp, e_info_8168g_1); 3359 } 3360 3361 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3362 { 3363 static const struct ephy_info e_info_8168g_2[] = { 3364 { 0x00, 0x0008, 0x0000 }, 3365 { 0x0c, 0x3ff0, 0x0820 }, 3366 { 0x19, 0xffff, 0x7c00 }, 3367 { 0x1e, 0xffff, 0x20eb }, 3368 { 0x0d, 0xffff, 0x1666 }, 3369 { 0x00, 0xffff, 0x10a3 }, 3370 { 0x06, 0xffff, 0xf050 }, 3371 { 0x04, 0x0000, 0x0010 }, 3372 { 0x1d, 0x4000, 0x0000 }, 3373 }; 3374 3375 rtl_hw_start_8168g(tp); 3376 rtl_ephy_init(tp, e_info_8168g_2); 3377 } 3378 3379 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3380 { 3381 static const u16 fix_data[] = { 3382 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3383 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3384 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3385 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3386 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3387 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3388 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3389 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3390 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3391 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3392 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3393 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3394 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3395 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3396 }; 3397 unsigned long flags; 3398 int i; 3399 3400 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3401 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3402 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3403 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3404 } 3405 3406 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3407 { 3408 static const struct ephy_info e_info_8411_2[] = { 3409 { 0x00, 0x0008, 0x0000 }, 3410 { 0x0c, 0x37d0, 0x0820 }, 3411 { 0x1e, 0x0000, 0x0001 }, 3412 { 0x19, 0x8021, 0x0000 }, 3413 { 0x1e, 0x0000, 0x2000 }, 3414 { 0x0d, 0x0100, 0x0200 }, 3415 { 0x00, 0x0000, 0x0080 }, 3416 { 0x06, 0x0000, 0x0010 }, 3417 { 0x04, 0x0000, 0x0010 }, 3418 { 0x1d, 0x0000, 0x4000 }, 3419 }; 3420 3421 rtl_hw_start_8168g(tp); 3422 3423 rtl_ephy_init(tp, e_info_8411_2); 3424 3425 /* The following Realtek-provided magic fixes an issue with the RX unit 3426 * getting confused after the PHY having been powered-down. 3427 */ 3428 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3429 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3430 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3431 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3432 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3433 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3434 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3435 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3436 mdelay(3); 3437 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3438 3439 rtl8411b_fix_phy_down(tp); 3440 3441 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3442 3443 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3444 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3445 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3446 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3447 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3448 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3449 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3450 } 3451 3452 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3453 { 3454 static const struct ephy_info e_info_8168h_1[] = { 3455 { 0x1e, 0x0800, 0x0001 }, 3456 { 0x1d, 0x0000, 0x0800 }, 3457 { 0x05, 0xffff, 0x2089 }, 3458 { 0x06, 0xffff, 0x5881 }, 3459 { 0x04, 0xffff, 0x854a }, 3460 { 0x01, 0xffff, 0x068b } 3461 }; 3462 int rg_saw_cnt; 3463 3464 rtl_ephy_init(tp, e_info_8168h_1); 3465 3466 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3467 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3468 3469 rtl_set_def_aspm_entry_latency(tp); 3470 3471 rtl_reset_packet_filter(tp); 3472 3473 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3474 3475 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3476 3477 rtl_disable_rxdvgate(tp); 3478 3479 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3480 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3481 3482 rtl8168_config_eee_mac(tp); 3483 3484 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3485 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3486 3487 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3488 3489 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3490 3491 rtl_pcie_state_l2l3_disable(tp); 3492 3493 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3494 if (rg_saw_cnt > 0) { 3495 u16 sw_cnt_1ms_ini; 3496 3497 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3498 sw_cnt_1ms_ini &= 0x0fff; 3499 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3500 } 3501 3502 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3503 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3504 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3505 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3506 3507 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3508 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3509 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3510 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3511 } 3512 3513 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3514 { 3515 rtl8168ep_stop_cmac(tp); 3516 3517 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3518 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3519 3520 rtl_set_def_aspm_entry_latency(tp); 3521 3522 rtl_reset_packet_filter(tp); 3523 3524 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3525 3526 rtl_disable_rxdvgate(tp); 3527 3528 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3529 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3530 3531 rtl8168_config_eee_mac(tp); 3532 3533 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3534 3535 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3536 3537 rtl_pcie_state_l2l3_disable(tp); 3538 } 3539 3540 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3541 { 3542 static const struct ephy_info e_info_8168ep_3[] = { 3543 { 0x00, 0x0000, 0x0080 }, 3544 { 0x0d, 0x0100, 0x0200 }, 3545 { 0x19, 0x8021, 0x0000 }, 3546 { 0x1e, 0x0000, 0x2000 }, 3547 }; 3548 3549 rtl_ephy_init(tp, e_info_8168ep_3); 3550 3551 rtl_hw_start_8168ep(tp); 3552 3553 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3554 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3555 3556 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3557 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3558 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3559 } 3560 3561 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3562 { 3563 static const struct ephy_info e_info_8117[] = { 3564 { 0x19, 0x0040, 0x1100 }, 3565 { 0x59, 0x0040, 0x1100 }, 3566 }; 3567 int rg_saw_cnt; 3568 3569 rtl8168ep_stop_cmac(tp); 3570 rtl_ephy_init(tp, e_info_8117); 3571 3572 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3573 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3574 3575 rtl_set_def_aspm_entry_latency(tp); 3576 3577 rtl_reset_packet_filter(tp); 3578 3579 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3580 3581 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3582 3583 rtl_disable_rxdvgate(tp); 3584 3585 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3586 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3587 3588 rtl8168_config_eee_mac(tp); 3589 3590 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3591 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3592 3593 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3594 3595 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3596 3597 rtl_pcie_state_l2l3_disable(tp); 3598 3599 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3600 if (rg_saw_cnt > 0) { 3601 u16 sw_cnt_1ms_ini; 3602 3603 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3604 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3605 } 3606 3607 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3608 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3609 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3610 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3611 3612 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3613 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3614 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3615 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3616 3617 /* firmware is for MAC only */ 3618 r8169_apply_firmware(tp); 3619 } 3620 3621 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3622 { 3623 static const struct ephy_info e_info_8102e_1[] = { 3624 { 0x01, 0, 0x6e65 }, 3625 { 0x02, 0, 0x091f }, 3626 { 0x03, 0, 0xc2f9 }, 3627 { 0x06, 0, 0xafb5 }, 3628 { 0x07, 0, 0x0e00 }, 3629 { 0x19, 0, 0xec80 }, 3630 { 0x01, 0, 0x2e65 }, 3631 { 0x01, 0, 0x6e65 } 3632 }; 3633 u8 cfg1; 3634 3635 rtl_set_def_aspm_entry_latency(tp); 3636 3637 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3638 3639 RTL_W8(tp, Config1, 3640 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3641 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3642 3643 cfg1 = RTL_R8(tp, Config1); 3644 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3645 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3646 3647 rtl_ephy_init(tp, e_info_8102e_1); 3648 } 3649 3650 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3651 { 3652 rtl_set_def_aspm_entry_latency(tp); 3653 3654 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3655 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3656 } 3657 3658 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3659 { 3660 rtl_hw_start_8102e_2(tp); 3661 3662 rtl_ephy_write(tp, 0x03, 0xc2f9); 3663 } 3664 3665 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3666 { 3667 static const struct ephy_info e_info_8401[] = { 3668 { 0x01, 0xffff, 0x6fe5 }, 3669 { 0x03, 0xffff, 0x0599 }, 3670 { 0x06, 0xffff, 0xaf25 }, 3671 { 0x07, 0xffff, 0x8e68 }, 3672 }; 3673 3674 rtl_ephy_init(tp, e_info_8401); 3675 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3676 } 3677 3678 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3679 { 3680 static const struct ephy_info e_info_8105e_1[] = { 3681 { 0x07, 0, 0x4000 }, 3682 { 0x19, 0, 0x0200 }, 3683 { 0x19, 0, 0x0020 }, 3684 { 0x1e, 0, 0x2000 }, 3685 { 0x03, 0, 0x0001 }, 3686 { 0x19, 0, 0x0100 }, 3687 { 0x19, 0, 0x0004 }, 3688 { 0x0a, 0, 0x0020 } 3689 }; 3690 3691 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3692 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3693 3694 /* Disable Early Tally Counter */ 3695 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3696 3697 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3698 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3699 3700 rtl_ephy_init(tp, e_info_8105e_1); 3701 3702 rtl_pcie_state_l2l3_disable(tp); 3703 } 3704 3705 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3706 { 3707 rtl_hw_start_8105e_1(tp); 3708 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3709 } 3710 3711 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3712 { 3713 static const struct ephy_info e_info_8402[] = { 3714 { 0x19, 0xffff, 0xff64 }, 3715 { 0x1e, 0, 0x4000 } 3716 }; 3717 3718 rtl_set_def_aspm_entry_latency(tp); 3719 3720 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3721 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3722 3723 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3724 3725 rtl_ephy_init(tp, e_info_8402); 3726 3727 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3728 rtl_reset_packet_filter(tp); 3729 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3730 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3731 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3732 3733 /* disable EEE */ 3734 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3735 3736 rtl_pcie_state_l2l3_disable(tp); 3737 } 3738 3739 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3740 { 3741 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3742 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3743 3744 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3745 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3746 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3747 3748 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3749 rtl_set_aspm_entry_latency(tp, 0x2f); 3750 3751 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3752 3753 /* disable EEE */ 3754 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3755 3756 rtl_pcie_state_l2l3_disable(tp); 3757 } 3758 3759 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3760 { 3761 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3762 } 3763 3764 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3765 { 3766 rtl_pcie_state_l2l3_disable(tp); 3767 3768 RTL_W16(tp, 0x382, 0x221b); 3769 RTL_W8(tp, 0x4500, 0); 3770 RTL_W16(tp, 0x4800, 0); 3771 3772 /* disable UPS */ 3773 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3774 3775 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3776 3777 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3778 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3779 3780 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3781 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3782 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3783 3784 /* disable new tx descriptor format */ 3785 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3786 3787 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3788 tp->mac_version == RTL_GIGA_MAC_VER_66) 3789 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3790 3791 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3792 tp->mac_version == RTL_GIGA_MAC_VER_66) 3793 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3794 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3795 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3796 else 3797 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3798 3799 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3800 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3801 else 3802 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3803 3804 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3805 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3806 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3807 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3808 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3809 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3810 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3811 tp->mac_version == RTL_GIGA_MAC_VER_66) 3812 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3813 else 3814 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3815 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3816 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3817 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3818 3819 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3820 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3821 udelay(1); 3822 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3823 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3824 3825 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3826 3827 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3828 3829 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3830 rtl8125a_config_eee_mac(tp); 3831 else 3832 rtl8125b_config_eee_mac(tp); 3833 3834 rtl_disable_rxdvgate(tp); 3835 } 3836 3837 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3838 { 3839 static const struct ephy_info e_info_8125a_2[] = { 3840 { 0x04, 0xffff, 0xd000 }, 3841 { 0x0a, 0xffff, 0x8653 }, 3842 { 0x23, 0xffff, 0xab66 }, 3843 { 0x20, 0xffff, 0x9455 }, 3844 { 0x21, 0xffff, 0x99ff }, 3845 { 0x29, 0xffff, 0xfe04 }, 3846 3847 { 0x44, 0xffff, 0xd000 }, 3848 { 0x4a, 0xffff, 0x8653 }, 3849 { 0x63, 0xffff, 0xab66 }, 3850 { 0x60, 0xffff, 0x9455 }, 3851 { 0x61, 0xffff, 0x99ff }, 3852 { 0x69, 0xffff, 0xfe04 }, 3853 }; 3854 3855 rtl_set_def_aspm_entry_latency(tp); 3856 rtl_ephy_init(tp, e_info_8125a_2); 3857 rtl_hw_start_8125_common(tp); 3858 } 3859 3860 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3861 { 3862 static const struct ephy_info e_info_8125b[] = { 3863 { 0x0b, 0xffff, 0xa908 }, 3864 { 0x1e, 0xffff, 0x20eb }, 3865 { 0x4b, 0xffff, 0xa908 }, 3866 { 0x5e, 0xffff, 0x20eb }, 3867 { 0x22, 0x0030, 0x0020 }, 3868 { 0x62, 0x0030, 0x0020 }, 3869 }; 3870 3871 rtl_set_def_aspm_entry_latency(tp); 3872 rtl_ephy_init(tp, e_info_8125b); 3873 rtl_hw_start_8125_common(tp); 3874 } 3875 3876 static void rtl_hw_start_8125d(struct rtl8169_private *tp) 3877 { 3878 rtl_set_def_aspm_entry_latency(tp); 3879 rtl_hw_start_8125_common(tp); 3880 } 3881 3882 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3883 { 3884 rtl_set_def_aspm_entry_latency(tp); 3885 rtl_hw_start_8125_common(tp); 3886 } 3887 3888 static void rtl_hw_config(struct rtl8169_private *tp) 3889 { 3890 static const rtl_generic_fct hw_configs[] = { 3891 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3892 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3893 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3894 [RTL_GIGA_MAC_VER_10] = NULL, 3895 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3896 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3897 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3898 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3899 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3900 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3901 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3902 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3903 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3904 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3905 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3906 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3907 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3908 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3909 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3910 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3911 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3912 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3913 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3914 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3915 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3916 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3917 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3918 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3919 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3920 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3921 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3922 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3923 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3924 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3925 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3926 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3927 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3928 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3929 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3930 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, 3931 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3932 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a, 3933 }; 3934 3935 if (hw_configs[tp->mac_version]) 3936 hw_configs[tp->mac_version](tp); 3937 } 3938 3939 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3940 { 3941 int i; 3942 3943 RTL_W8(tp, INT_CFG0_8125, 0x00); 3944 3945 /* disable interrupt coalescing */ 3946 switch (tp->mac_version) { 3947 case RTL_GIGA_MAC_VER_61: 3948 case RTL_GIGA_MAC_VER_64: 3949 for (i = 0xa00; i < 0xb00; i += 4) 3950 RTL_W32(tp, i, 0); 3951 break; 3952 case RTL_GIGA_MAC_VER_63: 3953 case RTL_GIGA_MAC_VER_65: 3954 case RTL_GIGA_MAC_VER_66: 3955 for (i = 0xa00; i < 0xa80; i += 4) 3956 RTL_W32(tp, i, 0); 3957 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3958 break; 3959 default: 3960 break; 3961 } 3962 3963 /* enable extended tally counter */ 3964 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); 3965 3966 rtl_hw_config(tp); 3967 } 3968 3969 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3970 { 3971 if (rtl_is_8168evl_up(tp)) 3972 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3973 else 3974 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3975 3976 rtl_hw_config(tp); 3977 3978 /* disable interrupt coalescing */ 3979 RTL_W16(tp, IntrMitigate, 0x0000); 3980 } 3981 3982 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3983 { 3984 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3985 3986 tp->cp_cmd |= PCIMulRW; 3987 3988 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3989 tp->mac_version == RTL_GIGA_MAC_VER_03) 3990 tp->cp_cmd |= EnAnaPLL; 3991 3992 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3993 3994 rtl8169_set_magic_reg(tp); 3995 3996 /* disable interrupt coalescing */ 3997 RTL_W16(tp, IntrMitigate, 0x0000); 3998 } 3999 4000 static void rtl_hw_start(struct rtl8169_private *tp) 4001 { 4002 rtl_unlock_config_regs(tp); 4003 /* disable aspm and clock request before ephy access */ 4004 rtl_hw_aspm_clkreq_enable(tp, false); 4005 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 4006 4007 rtl_set_eee_txidle_timer(tp); 4008 4009 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4010 rtl_hw_start_8169(tp); 4011 else if (rtl_is_8125(tp)) 4012 rtl_hw_start_8125(tp); 4013 else 4014 rtl_hw_start_8168(tp); 4015 4016 rtl_enable_exit_l1(tp); 4017 rtl_hw_aspm_clkreq_enable(tp, true); 4018 rtl_set_rx_max_size(tp); 4019 rtl_set_rx_tx_desc_registers(tp); 4020 rtl_lock_config_regs(tp); 4021 4022 rtl_jumbo_config(tp); 4023 4024 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 4025 rtl_pci_commit(tp); 4026 4027 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 4028 rtl_init_rxcfg(tp); 4029 rtl_set_tx_config_registers(tp); 4030 rtl_set_rx_config_features(tp, tp->dev->features); 4031 rtl_set_rx_mode(tp->dev); 4032 rtl_irq_enable(tp); 4033 } 4034 4035 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 4036 { 4037 struct rtl8169_private *tp = netdev_priv(dev); 4038 4039 WRITE_ONCE(dev->mtu, new_mtu); 4040 netdev_update_features(dev); 4041 rtl_jumbo_config(tp); 4042 rtl_set_eee_txidle_timer(tp); 4043 4044 return 0; 4045 } 4046 4047 static void rtl8169_mark_to_asic(struct RxDesc *desc) 4048 { 4049 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 4050 4051 desc->opts2 = 0; 4052 /* Force memory writes to complete before releasing descriptor */ 4053 dma_wmb(); 4054 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 4055 } 4056 4057 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 4058 struct RxDesc *desc) 4059 { 4060 struct device *d = tp_to_dev(tp); 4061 int node = dev_to_node(d); 4062 dma_addr_t mapping; 4063 struct page *data; 4064 4065 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 4066 if (!data) 4067 return NULL; 4068 4069 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4070 if (unlikely(dma_mapping_error(d, mapping))) { 4071 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 4072 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 4073 return NULL; 4074 } 4075 4076 desc->addr = cpu_to_le64(mapping); 4077 rtl8169_mark_to_asic(desc); 4078 4079 return data; 4080 } 4081 4082 static void rtl8169_rx_clear(struct rtl8169_private *tp) 4083 { 4084 int i; 4085 4086 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 4087 dma_unmap_page(tp_to_dev(tp), 4088 le64_to_cpu(tp->RxDescArray[i].addr), 4089 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4090 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4091 tp->Rx_databuff[i] = NULL; 4092 tp->RxDescArray[i].addr = 0; 4093 tp->RxDescArray[i].opts1 = 0; 4094 } 4095 } 4096 4097 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4098 { 4099 int i; 4100 4101 for (i = 0; i < NUM_RX_DESC; i++) { 4102 struct page *data; 4103 4104 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4105 if (!data) { 4106 rtl8169_rx_clear(tp); 4107 return -ENOMEM; 4108 } 4109 tp->Rx_databuff[i] = data; 4110 } 4111 4112 /* mark as last descriptor in the ring */ 4113 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4114 4115 return 0; 4116 } 4117 4118 static int rtl8169_init_ring(struct rtl8169_private *tp) 4119 { 4120 rtl8169_init_ring_indexes(tp); 4121 4122 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4123 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4124 4125 return rtl8169_rx_fill(tp); 4126 } 4127 4128 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4129 { 4130 struct ring_info *tx_skb = tp->tx_skb + entry; 4131 struct TxDesc *desc = tp->TxDescArray + entry; 4132 4133 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4134 DMA_TO_DEVICE); 4135 memset(desc, 0, sizeof(*desc)); 4136 memset(tx_skb, 0, sizeof(*tx_skb)); 4137 } 4138 4139 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4140 unsigned int n) 4141 { 4142 unsigned int i; 4143 4144 for (i = 0; i < n; i++) { 4145 unsigned int entry = (start + i) % NUM_TX_DESC; 4146 struct ring_info *tx_skb = tp->tx_skb + entry; 4147 unsigned int len = tx_skb->len; 4148 4149 if (len) { 4150 struct sk_buff *skb = tx_skb->skb; 4151 4152 rtl8169_unmap_tx_skb(tp, entry); 4153 if (skb) 4154 dev_consume_skb_any(skb); 4155 } 4156 } 4157 } 4158 4159 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4160 { 4161 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4162 netdev_reset_queue(tp->dev); 4163 } 4164 4165 static void rtl8169_cleanup(struct rtl8169_private *tp) 4166 { 4167 napi_disable(&tp->napi); 4168 4169 /* Give a racing hard_start_xmit a few cycles to complete. */ 4170 synchronize_net(); 4171 4172 /* Disable interrupts */ 4173 rtl8169_irq_mask_and_ack(tp); 4174 4175 rtl_rx_close(tp); 4176 4177 switch (tp->mac_version) { 4178 case RTL_GIGA_MAC_VER_28: 4179 case RTL_GIGA_MAC_VER_31: 4180 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4181 break; 4182 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4183 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4184 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4185 break; 4186 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 4187 rtl_enable_rxdvgate(tp); 4188 fsleep(2000); 4189 break; 4190 default: 4191 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4192 fsleep(100); 4193 break; 4194 } 4195 4196 rtl_hw_reset(tp); 4197 4198 rtl8169_tx_clear(tp); 4199 rtl8169_init_ring_indexes(tp); 4200 } 4201 4202 static void rtl_reset_work(struct rtl8169_private *tp) 4203 { 4204 int i; 4205 4206 netif_stop_queue(tp->dev); 4207 4208 rtl8169_cleanup(tp); 4209 4210 for (i = 0; i < NUM_RX_DESC; i++) 4211 rtl8169_mark_to_asic(tp->RxDescArray + i); 4212 4213 napi_enable(&tp->napi); 4214 rtl_hw_start(tp); 4215 } 4216 4217 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4218 { 4219 struct rtl8169_private *tp = netdev_priv(dev); 4220 4221 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4222 } 4223 4224 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4225 void *addr, unsigned int entry, bool desc_own) 4226 { 4227 struct TxDesc *txd = tp->TxDescArray + entry; 4228 struct device *d = tp_to_dev(tp); 4229 dma_addr_t mapping; 4230 u32 opts1; 4231 int ret; 4232 4233 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4234 ret = dma_mapping_error(d, mapping); 4235 if (unlikely(ret)) { 4236 if (net_ratelimit()) 4237 netdev_err(tp->dev, "Failed to map TX data!\n"); 4238 return ret; 4239 } 4240 4241 txd->addr = cpu_to_le64(mapping); 4242 txd->opts2 = cpu_to_le32(opts[1]); 4243 4244 opts1 = opts[0] | len; 4245 if (entry == NUM_TX_DESC - 1) 4246 opts1 |= RingEnd; 4247 if (desc_own) 4248 opts1 |= DescOwn; 4249 txd->opts1 = cpu_to_le32(opts1); 4250 4251 tp->tx_skb[entry].len = len; 4252 4253 return 0; 4254 } 4255 4256 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4257 const u32 *opts, unsigned int entry) 4258 { 4259 struct skb_shared_info *info = skb_shinfo(skb); 4260 unsigned int cur_frag; 4261 4262 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4263 const skb_frag_t *frag = info->frags + cur_frag; 4264 void *addr = skb_frag_address(frag); 4265 u32 len = skb_frag_size(frag); 4266 4267 entry = (entry + 1) % NUM_TX_DESC; 4268 4269 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4270 goto err_out; 4271 } 4272 4273 return 0; 4274 4275 err_out: 4276 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4277 return -EIO; 4278 } 4279 4280 static bool rtl_skb_is_udp(struct sk_buff *skb) 4281 { 4282 int no = skb_network_offset(skb); 4283 struct ipv6hdr *i6h, _i6h; 4284 struct iphdr *ih, _ih; 4285 4286 switch (vlan_get_protocol(skb)) { 4287 case htons(ETH_P_IP): 4288 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4289 return ih && ih->protocol == IPPROTO_UDP; 4290 case htons(ETH_P_IPV6): 4291 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4292 return i6h && i6h->nexthdr == IPPROTO_UDP; 4293 default: 4294 return false; 4295 } 4296 } 4297 4298 #define RTL_MIN_PATCH_LEN 47 4299 4300 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4301 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4302 struct sk_buff *skb) 4303 { 4304 unsigned int padto = 0, len = skb->len; 4305 4306 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) && 4307 skb_transport_header_was_set(skb)) { 4308 unsigned int trans_data_len = skb_tail_pointer(skb) - 4309 skb_transport_header(skb); 4310 4311 if (trans_data_len >= offsetof(struct udphdr, len) && 4312 trans_data_len < RTL_MIN_PATCH_LEN) { 4313 u16 dest = ntohs(udp_hdr(skb)->dest); 4314 4315 /* dest is a standard PTP port */ 4316 if (dest == 319 || dest == 320) 4317 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4318 } 4319 4320 if (trans_data_len < sizeof(struct udphdr)) 4321 padto = max_t(unsigned int, padto, 4322 len + sizeof(struct udphdr) - trans_data_len); 4323 } 4324 4325 return padto; 4326 } 4327 4328 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4329 struct sk_buff *skb) 4330 { 4331 unsigned int padto = 0; 4332 4333 switch (tp->mac_version) { 4334 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 4335 padto = rtl8125_quirk_udp_padto(tp, skb); 4336 break; 4337 default: 4338 break; 4339 } 4340 4341 switch (tp->mac_version) { 4342 case RTL_GIGA_MAC_VER_34: 4343 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 4344 padto = max_t(unsigned int, padto, ETH_ZLEN); 4345 break; 4346 default: 4347 break; 4348 } 4349 4350 return padto; 4351 } 4352 4353 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4354 { 4355 u32 mss = skb_shinfo(skb)->gso_size; 4356 4357 if (mss) { 4358 opts[0] |= TD_LSO; 4359 opts[0] |= mss << TD0_MSS_SHIFT; 4360 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4361 const struct iphdr *ip = ip_hdr(skb); 4362 4363 if (ip->protocol == IPPROTO_TCP) 4364 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4365 else if (ip->protocol == IPPROTO_UDP) 4366 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4367 else 4368 WARN_ON_ONCE(1); 4369 } 4370 } 4371 4372 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4373 struct sk_buff *skb, u32 *opts) 4374 { 4375 struct skb_shared_info *shinfo = skb_shinfo(skb); 4376 u32 mss = shinfo->gso_size; 4377 4378 if (mss) { 4379 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4380 opts[0] |= TD1_GTSENV4; 4381 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4382 if (skb_cow_head(skb, 0)) 4383 return false; 4384 4385 tcp_v6_gso_csum_prep(skb); 4386 opts[0] |= TD1_GTSENV6; 4387 } else { 4388 WARN_ON_ONCE(1); 4389 } 4390 4391 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4392 opts[1] |= mss << TD1_MSS_SHIFT; 4393 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4394 u8 ip_protocol; 4395 4396 switch (vlan_get_protocol(skb)) { 4397 case htons(ETH_P_IP): 4398 opts[1] |= TD1_IPv4_CS; 4399 ip_protocol = ip_hdr(skb)->protocol; 4400 break; 4401 4402 case htons(ETH_P_IPV6): 4403 opts[1] |= TD1_IPv6_CS; 4404 ip_protocol = ipv6_hdr(skb)->nexthdr; 4405 break; 4406 4407 default: 4408 ip_protocol = IPPROTO_RAW; 4409 break; 4410 } 4411 4412 if (ip_protocol == IPPROTO_TCP) 4413 opts[1] |= TD1_TCP_CS; 4414 else if (ip_protocol == IPPROTO_UDP) 4415 opts[1] |= TD1_UDP_CS; 4416 else 4417 WARN_ON_ONCE(1); 4418 4419 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4420 } else { 4421 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4422 4423 /* skb_padto would free the skb on error */ 4424 return !__skb_put_padto(skb, padto, false); 4425 } 4426 4427 return true; 4428 } 4429 4430 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4431 { 4432 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4433 } 4434 4435 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4436 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4437 { 4438 switch (tp->mac_version) { 4439 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4440 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4441 return false; 4442 default: 4443 return true; 4444 } 4445 } 4446 4447 static void rtl8169_doorbell(struct rtl8169_private *tp) 4448 { 4449 if (rtl_is_8125(tp)) 4450 RTL_W16(tp, TxPoll_8125, BIT(0)); 4451 else 4452 RTL_W8(tp, TxPoll, NPQ); 4453 } 4454 4455 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4456 struct net_device *dev) 4457 { 4458 struct rtl8169_private *tp = netdev_priv(dev); 4459 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4460 struct TxDesc *txd_first, *txd_last; 4461 bool stop_queue, door_bell; 4462 unsigned int frags; 4463 u32 opts[2]; 4464 4465 if (unlikely(!rtl_tx_slots_avail(tp))) { 4466 if (net_ratelimit()) 4467 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4468 netif_stop_queue(dev); 4469 return NETDEV_TX_BUSY; 4470 } 4471 4472 opts[1] = rtl8169_tx_vlan_tag(skb); 4473 opts[0] = 0; 4474 4475 if (!rtl_chip_supports_csum_v2(tp)) 4476 rtl8169_tso_csum_v1(skb, opts); 4477 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4478 goto err_dma_0; 4479 4480 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4481 entry, false))) 4482 goto err_dma_0; 4483 4484 txd_first = tp->TxDescArray + entry; 4485 4486 frags = skb_shinfo(skb)->nr_frags; 4487 if (frags) { 4488 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4489 goto err_dma_1; 4490 entry = (entry + frags) % NUM_TX_DESC; 4491 } 4492 4493 txd_last = tp->TxDescArray + entry; 4494 txd_last->opts1 |= cpu_to_le32(LastFrag); 4495 tp->tx_skb[entry].skb = skb; 4496 4497 skb_tx_timestamp(skb); 4498 4499 /* Force memory writes to complete before releasing descriptor */ 4500 dma_wmb(); 4501 4502 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4503 4504 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4505 4506 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4507 smp_wmb(); 4508 4509 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4510 4511 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4512 R8169_TX_STOP_THRS, 4513 R8169_TX_START_THRS); 4514 if (door_bell || stop_queue) 4515 rtl8169_doorbell(tp); 4516 4517 return NETDEV_TX_OK; 4518 4519 err_dma_1: 4520 rtl8169_unmap_tx_skb(tp, entry); 4521 err_dma_0: 4522 dev_kfree_skb_any(skb); 4523 dev->stats.tx_dropped++; 4524 return NETDEV_TX_OK; 4525 } 4526 4527 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4528 { 4529 struct skb_shared_info *info = skb_shinfo(skb); 4530 unsigned int nr_frags = info->nr_frags; 4531 4532 if (!nr_frags) 4533 return UINT_MAX; 4534 4535 return skb_frag_size(info->frags + nr_frags - 1); 4536 } 4537 4538 /* Workaround for hw issues with TSO on RTL8168evl */ 4539 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4540 netdev_features_t features) 4541 { 4542 /* IPv4 header has options field */ 4543 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4544 ip_hdrlen(skb) > sizeof(struct iphdr)) 4545 features &= ~NETIF_F_ALL_TSO; 4546 4547 /* IPv4 TCP header has options field */ 4548 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4549 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4550 features &= ~NETIF_F_ALL_TSO; 4551 4552 else if (rtl_last_frag_len(skb) <= 6) 4553 features &= ~NETIF_F_ALL_TSO; 4554 4555 return features; 4556 } 4557 4558 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4559 struct net_device *dev, 4560 netdev_features_t features) 4561 { 4562 struct rtl8169_private *tp = netdev_priv(dev); 4563 4564 if (skb_is_gso(skb)) { 4565 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4566 features = rtl8168evl_fix_tso(skb, features); 4567 4568 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4569 rtl_chip_supports_csum_v2(tp)) 4570 features &= ~NETIF_F_ALL_TSO; 4571 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4572 /* work around hw bug on some chip versions */ 4573 if (skb->len < ETH_ZLEN) 4574 features &= ~NETIF_F_CSUM_MASK; 4575 4576 if (rtl_quirk_packet_padto(tp, skb)) 4577 features &= ~NETIF_F_CSUM_MASK; 4578 4579 if (skb_transport_offset(skb) > TCPHO_MAX && 4580 rtl_chip_supports_csum_v2(tp)) 4581 features &= ~NETIF_F_CSUM_MASK; 4582 } 4583 4584 return vlan_features_check(skb, features); 4585 } 4586 4587 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4588 { 4589 struct rtl8169_private *tp = netdev_priv(dev); 4590 struct pci_dev *pdev = tp->pci_dev; 4591 int pci_status_errs; 4592 u16 pci_cmd; 4593 4594 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4595 4596 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4597 4598 if (net_ratelimit()) 4599 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4600 pci_cmd, pci_status_errs); 4601 4602 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4603 } 4604 4605 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4606 int budget) 4607 { 4608 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4609 struct sk_buff *skb; 4610 4611 dirty_tx = tp->dirty_tx; 4612 4613 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4614 unsigned int entry = dirty_tx % NUM_TX_DESC; 4615 u32 status; 4616 4617 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4618 if (status & DescOwn) 4619 break; 4620 4621 skb = tp->tx_skb[entry].skb; 4622 rtl8169_unmap_tx_skb(tp, entry); 4623 4624 if (skb) { 4625 pkts_compl++; 4626 bytes_compl += skb->len; 4627 napi_consume_skb(skb, budget); 4628 } 4629 dirty_tx++; 4630 } 4631 4632 if (tp->dirty_tx != dirty_tx) { 4633 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4634 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4635 4636 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4637 rtl_tx_slots_avail(tp), 4638 R8169_TX_START_THRS); 4639 /* 4640 * 8168 hack: TxPoll requests are lost when the Tx packets are 4641 * too close. Let's kick an extra TxPoll request when a burst 4642 * of start_xmit activity is detected (if it is not detected, 4643 * it is slow enough). -- FR 4644 * If skb is NULL then we come here again once a tx irq is 4645 * triggered after the last fragment is marked transmitted. 4646 */ 4647 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4648 rtl8169_doorbell(tp); 4649 } 4650 } 4651 4652 static inline int rtl8169_fragmented_frame(u32 status) 4653 { 4654 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4655 } 4656 4657 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4658 { 4659 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4660 4661 if (status == RxProtoTCP || status == RxProtoUDP) 4662 skb->ip_summed = CHECKSUM_UNNECESSARY; 4663 else 4664 skb_checksum_none_assert(skb); 4665 } 4666 4667 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4668 { 4669 struct device *d = tp_to_dev(tp); 4670 int count; 4671 4672 for (count = 0; count < budget; count++, tp->cur_rx++) { 4673 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4674 struct RxDesc *desc = tp->RxDescArray + entry; 4675 struct sk_buff *skb; 4676 const void *rx_buf; 4677 dma_addr_t addr; 4678 u32 status; 4679 4680 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4681 if (status & DescOwn) 4682 break; 4683 4684 /* This barrier is needed to keep us from reading 4685 * any other fields out of the Rx descriptor until 4686 * we know the status of DescOwn 4687 */ 4688 dma_rmb(); 4689 4690 if (unlikely(status & RxRES)) { 4691 if (net_ratelimit()) 4692 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4693 status); 4694 dev->stats.rx_errors++; 4695 if (status & (RxRWT | RxRUNT)) 4696 dev->stats.rx_length_errors++; 4697 if (status & RxCRC) 4698 dev->stats.rx_crc_errors++; 4699 4700 if (!(dev->features & NETIF_F_RXALL)) 4701 goto release_descriptor; 4702 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4703 goto release_descriptor; 4704 } 4705 4706 pkt_size = status & GENMASK(13, 0); 4707 if (likely(!(dev->features & NETIF_F_RXFCS))) 4708 pkt_size -= ETH_FCS_LEN; 4709 4710 /* The driver does not support incoming fragmented frames. 4711 * They are seen as a symptom of over-mtu sized frames. 4712 */ 4713 if (unlikely(rtl8169_fragmented_frame(status))) { 4714 dev->stats.rx_dropped++; 4715 dev->stats.rx_length_errors++; 4716 goto release_descriptor; 4717 } 4718 4719 skb = napi_alloc_skb(&tp->napi, pkt_size); 4720 if (unlikely(!skb)) { 4721 dev->stats.rx_dropped++; 4722 goto release_descriptor; 4723 } 4724 4725 addr = le64_to_cpu(desc->addr); 4726 rx_buf = page_address(tp->Rx_databuff[entry]); 4727 4728 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4729 prefetch(rx_buf); 4730 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4731 skb->tail += pkt_size; 4732 skb->len = pkt_size; 4733 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4734 4735 rtl8169_rx_csum(skb, status); 4736 skb->protocol = eth_type_trans(skb, dev); 4737 4738 rtl8169_rx_vlan_tag(desc, skb); 4739 4740 if (skb->pkt_type == PACKET_MULTICAST) 4741 dev->stats.multicast++; 4742 4743 napi_gro_receive(&tp->napi, skb); 4744 4745 dev_sw_netstats_rx_add(dev, pkt_size); 4746 release_descriptor: 4747 rtl8169_mark_to_asic(desc); 4748 } 4749 4750 return count; 4751 } 4752 4753 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4754 { 4755 struct rtl8169_private *tp = dev_instance; 4756 u32 status = rtl_get_events(tp); 4757 4758 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4759 return IRQ_NONE; 4760 4761 /* At least RTL8168fp may unexpectedly set the SYSErr bit */ 4762 if (unlikely(status & SYSErr && 4763 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { 4764 rtl8169_pcierr_interrupt(tp->dev); 4765 goto out; 4766 } 4767 4768 if (status & LinkChg) 4769 phy_mac_interrupt(tp->phydev); 4770 4771 if (unlikely(status & RxFIFOOver && 4772 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4773 netif_stop_queue(tp->dev); 4774 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4775 } 4776 4777 rtl_irq_disable(tp); 4778 napi_schedule(&tp->napi); 4779 out: 4780 rtl_ack_events(tp, status); 4781 4782 return IRQ_HANDLED; 4783 } 4784 4785 static void rtl_task(struct work_struct *work) 4786 { 4787 struct rtl8169_private *tp = 4788 container_of(work, struct rtl8169_private, wk.work); 4789 int ret; 4790 4791 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4792 /* if chip isn't accessible, reset bus to revive it */ 4793 if (RTL_R32(tp, TxConfig) == ~0) { 4794 ret = pci_reset_bus(tp->pci_dev); 4795 if (ret < 0) { 4796 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4797 netif_device_detach(tp->dev); 4798 return; 4799 } 4800 } 4801 4802 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4803 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4804 PCIE_LINK_STATE_L0S); 4805 if (!ret) 4806 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4807 goto reset; 4808 } 4809 4810 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4811 reset: 4812 rtl_reset_work(tp); 4813 netif_wake_queue(tp->dev); 4814 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4815 rtl_reset_work(tp); 4816 } 4817 } 4818 4819 static int rtl8169_poll(struct napi_struct *napi, int budget) 4820 { 4821 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4822 struct net_device *dev = tp->dev; 4823 int work_done; 4824 4825 rtl_tx(dev, tp, budget); 4826 4827 work_done = rtl_rx(dev, tp, budget); 4828 4829 if (work_done < budget && napi_complete_done(napi, work_done)) 4830 rtl_irq_enable(tp); 4831 4832 return work_done; 4833 } 4834 4835 static void r8169_phylink_handler(struct net_device *ndev) 4836 { 4837 struct rtl8169_private *tp = netdev_priv(ndev); 4838 struct device *d = tp_to_dev(tp); 4839 4840 if (netif_carrier_ok(ndev)) { 4841 rtl_link_chg_patch(tp); 4842 pm_request_resume(d); 4843 } else { 4844 pm_runtime_idle(d); 4845 } 4846 4847 phy_print_status(tp->phydev); 4848 } 4849 4850 static int r8169_phy_connect(struct rtl8169_private *tp) 4851 { 4852 struct phy_device *phydev = tp->phydev; 4853 phy_interface_t phy_mode; 4854 int ret; 4855 4856 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4857 PHY_INTERFACE_MODE_MII; 4858 4859 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4860 phy_mode); 4861 if (ret) 4862 return ret; 4863 4864 if (!tp->supports_gmii) 4865 phy_set_max_speed(phydev, SPEED_100); 4866 4867 phy_attached_info(phydev); 4868 4869 return 0; 4870 } 4871 4872 static void rtl8169_down(struct rtl8169_private *tp) 4873 { 4874 disable_work_sync(&tp->wk.work); 4875 /* Clear all task flags */ 4876 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4877 4878 phy_stop(tp->phydev); 4879 4880 rtl8169_update_counters(tp); 4881 4882 pci_clear_master(tp->pci_dev); 4883 rtl_pci_commit(tp); 4884 4885 rtl8169_cleanup(tp); 4886 rtl_disable_exit_l1(tp); 4887 rtl_prepare_power_down(tp); 4888 4889 if (tp->dash_type != RTL_DASH_NONE) 4890 rtl8168_driver_stop(tp); 4891 } 4892 4893 static void rtl8169_up(struct rtl8169_private *tp) 4894 { 4895 if (tp->dash_type != RTL_DASH_NONE) 4896 rtl8168_driver_start(tp); 4897 4898 pci_set_master(tp->pci_dev); 4899 phy_init_hw(tp->phydev); 4900 phy_resume(tp->phydev); 4901 rtl8169_init_phy(tp); 4902 napi_enable(&tp->napi); 4903 enable_work(&tp->wk.work); 4904 rtl_reset_work(tp); 4905 4906 phy_start(tp->phydev); 4907 } 4908 4909 static int rtl8169_close(struct net_device *dev) 4910 { 4911 struct rtl8169_private *tp = netdev_priv(dev); 4912 struct pci_dev *pdev = tp->pci_dev; 4913 4914 pm_runtime_get_sync(&pdev->dev); 4915 4916 netif_stop_queue(dev); 4917 rtl8169_down(tp); 4918 rtl8169_rx_clear(tp); 4919 4920 free_irq(tp->irq, tp); 4921 4922 phy_disconnect(tp->phydev); 4923 4924 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4925 tp->RxPhyAddr); 4926 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4927 tp->TxPhyAddr); 4928 tp->TxDescArray = NULL; 4929 tp->RxDescArray = NULL; 4930 4931 pm_runtime_put_sync(&pdev->dev); 4932 4933 return 0; 4934 } 4935 4936 #ifdef CONFIG_NET_POLL_CONTROLLER 4937 static void rtl8169_netpoll(struct net_device *dev) 4938 { 4939 struct rtl8169_private *tp = netdev_priv(dev); 4940 4941 rtl8169_interrupt(tp->irq, tp); 4942 } 4943 #endif 4944 4945 static int rtl_open(struct net_device *dev) 4946 { 4947 struct rtl8169_private *tp = netdev_priv(dev); 4948 struct pci_dev *pdev = tp->pci_dev; 4949 unsigned long irqflags; 4950 int retval = -ENOMEM; 4951 4952 pm_runtime_get_sync(&pdev->dev); 4953 4954 /* 4955 * Rx and Tx descriptors needs 256 bytes alignment. 4956 * dma_alloc_coherent provides more. 4957 */ 4958 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4959 &tp->TxPhyAddr, GFP_KERNEL); 4960 if (!tp->TxDescArray) 4961 goto out; 4962 4963 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4964 &tp->RxPhyAddr, GFP_KERNEL); 4965 if (!tp->RxDescArray) 4966 goto err_free_tx_0; 4967 4968 retval = rtl8169_init_ring(tp); 4969 if (retval < 0) 4970 goto err_free_rx_1; 4971 4972 rtl_request_firmware(tp); 4973 4974 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4975 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4976 if (retval < 0) 4977 goto err_release_fw_2; 4978 4979 retval = r8169_phy_connect(tp); 4980 if (retval) 4981 goto err_free_irq; 4982 4983 rtl8169_up(tp); 4984 rtl8169_init_counter_offsets(tp); 4985 netif_start_queue(dev); 4986 out: 4987 pm_runtime_put_sync(&pdev->dev); 4988 4989 return retval; 4990 4991 err_free_irq: 4992 free_irq(tp->irq, tp); 4993 err_release_fw_2: 4994 rtl_release_firmware(tp); 4995 rtl8169_rx_clear(tp); 4996 err_free_rx_1: 4997 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4998 tp->RxPhyAddr); 4999 tp->RxDescArray = NULL; 5000 err_free_tx_0: 5001 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 5002 tp->TxPhyAddr); 5003 tp->TxDescArray = NULL; 5004 goto out; 5005 } 5006 5007 static void 5008 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 5009 { 5010 struct rtl8169_private *tp = netdev_priv(dev); 5011 struct pci_dev *pdev = tp->pci_dev; 5012 struct rtl8169_counters *counters = tp->counters; 5013 5014 pm_runtime_get_noresume(&pdev->dev); 5015 5016 netdev_stats_to_stats64(stats, &dev->stats); 5017 dev_fetch_sw_netstats(stats, dev->tstats); 5018 5019 /* 5020 * Fetch additional counter values missing in stats collected by driver 5021 * from tally counters. 5022 */ 5023 if (pm_runtime_active(&pdev->dev)) 5024 rtl8169_update_counters(tp); 5025 5026 /* 5027 * Subtract values fetched during initalization. 5028 * See rtl8169_init_counter_offsets for a description why we do that. 5029 */ 5030 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 5031 le64_to_cpu(tp->tc_offset.tx_errors); 5032 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 5033 le32_to_cpu(tp->tc_offset.tx_multi_collision); 5034 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 5035 le16_to_cpu(tp->tc_offset.tx_aborted); 5036 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 5037 le16_to_cpu(tp->tc_offset.rx_missed); 5038 5039 pm_runtime_put_noidle(&pdev->dev); 5040 } 5041 5042 static void rtl8169_net_suspend(struct rtl8169_private *tp) 5043 { 5044 netif_device_detach(tp->dev); 5045 5046 if (netif_running(tp->dev)) 5047 rtl8169_down(tp); 5048 } 5049 5050 static int rtl8169_runtime_resume(struct device *dev) 5051 { 5052 struct rtl8169_private *tp = dev_get_drvdata(dev); 5053 5054 rtl_rar_set(tp, tp->dev->dev_addr); 5055 __rtl8169_set_wol(tp, tp->saved_wolopts); 5056 5057 if (tp->TxDescArray) 5058 rtl8169_up(tp); 5059 5060 netif_device_attach(tp->dev); 5061 5062 return 0; 5063 } 5064 5065 static int rtl8169_suspend(struct device *device) 5066 { 5067 struct rtl8169_private *tp = dev_get_drvdata(device); 5068 5069 rtnl_lock(); 5070 rtl8169_net_suspend(tp); 5071 if (!device_may_wakeup(tp_to_dev(tp))) 5072 clk_disable_unprepare(tp->clk); 5073 rtnl_unlock(); 5074 5075 return 0; 5076 } 5077 5078 static int rtl8169_resume(struct device *device) 5079 { 5080 struct rtl8169_private *tp = dev_get_drvdata(device); 5081 5082 if (!device_may_wakeup(tp_to_dev(tp))) 5083 clk_prepare_enable(tp->clk); 5084 5085 /* Reportedly at least Asus X453MA truncates packets otherwise */ 5086 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 5087 rtl_init_rxcfg(tp); 5088 5089 return rtl8169_runtime_resume(device); 5090 } 5091 5092 static int rtl8169_runtime_suspend(struct device *device) 5093 { 5094 struct rtl8169_private *tp = dev_get_drvdata(device); 5095 5096 if (!tp->TxDescArray) { 5097 netif_device_detach(tp->dev); 5098 return 0; 5099 } 5100 5101 rtnl_lock(); 5102 __rtl8169_set_wol(tp, WAKE_PHY); 5103 rtl8169_net_suspend(tp); 5104 rtnl_unlock(); 5105 5106 return 0; 5107 } 5108 5109 static int rtl8169_runtime_idle(struct device *device) 5110 { 5111 struct rtl8169_private *tp = dev_get_drvdata(device); 5112 5113 if (tp->dash_enabled) 5114 return -EBUSY; 5115 5116 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5117 pm_schedule_suspend(device, 10000); 5118 5119 return -EBUSY; 5120 } 5121 5122 static const struct dev_pm_ops rtl8169_pm_ops = { 5123 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5124 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5125 rtl8169_runtime_idle) 5126 }; 5127 5128 static void rtl_shutdown(struct pci_dev *pdev) 5129 { 5130 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5131 5132 rtnl_lock(); 5133 rtl8169_net_suspend(tp); 5134 rtnl_unlock(); 5135 5136 /* Restore original MAC address */ 5137 rtl_rar_set(tp, tp->dev->perm_addr); 5138 5139 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5140 pci_wake_from_d3(pdev, tp->saved_wolopts); 5141 pci_set_power_state(pdev, PCI_D3hot); 5142 } 5143 } 5144 5145 static void rtl_remove_one(struct pci_dev *pdev) 5146 { 5147 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5148 5149 if (pci_dev_run_wake(pdev)) 5150 pm_runtime_get_noresume(&pdev->dev); 5151 5152 disable_work_sync(&tp->wk.work); 5153 5154 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5155 r8169_remove_leds(tp->leds); 5156 5157 unregister_netdev(tp->dev); 5158 5159 if (tp->dash_type != RTL_DASH_NONE) 5160 rtl8168_driver_stop(tp); 5161 5162 rtl_release_firmware(tp); 5163 5164 /* restore original MAC address */ 5165 rtl_rar_set(tp, tp->dev->perm_addr); 5166 } 5167 5168 static const struct net_device_ops rtl_netdev_ops = { 5169 .ndo_open = rtl_open, 5170 .ndo_stop = rtl8169_close, 5171 .ndo_get_stats64 = rtl8169_get_stats64, 5172 .ndo_start_xmit = rtl8169_start_xmit, 5173 .ndo_features_check = rtl8169_features_check, 5174 .ndo_tx_timeout = rtl8169_tx_timeout, 5175 .ndo_validate_addr = eth_validate_addr, 5176 .ndo_change_mtu = rtl8169_change_mtu, 5177 .ndo_fix_features = rtl8169_fix_features, 5178 .ndo_set_features = rtl8169_set_features, 5179 .ndo_set_mac_address = rtl_set_mac_address, 5180 .ndo_eth_ioctl = phy_do_ioctl_running, 5181 .ndo_set_rx_mode = rtl_set_rx_mode, 5182 #ifdef CONFIG_NET_POLL_CONTROLLER 5183 .ndo_poll_controller = rtl8169_netpoll, 5184 #endif 5185 5186 }; 5187 5188 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5189 { 5190 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5191 5192 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5193 tp->irq_mask |= SYSErr | RxFIFOOver; 5194 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5195 /* special workaround needed */ 5196 tp->irq_mask |= RxFIFOOver; 5197 } 5198 5199 static int rtl_alloc_irq(struct rtl8169_private *tp) 5200 { 5201 unsigned int flags; 5202 5203 switch (tp->mac_version) { 5204 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5205 rtl_unlock_config_regs(tp); 5206 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5207 rtl_lock_config_regs(tp); 5208 fallthrough; 5209 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5210 flags = PCI_IRQ_INTX; 5211 break; 5212 default: 5213 flags = PCI_IRQ_ALL_TYPES; 5214 break; 5215 } 5216 5217 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5218 } 5219 5220 static void rtl_read_mac_address(struct rtl8169_private *tp, 5221 u8 mac_addr[ETH_ALEN]) 5222 { 5223 /* Get MAC address */ 5224 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5225 u32 value; 5226 5227 value = rtl_eri_read(tp, 0xe0); 5228 put_unaligned_le32(value, mac_addr); 5229 value = rtl_eri_read(tp, 0xe4); 5230 put_unaligned_le16(value, mac_addr + 4); 5231 } else if (rtl_is_8125(tp)) { 5232 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5233 } 5234 } 5235 5236 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5237 { 5238 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5239 } 5240 5241 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5242 { 5243 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5244 } 5245 5246 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5247 { 5248 struct rtl8169_private *tp = mii_bus->priv; 5249 5250 if (phyaddr > 0) 5251 return -ENODEV; 5252 5253 return rtl_readphy(tp, phyreg); 5254 } 5255 5256 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5257 int phyreg, u16 val) 5258 { 5259 struct rtl8169_private *tp = mii_bus->priv; 5260 5261 if (phyaddr > 0) 5262 return -ENODEV; 5263 5264 rtl_writephy(tp, phyreg, val); 5265 5266 return 0; 5267 } 5268 5269 static int r8169_mdio_register(struct rtl8169_private *tp) 5270 { 5271 struct pci_dev *pdev = tp->pci_dev; 5272 struct mii_bus *new_bus; 5273 int ret; 5274 5275 /* On some boards with this chip version the BIOS is buggy and misses 5276 * to reset the PHY page selector. This results in the PHY ID read 5277 * accessing registers on a different page, returning a more or 5278 * less random value. Fix this by resetting the page selector first. 5279 */ 5280 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5281 tp->mac_version == RTL_GIGA_MAC_VER_26) 5282 r8169_mdio_write(tp, 0x1f, 0); 5283 5284 new_bus = devm_mdiobus_alloc(&pdev->dev); 5285 if (!new_bus) 5286 return -ENOMEM; 5287 5288 new_bus->name = "r8169"; 5289 new_bus->priv = tp; 5290 new_bus->parent = &pdev->dev; 5291 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5292 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5293 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5294 5295 new_bus->read = r8169_mdio_read_reg; 5296 new_bus->write = r8169_mdio_write_reg; 5297 5298 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5299 if (ret) 5300 return ret; 5301 5302 tp->phydev = mdiobus_get_phy(new_bus, 0); 5303 if (!tp->phydev) { 5304 return -ENODEV; 5305 } else if (!tp->phydev->drv) { 5306 /* Most chip versions fail with the genphy driver. 5307 * Therefore ensure that the dedicated PHY driver is loaded. 5308 */ 5309 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5310 tp->phydev->phy_id); 5311 return -EUNATCH; 5312 } 5313 5314 tp->phydev->mac_managed_pm = true; 5315 if (rtl_supports_eee(tp)) 5316 phy_support_eee(tp->phydev); 5317 phy_support_asym_pause(tp->phydev); 5318 5319 /* PHY will be woken up in rtl_open() */ 5320 phy_suspend(tp->phydev); 5321 5322 return 0; 5323 } 5324 5325 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5326 { 5327 rtl_enable_rxdvgate(tp); 5328 5329 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5330 msleep(1); 5331 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5332 5333 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5334 r8168g_wait_ll_share_fifo_ready(tp); 5335 5336 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5337 r8168g_wait_ll_share_fifo_ready(tp); 5338 } 5339 5340 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5341 { 5342 rtl_enable_rxdvgate(tp); 5343 5344 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5345 msleep(1); 5346 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5347 5348 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5349 r8168g_wait_ll_share_fifo_ready(tp); 5350 5351 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5352 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5353 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5354 r8168g_wait_ll_share_fifo_ready(tp); 5355 } 5356 5357 static void rtl_hw_initialize(struct rtl8169_private *tp) 5358 { 5359 switch (tp->mac_version) { 5360 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5361 rtl8168ep_stop_cmac(tp); 5362 fallthrough; 5363 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5364 rtl_hw_init_8168g(tp); 5365 break; 5366 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 5367 rtl_hw_init_8125(tp); 5368 break; 5369 default: 5370 break; 5371 } 5372 } 5373 5374 static int rtl_jumbo_max(struct rtl8169_private *tp) 5375 { 5376 /* Non-GBit versions don't support jumbo frames */ 5377 if (!tp->supports_gmii) 5378 return 0; 5379 5380 switch (tp->mac_version) { 5381 /* RTL8169 */ 5382 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5383 return JUMBO_7K; 5384 /* RTL8168b */ 5385 case RTL_GIGA_MAC_VER_11: 5386 case RTL_GIGA_MAC_VER_17: 5387 return JUMBO_4K; 5388 /* RTL8168c */ 5389 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5390 return JUMBO_6K; 5391 default: 5392 return JUMBO_9K; 5393 } 5394 } 5395 5396 static void rtl_init_mac_address(struct rtl8169_private *tp) 5397 { 5398 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5399 struct net_device *dev = tp->dev; 5400 int rc; 5401 5402 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5403 if (!rc) 5404 goto done; 5405 5406 rtl_read_mac_address(tp, mac_addr); 5407 if (is_valid_ether_addr(mac_addr)) 5408 goto done; 5409 5410 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5411 if (is_valid_ether_addr(mac_addr)) 5412 goto done; 5413 5414 eth_random_addr(mac_addr); 5415 dev->addr_assign_type = NET_ADDR_RANDOM; 5416 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5417 done: 5418 eth_hw_addr_set(dev, mac_addr); 5419 rtl_rar_set(tp, mac_addr); 5420 } 5421 5422 /* register is set if system vendor successfully tested ASPM 1.2 */ 5423 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5424 { 5425 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5426 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5427 return true; 5428 5429 return false; 5430 } 5431 5432 static umode_t r8169_hwmon_is_visible(const void *drvdata, 5433 enum hwmon_sensor_types type, 5434 u32 attr, int channel) 5435 { 5436 return 0444; 5437 } 5438 5439 static int r8169_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 5440 u32 attr, int channel, long *val) 5441 { 5442 struct rtl8169_private *tp = dev_get_drvdata(dev); 5443 int val_raw; 5444 5445 val_raw = phy_read_paged(tp->phydev, 0xbd8, 0x12) & 0x3ff; 5446 if (val_raw >= 512) 5447 val_raw -= 1024; 5448 5449 *val = 1000 * val_raw / 2; 5450 5451 return 0; 5452 } 5453 5454 static const struct hwmon_ops r8169_hwmon_ops = { 5455 .is_visible = r8169_hwmon_is_visible, 5456 .read = r8169_hwmon_read, 5457 }; 5458 5459 static const struct hwmon_channel_info * const r8169_hwmon_info[] = { 5460 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 5461 NULL 5462 }; 5463 5464 static const struct hwmon_chip_info r8169_hwmon_chip_info = { 5465 .ops = &r8169_hwmon_ops, 5466 .info = r8169_hwmon_info, 5467 }; 5468 5469 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5470 { 5471 struct rtl8169_private *tp; 5472 int jumbo_max, region, rc; 5473 enum mac_version chipset; 5474 struct net_device *dev; 5475 u32 txconfig; 5476 u16 xid; 5477 5478 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5479 if (!dev) 5480 return -ENOMEM; 5481 5482 SET_NETDEV_DEV(dev, &pdev->dev); 5483 dev->netdev_ops = &rtl_netdev_ops; 5484 tp = netdev_priv(dev); 5485 tp->dev = dev; 5486 tp->pci_dev = pdev; 5487 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5488 tp->ocp_base = OCP_STD_PHY_BASE; 5489 5490 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5491 raw_spin_lock_init(&tp->config25_lock); 5492 raw_spin_lock_init(&tp->mac_ocp_lock); 5493 mutex_init(&tp->led_lock); 5494 5495 /* Get the *optional* external "ether_clk" used on some boards */ 5496 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5497 if (IS_ERR(tp->clk)) 5498 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5499 5500 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5501 rc = pcim_enable_device(pdev); 5502 if (rc < 0) 5503 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5504 5505 if (pcim_set_mwi(pdev) < 0) 5506 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5507 5508 /* use first MMIO region */ 5509 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5510 if (region < 0) 5511 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5512 5513 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5514 if (rc < 0) 5515 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5516 5517 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5518 5519 txconfig = RTL_R32(tp, TxConfig); 5520 if (txconfig == ~0U) 5521 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5522 5523 xid = (txconfig >> 20) & 0xfcf; 5524 5525 /* Identify chip attached to board */ 5526 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5527 if (chipset == RTL_GIGA_MAC_NONE) 5528 return dev_err_probe(&pdev->dev, -ENODEV, 5529 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5530 xid); 5531 tp->mac_version = chipset; 5532 5533 /* Disable ASPM L1 as that cause random device stop working 5534 * problems as well as full system hangs for some PCIe devices users. 5535 */ 5536 if (rtl_aspm_is_safe(tp)) 5537 rc = 0; 5538 else 5539 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5540 tp->aspm_manageable = !rc; 5541 5542 tp->dash_type = rtl_get_dash_type(tp); 5543 tp->dash_enabled = rtl_dash_is_enabled(tp); 5544 5545 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5546 5547 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5548 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5549 dev->features |= NETIF_F_HIGHDMA; 5550 5551 rtl_init_rxcfg(tp); 5552 5553 rtl8169_irq_mask_and_ack(tp); 5554 5555 rtl_hw_initialize(tp); 5556 5557 rtl_hw_reset(tp); 5558 5559 rc = rtl_alloc_irq(tp); 5560 if (rc < 0) 5561 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5562 5563 tp->irq = pci_irq_vector(pdev, 0); 5564 5565 INIT_WORK(&tp->wk.work, rtl_task); 5566 disable_work(&tp->wk.work); 5567 5568 rtl_init_mac_address(tp); 5569 5570 dev->ethtool_ops = &rtl8169_ethtool_ops; 5571 5572 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5573 5574 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5575 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5576 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5577 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5578 5579 /* 5580 * Pretend we are using VLANs; This bypasses a nasty bug where 5581 * Interrupts stop flowing on high load on 8110SCd controllers. 5582 */ 5583 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5584 /* Disallow toggling */ 5585 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5586 5587 if (rtl_chip_supports_csum_v2(tp)) 5588 dev->hw_features |= NETIF_F_IPV6_CSUM; 5589 5590 dev->features |= dev->hw_features; 5591 5592 if (rtl_chip_supports_csum_v2(tp)) { 5593 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5594 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5595 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5596 } else { 5597 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5598 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5599 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5600 } 5601 5602 /* There has been a number of reports that using SG/TSO results in 5603 * tx timeouts. However for a lot of people SG/TSO works fine. 5604 * It's not fully clear which chip versions are affected. Vendor 5605 * drivers enable SG/TSO for certain chip versions per default, 5606 * let's mimic this here. On other chip versions users can 5607 * use ethtool to enable SG/TSO, use at own risk! 5608 */ 5609 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5610 tp->mac_version != RTL_GIGA_MAC_VER_61) 5611 dev->features |= dev->hw_features; 5612 5613 dev->hw_features |= NETIF_F_RXALL; 5614 dev->hw_features |= NETIF_F_RXFCS; 5615 5616 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5617 5618 netdev_sw_irq_coalesce_default_on(dev); 5619 5620 /* configure chip for default features */ 5621 rtl8169_set_features(dev, dev->features); 5622 5623 if (!tp->dash_enabled) { 5624 rtl_set_d3_pll_down(tp, true); 5625 } else { 5626 rtl_set_d3_pll_down(tp, false); 5627 dev->ethtool->wol_enabled = 1; 5628 } 5629 5630 jumbo_max = rtl_jumbo_max(tp); 5631 if (jumbo_max) 5632 dev->max_mtu = jumbo_max; 5633 5634 rtl_set_irq_mask(tp); 5635 5636 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5637 5638 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5639 &tp->counters_phys_addr, 5640 GFP_KERNEL); 5641 if (!tp->counters) 5642 return -ENOMEM; 5643 5644 pci_set_drvdata(pdev, tp); 5645 5646 rc = r8169_mdio_register(tp); 5647 if (rc) 5648 return rc; 5649 5650 /* The temperature sensor is available from RTl8125B */ 5651 if (IS_REACHABLE(CONFIG_HWMON) && tp->mac_version >= RTL_GIGA_MAC_VER_63) 5652 /* ignore errors */ 5653 devm_hwmon_device_register_with_info(&pdev->dev, "nic_temp", tp, 5654 &r8169_hwmon_chip_info, 5655 NULL); 5656 rc = register_netdev(dev); 5657 if (rc) 5658 return rc; 5659 5660 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5661 if (rtl_is_8125(tp)) 5662 tp->leds = rtl8125_init_leds(dev); 5663 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5664 tp->leds = rtl8168_init_leds(dev); 5665 } 5666 5667 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5668 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5669 5670 if (jumbo_max) 5671 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5672 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5673 "ok" : "ko"); 5674 5675 if (tp->dash_type != RTL_DASH_NONE) { 5676 netdev_info(dev, "DASH %s\n", 5677 tp->dash_enabled ? "enabled" : "disabled"); 5678 rtl8168_driver_start(tp); 5679 } 5680 5681 if (pci_dev_run_wake(pdev)) 5682 pm_runtime_put_sync(&pdev->dev); 5683 5684 return 0; 5685 } 5686 5687 static struct pci_driver rtl8169_pci_driver = { 5688 .name = KBUILD_MODNAME, 5689 .id_table = rtl8169_pci_tbl, 5690 .probe = rtl_init_one, 5691 .remove = rtl_remove_one, 5692 .shutdown = rtl_shutdown, 5693 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5694 }; 5695 5696 module_pci_driver(rtl8169_pci_driver); 5697