1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <linux/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" 59 #define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw" 60 #define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw" 61 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 62 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 63 64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 66 67 #define R8169_REGS_SIZE 256 68 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 69 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 70 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 73 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 74 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 75 76 #define OCP_STD_PHY_BASE 0xa400 77 78 #define RTL_CFG_NO_GBIT 1 79 80 /* write/read MMIO register */ 81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 87 88 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 92 #define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN) 93 94 static const struct { 95 const char *name; 96 const char *fw_name; 97 } rtl_chip_infos[] = { 98 /* PCI devices. */ 99 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 100 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 101 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 102 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 103 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 104 /* PCI-E devices. */ 105 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 106 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 107 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 108 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 109 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 110 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 111 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 112 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 117 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 118 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 119 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 120 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 121 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 122 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 123 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 125 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 126 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 127 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 128 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 129 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 130 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 131 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 132 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 133 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 134 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 135 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 136 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 137 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 138 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 139 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 140 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 141 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 142 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 143 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 144 [RTL_GIGA_MAC_VER_64] = {"RTL8125D", FIRMWARE_8125D_1}, 145 [RTL_GIGA_MAC_VER_65] = {"RTL8125D", FIRMWARE_8125D_2}, 146 [RTL_GIGA_MAC_VER_66] = {"RTL8125BP", FIRMWARE_8125BP_2}, 147 [RTL_GIGA_MAC_VER_70] = {"RTL8126A", FIRMWARE_8126A_2}, 148 [RTL_GIGA_MAC_VER_71] = {"RTL8126A", FIRMWARE_8126A_3}, 149 }; 150 151 static const struct pci_device_id rtl8169_pci_tbl[] = { 152 { PCI_VDEVICE(REALTEK, 0x2502) }, 153 { PCI_VDEVICE(REALTEK, 0x2600) }, 154 { PCI_VDEVICE(REALTEK, 0x8129) }, 155 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 156 { PCI_VDEVICE(REALTEK, 0x8161) }, 157 { PCI_VDEVICE(REALTEK, 0x8162) }, 158 { PCI_VDEVICE(REALTEK, 0x8167) }, 159 { PCI_VDEVICE(REALTEK, 0x8168) }, 160 { PCI_VDEVICE(NCUBE, 0x8168) }, 161 { PCI_VDEVICE(REALTEK, 0x8169) }, 162 { PCI_VENDOR_ID_DLINK, 0x4300, 163 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 164 { PCI_VDEVICE(DLINK, 0x4300) }, 165 { PCI_VDEVICE(DLINK, 0x4302) }, 166 { PCI_VDEVICE(AT, 0xc107) }, 167 { PCI_VDEVICE(USR, 0x0116) }, 168 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 169 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 170 { PCI_VDEVICE(REALTEK, 0x8125) }, 171 { PCI_VDEVICE(REALTEK, 0x8126) }, 172 { PCI_VDEVICE(REALTEK, 0x3000) }, 173 { PCI_VDEVICE(REALTEK, 0x5000) }, 174 {} 175 }; 176 177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 178 179 enum rtl_registers { 180 MAC0 = 0, /* Ethernet hardware address. */ 181 MAC4 = 4, 182 MAR0 = 8, /* Multicast filter. */ 183 CounterAddrLow = 0x10, 184 CounterAddrHigh = 0x14, 185 TxDescStartAddrLow = 0x20, 186 TxDescStartAddrHigh = 0x24, 187 TxHDescStartAddrLow = 0x28, 188 TxHDescStartAddrHigh = 0x2c, 189 FLASH = 0x30, 190 ERSR = 0x36, 191 ChipCmd = 0x37, 192 TxPoll = 0x38, 193 IntrMask = 0x3c, 194 IntrStatus = 0x3e, 195 196 TxConfig = 0x40, 197 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 198 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 199 200 RxConfig = 0x44, 201 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 202 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 203 #define RXCFG_FIFO_SHIFT 13 204 /* No threshold before first PCI xfer */ 205 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 206 #define RX_EARLY_OFF (1 << 11) 207 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 208 #define RXCFG_DMA_SHIFT 8 209 /* Unlimited maximum PCI burst. */ 210 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 211 212 Cfg9346 = 0x50, 213 Config0 = 0x51, 214 Config1 = 0x52, 215 Config2 = 0x53, 216 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 217 218 Config3 = 0x54, 219 Config4 = 0x55, 220 Config5 = 0x56, 221 PHYAR = 0x60, 222 PHYstatus = 0x6c, 223 RxMaxSize = 0xda, 224 CPlusCmd = 0xe0, 225 IntrMitigate = 0xe2, 226 227 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 228 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 229 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 230 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 231 232 #define RTL_COALESCE_T_MAX 0x0fU 233 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 234 235 RxDescAddrLow = 0xe4, 236 RxDescAddrHigh = 0xe8, 237 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 238 239 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 240 241 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 242 243 #define TxPacketMax (8064 >> 7) 244 #define EarlySize 0x27 245 246 FuncEvent = 0xf0, 247 FuncEventMask = 0xf4, 248 FuncPresetState = 0xf8, 249 IBCR0 = 0xf8, 250 IBCR2 = 0xf9, 251 IBIMR0 = 0xfa, 252 IBISR0 = 0xfb, 253 FuncForceEvent = 0xfc, 254 }; 255 256 enum rtl8168_8101_registers { 257 CSIDR = 0x64, 258 CSIAR = 0x68, 259 #define CSIAR_FLAG 0x80000000 260 #define CSIAR_WRITE_CMD 0x80000000 261 #define CSIAR_BYTE_ENABLE 0x0000f000 262 #define CSIAR_ADDR_MASK 0x00000fff 263 PMCH = 0x6f, 264 #define D3COLD_NO_PLL_DOWN BIT(7) 265 #define D3HOT_NO_PLL_DOWN BIT(6) 266 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 267 EPHYAR = 0x80, 268 #define EPHYAR_FLAG 0x80000000 269 #define EPHYAR_WRITE_CMD 0x80000000 270 #define EPHYAR_REG_MASK 0x1f 271 #define EPHYAR_REG_SHIFT 16 272 #define EPHYAR_DATA_MASK 0xffff 273 DLLPR = 0xd0, 274 #define PFM_EN (1 << 6) 275 #define TX_10M_PS_EN (1 << 7) 276 DBG_REG = 0xd1, 277 #define FIX_NAK_1 (1 << 4) 278 #define FIX_NAK_2 (1 << 3) 279 TWSI = 0xd2, 280 MCU = 0xd3, 281 #define NOW_IS_OOB (1 << 7) 282 #define TX_EMPTY (1 << 5) 283 #define RX_EMPTY (1 << 4) 284 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 285 #define EN_NDP (1 << 3) 286 #define EN_OOB_RESET (1 << 2) 287 #define LINK_LIST_RDY (1 << 1) 288 EFUSEAR = 0xdc, 289 #define EFUSEAR_FLAG 0x80000000 290 #define EFUSEAR_WRITE_CMD 0x80000000 291 #define EFUSEAR_READ_CMD 0x00000000 292 #define EFUSEAR_REG_MASK 0x03ff 293 #define EFUSEAR_REG_SHIFT 8 294 #define EFUSEAR_DATA_MASK 0xff 295 MISC_1 = 0xf2, 296 #define PFM_D3COLD_EN (1 << 6) 297 }; 298 299 enum rtl8168_registers { 300 LED_CTRL = 0x18, 301 LED_FREQ = 0x1a, 302 EEE_LED = 0x1b, 303 ERIDR = 0x70, 304 ERIAR = 0x74, 305 #define ERIAR_FLAG 0x80000000 306 #define ERIAR_WRITE_CMD 0x80000000 307 #define ERIAR_READ_CMD 0x00000000 308 #define ERIAR_ADDR_BYTE_ALIGN 4 309 #define ERIAR_TYPE_SHIFT 16 310 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 312 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 313 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 314 #define ERIAR_MASK_SHIFT 12 315 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 317 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 318 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 319 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 320 EPHY_RXER_NUM = 0x7c, 321 OCPDR = 0xb0, /* OCP GPHY access */ 322 #define OCPDR_WRITE_CMD 0x80000000 323 #define OCPDR_READ_CMD 0x00000000 324 #define OCPDR_REG_MASK 0x7f 325 #define OCPDR_GPHY_REG_SHIFT 16 326 #define OCPDR_DATA_MASK 0xffff 327 OCPAR = 0xb4, 328 #define OCPAR_FLAG 0x80000000 329 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 330 #define OCPAR_GPHY_READ_CMD 0x0000f060 331 GPHY_OCP = 0xb8, 332 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 333 MISC = 0xf0, /* 8168e only. */ 334 #define TXPLA_RST (1 << 29) 335 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 336 #define PWM_EN (1 << 22) 337 #define RXDV_GATED_EN (1 << 19) 338 #define EARLY_TALLY_EN (1 << 16) 339 }; 340 341 enum rtl8125_registers { 342 LEDSEL0 = 0x18, 343 INT_CFG0_8125 = 0x34, 344 #define INT_CFG0_ENABLE_8125 BIT(0) 345 #define INT_CFG0_CLKREQEN BIT(3) 346 IntrMask_8125 = 0x38, 347 IntrStatus_8125 = 0x3c, 348 INT_CFG1_8125 = 0x7a, 349 LEDSEL2 = 0x84, 350 LEDSEL1 = 0x86, 351 TxPoll_8125 = 0x90, 352 LEDSEL3 = 0x96, 353 MAC0_BKP = 0x19e0, 354 RSS_CTRL_8125 = 0x4500, 355 Q_NUM_CTRL_8125 = 0x4800, 356 EEE_TXIDLE_TIMER_8125 = 0x6048, 357 }; 358 359 #define LEDSEL_MASK_8125 0x23f 360 361 #define RX_VLAN_INNER_8125 BIT(22) 362 #define RX_VLAN_OUTER_8125 BIT(23) 363 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 364 365 #define RX_FETCH_DFLT_8125 (8 << 27) 366 367 enum rtl_register_content { 368 /* InterruptStatusBits */ 369 SYSErr = 0x8000, 370 PCSTimeout = 0x4000, 371 SWInt = 0x0100, 372 TxDescUnavail = 0x0080, 373 RxFIFOOver = 0x0040, 374 LinkChg = 0x0020, 375 RxOverflow = 0x0010, 376 TxErr = 0x0008, 377 TxOK = 0x0004, 378 RxErr = 0x0002, 379 RxOK = 0x0001, 380 381 /* RxStatusDesc */ 382 RxRWT = (1 << 22), 383 RxRES = (1 << 21), 384 RxRUNT = (1 << 20), 385 RxCRC = (1 << 19), 386 387 /* ChipCmdBits */ 388 StopReq = 0x80, 389 CmdReset = 0x10, 390 CmdRxEnb = 0x08, 391 CmdTxEnb = 0x04, 392 RxBufEmpty = 0x01, 393 394 /* TXPoll register p.5 */ 395 HPQ = 0x80, /* Poll cmd on the high prio queue */ 396 NPQ = 0x40, /* Poll cmd on the low prio queue */ 397 FSWInt = 0x01, /* Forced software interrupt */ 398 399 /* Cfg9346Bits */ 400 Cfg9346_Lock = 0x00, 401 Cfg9346_Unlock = 0xc0, 402 403 /* rx_mode_bits */ 404 AcceptErr = 0x20, 405 AcceptRunt = 0x10, 406 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 407 AcceptBroadcast = 0x08, 408 AcceptMulticast = 0x04, 409 AcceptMyPhys = 0x02, 410 AcceptAllPhys = 0x01, 411 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 412 #define RX_CONFIG_ACCEPT_MASK 0x3f 413 414 /* TxConfigBits */ 415 TxInterFrameGapShift = 24, 416 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 417 418 /* Config1 register p.24 */ 419 LEDS1 = (1 << 7), 420 LEDS0 = (1 << 6), 421 Speed_down = (1 << 4), 422 MEMMAP = (1 << 3), 423 IOMAP = (1 << 2), 424 VPD = (1 << 1), 425 PMEnable = (1 << 0), /* Power Management Enable */ 426 427 /* Config2 register p. 25 */ 428 ClkReqEn = (1 << 7), /* Clock Request Enable */ 429 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 430 PCI_Clock_66MHz = 0x01, 431 PCI_Clock_33MHz = 0x00, 432 433 /* Config3 register p.25 */ 434 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 435 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 436 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 437 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 438 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 439 440 /* Config4 register */ 441 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 442 443 /* Config5 register p.27 */ 444 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 445 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 446 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 447 Spi_en = (1 << 3), 448 LanWake = (1 << 1), /* LanWake enable/disable */ 449 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 450 ASPM_en = (1 << 0), /* ASPM enable */ 451 452 /* CPlusCmd p.31 */ 453 EnableBist = (1 << 15), // 8168 8101 454 Mac_dbgo_oe = (1 << 14), // 8168 8101 455 EnAnaPLL = (1 << 14), // 8169 456 Normal_mode = (1 << 13), // unused 457 Force_half_dup = (1 << 12), // 8168 8101 458 Force_rxflow_en = (1 << 11), // 8168 8101 459 Force_txflow_en = (1 << 10), // 8168 8101 460 Cxpl_dbg_sel = (1 << 9), // 8168 8101 461 ASF = (1 << 8), // 8168 8101 462 PktCntrDisable = (1 << 7), // 8168 8101 463 Mac_dbgo_sel = 0x001c, // 8168 464 RxVlan = (1 << 6), 465 RxChkSum = (1 << 5), 466 PCIDAC = (1 << 4), 467 PCIMulRW = (1 << 3), 468 #define INTT_MASK GENMASK(1, 0) 469 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 470 471 /* rtl8169_PHYstatus */ 472 TBI_Enable = 0x80, 473 TxFlowCtrl = 0x40, 474 RxFlowCtrl = 0x20, 475 _1000bpsF = 0x10, 476 _100bps = 0x08, 477 _10bps = 0x04, 478 LinkStatus = 0x02, 479 FullDup = 0x01, 480 481 /* ResetCounterCommand */ 482 CounterReset = 0x1, 483 484 /* DumpCounterCommand */ 485 CounterDump = 0x8, 486 487 /* magic enable v2 */ 488 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 489 }; 490 491 enum rtl_desc_bit { 492 /* First doubleword. */ 493 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 494 RingEnd = (1 << 30), /* End of descriptor ring */ 495 FirstFrag = (1 << 29), /* First segment of a packet */ 496 LastFrag = (1 << 28), /* Final segment of a packet */ 497 }; 498 499 /* Generic case. */ 500 enum rtl_tx_desc_bit { 501 /* First doubleword. */ 502 TD_LSO = (1 << 27), /* Large Send Offload */ 503 #define TD_MSS_MAX 0x07ffu /* MSS value */ 504 505 /* Second doubleword. */ 506 TxVlanTag = (1 << 17), /* Add VLAN tag */ 507 }; 508 509 /* 8169, 8168b and 810x except 8102e. */ 510 enum rtl_tx_desc_bit_0 { 511 /* First doubleword. */ 512 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 513 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 514 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 515 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 516 }; 517 518 /* 8102e, 8168c and beyond. */ 519 enum rtl_tx_desc_bit_1 { 520 /* First doubleword. */ 521 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 522 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 523 #define GTTCPHO_SHIFT 18 524 #define GTTCPHO_MAX 0x7f 525 526 /* Second doubleword. */ 527 #define TCPHO_SHIFT 18 528 #define TCPHO_MAX 0x3ff 529 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 530 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 531 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 532 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 533 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 534 }; 535 536 enum rtl_rx_desc_bit { 537 /* Rx private */ 538 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 539 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 540 541 #define RxProtoUDP (PID1) 542 #define RxProtoTCP (PID0) 543 #define RxProtoIP (PID1 | PID0) 544 #define RxProtoMask RxProtoIP 545 546 IPFail = (1 << 16), /* IP checksum failed */ 547 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 548 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 549 550 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 551 552 RxVlanTag = (1 << 16), /* VLAN tag available */ 553 }; 554 555 #define RTL_GSO_MAX_SIZE_V1 32000 556 #define RTL_GSO_MAX_SEGS_V1 24 557 #define RTL_GSO_MAX_SIZE_V2 64000 558 #define RTL_GSO_MAX_SEGS_V2 64 559 560 struct TxDesc { 561 __le32 opts1; 562 __le32 opts2; 563 __le64 addr; 564 }; 565 566 struct RxDesc { 567 __le32 opts1; 568 __le32 opts2; 569 __le64 addr; 570 }; 571 572 struct ring_info { 573 struct sk_buff *skb; 574 u32 len; 575 }; 576 577 struct rtl8169_counters { 578 __le64 tx_packets; 579 __le64 rx_packets; 580 __le64 tx_errors; 581 __le32 rx_errors; 582 __le16 rx_missed; 583 __le16 align_errors; 584 __le32 tx_one_collision; 585 __le32 tx_multi_collision; 586 __le64 rx_unicast; 587 __le64 rx_broadcast; 588 __le32 rx_multicast; 589 __le16 tx_aborted; 590 __le16 tx_underrun; 591 /* new since RTL8125 */ 592 __le64 tx_octets; 593 __le64 rx_octets; 594 __le64 rx_multicast64; 595 __le64 tx_unicast64; 596 __le64 tx_broadcast64; 597 __le64 tx_multicast64; 598 __le32 tx_pause_on; 599 __le32 tx_pause_off; 600 __le32 tx_pause_all; 601 __le32 tx_deferred; 602 __le32 tx_late_collision; 603 __le32 tx_all_collision; 604 __le32 tx_aborted32; 605 __le32 align_errors32; 606 __le32 rx_frame_too_long; 607 __le32 rx_runt; 608 __le32 rx_pause_on; 609 __le32 rx_pause_off; 610 __le32 rx_pause_all; 611 __le32 rx_unknown_opcode; 612 __le32 rx_mac_error; 613 __le32 tx_underrun32; 614 __le32 rx_mac_missed; 615 __le32 rx_tcam_dropped; 616 __le32 tdu; 617 __le32 rdu; 618 }; 619 620 struct rtl8169_tc_offsets { 621 bool inited; 622 __le64 tx_errors; 623 __le32 tx_multi_collision; 624 __le16 tx_aborted; 625 __le16 rx_missed; 626 }; 627 628 enum rtl_flag { 629 RTL_FLAG_TASK_RESET_PENDING, 630 RTL_FLAG_TASK_TX_TIMEOUT, 631 RTL_FLAG_MAX 632 }; 633 634 enum rtl_dash_type { 635 RTL_DASH_NONE, 636 RTL_DASH_DP, 637 RTL_DASH_EP, 638 RTL_DASH_25_BP, 639 }; 640 641 struct rtl8169_private { 642 void __iomem *mmio_addr; /* memory map physical address */ 643 struct pci_dev *pci_dev; 644 struct net_device *dev; 645 struct phy_device *phydev; 646 struct napi_struct napi; 647 enum mac_version mac_version; 648 enum rtl_dash_type dash_type; 649 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 650 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 651 u32 dirty_tx; 652 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 653 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 654 dma_addr_t TxPhyAddr; 655 dma_addr_t RxPhyAddr; 656 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 657 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 658 u16 cp_cmd; 659 u16 tx_lpi_timer; 660 u32 irq_mask; 661 int irq; 662 struct clk *clk; 663 664 struct { 665 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 666 struct work_struct work; 667 } wk; 668 669 raw_spinlock_t mac_ocp_lock; 670 struct mutex led_lock; /* serialize LED ctrl RMW access */ 671 672 unsigned supports_gmii:1; 673 unsigned aspm_manageable:1; 674 unsigned dash_enabled:1; 675 dma_addr_t counters_phys_addr; 676 struct rtl8169_counters *counters; 677 struct rtl8169_tc_offsets tc_offset; 678 u32 saved_wolopts; 679 680 const char *fw_name; 681 struct rtl_fw *rtl_fw; 682 683 struct r8169_led_classdev *leds; 684 685 u32 ocp_base; 686 }; 687 688 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 689 690 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 691 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 692 MODULE_SOFTDEP("pre: realtek"); 693 MODULE_LICENSE("GPL"); 694 MODULE_FIRMWARE(FIRMWARE_8168D_1); 695 MODULE_FIRMWARE(FIRMWARE_8168D_2); 696 MODULE_FIRMWARE(FIRMWARE_8168E_1); 697 MODULE_FIRMWARE(FIRMWARE_8168E_2); 698 MODULE_FIRMWARE(FIRMWARE_8168E_3); 699 MODULE_FIRMWARE(FIRMWARE_8105E_1); 700 MODULE_FIRMWARE(FIRMWARE_8168F_1); 701 MODULE_FIRMWARE(FIRMWARE_8168F_2); 702 MODULE_FIRMWARE(FIRMWARE_8402_1); 703 MODULE_FIRMWARE(FIRMWARE_8411_1); 704 MODULE_FIRMWARE(FIRMWARE_8411_2); 705 MODULE_FIRMWARE(FIRMWARE_8106E_1); 706 MODULE_FIRMWARE(FIRMWARE_8106E_2); 707 MODULE_FIRMWARE(FIRMWARE_8168G_2); 708 MODULE_FIRMWARE(FIRMWARE_8168G_3); 709 MODULE_FIRMWARE(FIRMWARE_8168H_2); 710 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 711 MODULE_FIRMWARE(FIRMWARE_8107E_2); 712 MODULE_FIRMWARE(FIRMWARE_8125A_3); 713 MODULE_FIRMWARE(FIRMWARE_8125B_2); 714 MODULE_FIRMWARE(FIRMWARE_8125D_1); 715 MODULE_FIRMWARE(FIRMWARE_8125D_2); 716 MODULE_FIRMWARE(FIRMWARE_8125BP_2); 717 MODULE_FIRMWARE(FIRMWARE_8126A_2); 718 MODULE_FIRMWARE(FIRMWARE_8126A_3); 719 720 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 721 { 722 return &tp->pci_dev->dev; 723 } 724 725 static void rtl_lock_config_regs(struct rtl8169_private *tp) 726 { 727 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 728 } 729 730 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 731 { 732 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 733 } 734 735 static void rtl_pci_commit(struct rtl8169_private *tp) 736 { 737 /* Read an arbitrary register to commit a preceding PCI write */ 738 RTL_R8(tp, ChipCmd); 739 } 740 741 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 742 { 743 u8 val; 744 745 val = RTL_R8(tp, Config2); 746 RTL_W8(tp, Config2, (val & ~clear) | set); 747 } 748 749 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 750 { 751 u8 val; 752 753 val = RTL_R8(tp, Config5); 754 RTL_W8(tp, Config5, (val & ~clear) | set); 755 } 756 757 static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg, 758 u8 bits, bool cond) 759 { 760 u8 val, old_val; 761 762 old_val = RTL_R8(tp, reg); 763 if (cond) 764 val = old_val | bits; 765 else 766 val = old_val & ~bits; 767 if (val != old_val) 768 RTL_W8(tp, reg, val); 769 } 770 771 static bool rtl_is_8125(struct rtl8169_private *tp) 772 { 773 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 774 } 775 776 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 777 { 778 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 779 tp->mac_version != RTL_GIGA_MAC_VER_39 && 780 tp->mac_version <= RTL_GIGA_MAC_VER_53; 781 } 782 783 static bool rtl_supports_eee(struct rtl8169_private *tp) 784 { 785 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 786 tp->mac_version != RTL_GIGA_MAC_VER_37 && 787 tp->mac_version != RTL_GIGA_MAC_VER_39; 788 } 789 790 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 791 { 792 int i; 793 794 for (i = 0; i < ETH_ALEN; i++) 795 mac[i] = RTL_R8(tp, reg + i); 796 } 797 798 struct rtl_cond { 799 bool (*check)(struct rtl8169_private *); 800 const char *msg; 801 }; 802 803 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 804 unsigned long usecs, int n, bool high) 805 { 806 int i; 807 808 for (i = 0; i < n; i++) { 809 if (c->check(tp) == high) 810 return true; 811 fsleep(usecs); 812 } 813 814 if (net_ratelimit()) 815 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 816 c->msg, !high, n, usecs); 817 return false; 818 } 819 820 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 821 const struct rtl_cond *c, 822 unsigned long d, int n) 823 { 824 return rtl_loop_wait(tp, c, d, n, true); 825 } 826 827 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 828 const struct rtl_cond *c, 829 unsigned long d, int n) 830 { 831 return rtl_loop_wait(tp, c, d, n, false); 832 } 833 834 #define DECLARE_RTL_COND(name) \ 835 static bool name ## _check(struct rtl8169_private *); \ 836 \ 837 static const struct rtl_cond name = { \ 838 .check = name ## _check, \ 839 .msg = #name \ 840 }; \ 841 \ 842 static bool name ## _check(struct rtl8169_private *tp) 843 844 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 845 { 846 struct device *dev = tp_to_dev(tp); 847 int ret; 848 849 ret = pm_runtime_resume_and_get(dev); 850 if (ret < 0) 851 return ret; 852 853 mutex_lock(&tp->led_lock); 854 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 855 mutex_unlock(&tp->led_lock); 856 857 pm_runtime_put_sync(dev); 858 859 return 0; 860 } 861 862 int rtl8168_get_led_mode(struct rtl8169_private *tp) 863 { 864 struct device *dev = tp_to_dev(tp); 865 int ret; 866 867 ret = pm_runtime_resume_and_get(dev); 868 if (ret < 0) 869 return ret; 870 871 ret = RTL_R16(tp, LED_CTRL); 872 873 pm_runtime_put_sync(dev); 874 875 return ret; 876 } 877 878 static int rtl8125_get_led_reg(int index) 879 { 880 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 881 882 return led_regs[index]; 883 } 884 885 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 886 { 887 int reg = rtl8125_get_led_reg(index); 888 struct device *dev = tp_to_dev(tp); 889 int ret; 890 u16 val; 891 892 ret = pm_runtime_resume_and_get(dev); 893 if (ret < 0) 894 return ret; 895 896 mutex_lock(&tp->led_lock); 897 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 898 RTL_W16(tp, reg, val | mode); 899 mutex_unlock(&tp->led_lock); 900 901 pm_runtime_put_sync(dev); 902 903 return 0; 904 } 905 906 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 907 { 908 int reg = rtl8125_get_led_reg(index); 909 struct device *dev = tp_to_dev(tp); 910 int ret; 911 912 ret = pm_runtime_resume_and_get(dev); 913 if (ret < 0) 914 return ret; 915 916 ret = RTL_R16(tp, reg); 917 918 pm_runtime_put_sync(dev); 919 920 return ret; 921 } 922 923 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 924 char *buf, int buf_len) 925 { 926 struct pci_dev *pdev = tp->pci_dev; 927 char pdom[8], pfun[8]; 928 int domain; 929 930 domain = pci_domain_nr(pdev->bus); 931 if (domain) 932 snprintf(pdom, sizeof(pdom), "P%d", domain); 933 else 934 pdom[0] = '\0'; 935 936 if (pdev->multifunction) 937 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 938 else 939 pfun[0] = '\0'; 940 941 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 942 PCI_SLOT(pdev->devfn), pfun, idx); 943 } 944 945 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 946 { 947 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 948 if (type == ERIAR_OOB && 949 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 950 tp->mac_version == RTL_GIGA_MAC_VER_53)) 951 *cmd |= 0xf70 << 18; 952 } 953 954 DECLARE_RTL_COND(rtl_eriar_cond) 955 { 956 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 957 } 958 959 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 960 u32 val, int type) 961 { 962 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 963 964 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 965 return; 966 967 RTL_W32(tp, ERIDR, val); 968 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 969 RTL_W32(tp, ERIAR, cmd); 970 971 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 972 } 973 974 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 975 u32 val) 976 { 977 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 978 } 979 980 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 981 { 982 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 983 984 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 985 RTL_W32(tp, ERIAR, cmd); 986 987 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 988 RTL_R32(tp, ERIDR) : ~0; 989 } 990 991 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 992 { 993 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 994 } 995 996 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 997 { 998 u32 val = rtl_eri_read(tp, addr); 999 1000 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 1001 } 1002 1003 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1004 { 1005 rtl_w0w1_eri(tp, addr, p, 0); 1006 } 1007 1008 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1009 { 1010 rtl_w0w1_eri(tp, addr, 0, m); 1011 } 1012 1013 static bool rtl_ocp_reg_failure(u32 reg) 1014 { 1015 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1016 } 1017 1018 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1019 { 1020 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1021 } 1022 1023 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1024 { 1025 if (rtl_ocp_reg_failure(reg)) 1026 return; 1027 1028 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1029 1030 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1031 } 1032 1033 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1034 { 1035 if (rtl_ocp_reg_failure(reg)) 1036 return 0; 1037 1038 RTL_W32(tp, GPHY_OCP, reg << 15); 1039 1040 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1041 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1042 } 1043 1044 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1045 { 1046 if (rtl_ocp_reg_failure(reg)) 1047 return; 1048 1049 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1050 } 1051 1052 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1053 { 1054 unsigned long flags; 1055 1056 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1057 __r8168_mac_ocp_write(tp, reg, data); 1058 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1059 } 1060 1061 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1062 { 1063 if (rtl_ocp_reg_failure(reg)) 1064 return 0; 1065 1066 RTL_W32(tp, OCPDR, reg << 15); 1067 1068 return RTL_R32(tp, OCPDR); 1069 } 1070 1071 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1072 { 1073 unsigned long flags; 1074 u16 val; 1075 1076 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1077 val = __r8168_mac_ocp_read(tp, reg); 1078 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1079 1080 return val; 1081 } 1082 1083 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1084 u16 set) 1085 { 1086 unsigned long flags; 1087 u16 data; 1088 1089 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1090 data = __r8168_mac_ocp_read(tp, reg); 1091 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1092 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1093 } 1094 1095 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1096 * PHY MCU interrupts before PHY power-down. 1097 */ 1098 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1099 { 1100 switch (tp->mac_version) { 1101 case RTL_GIGA_MAC_VER_40: 1102 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1103 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1104 else 1105 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1106 break; 1107 default: 1108 break; 1109 } 1110 }; 1111 1112 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1113 { 1114 if (reg == 0x1f) { 1115 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1116 return; 1117 } 1118 1119 if (tp->ocp_base != OCP_STD_PHY_BASE) 1120 reg -= 0x10; 1121 1122 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1123 rtl8168g_phy_suspend_quirk(tp, value); 1124 1125 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1126 } 1127 1128 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1129 { 1130 if (reg == 0x1f) 1131 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1132 1133 if (tp->ocp_base != OCP_STD_PHY_BASE) 1134 reg -= 0x10; 1135 1136 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1137 } 1138 1139 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1140 { 1141 if (reg == 0x1f) { 1142 tp->ocp_base = value << 4; 1143 return; 1144 } 1145 1146 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1147 } 1148 1149 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1150 { 1151 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1152 } 1153 1154 DECLARE_RTL_COND(rtl_phyar_cond) 1155 { 1156 return RTL_R32(tp, PHYAR) & 0x80000000; 1157 } 1158 1159 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1160 { 1161 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1162 1163 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1164 /* 1165 * According to hardware specs a 20us delay is required after write 1166 * complete indication, but before sending next command. 1167 */ 1168 udelay(20); 1169 } 1170 1171 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1172 { 1173 int value; 1174 1175 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1176 1177 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1178 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1179 1180 /* 1181 * According to hardware specs a 20us delay is required after read 1182 * complete indication, but before sending next command. 1183 */ 1184 udelay(20); 1185 1186 return value; 1187 } 1188 1189 DECLARE_RTL_COND(rtl_ocpar_cond) 1190 { 1191 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1192 } 1193 1194 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1195 1196 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1197 { 1198 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1199 } 1200 1201 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1202 { 1203 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1204 } 1205 1206 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1207 { 1208 r8168dp_2_mdio_start(tp); 1209 1210 r8169_mdio_write(tp, reg, value); 1211 1212 r8168dp_2_mdio_stop(tp); 1213 } 1214 1215 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1216 { 1217 int value; 1218 1219 /* Work around issue with chip reporting wrong PHY ID */ 1220 if (reg == MII_PHYSID2) 1221 return 0xc912; 1222 1223 r8168dp_2_mdio_start(tp); 1224 1225 value = r8169_mdio_read(tp, reg); 1226 1227 r8168dp_2_mdio_stop(tp); 1228 1229 return value; 1230 } 1231 1232 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1233 { 1234 switch (tp->mac_version) { 1235 case RTL_GIGA_MAC_VER_28: 1236 case RTL_GIGA_MAC_VER_31: 1237 r8168dp_2_mdio_write(tp, location, val); 1238 break; 1239 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 1240 r8168g_mdio_write(tp, location, val); 1241 break; 1242 default: 1243 r8169_mdio_write(tp, location, val); 1244 break; 1245 } 1246 } 1247 1248 static int rtl_readphy(struct rtl8169_private *tp, int location) 1249 { 1250 switch (tp->mac_version) { 1251 case RTL_GIGA_MAC_VER_28: 1252 case RTL_GIGA_MAC_VER_31: 1253 return r8168dp_2_mdio_read(tp, location); 1254 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 1255 return r8168g_mdio_read(tp, location); 1256 default: 1257 return r8169_mdio_read(tp, location); 1258 } 1259 } 1260 1261 DECLARE_RTL_COND(rtl_ephyar_cond) 1262 { 1263 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1264 } 1265 1266 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1267 { 1268 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1269 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1270 1271 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1272 1273 udelay(10); 1274 } 1275 1276 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1277 { 1278 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1279 1280 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1281 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1282 } 1283 1284 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1285 { 1286 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1287 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1288 RTL_R32(tp, OCPDR) : ~0; 1289 } 1290 1291 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1292 { 1293 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1294 } 1295 1296 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1297 u32 data) 1298 { 1299 RTL_W32(tp, OCPDR, data); 1300 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1301 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1302 } 1303 1304 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1305 u32 data) 1306 { 1307 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1308 data, ERIAR_OOB); 1309 } 1310 1311 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1312 { 1313 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1314 1315 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1316 } 1317 1318 #define OOB_CMD_RESET 0x00 1319 #define OOB_CMD_DRIVER_START 0x05 1320 #define OOB_CMD_DRIVER_STOP 0x06 1321 1322 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1323 { 1324 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1325 } 1326 1327 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1328 { 1329 u16 reg; 1330 1331 reg = rtl8168_get_ocp_reg(tp); 1332 1333 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1334 } 1335 1336 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1337 { 1338 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1339 } 1340 1341 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1342 { 1343 return RTL_R8(tp, IBISR0) & 0x20; 1344 } 1345 1346 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1347 { 1348 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1349 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1350 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1351 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1352 } 1353 1354 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1355 { 1356 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1357 if (tp->dash_enabled) 1358 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1359 } 1360 1361 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1362 { 1363 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1364 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1365 if (tp->dash_enabled) 1366 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1367 } 1368 1369 static void rtl8125bp_driver_start(struct rtl8169_private *tp) 1370 { 1371 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_START); 1372 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); 1373 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); 1374 } 1375 1376 static void rtl8168_driver_start(struct rtl8169_private *tp) 1377 { 1378 if (tp->dash_type == RTL_DASH_DP) 1379 rtl8168dp_driver_start(tp); 1380 else if (tp->dash_type == RTL_DASH_25_BP) 1381 rtl8125bp_driver_start(tp); 1382 else 1383 rtl8168ep_driver_start(tp); 1384 } 1385 1386 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1387 { 1388 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1389 if (tp->dash_enabled) 1390 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1391 } 1392 1393 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1394 { 1395 rtl8168ep_stop_cmac(tp); 1396 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1397 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1398 if (tp->dash_enabled) 1399 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1400 } 1401 1402 static void rtl8125bp_driver_stop(struct rtl8169_private *tp) 1403 { 1404 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_STOP); 1405 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); 1406 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); 1407 } 1408 1409 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1410 { 1411 if (tp->dash_type == RTL_DASH_DP) 1412 rtl8168dp_driver_stop(tp); 1413 else if (tp->dash_type == RTL_DASH_25_BP) 1414 rtl8125bp_driver_stop(tp); 1415 else 1416 rtl8168ep_driver_stop(tp); 1417 } 1418 1419 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1420 { 1421 u16 reg = rtl8168_get_ocp_reg(tp); 1422 1423 return r8168dp_ocp_read(tp, reg) & BIT(15); 1424 } 1425 1426 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1427 { 1428 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1429 } 1430 1431 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1432 { 1433 switch (tp->dash_type) { 1434 case RTL_DASH_DP: 1435 return r8168dp_check_dash(tp); 1436 case RTL_DASH_EP: 1437 case RTL_DASH_25_BP: 1438 return r8168ep_check_dash(tp); 1439 default: 1440 return false; 1441 } 1442 } 1443 1444 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1445 { 1446 switch (tp->mac_version) { 1447 case RTL_GIGA_MAC_VER_28: 1448 case RTL_GIGA_MAC_VER_31: 1449 return RTL_DASH_DP; 1450 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1451 return RTL_DASH_EP; 1452 case RTL_GIGA_MAC_VER_66: 1453 return RTL_DASH_25_BP; 1454 default: 1455 return RTL_DASH_NONE; 1456 } 1457 } 1458 1459 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1460 { 1461 if (tp->mac_version >= RTL_GIGA_MAC_VER_25 && 1462 tp->mac_version != RTL_GIGA_MAC_VER_28 && 1463 tp->mac_version != RTL_GIGA_MAC_VER_31 && 1464 tp->mac_version != RTL_GIGA_MAC_VER_38) 1465 r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, !enable); 1466 } 1467 1468 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1469 { 1470 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1471 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1472 } 1473 1474 DECLARE_RTL_COND(rtl_efusear_cond) 1475 { 1476 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1477 } 1478 1479 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1480 { 1481 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1482 1483 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1484 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1485 } 1486 1487 static u32 rtl_get_events(struct rtl8169_private *tp) 1488 { 1489 if (rtl_is_8125(tp)) 1490 return RTL_R32(tp, IntrStatus_8125); 1491 else 1492 return RTL_R16(tp, IntrStatus); 1493 } 1494 1495 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1496 { 1497 if (rtl_is_8125(tp)) 1498 RTL_W32(tp, IntrStatus_8125, bits); 1499 else 1500 RTL_W16(tp, IntrStatus, bits); 1501 } 1502 1503 static void rtl_irq_disable(struct rtl8169_private *tp) 1504 { 1505 if (rtl_is_8125(tp)) 1506 RTL_W32(tp, IntrMask_8125, 0); 1507 else 1508 RTL_W16(tp, IntrMask, 0); 1509 } 1510 1511 static void rtl_irq_enable(struct rtl8169_private *tp) 1512 { 1513 if (rtl_is_8125(tp)) 1514 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1515 else 1516 RTL_W16(tp, IntrMask, tp->irq_mask); 1517 } 1518 1519 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1520 { 1521 rtl_irq_disable(tp); 1522 rtl_ack_events(tp, 0xffffffff); 1523 rtl_pci_commit(tp); 1524 } 1525 1526 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1527 { 1528 struct phy_device *phydev = tp->phydev; 1529 1530 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1531 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1532 if (phydev->speed == SPEED_1000) { 1533 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1534 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1535 } else if (phydev->speed == SPEED_100) { 1536 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1537 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1538 } else { 1539 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1540 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1541 } 1542 rtl_reset_packet_filter(tp); 1543 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1544 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1545 if (phydev->speed == SPEED_1000) { 1546 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1547 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1548 } else { 1549 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1550 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1551 } 1552 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1553 if (phydev->speed == SPEED_10) { 1554 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1555 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1556 } else { 1557 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1558 } 1559 } 1560 } 1561 1562 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1563 1564 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1565 { 1566 struct rtl8169_private *tp = netdev_priv(dev); 1567 1568 wol->supported = WAKE_ANY; 1569 wol->wolopts = tp->saved_wolopts; 1570 } 1571 1572 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1573 { 1574 rtl_unlock_config_regs(tp); 1575 1576 if (rtl_is_8168evl_up(tp)) { 1577 if (wolopts & WAKE_MAGIC) 1578 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1579 else 1580 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1581 } else if (rtl_is_8125(tp)) { 1582 if (wolopts & WAKE_MAGIC) 1583 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1584 else 1585 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1586 } else { 1587 r8169_mod_reg8_cond(tp, Config3, MagicPacket, 1588 wolopts & WAKE_MAGIC); 1589 } 1590 1591 r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY); 1592 if (rtl_is_8125(tp)) 1593 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, 1594 wolopts & WAKE_PHY ? 0x13 : 0); 1595 r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST); 1596 r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST); 1597 r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST); 1598 r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts); 1599 1600 switch (tp->mac_version) { 1601 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1602 r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts); 1603 break; 1604 case RTL_GIGA_MAC_VER_34: 1605 case RTL_GIGA_MAC_VER_37: 1606 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_71: 1607 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); 1608 break; 1609 default: 1610 break; 1611 } 1612 1613 rtl_lock_config_regs(tp); 1614 1615 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1616 1617 if (!tp->dash_enabled) { 1618 rtl_set_d3_pll_down(tp, !wolopts); 1619 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1620 } 1621 } 1622 1623 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1624 { 1625 struct rtl8169_private *tp = netdev_priv(dev); 1626 1627 if (wol->wolopts & ~WAKE_ANY) 1628 return -EINVAL; 1629 1630 tp->saved_wolopts = wol->wolopts; 1631 __rtl8169_set_wol(tp, tp->saved_wolopts); 1632 1633 return 0; 1634 } 1635 1636 static void rtl8169_get_drvinfo(struct net_device *dev, 1637 struct ethtool_drvinfo *info) 1638 { 1639 struct rtl8169_private *tp = netdev_priv(dev); 1640 struct rtl_fw *rtl_fw = tp->rtl_fw; 1641 1642 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1643 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1644 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1645 if (rtl_fw) 1646 strscpy(info->fw_version, rtl_fw->version, 1647 sizeof(info->fw_version)); 1648 } 1649 1650 static int rtl8169_get_regs_len(struct net_device *dev) 1651 { 1652 return R8169_REGS_SIZE; 1653 } 1654 1655 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1656 netdev_features_t features) 1657 { 1658 struct rtl8169_private *tp = netdev_priv(dev); 1659 1660 if (dev->mtu > TD_MSS_MAX) 1661 features &= ~NETIF_F_ALL_TSO; 1662 1663 if (dev->mtu > ETH_DATA_LEN && 1664 tp->mac_version > RTL_GIGA_MAC_VER_06) 1665 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1666 1667 return features; 1668 } 1669 1670 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1671 netdev_features_t features) 1672 { 1673 u32 rx_config = RTL_R32(tp, RxConfig); 1674 1675 if (features & NETIF_F_RXALL) 1676 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1677 else 1678 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1679 1680 if (rtl_is_8125(tp)) { 1681 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1682 rx_config |= RX_VLAN_8125; 1683 else 1684 rx_config &= ~RX_VLAN_8125; 1685 } 1686 1687 RTL_W32(tp, RxConfig, rx_config); 1688 } 1689 1690 static int rtl8169_set_features(struct net_device *dev, 1691 netdev_features_t features) 1692 { 1693 struct rtl8169_private *tp = netdev_priv(dev); 1694 1695 rtl_set_rx_config_features(tp, features); 1696 1697 if (features & NETIF_F_RXCSUM) 1698 tp->cp_cmd |= RxChkSum; 1699 else 1700 tp->cp_cmd &= ~RxChkSum; 1701 1702 if (!rtl_is_8125(tp)) { 1703 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1704 tp->cp_cmd |= RxVlan; 1705 else 1706 tp->cp_cmd &= ~RxVlan; 1707 } 1708 1709 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1710 rtl_pci_commit(tp); 1711 1712 return 0; 1713 } 1714 1715 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1716 { 1717 return (skb_vlan_tag_present(skb)) ? 1718 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1719 } 1720 1721 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1722 { 1723 u32 opts2 = le32_to_cpu(desc->opts2); 1724 1725 if (opts2 & RxVlanTag) 1726 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1727 } 1728 1729 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1730 void *p) 1731 { 1732 struct rtl8169_private *tp = netdev_priv(dev); 1733 u32 __iomem *data = tp->mmio_addr; 1734 u32 *dw = p; 1735 int i; 1736 1737 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1738 memcpy_fromio(dw++, data++, 4); 1739 } 1740 1741 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1742 "tx_packets", 1743 "rx_packets", 1744 "tx_errors", 1745 "rx_errors", 1746 "rx_missed", 1747 "align_errors", 1748 "tx_single_collisions", 1749 "tx_multi_collisions", 1750 "unicast", 1751 "broadcast", 1752 "multicast", 1753 "tx_aborted", 1754 "tx_underrun", 1755 }; 1756 1757 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1758 { 1759 switch (sset) { 1760 case ETH_SS_STATS: 1761 return ARRAY_SIZE(rtl8169_gstrings); 1762 default: 1763 return -EOPNOTSUPP; 1764 } 1765 } 1766 1767 DECLARE_RTL_COND(rtl_counters_cond) 1768 { 1769 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1770 } 1771 1772 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1773 { 1774 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1775 1776 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1777 rtl_pci_commit(tp); 1778 RTL_W32(tp, CounterAddrLow, cmd); 1779 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1780 1781 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1782 } 1783 1784 static void rtl8169_update_counters(struct rtl8169_private *tp) 1785 { 1786 u8 val = RTL_R8(tp, ChipCmd); 1787 1788 /* 1789 * Some chips are unable to dump tally counters when the receiver 1790 * is disabled. If 0xff chip may be in a PCI power-save state. 1791 */ 1792 if (val & CmdRxEnb && val != 0xff) 1793 rtl8169_do_counters(tp, CounterDump); 1794 } 1795 1796 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1797 { 1798 struct rtl8169_counters *counters = tp->counters; 1799 1800 /* 1801 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1802 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1803 * reset by a power cycle, while the counter values collected by the 1804 * driver are reset at every driver unload/load cycle. 1805 * 1806 * To make sure the HW values returned by @get_stats64 match the SW 1807 * values, we collect the initial values at first open(*) and use them 1808 * as offsets to normalize the values returned by @get_stats64. 1809 * 1810 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1811 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1812 * set at open time by rtl_hw_start. 1813 */ 1814 1815 if (tp->tc_offset.inited) 1816 return; 1817 1818 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1819 rtl8169_do_counters(tp, CounterReset); 1820 } else { 1821 rtl8169_update_counters(tp); 1822 tp->tc_offset.tx_errors = counters->tx_errors; 1823 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1824 tp->tc_offset.tx_aborted = counters->tx_aborted; 1825 tp->tc_offset.rx_missed = counters->rx_missed; 1826 } 1827 1828 tp->tc_offset.inited = true; 1829 } 1830 1831 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1832 struct ethtool_stats *stats, u64 *data) 1833 { 1834 struct rtl8169_private *tp = netdev_priv(dev); 1835 struct rtl8169_counters *counters; 1836 1837 counters = tp->counters; 1838 rtl8169_update_counters(tp); 1839 1840 data[0] = le64_to_cpu(counters->tx_packets); 1841 data[1] = le64_to_cpu(counters->rx_packets); 1842 data[2] = le64_to_cpu(counters->tx_errors); 1843 data[3] = le32_to_cpu(counters->rx_errors); 1844 data[4] = le16_to_cpu(counters->rx_missed); 1845 data[5] = le16_to_cpu(counters->align_errors); 1846 data[6] = le32_to_cpu(counters->tx_one_collision); 1847 data[7] = le32_to_cpu(counters->tx_multi_collision); 1848 data[8] = le64_to_cpu(counters->rx_unicast); 1849 data[9] = le64_to_cpu(counters->rx_broadcast); 1850 data[10] = le32_to_cpu(counters->rx_multicast); 1851 data[11] = le16_to_cpu(counters->tx_aborted); 1852 data[12] = le16_to_cpu(counters->tx_underrun); 1853 } 1854 1855 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1856 { 1857 switch(stringset) { 1858 case ETH_SS_STATS: 1859 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1860 break; 1861 } 1862 } 1863 1864 /* 1865 * Interrupt coalescing 1866 * 1867 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1868 * > 8169, 8168 and 810x line of chipsets 1869 * 1870 * 8169, 8168, and 8136(810x) serial chipsets support it. 1871 * 1872 * > 2 - the Tx timer unit at gigabit speed 1873 * 1874 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1875 * (0xe0) bit 1 and bit 0. 1876 * 1877 * For 8169 1878 * bit[1:0] \ speed 1000M 100M 10M 1879 * 0 0 320ns 2.56us 40.96us 1880 * 0 1 2.56us 20.48us 327.7us 1881 * 1 0 5.12us 40.96us 655.4us 1882 * 1 1 10.24us 81.92us 1.31ms 1883 * 1884 * For the other 1885 * bit[1:0] \ speed 1000M 100M 10M 1886 * 0 0 5us 2.56us 40.96us 1887 * 0 1 40us 20.48us 327.7us 1888 * 1 0 80us 40.96us 655.4us 1889 * 1 1 160us 81.92us 1.31ms 1890 */ 1891 1892 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1893 struct rtl_coalesce_info { 1894 u32 speed; 1895 u32 scale_nsecs[4]; 1896 }; 1897 1898 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1899 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1900 1901 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1902 { SPEED_1000, COALESCE_DELAY(320) }, 1903 { SPEED_100, COALESCE_DELAY(2560) }, 1904 { SPEED_10, COALESCE_DELAY(40960) }, 1905 { 0 }, 1906 }; 1907 1908 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1909 { SPEED_1000, COALESCE_DELAY(5000) }, 1910 { SPEED_100, COALESCE_DELAY(2560) }, 1911 { SPEED_10, COALESCE_DELAY(40960) }, 1912 { 0 }, 1913 }; 1914 #undef COALESCE_DELAY 1915 1916 /* get rx/tx scale vector corresponding to current speed */ 1917 static const struct rtl_coalesce_info * 1918 rtl_coalesce_info(struct rtl8169_private *tp) 1919 { 1920 const struct rtl_coalesce_info *ci; 1921 1922 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1923 ci = rtl_coalesce_info_8169; 1924 else 1925 ci = rtl_coalesce_info_8168_8136; 1926 1927 /* if speed is unknown assume highest one */ 1928 if (tp->phydev->speed == SPEED_UNKNOWN) 1929 return ci; 1930 1931 for (; ci->speed; ci++) { 1932 if (tp->phydev->speed == ci->speed) 1933 return ci; 1934 } 1935 1936 return ERR_PTR(-ELNRNG); 1937 } 1938 1939 static int rtl_get_coalesce(struct net_device *dev, 1940 struct ethtool_coalesce *ec, 1941 struct kernel_ethtool_coalesce *kernel_coal, 1942 struct netlink_ext_ack *extack) 1943 { 1944 struct rtl8169_private *tp = netdev_priv(dev); 1945 const struct rtl_coalesce_info *ci; 1946 u32 scale, c_us, c_fr; 1947 u16 intrmit; 1948 1949 if (rtl_is_8125(tp)) 1950 return -EOPNOTSUPP; 1951 1952 memset(ec, 0, sizeof(*ec)); 1953 1954 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1955 ci = rtl_coalesce_info(tp); 1956 if (IS_ERR(ci)) 1957 return PTR_ERR(ci); 1958 1959 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1960 1961 intrmit = RTL_R16(tp, IntrMitigate); 1962 1963 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1964 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1965 1966 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1967 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1968 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1969 1970 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1971 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1972 1973 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1974 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1975 1976 return 0; 1977 } 1978 1979 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1980 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1981 u16 *cp01) 1982 { 1983 const struct rtl_coalesce_info *ci; 1984 u16 i; 1985 1986 ci = rtl_coalesce_info(tp); 1987 if (IS_ERR(ci)) 1988 return PTR_ERR(ci); 1989 1990 for (i = 0; i < 4; i++) { 1991 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1992 *cp01 = i; 1993 return ci->scale_nsecs[i]; 1994 } 1995 } 1996 1997 return -ERANGE; 1998 } 1999 2000 static int rtl_set_coalesce(struct net_device *dev, 2001 struct ethtool_coalesce *ec, 2002 struct kernel_ethtool_coalesce *kernel_coal, 2003 struct netlink_ext_ack *extack) 2004 { 2005 struct rtl8169_private *tp = netdev_priv(dev); 2006 u32 tx_fr = ec->tx_max_coalesced_frames; 2007 u32 rx_fr = ec->rx_max_coalesced_frames; 2008 u32 coal_usec_max, units; 2009 u16 w = 0, cp01 = 0; 2010 int scale; 2011 2012 if (rtl_is_8125(tp)) 2013 return -EOPNOTSUPP; 2014 2015 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 2016 return -ERANGE; 2017 2018 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 2019 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 2020 if (scale < 0) 2021 return scale; 2022 2023 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 2024 * not only when usecs=0 because of e.g. the following scenario: 2025 * 2026 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2027 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2028 * - then user does `ethtool -C eth0 rx-usecs 100` 2029 * 2030 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2031 * if we want to ignore rx_frames then it has to be set to 0. 2032 */ 2033 if (rx_fr == 1) 2034 rx_fr = 0; 2035 if (tx_fr == 1) 2036 tx_fr = 0; 2037 2038 /* HW requires time limit to be set if frame limit is set */ 2039 if ((tx_fr && !ec->tx_coalesce_usecs) || 2040 (rx_fr && !ec->rx_coalesce_usecs)) 2041 return -EINVAL; 2042 2043 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2044 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2045 2046 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2047 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2048 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2049 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2050 2051 RTL_W16(tp, IntrMitigate, w); 2052 2053 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2054 if (rtl_is_8168evl_up(tp)) { 2055 if (!rx_fr && !tx_fr) 2056 /* disable packet counter */ 2057 tp->cp_cmd |= PktCntrDisable; 2058 else 2059 tp->cp_cmd &= ~PktCntrDisable; 2060 } 2061 2062 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2063 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2064 rtl_pci_commit(tp); 2065 2066 return 0; 2067 } 2068 2069 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2070 { 2071 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2072 2073 switch (tp->mac_version) { 2074 case RTL_GIGA_MAC_VER_46: 2075 case RTL_GIGA_MAC_VER_48: 2076 tp->tx_lpi_timer = timer_val; 2077 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2078 break; 2079 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 2080 tp->tx_lpi_timer = timer_val; 2081 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2082 break; 2083 default: 2084 break; 2085 } 2086 } 2087 2088 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2089 { 2090 unsigned int speed = tp->phydev->speed; 2091 unsigned int timer = tp->tx_lpi_timer; 2092 2093 if (!timer || speed == SPEED_UNKNOWN) 2094 return 0; 2095 2096 /* tx_lpi_timer value is in bytes */ 2097 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2098 } 2099 2100 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2101 { 2102 struct rtl8169_private *tp = netdev_priv(dev); 2103 int ret; 2104 2105 if (!rtl_supports_eee(tp)) 2106 return -EOPNOTSUPP; 2107 2108 ret = phy_ethtool_get_eee(tp->phydev, data); 2109 if (ret) 2110 return ret; 2111 2112 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2113 2114 return 0; 2115 } 2116 2117 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2118 { 2119 struct rtl8169_private *tp = netdev_priv(dev); 2120 2121 if (!rtl_supports_eee(tp)) 2122 return -EOPNOTSUPP; 2123 2124 return phy_ethtool_set_eee(tp->phydev, data); 2125 } 2126 2127 static void rtl8169_get_ringparam(struct net_device *dev, 2128 struct ethtool_ringparam *data, 2129 struct kernel_ethtool_ringparam *kernel_data, 2130 struct netlink_ext_ack *extack) 2131 { 2132 data->rx_max_pending = NUM_RX_DESC; 2133 data->rx_pending = NUM_RX_DESC; 2134 data->tx_max_pending = NUM_TX_DESC; 2135 data->tx_pending = NUM_TX_DESC; 2136 } 2137 2138 static void rtl8169_get_pause_stats(struct net_device *dev, 2139 struct ethtool_pause_stats *pause_stats) 2140 { 2141 struct rtl8169_private *tp = netdev_priv(dev); 2142 2143 if (!rtl_is_8125(tp)) 2144 return; 2145 2146 rtl8169_update_counters(tp); 2147 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on); 2148 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on); 2149 } 2150 2151 static void rtl8169_get_pauseparam(struct net_device *dev, 2152 struct ethtool_pauseparam *data) 2153 { 2154 struct rtl8169_private *tp = netdev_priv(dev); 2155 bool tx_pause, rx_pause; 2156 2157 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2158 2159 data->autoneg = tp->phydev->autoneg; 2160 data->tx_pause = tx_pause ? 1 : 0; 2161 data->rx_pause = rx_pause ? 1 : 0; 2162 } 2163 2164 static int rtl8169_set_pauseparam(struct net_device *dev, 2165 struct ethtool_pauseparam *data) 2166 { 2167 struct rtl8169_private *tp = netdev_priv(dev); 2168 2169 if (dev->mtu > ETH_DATA_LEN) 2170 return -EOPNOTSUPP; 2171 2172 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2173 2174 return 0; 2175 } 2176 2177 static void rtl8169_get_eth_mac_stats(struct net_device *dev, 2178 struct ethtool_eth_mac_stats *mac_stats) 2179 { 2180 struct rtl8169_private *tp = netdev_priv(dev); 2181 2182 rtl8169_update_counters(tp); 2183 2184 mac_stats->FramesTransmittedOK = 2185 le64_to_cpu(tp->counters->tx_packets); 2186 mac_stats->SingleCollisionFrames = 2187 le32_to_cpu(tp->counters->tx_one_collision); 2188 mac_stats->MultipleCollisionFrames = 2189 le32_to_cpu(tp->counters->tx_multi_collision); 2190 mac_stats->FramesReceivedOK = 2191 le64_to_cpu(tp->counters->rx_packets); 2192 mac_stats->AlignmentErrors = 2193 le16_to_cpu(tp->counters->align_errors); 2194 mac_stats->FramesLostDueToIntMACXmitError = 2195 le64_to_cpu(tp->counters->tx_errors); 2196 mac_stats->BroadcastFramesReceivedOK = 2197 le64_to_cpu(tp->counters->rx_broadcast); 2198 mac_stats->MulticastFramesReceivedOK = 2199 le32_to_cpu(tp->counters->rx_multicast); 2200 2201 if (!rtl_is_8125(tp)) 2202 return; 2203 2204 mac_stats->AlignmentErrors = 2205 le32_to_cpu(tp->counters->align_errors32); 2206 mac_stats->OctetsTransmittedOK = 2207 le64_to_cpu(tp->counters->tx_octets); 2208 mac_stats->LateCollisions = 2209 le32_to_cpu(tp->counters->tx_late_collision); 2210 mac_stats->FramesAbortedDueToXSColls = 2211 le32_to_cpu(tp->counters->tx_aborted32); 2212 mac_stats->OctetsReceivedOK = 2213 le64_to_cpu(tp->counters->rx_octets); 2214 mac_stats->FramesLostDueToIntMACRcvError = 2215 le32_to_cpu(tp->counters->rx_mac_error); 2216 mac_stats->MulticastFramesXmittedOK = 2217 le64_to_cpu(tp->counters->tx_multicast64); 2218 mac_stats->BroadcastFramesXmittedOK = 2219 le64_to_cpu(tp->counters->tx_broadcast64); 2220 mac_stats->MulticastFramesReceivedOK = 2221 le64_to_cpu(tp->counters->rx_multicast64); 2222 mac_stats->FrameTooLongErrors = 2223 le32_to_cpu(tp->counters->rx_frame_too_long); 2224 } 2225 2226 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, 2227 struct ethtool_eth_ctrl_stats *ctrl_stats) 2228 { 2229 struct rtl8169_private *tp = netdev_priv(dev); 2230 2231 if (!rtl_is_8125(tp)) 2232 return; 2233 2234 rtl8169_update_counters(tp); 2235 2236 ctrl_stats->UnsupportedOpcodesReceived = 2237 le32_to_cpu(tp->counters->rx_unknown_opcode); 2238 } 2239 2240 static const struct ethtool_ops rtl8169_ethtool_ops = { 2241 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2242 ETHTOOL_COALESCE_MAX_FRAMES, 2243 .get_drvinfo = rtl8169_get_drvinfo, 2244 .get_regs_len = rtl8169_get_regs_len, 2245 .get_link = ethtool_op_get_link, 2246 .get_coalesce = rtl_get_coalesce, 2247 .set_coalesce = rtl_set_coalesce, 2248 .get_regs = rtl8169_get_regs, 2249 .get_wol = rtl8169_get_wol, 2250 .set_wol = rtl8169_set_wol, 2251 .get_strings = rtl8169_get_strings, 2252 .get_sset_count = rtl8169_get_sset_count, 2253 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2254 .get_ts_info = ethtool_op_get_ts_info, 2255 .nway_reset = phy_ethtool_nway_reset, 2256 .get_eee = rtl8169_get_eee, 2257 .set_eee = rtl8169_set_eee, 2258 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2259 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2260 .get_ringparam = rtl8169_get_ringparam, 2261 .get_pause_stats = rtl8169_get_pause_stats, 2262 .get_pauseparam = rtl8169_get_pauseparam, 2263 .set_pauseparam = rtl8169_set_pauseparam, 2264 .get_eth_mac_stats = rtl8169_get_eth_mac_stats, 2265 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, 2266 }; 2267 2268 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2269 { 2270 /* 2271 * The driver currently handles the 8168Bf and the 8168Be identically 2272 * but they can be identified more specifically through the test below 2273 * if needed: 2274 * 2275 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2276 * 2277 * Same thing for the 8101Eb and the 8101Ec: 2278 * 2279 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2280 */ 2281 static const struct rtl_mac_info { 2282 u16 mask; 2283 u16 val; 2284 enum mac_version ver; 2285 } mac_info[] = { 2286 /* 8126A family. */ 2287 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_71 }, 2288 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70 }, 2289 2290 /* 8125BP family. */ 2291 { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66 }, 2292 2293 /* 8125D family. */ 2294 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_65 }, 2295 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, 2296 2297 /* 8125B family. */ 2298 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2299 2300 /* 8125A family. */ 2301 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2302 /* It seems only XID 609 made it to the mass market. 2303 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2304 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2305 */ 2306 2307 /* RTL8117 */ 2308 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2309 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2310 2311 /* 8168EP family. */ 2312 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2313 /* It seems this chip version never made it to 2314 * the wild. Let's disable detection. 2315 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2316 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2317 */ 2318 2319 /* 8168H family. */ 2320 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2321 /* It seems this chip version never made it to 2322 * the wild. Let's disable detection. 2323 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2324 */ 2325 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 2326 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, 2327 2328 /* 8168G family. */ 2329 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2330 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2331 /* It seems this chip version never made it to 2332 * the wild. Let's disable detection. 2333 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2334 */ 2335 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2336 2337 /* 8168F family. */ 2338 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2339 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2340 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2341 2342 /* 8168E family. */ 2343 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2344 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2345 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2346 2347 /* 8168D family. */ 2348 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2349 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2350 2351 /* 8168DP family. */ 2352 /* It seems this early RTL8168dp version never made it to 2353 * the wild. Support has been removed. 2354 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2355 */ 2356 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2357 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2358 2359 /* 8168C family. */ 2360 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2361 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2362 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2363 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2364 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2365 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2366 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2367 2368 /* 8168B family. */ 2369 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2370 /* This one is very old and rare, support has been removed. 2371 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2372 */ 2373 2374 /* 8101 family. */ 2375 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2376 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2377 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2378 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2379 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2380 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2381 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2382 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2383 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2384 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2385 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2386 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2387 2388 /* 8110 family. */ 2389 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2390 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2391 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2392 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2393 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2394 2395 /* Catch-all */ 2396 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2397 }; 2398 const struct rtl_mac_info *p = mac_info; 2399 enum mac_version ver; 2400 2401 while ((xid & p->mask) != p->val) 2402 p++; 2403 ver = p->ver; 2404 2405 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2406 if (ver == RTL_GIGA_MAC_VER_42) 2407 ver = RTL_GIGA_MAC_VER_43; 2408 else if (ver == RTL_GIGA_MAC_VER_46) 2409 ver = RTL_GIGA_MAC_VER_48; 2410 } 2411 2412 return ver; 2413 } 2414 2415 static void rtl_release_firmware(struct rtl8169_private *tp) 2416 { 2417 if (tp->rtl_fw) { 2418 rtl_fw_release_firmware(tp->rtl_fw); 2419 kfree(tp->rtl_fw); 2420 tp->rtl_fw = NULL; 2421 } 2422 } 2423 2424 void r8169_apply_firmware(struct rtl8169_private *tp) 2425 { 2426 int val; 2427 2428 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2429 if (tp->rtl_fw) { 2430 rtl_fw_write_firmware(tp, tp->rtl_fw); 2431 /* At least one firmware doesn't reset tp->ocp_base. */ 2432 tp->ocp_base = OCP_STD_PHY_BASE; 2433 2434 /* PHY soft reset may still be in progress */ 2435 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2436 !(val & BMCR_RESET), 2437 50000, 600000, true); 2438 } 2439 } 2440 2441 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2442 { 2443 /* Adjust EEE LED frequency */ 2444 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2445 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2446 2447 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2448 } 2449 2450 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2451 { 2452 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2453 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2454 } 2455 2456 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2457 { 2458 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2459 } 2460 2461 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2462 { 2463 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2464 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2465 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2466 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2467 } 2468 2469 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2470 { 2471 u16 data1, data2, ioffset; 2472 2473 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2474 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2475 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2476 2477 ioffset = (data2 >> 1) & 0x7ff8; 2478 ioffset |= data2 & 0x0007; 2479 if (data1 & BIT(7)) 2480 ioffset |= BIT(15); 2481 2482 return ioffset; 2483 } 2484 2485 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2486 { 2487 set_bit(flag, tp->wk.flags); 2488 if (!schedule_work(&tp->wk.work)) 2489 clear_bit(flag, tp->wk.flags); 2490 } 2491 2492 static void rtl8169_init_phy(struct rtl8169_private *tp) 2493 { 2494 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2495 2496 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2497 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2498 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2499 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2500 RTL_W8(tp, 0x82, 0x01); 2501 } 2502 2503 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2504 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2505 tp->pci_dev->subsystem_device == 0xe000) 2506 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2507 2508 /* We may have called phy_speed_down before */ 2509 phy_speed_up(tp->phydev); 2510 2511 genphy_soft_reset(tp->phydev); 2512 } 2513 2514 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2515 { 2516 rtl_unlock_config_regs(tp); 2517 2518 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2519 rtl_pci_commit(tp); 2520 2521 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2522 rtl_pci_commit(tp); 2523 2524 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2525 rtl_rar_exgmac_set(tp, addr); 2526 2527 rtl_lock_config_regs(tp); 2528 } 2529 2530 static int rtl_set_mac_address(struct net_device *dev, void *p) 2531 { 2532 struct rtl8169_private *tp = netdev_priv(dev); 2533 int ret; 2534 2535 ret = eth_mac_addr(dev, p); 2536 if (ret) 2537 return ret; 2538 2539 rtl_rar_set(tp, dev->dev_addr); 2540 2541 return 0; 2542 } 2543 2544 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2545 { 2546 switch (tp->mac_version) { 2547 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2548 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2549 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2550 break; 2551 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2552 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2553 case RTL_GIGA_MAC_VER_38: 2554 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2555 break; 2556 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2557 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2558 break; 2559 case RTL_GIGA_MAC_VER_61: 2560 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2561 break; 2562 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71: 2563 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2564 RX_PAUSE_SLOT_ON); 2565 break; 2566 default: 2567 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2568 break; 2569 } 2570 } 2571 2572 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2573 { 2574 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2575 } 2576 2577 static void rtl_jumbo_config(struct rtl8169_private *tp) 2578 { 2579 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2580 int readrq = 4096; 2581 2582 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 && 2583 tp->mac_version <= RTL_GIGA_MAC_VER_26) 2584 readrq = 512; 2585 2586 rtl_unlock_config_regs(tp); 2587 switch (tp->mac_version) { 2588 case RTL_GIGA_MAC_VER_17: 2589 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2590 break; 2591 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2592 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2593 r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo); 2594 break; 2595 case RTL_GIGA_MAC_VER_28: 2596 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2597 break; 2598 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2599 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); 2600 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2601 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2602 break; 2603 default: 2604 break; 2605 } 2606 rtl_lock_config_regs(tp); 2607 2608 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2609 pcie_set_readrq(tp->pci_dev, readrq); 2610 2611 /* Chip doesn't support pause in jumbo mode */ 2612 if (jumbo) { 2613 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2614 tp->phydev->advertising); 2615 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2616 tp->phydev->advertising); 2617 phy_start_aneg(tp->phydev); 2618 } 2619 } 2620 2621 DECLARE_RTL_COND(rtl_chipcmd_cond) 2622 { 2623 return RTL_R8(tp, ChipCmd) & CmdReset; 2624 } 2625 2626 static void rtl_hw_reset(struct rtl8169_private *tp) 2627 { 2628 RTL_W8(tp, ChipCmd, CmdReset); 2629 2630 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2631 } 2632 2633 static void rtl_request_firmware(struct rtl8169_private *tp) 2634 { 2635 struct rtl_fw *rtl_fw; 2636 2637 /* firmware loaded already or no firmware available */ 2638 if (tp->rtl_fw || !tp->fw_name) 2639 return; 2640 2641 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2642 if (!rtl_fw) 2643 return; 2644 2645 rtl_fw->phy_write = rtl_writephy; 2646 rtl_fw->phy_read = rtl_readphy; 2647 rtl_fw->mac_mcu_write = mac_mcu_write; 2648 rtl_fw->mac_mcu_read = mac_mcu_read; 2649 rtl_fw->fw_name = tp->fw_name; 2650 rtl_fw->dev = tp_to_dev(tp); 2651 2652 if (rtl_fw_request_firmware(rtl_fw)) 2653 kfree(rtl_fw); 2654 else 2655 tp->rtl_fw = rtl_fw; 2656 } 2657 2658 static void rtl_rx_close(struct rtl8169_private *tp) 2659 { 2660 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2661 } 2662 2663 DECLARE_RTL_COND(rtl_npq_cond) 2664 { 2665 return RTL_R8(tp, TxPoll) & NPQ; 2666 } 2667 2668 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2669 { 2670 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2671 } 2672 2673 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2674 { 2675 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2676 } 2677 2678 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2679 { 2680 /* IntrMitigate has new functionality on RTL8125 */ 2681 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2682 } 2683 2684 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2685 { 2686 switch (tp->mac_version) { 2687 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2688 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2689 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2690 break; 2691 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2692 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2693 break; 2694 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71: 2695 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2696 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2697 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2698 break; 2699 default: 2700 break; 2701 } 2702 } 2703 2704 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2705 { 2706 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2707 } 2708 2709 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2710 { 2711 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2712 fsleep(2000); 2713 rtl_wait_txrx_fifo_empty(tp); 2714 } 2715 2716 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2717 { 2718 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2719 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2720 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2721 2722 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2723 rtl_disable_rxdvgate(tp); 2724 } 2725 2726 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2727 { 2728 if (tp->dash_enabled) 2729 return; 2730 2731 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2732 tp->mac_version == RTL_GIGA_MAC_VER_33) 2733 rtl_ephy_write(tp, 0x19, 0xff64); 2734 2735 if (device_may_wakeup(tp_to_dev(tp))) { 2736 phy_speed_down(tp->phydev, false); 2737 rtl_wol_enable_rx(tp); 2738 } 2739 } 2740 2741 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2742 { 2743 u32 val = TX_DMA_BURST << TxDMAShift | 2744 InterFrameGap << TxInterFrameGapShift; 2745 2746 if (rtl_is_8168evl_up(tp)) 2747 val |= TXCFG_AUTO_FIFO; 2748 2749 RTL_W32(tp, TxConfig, val); 2750 } 2751 2752 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2753 { 2754 /* Low hurts. Let's disable the filtering. */ 2755 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2756 } 2757 2758 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2759 { 2760 /* 2761 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2762 * register to be written before TxDescAddrLow to work. 2763 * Switching from MMIO to I/O access fixes the issue as well. 2764 */ 2765 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2766 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2767 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2768 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2769 } 2770 2771 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2772 { 2773 u32 val; 2774 2775 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2776 val = 0x000fff00; 2777 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2778 val = 0x00ffff00; 2779 else 2780 return; 2781 2782 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2783 val |= 0xff; 2784 2785 RTL_W32(tp, 0x7c, val); 2786 } 2787 2788 static void rtl_set_rx_mode(struct net_device *dev) 2789 { 2790 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2791 /* Multicast hash filter */ 2792 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2793 struct rtl8169_private *tp = netdev_priv(dev); 2794 u32 tmp; 2795 2796 if (dev->flags & IFF_PROMISC) { 2797 rx_mode |= AcceptAllPhys; 2798 } else if (!(dev->flags & IFF_MULTICAST)) { 2799 rx_mode &= ~AcceptMulticast; 2800 } else if (dev->flags & IFF_ALLMULTI || 2801 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2802 /* accept all multicasts */ 2803 } else if (netdev_mc_empty(dev)) { 2804 rx_mode &= ~AcceptMulticast; 2805 } else { 2806 struct netdev_hw_addr *ha; 2807 2808 mc_filter[1] = mc_filter[0] = 0; 2809 netdev_for_each_mc_addr(ha, dev) { 2810 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2811 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2812 } 2813 2814 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2815 tmp = mc_filter[0]; 2816 mc_filter[0] = swab32(mc_filter[1]); 2817 mc_filter[1] = swab32(tmp); 2818 } 2819 } 2820 2821 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2822 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2823 2824 tmp = RTL_R32(tp, RxConfig); 2825 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2826 } 2827 2828 DECLARE_RTL_COND(rtl_csiar_cond) 2829 { 2830 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2831 } 2832 2833 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2834 { 2835 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2836 2837 RTL_W32(tp, CSIDR, value); 2838 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2839 CSIAR_BYTE_ENABLE | func << 16); 2840 2841 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2842 } 2843 2844 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2845 { 2846 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2847 2848 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2849 CSIAR_BYTE_ENABLE); 2850 2851 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2852 RTL_R32(tp, CSIDR) : ~0; 2853 } 2854 2855 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2856 { 2857 struct pci_dev *pdev = tp->pci_dev; 2858 u32 csi; 2859 2860 /* According to Realtek the value at config space address 0x070f 2861 * controls the L0s/L1 entrance latency. We try standard ECAM access 2862 * first and if it fails fall back to CSI. 2863 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2864 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2865 */ 2866 if (pdev->cfg_size > 0x070f && 2867 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2868 return; 2869 2870 netdev_notice_once(tp->dev, 2871 "No native access to PCI extended config space, falling back to CSI\n"); 2872 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2873 rtl_csi_write(tp, 0x070c, csi | val << 24); 2874 } 2875 2876 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2877 { 2878 /* L0 7us, L1 16us */ 2879 rtl_set_aspm_entry_latency(tp, 0x27); 2880 } 2881 2882 struct ephy_info { 2883 unsigned int offset; 2884 u16 mask; 2885 u16 bits; 2886 }; 2887 2888 static void __rtl_ephy_init(struct rtl8169_private *tp, 2889 const struct ephy_info *e, int len) 2890 { 2891 u16 w; 2892 2893 while (len-- > 0) { 2894 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2895 rtl_ephy_write(tp, e->offset, w); 2896 e++; 2897 } 2898 } 2899 2900 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2901 2902 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2903 { 2904 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2905 PCI_EXP_LNKCTL_CLKREQ_EN); 2906 } 2907 2908 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2909 { 2910 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2911 PCI_EXP_LNKCTL_CLKREQ_EN); 2912 } 2913 2914 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2915 { 2916 /* work around an issue when PCI reset occurs during L2/L3 state */ 2917 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2918 } 2919 2920 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2921 { 2922 /* Bits control which events trigger ASPM L1 exit: 2923 * Bit 12: rxdv 2924 * Bit 11: ltr_msg 2925 * Bit 10: txdma_poll 2926 * Bit 9: xadm 2927 * Bit 8: pktavi 2928 * Bit 7: txpla 2929 */ 2930 switch (tp->mac_version) { 2931 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2932 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2933 break; 2934 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2935 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2936 break; 2937 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 2938 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2939 break; 2940 default: 2941 break; 2942 } 2943 } 2944 2945 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2946 { 2947 switch (tp->mac_version) { 2948 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2949 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2950 break; 2951 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 2952 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2953 break; 2954 default: 2955 break; 2956 } 2957 } 2958 2959 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2960 { 2961 u8 val8; 2962 2963 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2964 return; 2965 2966 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2967 if (enable && tp->aspm_manageable) { 2968 /* On these chip versions ASPM can even harm 2969 * bus communication of other PCI devices. 2970 */ 2971 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2972 tp->mac_version == RTL_GIGA_MAC_VER_43) 2973 return; 2974 2975 rtl_mod_config5(tp, 0, ASPM_en); 2976 switch (tp->mac_version) { 2977 case RTL_GIGA_MAC_VER_70: 2978 case RTL_GIGA_MAC_VER_71: 2979 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2980 RTL_W8(tp, INT_CFG0_8125, val8); 2981 break; 2982 default: 2983 rtl_mod_config2(tp, 0, ClkReqEn); 2984 break; 2985 } 2986 2987 switch (tp->mac_version) { 2988 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2989 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 2990 /* reset ephy tx/rx disable timer */ 2991 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2992 /* chip can trigger L1.2 */ 2993 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2994 break; 2995 default: 2996 break; 2997 } 2998 } else { 2999 switch (tp->mac_version) { 3000 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 3001 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 3002 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 3003 break; 3004 default: 3005 break; 3006 } 3007 3008 switch (tp->mac_version) { 3009 case RTL_GIGA_MAC_VER_70: 3010 case RTL_GIGA_MAC_VER_71: 3011 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 3012 RTL_W8(tp, INT_CFG0_8125, val8); 3013 break; 3014 default: 3015 rtl_mod_config2(tp, ClkReqEn, 0); 3016 break; 3017 } 3018 rtl_mod_config5(tp, ASPM_en, 0); 3019 } 3020 } 3021 3022 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 3023 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 3024 { 3025 /* Usage of dynamic vs. static FIFO is controlled by bit 3026 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 3027 */ 3028 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 3029 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 3030 } 3031 3032 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3033 u8 low, u8 high) 3034 { 3035 /* FIFO thresholds for pause flow control */ 3036 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3037 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3038 } 3039 3040 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3041 { 3042 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3043 } 3044 3045 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3046 { 3047 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3048 3049 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3050 3051 rtl_disable_clock_request(tp); 3052 } 3053 3054 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3055 { 3056 static const struct ephy_info e_info_8168cp[] = { 3057 { 0x01, 0, 0x0001 }, 3058 { 0x02, 0x0800, 0x1000 }, 3059 { 0x03, 0, 0x0042 }, 3060 { 0x06, 0x0080, 0x0000 }, 3061 { 0x07, 0, 0x2000 } 3062 }; 3063 3064 rtl_set_def_aspm_entry_latency(tp); 3065 3066 rtl_ephy_init(tp, e_info_8168cp); 3067 3068 __rtl_hw_start_8168cp(tp); 3069 } 3070 3071 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3072 { 3073 rtl_set_def_aspm_entry_latency(tp); 3074 3075 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3076 } 3077 3078 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3079 { 3080 rtl_set_def_aspm_entry_latency(tp); 3081 3082 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3083 3084 /* Magic. */ 3085 RTL_W8(tp, DBG_REG, 0x20); 3086 } 3087 3088 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3089 { 3090 static const struct ephy_info e_info_8168c_1[] = { 3091 { 0x02, 0x0800, 0x1000 }, 3092 { 0x03, 0, 0x0002 }, 3093 { 0x06, 0x0080, 0x0000 } 3094 }; 3095 3096 rtl_set_def_aspm_entry_latency(tp); 3097 3098 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3099 3100 rtl_ephy_init(tp, e_info_8168c_1); 3101 3102 __rtl_hw_start_8168cp(tp); 3103 } 3104 3105 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3106 { 3107 static const struct ephy_info e_info_8168c_2[] = { 3108 { 0x01, 0, 0x0001 }, 3109 { 0x03, 0x0400, 0x0020 } 3110 }; 3111 3112 rtl_set_def_aspm_entry_latency(tp); 3113 3114 rtl_ephy_init(tp, e_info_8168c_2); 3115 3116 __rtl_hw_start_8168cp(tp); 3117 } 3118 3119 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3120 { 3121 rtl_set_def_aspm_entry_latency(tp); 3122 3123 __rtl_hw_start_8168cp(tp); 3124 } 3125 3126 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3127 { 3128 rtl_set_def_aspm_entry_latency(tp); 3129 3130 rtl_disable_clock_request(tp); 3131 } 3132 3133 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3134 { 3135 static const struct ephy_info e_info_8168d_4[] = { 3136 { 0x0b, 0x0000, 0x0048 }, 3137 { 0x19, 0x0020, 0x0050 }, 3138 { 0x0c, 0x0100, 0x0020 }, 3139 { 0x10, 0x0004, 0x0000 }, 3140 }; 3141 3142 rtl_set_def_aspm_entry_latency(tp); 3143 3144 rtl_ephy_init(tp, e_info_8168d_4); 3145 3146 rtl_enable_clock_request(tp); 3147 } 3148 3149 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3150 { 3151 static const struct ephy_info e_info_8168e_1[] = { 3152 { 0x00, 0x0200, 0x0100 }, 3153 { 0x00, 0x0000, 0x0004 }, 3154 { 0x06, 0x0002, 0x0001 }, 3155 { 0x06, 0x0000, 0x0030 }, 3156 { 0x07, 0x0000, 0x2000 }, 3157 { 0x00, 0x0000, 0x0020 }, 3158 { 0x03, 0x5800, 0x2000 }, 3159 { 0x03, 0x0000, 0x0001 }, 3160 { 0x01, 0x0800, 0x1000 }, 3161 { 0x07, 0x0000, 0x4000 }, 3162 { 0x1e, 0x0000, 0x2000 }, 3163 { 0x19, 0xffff, 0xfe6c }, 3164 { 0x0a, 0x0000, 0x0040 } 3165 }; 3166 3167 rtl_set_def_aspm_entry_latency(tp); 3168 3169 rtl_ephy_init(tp, e_info_8168e_1); 3170 3171 rtl_disable_clock_request(tp); 3172 3173 /* Reset tx FIFO pointer */ 3174 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3175 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3176 3177 rtl_mod_config5(tp, Spi_en, 0); 3178 } 3179 3180 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3181 { 3182 static const struct ephy_info e_info_8168e_2[] = { 3183 { 0x09, 0x0000, 0x0080 }, 3184 { 0x19, 0x0000, 0x0224 }, 3185 { 0x00, 0x0000, 0x0004 }, 3186 { 0x0c, 0x3df0, 0x0200 }, 3187 }; 3188 3189 rtl_set_def_aspm_entry_latency(tp); 3190 3191 rtl_ephy_init(tp, e_info_8168e_2); 3192 3193 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3194 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3195 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3196 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3197 rtl_reset_packet_filter(tp); 3198 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3199 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3200 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3201 3202 rtl_disable_clock_request(tp); 3203 3204 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3205 3206 rtl8168_config_eee_mac(tp); 3207 3208 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3209 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3210 rtl_mod_config5(tp, Spi_en, 0); 3211 } 3212 3213 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3214 { 3215 rtl_set_def_aspm_entry_latency(tp); 3216 3217 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3218 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3219 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3220 rtl_reset_packet_filter(tp); 3221 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3222 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3223 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3224 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3225 3226 rtl_disable_clock_request(tp); 3227 3228 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3229 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3230 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3231 rtl_mod_config5(tp, Spi_en, 0); 3232 3233 rtl8168_config_eee_mac(tp); 3234 } 3235 3236 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3237 { 3238 static const struct ephy_info e_info_8168f_1[] = { 3239 { 0x06, 0x00c0, 0x0020 }, 3240 { 0x08, 0x0001, 0x0002 }, 3241 { 0x09, 0x0000, 0x0080 }, 3242 { 0x19, 0x0000, 0x0224 }, 3243 { 0x00, 0x0000, 0x0008 }, 3244 { 0x0c, 0x3df0, 0x0200 }, 3245 }; 3246 3247 rtl_hw_start_8168f(tp); 3248 3249 rtl_ephy_init(tp, e_info_8168f_1); 3250 } 3251 3252 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3253 { 3254 static const struct ephy_info e_info_8168f_1[] = { 3255 { 0x06, 0x00c0, 0x0020 }, 3256 { 0x0f, 0xffff, 0x5200 }, 3257 { 0x19, 0x0000, 0x0224 }, 3258 { 0x00, 0x0000, 0x0008 }, 3259 { 0x0c, 0x3df0, 0x0200 }, 3260 }; 3261 3262 rtl_hw_start_8168f(tp); 3263 rtl_pcie_state_l2l3_disable(tp); 3264 3265 rtl_ephy_init(tp, e_info_8168f_1); 3266 } 3267 3268 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3269 { 3270 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3271 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3272 3273 rtl_set_def_aspm_entry_latency(tp); 3274 3275 rtl_reset_packet_filter(tp); 3276 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3277 3278 rtl_disable_rxdvgate(tp); 3279 3280 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3281 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3282 3283 rtl8168_config_eee_mac(tp); 3284 3285 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3286 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3287 3288 rtl_pcie_state_l2l3_disable(tp); 3289 } 3290 3291 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3292 { 3293 static const struct ephy_info e_info_8168g_1[] = { 3294 { 0x00, 0x0008, 0x0000 }, 3295 { 0x0c, 0x3ff0, 0x0820 }, 3296 { 0x1e, 0x0000, 0x0001 }, 3297 { 0x19, 0x8000, 0x0000 } 3298 }; 3299 3300 rtl_hw_start_8168g(tp); 3301 rtl_ephy_init(tp, e_info_8168g_1); 3302 } 3303 3304 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3305 { 3306 static const struct ephy_info e_info_8168g_2[] = { 3307 { 0x00, 0x0008, 0x0000 }, 3308 { 0x0c, 0x3ff0, 0x0820 }, 3309 { 0x19, 0xffff, 0x7c00 }, 3310 { 0x1e, 0xffff, 0x20eb }, 3311 { 0x0d, 0xffff, 0x1666 }, 3312 { 0x00, 0xffff, 0x10a3 }, 3313 { 0x06, 0xffff, 0xf050 }, 3314 { 0x04, 0x0000, 0x0010 }, 3315 { 0x1d, 0x4000, 0x0000 }, 3316 }; 3317 3318 rtl_hw_start_8168g(tp); 3319 rtl_ephy_init(tp, e_info_8168g_2); 3320 } 3321 3322 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3323 { 3324 static const u16 fix_data[] = { 3325 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3326 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3327 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3328 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3329 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3330 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3331 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3332 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3333 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3334 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3335 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3336 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3337 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3338 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3339 }; 3340 unsigned long flags; 3341 int i; 3342 3343 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3344 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3345 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3346 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3347 } 3348 3349 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3350 { 3351 static const struct ephy_info e_info_8411_2[] = { 3352 { 0x00, 0x0008, 0x0000 }, 3353 { 0x0c, 0x37d0, 0x0820 }, 3354 { 0x1e, 0x0000, 0x0001 }, 3355 { 0x19, 0x8021, 0x0000 }, 3356 { 0x1e, 0x0000, 0x2000 }, 3357 { 0x0d, 0x0100, 0x0200 }, 3358 { 0x00, 0x0000, 0x0080 }, 3359 { 0x06, 0x0000, 0x0010 }, 3360 { 0x04, 0x0000, 0x0010 }, 3361 { 0x1d, 0x0000, 0x4000 }, 3362 }; 3363 3364 rtl_hw_start_8168g(tp); 3365 3366 rtl_ephy_init(tp, e_info_8411_2); 3367 3368 /* The following Realtek-provided magic fixes an issue with the RX unit 3369 * getting confused after the PHY having been powered-down. 3370 */ 3371 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3372 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3373 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3374 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3375 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3376 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3377 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3378 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3379 mdelay(3); 3380 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3381 3382 rtl8411b_fix_phy_down(tp); 3383 3384 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3385 3386 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3387 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3388 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3389 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3390 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3391 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3392 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3393 } 3394 3395 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3396 { 3397 static const struct ephy_info e_info_8168h_1[] = { 3398 { 0x1e, 0x0800, 0x0001 }, 3399 { 0x1d, 0x0000, 0x0800 }, 3400 { 0x05, 0xffff, 0x2089 }, 3401 { 0x06, 0xffff, 0x5881 }, 3402 { 0x04, 0xffff, 0x854a }, 3403 { 0x01, 0xffff, 0x068b } 3404 }; 3405 int rg_saw_cnt; 3406 3407 rtl_ephy_init(tp, e_info_8168h_1); 3408 3409 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3410 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3411 3412 rtl_set_def_aspm_entry_latency(tp); 3413 3414 rtl_reset_packet_filter(tp); 3415 3416 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3417 3418 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3419 3420 rtl_disable_rxdvgate(tp); 3421 3422 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3423 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3424 3425 rtl8168_config_eee_mac(tp); 3426 3427 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3428 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3429 3430 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3431 3432 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3433 3434 rtl_pcie_state_l2l3_disable(tp); 3435 3436 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3437 if (rg_saw_cnt > 0) { 3438 u16 sw_cnt_1ms_ini; 3439 3440 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3441 sw_cnt_1ms_ini &= 0x0fff; 3442 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3443 } 3444 3445 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3446 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3447 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3448 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3449 3450 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3451 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3452 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3453 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3454 } 3455 3456 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3457 { 3458 rtl8168ep_stop_cmac(tp); 3459 3460 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3461 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3462 3463 rtl_set_def_aspm_entry_latency(tp); 3464 3465 rtl_reset_packet_filter(tp); 3466 3467 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3468 3469 rtl_disable_rxdvgate(tp); 3470 3471 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3472 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3473 3474 rtl8168_config_eee_mac(tp); 3475 3476 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3477 3478 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3479 3480 rtl_pcie_state_l2l3_disable(tp); 3481 } 3482 3483 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3484 { 3485 static const struct ephy_info e_info_8168ep_3[] = { 3486 { 0x00, 0x0000, 0x0080 }, 3487 { 0x0d, 0x0100, 0x0200 }, 3488 { 0x19, 0x8021, 0x0000 }, 3489 { 0x1e, 0x0000, 0x2000 }, 3490 }; 3491 3492 rtl_ephy_init(tp, e_info_8168ep_3); 3493 3494 rtl_hw_start_8168ep(tp); 3495 3496 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3497 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3498 3499 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3500 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3501 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3502 } 3503 3504 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3505 { 3506 static const struct ephy_info e_info_8117[] = { 3507 { 0x19, 0x0040, 0x1100 }, 3508 { 0x59, 0x0040, 0x1100 }, 3509 }; 3510 int rg_saw_cnt; 3511 3512 rtl8168ep_stop_cmac(tp); 3513 rtl_ephy_init(tp, e_info_8117); 3514 3515 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3516 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3517 3518 rtl_set_def_aspm_entry_latency(tp); 3519 3520 rtl_reset_packet_filter(tp); 3521 3522 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3523 3524 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3525 3526 rtl_disable_rxdvgate(tp); 3527 3528 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3529 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3530 3531 rtl8168_config_eee_mac(tp); 3532 3533 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3534 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3535 3536 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3537 3538 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3539 3540 rtl_pcie_state_l2l3_disable(tp); 3541 3542 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3543 if (rg_saw_cnt > 0) { 3544 u16 sw_cnt_1ms_ini; 3545 3546 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3547 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3548 } 3549 3550 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3551 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3552 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3553 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3554 3555 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3556 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3557 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3558 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3559 3560 /* firmware is for MAC only */ 3561 r8169_apply_firmware(tp); 3562 } 3563 3564 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3565 { 3566 static const struct ephy_info e_info_8102e_1[] = { 3567 { 0x01, 0, 0x6e65 }, 3568 { 0x02, 0, 0x091f }, 3569 { 0x03, 0, 0xc2f9 }, 3570 { 0x06, 0, 0xafb5 }, 3571 { 0x07, 0, 0x0e00 }, 3572 { 0x19, 0, 0xec80 }, 3573 { 0x01, 0, 0x2e65 }, 3574 { 0x01, 0, 0x6e65 } 3575 }; 3576 u8 cfg1; 3577 3578 rtl_set_def_aspm_entry_latency(tp); 3579 3580 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3581 3582 RTL_W8(tp, Config1, 3583 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3584 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3585 3586 cfg1 = RTL_R8(tp, Config1); 3587 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3588 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3589 3590 rtl_ephy_init(tp, e_info_8102e_1); 3591 } 3592 3593 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3594 { 3595 rtl_set_def_aspm_entry_latency(tp); 3596 3597 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3598 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3599 } 3600 3601 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3602 { 3603 rtl_hw_start_8102e_2(tp); 3604 3605 rtl_ephy_write(tp, 0x03, 0xc2f9); 3606 } 3607 3608 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3609 { 3610 static const struct ephy_info e_info_8401[] = { 3611 { 0x01, 0xffff, 0x6fe5 }, 3612 { 0x03, 0xffff, 0x0599 }, 3613 { 0x06, 0xffff, 0xaf25 }, 3614 { 0x07, 0xffff, 0x8e68 }, 3615 }; 3616 3617 rtl_ephy_init(tp, e_info_8401); 3618 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3619 } 3620 3621 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3622 { 3623 static const struct ephy_info e_info_8105e_1[] = { 3624 { 0x07, 0, 0x4000 }, 3625 { 0x19, 0, 0x0200 }, 3626 { 0x19, 0, 0x0020 }, 3627 { 0x1e, 0, 0x2000 }, 3628 { 0x03, 0, 0x0001 }, 3629 { 0x19, 0, 0x0100 }, 3630 { 0x19, 0, 0x0004 }, 3631 { 0x0a, 0, 0x0020 } 3632 }; 3633 3634 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3635 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3636 3637 /* Disable Early Tally Counter */ 3638 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3639 3640 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3641 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3642 3643 rtl_ephy_init(tp, e_info_8105e_1); 3644 3645 rtl_pcie_state_l2l3_disable(tp); 3646 } 3647 3648 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3649 { 3650 rtl_hw_start_8105e_1(tp); 3651 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3652 } 3653 3654 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3655 { 3656 static const struct ephy_info e_info_8402[] = { 3657 { 0x19, 0xffff, 0xff64 }, 3658 { 0x1e, 0, 0x4000 } 3659 }; 3660 3661 rtl_set_def_aspm_entry_latency(tp); 3662 3663 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3664 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3665 3666 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3667 3668 rtl_ephy_init(tp, e_info_8402); 3669 3670 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3671 rtl_reset_packet_filter(tp); 3672 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3673 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3674 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3675 3676 /* disable EEE */ 3677 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3678 3679 rtl_pcie_state_l2l3_disable(tp); 3680 } 3681 3682 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3683 { 3684 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3685 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3686 3687 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3688 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3689 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3690 3691 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3692 rtl_set_aspm_entry_latency(tp, 0x2f); 3693 3694 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3695 3696 /* disable EEE */ 3697 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3698 3699 rtl_pcie_state_l2l3_disable(tp); 3700 } 3701 3702 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3703 { 3704 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3705 } 3706 3707 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3708 { 3709 rtl_pcie_state_l2l3_disable(tp); 3710 3711 RTL_W16(tp, 0x382, 0x221b); 3712 RTL_W32(tp, RSS_CTRL_8125, 0); 3713 RTL_W16(tp, Q_NUM_CTRL_8125, 0); 3714 3715 /* disable UPS */ 3716 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3717 3718 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3719 3720 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3721 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3722 3723 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3724 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3725 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3726 3727 /* disable new tx descriptor format */ 3728 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3729 3730 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3731 tp->mac_version == RTL_GIGA_MAC_VER_71) 3732 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3733 3734 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3735 tp->mac_version == RTL_GIGA_MAC_VER_71) 3736 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3737 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3738 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3739 else 3740 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3741 3742 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3743 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3744 else 3745 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3746 3747 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3748 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3749 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3750 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3751 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3752 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3753 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3754 tp->mac_version == RTL_GIGA_MAC_VER_71) 3755 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3756 else 3757 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3758 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3759 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3760 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3761 3762 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3763 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3764 udelay(1); 3765 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3766 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3767 3768 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3769 3770 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3771 3772 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3773 rtl8125a_config_eee_mac(tp); 3774 else 3775 rtl8125b_config_eee_mac(tp); 3776 3777 rtl_disable_rxdvgate(tp); 3778 } 3779 3780 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3781 { 3782 static const struct ephy_info e_info_8125a_2[] = { 3783 { 0x04, 0xffff, 0xd000 }, 3784 { 0x0a, 0xffff, 0x8653 }, 3785 { 0x23, 0xffff, 0xab66 }, 3786 { 0x20, 0xffff, 0x9455 }, 3787 { 0x21, 0xffff, 0x99ff }, 3788 { 0x29, 0xffff, 0xfe04 }, 3789 3790 { 0x44, 0xffff, 0xd000 }, 3791 { 0x4a, 0xffff, 0x8653 }, 3792 { 0x63, 0xffff, 0xab66 }, 3793 { 0x60, 0xffff, 0x9455 }, 3794 { 0x61, 0xffff, 0x99ff }, 3795 { 0x69, 0xffff, 0xfe04 }, 3796 }; 3797 3798 rtl_set_def_aspm_entry_latency(tp); 3799 rtl_ephy_init(tp, e_info_8125a_2); 3800 rtl_hw_start_8125_common(tp); 3801 } 3802 3803 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3804 { 3805 static const struct ephy_info e_info_8125b[] = { 3806 { 0x0b, 0xffff, 0xa908 }, 3807 { 0x1e, 0xffff, 0x20eb }, 3808 { 0x4b, 0xffff, 0xa908 }, 3809 { 0x5e, 0xffff, 0x20eb }, 3810 { 0x22, 0x0030, 0x0020 }, 3811 { 0x62, 0x0030, 0x0020 }, 3812 }; 3813 3814 rtl_set_def_aspm_entry_latency(tp); 3815 rtl_ephy_init(tp, e_info_8125b); 3816 rtl_hw_start_8125_common(tp); 3817 } 3818 3819 static void rtl_hw_start_8125d(struct rtl8169_private *tp) 3820 { 3821 rtl_set_def_aspm_entry_latency(tp); 3822 rtl_hw_start_8125_common(tp); 3823 } 3824 3825 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3826 { 3827 rtl_set_def_aspm_entry_latency(tp); 3828 rtl_hw_start_8125_common(tp); 3829 } 3830 3831 static void rtl_hw_config(struct rtl8169_private *tp) 3832 { 3833 static const rtl_generic_fct hw_configs[] = { 3834 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3835 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3836 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3837 [RTL_GIGA_MAC_VER_10] = NULL, 3838 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3839 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3840 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3841 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3842 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3843 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3844 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3845 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3846 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3847 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3848 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3849 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3850 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3851 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3852 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3853 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3854 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3855 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3856 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3857 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3858 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3859 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3860 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3861 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3862 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3863 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3864 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3865 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3866 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3867 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3868 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3869 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3870 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3871 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3872 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, 3873 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d, 3874 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, 3875 [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, 3876 [RTL_GIGA_MAC_VER_71] = rtl_hw_start_8126a, 3877 }; 3878 3879 if (hw_configs[tp->mac_version]) 3880 hw_configs[tp->mac_version](tp); 3881 } 3882 3883 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3884 { 3885 int i; 3886 3887 RTL_W8(tp, INT_CFG0_8125, 0x00); 3888 3889 /* disable interrupt coalescing */ 3890 switch (tp->mac_version) { 3891 case RTL_GIGA_MAC_VER_61: 3892 case RTL_GIGA_MAC_VER_64: 3893 case RTL_GIGA_MAC_VER_65: 3894 case RTL_GIGA_MAC_VER_66: 3895 for (i = 0xa00; i < 0xb00; i += 4) 3896 RTL_W32(tp, i, 0); 3897 break; 3898 case RTL_GIGA_MAC_VER_63: 3899 case RTL_GIGA_MAC_VER_70: 3900 case RTL_GIGA_MAC_VER_71: 3901 for (i = 0xa00; i < 0xa80; i += 4) 3902 RTL_W32(tp, i, 0); 3903 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3904 break; 3905 default: 3906 break; 3907 } 3908 3909 /* enable extended tally counter */ 3910 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); 3911 3912 rtl_hw_config(tp); 3913 } 3914 3915 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3916 { 3917 if (rtl_is_8168evl_up(tp)) 3918 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3919 else 3920 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3921 3922 rtl_hw_config(tp); 3923 3924 /* disable interrupt coalescing */ 3925 RTL_W16(tp, IntrMitigate, 0x0000); 3926 } 3927 3928 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3929 { 3930 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3931 3932 tp->cp_cmd |= PCIMulRW; 3933 3934 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3935 tp->mac_version == RTL_GIGA_MAC_VER_03) 3936 tp->cp_cmd |= EnAnaPLL; 3937 3938 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3939 3940 rtl8169_set_magic_reg(tp); 3941 3942 /* disable interrupt coalescing */ 3943 RTL_W16(tp, IntrMitigate, 0x0000); 3944 } 3945 3946 static void rtl_hw_start(struct rtl8169_private *tp) 3947 { 3948 rtl_unlock_config_regs(tp); 3949 /* disable aspm and clock request before ephy access */ 3950 rtl_hw_aspm_clkreq_enable(tp, false); 3951 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3952 3953 rtl_set_eee_txidle_timer(tp); 3954 3955 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3956 rtl_hw_start_8169(tp); 3957 else if (rtl_is_8125(tp)) 3958 rtl_hw_start_8125(tp); 3959 else 3960 rtl_hw_start_8168(tp); 3961 3962 rtl_enable_exit_l1(tp); 3963 rtl_hw_aspm_clkreq_enable(tp, true); 3964 rtl_set_rx_max_size(tp); 3965 rtl_set_rx_tx_desc_registers(tp); 3966 rtl_lock_config_regs(tp); 3967 3968 rtl_jumbo_config(tp); 3969 3970 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3971 rtl_pci_commit(tp); 3972 3973 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3974 rtl_init_rxcfg(tp); 3975 rtl_set_tx_config_registers(tp); 3976 rtl_set_rx_config_features(tp, tp->dev->features); 3977 rtl_set_rx_mode(tp->dev); 3978 rtl_irq_enable(tp); 3979 } 3980 3981 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3982 { 3983 struct rtl8169_private *tp = netdev_priv(dev); 3984 3985 WRITE_ONCE(dev->mtu, new_mtu); 3986 netdev_update_features(dev); 3987 rtl_jumbo_config(tp); 3988 rtl_set_eee_txidle_timer(tp); 3989 3990 return 0; 3991 } 3992 3993 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3994 { 3995 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3996 3997 desc->opts2 = 0; 3998 /* Force memory writes to complete before releasing descriptor */ 3999 dma_wmb(); 4000 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 4001 } 4002 4003 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 4004 struct RxDesc *desc) 4005 { 4006 struct device *d = tp_to_dev(tp); 4007 int node = dev_to_node(d); 4008 dma_addr_t mapping; 4009 struct page *data; 4010 4011 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 4012 if (!data) 4013 return NULL; 4014 4015 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4016 if (unlikely(dma_mapping_error(d, mapping))) { 4017 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 4018 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 4019 return NULL; 4020 } 4021 4022 desc->addr = cpu_to_le64(mapping); 4023 rtl8169_mark_to_asic(desc); 4024 4025 return data; 4026 } 4027 4028 static void rtl8169_rx_clear(struct rtl8169_private *tp) 4029 { 4030 int i; 4031 4032 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 4033 dma_unmap_page(tp_to_dev(tp), 4034 le64_to_cpu(tp->RxDescArray[i].addr), 4035 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4036 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4037 tp->Rx_databuff[i] = NULL; 4038 tp->RxDescArray[i].addr = 0; 4039 tp->RxDescArray[i].opts1 = 0; 4040 } 4041 } 4042 4043 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4044 { 4045 int i; 4046 4047 for (i = 0; i < NUM_RX_DESC; i++) { 4048 struct page *data; 4049 4050 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4051 if (!data) { 4052 rtl8169_rx_clear(tp); 4053 return -ENOMEM; 4054 } 4055 tp->Rx_databuff[i] = data; 4056 } 4057 4058 /* mark as last descriptor in the ring */ 4059 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4060 4061 return 0; 4062 } 4063 4064 static int rtl8169_init_ring(struct rtl8169_private *tp) 4065 { 4066 rtl8169_init_ring_indexes(tp); 4067 4068 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4069 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4070 4071 return rtl8169_rx_fill(tp); 4072 } 4073 4074 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4075 { 4076 struct ring_info *tx_skb = tp->tx_skb + entry; 4077 struct TxDesc *desc = tp->TxDescArray + entry; 4078 4079 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4080 DMA_TO_DEVICE); 4081 memset(desc, 0, sizeof(*desc)); 4082 memset(tx_skb, 0, sizeof(*tx_skb)); 4083 } 4084 4085 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4086 unsigned int n) 4087 { 4088 unsigned int i; 4089 4090 for (i = 0; i < n; i++) { 4091 unsigned int entry = (start + i) % NUM_TX_DESC; 4092 struct ring_info *tx_skb = tp->tx_skb + entry; 4093 unsigned int len = tx_skb->len; 4094 4095 if (len) { 4096 struct sk_buff *skb = tx_skb->skb; 4097 4098 rtl8169_unmap_tx_skb(tp, entry); 4099 if (skb) 4100 dev_consume_skb_any(skb); 4101 } 4102 } 4103 } 4104 4105 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4106 { 4107 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4108 netdev_reset_queue(tp->dev); 4109 } 4110 4111 static void rtl8169_cleanup(struct rtl8169_private *tp) 4112 { 4113 napi_disable(&tp->napi); 4114 4115 /* Give a racing hard_start_xmit a few cycles to complete. */ 4116 synchronize_net(); 4117 4118 /* Disable interrupts */ 4119 rtl8169_irq_mask_and_ack(tp); 4120 4121 rtl_rx_close(tp); 4122 4123 switch (tp->mac_version) { 4124 case RTL_GIGA_MAC_VER_28: 4125 case RTL_GIGA_MAC_VER_31: 4126 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4127 break; 4128 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4129 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4130 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4131 break; 4132 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 4133 rtl_enable_rxdvgate(tp); 4134 fsleep(2000); 4135 break; 4136 default: 4137 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4138 fsleep(100); 4139 break; 4140 } 4141 4142 rtl_hw_reset(tp); 4143 4144 rtl8169_tx_clear(tp); 4145 rtl8169_init_ring_indexes(tp); 4146 } 4147 4148 static void rtl_reset_work(struct rtl8169_private *tp) 4149 { 4150 int i; 4151 4152 netif_stop_queue(tp->dev); 4153 4154 rtl8169_cleanup(tp); 4155 4156 for (i = 0; i < NUM_RX_DESC; i++) 4157 rtl8169_mark_to_asic(tp->RxDescArray + i); 4158 4159 napi_enable(&tp->napi); 4160 rtl_hw_start(tp); 4161 } 4162 4163 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4164 { 4165 struct rtl8169_private *tp = netdev_priv(dev); 4166 4167 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4168 } 4169 4170 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4171 void *addr, unsigned int entry, bool desc_own) 4172 { 4173 struct TxDesc *txd = tp->TxDescArray + entry; 4174 struct device *d = tp_to_dev(tp); 4175 dma_addr_t mapping; 4176 u32 opts1; 4177 int ret; 4178 4179 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4180 ret = dma_mapping_error(d, mapping); 4181 if (unlikely(ret)) { 4182 if (net_ratelimit()) 4183 netdev_err(tp->dev, "Failed to map TX data!\n"); 4184 return ret; 4185 } 4186 4187 txd->addr = cpu_to_le64(mapping); 4188 txd->opts2 = cpu_to_le32(opts[1]); 4189 4190 opts1 = opts[0] | len; 4191 if (entry == NUM_TX_DESC - 1) 4192 opts1 |= RingEnd; 4193 if (desc_own) 4194 opts1 |= DescOwn; 4195 txd->opts1 = cpu_to_le32(opts1); 4196 4197 tp->tx_skb[entry].len = len; 4198 4199 return 0; 4200 } 4201 4202 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4203 const u32 *opts, unsigned int entry) 4204 { 4205 struct skb_shared_info *info = skb_shinfo(skb); 4206 unsigned int cur_frag; 4207 4208 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4209 const skb_frag_t *frag = info->frags + cur_frag; 4210 void *addr = skb_frag_address(frag); 4211 u32 len = skb_frag_size(frag); 4212 4213 entry = (entry + 1) % NUM_TX_DESC; 4214 4215 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4216 goto err_out; 4217 } 4218 4219 return 0; 4220 4221 err_out: 4222 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4223 return -EIO; 4224 } 4225 4226 static bool rtl_skb_is_udp(struct sk_buff *skb) 4227 { 4228 int no = skb_network_offset(skb); 4229 struct ipv6hdr *i6h, _i6h; 4230 struct iphdr *ih, _ih; 4231 4232 switch (vlan_get_protocol(skb)) { 4233 case htons(ETH_P_IP): 4234 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4235 return ih && ih->protocol == IPPROTO_UDP; 4236 case htons(ETH_P_IPV6): 4237 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4238 return i6h && i6h->nexthdr == IPPROTO_UDP; 4239 default: 4240 return false; 4241 } 4242 } 4243 4244 #define RTL_MIN_PATCH_LEN 47 4245 4246 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4247 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4248 struct sk_buff *skb) 4249 { 4250 unsigned int padto = 0, len = skb->len; 4251 4252 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) && 4253 skb_transport_header_was_set(skb)) { 4254 unsigned int trans_data_len = skb_tail_pointer(skb) - 4255 skb_transport_header(skb); 4256 4257 if (trans_data_len >= offsetof(struct udphdr, len) && 4258 trans_data_len < RTL_MIN_PATCH_LEN) { 4259 u16 dest = ntohs(udp_hdr(skb)->dest); 4260 4261 /* dest is a standard PTP port */ 4262 if (dest == 319 || dest == 320) 4263 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4264 } 4265 4266 if (trans_data_len < sizeof(struct udphdr)) 4267 padto = max_t(unsigned int, padto, 4268 len + sizeof(struct udphdr) - trans_data_len); 4269 } 4270 4271 return padto; 4272 } 4273 4274 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4275 struct sk_buff *skb) 4276 { 4277 unsigned int padto = 0; 4278 4279 switch (tp->mac_version) { 4280 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 4281 padto = rtl8125_quirk_udp_padto(tp, skb); 4282 break; 4283 default: 4284 break; 4285 } 4286 4287 switch (tp->mac_version) { 4288 case RTL_GIGA_MAC_VER_34: 4289 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 4290 padto = max_t(unsigned int, padto, ETH_ZLEN); 4291 break; 4292 default: 4293 break; 4294 } 4295 4296 return padto; 4297 } 4298 4299 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4300 { 4301 u32 mss = skb_shinfo(skb)->gso_size; 4302 4303 if (mss) { 4304 opts[0] |= TD_LSO; 4305 opts[0] |= mss << TD0_MSS_SHIFT; 4306 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4307 const struct iphdr *ip = ip_hdr(skb); 4308 4309 if (ip->protocol == IPPROTO_TCP) 4310 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4311 else if (ip->protocol == IPPROTO_UDP) 4312 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4313 else 4314 WARN_ON_ONCE(1); 4315 } 4316 } 4317 4318 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4319 struct sk_buff *skb, u32 *opts) 4320 { 4321 struct skb_shared_info *shinfo = skb_shinfo(skb); 4322 u32 mss = shinfo->gso_size; 4323 4324 if (mss) { 4325 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4326 opts[0] |= TD1_GTSENV4; 4327 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4328 if (skb_cow_head(skb, 0)) 4329 return false; 4330 4331 tcp_v6_gso_csum_prep(skb); 4332 opts[0] |= TD1_GTSENV6; 4333 } else { 4334 WARN_ON_ONCE(1); 4335 } 4336 4337 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4338 opts[1] |= mss << TD1_MSS_SHIFT; 4339 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4340 u8 ip_protocol; 4341 4342 switch (vlan_get_protocol(skb)) { 4343 case htons(ETH_P_IP): 4344 opts[1] |= TD1_IPv4_CS; 4345 ip_protocol = ip_hdr(skb)->protocol; 4346 break; 4347 4348 case htons(ETH_P_IPV6): 4349 opts[1] |= TD1_IPv6_CS; 4350 ip_protocol = ipv6_hdr(skb)->nexthdr; 4351 break; 4352 4353 default: 4354 ip_protocol = IPPROTO_RAW; 4355 break; 4356 } 4357 4358 if (ip_protocol == IPPROTO_TCP) 4359 opts[1] |= TD1_TCP_CS; 4360 else if (ip_protocol == IPPROTO_UDP) 4361 opts[1] |= TD1_UDP_CS; 4362 else 4363 WARN_ON_ONCE(1); 4364 4365 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4366 } else { 4367 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4368 4369 /* skb_padto would free the skb on error */ 4370 return !__skb_put_padto(skb, padto, false); 4371 } 4372 4373 return true; 4374 } 4375 4376 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4377 { 4378 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4379 } 4380 4381 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4382 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4383 { 4384 switch (tp->mac_version) { 4385 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4386 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4387 return false; 4388 default: 4389 return true; 4390 } 4391 } 4392 4393 static void rtl8169_doorbell(struct rtl8169_private *tp) 4394 { 4395 if (rtl_is_8125(tp)) 4396 RTL_W16(tp, TxPoll_8125, BIT(0)); 4397 else 4398 RTL_W8(tp, TxPoll, NPQ); 4399 } 4400 4401 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4402 struct net_device *dev) 4403 { 4404 struct rtl8169_private *tp = netdev_priv(dev); 4405 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4406 struct TxDesc *txd_first, *txd_last; 4407 bool stop_queue, door_bell; 4408 unsigned int frags; 4409 u32 opts[2]; 4410 4411 if (unlikely(!rtl_tx_slots_avail(tp))) { 4412 if (net_ratelimit()) 4413 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4414 netif_stop_queue(dev); 4415 return NETDEV_TX_BUSY; 4416 } 4417 4418 opts[1] = rtl8169_tx_vlan_tag(skb); 4419 opts[0] = 0; 4420 4421 if (!rtl_chip_supports_csum_v2(tp)) 4422 rtl8169_tso_csum_v1(skb, opts); 4423 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4424 goto err_dma_0; 4425 4426 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4427 entry, false))) 4428 goto err_dma_0; 4429 4430 txd_first = tp->TxDescArray + entry; 4431 4432 frags = skb_shinfo(skb)->nr_frags; 4433 if (frags) { 4434 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4435 goto err_dma_1; 4436 entry = (entry + frags) % NUM_TX_DESC; 4437 } 4438 4439 txd_last = tp->TxDescArray + entry; 4440 txd_last->opts1 |= cpu_to_le32(LastFrag); 4441 tp->tx_skb[entry].skb = skb; 4442 4443 skb_tx_timestamp(skb); 4444 4445 /* Force memory writes to complete before releasing descriptor */ 4446 dma_wmb(); 4447 4448 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4449 4450 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4451 4452 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4453 smp_wmb(); 4454 4455 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4456 4457 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4458 R8169_TX_STOP_THRS, 4459 R8169_TX_START_THRS); 4460 if (door_bell || stop_queue) 4461 rtl8169_doorbell(tp); 4462 4463 return NETDEV_TX_OK; 4464 4465 err_dma_1: 4466 rtl8169_unmap_tx_skb(tp, entry); 4467 err_dma_0: 4468 dev_kfree_skb_any(skb); 4469 dev->stats.tx_dropped++; 4470 return NETDEV_TX_OK; 4471 } 4472 4473 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4474 { 4475 struct skb_shared_info *info = skb_shinfo(skb); 4476 unsigned int nr_frags = info->nr_frags; 4477 4478 if (!nr_frags) 4479 return UINT_MAX; 4480 4481 return skb_frag_size(info->frags + nr_frags - 1); 4482 } 4483 4484 /* Workaround for hw issues with TSO on RTL8168evl */ 4485 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4486 netdev_features_t features) 4487 { 4488 /* IPv4 header has options field */ 4489 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4490 ip_hdrlen(skb) > sizeof(struct iphdr)) 4491 features &= ~NETIF_F_ALL_TSO; 4492 4493 /* IPv4 TCP header has options field */ 4494 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4495 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4496 features &= ~NETIF_F_ALL_TSO; 4497 4498 else if (rtl_last_frag_len(skb) <= 6) 4499 features &= ~NETIF_F_ALL_TSO; 4500 4501 return features; 4502 } 4503 4504 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4505 struct net_device *dev, 4506 netdev_features_t features) 4507 { 4508 struct rtl8169_private *tp = netdev_priv(dev); 4509 4510 if (skb_is_gso(skb)) { 4511 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4512 features = rtl8168evl_fix_tso(skb, features); 4513 4514 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4515 rtl_chip_supports_csum_v2(tp)) 4516 features &= ~NETIF_F_ALL_TSO; 4517 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4518 /* work around hw bug on some chip versions */ 4519 if (skb->len < ETH_ZLEN) 4520 features &= ~NETIF_F_CSUM_MASK; 4521 4522 if (rtl_quirk_packet_padto(tp, skb)) 4523 features &= ~NETIF_F_CSUM_MASK; 4524 4525 if (skb_transport_offset(skb) > TCPHO_MAX && 4526 rtl_chip_supports_csum_v2(tp)) 4527 features &= ~NETIF_F_CSUM_MASK; 4528 } 4529 4530 return vlan_features_check(skb, features); 4531 } 4532 4533 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4534 { 4535 struct rtl8169_private *tp = netdev_priv(dev); 4536 struct pci_dev *pdev = tp->pci_dev; 4537 int pci_status_errs; 4538 u16 pci_cmd; 4539 4540 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4541 4542 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4543 4544 if (net_ratelimit()) 4545 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4546 pci_cmd, pci_status_errs); 4547 4548 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4549 } 4550 4551 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4552 int budget) 4553 { 4554 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4555 struct sk_buff *skb; 4556 4557 dirty_tx = tp->dirty_tx; 4558 4559 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4560 unsigned int entry = dirty_tx % NUM_TX_DESC; 4561 u32 status; 4562 4563 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4564 if (status & DescOwn) 4565 break; 4566 4567 skb = tp->tx_skb[entry].skb; 4568 rtl8169_unmap_tx_skb(tp, entry); 4569 4570 if (skb) { 4571 pkts_compl++; 4572 bytes_compl += skb->len; 4573 napi_consume_skb(skb, budget); 4574 } 4575 dirty_tx++; 4576 } 4577 4578 if (tp->dirty_tx != dirty_tx) { 4579 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4580 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4581 4582 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4583 rtl_tx_slots_avail(tp), 4584 R8169_TX_START_THRS); 4585 /* 4586 * 8168 hack: TxPoll requests are lost when the Tx packets are 4587 * too close. Let's kick an extra TxPoll request when a burst 4588 * of start_xmit activity is detected (if it is not detected, 4589 * it is slow enough). -- FR 4590 * If skb is NULL then we come here again once a tx irq is 4591 * triggered after the last fragment is marked transmitted. 4592 */ 4593 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4594 rtl8169_doorbell(tp); 4595 } 4596 } 4597 4598 static inline int rtl8169_fragmented_frame(u32 status) 4599 { 4600 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4601 } 4602 4603 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4604 { 4605 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4606 4607 if (status == RxProtoTCP || status == RxProtoUDP) 4608 skb->ip_summed = CHECKSUM_UNNECESSARY; 4609 else 4610 skb_checksum_none_assert(skb); 4611 } 4612 4613 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4614 { 4615 struct device *d = tp_to_dev(tp); 4616 int count; 4617 4618 for (count = 0; count < budget; count++, tp->cur_rx++) { 4619 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4620 struct RxDesc *desc = tp->RxDescArray + entry; 4621 struct sk_buff *skb; 4622 const void *rx_buf; 4623 dma_addr_t addr; 4624 u32 status; 4625 4626 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4627 if (status & DescOwn) 4628 break; 4629 4630 /* This barrier is needed to keep us from reading 4631 * any other fields out of the Rx descriptor until 4632 * we know the status of DescOwn 4633 */ 4634 dma_rmb(); 4635 4636 if (unlikely(status & RxRES)) { 4637 if (net_ratelimit()) 4638 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4639 status); 4640 dev->stats.rx_errors++; 4641 if (status & (RxRWT | RxRUNT)) 4642 dev->stats.rx_length_errors++; 4643 if (status & RxCRC) 4644 dev->stats.rx_crc_errors++; 4645 4646 if (!(dev->features & NETIF_F_RXALL)) 4647 goto release_descriptor; 4648 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4649 goto release_descriptor; 4650 } 4651 4652 pkt_size = status & GENMASK(13, 0); 4653 if (likely(!(dev->features & NETIF_F_RXFCS))) 4654 pkt_size -= ETH_FCS_LEN; 4655 4656 /* The driver does not support incoming fragmented frames. 4657 * They are seen as a symptom of over-mtu sized frames. 4658 */ 4659 if (unlikely(rtl8169_fragmented_frame(status))) { 4660 dev->stats.rx_dropped++; 4661 dev->stats.rx_length_errors++; 4662 goto release_descriptor; 4663 } 4664 4665 skb = napi_alloc_skb(&tp->napi, pkt_size); 4666 if (unlikely(!skb)) { 4667 dev->stats.rx_dropped++; 4668 goto release_descriptor; 4669 } 4670 4671 addr = le64_to_cpu(desc->addr); 4672 rx_buf = page_address(tp->Rx_databuff[entry]); 4673 4674 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4675 prefetch(rx_buf); 4676 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4677 skb->tail += pkt_size; 4678 skb->len = pkt_size; 4679 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4680 4681 rtl8169_rx_csum(skb, status); 4682 skb->protocol = eth_type_trans(skb, dev); 4683 4684 rtl8169_rx_vlan_tag(desc, skb); 4685 4686 if (skb->pkt_type == PACKET_MULTICAST) 4687 dev->stats.multicast++; 4688 4689 napi_gro_receive(&tp->napi, skb); 4690 4691 dev_sw_netstats_rx_add(dev, pkt_size); 4692 release_descriptor: 4693 rtl8169_mark_to_asic(desc); 4694 } 4695 4696 return count; 4697 } 4698 4699 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4700 { 4701 struct rtl8169_private *tp = dev_instance; 4702 u32 status = rtl_get_events(tp); 4703 4704 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4705 return IRQ_NONE; 4706 4707 /* At least RTL8168fp may unexpectedly set the SYSErr bit */ 4708 if (unlikely(status & SYSErr && 4709 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { 4710 rtl8169_pcierr_interrupt(tp->dev); 4711 goto out; 4712 } 4713 4714 if (status & LinkChg) 4715 phy_mac_interrupt(tp->phydev); 4716 4717 rtl_irq_disable(tp); 4718 napi_schedule(&tp->napi); 4719 out: 4720 rtl_ack_events(tp, status); 4721 4722 return IRQ_HANDLED; 4723 } 4724 4725 static void rtl_task(struct work_struct *work) 4726 { 4727 struct rtl8169_private *tp = 4728 container_of(work, struct rtl8169_private, wk.work); 4729 int ret; 4730 4731 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4732 /* if chip isn't accessible, reset bus to revive it */ 4733 if (RTL_R32(tp, TxConfig) == ~0) { 4734 ret = pci_reset_bus(tp->pci_dev); 4735 if (ret < 0) { 4736 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4737 netif_device_detach(tp->dev); 4738 return; 4739 } 4740 } 4741 4742 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4743 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4744 PCIE_LINK_STATE_L0S); 4745 if (!ret) 4746 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4747 goto reset; 4748 } 4749 4750 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4751 reset: 4752 rtl_reset_work(tp); 4753 netif_wake_queue(tp->dev); 4754 } 4755 } 4756 4757 static int rtl8169_poll(struct napi_struct *napi, int budget) 4758 { 4759 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4760 struct net_device *dev = tp->dev; 4761 int work_done; 4762 4763 rtl_tx(dev, tp, budget); 4764 4765 work_done = rtl_rx(dev, tp, budget); 4766 4767 if (work_done < budget && napi_complete_done(napi, work_done)) 4768 rtl_irq_enable(tp); 4769 4770 return work_done; 4771 } 4772 4773 static void r8169_phylink_handler(struct net_device *ndev) 4774 { 4775 struct rtl8169_private *tp = netdev_priv(ndev); 4776 struct device *d = tp_to_dev(tp); 4777 4778 if (netif_carrier_ok(ndev)) { 4779 rtl_link_chg_patch(tp); 4780 pm_request_resume(d); 4781 } else { 4782 pm_runtime_idle(d); 4783 } 4784 4785 phy_print_status(tp->phydev); 4786 } 4787 4788 static int r8169_phy_connect(struct rtl8169_private *tp) 4789 { 4790 struct phy_device *phydev = tp->phydev; 4791 phy_interface_t phy_mode; 4792 int ret; 4793 4794 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4795 PHY_INTERFACE_MODE_MII; 4796 4797 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4798 phy_mode); 4799 if (ret) 4800 return ret; 4801 4802 if (!tp->supports_gmii) 4803 phy_set_max_speed(phydev, SPEED_100); 4804 4805 phy_attached_info(phydev); 4806 4807 return 0; 4808 } 4809 4810 static void rtl8169_down(struct rtl8169_private *tp) 4811 { 4812 disable_work_sync(&tp->wk.work); 4813 /* Clear all task flags */ 4814 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4815 4816 phy_stop(tp->phydev); 4817 4818 rtl8169_update_counters(tp); 4819 4820 pci_clear_master(tp->pci_dev); 4821 rtl_pci_commit(tp); 4822 4823 rtl8169_cleanup(tp); 4824 rtl_disable_exit_l1(tp); 4825 rtl_prepare_power_down(tp); 4826 4827 if (tp->dash_type != RTL_DASH_NONE) 4828 rtl8168_driver_stop(tp); 4829 } 4830 4831 static void rtl8169_up(struct rtl8169_private *tp) 4832 { 4833 if (tp->dash_type != RTL_DASH_NONE) 4834 rtl8168_driver_start(tp); 4835 4836 pci_set_master(tp->pci_dev); 4837 phy_init_hw(tp->phydev); 4838 phy_resume(tp->phydev); 4839 rtl8169_init_phy(tp); 4840 napi_enable(&tp->napi); 4841 enable_work(&tp->wk.work); 4842 rtl_reset_work(tp); 4843 4844 phy_start(tp->phydev); 4845 } 4846 4847 static int rtl8169_close(struct net_device *dev) 4848 { 4849 struct rtl8169_private *tp = netdev_priv(dev); 4850 struct pci_dev *pdev = tp->pci_dev; 4851 4852 pm_runtime_get_sync(&pdev->dev); 4853 4854 netif_stop_queue(dev); 4855 rtl8169_down(tp); 4856 rtl8169_rx_clear(tp); 4857 4858 free_irq(tp->irq, tp); 4859 4860 phy_disconnect(tp->phydev); 4861 4862 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4863 tp->RxPhyAddr); 4864 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4865 tp->TxPhyAddr); 4866 tp->TxDescArray = NULL; 4867 tp->RxDescArray = NULL; 4868 4869 pm_runtime_put_sync(&pdev->dev); 4870 4871 return 0; 4872 } 4873 4874 #ifdef CONFIG_NET_POLL_CONTROLLER 4875 static void rtl8169_netpoll(struct net_device *dev) 4876 { 4877 struct rtl8169_private *tp = netdev_priv(dev); 4878 4879 rtl8169_interrupt(tp->irq, tp); 4880 } 4881 #endif 4882 4883 static int rtl_open(struct net_device *dev) 4884 { 4885 struct rtl8169_private *tp = netdev_priv(dev); 4886 struct pci_dev *pdev = tp->pci_dev; 4887 unsigned long irqflags; 4888 int retval = -ENOMEM; 4889 4890 pm_runtime_get_sync(&pdev->dev); 4891 4892 /* 4893 * Rx and Tx descriptors needs 256 bytes alignment. 4894 * dma_alloc_coherent provides more. 4895 */ 4896 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4897 &tp->TxPhyAddr, GFP_KERNEL); 4898 if (!tp->TxDescArray) 4899 goto out; 4900 4901 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4902 &tp->RxPhyAddr, GFP_KERNEL); 4903 if (!tp->RxDescArray) 4904 goto err_free_tx_0; 4905 4906 retval = rtl8169_init_ring(tp); 4907 if (retval < 0) 4908 goto err_free_rx_1; 4909 4910 rtl_request_firmware(tp); 4911 4912 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4913 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4914 if (retval < 0) 4915 goto err_release_fw_2; 4916 4917 retval = r8169_phy_connect(tp); 4918 if (retval) 4919 goto err_free_irq; 4920 4921 rtl8169_up(tp); 4922 rtl8169_init_counter_offsets(tp); 4923 netif_start_queue(dev); 4924 out: 4925 pm_runtime_put_sync(&pdev->dev); 4926 4927 return retval; 4928 4929 err_free_irq: 4930 free_irq(tp->irq, tp); 4931 err_release_fw_2: 4932 rtl_release_firmware(tp); 4933 rtl8169_rx_clear(tp); 4934 err_free_rx_1: 4935 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4936 tp->RxPhyAddr); 4937 tp->RxDescArray = NULL; 4938 err_free_tx_0: 4939 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4940 tp->TxPhyAddr); 4941 tp->TxDescArray = NULL; 4942 goto out; 4943 } 4944 4945 static void 4946 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4947 { 4948 struct rtl8169_private *tp = netdev_priv(dev); 4949 struct pci_dev *pdev = tp->pci_dev; 4950 struct rtl8169_counters *counters = tp->counters; 4951 4952 pm_runtime_get_noresume(&pdev->dev); 4953 4954 netdev_stats_to_stats64(stats, &dev->stats); 4955 dev_fetch_sw_netstats(stats, dev->tstats); 4956 4957 /* 4958 * Fetch additional counter values missing in stats collected by driver 4959 * from tally counters. 4960 */ 4961 if (pm_runtime_active(&pdev->dev)) 4962 rtl8169_update_counters(tp); 4963 4964 /* 4965 * Subtract values fetched during initalization. 4966 * See rtl8169_init_counter_offsets for a description why we do that. 4967 */ 4968 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4969 le64_to_cpu(tp->tc_offset.tx_errors); 4970 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4971 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4972 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4973 le16_to_cpu(tp->tc_offset.tx_aborted); 4974 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4975 le16_to_cpu(tp->tc_offset.rx_missed); 4976 4977 pm_runtime_put_noidle(&pdev->dev); 4978 } 4979 4980 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4981 { 4982 netif_device_detach(tp->dev); 4983 4984 if (netif_running(tp->dev)) 4985 rtl8169_down(tp); 4986 } 4987 4988 static int rtl8169_runtime_resume(struct device *dev) 4989 { 4990 struct rtl8169_private *tp = dev_get_drvdata(dev); 4991 4992 rtl_rar_set(tp, tp->dev->dev_addr); 4993 __rtl8169_set_wol(tp, tp->saved_wolopts); 4994 4995 if (tp->TxDescArray) 4996 rtl8169_up(tp); 4997 4998 netif_device_attach(tp->dev); 4999 5000 return 0; 5001 } 5002 5003 static int rtl8169_suspend(struct device *device) 5004 { 5005 struct rtl8169_private *tp = dev_get_drvdata(device); 5006 5007 rtnl_lock(); 5008 rtl8169_net_suspend(tp); 5009 if (!device_may_wakeup(tp_to_dev(tp))) 5010 clk_disable_unprepare(tp->clk); 5011 rtnl_unlock(); 5012 5013 return 0; 5014 } 5015 5016 static int rtl8169_resume(struct device *device) 5017 { 5018 struct rtl8169_private *tp = dev_get_drvdata(device); 5019 5020 if (!device_may_wakeup(tp_to_dev(tp))) 5021 clk_prepare_enable(tp->clk); 5022 5023 /* Reportedly at least Asus X453MA truncates packets otherwise */ 5024 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 5025 rtl_init_rxcfg(tp); 5026 5027 return rtl8169_runtime_resume(device); 5028 } 5029 5030 static int rtl8169_runtime_suspend(struct device *device) 5031 { 5032 struct rtl8169_private *tp = dev_get_drvdata(device); 5033 5034 if (!tp->TxDescArray) { 5035 netif_device_detach(tp->dev); 5036 return 0; 5037 } 5038 5039 rtnl_lock(); 5040 __rtl8169_set_wol(tp, WAKE_PHY); 5041 rtl8169_net_suspend(tp); 5042 rtnl_unlock(); 5043 5044 return 0; 5045 } 5046 5047 static int rtl8169_runtime_idle(struct device *device) 5048 { 5049 struct rtl8169_private *tp = dev_get_drvdata(device); 5050 5051 if (tp->dash_enabled) 5052 return -EBUSY; 5053 5054 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5055 pm_schedule_suspend(device, 10000); 5056 5057 return -EBUSY; 5058 } 5059 5060 static const struct dev_pm_ops rtl8169_pm_ops = { 5061 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5062 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5063 rtl8169_runtime_idle) 5064 }; 5065 5066 static void rtl_shutdown(struct pci_dev *pdev) 5067 { 5068 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5069 5070 rtnl_lock(); 5071 rtl8169_net_suspend(tp); 5072 rtnl_unlock(); 5073 5074 /* Restore original MAC address */ 5075 rtl_rar_set(tp, tp->dev->perm_addr); 5076 5077 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5078 pci_wake_from_d3(pdev, tp->saved_wolopts); 5079 pci_set_power_state(pdev, PCI_D3hot); 5080 } 5081 } 5082 5083 static void rtl_remove_one(struct pci_dev *pdev) 5084 { 5085 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5086 5087 if (pci_dev_run_wake(pdev)) 5088 pm_runtime_get_noresume(&pdev->dev); 5089 5090 disable_work_sync(&tp->wk.work); 5091 5092 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5093 r8169_remove_leds(tp->leds); 5094 5095 unregister_netdev(tp->dev); 5096 5097 if (tp->dash_type != RTL_DASH_NONE) 5098 rtl8168_driver_stop(tp); 5099 5100 rtl_release_firmware(tp); 5101 5102 /* restore original MAC address */ 5103 rtl_rar_set(tp, tp->dev->perm_addr); 5104 } 5105 5106 static const struct net_device_ops rtl_netdev_ops = { 5107 .ndo_open = rtl_open, 5108 .ndo_stop = rtl8169_close, 5109 .ndo_get_stats64 = rtl8169_get_stats64, 5110 .ndo_start_xmit = rtl8169_start_xmit, 5111 .ndo_features_check = rtl8169_features_check, 5112 .ndo_tx_timeout = rtl8169_tx_timeout, 5113 .ndo_validate_addr = eth_validate_addr, 5114 .ndo_change_mtu = rtl8169_change_mtu, 5115 .ndo_fix_features = rtl8169_fix_features, 5116 .ndo_set_features = rtl8169_set_features, 5117 .ndo_set_mac_address = rtl_set_mac_address, 5118 .ndo_eth_ioctl = phy_do_ioctl_running, 5119 .ndo_set_rx_mode = rtl_set_rx_mode, 5120 #ifdef CONFIG_NET_POLL_CONTROLLER 5121 .ndo_poll_controller = rtl8169_netpoll, 5122 #endif 5123 5124 }; 5125 5126 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5127 { 5128 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5129 5130 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5131 tp->irq_mask |= SYSErr | RxFIFOOver; 5132 } 5133 5134 static int rtl_alloc_irq(struct rtl8169_private *tp) 5135 { 5136 unsigned int flags; 5137 5138 switch (tp->mac_version) { 5139 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5140 rtl_unlock_config_regs(tp); 5141 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5142 rtl_lock_config_regs(tp); 5143 fallthrough; 5144 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5145 flags = PCI_IRQ_INTX; 5146 break; 5147 default: 5148 flags = PCI_IRQ_ALL_TYPES; 5149 break; 5150 } 5151 5152 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5153 } 5154 5155 static void rtl_read_mac_address(struct rtl8169_private *tp, 5156 u8 mac_addr[ETH_ALEN]) 5157 { 5158 /* Get MAC address */ 5159 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5160 u32 value; 5161 5162 value = rtl_eri_read(tp, 0xe0); 5163 put_unaligned_le32(value, mac_addr); 5164 value = rtl_eri_read(tp, 0xe4); 5165 put_unaligned_le16(value, mac_addr + 4); 5166 } else if (rtl_is_8125(tp)) { 5167 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5168 } 5169 } 5170 5171 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5172 { 5173 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5174 } 5175 5176 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5177 { 5178 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5179 } 5180 5181 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5182 { 5183 struct rtl8169_private *tp = mii_bus->priv; 5184 5185 if (phyaddr > 0) 5186 return -ENODEV; 5187 5188 return rtl_readphy(tp, phyreg); 5189 } 5190 5191 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5192 int phyreg, u16 val) 5193 { 5194 struct rtl8169_private *tp = mii_bus->priv; 5195 5196 if (phyaddr > 0) 5197 return -ENODEV; 5198 5199 rtl_writephy(tp, phyreg, val); 5200 5201 return 0; 5202 } 5203 5204 static int r8169_mdio_read_reg_c45(struct mii_bus *mii_bus, int addr, 5205 int devnum, int regnum) 5206 { 5207 struct rtl8169_private *tp = mii_bus->priv; 5208 5209 if (addr > 0) 5210 return -ENODEV; 5211 5212 if (devnum == MDIO_MMD_VEND2 && regnum > MDIO_STAT2) 5213 return r8168_phy_ocp_read(tp, regnum); 5214 5215 return 0; 5216 } 5217 5218 static int r8169_mdio_write_reg_c45(struct mii_bus *mii_bus, int addr, 5219 int devnum, int regnum, u16 val) 5220 { 5221 struct rtl8169_private *tp = mii_bus->priv; 5222 5223 if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2) 5224 return -ENODEV; 5225 5226 r8168_phy_ocp_write(tp, regnum, val); 5227 5228 return 0; 5229 } 5230 5231 static int r8169_mdio_register(struct rtl8169_private *tp) 5232 { 5233 struct pci_dev *pdev = tp->pci_dev; 5234 struct mii_bus *new_bus; 5235 int ret; 5236 5237 /* On some boards with this chip version the BIOS is buggy and misses 5238 * to reset the PHY page selector. This results in the PHY ID read 5239 * accessing registers on a different page, returning a more or 5240 * less random value. Fix this by resetting the page selector first. 5241 */ 5242 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5243 tp->mac_version == RTL_GIGA_MAC_VER_26) 5244 r8169_mdio_write(tp, 0x1f, 0); 5245 5246 new_bus = devm_mdiobus_alloc(&pdev->dev); 5247 if (!new_bus) 5248 return -ENOMEM; 5249 5250 new_bus->name = "r8169"; 5251 new_bus->priv = tp; 5252 new_bus->parent = &pdev->dev; 5253 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5254 new_bus->phy_mask = GENMASK(31, 1); 5255 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5256 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5257 5258 new_bus->read = r8169_mdio_read_reg; 5259 new_bus->write = r8169_mdio_write_reg; 5260 5261 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) { 5262 new_bus->read_c45 = r8169_mdio_read_reg_c45; 5263 new_bus->write_c45 = r8169_mdio_write_reg_c45; 5264 } 5265 5266 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5267 if (ret) 5268 return ret; 5269 5270 tp->phydev = mdiobus_get_phy(new_bus, 0); 5271 if (!tp->phydev) { 5272 return -ENODEV; 5273 } else if (!tp->phydev->drv) { 5274 /* Most chip versions fail with the genphy driver. 5275 * Therefore ensure that the dedicated PHY driver is loaded. 5276 */ 5277 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5278 tp->phydev->phy_id); 5279 return -EUNATCH; 5280 } 5281 5282 tp->phydev->mac_managed_pm = true; 5283 if (rtl_supports_eee(tp)) 5284 phy_support_eee(tp->phydev); 5285 phy_support_asym_pause(tp->phydev); 5286 5287 /* mimic behavior of r8125/r8126 vendor drivers */ 5288 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 5289 phy_disable_eee_mode(tp->phydev, 5290 ETHTOOL_LINK_MODE_2500baseT_Full_BIT); 5291 phy_disable_eee_mode(tp->phydev, ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 5292 5293 /* PHY will be woken up in rtl_open() */ 5294 phy_suspend(tp->phydev); 5295 5296 return 0; 5297 } 5298 5299 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5300 { 5301 rtl_enable_rxdvgate(tp); 5302 5303 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5304 msleep(1); 5305 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5306 5307 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5308 r8168g_wait_ll_share_fifo_ready(tp); 5309 5310 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5311 r8168g_wait_ll_share_fifo_ready(tp); 5312 } 5313 5314 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5315 { 5316 rtl_enable_rxdvgate(tp); 5317 5318 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5319 msleep(1); 5320 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5321 5322 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5323 r8168g_wait_ll_share_fifo_ready(tp); 5324 5325 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5326 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5327 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5328 r8168g_wait_ll_share_fifo_ready(tp); 5329 } 5330 5331 static void rtl_hw_initialize(struct rtl8169_private *tp) 5332 { 5333 switch (tp->mac_version) { 5334 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5335 rtl8168ep_stop_cmac(tp); 5336 fallthrough; 5337 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5338 rtl_hw_init_8168g(tp); 5339 break; 5340 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 5341 rtl_hw_init_8125(tp); 5342 break; 5343 default: 5344 break; 5345 } 5346 } 5347 5348 static int rtl_jumbo_max(struct rtl8169_private *tp) 5349 { 5350 /* Non-GBit versions don't support jumbo frames */ 5351 if (!tp->supports_gmii) 5352 return 0; 5353 5354 switch (tp->mac_version) { 5355 /* RTL8169 */ 5356 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5357 return JUMBO_7K; 5358 /* RTL8168b */ 5359 case RTL_GIGA_MAC_VER_17: 5360 return JUMBO_4K; 5361 /* RTL8168c */ 5362 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5363 return JUMBO_6K; 5364 /* RTL8125/8126 */ 5365 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 5366 return JUMBO_16K; 5367 default: 5368 return JUMBO_9K; 5369 } 5370 } 5371 5372 static void rtl_init_mac_address(struct rtl8169_private *tp) 5373 { 5374 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5375 struct net_device *dev = tp->dev; 5376 int rc; 5377 5378 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5379 if (!rc) 5380 goto done; 5381 5382 rtl_read_mac_address(tp, mac_addr); 5383 if (is_valid_ether_addr(mac_addr)) 5384 goto done; 5385 5386 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5387 if (is_valid_ether_addr(mac_addr)) 5388 goto done; 5389 5390 eth_random_addr(mac_addr); 5391 dev->addr_assign_type = NET_ADDR_RANDOM; 5392 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5393 done: 5394 eth_hw_addr_set(dev, mac_addr); 5395 rtl_rar_set(tp, mac_addr); 5396 } 5397 5398 /* register is set if system vendor successfully tested ASPM 1.2 */ 5399 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5400 { 5401 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5402 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5403 return true; 5404 5405 return false; 5406 } 5407 5408 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5409 { 5410 struct rtl8169_private *tp; 5411 int jumbo_max, region, rc; 5412 enum mac_version chipset; 5413 struct net_device *dev; 5414 u32 txconfig; 5415 u16 xid; 5416 5417 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5418 if (!dev) 5419 return -ENOMEM; 5420 5421 SET_NETDEV_DEV(dev, &pdev->dev); 5422 dev->netdev_ops = &rtl_netdev_ops; 5423 tp = netdev_priv(dev); 5424 tp->dev = dev; 5425 tp->pci_dev = pdev; 5426 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5427 tp->ocp_base = OCP_STD_PHY_BASE; 5428 5429 raw_spin_lock_init(&tp->mac_ocp_lock); 5430 mutex_init(&tp->led_lock); 5431 5432 /* Get the *optional* external "ether_clk" used on some boards */ 5433 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5434 if (IS_ERR(tp->clk)) 5435 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5436 5437 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5438 rc = pcim_enable_device(pdev); 5439 if (rc < 0) 5440 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5441 5442 if (pcim_set_mwi(pdev) < 0) 5443 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5444 5445 /* use first MMIO region */ 5446 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5447 if (region < 0) 5448 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5449 5450 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5451 if (rc < 0) 5452 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5453 5454 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5455 5456 txconfig = RTL_R32(tp, TxConfig); 5457 if (txconfig == ~0U) 5458 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5459 5460 xid = (txconfig >> 20) & 0xfcf; 5461 5462 /* Identify chip attached to board */ 5463 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5464 if (chipset == RTL_GIGA_MAC_NONE) 5465 return dev_err_probe(&pdev->dev, -ENODEV, 5466 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5467 xid); 5468 tp->mac_version = chipset; 5469 5470 /* Disable ASPM L1 as that cause random device stop working 5471 * problems as well as full system hangs for some PCIe devices users. 5472 */ 5473 if (rtl_aspm_is_safe(tp)) 5474 rc = 0; 5475 else 5476 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5477 tp->aspm_manageable = !rc; 5478 5479 tp->dash_type = rtl_get_dash_type(tp); 5480 tp->dash_enabled = rtl_dash_is_enabled(tp); 5481 5482 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5483 5484 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5485 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5486 dev->features |= NETIF_F_HIGHDMA; 5487 5488 rtl_init_rxcfg(tp); 5489 5490 rtl8169_irq_mask_and_ack(tp); 5491 5492 rtl_hw_initialize(tp); 5493 5494 rtl_hw_reset(tp); 5495 5496 rc = rtl_alloc_irq(tp); 5497 if (rc < 0) 5498 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5499 5500 tp->irq = pci_irq_vector(pdev, 0); 5501 5502 INIT_WORK(&tp->wk.work, rtl_task); 5503 disable_work(&tp->wk.work); 5504 5505 rtl_init_mac_address(tp); 5506 5507 dev->ethtool_ops = &rtl8169_ethtool_ops; 5508 5509 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5510 5511 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5512 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5513 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5514 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5515 5516 /* 5517 * Pretend we are using VLANs; This bypasses a nasty bug where 5518 * Interrupts stop flowing on high load on 8110SCd controllers. 5519 */ 5520 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5521 /* Disallow toggling */ 5522 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5523 5524 if (rtl_chip_supports_csum_v2(tp)) 5525 dev->hw_features |= NETIF_F_IPV6_CSUM; 5526 5527 dev->features |= dev->hw_features; 5528 5529 if (rtl_chip_supports_csum_v2(tp)) { 5530 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5531 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5532 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5533 } else { 5534 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5535 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5536 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5537 } 5538 5539 /* There has been a number of reports that using SG/TSO results in 5540 * tx timeouts. However for a lot of people SG/TSO works fine. 5541 * It's not fully clear which chip versions are affected. Vendor 5542 * drivers enable SG/TSO for certain chip versions per default, 5543 * let's mimic this here. On other chip versions users can 5544 * use ethtool to enable SG/TSO, use at own risk! 5545 */ 5546 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5547 tp->mac_version != RTL_GIGA_MAC_VER_61) 5548 dev->features |= dev->hw_features; 5549 5550 dev->hw_features |= NETIF_F_RXALL; 5551 dev->hw_features |= NETIF_F_RXFCS; 5552 5553 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5554 5555 netdev_sw_irq_coalesce_default_on(dev); 5556 5557 /* configure chip for default features */ 5558 rtl8169_set_features(dev, dev->features); 5559 5560 if (!tp->dash_enabled) { 5561 rtl_set_d3_pll_down(tp, true); 5562 } else { 5563 rtl_set_d3_pll_down(tp, false); 5564 dev->ethtool->wol_enabled = 1; 5565 } 5566 5567 jumbo_max = rtl_jumbo_max(tp); 5568 if (jumbo_max) 5569 dev->max_mtu = jumbo_max; 5570 5571 rtl_set_irq_mask(tp); 5572 5573 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5574 5575 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5576 &tp->counters_phys_addr, 5577 GFP_KERNEL); 5578 if (!tp->counters) 5579 return -ENOMEM; 5580 5581 pci_set_drvdata(pdev, tp); 5582 5583 rc = r8169_mdio_register(tp); 5584 if (rc) 5585 return rc; 5586 5587 rc = register_netdev(dev); 5588 if (rc) 5589 return rc; 5590 5591 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5592 if (rtl_is_8125(tp)) 5593 tp->leds = rtl8125_init_leds(dev); 5594 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5595 tp->leds = rtl8168_init_leds(dev); 5596 } 5597 5598 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5599 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5600 5601 if (jumbo_max) 5602 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5603 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5604 "ok" : "ko"); 5605 5606 if (tp->dash_type != RTL_DASH_NONE) { 5607 netdev_info(dev, "DASH %s\n", 5608 tp->dash_enabled ? "enabled" : "disabled"); 5609 rtl8168_driver_start(tp); 5610 } 5611 5612 if (pci_dev_run_wake(pdev)) 5613 pm_runtime_put_sync(&pdev->dev); 5614 5615 return 0; 5616 } 5617 5618 static struct pci_driver rtl8169_pci_driver = { 5619 .name = KBUILD_MODNAME, 5620 .id_table = rtl8169_pci_tbl, 5621 .probe = rtl_init_one, 5622 .remove = rtl_remove_one, 5623 .shutdown = rtl_shutdown, 5624 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5625 }; 5626 5627 module_pci_driver(rtl8169_pci_driver); 5628