1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 52 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 53 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 54 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 55 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 56 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 57 58 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 59 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 60 #define MC_FILTER_LIMIT 32 61 62 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 63 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 64 65 #define R8169_REGS_SIZE 256 66 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 67 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 68 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 69 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 70 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 71 72 #define OCP_STD_PHY_BASE 0xa400 73 74 #define RTL_CFG_NO_GBIT 1 75 76 /* write/read MMIO register */ 77 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 81 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 82 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 83 84 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 89 static const struct { 90 const char *name; 91 const char *fw_name; 92 } rtl_chip_infos[] = { 93 /* PCI devices. */ 94 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 95 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 96 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 97 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 98 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 99 /* PCI-E devices. */ 100 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 102 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 103 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 104 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 105 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 106 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 108 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 109 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 115 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 116 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 117 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 118 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 119 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 121 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 122 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 123 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 124 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 125 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 126 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 127 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 128 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 129 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 130 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 131 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 132 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 133 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 134 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 135 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 136 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 137 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 138 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 139 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 140 }; 141 142 static const struct pci_device_id rtl8169_pci_tbl[] = { 143 { PCI_VDEVICE(REALTEK, 0x2502) }, 144 { PCI_VDEVICE(REALTEK, 0x2600) }, 145 { PCI_VDEVICE(REALTEK, 0x8129) }, 146 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 147 { PCI_VDEVICE(REALTEK, 0x8161) }, 148 { PCI_VDEVICE(REALTEK, 0x8162) }, 149 { PCI_VDEVICE(REALTEK, 0x8167) }, 150 { PCI_VDEVICE(REALTEK, 0x8168) }, 151 { PCI_VDEVICE(NCUBE, 0x8168) }, 152 { PCI_VDEVICE(REALTEK, 0x8169) }, 153 { PCI_VENDOR_ID_DLINK, 0x4300, 154 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 155 { PCI_VDEVICE(DLINK, 0x4300) }, 156 { PCI_VDEVICE(DLINK, 0x4302) }, 157 { PCI_VDEVICE(AT, 0xc107) }, 158 { PCI_VDEVICE(USR, 0x0116) }, 159 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 160 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 161 { PCI_VDEVICE(REALTEK, 0x8125) }, 162 { PCI_VDEVICE(REALTEK, 0x3000) }, 163 {} 164 }; 165 166 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 167 168 enum rtl_registers { 169 MAC0 = 0, /* Ethernet hardware address. */ 170 MAC4 = 4, 171 MAR0 = 8, /* Multicast filter. */ 172 CounterAddrLow = 0x10, 173 CounterAddrHigh = 0x14, 174 TxDescStartAddrLow = 0x20, 175 TxDescStartAddrHigh = 0x24, 176 TxHDescStartAddrLow = 0x28, 177 TxHDescStartAddrHigh = 0x2c, 178 FLASH = 0x30, 179 ERSR = 0x36, 180 ChipCmd = 0x37, 181 TxPoll = 0x38, 182 IntrMask = 0x3c, 183 IntrStatus = 0x3e, 184 185 TxConfig = 0x40, 186 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 187 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 188 189 RxConfig = 0x44, 190 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 191 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 192 #define RXCFG_FIFO_SHIFT 13 193 /* No threshold before first PCI xfer */ 194 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 195 #define RX_EARLY_OFF (1 << 11) 196 #define RXCFG_DMA_SHIFT 8 197 /* Unlimited maximum PCI burst. */ 198 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 199 200 Cfg9346 = 0x50, 201 Config0 = 0x51, 202 Config1 = 0x52, 203 Config2 = 0x53, 204 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 205 206 Config3 = 0x54, 207 Config4 = 0x55, 208 Config5 = 0x56, 209 PHYAR = 0x60, 210 PHYstatus = 0x6c, 211 RxMaxSize = 0xda, 212 CPlusCmd = 0xe0, 213 IntrMitigate = 0xe2, 214 215 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 216 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 217 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 218 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 219 220 #define RTL_COALESCE_T_MAX 0x0fU 221 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 222 223 RxDescAddrLow = 0xe4, 224 RxDescAddrHigh = 0xe8, 225 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 226 227 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 228 229 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 230 231 #define TxPacketMax (8064 >> 7) 232 #define EarlySize 0x27 233 234 FuncEvent = 0xf0, 235 FuncEventMask = 0xf4, 236 FuncPresetState = 0xf8, 237 IBCR0 = 0xf8, 238 IBCR2 = 0xf9, 239 IBIMR0 = 0xfa, 240 IBISR0 = 0xfb, 241 FuncForceEvent = 0xfc, 242 }; 243 244 enum rtl8168_8101_registers { 245 CSIDR = 0x64, 246 CSIAR = 0x68, 247 #define CSIAR_FLAG 0x80000000 248 #define CSIAR_WRITE_CMD 0x80000000 249 #define CSIAR_BYTE_ENABLE 0x0000f000 250 #define CSIAR_ADDR_MASK 0x00000fff 251 PMCH = 0x6f, 252 #define D3COLD_NO_PLL_DOWN BIT(7) 253 #define D3HOT_NO_PLL_DOWN BIT(6) 254 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 255 EPHYAR = 0x80, 256 #define EPHYAR_FLAG 0x80000000 257 #define EPHYAR_WRITE_CMD 0x80000000 258 #define EPHYAR_REG_MASK 0x1f 259 #define EPHYAR_REG_SHIFT 16 260 #define EPHYAR_DATA_MASK 0xffff 261 DLLPR = 0xd0, 262 #define PFM_EN (1 << 6) 263 #define TX_10M_PS_EN (1 << 7) 264 DBG_REG = 0xd1, 265 #define FIX_NAK_1 (1 << 4) 266 #define FIX_NAK_2 (1 << 3) 267 TWSI = 0xd2, 268 MCU = 0xd3, 269 #define NOW_IS_OOB (1 << 7) 270 #define TX_EMPTY (1 << 5) 271 #define RX_EMPTY (1 << 4) 272 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 273 #define EN_NDP (1 << 3) 274 #define EN_OOB_RESET (1 << 2) 275 #define LINK_LIST_RDY (1 << 1) 276 EFUSEAR = 0xdc, 277 #define EFUSEAR_FLAG 0x80000000 278 #define EFUSEAR_WRITE_CMD 0x80000000 279 #define EFUSEAR_READ_CMD 0x00000000 280 #define EFUSEAR_REG_MASK 0x03ff 281 #define EFUSEAR_REG_SHIFT 8 282 #define EFUSEAR_DATA_MASK 0xff 283 MISC_1 = 0xf2, 284 #define PFM_D3COLD_EN (1 << 6) 285 }; 286 287 enum rtl8168_registers { 288 LED_FREQ = 0x1a, 289 EEE_LED = 0x1b, 290 ERIDR = 0x70, 291 ERIAR = 0x74, 292 #define ERIAR_FLAG 0x80000000 293 #define ERIAR_WRITE_CMD 0x80000000 294 #define ERIAR_READ_CMD 0x00000000 295 #define ERIAR_ADDR_BYTE_ALIGN 4 296 #define ERIAR_TYPE_SHIFT 16 297 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 298 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 299 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 300 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 301 #define ERIAR_MASK_SHIFT 12 302 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 303 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 304 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 305 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 306 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 307 EPHY_RXER_NUM = 0x7c, 308 OCPDR = 0xb0, /* OCP GPHY access */ 309 #define OCPDR_WRITE_CMD 0x80000000 310 #define OCPDR_READ_CMD 0x00000000 311 #define OCPDR_REG_MASK 0x7f 312 #define OCPDR_GPHY_REG_SHIFT 16 313 #define OCPDR_DATA_MASK 0xffff 314 OCPAR = 0xb4, 315 #define OCPAR_FLAG 0x80000000 316 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 317 #define OCPAR_GPHY_READ_CMD 0x0000f060 318 GPHY_OCP = 0xb8, 319 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 320 MISC = 0xf0, /* 8168e only. */ 321 #define TXPLA_RST (1 << 29) 322 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 323 #define PWM_EN (1 << 22) 324 #define RXDV_GATED_EN (1 << 19) 325 #define EARLY_TALLY_EN (1 << 16) 326 }; 327 328 enum rtl8125_registers { 329 IntrMask_8125 = 0x38, 330 IntrStatus_8125 = 0x3c, 331 TxPoll_8125 = 0x90, 332 MAC0_BKP = 0x19e0, 333 EEE_TXIDLE_TIMER_8125 = 0x6048, 334 }; 335 336 #define RX_VLAN_INNER_8125 BIT(22) 337 #define RX_VLAN_OUTER_8125 BIT(23) 338 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 339 340 #define RX_FETCH_DFLT_8125 (8 << 27) 341 342 enum rtl_register_content { 343 /* InterruptStatusBits */ 344 SYSErr = 0x8000, 345 PCSTimeout = 0x4000, 346 SWInt = 0x0100, 347 TxDescUnavail = 0x0080, 348 RxFIFOOver = 0x0040, 349 LinkChg = 0x0020, 350 RxOverflow = 0x0010, 351 TxErr = 0x0008, 352 TxOK = 0x0004, 353 RxErr = 0x0002, 354 RxOK = 0x0001, 355 356 /* RxStatusDesc */ 357 RxRWT = (1 << 22), 358 RxRES = (1 << 21), 359 RxRUNT = (1 << 20), 360 RxCRC = (1 << 19), 361 362 /* ChipCmdBits */ 363 StopReq = 0x80, 364 CmdReset = 0x10, 365 CmdRxEnb = 0x08, 366 CmdTxEnb = 0x04, 367 RxBufEmpty = 0x01, 368 369 /* TXPoll register p.5 */ 370 HPQ = 0x80, /* Poll cmd on the high prio queue */ 371 NPQ = 0x40, /* Poll cmd on the low prio queue */ 372 FSWInt = 0x01, /* Forced software interrupt */ 373 374 /* Cfg9346Bits */ 375 Cfg9346_Lock = 0x00, 376 Cfg9346_Unlock = 0xc0, 377 378 /* rx_mode_bits */ 379 AcceptErr = 0x20, 380 AcceptRunt = 0x10, 381 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 382 AcceptBroadcast = 0x08, 383 AcceptMulticast = 0x04, 384 AcceptMyPhys = 0x02, 385 AcceptAllPhys = 0x01, 386 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 387 #define RX_CONFIG_ACCEPT_MASK 0x3f 388 389 /* TxConfigBits */ 390 TxInterFrameGapShift = 24, 391 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 392 393 /* Config1 register p.24 */ 394 LEDS1 = (1 << 7), 395 LEDS0 = (1 << 6), 396 Speed_down = (1 << 4), 397 MEMMAP = (1 << 3), 398 IOMAP = (1 << 2), 399 VPD = (1 << 1), 400 PMEnable = (1 << 0), /* Power Management Enable */ 401 402 /* Config2 register p. 25 */ 403 ClkReqEn = (1 << 7), /* Clock Request Enable */ 404 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 405 PCI_Clock_66MHz = 0x01, 406 PCI_Clock_33MHz = 0x00, 407 408 /* Config3 register p.25 */ 409 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 410 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 411 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 412 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 413 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 414 415 /* Config4 register */ 416 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 417 418 /* Config5 register p.27 */ 419 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 420 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 421 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 422 Spi_en = (1 << 3), 423 LanWake = (1 << 1), /* LanWake enable/disable */ 424 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 425 ASPM_en = (1 << 0), /* ASPM enable */ 426 427 /* CPlusCmd p.31 */ 428 EnableBist = (1 << 15), // 8168 8101 429 Mac_dbgo_oe = (1 << 14), // 8168 8101 430 EnAnaPLL = (1 << 14), // 8169 431 Normal_mode = (1 << 13), // unused 432 Force_half_dup = (1 << 12), // 8168 8101 433 Force_rxflow_en = (1 << 11), // 8168 8101 434 Force_txflow_en = (1 << 10), // 8168 8101 435 Cxpl_dbg_sel = (1 << 9), // 8168 8101 436 ASF = (1 << 8), // 8168 8101 437 PktCntrDisable = (1 << 7), // 8168 8101 438 Mac_dbgo_sel = 0x001c, // 8168 439 RxVlan = (1 << 6), 440 RxChkSum = (1 << 5), 441 PCIDAC = (1 << 4), 442 PCIMulRW = (1 << 3), 443 #define INTT_MASK GENMASK(1, 0) 444 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 445 446 /* rtl8169_PHYstatus */ 447 TBI_Enable = 0x80, 448 TxFlowCtrl = 0x40, 449 RxFlowCtrl = 0x20, 450 _1000bpsF = 0x10, 451 _100bps = 0x08, 452 _10bps = 0x04, 453 LinkStatus = 0x02, 454 FullDup = 0x01, 455 456 /* ResetCounterCommand */ 457 CounterReset = 0x1, 458 459 /* DumpCounterCommand */ 460 CounterDump = 0x8, 461 462 /* magic enable v2 */ 463 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 464 }; 465 466 enum rtl_desc_bit { 467 /* First doubleword. */ 468 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 469 RingEnd = (1 << 30), /* End of descriptor ring */ 470 FirstFrag = (1 << 29), /* First segment of a packet */ 471 LastFrag = (1 << 28), /* Final segment of a packet */ 472 }; 473 474 /* Generic case. */ 475 enum rtl_tx_desc_bit { 476 /* First doubleword. */ 477 TD_LSO = (1 << 27), /* Large Send Offload */ 478 #define TD_MSS_MAX 0x07ffu /* MSS value */ 479 480 /* Second doubleword. */ 481 TxVlanTag = (1 << 17), /* Add VLAN tag */ 482 }; 483 484 /* 8169, 8168b and 810x except 8102e. */ 485 enum rtl_tx_desc_bit_0 { 486 /* First doubleword. */ 487 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 488 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 489 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 490 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 491 }; 492 493 /* 8102e, 8168c and beyond. */ 494 enum rtl_tx_desc_bit_1 { 495 /* First doubleword. */ 496 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 497 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 498 #define GTTCPHO_SHIFT 18 499 #define GTTCPHO_MAX 0x7f 500 501 /* Second doubleword. */ 502 #define TCPHO_SHIFT 18 503 #define TCPHO_MAX 0x3ff 504 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 505 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 506 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 507 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 508 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 509 }; 510 511 enum rtl_rx_desc_bit { 512 /* Rx private */ 513 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 514 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 515 516 #define RxProtoUDP (PID1) 517 #define RxProtoTCP (PID0) 518 #define RxProtoIP (PID1 | PID0) 519 #define RxProtoMask RxProtoIP 520 521 IPFail = (1 << 16), /* IP checksum failed */ 522 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 523 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 524 525 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 526 527 RxVlanTag = (1 << 16), /* VLAN tag available */ 528 }; 529 530 #define RTL_GSO_MAX_SIZE_V1 32000 531 #define RTL_GSO_MAX_SEGS_V1 24 532 #define RTL_GSO_MAX_SIZE_V2 64000 533 #define RTL_GSO_MAX_SEGS_V2 64 534 535 struct TxDesc { 536 __le32 opts1; 537 __le32 opts2; 538 __le64 addr; 539 }; 540 541 struct RxDesc { 542 __le32 opts1; 543 __le32 opts2; 544 __le64 addr; 545 }; 546 547 struct ring_info { 548 struct sk_buff *skb; 549 u32 len; 550 }; 551 552 struct rtl8169_counters { 553 __le64 tx_packets; 554 __le64 rx_packets; 555 __le64 tx_errors; 556 __le32 rx_errors; 557 __le16 rx_missed; 558 __le16 align_errors; 559 __le32 tx_one_collision; 560 __le32 tx_multi_collision; 561 __le64 rx_unicast; 562 __le64 rx_broadcast; 563 __le32 rx_multicast; 564 __le16 tx_aborted; 565 __le16 tx_underun; 566 }; 567 568 struct rtl8169_tc_offsets { 569 bool inited; 570 __le64 tx_errors; 571 __le32 tx_multi_collision; 572 __le16 tx_aborted; 573 __le16 rx_missed; 574 }; 575 576 enum rtl_flag { 577 RTL_FLAG_TASK_ENABLED = 0, 578 RTL_FLAG_TASK_RESET_PENDING, 579 RTL_FLAG_TASK_TX_TIMEOUT, 580 RTL_FLAG_MAX 581 }; 582 583 enum rtl_dash_type { 584 RTL_DASH_NONE, 585 RTL_DASH_DP, 586 RTL_DASH_EP, 587 }; 588 589 struct rtl8169_private { 590 void __iomem *mmio_addr; /* memory map physical address */ 591 struct pci_dev *pci_dev; 592 struct net_device *dev; 593 struct phy_device *phydev; 594 struct napi_struct napi; 595 enum mac_version mac_version; 596 enum rtl_dash_type dash_type; 597 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 598 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 599 u32 dirty_tx; 600 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 601 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 602 dma_addr_t TxPhyAddr; 603 dma_addr_t RxPhyAddr; 604 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 605 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 606 u16 cp_cmd; 607 u32 irq_mask; 608 int irq; 609 struct clk *clk; 610 611 struct { 612 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 613 struct work_struct work; 614 } wk; 615 616 spinlock_t config25_lock; 617 spinlock_t mac_ocp_lock; 618 619 spinlock_t cfg9346_usage_lock; 620 int cfg9346_usage_count; 621 622 unsigned supports_gmii:1; 623 dma_addr_t counters_phys_addr; 624 struct rtl8169_counters *counters; 625 struct rtl8169_tc_offsets tc_offset; 626 u32 saved_wolopts; 627 int eee_adv; 628 629 const char *fw_name; 630 struct rtl_fw *rtl_fw; 631 632 u32 ocp_base; 633 }; 634 635 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 636 637 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 638 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 639 MODULE_SOFTDEP("pre: realtek"); 640 MODULE_LICENSE("GPL"); 641 MODULE_FIRMWARE(FIRMWARE_8168D_1); 642 MODULE_FIRMWARE(FIRMWARE_8168D_2); 643 MODULE_FIRMWARE(FIRMWARE_8168E_1); 644 MODULE_FIRMWARE(FIRMWARE_8168E_2); 645 MODULE_FIRMWARE(FIRMWARE_8168E_3); 646 MODULE_FIRMWARE(FIRMWARE_8105E_1); 647 MODULE_FIRMWARE(FIRMWARE_8168F_1); 648 MODULE_FIRMWARE(FIRMWARE_8168F_2); 649 MODULE_FIRMWARE(FIRMWARE_8402_1); 650 MODULE_FIRMWARE(FIRMWARE_8411_1); 651 MODULE_FIRMWARE(FIRMWARE_8411_2); 652 MODULE_FIRMWARE(FIRMWARE_8106E_1); 653 MODULE_FIRMWARE(FIRMWARE_8106E_2); 654 MODULE_FIRMWARE(FIRMWARE_8168G_2); 655 MODULE_FIRMWARE(FIRMWARE_8168G_3); 656 MODULE_FIRMWARE(FIRMWARE_8168H_2); 657 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 658 MODULE_FIRMWARE(FIRMWARE_8107E_2); 659 MODULE_FIRMWARE(FIRMWARE_8125A_3); 660 MODULE_FIRMWARE(FIRMWARE_8125B_2); 661 662 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 663 { 664 return &tp->pci_dev->dev; 665 } 666 667 static void rtl_lock_config_regs(struct rtl8169_private *tp) 668 { 669 unsigned long flags; 670 671 spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 672 if (!--tp->cfg9346_usage_count) 673 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 674 spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 675 } 676 677 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 678 { 679 unsigned long flags; 680 681 spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 682 if (!tp->cfg9346_usage_count++) 683 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 684 spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 685 } 686 687 static void rtl_pci_commit(struct rtl8169_private *tp) 688 { 689 /* Read an arbitrary register to commit a preceding PCI write */ 690 RTL_R8(tp, ChipCmd); 691 } 692 693 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 694 { 695 unsigned long flags; 696 u8 val; 697 698 spin_lock_irqsave(&tp->config25_lock, flags); 699 val = RTL_R8(tp, Config2); 700 RTL_W8(tp, Config2, (val & ~clear) | set); 701 spin_unlock_irqrestore(&tp->config25_lock, flags); 702 } 703 704 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 705 { 706 unsigned long flags; 707 u8 val; 708 709 spin_lock_irqsave(&tp->config25_lock, flags); 710 val = RTL_R8(tp, Config5); 711 RTL_W8(tp, Config5, (val & ~clear) | set); 712 spin_unlock_irqrestore(&tp->config25_lock, flags); 713 } 714 715 static bool rtl_is_8125(struct rtl8169_private *tp) 716 { 717 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 718 } 719 720 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 721 { 722 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 723 tp->mac_version != RTL_GIGA_MAC_VER_39 && 724 tp->mac_version <= RTL_GIGA_MAC_VER_53; 725 } 726 727 static bool rtl_supports_eee(struct rtl8169_private *tp) 728 { 729 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 730 tp->mac_version != RTL_GIGA_MAC_VER_37 && 731 tp->mac_version != RTL_GIGA_MAC_VER_39; 732 } 733 734 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 735 { 736 int i; 737 738 for (i = 0; i < ETH_ALEN; i++) 739 mac[i] = RTL_R8(tp, reg + i); 740 } 741 742 struct rtl_cond { 743 bool (*check)(struct rtl8169_private *); 744 const char *msg; 745 }; 746 747 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 748 unsigned long usecs, int n, bool high) 749 { 750 int i; 751 752 for (i = 0; i < n; i++) { 753 if (c->check(tp) == high) 754 return true; 755 fsleep(usecs); 756 } 757 758 if (net_ratelimit()) 759 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 760 c->msg, !high, n, usecs); 761 return false; 762 } 763 764 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 765 const struct rtl_cond *c, 766 unsigned long d, int n) 767 { 768 return rtl_loop_wait(tp, c, d, n, true); 769 } 770 771 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 772 const struct rtl_cond *c, 773 unsigned long d, int n) 774 { 775 return rtl_loop_wait(tp, c, d, n, false); 776 } 777 778 #define DECLARE_RTL_COND(name) \ 779 static bool name ## _check(struct rtl8169_private *); \ 780 \ 781 static const struct rtl_cond name = { \ 782 .check = name ## _check, \ 783 .msg = #name \ 784 }; \ 785 \ 786 static bool name ## _check(struct rtl8169_private *tp) 787 788 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 789 { 790 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 791 if (type == ERIAR_OOB && 792 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 793 tp->mac_version == RTL_GIGA_MAC_VER_53)) 794 *cmd |= 0xf70 << 18; 795 } 796 797 DECLARE_RTL_COND(rtl_eriar_cond) 798 { 799 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 800 } 801 802 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 803 u32 val, int type) 804 { 805 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 806 807 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 808 return; 809 810 RTL_W32(tp, ERIDR, val); 811 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 812 RTL_W32(tp, ERIAR, cmd); 813 814 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 815 } 816 817 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 818 u32 val) 819 { 820 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 821 } 822 823 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 824 { 825 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 826 827 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 828 RTL_W32(tp, ERIAR, cmd); 829 830 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 831 RTL_R32(tp, ERIDR) : ~0; 832 } 833 834 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 835 { 836 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 837 } 838 839 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 840 { 841 u32 val = rtl_eri_read(tp, addr); 842 843 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 844 } 845 846 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 847 { 848 rtl_w0w1_eri(tp, addr, p, 0); 849 } 850 851 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 852 { 853 rtl_w0w1_eri(tp, addr, 0, m); 854 } 855 856 static bool rtl_ocp_reg_failure(u32 reg) 857 { 858 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 859 } 860 861 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 862 { 863 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 864 } 865 866 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 867 { 868 if (rtl_ocp_reg_failure(reg)) 869 return; 870 871 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 872 873 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 874 } 875 876 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 877 { 878 if (rtl_ocp_reg_failure(reg)) 879 return 0; 880 881 RTL_W32(tp, GPHY_OCP, reg << 15); 882 883 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 884 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 885 } 886 887 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 888 { 889 if (rtl_ocp_reg_failure(reg)) 890 return; 891 892 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 893 } 894 895 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 896 { 897 unsigned long flags; 898 899 spin_lock_irqsave(&tp->mac_ocp_lock, flags); 900 __r8168_mac_ocp_write(tp, reg, data); 901 spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 902 } 903 904 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 905 { 906 if (rtl_ocp_reg_failure(reg)) 907 return 0; 908 909 RTL_W32(tp, OCPDR, reg << 15); 910 911 return RTL_R32(tp, OCPDR); 912 } 913 914 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 915 { 916 unsigned long flags; 917 u16 val; 918 919 spin_lock_irqsave(&tp->mac_ocp_lock, flags); 920 val = __r8168_mac_ocp_read(tp, reg); 921 spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 922 923 return val; 924 } 925 926 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 927 u16 set) 928 { 929 unsigned long flags; 930 u16 data; 931 932 spin_lock_irqsave(&tp->mac_ocp_lock, flags); 933 data = __r8168_mac_ocp_read(tp, reg); 934 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 935 spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 936 } 937 938 /* Work around a hw issue with RTL8168g PHY, the quirk disables 939 * PHY MCU interrupts before PHY power-down. 940 */ 941 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 942 { 943 switch (tp->mac_version) { 944 case RTL_GIGA_MAC_VER_40: 945 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 946 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 947 else 948 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 949 break; 950 default: 951 break; 952 } 953 }; 954 955 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 956 { 957 if (reg == 0x1f) { 958 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 959 return; 960 } 961 962 if (tp->ocp_base != OCP_STD_PHY_BASE) 963 reg -= 0x10; 964 965 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 966 rtl8168g_phy_suspend_quirk(tp, value); 967 968 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 969 } 970 971 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 972 { 973 if (reg == 0x1f) 974 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 975 976 if (tp->ocp_base != OCP_STD_PHY_BASE) 977 reg -= 0x10; 978 979 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 980 } 981 982 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 983 { 984 if (reg == 0x1f) { 985 tp->ocp_base = value << 4; 986 return; 987 } 988 989 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 990 } 991 992 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 993 { 994 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 995 } 996 997 DECLARE_RTL_COND(rtl_phyar_cond) 998 { 999 return RTL_R32(tp, PHYAR) & 0x80000000; 1000 } 1001 1002 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1003 { 1004 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1005 1006 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1007 /* 1008 * According to hardware specs a 20us delay is required after write 1009 * complete indication, but before sending next command. 1010 */ 1011 udelay(20); 1012 } 1013 1014 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1015 { 1016 int value; 1017 1018 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1019 1020 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1021 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1022 1023 /* 1024 * According to hardware specs a 20us delay is required after read 1025 * complete indication, but before sending next command. 1026 */ 1027 udelay(20); 1028 1029 return value; 1030 } 1031 1032 DECLARE_RTL_COND(rtl_ocpar_cond) 1033 { 1034 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1035 } 1036 1037 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1038 1039 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1040 { 1041 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1042 } 1043 1044 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1045 { 1046 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1047 } 1048 1049 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1050 { 1051 r8168dp_2_mdio_start(tp); 1052 1053 r8169_mdio_write(tp, reg, value); 1054 1055 r8168dp_2_mdio_stop(tp); 1056 } 1057 1058 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1059 { 1060 int value; 1061 1062 /* Work around issue with chip reporting wrong PHY ID */ 1063 if (reg == MII_PHYSID2) 1064 return 0xc912; 1065 1066 r8168dp_2_mdio_start(tp); 1067 1068 value = r8169_mdio_read(tp, reg); 1069 1070 r8168dp_2_mdio_stop(tp); 1071 1072 return value; 1073 } 1074 1075 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1076 { 1077 switch (tp->mac_version) { 1078 case RTL_GIGA_MAC_VER_28: 1079 case RTL_GIGA_MAC_VER_31: 1080 r8168dp_2_mdio_write(tp, location, val); 1081 break; 1082 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1083 r8168g_mdio_write(tp, location, val); 1084 break; 1085 default: 1086 r8169_mdio_write(tp, location, val); 1087 break; 1088 } 1089 } 1090 1091 static int rtl_readphy(struct rtl8169_private *tp, int location) 1092 { 1093 switch (tp->mac_version) { 1094 case RTL_GIGA_MAC_VER_28: 1095 case RTL_GIGA_MAC_VER_31: 1096 return r8168dp_2_mdio_read(tp, location); 1097 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1098 return r8168g_mdio_read(tp, location); 1099 default: 1100 return r8169_mdio_read(tp, location); 1101 } 1102 } 1103 1104 DECLARE_RTL_COND(rtl_ephyar_cond) 1105 { 1106 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1107 } 1108 1109 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1110 { 1111 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1112 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1113 1114 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1115 1116 udelay(10); 1117 } 1118 1119 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1120 { 1121 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1122 1123 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1124 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1125 } 1126 1127 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1128 { 1129 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1130 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1131 RTL_R32(tp, OCPDR) : ~0; 1132 } 1133 1134 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1135 { 1136 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1137 } 1138 1139 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1140 u32 data) 1141 { 1142 RTL_W32(tp, OCPDR, data); 1143 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1144 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1145 } 1146 1147 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1148 u32 data) 1149 { 1150 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1151 data, ERIAR_OOB); 1152 } 1153 1154 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1155 { 1156 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1157 1158 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1159 } 1160 1161 #define OOB_CMD_RESET 0x00 1162 #define OOB_CMD_DRIVER_START 0x05 1163 #define OOB_CMD_DRIVER_STOP 0x06 1164 1165 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1166 { 1167 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1168 } 1169 1170 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1171 { 1172 u16 reg; 1173 1174 reg = rtl8168_get_ocp_reg(tp); 1175 1176 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1177 } 1178 1179 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1180 { 1181 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1182 } 1183 1184 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1185 { 1186 return RTL_R8(tp, IBISR0) & 0x20; 1187 } 1188 1189 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1190 { 1191 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1192 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1193 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1194 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1195 } 1196 1197 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1198 { 1199 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1200 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1201 } 1202 1203 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1204 { 1205 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1206 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1207 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1208 } 1209 1210 static void rtl8168_driver_start(struct rtl8169_private *tp) 1211 { 1212 if (tp->dash_type == RTL_DASH_DP) 1213 rtl8168dp_driver_start(tp); 1214 else 1215 rtl8168ep_driver_start(tp); 1216 } 1217 1218 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1219 { 1220 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1221 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1222 } 1223 1224 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1225 { 1226 rtl8168ep_stop_cmac(tp); 1227 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1228 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1229 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1230 } 1231 1232 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1233 { 1234 if (tp->dash_type == RTL_DASH_DP) 1235 rtl8168dp_driver_stop(tp); 1236 else 1237 rtl8168ep_driver_stop(tp); 1238 } 1239 1240 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1241 { 1242 u16 reg = rtl8168_get_ocp_reg(tp); 1243 1244 return r8168dp_ocp_read(tp, reg) & BIT(15); 1245 } 1246 1247 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1248 { 1249 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1250 } 1251 1252 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1253 { 1254 switch (tp->mac_version) { 1255 case RTL_GIGA_MAC_VER_28: 1256 case RTL_GIGA_MAC_VER_31: 1257 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1258 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1259 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1260 default: 1261 return RTL_DASH_NONE; 1262 } 1263 } 1264 1265 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1266 { 1267 switch (tp->mac_version) { 1268 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1269 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1270 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1271 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1272 if (enable) 1273 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1274 else 1275 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1276 break; 1277 default: 1278 break; 1279 } 1280 } 1281 1282 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1283 { 1284 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1285 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1286 } 1287 1288 DECLARE_RTL_COND(rtl_efusear_cond) 1289 { 1290 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1291 } 1292 1293 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1294 { 1295 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1296 1297 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1298 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1299 } 1300 1301 static u32 rtl_get_events(struct rtl8169_private *tp) 1302 { 1303 if (rtl_is_8125(tp)) 1304 return RTL_R32(tp, IntrStatus_8125); 1305 else 1306 return RTL_R16(tp, IntrStatus); 1307 } 1308 1309 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1310 { 1311 if (rtl_is_8125(tp)) 1312 RTL_W32(tp, IntrStatus_8125, bits); 1313 else 1314 RTL_W16(tp, IntrStatus, bits); 1315 } 1316 1317 static void rtl_irq_disable(struct rtl8169_private *tp) 1318 { 1319 if (rtl_is_8125(tp)) 1320 RTL_W32(tp, IntrMask_8125, 0); 1321 else 1322 RTL_W16(tp, IntrMask, 0); 1323 } 1324 1325 static void rtl_irq_enable(struct rtl8169_private *tp) 1326 { 1327 if (rtl_is_8125(tp)) 1328 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1329 else 1330 RTL_W16(tp, IntrMask, tp->irq_mask); 1331 } 1332 1333 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1334 { 1335 rtl_irq_disable(tp); 1336 rtl_ack_events(tp, 0xffffffff); 1337 rtl_pci_commit(tp); 1338 } 1339 1340 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1341 { 1342 struct phy_device *phydev = tp->phydev; 1343 1344 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1345 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1346 if (phydev->speed == SPEED_1000) { 1347 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1348 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1349 } else if (phydev->speed == SPEED_100) { 1350 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1351 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1352 } else { 1353 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1354 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1355 } 1356 rtl_reset_packet_filter(tp); 1357 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1358 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1359 if (phydev->speed == SPEED_1000) { 1360 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1361 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1362 } else { 1363 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1364 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1365 } 1366 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1367 if (phydev->speed == SPEED_10) { 1368 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1369 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1370 } else { 1371 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1372 } 1373 } 1374 } 1375 1376 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1377 1378 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1379 { 1380 struct rtl8169_private *tp = netdev_priv(dev); 1381 1382 wol->supported = WAKE_ANY; 1383 wol->wolopts = tp->saved_wolopts; 1384 } 1385 1386 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1387 { 1388 static const struct { 1389 u32 opt; 1390 u16 reg; 1391 u8 mask; 1392 } cfg[] = { 1393 { WAKE_PHY, Config3, LinkUp }, 1394 { WAKE_UCAST, Config5, UWF }, 1395 { WAKE_BCAST, Config5, BWF }, 1396 { WAKE_MCAST, Config5, MWF }, 1397 { WAKE_ANY, Config5, LanWake }, 1398 { WAKE_MAGIC, Config3, MagicPacket } 1399 }; 1400 unsigned int i, tmp = ARRAY_SIZE(cfg); 1401 unsigned long flags; 1402 u8 options; 1403 1404 rtl_unlock_config_regs(tp); 1405 1406 if (rtl_is_8168evl_up(tp)) { 1407 tmp--; 1408 if (wolopts & WAKE_MAGIC) 1409 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1410 else 1411 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1412 } else if (rtl_is_8125(tp)) { 1413 tmp--; 1414 if (wolopts & WAKE_MAGIC) 1415 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1416 else 1417 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1418 } 1419 1420 spin_lock_irqsave(&tp->config25_lock, flags); 1421 for (i = 0; i < tmp; i++) { 1422 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1423 if (wolopts & cfg[i].opt) 1424 options |= cfg[i].mask; 1425 RTL_W8(tp, cfg[i].reg, options); 1426 } 1427 spin_unlock_irqrestore(&tp->config25_lock, flags); 1428 1429 switch (tp->mac_version) { 1430 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1431 options = RTL_R8(tp, Config1) & ~PMEnable; 1432 if (wolopts) 1433 options |= PMEnable; 1434 RTL_W8(tp, Config1, options); 1435 break; 1436 case RTL_GIGA_MAC_VER_34: 1437 case RTL_GIGA_MAC_VER_37: 1438 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1439 if (wolopts) 1440 rtl_mod_config2(tp, 0, PME_SIGNAL); 1441 else 1442 rtl_mod_config2(tp, PME_SIGNAL, 0); 1443 break; 1444 default: 1445 break; 1446 } 1447 1448 rtl_lock_config_regs(tp); 1449 1450 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1451 1452 if (tp->dash_type == RTL_DASH_NONE) { 1453 rtl_set_d3_pll_down(tp, !wolopts); 1454 tp->dev->wol_enabled = wolopts ? 1 : 0; 1455 } 1456 } 1457 1458 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1459 { 1460 struct rtl8169_private *tp = netdev_priv(dev); 1461 1462 if (wol->wolopts & ~WAKE_ANY) 1463 return -EINVAL; 1464 1465 tp->saved_wolopts = wol->wolopts; 1466 __rtl8169_set_wol(tp, tp->saved_wolopts); 1467 1468 return 0; 1469 } 1470 1471 static void rtl8169_get_drvinfo(struct net_device *dev, 1472 struct ethtool_drvinfo *info) 1473 { 1474 struct rtl8169_private *tp = netdev_priv(dev); 1475 struct rtl_fw *rtl_fw = tp->rtl_fw; 1476 1477 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1478 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1479 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1480 if (rtl_fw) 1481 strscpy(info->fw_version, rtl_fw->version, 1482 sizeof(info->fw_version)); 1483 } 1484 1485 static int rtl8169_get_regs_len(struct net_device *dev) 1486 { 1487 return R8169_REGS_SIZE; 1488 } 1489 1490 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1491 netdev_features_t features) 1492 { 1493 struct rtl8169_private *tp = netdev_priv(dev); 1494 1495 if (dev->mtu > TD_MSS_MAX) 1496 features &= ~NETIF_F_ALL_TSO; 1497 1498 if (dev->mtu > ETH_DATA_LEN && 1499 tp->mac_version > RTL_GIGA_MAC_VER_06) 1500 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1501 1502 return features; 1503 } 1504 1505 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1506 netdev_features_t features) 1507 { 1508 u32 rx_config = RTL_R32(tp, RxConfig); 1509 1510 if (features & NETIF_F_RXALL) 1511 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1512 else 1513 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1514 1515 if (rtl_is_8125(tp)) { 1516 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1517 rx_config |= RX_VLAN_8125; 1518 else 1519 rx_config &= ~RX_VLAN_8125; 1520 } 1521 1522 RTL_W32(tp, RxConfig, rx_config); 1523 } 1524 1525 static int rtl8169_set_features(struct net_device *dev, 1526 netdev_features_t features) 1527 { 1528 struct rtl8169_private *tp = netdev_priv(dev); 1529 1530 rtl_set_rx_config_features(tp, features); 1531 1532 if (features & NETIF_F_RXCSUM) 1533 tp->cp_cmd |= RxChkSum; 1534 else 1535 tp->cp_cmd &= ~RxChkSum; 1536 1537 if (!rtl_is_8125(tp)) { 1538 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1539 tp->cp_cmd |= RxVlan; 1540 else 1541 tp->cp_cmd &= ~RxVlan; 1542 } 1543 1544 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1545 rtl_pci_commit(tp); 1546 1547 return 0; 1548 } 1549 1550 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1551 { 1552 return (skb_vlan_tag_present(skb)) ? 1553 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1554 } 1555 1556 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1557 { 1558 u32 opts2 = le32_to_cpu(desc->opts2); 1559 1560 if (opts2 & RxVlanTag) 1561 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1562 } 1563 1564 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1565 void *p) 1566 { 1567 struct rtl8169_private *tp = netdev_priv(dev); 1568 u32 __iomem *data = tp->mmio_addr; 1569 u32 *dw = p; 1570 int i; 1571 1572 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1573 memcpy_fromio(dw++, data++, 4); 1574 } 1575 1576 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1577 "tx_packets", 1578 "rx_packets", 1579 "tx_errors", 1580 "rx_errors", 1581 "rx_missed", 1582 "align_errors", 1583 "tx_single_collisions", 1584 "tx_multi_collisions", 1585 "unicast", 1586 "broadcast", 1587 "multicast", 1588 "tx_aborted", 1589 "tx_underrun", 1590 }; 1591 1592 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1593 { 1594 switch (sset) { 1595 case ETH_SS_STATS: 1596 return ARRAY_SIZE(rtl8169_gstrings); 1597 default: 1598 return -EOPNOTSUPP; 1599 } 1600 } 1601 1602 DECLARE_RTL_COND(rtl_counters_cond) 1603 { 1604 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1605 } 1606 1607 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1608 { 1609 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1610 1611 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1612 rtl_pci_commit(tp); 1613 RTL_W32(tp, CounterAddrLow, cmd); 1614 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1615 1616 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1617 } 1618 1619 static void rtl8169_update_counters(struct rtl8169_private *tp) 1620 { 1621 u8 val = RTL_R8(tp, ChipCmd); 1622 1623 /* 1624 * Some chips are unable to dump tally counters when the receiver 1625 * is disabled. If 0xff chip may be in a PCI power-save state. 1626 */ 1627 if (val & CmdRxEnb && val != 0xff) 1628 rtl8169_do_counters(tp, CounterDump); 1629 } 1630 1631 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1632 { 1633 struct rtl8169_counters *counters = tp->counters; 1634 1635 /* 1636 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1637 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1638 * reset by a power cycle, while the counter values collected by the 1639 * driver are reset at every driver unload/load cycle. 1640 * 1641 * To make sure the HW values returned by @get_stats64 match the SW 1642 * values, we collect the initial values at first open(*) and use them 1643 * as offsets to normalize the values returned by @get_stats64. 1644 * 1645 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1646 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1647 * set at open time by rtl_hw_start. 1648 */ 1649 1650 if (tp->tc_offset.inited) 1651 return; 1652 1653 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1654 rtl8169_do_counters(tp, CounterReset); 1655 } else { 1656 rtl8169_update_counters(tp); 1657 tp->tc_offset.tx_errors = counters->tx_errors; 1658 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1659 tp->tc_offset.tx_aborted = counters->tx_aborted; 1660 tp->tc_offset.rx_missed = counters->rx_missed; 1661 } 1662 1663 tp->tc_offset.inited = true; 1664 } 1665 1666 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1667 struct ethtool_stats *stats, u64 *data) 1668 { 1669 struct rtl8169_private *tp = netdev_priv(dev); 1670 struct rtl8169_counters *counters; 1671 1672 counters = tp->counters; 1673 rtl8169_update_counters(tp); 1674 1675 data[0] = le64_to_cpu(counters->tx_packets); 1676 data[1] = le64_to_cpu(counters->rx_packets); 1677 data[2] = le64_to_cpu(counters->tx_errors); 1678 data[3] = le32_to_cpu(counters->rx_errors); 1679 data[4] = le16_to_cpu(counters->rx_missed); 1680 data[5] = le16_to_cpu(counters->align_errors); 1681 data[6] = le32_to_cpu(counters->tx_one_collision); 1682 data[7] = le32_to_cpu(counters->tx_multi_collision); 1683 data[8] = le64_to_cpu(counters->rx_unicast); 1684 data[9] = le64_to_cpu(counters->rx_broadcast); 1685 data[10] = le32_to_cpu(counters->rx_multicast); 1686 data[11] = le16_to_cpu(counters->tx_aborted); 1687 data[12] = le16_to_cpu(counters->tx_underun); 1688 } 1689 1690 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1691 { 1692 switch(stringset) { 1693 case ETH_SS_STATS: 1694 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1695 break; 1696 } 1697 } 1698 1699 /* 1700 * Interrupt coalescing 1701 * 1702 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1703 * > 8169, 8168 and 810x line of chipsets 1704 * 1705 * 8169, 8168, and 8136(810x) serial chipsets support it. 1706 * 1707 * > 2 - the Tx timer unit at gigabit speed 1708 * 1709 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1710 * (0xe0) bit 1 and bit 0. 1711 * 1712 * For 8169 1713 * bit[1:0] \ speed 1000M 100M 10M 1714 * 0 0 320ns 2.56us 40.96us 1715 * 0 1 2.56us 20.48us 327.7us 1716 * 1 0 5.12us 40.96us 655.4us 1717 * 1 1 10.24us 81.92us 1.31ms 1718 * 1719 * For the other 1720 * bit[1:0] \ speed 1000M 100M 10M 1721 * 0 0 5us 2.56us 40.96us 1722 * 0 1 40us 20.48us 327.7us 1723 * 1 0 80us 40.96us 655.4us 1724 * 1 1 160us 81.92us 1.31ms 1725 */ 1726 1727 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1728 struct rtl_coalesce_info { 1729 u32 speed; 1730 u32 scale_nsecs[4]; 1731 }; 1732 1733 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1734 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1735 1736 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1737 { SPEED_1000, COALESCE_DELAY(320) }, 1738 { SPEED_100, COALESCE_DELAY(2560) }, 1739 { SPEED_10, COALESCE_DELAY(40960) }, 1740 { 0 }, 1741 }; 1742 1743 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1744 { SPEED_1000, COALESCE_DELAY(5000) }, 1745 { SPEED_100, COALESCE_DELAY(2560) }, 1746 { SPEED_10, COALESCE_DELAY(40960) }, 1747 { 0 }, 1748 }; 1749 #undef COALESCE_DELAY 1750 1751 /* get rx/tx scale vector corresponding to current speed */ 1752 static const struct rtl_coalesce_info * 1753 rtl_coalesce_info(struct rtl8169_private *tp) 1754 { 1755 const struct rtl_coalesce_info *ci; 1756 1757 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1758 ci = rtl_coalesce_info_8169; 1759 else 1760 ci = rtl_coalesce_info_8168_8136; 1761 1762 /* if speed is unknown assume highest one */ 1763 if (tp->phydev->speed == SPEED_UNKNOWN) 1764 return ci; 1765 1766 for (; ci->speed; ci++) { 1767 if (tp->phydev->speed == ci->speed) 1768 return ci; 1769 } 1770 1771 return ERR_PTR(-ELNRNG); 1772 } 1773 1774 static int rtl_get_coalesce(struct net_device *dev, 1775 struct ethtool_coalesce *ec, 1776 struct kernel_ethtool_coalesce *kernel_coal, 1777 struct netlink_ext_ack *extack) 1778 { 1779 struct rtl8169_private *tp = netdev_priv(dev); 1780 const struct rtl_coalesce_info *ci; 1781 u32 scale, c_us, c_fr; 1782 u16 intrmit; 1783 1784 if (rtl_is_8125(tp)) 1785 return -EOPNOTSUPP; 1786 1787 memset(ec, 0, sizeof(*ec)); 1788 1789 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1790 ci = rtl_coalesce_info(tp); 1791 if (IS_ERR(ci)) 1792 return PTR_ERR(ci); 1793 1794 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1795 1796 intrmit = RTL_R16(tp, IntrMitigate); 1797 1798 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1799 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1800 1801 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1802 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1803 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1804 1805 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1806 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1807 1808 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1809 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1810 1811 return 0; 1812 } 1813 1814 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1815 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1816 u16 *cp01) 1817 { 1818 const struct rtl_coalesce_info *ci; 1819 u16 i; 1820 1821 ci = rtl_coalesce_info(tp); 1822 if (IS_ERR(ci)) 1823 return PTR_ERR(ci); 1824 1825 for (i = 0; i < 4; i++) { 1826 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1827 *cp01 = i; 1828 return ci->scale_nsecs[i]; 1829 } 1830 } 1831 1832 return -ERANGE; 1833 } 1834 1835 static int rtl_set_coalesce(struct net_device *dev, 1836 struct ethtool_coalesce *ec, 1837 struct kernel_ethtool_coalesce *kernel_coal, 1838 struct netlink_ext_ack *extack) 1839 { 1840 struct rtl8169_private *tp = netdev_priv(dev); 1841 u32 tx_fr = ec->tx_max_coalesced_frames; 1842 u32 rx_fr = ec->rx_max_coalesced_frames; 1843 u32 coal_usec_max, units; 1844 u16 w = 0, cp01 = 0; 1845 int scale; 1846 1847 if (rtl_is_8125(tp)) 1848 return -EOPNOTSUPP; 1849 1850 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1851 return -ERANGE; 1852 1853 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1854 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1855 if (scale < 0) 1856 return scale; 1857 1858 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1859 * not only when usecs=0 because of e.g. the following scenario: 1860 * 1861 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1862 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1863 * - then user does `ethtool -C eth0 rx-usecs 100` 1864 * 1865 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1866 * if we want to ignore rx_frames then it has to be set to 0. 1867 */ 1868 if (rx_fr == 1) 1869 rx_fr = 0; 1870 if (tx_fr == 1) 1871 tx_fr = 0; 1872 1873 /* HW requires time limit to be set if frame limit is set */ 1874 if ((tx_fr && !ec->tx_coalesce_usecs) || 1875 (rx_fr && !ec->rx_coalesce_usecs)) 1876 return -EINVAL; 1877 1878 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1879 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1880 1881 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1882 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1883 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1884 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1885 1886 RTL_W16(tp, IntrMitigate, w); 1887 1888 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1889 if (rtl_is_8168evl_up(tp)) { 1890 if (!rx_fr && !tx_fr) 1891 /* disable packet counter */ 1892 tp->cp_cmd |= PktCntrDisable; 1893 else 1894 tp->cp_cmd &= ~PktCntrDisable; 1895 } 1896 1897 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1898 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1899 rtl_pci_commit(tp); 1900 1901 return 0; 1902 } 1903 1904 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1905 { 1906 struct rtl8169_private *tp = netdev_priv(dev); 1907 1908 if (!rtl_supports_eee(tp)) 1909 return -EOPNOTSUPP; 1910 1911 return phy_ethtool_get_eee(tp->phydev, data); 1912 } 1913 1914 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1915 { 1916 struct rtl8169_private *tp = netdev_priv(dev); 1917 int ret; 1918 1919 if (!rtl_supports_eee(tp)) 1920 return -EOPNOTSUPP; 1921 1922 ret = phy_ethtool_set_eee(tp->phydev, data); 1923 1924 if (!ret) 1925 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1926 MDIO_AN_EEE_ADV); 1927 return ret; 1928 } 1929 1930 static void rtl8169_get_ringparam(struct net_device *dev, 1931 struct ethtool_ringparam *data, 1932 struct kernel_ethtool_ringparam *kernel_data, 1933 struct netlink_ext_ack *extack) 1934 { 1935 data->rx_max_pending = NUM_RX_DESC; 1936 data->rx_pending = NUM_RX_DESC; 1937 data->tx_max_pending = NUM_TX_DESC; 1938 data->tx_pending = NUM_TX_DESC; 1939 } 1940 1941 static void rtl8169_get_pauseparam(struct net_device *dev, 1942 struct ethtool_pauseparam *data) 1943 { 1944 struct rtl8169_private *tp = netdev_priv(dev); 1945 bool tx_pause, rx_pause; 1946 1947 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1948 1949 data->autoneg = tp->phydev->autoneg; 1950 data->tx_pause = tx_pause ? 1 : 0; 1951 data->rx_pause = rx_pause ? 1 : 0; 1952 } 1953 1954 static int rtl8169_set_pauseparam(struct net_device *dev, 1955 struct ethtool_pauseparam *data) 1956 { 1957 struct rtl8169_private *tp = netdev_priv(dev); 1958 1959 if (dev->mtu > ETH_DATA_LEN) 1960 return -EOPNOTSUPP; 1961 1962 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1963 1964 return 0; 1965 } 1966 1967 static const struct ethtool_ops rtl8169_ethtool_ops = { 1968 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1969 ETHTOOL_COALESCE_MAX_FRAMES, 1970 .get_drvinfo = rtl8169_get_drvinfo, 1971 .get_regs_len = rtl8169_get_regs_len, 1972 .get_link = ethtool_op_get_link, 1973 .get_coalesce = rtl_get_coalesce, 1974 .set_coalesce = rtl_set_coalesce, 1975 .get_regs = rtl8169_get_regs, 1976 .get_wol = rtl8169_get_wol, 1977 .set_wol = rtl8169_set_wol, 1978 .get_strings = rtl8169_get_strings, 1979 .get_sset_count = rtl8169_get_sset_count, 1980 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1981 .get_ts_info = ethtool_op_get_ts_info, 1982 .nway_reset = phy_ethtool_nway_reset, 1983 .get_eee = rtl8169_get_eee, 1984 .set_eee = rtl8169_set_eee, 1985 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1986 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1987 .get_ringparam = rtl8169_get_ringparam, 1988 .get_pauseparam = rtl8169_get_pauseparam, 1989 .set_pauseparam = rtl8169_set_pauseparam, 1990 }; 1991 1992 static void rtl_enable_eee(struct rtl8169_private *tp) 1993 { 1994 struct phy_device *phydev = tp->phydev; 1995 int adv; 1996 1997 /* respect EEE advertisement the user may have set */ 1998 if (tp->eee_adv >= 0) 1999 adv = tp->eee_adv; 2000 else 2001 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2002 2003 if (adv >= 0) 2004 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2005 } 2006 2007 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2008 { 2009 /* 2010 * The driver currently handles the 8168Bf and the 8168Be identically 2011 * but they can be identified more specifically through the test below 2012 * if needed: 2013 * 2014 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2015 * 2016 * Same thing for the 8101Eb and the 8101Ec: 2017 * 2018 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2019 */ 2020 static const struct rtl_mac_info { 2021 u16 mask; 2022 u16 val; 2023 enum mac_version ver; 2024 } mac_info[] = { 2025 /* 8125B family. */ 2026 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2027 2028 /* 8125A family. */ 2029 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2030 /* It seems only XID 609 made it to the mass market. 2031 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2032 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2033 */ 2034 2035 /* RTL8117 */ 2036 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2037 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2038 2039 /* 8168EP family. */ 2040 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2041 /* It seems this chip version never made it to 2042 * the wild. Let's disable detection. 2043 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2044 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2045 */ 2046 2047 /* 8168H family. */ 2048 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2049 /* It seems this chip version never made it to 2050 * the wild. Let's disable detection. 2051 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2052 */ 2053 2054 /* 8168G family. */ 2055 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2056 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2057 /* It seems this chip version never made it to 2058 * the wild. Let's disable detection. 2059 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2060 */ 2061 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2062 2063 /* 8168F family. */ 2064 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2065 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2066 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2067 2068 /* 8168E family. */ 2069 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2070 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2071 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2072 2073 /* 8168D family. */ 2074 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2075 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2076 2077 /* 8168DP family. */ 2078 /* It seems this early RTL8168dp version never made it to 2079 * the wild. Support has been removed. 2080 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2081 */ 2082 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2083 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2084 2085 /* 8168C family. */ 2086 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2087 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2088 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2089 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2090 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2091 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2092 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2093 2094 /* 8168B family. */ 2095 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2096 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2097 2098 /* 8101 family. */ 2099 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2100 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2101 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2102 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2103 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2104 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2105 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2106 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2107 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2108 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2109 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2110 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2111 2112 /* 8110 family. */ 2113 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2114 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2115 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2116 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2117 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2118 2119 /* Catch-all */ 2120 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2121 }; 2122 const struct rtl_mac_info *p = mac_info; 2123 enum mac_version ver; 2124 2125 while ((xid & p->mask) != p->val) 2126 p++; 2127 ver = p->ver; 2128 2129 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2130 if (ver == RTL_GIGA_MAC_VER_42) 2131 ver = RTL_GIGA_MAC_VER_43; 2132 else if (ver == RTL_GIGA_MAC_VER_46) 2133 ver = RTL_GIGA_MAC_VER_48; 2134 } 2135 2136 return ver; 2137 } 2138 2139 static void rtl_release_firmware(struct rtl8169_private *tp) 2140 { 2141 if (tp->rtl_fw) { 2142 rtl_fw_release_firmware(tp->rtl_fw); 2143 kfree(tp->rtl_fw); 2144 tp->rtl_fw = NULL; 2145 } 2146 } 2147 2148 void r8169_apply_firmware(struct rtl8169_private *tp) 2149 { 2150 int val; 2151 2152 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2153 if (tp->rtl_fw) { 2154 rtl_fw_write_firmware(tp, tp->rtl_fw); 2155 /* At least one firmware doesn't reset tp->ocp_base. */ 2156 tp->ocp_base = OCP_STD_PHY_BASE; 2157 2158 /* PHY soft reset may still be in progress */ 2159 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2160 !(val & BMCR_RESET), 2161 50000, 600000, true); 2162 } 2163 } 2164 2165 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2166 { 2167 /* Adjust EEE LED frequency */ 2168 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2169 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2170 2171 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2172 } 2173 2174 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2175 { 2176 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2177 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2178 } 2179 2180 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2181 { 2182 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2183 } 2184 2185 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2186 { 2187 rtl8125_set_eee_txidle_timer(tp); 2188 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2189 } 2190 2191 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2192 { 2193 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2194 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2195 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2196 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2197 } 2198 2199 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2200 { 2201 u16 data1, data2, ioffset; 2202 2203 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2204 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2205 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2206 2207 ioffset = (data2 >> 1) & 0x7ff8; 2208 ioffset |= data2 & 0x0007; 2209 if (data1 & BIT(7)) 2210 ioffset |= BIT(15); 2211 2212 return ioffset; 2213 } 2214 2215 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2216 { 2217 set_bit(flag, tp->wk.flags); 2218 schedule_work(&tp->wk.work); 2219 } 2220 2221 static void rtl8169_init_phy(struct rtl8169_private *tp) 2222 { 2223 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2224 2225 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2226 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2227 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2228 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2229 RTL_W8(tp, 0x82, 0x01); 2230 } 2231 2232 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2233 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2234 tp->pci_dev->subsystem_device == 0xe000) 2235 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2236 2237 /* We may have called phy_speed_down before */ 2238 phy_speed_up(tp->phydev); 2239 2240 if (rtl_supports_eee(tp)) 2241 rtl_enable_eee(tp); 2242 2243 genphy_soft_reset(tp->phydev); 2244 } 2245 2246 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2247 { 2248 rtl_unlock_config_regs(tp); 2249 2250 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2251 rtl_pci_commit(tp); 2252 2253 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2254 rtl_pci_commit(tp); 2255 2256 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2257 rtl_rar_exgmac_set(tp, addr); 2258 2259 rtl_lock_config_regs(tp); 2260 } 2261 2262 static int rtl_set_mac_address(struct net_device *dev, void *p) 2263 { 2264 struct rtl8169_private *tp = netdev_priv(dev); 2265 int ret; 2266 2267 ret = eth_mac_addr(dev, p); 2268 if (ret) 2269 return ret; 2270 2271 rtl_rar_set(tp, dev->dev_addr); 2272 2273 return 0; 2274 } 2275 2276 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2277 { 2278 switch (tp->mac_version) { 2279 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2280 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2281 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2282 break; 2283 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2284 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2285 case RTL_GIGA_MAC_VER_38: 2286 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2287 break; 2288 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2289 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2290 break; 2291 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2292 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2293 break; 2294 default: 2295 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2296 break; 2297 } 2298 } 2299 2300 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2301 { 2302 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2303 } 2304 2305 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2306 { 2307 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2308 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2309 } 2310 2311 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2312 { 2313 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2314 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2315 } 2316 2317 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2318 { 2319 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2320 } 2321 2322 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2323 { 2324 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2325 } 2326 2327 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2328 { 2329 RTL_W8(tp, MaxTxPacketSize, 0x24); 2330 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2331 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2332 } 2333 2334 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2335 { 2336 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2337 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2338 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2339 } 2340 2341 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2342 { 2343 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2344 } 2345 2346 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2347 { 2348 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2349 } 2350 2351 static void rtl_jumbo_config(struct rtl8169_private *tp) 2352 { 2353 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2354 int readrq = 4096; 2355 2356 rtl_unlock_config_regs(tp); 2357 switch (tp->mac_version) { 2358 case RTL_GIGA_MAC_VER_17: 2359 if (jumbo) { 2360 readrq = 512; 2361 r8168b_1_hw_jumbo_enable(tp); 2362 } else { 2363 r8168b_1_hw_jumbo_disable(tp); 2364 } 2365 break; 2366 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2367 if (jumbo) { 2368 readrq = 512; 2369 r8168c_hw_jumbo_enable(tp); 2370 } else { 2371 r8168c_hw_jumbo_disable(tp); 2372 } 2373 break; 2374 case RTL_GIGA_MAC_VER_28: 2375 if (jumbo) 2376 r8168dp_hw_jumbo_enable(tp); 2377 else 2378 r8168dp_hw_jumbo_disable(tp); 2379 break; 2380 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2381 if (jumbo) 2382 r8168e_hw_jumbo_enable(tp); 2383 else 2384 r8168e_hw_jumbo_disable(tp); 2385 break; 2386 default: 2387 break; 2388 } 2389 rtl_lock_config_regs(tp); 2390 2391 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2392 pcie_set_readrq(tp->pci_dev, readrq); 2393 2394 /* Chip doesn't support pause in jumbo mode */ 2395 if (jumbo) { 2396 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2397 tp->phydev->advertising); 2398 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2399 tp->phydev->advertising); 2400 phy_start_aneg(tp->phydev); 2401 } 2402 } 2403 2404 DECLARE_RTL_COND(rtl_chipcmd_cond) 2405 { 2406 return RTL_R8(tp, ChipCmd) & CmdReset; 2407 } 2408 2409 static void rtl_hw_reset(struct rtl8169_private *tp) 2410 { 2411 RTL_W8(tp, ChipCmd, CmdReset); 2412 2413 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2414 } 2415 2416 static void rtl_request_firmware(struct rtl8169_private *tp) 2417 { 2418 struct rtl_fw *rtl_fw; 2419 2420 /* firmware loaded already or no firmware available */ 2421 if (tp->rtl_fw || !tp->fw_name) 2422 return; 2423 2424 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2425 if (!rtl_fw) 2426 return; 2427 2428 rtl_fw->phy_write = rtl_writephy; 2429 rtl_fw->phy_read = rtl_readphy; 2430 rtl_fw->mac_mcu_write = mac_mcu_write; 2431 rtl_fw->mac_mcu_read = mac_mcu_read; 2432 rtl_fw->fw_name = tp->fw_name; 2433 rtl_fw->dev = tp_to_dev(tp); 2434 2435 if (rtl_fw_request_firmware(rtl_fw)) 2436 kfree(rtl_fw); 2437 else 2438 tp->rtl_fw = rtl_fw; 2439 } 2440 2441 static void rtl_rx_close(struct rtl8169_private *tp) 2442 { 2443 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2444 } 2445 2446 DECLARE_RTL_COND(rtl_npq_cond) 2447 { 2448 return RTL_R8(tp, TxPoll) & NPQ; 2449 } 2450 2451 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2452 { 2453 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2454 } 2455 2456 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2457 { 2458 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2459 } 2460 2461 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2462 { 2463 /* IntrMitigate has new functionality on RTL8125 */ 2464 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2465 } 2466 2467 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2468 { 2469 switch (tp->mac_version) { 2470 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2471 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2472 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2473 break; 2474 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2475 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2476 break; 2477 case RTL_GIGA_MAC_VER_63: 2478 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2479 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2480 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2481 break; 2482 default: 2483 break; 2484 } 2485 } 2486 2487 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2488 { 2489 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2490 } 2491 2492 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2493 { 2494 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2495 fsleep(2000); 2496 rtl_wait_txrx_fifo_empty(tp); 2497 } 2498 2499 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2500 { 2501 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2502 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2503 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2504 2505 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2506 rtl_disable_rxdvgate(tp); 2507 } 2508 2509 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2510 { 2511 if (tp->dash_type != RTL_DASH_NONE) 2512 return; 2513 2514 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2515 tp->mac_version == RTL_GIGA_MAC_VER_33) 2516 rtl_ephy_write(tp, 0x19, 0xff64); 2517 2518 if (device_may_wakeup(tp_to_dev(tp))) { 2519 phy_speed_down(tp->phydev, false); 2520 rtl_wol_enable_rx(tp); 2521 } 2522 } 2523 2524 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2525 { 2526 u32 val = TX_DMA_BURST << TxDMAShift | 2527 InterFrameGap << TxInterFrameGapShift; 2528 2529 if (rtl_is_8168evl_up(tp)) 2530 val |= TXCFG_AUTO_FIFO; 2531 2532 RTL_W32(tp, TxConfig, val); 2533 } 2534 2535 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2536 { 2537 /* Low hurts. Let's disable the filtering. */ 2538 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2539 } 2540 2541 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2542 { 2543 /* 2544 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2545 * register to be written before TxDescAddrLow to work. 2546 * Switching from MMIO to I/O access fixes the issue as well. 2547 */ 2548 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2549 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2550 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2551 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2552 } 2553 2554 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2555 { 2556 u32 val; 2557 2558 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2559 val = 0x000fff00; 2560 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2561 val = 0x00ffff00; 2562 else 2563 return; 2564 2565 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2566 val |= 0xff; 2567 2568 RTL_W32(tp, 0x7c, val); 2569 } 2570 2571 static void rtl_set_rx_mode(struct net_device *dev) 2572 { 2573 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2574 /* Multicast hash filter */ 2575 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2576 struct rtl8169_private *tp = netdev_priv(dev); 2577 u32 tmp; 2578 2579 if (dev->flags & IFF_PROMISC) { 2580 rx_mode |= AcceptAllPhys; 2581 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2582 dev->flags & IFF_ALLMULTI || 2583 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2584 /* accept all multicasts */ 2585 } else if (netdev_mc_empty(dev)) { 2586 rx_mode &= ~AcceptMulticast; 2587 } else { 2588 struct netdev_hw_addr *ha; 2589 2590 mc_filter[1] = mc_filter[0] = 0; 2591 netdev_for_each_mc_addr(ha, dev) { 2592 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2593 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2594 } 2595 2596 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2597 tmp = mc_filter[0]; 2598 mc_filter[0] = swab32(mc_filter[1]); 2599 mc_filter[1] = swab32(tmp); 2600 } 2601 } 2602 2603 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2604 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2605 2606 tmp = RTL_R32(tp, RxConfig); 2607 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2608 } 2609 2610 DECLARE_RTL_COND(rtl_csiar_cond) 2611 { 2612 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2613 } 2614 2615 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2616 { 2617 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2618 2619 RTL_W32(tp, CSIDR, value); 2620 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2621 CSIAR_BYTE_ENABLE | func << 16); 2622 2623 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2624 } 2625 2626 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2627 { 2628 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2629 2630 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2631 CSIAR_BYTE_ENABLE); 2632 2633 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2634 RTL_R32(tp, CSIDR) : ~0; 2635 } 2636 2637 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2638 { 2639 struct pci_dev *pdev = tp->pci_dev; 2640 u32 csi; 2641 2642 /* According to Realtek the value at config space address 0x070f 2643 * controls the L0s/L1 entrance latency. We try standard ECAM access 2644 * first and if it fails fall back to CSI. 2645 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2646 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2647 */ 2648 if (pdev->cfg_size > 0x070f && 2649 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2650 return; 2651 2652 netdev_notice_once(tp->dev, 2653 "No native access to PCI extended config space, falling back to CSI\n"); 2654 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2655 rtl_csi_write(tp, 0x070c, csi | val << 24); 2656 } 2657 2658 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2659 { 2660 /* L0 7us, L1 16us */ 2661 rtl_set_aspm_entry_latency(tp, 0x27); 2662 } 2663 2664 struct ephy_info { 2665 unsigned int offset; 2666 u16 mask; 2667 u16 bits; 2668 }; 2669 2670 static void __rtl_ephy_init(struct rtl8169_private *tp, 2671 const struct ephy_info *e, int len) 2672 { 2673 u16 w; 2674 2675 while (len-- > 0) { 2676 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2677 rtl_ephy_write(tp, e->offset, w); 2678 e++; 2679 } 2680 } 2681 2682 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2683 2684 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2685 { 2686 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2687 PCI_EXP_LNKCTL_CLKREQ_EN); 2688 } 2689 2690 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2691 { 2692 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2693 PCI_EXP_LNKCTL_CLKREQ_EN); 2694 } 2695 2696 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2697 { 2698 /* work around an issue when PCI reset occurs during L2/L3 state */ 2699 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2700 } 2701 2702 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2703 { 2704 /* Bits control which events trigger ASPM L1 exit: 2705 * Bit 12: rxdv 2706 * Bit 11: ltr_msg 2707 * Bit 10: txdma_poll 2708 * Bit 9: xadm 2709 * Bit 8: pktavi 2710 * Bit 7: txpla 2711 */ 2712 switch (tp->mac_version) { 2713 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2714 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2715 break; 2716 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2717 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2718 break; 2719 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2720 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2721 break; 2722 default: 2723 break; 2724 } 2725 } 2726 2727 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2728 { 2729 switch (tp->mac_version) { 2730 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2731 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2732 break; 2733 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2734 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2735 break; 2736 default: 2737 break; 2738 } 2739 } 2740 2741 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2742 { 2743 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2744 return; 2745 2746 if (enable) { 2747 rtl_mod_config5(tp, 0, ASPM_en); 2748 rtl_mod_config2(tp, 0, ClkReqEn); 2749 2750 switch (tp->mac_version) { 2751 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2752 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2753 /* reset ephy tx/rx disable timer */ 2754 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2755 /* chip can trigger L1.2 */ 2756 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2757 break; 2758 default: 2759 break; 2760 } 2761 } else { 2762 switch (tp->mac_version) { 2763 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2764 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2765 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2766 break; 2767 default: 2768 break; 2769 } 2770 2771 rtl_mod_config2(tp, ClkReqEn, 0); 2772 rtl_mod_config5(tp, ASPM_en, 0); 2773 } 2774 } 2775 2776 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2777 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2778 { 2779 /* Usage of dynamic vs. static FIFO is controlled by bit 2780 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2781 */ 2782 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2783 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2784 } 2785 2786 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2787 u8 low, u8 high) 2788 { 2789 /* FIFO thresholds for pause flow control */ 2790 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2791 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2792 } 2793 2794 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2795 { 2796 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2797 } 2798 2799 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2800 { 2801 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2802 2803 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2804 2805 rtl_disable_clock_request(tp); 2806 } 2807 2808 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2809 { 2810 static const struct ephy_info e_info_8168cp[] = { 2811 { 0x01, 0, 0x0001 }, 2812 { 0x02, 0x0800, 0x1000 }, 2813 { 0x03, 0, 0x0042 }, 2814 { 0x06, 0x0080, 0x0000 }, 2815 { 0x07, 0, 0x2000 } 2816 }; 2817 2818 rtl_set_def_aspm_entry_latency(tp); 2819 2820 rtl_ephy_init(tp, e_info_8168cp); 2821 2822 __rtl_hw_start_8168cp(tp); 2823 } 2824 2825 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2826 { 2827 rtl_set_def_aspm_entry_latency(tp); 2828 2829 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2830 } 2831 2832 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2833 { 2834 rtl_set_def_aspm_entry_latency(tp); 2835 2836 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2837 2838 /* Magic. */ 2839 RTL_W8(tp, DBG_REG, 0x20); 2840 } 2841 2842 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2843 { 2844 static const struct ephy_info e_info_8168c_1[] = { 2845 { 0x02, 0x0800, 0x1000 }, 2846 { 0x03, 0, 0x0002 }, 2847 { 0x06, 0x0080, 0x0000 } 2848 }; 2849 2850 rtl_set_def_aspm_entry_latency(tp); 2851 2852 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2853 2854 rtl_ephy_init(tp, e_info_8168c_1); 2855 2856 __rtl_hw_start_8168cp(tp); 2857 } 2858 2859 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2860 { 2861 static const struct ephy_info e_info_8168c_2[] = { 2862 { 0x01, 0, 0x0001 }, 2863 { 0x03, 0x0400, 0x0020 } 2864 }; 2865 2866 rtl_set_def_aspm_entry_latency(tp); 2867 2868 rtl_ephy_init(tp, e_info_8168c_2); 2869 2870 __rtl_hw_start_8168cp(tp); 2871 } 2872 2873 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2874 { 2875 rtl_set_def_aspm_entry_latency(tp); 2876 2877 __rtl_hw_start_8168cp(tp); 2878 } 2879 2880 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2881 { 2882 rtl_set_def_aspm_entry_latency(tp); 2883 2884 rtl_disable_clock_request(tp); 2885 } 2886 2887 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2888 { 2889 static const struct ephy_info e_info_8168d_4[] = { 2890 { 0x0b, 0x0000, 0x0048 }, 2891 { 0x19, 0x0020, 0x0050 }, 2892 { 0x0c, 0x0100, 0x0020 }, 2893 { 0x10, 0x0004, 0x0000 }, 2894 }; 2895 2896 rtl_set_def_aspm_entry_latency(tp); 2897 2898 rtl_ephy_init(tp, e_info_8168d_4); 2899 2900 rtl_enable_clock_request(tp); 2901 } 2902 2903 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2904 { 2905 static const struct ephy_info e_info_8168e_1[] = { 2906 { 0x00, 0x0200, 0x0100 }, 2907 { 0x00, 0x0000, 0x0004 }, 2908 { 0x06, 0x0002, 0x0001 }, 2909 { 0x06, 0x0000, 0x0030 }, 2910 { 0x07, 0x0000, 0x2000 }, 2911 { 0x00, 0x0000, 0x0020 }, 2912 { 0x03, 0x5800, 0x2000 }, 2913 { 0x03, 0x0000, 0x0001 }, 2914 { 0x01, 0x0800, 0x1000 }, 2915 { 0x07, 0x0000, 0x4000 }, 2916 { 0x1e, 0x0000, 0x2000 }, 2917 { 0x19, 0xffff, 0xfe6c }, 2918 { 0x0a, 0x0000, 0x0040 } 2919 }; 2920 2921 rtl_set_def_aspm_entry_latency(tp); 2922 2923 rtl_ephy_init(tp, e_info_8168e_1); 2924 2925 rtl_disable_clock_request(tp); 2926 2927 /* Reset tx FIFO pointer */ 2928 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2929 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2930 2931 rtl_mod_config5(tp, Spi_en, 0); 2932 } 2933 2934 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2935 { 2936 static const struct ephy_info e_info_8168e_2[] = { 2937 { 0x09, 0x0000, 0x0080 }, 2938 { 0x19, 0x0000, 0x0224 }, 2939 { 0x00, 0x0000, 0x0004 }, 2940 { 0x0c, 0x3df0, 0x0200 }, 2941 }; 2942 2943 rtl_set_def_aspm_entry_latency(tp); 2944 2945 rtl_ephy_init(tp, e_info_8168e_2); 2946 2947 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2948 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2949 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2950 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2951 rtl_reset_packet_filter(tp); 2952 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2953 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2954 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2955 2956 rtl_disable_clock_request(tp); 2957 2958 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2959 2960 rtl8168_config_eee_mac(tp); 2961 2962 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2963 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2964 rtl_mod_config5(tp, Spi_en, 0); 2965 } 2966 2967 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2968 { 2969 rtl_set_def_aspm_entry_latency(tp); 2970 2971 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2972 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2973 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2974 rtl_reset_packet_filter(tp); 2975 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2976 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2977 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2978 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2979 2980 rtl_disable_clock_request(tp); 2981 2982 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2983 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2984 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2985 rtl_mod_config5(tp, Spi_en, 0); 2986 2987 rtl8168_config_eee_mac(tp); 2988 } 2989 2990 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2991 { 2992 static const struct ephy_info e_info_8168f_1[] = { 2993 { 0x06, 0x00c0, 0x0020 }, 2994 { 0x08, 0x0001, 0x0002 }, 2995 { 0x09, 0x0000, 0x0080 }, 2996 { 0x19, 0x0000, 0x0224 }, 2997 { 0x00, 0x0000, 0x0008 }, 2998 { 0x0c, 0x3df0, 0x0200 }, 2999 }; 3000 3001 rtl_hw_start_8168f(tp); 3002 3003 rtl_ephy_init(tp, e_info_8168f_1); 3004 } 3005 3006 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3007 { 3008 static const struct ephy_info e_info_8168f_1[] = { 3009 { 0x06, 0x00c0, 0x0020 }, 3010 { 0x0f, 0xffff, 0x5200 }, 3011 { 0x19, 0x0000, 0x0224 }, 3012 { 0x00, 0x0000, 0x0008 }, 3013 { 0x0c, 0x3df0, 0x0200 }, 3014 }; 3015 3016 rtl_hw_start_8168f(tp); 3017 rtl_pcie_state_l2l3_disable(tp); 3018 3019 rtl_ephy_init(tp, e_info_8168f_1); 3020 } 3021 3022 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3023 { 3024 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3025 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3026 3027 rtl_set_def_aspm_entry_latency(tp); 3028 3029 rtl_reset_packet_filter(tp); 3030 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3031 3032 rtl_disable_rxdvgate(tp); 3033 3034 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3035 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3036 3037 rtl8168_config_eee_mac(tp); 3038 3039 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3040 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3041 3042 rtl_pcie_state_l2l3_disable(tp); 3043 } 3044 3045 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3046 { 3047 static const struct ephy_info e_info_8168g_1[] = { 3048 { 0x00, 0x0008, 0x0000 }, 3049 { 0x0c, 0x3ff0, 0x0820 }, 3050 { 0x1e, 0x0000, 0x0001 }, 3051 { 0x19, 0x8000, 0x0000 } 3052 }; 3053 3054 rtl_hw_start_8168g(tp); 3055 rtl_ephy_init(tp, e_info_8168g_1); 3056 } 3057 3058 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3059 { 3060 static const struct ephy_info e_info_8168g_2[] = { 3061 { 0x00, 0x0008, 0x0000 }, 3062 { 0x0c, 0x3ff0, 0x0820 }, 3063 { 0x19, 0xffff, 0x7c00 }, 3064 { 0x1e, 0xffff, 0x20eb }, 3065 { 0x0d, 0xffff, 0x1666 }, 3066 { 0x00, 0xffff, 0x10a3 }, 3067 { 0x06, 0xffff, 0xf050 }, 3068 { 0x04, 0x0000, 0x0010 }, 3069 { 0x1d, 0x4000, 0x0000 }, 3070 }; 3071 3072 rtl_hw_start_8168g(tp); 3073 rtl_ephy_init(tp, e_info_8168g_2); 3074 } 3075 3076 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3077 { 3078 static const struct ephy_info e_info_8411_2[] = { 3079 { 0x00, 0x0008, 0x0000 }, 3080 { 0x0c, 0x37d0, 0x0820 }, 3081 { 0x1e, 0x0000, 0x0001 }, 3082 { 0x19, 0x8021, 0x0000 }, 3083 { 0x1e, 0x0000, 0x2000 }, 3084 { 0x0d, 0x0100, 0x0200 }, 3085 { 0x00, 0x0000, 0x0080 }, 3086 { 0x06, 0x0000, 0x0010 }, 3087 { 0x04, 0x0000, 0x0010 }, 3088 { 0x1d, 0x0000, 0x4000 }, 3089 }; 3090 3091 rtl_hw_start_8168g(tp); 3092 3093 rtl_ephy_init(tp, e_info_8411_2); 3094 3095 /* The following Realtek-provided magic fixes an issue with the RX unit 3096 * getting confused after the PHY having been powered-down. 3097 */ 3098 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3099 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3100 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3101 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3102 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3103 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3104 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3105 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3106 mdelay(3); 3107 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3108 3109 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3110 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3111 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3112 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3113 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3114 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3115 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3116 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3117 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3118 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3119 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3120 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3121 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3122 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3123 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3124 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3125 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3126 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3127 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3128 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3129 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3130 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3131 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3132 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3133 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3134 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3135 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3136 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3137 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3138 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3139 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3140 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3141 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3142 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3143 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3144 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3145 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3146 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3147 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3148 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3149 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3150 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3151 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3152 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3153 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3154 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3155 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3156 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3157 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3158 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3159 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3160 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3161 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3162 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3163 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3164 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3165 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3166 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3167 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3168 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3169 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3170 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3171 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3172 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3173 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3174 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3175 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3176 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3177 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3178 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3179 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3180 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3181 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3182 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3183 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3184 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3185 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3186 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3187 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3188 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3189 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3190 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3191 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3192 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3193 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3194 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3195 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3196 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3197 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3198 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3199 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3200 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3201 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3202 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3203 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3204 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3205 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3206 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3207 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3208 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3209 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3210 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3211 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3212 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3213 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3214 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3215 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3216 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3217 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3218 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3219 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3220 3221 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3222 3223 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3224 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3225 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3226 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3227 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3228 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3229 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3230 } 3231 3232 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3233 { 3234 static const struct ephy_info e_info_8168h_1[] = { 3235 { 0x1e, 0x0800, 0x0001 }, 3236 { 0x1d, 0x0000, 0x0800 }, 3237 { 0x05, 0xffff, 0x2089 }, 3238 { 0x06, 0xffff, 0x5881 }, 3239 { 0x04, 0xffff, 0x854a }, 3240 { 0x01, 0xffff, 0x068b } 3241 }; 3242 int rg_saw_cnt; 3243 3244 rtl_ephy_init(tp, e_info_8168h_1); 3245 3246 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3247 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3248 3249 rtl_set_def_aspm_entry_latency(tp); 3250 3251 rtl_reset_packet_filter(tp); 3252 3253 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3254 3255 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3256 3257 rtl_disable_rxdvgate(tp); 3258 3259 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3260 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3261 3262 rtl8168_config_eee_mac(tp); 3263 3264 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3265 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3266 3267 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3268 3269 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3270 3271 rtl_pcie_state_l2l3_disable(tp); 3272 3273 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3274 if (rg_saw_cnt > 0) { 3275 u16 sw_cnt_1ms_ini; 3276 3277 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3278 sw_cnt_1ms_ini &= 0x0fff; 3279 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3280 } 3281 3282 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3283 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3284 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3285 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3286 3287 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3288 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3289 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3290 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3291 } 3292 3293 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3294 { 3295 rtl8168ep_stop_cmac(tp); 3296 3297 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3298 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3299 3300 rtl_set_def_aspm_entry_latency(tp); 3301 3302 rtl_reset_packet_filter(tp); 3303 3304 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3305 3306 rtl_disable_rxdvgate(tp); 3307 3308 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3309 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3310 3311 rtl8168_config_eee_mac(tp); 3312 3313 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3314 3315 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3316 3317 rtl_pcie_state_l2l3_disable(tp); 3318 } 3319 3320 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3321 { 3322 static const struct ephy_info e_info_8168ep_3[] = { 3323 { 0x00, 0x0000, 0x0080 }, 3324 { 0x0d, 0x0100, 0x0200 }, 3325 { 0x19, 0x8021, 0x0000 }, 3326 { 0x1e, 0x0000, 0x2000 }, 3327 }; 3328 3329 rtl_ephy_init(tp, e_info_8168ep_3); 3330 3331 rtl_hw_start_8168ep(tp); 3332 3333 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3334 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3335 3336 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3337 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3338 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3339 } 3340 3341 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3342 { 3343 static const struct ephy_info e_info_8117[] = { 3344 { 0x19, 0x0040, 0x1100 }, 3345 { 0x59, 0x0040, 0x1100 }, 3346 }; 3347 int rg_saw_cnt; 3348 3349 rtl8168ep_stop_cmac(tp); 3350 rtl_ephy_init(tp, e_info_8117); 3351 3352 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3353 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3354 3355 rtl_set_def_aspm_entry_latency(tp); 3356 3357 rtl_reset_packet_filter(tp); 3358 3359 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3360 3361 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3362 3363 rtl_disable_rxdvgate(tp); 3364 3365 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3366 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3367 3368 rtl8168_config_eee_mac(tp); 3369 3370 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3371 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3372 3373 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3374 3375 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3376 3377 rtl_pcie_state_l2l3_disable(tp); 3378 3379 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3380 if (rg_saw_cnt > 0) { 3381 u16 sw_cnt_1ms_ini; 3382 3383 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3384 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3385 } 3386 3387 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3388 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3389 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3390 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3391 3392 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3393 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3394 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3395 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3396 3397 /* firmware is for MAC only */ 3398 r8169_apply_firmware(tp); 3399 } 3400 3401 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3402 { 3403 static const struct ephy_info e_info_8102e_1[] = { 3404 { 0x01, 0, 0x6e65 }, 3405 { 0x02, 0, 0x091f }, 3406 { 0x03, 0, 0xc2f9 }, 3407 { 0x06, 0, 0xafb5 }, 3408 { 0x07, 0, 0x0e00 }, 3409 { 0x19, 0, 0xec80 }, 3410 { 0x01, 0, 0x2e65 }, 3411 { 0x01, 0, 0x6e65 } 3412 }; 3413 u8 cfg1; 3414 3415 rtl_set_def_aspm_entry_latency(tp); 3416 3417 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3418 3419 RTL_W8(tp, Config1, 3420 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3421 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3422 3423 cfg1 = RTL_R8(tp, Config1); 3424 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3425 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3426 3427 rtl_ephy_init(tp, e_info_8102e_1); 3428 } 3429 3430 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3431 { 3432 rtl_set_def_aspm_entry_latency(tp); 3433 3434 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3435 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3436 } 3437 3438 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3439 { 3440 rtl_hw_start_8102e_2(tp); 3441 3442 rtl_ephy_write(tp, 0x03, 0xc2f9); 3443 } 3444 3445 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3446 { 3447 static const struct ephy_info e_info_8401[] = { 3448 { 0x01, 0xffff, 0x6fe5 }, 3449 { 0x03, 0xffff, 0x0599 }, 3450 { 0x06, 0xffff, 0xaf25 }, 3451 { 0x07, 0xffff, 0x8e68 }, 3452 }; 3453 3454 rtl_ephy_init(tp, e_info_8401); 3455 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3456 } 3457 3458 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3459 { 3460 static const struct ephy_info e_info_8105e_1[] = { 3461 { 0x07, 0, 0x4000 }, 3462 { 0x19, 0, 0x0200 }, 3463 { 0x19, 0, 0x0020 }, 3464 { 0x1e, 0, 0x2000 }, 3465 { 0x03, 0, 0x0001 }, 3466 { 0x19, 0, 0x0100 }, 3467 { 0x19, 0, 0x0004 }, 3468 { 0x0a, 0, 0x0020 } 3469 }; 3470 3471 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3472 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3473 3474 /* Disable Early Tally Counter */ 3475 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3476 3477 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3478 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3479 3480 rtl_ephy_init(tp, e_info_8105e_1); 3481 3482 rtl_pcie_state_l2l3_disable(tp); 3483 } 3484 3485 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3486 { 3487 rtl_hw_start_8105e_1(tp); 3488 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3489 } 3490 3491 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3492 { 3493 static const struct ephy_info e_info_8402[] = { 3494 { 0x19, 0xffff, 0xff64 }, 3495 { 0x1e, 0, 0x4000 } 3496 }; 3497 3498 rtl_set_def_aspm_entry_latency(tp); 3499 3500 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3501 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3502 3503 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3504 3505 rtl_ephy_init(tp, e_info_8402); 3506 3507 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3508 rtl_reset_packet_filter(tp); 3509 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3510 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3511 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3512 3513 /* disable EEE */ 3514 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3515 3516 rtl_pcie_state_l2l3_disable(tp); 3517 } 3518 3519 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3520 { 3521 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3522 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3523 3524 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3525 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3526 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3527 3528 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3529 rtl_set_aspm_entry_latency(tp, 0x2f); 3530 3531 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3532 3533 /* disable EEE */ 3534 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3535 3536 rtl_pcie_state_l2l3_disable(tp); 3537 } 3538 3539 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3540 { 3541 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3542 } 3543 3544 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3545 { 3546 rtl_pcie_state_l2l3_disable(tp); 3547 3548 RTL_W16(tp, 0x382, 0x221b); 3549 RTL_W8(tp, 0x4500, 0); 3550 RTL_W16(tp, 0x4800, 0); 3551 3552 /* disable UPS */ 3553 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3554 3555 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3556 3557 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3558 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3559 3560 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3561 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3562 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3563 3564 /* disable new tx descriptor format */ 3565 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3566 3567 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3568 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3569 else 3570 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3571 3572 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3573 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3574 else 3575 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3576 3577 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3578 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3579 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3580 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3581 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3582 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3583 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3584 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3585 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3586 3587 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3588 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3589 udelay(1); 3590 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3591 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3592 3593 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3594 3595 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3596 3597 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3598 rtl8125b_config_eee_mac(tp); 3599 else 3600 rtl8125a_config_eee_mac(tp); 3601 3602 rtl_disable_rxdvgate(tp); 3603 } 3604 3605 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3606 { 3607 static const struct ephy_info e_info_8125a_2[] = { 3608 { 0x04, 0xffff, 0xd000 }, 3609 { 0x0a, 0xffff, 0x8653 }, 3610 { 0x23, 0xffff, 0xab66 }, 3611 { 0x20, 0xffff, 0x9455 }, 3612 { 0x21, 0xffff, 0x99ff }, 3613 { 0x29, 0xffff, 0xfe04 }, 3614 3615 { 0x44, 0xffff, 0xd000 }, 3616 { 0x4a, 0xffff, 0x8653 }, 3617 { 0x63, 0xffff, 0xab66 }, 3618 { 0x60, 0xffff, 0x9455 }, 3619 { 0x61, 0xffff, 0x99ff }, 3620 { 0x69, 0xffff, 0xfe04 }, 3621 }; 3622 3623 rtl_set_def_aspm_entry_latency(tp); 3624 rtl_ephy_init(tp, e_info_8125a_2); 3625 rtl_hw_start_8125_common(tp); 3626 } 3627 3628 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3629 { 3630 static const struct ephy_info e_info_8125b[] = { 3631 { 0x0b, 0xffff, 0xa908 }, 3632 { 0x1e, 0xffff, 0x20eb }, 3633 { 0x4b, 0xffff, 0xa908 }, 3634 { 0x5e, 0xffff, 0x20eb }, 3635 { 0x22, 0x0030, 0x0020 }, 3636 { 0x62, 0x0030, 0x0020 }, 3637 }; 3638 3639 rtl_set_def_aspm_entry_latency(tp); 3640 rtl_ephy_init(tp, e_info_8125b); 3641 rtl_hw_start_8125_common(tp); 3642 } 3643 3644 static void rtl_hw_config(struct rtl8169_private *tp) 3645 { 3646 static const rtl_generic_fct hw_configs[] = { 3647 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3648 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3649 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3650 [RTL_GIGA_MAC_VER_10] = NULL, 3651 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3652 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3653 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3654 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3655 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3656 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3657 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3658 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3659 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3660 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3661 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3662 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3663 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3664 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3665 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3666 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3667 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3668 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3669 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3670 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3671 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3672 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3673 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3674 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3675 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3676 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3677 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3678 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3679 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3680 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3681 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3682 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3683 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3684 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3685 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3686 }; 3687 3688 if (hw_configs[tp->mac_version]) 3689 hw_configs[tp->mac_version](tp); 3690 } 3691 3692 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3693 { 3694 int i; 3695 3696 /* disable interrupt coalescing */ 3697 for (i = 0xa00; i < 0xb00; i += 4) 3698 RTL_W32(tp, i, 0); 3699 3700 rtl_hw_config(tp); 3701 } 3702 3703 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3704 { 3705 if (rtl_is_8168evl_up(tp)) 3706 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3707 else 3708 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3709 3710 rtl_hw_config(tp); 3711 3712 /* disable interrupt coalescing */ 3713 RTL_W16(tp, IntrMitigate, 0x0000); 3714 } 3715 3716 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3717 { 3718 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3719 3720 tp->cp_cmd |= PCIMulRW; 3721 3722 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3723 tp->mac_version == RTL_GIGA_MAC_VER_03) 3724 tp->cp_cmd |= EnAnaPLL; 3725 3726 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3727 3728 rtl8169_set_magic_reg(tp); 3729 3730 /* disable interrupt coalescing */ 3731 RTL_W16(tp, IntrMitigate, 0x0000); 3732 } 3733 3734 static void rtl_hw_start(struct rtl8169_private *tp) 3735 { 3736 rtl_unlock_config_regs(tp); 3737 /* disable aspm and clock request before ephy access */ 3738 rtl_hw_aspm_clkreq_enable(tp, false); 3739 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3740 3741 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3742 rtl_hw_start_8169(tp); 3743 else if (rtl_is_8125(tp)) 3744 rtl_hw_start_8125(tp); 3745 else 3746 rtl_hw_start_8168(tp); 3747 3748 rtl_enable_exit_l1(tp); 3749 rtl_hw_aspm_clkreq_enable(tp, true); 3750 rtl_set_rx_max_size(tp); 3751 rtl_set_rx_tx_desc_registers(tp); 3752 rtl_lock_config_regs(tp); 3753 3754 rtl_jumbo_config(tp); 3755 3756 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3757 rtl_pci_commit(tp); 3758 3759 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3760 rtl_init_rxcfg(tp); 3761 rtl_set_tx_config_registers(tp); 3762 rtl_set_rx_config_features(tp, tp->dev->features); 3763 rtl_set_rx_mode(tp->dev); 3764 rtl_irq_enable(tp); 3765 } 3766 3767 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3768 { 3769 struct rtl8169_private *tp = netdev_priv(dev); 3770 3771 dev->mtu = new_mtu; 3772 netdev_update_features(dev); 3773 rtl_jumbo_config(tp); 3774 3775 switch (tp->mac_version) { 3776 case RTL_GIGA_MAC_VER_61: 3777 case RTL_GIGA_MAC_VER_63: 3778 rtl8125_set_eee_txidle_timer(tp); 3779 break; 3780 default: 3781 break; 3782 } 3783 3784 return 0; 3785 } 3786 3787 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3788 { 3789 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3790 3791 desc->opts2 = 0; 3792 /* Force memory writes to complete before releasing descriptor */ 3793 dma_wmb(); 3794 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3795 } 3796 3797 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3798 struct RxDesc *desc) 3799 { 3800 struct device *d = tp_to_dev(tp); 3801 int node = dev_to_node(d); 3802 dma_addr_t mapping; 3803 struct page *data; 3804 3805 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3806 if (!data) 3807 return NULL; 3808 3809 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3810 if (unlikely(dma_mapping_error(d, mapping))) { 3811 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3812 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3813 return NULL; 3814 } 3815 3816 desc->addr = cpu_to_le64(mapping); 3817 rtl8169_mark_to_asic(desc); 3818 3819 return data; 3820 } 3821 3822 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3823 { 3824 int i; 3825 3826 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3827 dma_unmap_page(tp_to_dev(tp), 3828 le64_to_cpu(tp->RxDescArray[i].addr), 3829 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3830 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3831 tp->Rx_databuff[i] = NULL; 3832 tp->RxDescArray[i].addr = 0; 3833 tp->RxDescArray[i].opts1 = 0; 3834 } 3835 } 3836 3837 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3838 { 3839 int i; 3840 3841 for (i = 0; i < NUM_RX_DESC; i++) { 3842 struct page *data; 3843 3844 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3845 if (!data) { 3846 rtl8169_rx_clear(tp); 3847 return -ENOMEM; 3848 } 3849 tp->Rx_databuff[i] = data; 3850 } 3851 3852 /* mark as last descriptor in the ring */ 3853 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3854 3855 return 0; 3856 } 3857 3858 static int rtl8169_init_ring(struct rtl8169_private *tp) 3859 { 3860 rtl8169_init_ring_indexes(tp); 3861 3862 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3863 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3864 3865 return rtl8169_rx_fill(tp); 3866 } 3867 3868 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3869 { 3870 struct ring_info *tx_skb = tp->tx_skb + entry; 3871 struct TxDesc *desc = tp->TxDescArray + entry; 3872 3873 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3874 DMA_TO_DEVICE); 3875 memset(desc, 0, sizeof(*desc)); 3876 memset(tx_skb, 0, sizeof(*tx_skb)); 3877 } 3878 3879 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3880 unsigned int n) 3881 { 3882 unsigned int i; 3883 3884 for (i = 0; i < n; i++) { 3885 unsigned int entry = (start + i) % NUM_TX_DESC; 3886 struct ring_info *tx_skb = tp->tx_skb + entry; 3887 unsigned int len = tx_skb->len; 3888 3889 if (len) { 3890 struct sk_buff *skb = tx_skb->skb; 3891 3892 rtl8169_unmap_tx_skb(tp, entry); 3893 if (skb) 3894 dev_consume_skb_any(skb); 3895 } 3896 } 3897 } 3898 3899 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3900 { 3901 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3902 netdev_reset_queue(tp->dev); 3903 } 3904 3905 static void rtl8169_cleanup(struct rtl8169_private *tp) 3906 { 3907 napi_disable(&tp->napi); 3908 3909 /* Give a racing hard_start_xmit a few cycles to complete. */ 3910 synchronize_net(); 3911 3912 /* Disable interrupts */ 3913 rtl8169_irq_mask_and_ack(tp); 3914 3915 rtl_rx_close(tp); 3916 3917 switch (tp->mac_version) { 3918 case RTL_GIGA_MAC_VER_28: 3919 case RTL_GIGA_MAC_VER_31: 3920 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3921 break; 3922 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3923 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3924 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3925 break; 3926 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3927 rtl_enable_rxdvgate(tp); 3928 fsleep(2000); 3929 break; 3930 default: 3931 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3932 fsleep(100); 3933 break; 3934 } 3935 3936 rtl_hw_reset(tp); 3937 3938 rtl8169_tx_clear(tp); 3939 rtl8169_init_ring_indexes(tp); 3940 } 3941 3942 static void rtl_reset_work(struct rtl8169_private *tp) 3943 { 3944 int i; 3945 3946 netif_stop_queue(tp->dev); 3947 3948 rtl8169_cleanup(tp); 3949 3950 for (i = 0; i < NUM_RX_DESC; i++) 3951 rtl8169_mark_to_asic(tp->RxDescArray + i); 3952 3953 napi_enable(&tp->napi); 3954 rtl_hw_start(tp); 3955 } 3956 3957 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3958 { 3959 struct rtl8169_private *tp = netdev_priv(dev); 3960 3961 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 3962 } 3963 3964 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3965 void *addr, unsigned int entry, bool desc_own) 3966 { 3967 struct TxDesc *txd = tp->TxDescArray + entry; 3968 struct device *d = tp_to_dev(tp); 3969 dma_addr_t mapping; 3970 u32 opts1; 3971 int ret; 3972 3973 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3974 ret = dma_mapping_error(d, mapping); 3975 if (unlikely(ret)) { 3976 if (net_ratelimit()) 3977 netdev_err(tp->dev, "Failed to map TX data!\n"); 3978 return ret; 3979 } 3980 3981 txd->addr = cpu_to_le64(mapping); 3982 txd->opts2 = cpu_to_le32(opts[1]); 3983 3984 opts1 = opts[0] | len; 3985 if (entry == NUM_TX_DESC - 1) 3986 opts1 |= RingEnd; 3987 if (desc_own) 3988 opts1 |= DescOwn; 3989 txd->opts1 = cpu_to_le32(opts1); 3990 3991 tp->tx_skb[entry].len = len; 3992 3993 return 0; 3994 } 3995 3996 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3997 const u32 *opts, unsigned int entry) 3998 { 3999 struct skb_shared_info *info = skb_shinfo(skb); 4000 unsigned int cur_frag; 4001 4002 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4003 const skb_frag_t *frag = info->frags + cur_frag; 4004 void *addr = skb_frag_address(frag); 4005 u32 len = skb_frag_size(frag); 4006 4007 entry = (entry + 1) % NUM_TX_DESC; 4008 4009 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4010 goto err_out; 4011 } 4012 4013 return 0; 4014 4015 err_out: 4016 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4017 return -EIO; 4018 } 4019 4020 static bool rtl_skb_is_udp(struct sk_buff *skb) 4021 { 4022 int no = skb_network_offset(skb); 4023 struct ipv6hdr *i6h, _i6h; 4024 struct iphdr *ih, _ih; 4025 4026 switch (vlan_get_protocol(skb)) { 4027 case htons(ETH_P_IP): 4028 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4029 return ih && ih->protocol == IPPROTO_UDP; 4030 case htons(ETH_P_IPV6): 4031 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4032 return i6h && i6h->nexthdr == IPPROTO_UDP; 4033 default: 4034 return false; 4035 } 4036 } 4037 4038 #define RTL_MIN_PATCH_LEN 47 4039 4040 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4041 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4042 struct sk_buff *skb) 4043 { 4044 unsigned int padto = 0, len = skb->len; 4045 4046 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4047 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4048 unsigned int trans_data_len = skb_tail_pointer(skb) - 4049 skb_transport_header(skb); 4050 4051 if (trans_data_len >= offsetof(struct udphdr, len) && 4052 trans_data_len < RTL_MIN_PATCH_LEN) { 4053 u16 dest = ntohs(udp_hdr(skb)->dest); 4054 4055 /* dest is a standard PTP port */ 4056 if (dest == 319 || dest == 320) 4057 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4058 } 4059 4060 if (trans_data_len < sizeof(struct udphdr)) 4061 padto = max_t(unsigned int, padto, 4062 len + sizeof(struct udphdr) - trans_data_len); 4063 } 4064 4065 return padto; 4066 } 4067 4068 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4069 struct sk_buff *skb) 4070 { 4071 unsigned int padto; 4072 4073 padto = rtl8125_quirk_udp_padto(tp, skb); 4074 4075 switch (tp->mac_version) { 4076 case RTL_GIGA_MAC_VER_34: 4077 case RTL_GIGA_MAC_VER_61: 4078 case RTL_GIGA_MAC_VER_63: 4079 padto = max_t(unsigned int, padto, ETH_ZLEN); 4080 break; 4081 default: 4082 break; 4083 } 4084 4085 return padto; 4086 } 4087 4088 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4089 { 4090 u32 mss = skb_shinfo(skb)->gso_size; 4091 4092 if (mss) { 4093 opts[0] |= TD_LSO; 4094 opts[0] |= mss << TD0_MSS_SHIFT; 4095 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4096 const struct iphdr *ip = ip_hdr(skb); 4097 4098 if (ip->protocol == IPPROTO_TCP) 4099 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4100 else if (ip->protocol == IPPROTO_UDP) 4101 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4102 else 4103 WARN_ON_ONCE(1); 4104 } 4105 } 4106 4107 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4108 struct sk_buff *skb, u32 *opts) 4109 { 4110 struct skb_shared_info *shinfo = skb_shinfo(skb); 4111 u32 mss = shinfo->gso_size; 4112 4113 if (mss) { 4114 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4115 opts[0] |= TD1_GTSENV4; 4116 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4117 if (skb_cow_head(skb, 0)) 4118 return false; 4119 4120 tcp_v6_gso_csum_prep(skb); 4121 opts[0] |= TD1_GTSENV6; 4122 } else { 4123 WARN_ON_ONCE(1); 4124 } 4125 4126 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4127 opts[1] |= mss << TD1_MSS_SHIFT; 4128 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4129 u8 ip_protocol; 4130 4131 switch (vlan_get_protocol(skb)) { 4132 case htons(ETH_P_IP): 4133 opts[1] |= TD1_IPv4_CS; 4134 ip_protocol = ip_hdr(skb)->protocol; 4135 break; 4136 4137 case htons(ETH_P_IPV6): 4138 opts[1] |= TD1_IPv6_CS; 4139 ip_protocol = ipv6_hdr(skb)->nexthdr; 4140 break; 4141 4142 default: 4143 ip_protocol = IPPROTO_RAW; 4144 break; 4145 } 4146 4147 if (ip_protocol == IPPROTO_TCP) 4148 opts[1] |= TD1_TCP_CS; 4149 else if (ip_protocol == IPPROTO_UDP) 4150 opts[1] |= TD1_UDP_CS; 4151 else 4152 WARN_ON_ONCE(1); 4153 4154 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4155 } else { 4156 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4157 4158 /* skb_padto would free the skb on error */ 4159 return !__skb_put_padto(skb, padto, false); 4160 } 4161 4162 return true; 4163 } 4164 4165 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4166 { 4167 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4168 - READ_ONCE(tp->cur_tx); 4169 4170 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4171 return slots_avail > MAX_SKB_FRAGS; 4172 } 4173 4174 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4175 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4176 { 4177 switch (tp->mac_version) { 4178 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4179 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4180 return false; 4181 default: 4182 return true; 4183 } 4184 } 4185 4186 static void rtl8169_doorbell(struct rtl8169_private *tp) 4187 { 4188 if (rtl_is_8125(tp)) 4189 RTL_W16(tp, TxPoll_8125, BIT(0)); 4190 else 4191 RTL_W8(tp, TxPoll, NPQ); 4192 } 4193 4194 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4195 struct net_device *dev) 4196 { 4197 unsigned int frags = skb_shinfo(skb)->nr_frags; 4198 struct rtl8169_private *tp = netdev_priv(dev); 4199 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4200 struct TxDesc *txd_first, *txd_last; 4201 bool stop_queue, door_bell; 4202 u32 opts[2]; 4203 4204 if (unlikely(!rtl_tx_slots_avail(tp))) { 4205 if (net_ratelimit()) 4206 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4207 goto err_stop_0; 4208 } 4209 4210 opts[1] = rtl8169_tx_vlan_tag(skb); 4211 opts[0] = 0; 4212 4213 if (!rtl_chip_supports_csum_v2(tp)) 4214 rtl8169_tso_csum_v1(skb, opts); 4215 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4216 goto err_dma_0; 4217 4218 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4219 entry, false))) 4220 goto err_dma_0; 4221 4222 txd_first = tp->TxDescArray + entry; 4223 4224 if (frags) { 4225 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4226 goto err_dma_1; 4227 entry = (entry + frags) % NUM_TX_DESC; 4228 } 4229 4230 txd_last = tp->TxDescArray + entry; 4231 txd_last->opts1 |= cpu_to_le32(LastFrag); 4232 tp->tx_skb[entry].skb = skb; 4233 4234 skb_tx_timestamp(skb); 4235 4236 /* Force memory writes to complete before releasing descriptor */ 4237 dma_wmb(); 4238 4239 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4240 4241 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4242 4243 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4244 smp_wmb(); 4245 4246 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4247 4248 stop_queue = !rtl_tx_slots_avail(tp); 4249 if (unlikely(stop_queue)) { 4250 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4251 * not miss a ring update when it notices a stopped queue. 4252 */ 4253 smp_wmb(); 4254 netif_stop_queue(dev); 4255 /* Sync with rtl_tx: 4256 * - publish queue status and cur_tx ring index (write barrier) 4257 * - refresh dirty_tx ring index (read barrier). 4258 * May the current thread have a pessimistic view of the ring 4259 * status and forget to wake up queue, a racing rtl_tx thread 4260 * can't. 4261 */ 4262 smp_mb__after_atomic(); 4263 if (rtl_tx_slots_avail(tp)) 4264 netif_start_queue(dev); 4265 door_bell = true; 4266 } 4267 4268 if (door_bell) 4269 rtl8169_doorbell(tp); 4270 4271 return NETDEV_TX_OK; 4272 4273 err_dma_1: 4274 rtl8169_unmap_tx_skb(tp, entry); 4275 err_dma_0: 4276 dev_kfree_skb_any(skb); 4277 dev->stats.tx_dropped++; 4278 return NETDEV_TX_OK; 4279 4280 err_stop_0: 4281 netif_stop_queue(dev); 4282 dev->stats.tx_dropped++; 4283 return NETDEV_TX_BUSY; 4284 } 4285 4286 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4287 { 4288 struct skb_shared_info *info = skb_shinfo(skb); 4289 unsigned int nr_frags = info->nr_frags; 4290 4291 if (!nr_frags) 4292 return UINT_MAX; 4293 4294 return skb_frag_size(info->frags + nr_frags - 1); 4295 } 4296 4297 /* Workaround for hw issues with TSO on RTL8168evl */ 4298 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4299 netdev_features_t features) 4300 { 4301 /* IPv4 header has options field */ 4302 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4303 ip_hdrlen(skb) > sizeof(struct iphdr)) 4304 features &= ~NETIF_F_ALL_TSO; 4305 4306 /* IPv4 TCP header has options field */ 4307 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4308 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4309 features &= ~NETIF_F_ALL_TSO; 4310 4311 else if (rtl_last_frag_len(skb) <= 6) 4312 features &= ~NETIF_F_ALL_TSO; 4313 4314 return features; 4315 } 4316 4317 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4318 struct net_device *dev, 4319 netdev_features_t features) 4320 { 4321 struct rtl8169_private *tp = netdev_priv(dev); 4322 4323 if (skb_is_gso(skb)) { 4324 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4325 features = rtl8168evl_fix_tso(skb, features); 4326 4327 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4328 rtl_chip_supports_csum_v2(tp)) 4329 features &= ~NETIF_F_ALL_TSO; 4330 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4331 /* work around hw bug on some chip versions */ 4332 if (skb->len < ETH_ZLEN) 4333 features &= ~NETIF_F_CSUM_MASK; 4334 4335 if (rtl_quirk_packet_padto(tp, skb)) 4336 features &= ~NETIF_F_CSUM_MASK; 4337 4338 if (skb_transport_offset(skb) > TCPHO_MAX && 4339 rtl_chip_supports_csum_v2(tp)) 4340 features &= ~NETIF_F_CSUM_MASK; 4341 } 4342 4343 return vlan_features_check(skb, features); 4344 } 4345 4346 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4347 { 4348 struct rtl8169_private *tp = netdev_priv(dev); 4349 struct pci_dev *pdev = tp->pci_dev; 4350 int pci_status_errs; 4351 u16 pci_cmd; 4352 4353 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4354 4355 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4356 4357 if (net_ratelimit()) 4358 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4359 pci_cmd, pci_status_errs); 4360 4361 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4362 } 4363 4364 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4365 int budget) 4366 { 4367 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4368 struct sk_buff *skb; 4369 4370 dirty_tx = tp->dirty_tx; 4371 4372 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4373 unsigned int entry = dirty_tx % NUM_TX_DESC; 4374 u32 status; 4375 4376 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4377 if (status & DescOwn) 4378 break; 4379 4380 skb = tp->tx_skb[entry].skb; 4381 rtl8169_unmap_tx_skb(tp, entry); 4382 4383 if (skb) { 4384 pkts_compl++; 4385 bytes_compl += skb->len; 4386 napi_consume_skb(skb, budget); 4387 } 4388 dirty_tx++; 4389 } 4390 4391 if (tp->dirty_tx != dirty_tx) { 4392 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4393 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4394 4395 /* Sync with rtl8169_start_xmit: 4396 * - publish dirty_tx ring index (write barrier) 4397 * - refresh cur_tx ring index and queue status (read barrier) 4398 * May the current thread miss the stopped queue condition, 4399 * a racing xmit thread can only have a right view of the 4400 * ring status. 4401 */ 4402 smp_store_mb(tp->dirty_tx, dirty_tx); 4403 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4404 netif_wake_queue(dev); 4405 /* 4406 * 8168 hack: TxPoll requests are lost when the Tx packets are 4407 * too close. Let's kick an extra TxPoll request when a burst 4408 * of start_xmit activity is detected (if it is not detected, 4409 * it is slow enough). -- FR 4410 * If skb is NULL then we come here again once a tx irq is 4411 * triggered after the last fragment is marked transmitted. 4412 */ 4413 if (tp->cur_tx != dirty_tx && skb) 4414 rtl8169_doorbell(tp); 4415 } 4416 } 4417 4418 static inline int rtl8169_fragmented_frame(u32 status) 4419 { 4420 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4421 } 4422 4423 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4424 { 4425 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4426 4427 if (status == RxProtoTCP || status == RxProtoUDP) 4428 skb->ip_summed = CHECKSUM_UNNECESSARY; 4429 else 4430 skb_checksum_none_assert(skb); 4431 } 4432 4433 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4434 { 4435 struct device *d = tp_to_dev(tp); 4436 int count; 4437 4438 for (count = 0; count < budget; count++, tp->cur_rx++) { 4439 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4440 struct RxDesc *desc = tp->RxDescArray + entry; 4441 struct sk_buff *skb; 4442 const void *rx_buf; 4443 dma_addr_t addr; 4444 u32 status; 4445 4446 status = le32_to_cpu(desc->opts1); 4447 if (status & DescOwn) 4448 break; 4449 4450 /* This barrier is needed to keep us from reading 4451 * any other fields out of the Rx descriptor until 4452 * we know the status of DescOwn 4453 */ 4454 dma_rmb(); 4455 4456 if (unlikely(status & RxRES)) { 4457 if (net_ratelimit()) 4458 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4459 status); 4460 dev->stats.rx_errors++; 4461 if (status & (RxRWT | RxRUNT)) 4462 dev->stats.rx_length_errors++; 4463 if (status & RxCRC) 4464 dev->stats.rx_crc_errors++; 4465 4466 if (!(dev->features & NETIF_F_RXALL)) 4467 goto release_descriptor; 4468 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4469 goto release_descriptor; 4470 } 4471 4472 pkt_size = status & GENMASK(13, 0); 4473 if (likely(!(dev->features & NETIF_F_RXFCS))) 4474 pkt_size -= ETH_FCS_LEN; 4475 4476 /* The driver does not support incoming fragmented frames. 4477 * They are seen as a symptom of over-mtu sized frames. 4478 */ 4479 if (unlikely(rtl8169_fragmented_frame(status))) { 4480 dev->stats.rx_dropped++; 4481 dev->stats.rx_length_errors++; 4482 goto release_descriptor; 4483 } 4484 4485 skb = napi_alloc_skb(&tp->napi, pkt_size); 4486 if (unlikely(!skb)) { 4487 dev->stats.rx_dropped++; 4488 goto release_descriptor; 4489 } 4490 4491 addr = le64_to_cpu(desc->addr); 4492 rx_buf = page_address(tp->Rx_databuff[entry]); 4493 4494 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4495 prefetch(rx_buf); 4496 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4497 skb->tail += pkt_size; 4498 skb->len = pkt_size; 4499 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4500 4501 rtl8169_rx_csum(skb, status); 4502 skb->protocol = eth_type_trans(skb, dev); 4503 4504 rtl8169_rx_vlan_tag(desc, skb); 4505 4506 if (skb->pkt_type == PACKET_MULTICAST) 4507 dev->stats.multicast++; 4508 4509 napi_gro_receive(&tp->napi, skb); 4510 4511 dev_sw_netstats_rx_add(dev, pkt_size); 4512 release_descriptor: 4513 rtl8169_mark_to_asic(desc); 4514 } 4515 4516 return count; 4517 } 4518 4519 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4520 { 4521 struct rtl8169_private *tp = dev_instance; 4522 u32 status = rtl_get_events(tp); 4523 4524 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4525 return IRQ_NONE; 4526 4527 if (unlikely(status & SYSErr)) { 4528 rtl8169_pcierr_interrupt(tp->dev); 4529 goto out; 4530 } 4531 4532 if (status & LinkChg) 4533 phy_mac_interrupt(tp->phydev); 4534 4535 if (unlikely(status & RxFIFOOver && 4536 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4537 netif_stop_queue(tp->dev); 4538 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4539 } 4540 4541 if (napi_schedule_prep(&tp->napi)) { 4542 rtl_unlock_config_regs(tp); 4543 rtl_hw_aspm_clkreq_enable(tp, false); 4544 rtl_lock_config_regs(tp); 4545 4546 rtl_irq_disable(tp); 4547 __napi_schedule(&tp->napi); 4548 } 4549 out: 4550 rtl_ack_events(tp, status); 4551 4552 return IRQ_HANDLED; 4553 } 4554 4555 static void rtl_task(struct work_struct *work) 4556 { 4557 struct rtl8169_private *tp = 4558 container_of(work, struct rtl8169_private, wk.work); 4559 int ret; 4560 4561 rtnl_lock(); 4562 4563 if (!netif_running(tp->dev) || 4564 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4565 goto out_unlock; 4566 4567 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4568 /* if chip isn't accessible, reset bus to revive it */ 4569 if (RTL_R32(tp, TxConfig) == ~0) { 4570 ret = pci_reset_bus(tp->pci_dev); 4571 if (ret < 0) { 4572 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4573 netif_device_detach(tp->dev); 4574 goto out_unlock; 4575 } 4576 } 4577 4578 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4579 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4580 PCIE_LINK_STATE_L0S); 4581 if (!ret) 4582 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4583 goto reset; 4584 } 4585 4586 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4587 reset: 4588 rtl_reset_work(tp); 4589 netif_wake_queue(tp->dev); 4590 } 4591 out_unlock: 4592 rtnl_unlock(); 4593 } 4594 4595 static int rtl8169_poll(struct napi_struct *napi, int budget) 4596 { 4597 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4598 struct net_device *dev = tp->dev; 4599 int work_done; 4600 4601 rtl_tx(dev, tp, budget); 4602 4603 work_done = rtl_rx(dev, tp, budget); 4604 4605 if (work_done < budget && napi_complete_done(napi, work_done)) { 4606 rtl_irq_enable(tp); 4607 4608 rtl_unlock_config_regs(tp); 4609 rtl_hw_aspm_clkreq_enable(tp, true); 4610 rtl_lock_config_regs(tp); 4611 } 4612 4613 return work_done; 4614 } 4615 4616 static void r8169_phylink_handler(struct net_device *ndev) 4617 { 4618 struct rtl8169_private *tp = netdev_priv(ndev); 4619 struct device *d = tp_to_dev(tp); 4620 4621 if (netif_carrier_ok(ndev)) { 4622 rtl_link_chg_patch(tp); 4623 pm_request_resume(d); 4624 } else { 4625 pm_runtime_idle(d); 4626 } 4627 4628 phy_print_status(tp->phydev); 4629 } 4630 4631 static int r8169_phy_connect(struct rtl8169_private *tp) 4632 { 4633 struct phy_device *phydev = tp->phydev; 4634 phy_interface_t phy_mode; 4635 int ret; 4636 4637 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4638 PHY_INTERFACE_MODE_MII; 4639 4640 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4641 phy_mode); 4642 if (ret) 4643 return ret; 4644 4645 if (!tp->supports_gmii) 4646 phy_set_max_speed(phydev, SPEED_100); 4647 4648 phy_attached_info(phydev); 4649 4650 return 0; 4651 } 4652 4653 static void rtl8169_down(struct rtl8169_private *tp) 4654 { 4655 /* Clear all task flags */ 4656 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4657 4658 phy_stop(tp->phydev); 4659 4660 rtl8169_update_counters(tp); 4661 4662 pci_clear_master(tp->pci_dev); 4663 rtl_pci_commit(tp); 4664 4665 rtl8169_cleanup(tp); 4666 rtl_disable_exit_l1(tp); 4667 rtl_prepare_power_down(tp); 4668 } 4669 4670 static void rtl8169_up(struct rtl8169_private *tp) 4671 { 4672 pci_set_master(tp->pci_dev); 4673 phy_init_hw(tp->phydev); 4674 phy_resume(tp->phydev); 4675 rtl8169_init_phy(tp); 4676 napi_enable(&tp->napi); 4677 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4678 rtl_reset_work(tp); 4679 4680 phy_start(tp->phydev); 4681 } 4682 4683 static int rtl8169_close(struct net_device *dev) 4684 { 4685 struct rtl8169_private *tp = netdev_priv(dev); 4686 struct pci_dev *pdev = tp->pci_dev; 4687 4688 pm_runtime_get_sync(&pdev->dev); 4689 4690 netif_stop_queue(dev); 4691 rtl8169_down(tp); 4692 rtl8169_rx_clear(tp); 4693 4694 cancel_work_sync(&tp->wk.work); 4695 4696 free_irq(tp->irq, tp); 4697 4698 phy_disconnect(tp->phydev); 4699 4700 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4701 tp->RxPhyAddr); 4702 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4703 tp->TxPhyAddr); 4704 tp->TxDescArray = NULL; 4705 tp->RxDescArray = NULL; 4706 4707 pm_runtime_put_sync(&pdev->dev); 4708 4709 return 0; 4710 } 4711 4712 #ifdef CONFIG_NET_POLL_CONTROLLER 4713 static void rtl8169_netpoll(struct net_device *dev) 4714 { 4715 struct rtl8169_private *tp = netdev_priv(dev); 4716 4717 rtl8169_interrupt(tp->irq, tp); 4718 } 4719 #endif 4720 4721 static int rtl_open(struct net_device *dev) 4722 { 4723 struct rtl8169_private *tp = netdev_priv(dev); 4724 struct pci_dev *pdev = tp->pci_dev; 4725 unsigned long irqflags; 4726 int retval = -ENOMEM; 4727 4728 pm_runtime_get_sync(&pdev->dev); 4729 4730 /* 4731 * Rx and Tx descriptors needs 256 bytes alignment. 4732 * dma_alloc_coherent provides more. 4733 */ 4734 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4735 &tp->TxPhyAddr, GFP_KERNEL); 4736 if (!tp->TxDescArray) 4737 goto out; 4738 4739 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4740 &tp->RxPhyAddr, GFP_KERNEL); 4741 if (!tp->RxDescArray) 4742 goto err_free_tx_0; 4743 4744 retval = rtl8169_init_ring(tp); 4745 if (retval < 0) 4746 goto err_free_rx_1; 4747 4748 rtl_request_firmware(tp); 4749 4750 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4751 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4752 if (retval < 0) 4753 goto err_release_fw_2; 4754 4755 retval = r8169_phy_connect(tp); 4756 if (retval) 4757 goto err_free_irq; 4758 4759 rtl8169_up(tp); 4760 rtl8169_init_counter_offsets(tp); 4761 netif_start_queue(dev); 4762 out: 4763 pm_runtime_put_sync(&pdev->dev); 4764 4765 return retval; 4766 4767 err_free_irq: 4768 free_irq(tp->irq, tp); 4769 err_release_fw_2: 4770 rtl_release_firmware(tp); 4771 rtl8169_rx_clear(tp); 4772 err_free_rx_1: 4773 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4774 tp->RxPhyAddr); 4775 tp->RxDescArray = NULL; 4776 err_free_tx_0: 4777 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4778 tp->TxPhyAddr); 4779 tp->TxDescArray = NULL; 4780 goto out; 4781 } 4782 4783 static void 4784 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4785 { 4786 struct rtl8169_private *tp = netdev_priv(dev); 4787 struct pci_dev *pdev = tp->pci_dev; 4788 struct rtl8169_counters *counters = tp->counters; 4789 4790 pm_runtime_get_noresume(&pdev->dev); 4791 4792 netdev_stats_to_stats64(stats, &dev->stats); 4793 dev_fetch_sw_netstats(stats, dev->tstats); 4794 4795 /* 4796 * Fetch additional counter values missing in stats collected by driver 4797 * from tally counters. 4798 */ 4799 if (pm_runtime_active(&pdev->dev)) 4800 rtl8169_update_counters(tp); 4801 4802 /* 4803 * Subtract values fetched during initalization. 4804 * See rtl8169_init_counter_offsets for a description why we do that. 4805 */ 4806 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4807 le64_to_cpu(tp->tc_offset.tx_errors); 4808 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4809 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4810 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4811 le16_to_cpu(tp->tc_offset.tx_aborted); 4812 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4813 le16_to_cpu(tp->tc_offset.rx_missed); 4814 4815 pm_runtime_put_noidle(&pdev->dev); 4816 } 4817 4818 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4819 { 4820 netif_device_detach(tp->dev); 4821 4822 if (netif_running(tp->dev)) 4823 rtl8169_down(tp); 4824 } 4825 4826 static int rtl8169_runtime_resume(struct device *dev) 4827 { 4828 struct rtl8169_private *tp = dev_get_drvdata(dev); 4829 4830 rtl_rar_set(tp, tp->dev->dev_addr); 4831 __rtl8169_set_wol(tp, tp->saved_wolopts); 4832 4833 if (tp->TxDescArray) 4834 rtl8169_up(tp); 4835 4836 netif_device_attach(tp->dev); 4837 4838 return 0; 4839 } 4840 4841 static int rtl8169_suspend(struct device *device) 4842 { 4843 struct rtl8169_private *tp = dev_get_drvdata(device); 4844 4845 rtnl_lock(); 4846 rtl8169_net_suspend(tp); 4847 if (!device_may_wakeup(tp_to_dev(tp))) 4848 clk_disable_unprepare(tp->clk); 4849 rtnl_unlock(); 4850 4851 return 0; 4852 } 4853 4854 static int rtl8169_resume(struct device *device) 4855 { 4856 struct rtl8169_private *tp = dev_get_drvdata(device); 4857 4858 if (!device_may_wakeup(tp_to_dev(tp))) 4859 clk_prepare_enable(tp->clk); 4860 4861 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4862 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4863 rtl_init_rxcfg(tp); 4864 4865 return rtl8169_runtime_resume(device); 4866 } 4867 4868 static int rtl8169_runtime_suspend(struct device *device) 4869 { 4870 struct rtl8169_private *tp = dev_get_drvdata(device); 4871 4872 if (!tp->TxDescArray) { 4873 netif_device_detach(tp->dev); 4874 return 0; 4875 } 4876 4877 rtnl_lock(); 4878 __rtl8169_set_wol(tp, WAKE_PHY); 4879 rtl8169_net_suspend(tp); 4880 rtnl_unlock(); 4881 4882 return 0; 4883 } 4884 4885 static int rtl8169_runtime_idle(struct device *device) 4886 { 4887 struct rtl8169_private *tp = dev_get_drvdata(device); 4888 4889 if (tp->dash_type != RTL_DASH_NONE) 4890 return -EBUSY; 4891 4892 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4893 pm_schedule_suspend(device, 10000); 4894 4895 return -EBUSY; 4896 } 4897 4898 static const struct dev_pm_ops rtl8169_pm_ops = { 4899 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4900 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4901 rtl8169_runtime_idle) 4902 }; 4903 4904 static void rtl_shutdown(struct pci_dev *pdev) 4905 { 4906 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4907 4908 rtnl_lock(); 4909 rtl8169_net_suspend(tp); 4910 rtnl_unlock(); 4911 4912 /* Restore original MAC address */ 4913 rtl_rar_set(tp, tp->dev->perm_addr); 4914 4915 if (system_state == SYSTEM_POWER_OFF && 4916 tp->dash_type == RTL_DASH_NONE) { 4917 pci_wake_from_d3(pdev, tp->saved_wolopts); 4918 pci_set_power_state(pdev, PCI_D3hot); 4919 } 4920 } 4921 4922 static void rtl_remove_one(struct pci_dev *pdev) 4923 { 4924 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4925 4926 if (pci_dev_run_wake(pdev)) 4927 pm_runtime_get_noresume(&pdev->dev); 4928 4929 unregister_netdev(tp->dev); 4930 4931 if (tp->dash_type != RTL_DASH_NONE) 4932 rtl8168_driver_stop(tp); 4933 4934 rtl_release_firmware(tp); 4935 4936 /* restore original MAC address */ 4937 rtl_rar_set(tp, tp->dev->perm_addr); 4938 } 4939 4940 static const struct net_device_ops rtl_netdev_ops = { 4941 .ndo_open = rtl_open, 4942 .ndo_stop = rtl8169_close, 4943 .ndo_get_stats64 = rtl8169_get_stats64, 4944 .ndo_start_xmit = rtl8169_start_xmit, 4945 .ndo_features_check = rtl8169_features_check, 4946 .ndo_tx_timeout = rtl8169_tx_timeout, 4947 .ndo_validate_addr = eth_validate_addr, 4948 .ndo_change_mtu = rtl8169_change_mtu, 4949 .ndo_fix_features = rtl8169_fix_features, 4950 .ndo_set_features = rtl8169_set_features, 4951 .ndo_set_mac_address = rtl_set_mac_address, 4952 .ndo_eth_ioctl = phy_do_ioctl_running, 4953 .ndo_set_rx_mode = rtl_set_rx_mode, 4954 #ifdef CONFIG_NET_POLL_CONTROLLER 4955 .ndo_poll_controller = rtl8169_netpoll, 4956 #endif 4957 4958 }; 4959 4960 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4961 { 4962 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4963 4964 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4965 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4966 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4967 /* special workaround needed */ 4968 tp->irq_mask |= RxFIFOOver; 4969 else 4970 tp->irq_mask |= RxOverflow; 4971 } 4972 4973 static int rtl_alloc_irq(struct rtl8169_private *tp) 4974 { 4975 unsigned int flags; 4976 4977 switch (tp->mac_version) { 4978 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4979 rtl_unlock_config_regs(tp); 4980 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4981 rtl_lock_config_regs(tp); 4982 fallthrough; 4983 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4984 flags = PCI_IRQ_LEGACY; 4985 break; 4986 default: 4987 flags = PCI_IRQ_ALL_TYPES; 4988 break; 4989 } 4990 4991 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4992 } 4993 4994 static void rtl_read_mac_address(struct rtl8169_private *tp, 4995 u8 mac_addr[ETH_ALEN]) 4996 { 4997 /* Get MAC address */ 4998 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 4999 u32 value; 5000 5001 value = rtl_eri_read(tp, 0xe0); 5002 put_unaligned_le32(value, mac_addr); 5003 value = rtl_eri_read(tp, 0xe4); 5004 put_unaligned_le16(value, mac_addr + 4); 5005 } else if (rtl_is_8125(tp)) { 5006 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5007 } 5008 } 5009 5010 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5011 { 5012 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5013 } 5014 5015 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5016 { 5017 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5018 } 5019 5020 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5021 { 5022 struct rtl8169_private *tp = mii_bus->priv; 5023 5024 if (phyaddr > 0) 5025 return -ENODEV; 5026 5027 return rtl_readphy(tp, phyreg); 5028 } 5029 5030 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5031 int phyreg, u16 val) 5032 { 5033 struct rtl8169_private *tp = mii_bus->priv; 5034 5035 if (phyaddr > 0) 5036 return -ENODEV; 5037 5038 rtl_writephy(tp, phyreg, val); 5039 5040 return 0; 5041 } 5042 5043 static int r8169_mdio_register(struct rtl8169_private *tp) 5044 { 5045 struct pci_dev *pdev = tp->pci_dev; 5046 struct mii_bus *new_bus; 5047 int ret; 5048 5049 new_bus = devm_mdiobus_alloc(&pdev->dev); 5050 if (!new_bus) 5051 return -ENOMEM; 5052 5053 new_bus->name = "r8169"; 5054 new_bus->priv = tp; 5055 new_bus->parent = &pdev->dev; 5056 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5057 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5058 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5059 5060 new_bus->read = r8169_mdio_read_reg; 5061 new_bus->write = r8169_mdio_write_reg; 5062 5063 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5064 if (ret) 5065 return ret; 5066 5067 tp->phydev = mdiobus_get_phy(new_bus, 0); 5068 if (!tp->phydev) { 5069 return -ENODEV; 5070 } else if (!tp->phydev->drv) { 5071 /* Most chip versions fail with the genphy driver. 5072 * Therefore ensure that the dedicated PHY driver is loaded. 5073 */ 5074 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5075 tp->phydev->phy_id); 5076 return -EUNATCH; 5077 } 5078 5079 tp->phydev->mac_managed_pm = true; 5080 5081 phy_support_asym_pause(tp->phydev); 5082 5083 /* PHY will be woken up in rtl_open() */ 5084 phy_suspend(tp->phydev); 5085 5086 return 0; 5087 } 5088 5089 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5090 { 5091 rtl_enable_rxdvgate(tp); 5092 5093 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5094 msleep(1); 5095 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5096 5097 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5098 r8168g_wait_ll_share_fifo_ready(tp); 5099 5100 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5101 r8168g_wait_ll_share_fifo_ready(tp); 5102 } 5103 5104 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5105 { 5106 rtl_enable_rxdvgate(tp); 5107 5108 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5109 msleep(1); 5110 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5111 5112 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5113 r8168g_wait_ll_share_fifo_ready(tp); 5114 5115 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5116 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5117 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5118 r8168g_wait_ll_share_fifo_ready(tp); 5119 } 5120 5121 static void rtl_hw_initialize(struct rtl8169_private *tp) 5122 { 5123 switch (tp->mac_version) { 5124 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5125 rtl8168ep_stop_cmac(tp); 5126 fallthrough; 5127 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5128 rtl_hw_init_8168g(tp); 5129 break; 5130 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5131 rtl_hw_init_8125(tp); 5132 break; 5133 default: 5134 break; 5135 } 5136 } 5137 5138 static int rtl_jumbo_max(struct rtl8169_private *tp) 5139 { 5140 /* Non-GBit versions don't support jumbo frames */ 5141 if (!tp->supports_gmii) 5142 return 0; 5143 5144 switch (tp->mac_version) { 5145 /* RTL8169 */ 5146 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5147 return JUMBO_7K; 5148 /* RTL8168b */ 5149 case RTL_GIGA_MAC_VER_11: 5150 case RTL_GIGA_MAC_VER_17: 5151 return JUMBO_4K; 5152 /* RTL8168c */ 5153 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5154 return JUMBO_6K; 5155 default: 5156 return JUMBO_9K; 5157 } 5158 } 5159 5160 static void rtl_init_mac_address(struct rtl8169_private *tp) 5161 { 5162 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5163 struct net_device *dev = tp->dev; 5164 int rc; 5165 5166 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5167 if (!rc) 5168 goto done; 5169 5170 rtl_read_mac_address(tp, mac_addr); 5171 if (is_valid_ether_addr(mac_addr)) 5172 goto done; 5173 5174 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5175 if (is_valid_ether_addr(mac_addr)) 5176 goto done; 5177 5178 eth_random_addr(mac_addr); 5179 dev->addr_assign_type = NET_ADDR_RANDOM; 5180 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5181 done: 5182 eth_hw_addr_set(dev, mac_addr); 5183 rtl_rar_set(tp, mac_addr); 5184 } 5185 5186 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5187 { 5188 struct rtl8169_private *tp; 5189 int jumbo_max, region, rc; 5190 enum mac_version chipset; 5191 struct net_device *dev; 5192 u16 xid; 5193 5194 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5195 if (!dev) 5196 return -ENOMEM; 5197 5198 SET_NETDEV_DEV(dev, &pdev->dev); 5199 dev->netdev_ops = &rtl_netdev_ops; 5200 tp = netdev_priv(dev); 5201 tp->dev = dev; 5202 tp->pci_dev = pdev; 5203 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5204 tp->eee_adv = -1; 5205 tp->ocp_base = OCP_STD_PHY_BASE; 5206 5207 spin_lock_init(&tp->cfg9346_usage_lock); 5208 spin_lock_init(&tp->config25_lock); 5209 spin_lock_init(&tp->mac_ocp_lock); 5210 5211 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5212 struct pcpu_sw_netstats); 5213 if (!dev->tstats) 5214 return -ENOMEM; 5215 5216 /* Get the *optional* external "ether_clk" used on some boards */ 5217 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5218 if (IS_ERR(tp->clk)) 5219 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5220 5221 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5222 rc = pcim_enable_device(pdev); 5223 if (rc < 0) { 5224 dev_err(&pdev->dev, "enable failure\n"); 5225 return rc; 5226 } 5227 5228 if (pcim_set_mwi(pdev) < 0) 5229 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5230 5231 /* use first MMIO region */ 5232 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5233 if (region < 0) { 5234 dev_err(&pdev->dev, "no MMIO resource found\n"); 5235 return -ENODEV; 5236 } 5237 5238 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5239 if (rc < 0) { 5240 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5241 return rc; 5242 } 5243 5244 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5245 5246 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5247 5248 /* Identify chip attached to board */ 5249 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5250 if (chipset == RTL_GIGA_MAC_NONE) { 5251 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5252 return -ENODEV; 5253 } 5254 5255 tp->mac_version = chipset; 5256 5257 tp->dash_type = rtl_check_dash(tp); 5258 5259 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5260 5261 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5262 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5263 dev->features |= NETIF_F_HIGHDMA; 5264 5265 rtl_init_rxcfg(tp); 5266 5267 rtl8169_irq_mask_and_ack(tp); 5268 5269 rtl_hw_initialize(tp); 5270 5271 rtl_hw_reset(tp); 5272 5273 rc = rtl_alloc_irq(tp); 5274 if (rc < 0) { 5275 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5276 return rc; 5277 } 5278 tp->irq = pci_irq_vector(pdev, 0); 5279 5280 INIT_WORK(&tp->wk.work, rtl_task); 5281 5282 rtl_init_mac_address(tp); 5283 5284 dev->ethtool_ops = &rtl8169_ethtool_ops; 5285 5286 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5287 5288 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5289 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5290 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5291 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5292 5293 /* 5294 * Pretend we are using VLANs; This bypasses a nasty bug where 5295 * Interrupts stop flowing on high load on 8110SCd controllers. 5296 */ 5297 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5298 /* Disallow toggling */ 5299 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5300 5301 if (rtl_chip_supports_csum_v2(tp)) 5302 dev->hw_features |= NETIF_F_IPV6_CSUM; 5303 5304 dev->features |= dev->hw_features; 5305 5306 /* There has been a number of reports that using SG/TSO results in 5307 * tx timeouts. However for a lot of people SG/TSO works fine. 5308 * Therefore disable both features by default, but allow users to 5309 * enable them. Use at own risk! 5310 */ 5311 if (rtl_chip_supports_csum_v2(tp)) { 5312 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5313 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5314 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5315 } else { 5316 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5317 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5318 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5319 } 5320 5321 dev->hw_features |= NETIF_F_RXALL; 5322 dev->hw_features |= NETIF_F_RXFCS; 5323 5324 netdev_sw_irq_coalesce_default_on(dev); 5325 5326 /* configure chip for default features */ 5327 rtl8169_set_features(dev, dev->features); 5328 5329 if (tp->dash_type == RTL_DASH_NONE) { 5330 rtl_set_d3_pll_down(tp, true); 5331 } else { 5332 rtl_set_d3_pll_down(tp, false); 5333 dev->wol_enabled = 1; 5334 } 5335 5336 jumbo_max = rtl_jumbo_max(tp); 5337 if (jumbo_max) 5338 dev->max_mtu = jumbo_max; 5339 5340 rtl_set_irq_mask(tp); 5341 5342 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5343 5344 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5345 &tp->counters_phys_addr, 5346 GFP_KERNEL); 5347 if (!tp->counters) 5348 return -ENOMEM; 5349 5350 pci_set_drvdata(pdev, tp); 5351 5352 rc = r8169_mdio_register(tp); 5353 if (rc) 5354 return rc; 5355 5356 rc = register_netdev(dev); 5357 if (rc) 5358 return rc; 5359 5360 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5361 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5362 5363 if (jumbo_max) 5364 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5365 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5366 "ok" : "ko"); 5367 5368 if (tp->dash_type != RTL_DASH_NONE) { 5369 netdev_info(dev, "DASH enabled\n"); 5370 rtl8168_driver_start(tp); 5371 } 5372 5373 if (pci_dev_run_wake(pdev)) 5374 pm_runtime_put_sync(&pdev->dev); 5375 5376 return 0; 5377 } 5378 5379 static struct pci_driver rtl8169_pci_driver = { 5380 .name = KBUILD_MODNAME, 5381 .id_table = rtl8169_pci_tbl, 5382 .probe = rtl_init_one, 5383 .remove = rtl_remove_one, 5384 .shutdown = rtl_shutdown, 5385 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5386 }; 5387 5388 module_pci_driver(rtl8169_pci_driver); 5389