1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 59 60 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 61 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 62 63 #define R8169_REGS_SIZE 256 64 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 65 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 66 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 67 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 68 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 69 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 70 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 71 72 #define OCP_STD_PHY_BASE 0xa400 73 74 #define RTL_CFG_NO_GBIT 1 75 76 /* write/read MMIO register */ 77 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 81 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 82 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 83 84 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 89 static const struct { 90 const char *name; 91 const char *fw_name; 92 } rtl_chip_infos[] = { 93 /* PCI devices. */ 94 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 95 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 96 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 97 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 98 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 99 /* PCI-E devices. */ 100 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 102 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 103 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 104 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 105 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 106 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 108 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 109 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 115 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 116 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 117 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 118 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 119 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 121 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 122 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 123 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 124 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 125 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 126 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 127 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 128 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 129 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 130 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 131 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 132 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 133 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 134 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 135 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 136 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 137 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 138 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 139 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 140 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 141 }; 142 143 static const struct pci_device_id rtl8169_pci_tbl[] = { 144 { PCI_VDEVICE(REALTEK, 0x2502) }, 145 { PCI_VDEVICE(REALTEK, 0x2600) }, 146 { PCI_VDEVICE(REALTEK, 0x8129) }, 147 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 148 { PCI_VDEVICE(REALTEK, 0x8161) }, 149 { PCI_VDEVICE(REALTEK, 0x8162) }, 150 { PCI_VDEVICE(REALTEK, 0x8167) }, 151 { PCI_VDEVICE(REALTEK, 0x8168) }, 152 { PCI_VDEVICE(NCUBE, 0x8168) }, 153 { PCI_VDEVICE(REALTEK, 0x8169) }, 154 { PCI_VENDOR_ID_DLINK, 0x4300, 155 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 156 { PCI_VDEVICE(DLINK, 0x4300) }, 157 { PCI_VDEVICE(DLINK, 0x4302) }, 158 { PCI_VDEVICE(AT, 0xc107) }, 159 { PCI_VDEVICE(USR, 0x0116) }, 160 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 161 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 162 { PCI_VDEVICE(REALTEK, 0x8125) }, 163 { PCI_VDEVICE(REALTEK, 0x8126) }, 164 { PCI_VDEVICE(REALTEK, 0x3000) }, 165 {} 166 }; 167 168 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 169 170 enum rtl_registers { 171 MAC0 = 0, /* Ethernet hardware address. */ 172 MAC4 = 4, 173 MAR0 = 8, /* Multicast filter. */ 174 CounterAddrLow = 0x10, 175 CounterAddrHigh = 0x14, 176 TxDescStartAddrLow = 0x20, 177 TxDescStartAddrHigh = 0x24, 178 TxHDescStartAddrLow = 0x28, 179 TxHDescStartAddrHigh = 0x2c, 180 FLASH = 0x30, 181 ERSR = 0x36, 182 ChipCmd = 0x37, 183 TxPoll = 0x38, 184 IntrMask = 0x3c, 185 IntrStatus = 0x3e, 186 187 TxConfig = 0x40, 188 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 189 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 190 191 RxConfig = 0x44, 192 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 193 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 194 #define RXCFG_FIFO_SHIFT 13 195 /* No threshold before first PCI xfer */ 196 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 197 #define RX_EARLY_OFF (1 << 11) 198 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 199 #define RXCFG_DMA_SHIFT 8 200 /* Unlimited maximum PCI burst. */ 201 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 202 203 Cfg9346 = 0x50, 204 Config0 = 0x51, 205 Config1 = 0x52, 206 Config2 = 0x53, 207 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 208 209 Config3 = 0x54, 210 Config4 = 0x55, 211 Config5 = 0x56, 212 PHYAR = 0x60, 213 PHYstatus = 0x6c, 214 RxMaxSize = 0xda, 215 CPlusCmd = 0xe0, 216 IntrMitigate = 0xe2, 217 218 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 219 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 220 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 221 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 222 223 #define RTL_COALESCE_T_MAX 0x0fU 224 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 225 226 RxDescAddrLow = 0xe4, 227 RxDescAddrHigh = 0xe8, 228 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 229 230 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 231 232 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 233 234 #define TxPacketMax (8064 >> 7) 235 #define EarlySize 0x27 236 237 FuncEvent = 0xf0, 238 FuncEventMask = 0xf4, 239 FuncPresetState = 0xf8, 240 IBCR0 = 0xf8, 241 IBCR2 = 0xf9, 242 IBIMR0 = 0xfa, 243 IBISR0 = 0xfb, 244 FuncForceEvent = 0xfc, 245 }; 246 247 enum rtl8168_8101_registers { 248 CSIDR = 0x64, 249 CSIAR = 0x68, 250 #define CSIAR_FLAG 0x80000000 251 #define CSIAR_WRITE_CMD 0x80000000 252 #define CSIAR_BYTE_ENABLE 0x0000f000 253 #define CSIAR_ADDR_MASK 0x00000fff 254 PMCH = 0x6f, 255 #define D3COLD_NO_PLL_DOWN BIT(7) 256 #define D3HOT_NO_PLL_DOWN BIT(6) 257 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 258 EPHYAR = 0x80, 259 #define EPHYAR_FLAG 0x80000000 260 #define EPHYAR_WRITE_CMD 0x80000000 261 #define EPHYAR_REG_MASK 0x1f 262 #define EPHYAR_REG_SHIFT 16 263 #define EPHYAR_DATA_MASK 0xffff 264 DLLPR = 0xd0, 265 #define PFM_EN (1 << 6) 266 #define TX_10M_PS_EN (1 << 7) 267 DBG_REG = 0xd1, 268 #define FIX_NAK_1 (1 << 4) 269 #define FIX_NAK_2 (1 << 3) 270 TWSI = 0xd2, 271 MCU = 0xd3, 272 #define NOW_IS_OOB (1 << 7) 273 #define TX_EMPTY (1 << 5) 274 #define RX_EMPTY (1 << 4) 275 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 276 #define EN_NDP (1 << 3) 277 #define EN_OOB_RESET (1 << 2) 278 #define LINK_LIST_RDY (1 << 1) 279 EFUSEAR = 0xdc, 280 #define EFUSEAR_FLAG 0x80000000 281 #define EFUSEAR_WRITE_CMD 0x80000000 282 #define EFUSEAR_READ_CMD 0x00000000 283 #define EFUSEAR_REG_MASK 0x03ff 284 #define EFUSEAR_REG_SHIFT 8 285 #define EFUSEAR_DATA_MASK 0xff 286 MISC_1 = 0xf2, 287 #define PFM_D3COLD_EN (1 << 6) 288 }; 289 290 enum rtl8168_registers { 291 LED_CTRL = 0x18, 292 LED_FREQ = 0x1a, 293 EEE_LED = 0x1b, 294 ERIDR = 0x70, 295 ERIAR = 0x74, 296 #define ERIAR_FLAG 0x80000000 297 #define ERIAR_WRITE_CMD 0x80000000 298 #define ERIAR_READ_CMD 0x00000000 299 #define ERIAR_ADDR_BYTE_ALIGN 4 300 #define ERIAR_TYPE_SHIFT 16 301 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 303 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_MASK_SHIFT 12 306 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 308 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 311 EPHY_RXER_NUM = 0x7c, 312 OCPDR = 0xb0, /* OCP GPHY access */ 313 #define OCPDR_WRITE_CMD 0x80000000 314 #define OCPDR_READ_CMD 0x00000000 315 #define OCPDR_REG_MASK 0x7f 316 #define OCPDR_GPHY_REG_SHIFT 16 317 #define OCPDR_DATA_MASK 0xffff 318 OCPAR = 0xb4, 319 #define OCPAR_FLAG 0x80000000 320 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 321 #define OCPAR_GPHY_READ_CMD 0x0000f060 322 GPHY_OCP = 0xb8, 323 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 324 MISC = 0xf0, /* 8168e only. */ 325 #define TXPLA_RST (1 << 29) 326 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 327 #define PWM_EN (1 << 22) 328 #define RXDV_GATED_EN (1 << 19) 329 #define EARLY_TALLY_EN (1 << 16) 330 }; 331 332 enum rtl8125_registers { 333 LEDSEL0 = 0x18, 334 INT_CFG0_8125 = 0x34, 335 #define INT_CFG0_ENABLE_8125 BIT(0) 336 #define INT_CFG0_CLKREQEN BIT(3) 337 IntrMask_8125 = 0x38, 338 IntrStatus_8125 = 0x3c, 339 INT_CFG1_8125 = 0x7a, 340 LEDSEL2 = 0x84, 341 LEDSEL1 = 0x86, 342 TxPoll_8125 = 0x90, 343 LEDSEL3 = 0x96, 344 MAC0_BKP = 0x19e0, 345 EEE_TXIDLE_TIMER_8125 = 0x6048, 346 }; 347 348 #define LEDSEL_MASK_8125 0x23f 349 350 #define RX_VLAN_INNER_8125 BIT(22) 351 #define RX_VLAN_OUTER_8125 BIT(23) 352 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 353 354 #define RX_FETCH_DFLT_8125 (8 << 27) 355 356 enum rtl_register_content { 357 /* InterruptStatusBits */ 358 SYSErr = 0x8000, 359 PCSTimeout = 0x4000, 360 SWInt = 0x0100, 361 TxDescUnavail = 0x0080, 362 RxFIFOOver = 0x0040, 363 LinkChg = 0x0020, 364 RxOverflow = 0x0010, 365 TxErr = 0x0008, 366 TxOK = 0x0004, 367 RxErr = 0x0002, 368 RxOK = 0x0001, 369 370 /* RxStatusDesc */ 371 RxRWT = (1 << 22), 372 RxRES = (1 << 21), 373 RxRUNT = (1 << 20), 374 RxCRC = (1 << 19), 375 376 /* ChipCmdBits */ 377 StopReq = 0x80, 378 CmdReset = 0x10, 379 CmdRxEnb = 0x08, 380 CmdTxEnb = 0x04, 381 RxBufEmpty = 0x01, 382 383 /* TXPoll register p.5 */ 384 HPQ = 0x80, /* Poll cmd on the high prio queue */ 385 NPQ = 0x40, /* Poll cmd on the low prio queue */ 386 FSWInt = 0x01, /* Forced software interrupt */ 387 388 /* Cfg9346Bits */ 389 Cfg9346_Lock = 0x00, 390 Cfg9346_Unlock = 0xc0, 391 392 /* rx_mode_bits */ 393 AcceptErr = 0x20, 394 AcceptRunt = 0x10, 395 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 396 AcceptBroadcast = 0x08, 397 AcceptMulticast = 0x04, 398 AcceptMyPhys = 0x02, 399 AcceptAllPhys = 0x01, 400 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 401 #define RX_CONFIG_ACCEPT_MASK 0x3f 402 403 /* TxConfigBits */ 404 TxInterFrameGapShift = 24, 405 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 406 407 /* Config1 register p.24 */ 408 LEDS1 = (1 << 7), 409 LEDS0 = (1 << 6), 410 Speed_down = (1 << 4), 411 MEMMAP = (1 << 3), 412 IOMAP = (1 << 2), 413 VPD = (1 << 1), 414 PMEnable = (1 << 0), /* Power Management Enable */ 415 416 /* Config2 register p. 25 */ 417 ClkReqEn = (1 << 7), /* Clock Request Enable */ 418 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 419 PCI_Clock_66MHz = 0x01, 420 PCI_Clock_33MHz = 0x00, 421 422 /* Config3 register p.25 */ 423 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 424 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 425 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 426 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 427 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 428 429 /* Config4 register */ 430 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 431 432 /* Config5 register p.27 */ 433 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 434 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 435 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 436 Spi_en = (1 << 3), 437 LanWake = (1 << 1), /* LanWake enable/disable */ 438 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 439 ASPM_en = (1 << 0), /* ASPM enable */ 440 441 /* CPlusCmd p.31 */ 442 EnableBist = (1 << 15), // 8168 8101 443 Mac_dbgo_oe = (1 << 14), // 8168 8101 444 EnAnaPLL = (1 << 14), // 8169 445 Normal_mode = (1 << 13), // unused 446 Force_half_dup = (1 << 12), // 8168 8101 447 Force_rxflow_en = (1 << 11), // 8168 8101 448 Force_txflow_en = (1 << 10), // 8168 8101 449 Cxpl_dbg_sel = (1 << 9), // 8168 8101 450 ASF = (1 << 8), // 8168 8101 451 PktCntrDisable = (1 << 7), // 8168 8101 452 Mac_dbgo_sel = 0x001c, // 8168 453 RxVlan = (1 << 6), 454 RxChkSum = (1 << 5), 455 PCIDAC = (1 << 4), 456 PCIMulRW = (1 << 3), 457 #define INTT_MASK GENMASK(1, 0) 458 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 459 460 /* rtl8169_PHYstatus */ 461 TBI_Enable = 0x80, 462 TxFlowCtrl = 0x40, 463 RxFlowCtrl = 0x20, 464 _1000bpsF = 0x10, 465 _100bps = 0x08, 466 _10bps = 0x04, 467 LinkStatus = 0x02, 468 FullDup = 0x01, 469 470 /* ResetCounterCommand */ 471 CounterReset = 0x1, 472 473 /* DumpCounterCommand */ 474 CounterDump = 0x8, 475 476 /* magic enable v2 */ 477 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 478 }; 479 480 enum rtl_desc_bit { 481 /* First doubleword. */ 482 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 483 RingEnd = (1 << 30), /* End of descriptor ring */ 484 FirstFrag = (1 << 29), /* First segment of a packet */ 485 LastFrag = (1 << 28), /* Final segment of a packet */ 486 }; 487 488 /* Generic case. */ 489 enum rtl_tx_desc_bit { 490 /* First doubleword. */ 491 TD_LSO = (1 << 27), /* Large Send Offload */ 492 #define TD_MSS_MAX 0x07ffu /* MSS value */ 493 494 /* Second doubleword. */ 495 TxVlanTag = (1 << 17), /* Add VLAN tag */ 496 }; 497 498 /* 8169, 8168b and 810x except 8102e. */ 499 enum rtl_tx_desc_bit_0 { 500 /* First doubleword. */ 501 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 502 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 503 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 504 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 505 }; 506 507 /* 8102e, 8168c and beyond. */ 508 enum rtl_tx_desc_bit_1 { 509 /* First doubleword. */ 510 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 511 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 512 #define GTTCPHO_SHIFT 18 513 #define GTTCPHO_MAX 0x7f 514 515 /* Second doubleword. */ 516 #define TCPHO_SHIFT 18 517 #define TCPHO_MAX 0x3ff 518 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 519 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 520 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 521 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 522 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 523 }; 524 525 enum rtl_rx_desc_bit { 526 /* Rx private */ 527 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 528 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 529 530 #define RxProtoUDP (PID1) 531 #define RxProtoTCP (PID0) 532 #define RxProtoIP (PID1 | PID0) 533 #define RxProtoMask RxProtoIP 534 535 IPFail = (1 << 16), /* IP checksum failed */ 536 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 537 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 538 539 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 540 541 RxVlanTag = (1 << 16), /* VLAN tag available */ 542 }; 543 544 #define RTL_GSO_MAX_SIZE_V1 32000 545 #define RTL_GSO_MAX_SEGS_V1 24 546 #define RTL_GSO_MAX_SIZE_V2 64000 547 #define RTL_GSO_MAX_SEGS_V2 64 548 549 struct TxDesc { 550 __le32 opts1; 551 __le32 opts2; 552 __le64 addr; 553 }; 554 555 struct RxDesc { 556 __le32 opts1; 557 __le32 opts2; 558 __le64 addr; 559 }; 560 561 struct ring_info { 562 struct sk_buff *skb; 563 u32 len; 564 }; 565 566 struct rtl8169_counters { 567 __le64 tx_packets; 568 __le64 rx_packets; 569 __le64 tx_errors; 570 __le32 rx_errors; 571 __le16 rx_missed; 572 __le16 align_errors; 573 __le32 tx_one_collision; 574 __le32 tx_multi_collision; 575 __le64 rx_unicast; 576 __le64 rx_broadcast; 577 __le32 rx_multicast; 578 __le16 tx_aborted; 579 __le16 tx_underun; 580 }; 581 582 struct rtl8169_tc_offsets { 583 bool inited; 584 __le64 tx_errors; 585 __le32 tx_multi_collision; 586 __le16 tx_aborted; 587 __le16 rx_missed; 588 }; 589 590 enum rtl_flag { 591 RTL_FLAG_TASK_ENABLED = 0, 592 RTL_FLAG_TASK_RESET_PENDING, 593 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 594 RTL_FLAG_TASK_TX_TIMEOUT, 595 RTL_FLAG_MAX 596 }; 597 598 enum rtl_dash_type { 599 RTL_DASH_NONE, 600 RTL_DASH_DP, 601 RTL_DASH_EP, 602 }; 603 604 struct rtl8169_private { 605 void __iomem *mmio_addr; /* memory map physical address */ 606 struct pci_dev *pci_dev; 607 struct net_device *dev; 608 struct phy_device *phydev; 609 struct napi_struct napi; 610 enum mac_version mac_version; 611 enum rtl_dash_type dash_type; 612 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 613 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 614 u32 dirty_tx; 615 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 616 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 617 dma_addr_t TxPhyAddr; 618 dma_addr_t RxPhyAddr; 619 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 620 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 621 u16 cp_cmd; 622 u16 tx_lpi_timer; 623 u32 irq_mask; 624 int irq; 625 struct clk *clk; 626 627 struct { 628 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 629 struct work_struct work; 630 } wk; 631 632 raw_spinlock_t config25_lock; 633 raw_spinlock_t mac_ocp_lock; 634 struct mutex led_lock; /* serialize LED ctrl RMW access */ 635 636 raw_spinlock_t cfg9346_usage_lock; 637 int cfg9346_usage_count; 638 639 unsigned supports_gmii:1; 640 unsigned aspm_manageable:1; 641 unsigned dash_enabled:1; 642 dma_addr_t counters_phys_addr; 643 struct rtl8169_counters *counters; 644 struct rtl8169_tc_offsets tc_offset; 645 u32 saved_wolopts; 646 647 const char *fw_name; 648 struct rtl_fw *rtl_fw; 649 650 u32 ocp_base; 651 }; 652 653 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 654 655 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 656 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 657 MODULE_SOFTDEP("pre: realtek"); 658 MODULE_LICENSE("GPL"); 659 MODULE_FIRMWARE(FIRMWARE_8168D_1); 660 MODULE_FIRMWARE(FIRMWARE_8168D_2); 661 MODULE_FIRMWARE(FIRMWARE_8168E_1); 662 MODULE_FIRMWARE(FIRMWARE_8168E_2); 663 MODULE_FIRMWARE(FIRMWARE_8168E_3); 664 MODULE_FIRMWARE(FIRMWARE_8105E_1); 665 MODULE_FIRMWARE(FIRMWARE_8168F_1); 666 MODULE_FIRMWARE(FIRMWARE_8168F_2); 667 MODULE_FIRMWARE(FIRMWARE_8402_1); 668 MODULE_FIRMWARE(FIRMWARE_8411_1); 669 MODULE_FIRMWARE(FIRMWARE_8411_2); 670 MODULE_FIRMWARE(FIRMWARE_8106E_1); 671 MODULE_FIRMWARE(FIRMWARE_8106E_2); 672 MODULE_FIRMWARE(FIRMWARE_8168G_2); 673 MODULE_FIRMWARE(FIRMWARE_8168G_3); 674 MODULE_FIRMWARE(FIRMWARE_8168H_2); 675 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 676 MODULE_FIRMWARE(FIRMWARE_8107E_2); 677 MODULE_FIRMWARE(FIRMWARE_8125A_3); 678 MODULE_FIRMWARE(FIRMWARE_8125B_2); 679 MODULE_FIRMWARE(FIRMWARE_8126A_2); 680 681 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 682 { 683 return &tp->pci_dev->dev; 684 } 685 686 static void rtl_lock_config_regs(struct rtl8169_private *tp) 687 { 688 unsigned long flags; 689 690 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 691 if (!--tp->cfg9346_usage_count) 692 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 693 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 694 } 695 696 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 697 { 698 unsigned long flags; 699 700 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 701 if (!tp->cfg9346_usage_count++) 702 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 703 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 704 } 705 706 static void rtl_pci_commit(struct rtl8169_private *tp) 707 { 708 /* Read an arbitrary register to commit a preceding PCI write */ 709 RTL_R8(tp, ChipCmd); 710 } 711 712 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 713 { 714 unsigned long flags; 715 u8 val; 716 717 raw_spin_lock_irqsave(&tp->config25_lock, flags); 718 val = RTL_R8(tp, Config2); 719 RTL_W8(tp, Config2, (val & ~clear) | set); 720 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 721 } 722 723 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 724 { 725 unsigned long flags; 726 u8 val; 727 728 raw_spin_lock_irqsave(&tp->config25_lock, flags); 729 val = RTL_R8(tp, Config5); 730 RTL_W8(tp, Config5, (val & ~clear) | set); 731 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 732 } 733 734 static bool rtl_is_8125(struct rtl8169_private *tp) 735 { 736 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 737 } 738 739 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 740 { 741 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 742 tp->mac_version != RTL_GIGA_MAC_VER_39 && 743 tp->mac_version <= RTL_GIGA_MAC_VER_53; 744 } 745 746 static bool rtl_supports_eee(struct rtl8169_private *tp) 747 { 748 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 749 tp->mac_version != RTL_GIGA_MAC_VER_37 && 750 tp->mac_version != RTL_GIGA_MAC_VER_39; 751 } 752 753 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 754 { 755 int i; 756 757 for (i = 0; i < ETH_ALEN; i++) 758 mac[i] = RTL_R8(tp, reg + i); 759 } 760 761 struct rtl_cond { 762 bool (*check)(struct rtl8169_private *); 763 const char *msg; 764 }; 765 766 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 767 unsigned long usecs, int n, bool high) 768 { 769 int i; 770 771 for (i = 0; i < n; i++) { 772 if (c->check(tp) == high) 773 return true; 774 fsleep(usecs); 775 } 776 777 if (net_ratelimit()) 778 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 779 c->msg, !high, n, usecs); 780 return false; 781 } 782 783 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 784 const struct rtl_cond *c, 785 unsigned long d, int n) 786 { 787 return rtl_loop_wait(tp, c, d, n, true); 788 } 789 790 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 791 const struct rtl_cond *c, 792 unsigned long d, int n) 793 { 794 return rtl_loop_wait(tp, c, d, n, false); 795 } 796 797 #define DECLARE_RTL_COND(name) \ 798 static bool name ## _check(struct rtl8169_private *); \ 799 \ 800 static const struct rtl_cond name = { \ 801 .check = name ## _check, \ 802 .msg = #name \ 803 }; \ 804 \ 805 static bool name ## _check(struct rtl8169_private *tp) 806 807 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 808 { 809 struct device *dev = tp_to_dev(tp); 810 int ret; 811 812 ret = pm_runtime_resume_and_get(dev); 813 if (ret < 0) 814 return ret; 815 816 mutex_lock(&tp->led_lock); 817 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 818 mutex_unlock(&tp->led_lock); 819 820 pm_runtime_put_sync(dev); 821 822 return 0; 823 } 824 825 int rtl8168_get_led_mode(struct rtl8169_private *tp) 826 { 827 struct device *dev = tp_to_dev(tp); 828 int ret; 829 830 ret = pm_runtime_resume_and_get(dev); 831 if (ret < 0) 832 return ret; 833 834 ret = RTL_R16(tp, LED_CTRL); 835 836 pm_runtime_put_sync(dev); 837 838 return ret; 839 } 840 841 static int rtl8125_get_led_reg(int index) 842 { 843 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 844 845 return led_regs[index]; 846 } 847 848 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 849 { 850 int reg = rtl8125_get_led_reg(index); 851 struct device *dev = tp_to_dev(tp); 852 int ret; 853 u16 val; 854 855 ret = pm_runtime_resume_and_get(dev); 856 if (ret < 0) 857 return ret; 858 859 mutex_lock(&tp->led_lock); 860 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 861 RTL_W16(tp, reg, val | mode); 862 mutex_unlock(&tp->led_lock); 863 864 pm_runtime_put_sync(dev); 865 866 return 0; 867 } 868 869 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 870 { 871 int reg = rtl8125_get_led_reg(index); 872 struct device *dev = tp_to_dev(tp); 873 int ret; 874 875 ret = pm_runtime_resume_and_get(dev); 876 if (ret < 0) 877 return ret; 878 879 ret = RTL_R16(tp, reg); 880 881 pm_runtime_put_sync(dev); 882 883 return ret; 884 } 885 886 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 887 char *buf, int buf_len) 888 { 889 struct pci_dev *pdev = tp->pci_dev; 890 char pdom[8], pfun[8]; 891 int domain; 892 893 domain = pci_domain_nr(pdev->bus); 894 if (domain) 895 snprintf(pdom, sizeof(pdom), "P%d", domain); 896 else 897 pdom[0] = '\0'; 898 899 if (pdev->multifunction) 900 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 901 else 902 pfun[0] = '\0'; 903 904 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 905 PCI_SLOT(pdev->devfn), pfun, idx); 906 } 907 908 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 909 { 910 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 911 if (type == ERIAR_OOB && 912 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 913 tp->mac_version == RTL_GIGA_MAC_VER_53)) 914 *cmd |= 0xf70 << 18; 915 } 916 917 DECLARE_RTL_COND(rtl_eriar_cond) 918 { 919 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 920 } 921 922 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 923 u32 val, int type) 924 { 925 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 926 927 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 928 return; 929 930 RTL_W32(tp, ERIDR, val); 931 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 932 RTL_W32(tp, ERIAR, cmd); 933 934 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 935 } 936 937 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 938 u32 val) 939 { 940 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 941 } 942 943 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 944 { 945 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 946 947 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 948 RTL_W32(tp, ERIAR, cmd); 949 950 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 951 RTL_R32(tp, ERIDR) : ~0; 952 } 953 954 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 955 { 956 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 957 } 958 959 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 960 { 961 u32 val = rtl_eri_read(tp, addr); 962 963 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 964 } 965 966 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 967 { 968 rtl_w0w1_eri(tp, addr, p, 0); 969 } 970 971 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 972 { 973 rtl_w0w1_eri(tp, addr, 0, m); 974 } 975 976 static bool rtl_ocp_reg_failure(u32 reg) 977 { 978 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 979 } 980 981 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 982 { 983 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 984 } 985 986 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 987 { 988 if (rtl_ocp_reg_failure(reg)) 989 return; 990 991 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 992 993 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 994 } 995 996 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 997 { 998 if (rtl_ocp_reg_failure(reg)) 999 return 0; 1000 1001 RTL_W32(tp, GPHY_OCP, reg << 15); 1002 1003 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1004 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1005 } 1006 1007 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1008 { 1009 if (rtl_ocp_reg_failure(reg)) 1010 return; 1011 1012 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1013 } 1014 1015 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1016 { 1017 unsigned long flags; 1018 1019 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1020 __r8168_mac_ocp_write(tp, reg, data); 1021 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1022 } 1023 1024 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1025 { 1026 if (rtl_ocp_reg_failure(reg)) 1027 return 0; 1028 1029 RTL_W32(tp, OCPDR, reg << 15); 1030 1031 return RTL_R32(tp, OCPDR); 1032 } 1033 1034 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1035 { 1036 unsigned long flags; 1037 u16 val; 1038 1039 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1040 val = __r8168_mac_ocp_read(tp, reg); 1041 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1042 1043 return val; 1044 } 1045 1046 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1047 u16 set) 1048 { 1049 unsigned long flags; 1050 u16 data; 1051 1052 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1053 data = __r8168_mac_ocp_read(tp, reg); 1054 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1055 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1056 } 1057 1058 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1059 * PHY MCU interrupts before PHY power-down. 1060 */ 1061 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1062 { 1063 switch (tp->mac_version) { 1064 case RTL_GIGA_MAC_VER_40: 1065 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1066 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1067 else 1068 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1069 break; 1070 default: 1071 break; 1072 } 1073 }; 1074 1075 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1076 { 1077 if (reg == 0x1f) { 1078 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1079 return; 1080 } 1081 1082 if (tp->ocp_base != OCP_STD_PHY_BASE) 1083 reg -= 0x10; 1084 1085 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1086 rtl8168g_phy_suspend_quirk(tp, value); 1087 1088 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1089 } 1090 1091 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1092 { 1093 if (reg == 0x1f) 1094 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1095 1096 if (tp->ocp_base != OCP_STD_PHY_BASE) 1097 reg -= 0x10; 1098 1099 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1100 } 1101 1102 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1103 { 1104 if (reg == 0x1f) { 1105 tp->ocp_base = value << 4; 1106 return; 1107 } 1108 1109 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1110 } 1111 1112 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1113 { 1114 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1115 } 1116 1117 DECLARE_RTL_COND(rtl_phyar_cond) 1118 { 1119 return RTL_R32(tp, PHYAR) & 0x80000000; 1120 } 1121 1122 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1123 { 1124 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1125 1126 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1127 /* 1128 * According to hardware specs a 20us delay is required after write 1129 * complete indication, but before sending next command. 1130 */ 1131 udelay(20); 1132 } 1133 1134 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1135 { 1136 int value; 1137 1138 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1139 1140 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1141 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1142 1143 /* 1144 * According to hardware specs a 20us delay is required after read 1145 * complete indication, but before sending next command. 1146 */ 1147 udelay(20); 1148 1149 return value; 1150 } 1151 1152 DECLARE_RTL_COND(rtl_ocpar_cond) 1153 { 1154 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1155 } 1156 1157 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1158 1159 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1160 { 1161 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1162 } 1163 1164 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1165 { 1166 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1167 } 1168 1169 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1170 { 1171 r8168dp_2_mdio_start(tp); 1172 1173 r8169_mdio_write(tp, reg, value); 1174 1175 r8168dp_2_mdio_stop(tp); 1176 } 1177 1178 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1179 { 1180 int value; 1181 1182 /* Work around issue with chip reporting wrong PHY ID */ 1183 if (reg == MII_PHYSID2) 1184 return 0xc912; 1185 1186 r8168dp_2_mdio_start(tp); 1187 1188 value = r8169_mdio_read(tp, reg); 1189 1190 r8168dp_2_mdio_stop(tp); 1191 1192 return value; 1193 } 1194 1195 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1196 { 1197 switch (tp->mac_version) { 1198 case RTL_GIGA_MAC_VER_28: 1199 case RTL_GIGA_MAC_VER_31: 1200 r8168dp_2_mdio_write(tp, location, val); 1201 break; 1202 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 1203 r8168g_mdio_write(tp, location, val); 1204 break; 1205 default: 1206 r8169_mdio_write(tp, location, val); 1207 break; 1208 } 1209 } 1210 1211 static int rtl_readphy(struct rtl8169_private *tp, int location) 1212 { 1213 switch (tp->mac_version) { 1214 case RTL_GIGA_MAC_VER_28: 1215 case RTL_GIGA_MAC_VER_31: 1216 return r8168dp_2_mdio_read(tp, location); 1217 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 1218 return r8168g_mdio_read(tp, location); 1219 default: 1220 return r8169_mdio_read(tp, location); 1221 } 1222 } 1223 1224 DECLARE_RTL_COND(rtl_ephyar_cond) 1225 { 1226 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1227 } 1228 1229 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1230 { 1231 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1232 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1233 1234 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1235 1236 udelay(10); 1237 } 1238 1239 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1240 { 1241 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1242 1243 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1244 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1245 } 1246 1247 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1248 { 1249 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1250 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1251 RTL_R32(tp, OCPDR) : ~0; 1252 } 1253 1254 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1255 { 1256 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1257 } 1258 1259 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1260 u32 data) 1261 { 1262 RTL_W32(tp, OCPDR, data); 1263 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1264 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1265 } 1266 1267 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1268 u32 data) 1269 { 1270 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1271 data, ERIAR_OOB); 1272 } 1273 1274 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1275 { 1276 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1277 1278 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1279 } 1280 1281 #define OOB_CMD_RESET 0x00 1282 #define OOB_CMD_DRIVER_START 0x05 1283 #define OOB_CMD_DRIVER_STOP 0x06 1284 1285 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1286 { 1287 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1288 } 1289 1290 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1291 { 1292 u16 reg; 1293 1294 reg = rtl8168_get_ocp_reg(tp); 1295 1296 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1297 } 1298 1299 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1300 { 1301 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1302 } 1303 1304 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1305 { 1306 return RTL_R8(tp, IBISR0) & 0x20; 1307 } 1308 1309 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1310 { 1311 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1312 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1313 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1314 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1315 } 1316 1317 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1318 { 1319 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1320 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1321 } 1322 1323 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1324 { 1325 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1326 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1327 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1328 } 1329 1330 static void rtl8168_driver_start(struct rtl8169_private *tp) 1331 { 1332 if (tp->dash_type == RTL_DASH_DP) 1333 rtl8168dp_driver_start(tp); 1334 else 1335 rtl8168ep_driver_start(tp); 1336 } 1337 1338 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1339 { 1340 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1341 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1342 } 1343 1344 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1345 { 1346 rtl8168ep_stop_cmac(tp); 1347 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1348 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1349 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1350 } 1351 1352 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1353 { 1354 if (tp->dash_type == RTL_DASH_DP) 1355 rtl8168dp_driver_stop(tp); 1356 else 1357 rtl8168ep_driver_stop(tp); 1358 } 1359 1360 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1361 { 1362 u16 reg = rtl8168_get_ocp_reg(tp); 1363 1364 return r8168dp_ocp_read(tp, reg) & BIT(15); 1365 } 1366 1367 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1368 { 1369 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1370 } 1371 1372 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1373 { 1374 switch (tp->dash_type) { 1375 case RTL_DASH_DP: 1376 return r8168dp_check_dash(tp); 1377 case RTL_DASH_EP: 1378 return r8168ep_check_dash(tp); 1379 default: 1380 return false; 1381 } 1382 } 1383 1384 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1385 { 1386 switch (tp->mac_version) { 1387 case RTL_GIGA_MAC_VER_28: 1388 case RTL_GIGA_MAC_VER_31: 1389 return RTL_DASH_DP; 1390 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1391 return RTL_DASH_EP; 1392 default: 1393 return RTL_DASH_NONE; 1394 } 1395 } 1396 1397 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1398 { 1399 switch (tp->mac_version) { 1400 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1401 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1402 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1403 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65: 1404 if (enable) 1405 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1406 else 1407 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1408 break; 1409 default: 1410 break; 1411 } 1412 } 1413 1414 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1415 { 1416 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1417 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1418 } 1419 1420 DECLARE_RTL_COND(rtl_efusear_cond) 1421 { 1422 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1423 } 1424 1425 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1426 { 1427 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1428 1429 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1430 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1431 } 1432 1433 static u32 rtl_get_events(struct rtl8169_private *tp) 1434 { 1435 if (rtl_is_8125(tp)) 1436 return RTL_R32(tp, IntrStatus_8125); 1437 else 1438 return RTL_R16(tp, IntrStatus); 1439 } 1440 1441 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1442 { 1443 if (rtl_is_8125(tp)) 1444 RTL_W32(tp, IntrStatus_8125, bits); 1445 else 1446 RTL_W16(tp, IntrStatus, bits); 1447 } 1448 1449 static void rtl_irq_disable(struct rtl8169_private *tp) 1450 { 1451 if (rtl_is_8125(tp)) 1452 RTL_W32(tp, IntrMask_8125, 0); 1453 else 1454 RTL_W16(tp, IntrMask, 0); 1455 } 1456 1457 static void rtl_irq_enable(struct rtl8169_private *tp) 1458 { 1459 if (rtl_is_8125(tp)) 1460 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1461 else 1462 RTL_W16(tp, IntrMask, tp->irq_mask); 1463 } 1464 1465 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1466 { 1467 rtl_irq_disable(tp); 1468 rtl_ack_events(tp, 0xffffffff); 1469 rtl_pci_commit(tp); 1470 } 1471 1472 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1473 { 1474 struct phy_device *phydev = tp->phydev; 1475 1476 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1477 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1478 if (phydev->speed == SPEED_1000) { 1479 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1480 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1481 } else if (phydev->speed == SPEED_100) { 1482 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1483 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1484 } else { 1485 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1486 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1487 } 1488 rtl_reset_packet_filter(tp); 1489 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1490 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1491 if (phydev->speed == SPEED_1000) { 1492 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1493 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1494 } else { 1495 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1496 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1497 } 1498 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1499 if (phydev->speed == SPEED_10) { 1500 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1501 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1502 } else { 1503 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1504 } 1505 } 1506 } 1507 1508 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1509 1510 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1511 { 1512 struct rtl8169_private *tp = netdev_priv(dev); 1513 1514 wol->supported = WAKE_ANY; 1515 wol->wolopts = tp->saved_wolopts; 1516 } 1517 1518 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1519 { 1520 static const struct { 1521 u32 opt; 1522 u16 reg; 1523 u8 mask; 1524 } cfg[] = { 1525 { WAKE_PHY, Config3, LinkUp }, 1526 { WAKE_UCAST, Config5, UWF }, 1527 { WAKE_BCAST, Config5, BWF }, 1528 { WAKE_MCAST, Config5, MWF }, 1529 { WAKE_ANY, Config5, LanWake }, 1530 { WAKE_MAGIC, Config3, MagicPacket } 1531 }; 1532 unsigned int i, tmp = ARRAY_SIZE(cfg); 1533 unsigned long flags; 1534 u8 options; 1535 1536 rtl_unlock_config_regs(tp); 1537 1538 if (rtl_is_8168evl_up(tp)) { 1539 tmp--; 1540 if (wolopts & WAKE_MAGIC) 1541 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1542 else 1543 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1544 } else if (rtl_is_8125(tp)) { 1545 tmp--; 1546 if (wolopts & WAKE_MAGIC) 1547 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1548 else 1549 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1550 } 1551 1552 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1553 for (i = 0; i < tmp; i++) { 1554 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1555 if (wolopts & cfg[i].opt) 1556 options |= cfg[i].mask; 1557 RTL_W8(tp, cfg[i].reg, options); 1558 } 1559 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1560 1561 switch (tp->mac_version) { 1562 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1563 options = RTL_R8(tp, Config1) & ~PMEnable; 1564 if (wolopts) 1565 options |= PMEnable; 1566 RTL_W8(tp, Config1, options); 1567 break; 1568 case RTL_GIGA_MAC_VER_34: 1569 case RTL_GIGA_MAC_VER_37: 1570 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65: 1571 if (wolopts) 1572 rtl_mod_config2(tp, 0, PME_SIGNAL); 1573 else 1574 rtl_mod_config2(tp, PME_SIGNAL, 0); 1575 break; 1576 default: 1577 break; 1578 } 1579 1580 rtl_lock_config_regs(tp); 1581 1582 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1583 1584 if (!tp->dash_enabled) { 1585 rtl_set_d3_pll_down(tp, !wolopts); 1586 tp->dev->wol_enabled = wolopts ? 1 : 0; 1587 } 1588 } 1589 1590 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1591 { 1592 struct rtl8169_private *tp = netdev_priv(dev); 1593 1594 if (wol->wolopts & ~WAKE_ANY) 1595 return -EINVAL; 1596 1597 tp->saved_wolopts = wol->wolopts; 1598 __rtl8169_set_wol(tp, tp->saved_wolopts); 1599 1600 return 0; 1601 } 1602 1603 static void rtl8169_get_drvinfo(struct net_device *dev, 1604 struct ethtool_drvinfo *info) 1605 { 1606 struct rtl8169_private *tp = netdev_priv(dev); 1607 struct rtl_fw *rtl_fw = tp->rtl_fw; 1608 1609 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1610 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1611 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1612 if (rtl_fw) 1613 strscpy(info->fw_version, rtl_fw->version, 1614 sizeof(info->fw_version)); 1615 } 1616 1617 static int rtl8169_get_regs_len(struct net_device *dev) 1618 { 1619 return R8169_REGS_SIZE; 1620 } 1621 1622 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1623 netdev_features_t features) 1624 { 1625 struct rtl8169_private *tp = netdev_priv(dev); 1626 1627 if (dev->mtu > TD_MSS_MAX) 1628 features &= ~NETIF_F_ALL_TSO; 1629 1630 if (dev->mtu > ETH_DATA_LEN && 1631 tp->mac_version > RTL_GIGA_MAC_VER_06) 1632 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1633 1634 return features; 1635 } 1636 1637 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1638 netdev_features_t features) 1639 { 1640 u32 rx_config = RTL_R32(tp, RxConfig); 1641 1642 if (features & NETIF_F_RXALL) 1643 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1644 else 1645 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1646 1647 if (rtl_is_8125(tp)) { 1648 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1649 rx_config |= RX_VLAN_8125; 1650 else 1651 rx_config &= ~RX_VLAN_8125; 1652 } 1653 1654 RTL_W32(tp, RxConfig, rx_config); 1655 } 1656 1657 static int rtl8169_set_features(struct net_device *dev, 1658 netdev_features_t features) 1659 { 1660 struct rtl8169_private *tp = netdev_priv(dev); 1661 1662 rtl_set_rx_config_features(tp, features); 1663 1664 if (features & NETIF_F_RXCSUM) 1665 tp->cp_cmd |= RxChkSum; 1666 else 1667 tp->cp_cmd &= ~RxChkSum; 1668 1669 if (!rtl_is_8125(tp)) { 1670 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1671 tp->cp_cmd |= RxVlan; 1672 else 1673 tp->cp_cmd &= ~RxVlan; 1674 } 1675 1676 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1677 rtl_pci_commit(tp); 1678 1679 return 0; 1680 } 1681 1682 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1683 { 1684 return (skb_vlan_tag_present(skb)) ? 1685 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1686 } 1687 1688 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1689 { 1690 u32 opts2 = le32_to_cpu(desc->opts2); 1691 1692 if (opts2 & RxVlanTag) 1693 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1694 } 1695 1696 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1697 void *p) 1698 { 1699 struct rtl8169_private *tp = netdev_priv(dev); 1700 u32 __iomem *data = tp->mmio_addr; 1701 u32 *dw = p; 1702 int i; 1703 1704 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1705 memcpy_fromio(dw++, data++, 4); 1706 } 1707 1708 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1709 "tx_packets", 1710 "rx_packets", 1711 "tx_errors", 1712 "rx_errors", 1713 "rx_missed", 1714 "align_errors", 1715 "tx_single_collisions", 1716 "tx_multi_collisions", 1717 "unicast", 1718 "broadcast", 1719 "multicast", 1720 "tx_aborted", 1721 "tx_underrun", 1722 }; 1723 1724 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1725 { 1726 switch (sset) { 1727 case ETH_SS_STATS: 1728 return ARRAY_SIZE(rtl8169_gstrings); 1729 default: 1730 return -EOPNOTSUPP; 1731 } 1732 } 1733 1734 DECLARE_RTL_COND(rtl_counters_cond) 1735 { 1736 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1737 } 1738 1739 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1740 { 1741 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1742 1743 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1744 rtl_pci_commit(tp); 1745 RTL_W32(tp, CounterAddrLow, cmd); 1746 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1747 1748 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1749 } 1750 1751 static void rtl8169_update_counters(struct rtl8169_private *tp) 1752 { 1753 u8 val = RTL_R8(tp, ChipCmd); 1754 1755 /* 1756 * Some chips are unable to dump tally counters when the receiver 1757 * is disabled. If 0xff chip may be in a PCI power-save state. 1758 */ 1759 if (val & CmdRxEnb && val != 0xff) 1760 rtl8169_do_counters(tp, CounterDump); 1761 } 1762 1763 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1764 { 1765 struct rtl8169_counters *counters = tp->counters; 1766 1767 /* 1768 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1769 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1770 * reset by a power cycle, while the counter values collected by the 1771 * driver are reset at every driver unload/load cycle. 1772 * 1773 * To make sure the HW values returned by @get_stats64 match the SW 1774 * values, we collect the initial values at first open(*) and use them 1775 * as offsets to normalize the values returned by @get_stats64. 1776 * 1777 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1778 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1779 * set at open time by rtl_hw_start. 1780 */ 1781 1782 if (tp->tc_offset.inited) 1783 return; 1784 1785 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1786 rtl8169_do_counters(tp, CounterReset); 1787 } else { 1788 rtl8169_update_counters(tp); 1789 tp->tc_offset.tx_errors = counters->tx_errors; 1790 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1791 tp->tc_offset.tx_aborted = counters->tx_aborted; 1792 tp->tc_offset.rx_missed = counters->rx_missed; 1793 } 1794 1795 tp->tc_offset.inited = true; 1796 } 1797 1798 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1799 struct ethtool_stats *stats, u64 *data) 1800 { 1801 struct rtl8169_private *tp = netdev_priv(dev); 1802 struct rtl8169_counters *counters; 1803 1804 counters = tp->counters; 1805 rtl8169_update_counters(tp); 1806 1807 data[0] = le64_to_cpu(counters->tx_packets); 1808 data[1] = le64_to_cpu(counters->rx_packets); 1809 data[2] = le64_to_cpu(counters->tx_errors); 1810 data[3] = le32_to_cpu(counters->rx_errors); 1811 data[4] = le16_to_cpu(counters->rx_missed); 1812 data[5] = le16_to_cpu(counters->align_errors); 1813 data[6] = le32_to_cpu(counters->tx_one_collision); 1814 data[7] = le32_to_cpu(counters->tx_multi_collision); 1815 data[8] = le64_to_cpu(counters->rx_unicast); 1816 data[9] = le64_to_cpu(counters->rx_broadcast); 1817 data[10] = le32_to_cpu(counters->rx_multicast); 1818 data[11] = le16_to_cpu(counters->tx_aborted); 1819 data[12] = le16_to_cpu(counters->tx_underun); 1820 } 1821 1822 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1823 { 1824 switch(stringset) { 1825 case ETH_SS_STATS: 1826 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1827 break; 1828 } 1829 } 1830 1831 /* 1832 * Interrupt coalescing 1833 * 1834 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1835 * > 8169, 8168 and 810x line of chipsets 1836 * 1837 * 8169, 8168, and 8136(810x) serial chipsets support it. 1838 * 1839 * > 2 - the Tx timer unit at gigabit speed 1840 * 1841 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1842 * (0xe0) bit 1 and bit 0. 1843 * 1844 * For 8169 1845 * bit[1:0] \ speed 1000M 100M 10M 1846 * 0 0 320ns 2.56us 40.96us 1847 * 0 1 2.56us 20.48us 327.7us 1848 * 1 0 5.12us 40.96us 655.4us 1849 * 1 1 10.24us 81.92us 1.31ms 1850 * 1851 * For the other 1852 * bit[1:0] \ speed 1000M 100M 10M 1853 * 0 0 5us 2.56us 40.96us 1854 * 0 1 40us 20.48us 327.7us 1855 * 1 0 80us 40.96us 655.4us 1856 * 1 1 160us 81.92us 1.31ms 1857 */ 1858 1859 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1860 struct rtl_coalesce_info { 1861 u32 speed; 1862 u32 scale_nsecs[4]; 1863 }; 1864 1865 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1866 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1867 1868 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1869 { SPEED_1000, COALESCE_DELAY(320) }, 1870 { SPEED_100, COALESCE_DELAY(2560) }, 1871 { SPEED_10, COALESCE_DELAY(40960) }, 1872 { 0 }, 1873 }; 1874 1875 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1876 { SPEED_1000, COALESCE_DELAY(5000) }, 1877 { SPEED_100, COALESCE_DELAY(2560) }, 1878 { SPEED_10, COALESCE_DELAY(40960) }, 1879 { 0 }, 1880 }; 1881 #undef COALESCE_DELAY 1882 1883 /* get rx/tx scale vector corresponding to current speed */ 1884 static const struct rtl_coalesce_info * 1885 rtl_coalesce_info(struct rtl8169_private *tp) 1886 { 1887 const struct rtl_coalesce_info *ci; 1888 1889 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1890 ci = rtl_coalesce_info_8169; 1891 else 1892 ci = rtl_coalesce_info_8168_8136; 1893 1894 /* if speed is unknown assume highest one */ 1895 if (tp->phydev->speed == SPEED_UNKNOWN) 1896 return ci; 1897 1898 for (; ci->speed; ci++) { 1899 if (tp->phydev->speed == ci->speed) 1900 return ci; 1901 } 1902 1903 return ERR_PTR(-ELNRNG); 1904 } 1905 1906 static int rtl_get_coalesce(struct net_device *dev, 1907 struct ethtool_coalesce *ec, 1908 struct kernel_ethtool_coalesce *kernel_coal, 1909 struct netlink_ext_ack *extack) 1910 { 1911 struct rtl8169_private *tp = netdev_priv(dev); 1912 const struct rtl_coalesce_info *ci; 1913 u32 scale, c_us, c_fr; 1914 u16 intrmit; 1915 1916 if (rtl_is_8125(tp)) 1917 return -EOPNOTSUPP; 1918 1919 memset(ec, 0, sizeof(*ec)); 1920 1921 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1922 ci = rtl_coalesce_info(tp); 1923 if (IS_ERR(ci)) 1924 return PTR_ERR(ci); 1925 1926 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1927 1928 intrmit = RTL_R16(tp, IntrMitigate); 1929 1930 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1931 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1932 1933 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1934 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1935 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1936 1937 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1938 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1939 1940 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1941 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1942 1943 return 0; 1944 } 1945 1946 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1947 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1948 u16 *cp01) 1949 { 1950 const struct rtl_coalesce_info *ci; 1951 u16 i; 1952 1953 ci = rtl_coalesce_info(tp); 1954 if (IS_ERR(ci)) 1955 return PTR_ERR(ci); 1956 1957 for (i = 0; i < 4; i++) { 1958 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1959 *cp01 = i; 1960 return ci->scale_nsecs[i]; 1961 } 1962 } 1963 1964 return -ERANGE; 1965 } 1966 1967 static int rtl_set_coalesce(struct net_device *dev, 1968 struct ethtool_coalesce *ec, 1969 struct kernel_ethtool_coalesce *kernel_coal, 1970 struct netlink_ext_ack *extack) 1971 { 1972 struct rtl8169_private *tp = netdev_priv(dev); 1973 u32 tx_fr = ec->tx_max_coalesced_frames; 1974 u32 rx_fr = ec->rx_max_coalesced_frames; 1975 u32 coal_usec_max, units; 1976 u16 w = 0, cp01 = 0; 1977 int scale; 1978 1979 if (rtl_is_8125(tp)) 1980 return -EOPNOTSUPP; 1981 1982 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1983 return -ERANGE; 1984 1985 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1986 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1987 if (scale < 0) 1988 return scale; 1989 1990 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1991 * not only when usecs=0 because of e.g. the following scenario: 1992 * 1993 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1994 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1995 * - then user does `ethtool -C eth0 rx-usecs 100` 1996 * 1997 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1998 * if we want to ignore rx_frames then it has to be set to 0. 1999 */ 2000 if (rx_fr == 1) 2001 rx_fr = 0; 2002 if (tx_fr == 1) 2003 tx_fr = 0; 2004 2005 /* HW requires time limit to be set if frame limit is set */ 2006 if ((tx_fr && !ec->tx_coalesce_usecs) || 2007 (rx_fr && !ec->rx_coalesce_usecs)) 2008 return -EINVAL; 2009 2010 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2011 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2012 2013 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2014 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2015 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2016 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2017 2018 RTL_W16(tp, IntrMitigate, w); 2019 2020 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2021 if (rtl_is_8168evl_up(tp)) { 2022 if (!rx_fr && !tx_fr) 2023 /* disable packet counter */ 2024 tp->cp_cmd |= PktCntrDisable; 2025 else 2026 tp->cp_cmd &= ~PktCntrDisable; 2027 } 2028 2029 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2030 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2031 rtl_pci_commit(tp); 2032 2033 return 0; 2034 } 2035 2036 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2037 { 2038 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2039 2040 switch (tp->mac_version) { 2041 case RTL_GIGA_MAC_VER_46: 2042 case RTL_GIGA_MAC_VER_48: 2043 tp->tx_lpi_timer = timer_val; 2044 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2045 break; 2046 case RTL_GIGA_MAC_VER_61: 2047 case RTL_GIGA_MAC_VER_63: 2048 case RTL_GIGA_MAC_VER_65: 2049 tp->tx_lpi_timer = timer_val; 2050 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2051 break; 2052 default: 2053 break; 2054 } 2055 } 2056 2057 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2058 { 2059 unsigned int speed = tp->phydev->speed; 2060 unsigned int timer = tp->tx_lpi_timer; 2061 2062 if (!timer || speed == SPEED_UNKNOWN) 2063 return 0; 2064 2065 /* tx_lpi_timer value is in bytes */ 2066 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2067 } 2068 2069 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2070 { 2071 struct rtl8169_private *tp = netdev_priv(dev); 2072 int ret; 2073 2074 if (!rtl_supports_eee(tp)) 2075 return -EOPNOTSUPP; 2076 2077 ret = phy_ethtool_get_eee(tp->phydev, data); 2078 if (ret) 2079 return ret; 2080 2081 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2082 data->tx_lpi_enabled = data->tx_lpi_timer ? data->eee_enabled : false; 2083 2084 return 0; 2085 } 2086 2087 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2088 { 2089 struct rtl8169_private *tp = netdev_priv(dev); 2090 2091 if (!rtl_supports_eee(tp)) 2092 return -EOPNOTSUPP; 2093 2094 return phy_ethtool_set_eee(tp->phydev, data); 2095 } 2096 2097 static void rtl8169_get_ringparam(struct net_device *dev, 2098 struct ethtool_ringparam *data, 2099 struct kernel_ethtool_ringparam *kernel_data, 2100 struct netlink_ext_ack *extack) 2101 { 2102 data->rx_max_pending = NUM_RX_DESC; 2103 data->rx_pending = NUM_RX_DESC; 2104 data->tx_max_pending = NUM_TX_DESC; 2105 data->tx_pending = NUM_TX_DESC; 2106 } 2107 2108 static void rtl8169_get_pauseparam(struct net_device *dev, 2109 struct ethtool_pauseparam *data) 2110 { 2111 struct rtl8169_private *tp = netdev_priv(dev); 2112 bool tx_pause, rx_pause; 2113 2114 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2115 2116 data->autoneg = tp->phydev->autoneg; 2117 data->tx_pause = tx_pause ? 1 : 0; 2118 data->rx_pause = rx_pause ? 1 : 0; 2119 } 2120 2121 static int rtl8169_set_pauseparam(struct net_device *dev, 2122 struct ethtool_pauseparam *data) 2123 { 2124 struct rtl8169_private *tp = netdev_priv(dev); 2125 2126 if (dev->mtu > ETH_DATA_LEN) 2127 return -EOPNOTSUPP; 2128 2129 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2130 2131 return 0; 2132 } 2133 2134 static const struct ethtool_ops rtl8169_ethtool_ops = { 2135 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2136 ETHTOOL_COALESCE_MAX_FRAMES, 2137 .get_drvinfo = rtl8169_get_drvinfo, 2138 .get_regs_len = rtl8169_get_regs_len, 2139 .get_link = ethtool_op_get_link, 2140 .get_coalesce = rtl_get_coalesce, 2141 .set_coalesce = rtl_set_coalesce, 2142 .get_regs = rtl8169_get_regs, 2143 .get_wol = rtl8169_get_wol, 2144 .set_wol = rtl8169_set_wol, 2145 .get_strings = rtl8169_get_strings, 2146 .get_sset_count = rtl8169_get_sset_count, 2147 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2148 .get_ts_info = ethtool_op_get_ts_info, 2149 .nway_reset = phy_ethtool_nway_reset, 2150 .get_eee = rtl8169_get_eee, 2151 .set_eee = rtl8169_set_eee, 2152 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2153 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2154 .get_ringparam = rtl8169_get_ringparam, 2155 .get_pauseparam = rtl8169_get_pauseparam, 2156 .set_pauseparam = rtl8169_set_pauseparam, 2157 }; 2158 2159 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2160 { 2161 /* 2162 * The driver currently handles the 8168Bf and the 8168Be identically 2163 * but they can be identified more specifically through the test below 2164 * if needed: 2165 * 2166 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2167 * 2168 * Same thing for the 8101Eb and the 8101Ec: 2169 * 2170 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2171 */ 2172 static const struct rtl_mac_info { 2173 u16 mask; 2174 u16 val; 2175 enum mac_version ver; 2176 } mac_info[] = { 2177 /* 8126A family. */ 2178 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2179 2180 /* 8125B family. */ 2181 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2182 2183 /* 8125A family. */ 2184 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2185 /* It seems only XID 609 made it to the mass market. 2186 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2187 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2188 */ 2189 2190 /* RTL8117 */ 2191 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2192 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2193 2194 /* 8168EP family. */ 2195 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2196 /* It seems this chip version never made it to 2197 * the wild. Let's disable detection. 2198 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2199 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2200 */ 2201 2202 /* 8168H family. */ 2203 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2204 /* It seems this chip version never made it to 2205 * the wild. Let's disable detection. 2206 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2207 */ 2208 2209 /* 8168G family. */ 2210 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2211 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2212 /* It seems this chip version never made it to 2213 * the wild. Let's disable detection. 2214 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2215 */ 2216 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2217 2218 /* 8168F family. */ 2219 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2220 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2221 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2222 2223 /* 8168E family. */ 2224 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2225 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2226 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2227 2228 /* 8168D family. */ 2229 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2230 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2231 2232 /* 8168DP family. */ 2233 /* It seems this early RTL8168dp version never made it to 2234 * the wild. Support has been removed. 2235 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2236 */ 2237 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2238 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2239 2240 /* 8168C family. */ 2241 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2242 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2243 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2244 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2245 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2246 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2247 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2248 2249 /* 8168B family. */ 2250 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2251 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2252 2253 /* 8101 family. */ 2254 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2255 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2256 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2257 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2258 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2259 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2260 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2261 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2262 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2263 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2264 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2265 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2266 2267 /* 8110 family. */ 2268 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2269 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2270 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2271 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2272 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2273 2274 /* Catch-all */ 2275 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2276 }; 2277 const struct rtl_mac_info *p = mac_info; 2278 enum mac_version ver; 2279 2280 while ((xid & p->mask) != p->val) 2281 p++; 2282 ver = p->ver; 2283 2284 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2285 if (ver == RTL_GIGA_MAC_VER_42) 2286 ver = RTL_GIGA_MAC_VER_43; 2287 else if (ver == RTL_GIGA_MAC_VER_46) 2288 ver = RTL_GIGA_MAC_VER_48; 2289 } 2290 2291 return ver; 2292 } 2293 2294 static void rtl_release_firmware(struct rtl8169_private *tp) 2295 { 2296 if (tp->rtl_fw) { 2297 rtl_fw_release_firmware(tp->rtl_fw); 2298 kfree(tp->rtl_fw); 2299 tp->rtl_fw = NULL; 2300 } 2301 } 2302 2303 void r8169_apply_firmware(struct rtl8169_private *tp) 2304 { 2305 int val; 2306 2307 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2308 if (tp->rtl_fw) { 2309 rtl_fw_write_firmware(tp, tp->rtl_fw); 2310 /* At least one firmware doesn't reset tp->ocp_base. */ 2311 tp->ocp_base = OCP_STD_PHY_BASE; 2312 2313 /* PHY soft reset may still be in progress */ 2314 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2315 !(val & BMCR_RESET), 2316 50000, 600000, true); 2317 } 2318 } 2319 2320 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2321 { 2322 /* Adjust EEE LED frequency */ 2323 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2324 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2325 2326 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2327 } 2328 2329 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2330 { 2331 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2332 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2333 } 2334 2335 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2336 { 2337 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2338 } 2339 2340 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2341 { 2342 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2343 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2344 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2345 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2346 } 2347 2348 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2349 { 2350 u16 data1, data2, ioffset; 2351 2352 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2353 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2354 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2355 2356 ioffset = (data2 >> 1) & 0x7ff8; 2357 ioffset |= data2 & 0x0007; 2358 if (data1 & BIT(7)) 2359 ioffset |= BIT(15); 2360 2361 return ioffset; 2362 } 2363 2364 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2365 { 2366 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 2367 return; 2368 2369 set_bit(flag, tp->wk.flags); 2370 schedule_work(&tp->wk.work); 2371 } 2372 2373 static void rtl8169_init_phy(struct rtl8169_private *tp) 2374 { 2375 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2376 2377 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2378 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2379 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2380 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2381 RTL_W8(tp, 0x82, 0x01); 2382 } 2383 2384 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2385 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2386 tp->pci_dev->subsystem_device == 0xe000) 2387 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2388 2389 /* We may have called phy_speed_down before */ 2390 phy_speed_up(tp->phydev); 2391 2392 genphy_soft_reset(tp->phydev); 2393 } 2394 2395 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2396 { 2397 rtl_unlock_config_regs(tp); 2398 2399 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2400 rtl_pci_commit(tp); 2401 2402 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2403 rtl_pci_commit(tp); 2404 2405 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2406 rtl_rar_exgmac_set(tp, addr); 2407 2408 rtl_lock_config_regs(tp); 2409 } 2410 2411 static int rtl_set_mac_address(struct net_device *dev, void *p) 2412 { 2413 struct rtl8169_private *tp = netdev_priv(dev); 2414 int ret; 2415 2416 ret = eth_mac_addr(dev, p); 2417 if (ret) 2418 return ret; 2419 2420 rtl_rar_set(tp, dev->dev_addr); 2421 2422 return 0; 2423 } 2424 2425 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2426 { 2427 switch (tp->mac_version) { 2428 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2429 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2430 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2431 break; 2432 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2433 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2434 case RTL_GIGA_MAC_VER_38: 2435 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2436 break; 2437 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2438 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2439 break; 2440 case RTL_GIGA_MAC_VER_61: 2441 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2442 break; 2443 case RTL_GIGA_MAC_VER_63: 2444 case RTL_GIGA_MAC_VER_65: 2445 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2446 RX_PAUSE_SLOT_ON); 2447 break; 2448 default: 2449 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2450 break; 2451 } 2452 } 2453 2454 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2455 { 2456 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2457 } 2458 2459 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2460 { 2461 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2462 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2463 } 2464 2465 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2466 { 2467 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2468 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2469 } 2470 2471 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2472 { 2473 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2474 } 2475 2476 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2477 { 2478 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2479 } 2480 2481 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2482 { 2483 RTL_W8(tp, MaxTxPacketSize, 0x24); 2484 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2485 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2486 } 2487 2488 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2489 { 2490 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2491 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2492 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2493 } 2494 2495 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2496 { 2497 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2498 } 2499 2500 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2501 { 2502 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2503 } 2504 2505 static void rtl_jumbo_config(struct rtl8169_private *tp) 2506 { 2507 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2508 int readrq = 4096; 2509 2510 rtl_unlock_config_regs(tp); 2511 switch (tp->mac_version) { 2512 case RTL_GIGA_MAC_VER_17: 2513 if (jumbo) { 2514 readrq = 512; 2515 r8168b_1_hw_jumbo_enable(tp); 2516 } else { 2517 r8168b_1_hw_jumbo_disable(tp); 2518 } 2519 break; 2520 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2521 if (jumbo) { 2522 readrq = 512; 2523 r8168c_hw_jumbo_enable(tp); 2524 } else { 2525 r8168c_hw_jumbo_disable(tp); 2526 } 2527 break; 2528 case RTL_GIGA_MAC_VER_28: 2529 if (jumbo) 2530 r8168dp_hw_jumbo_enable(tp); 2531 else 2532 r8168dp_hw_jumbo_disable(tp); 2533 break; 2534 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2535 if (jumbo) 2536 r8168e_hw_jumbo_enable(tp); 2537 else 2538 r8168e_hw_jumbo_disable(tp); 2539 break; 2540 default: 2541 break; 2542 } 2543 rtl_lock_config_regs(tp); 2544 2545 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2546 pcie_set_readrq(tp->pci_dev, readrq); 2547 2548 /* Chip doesn't support pause in jumbo mode */ 2549 if (jumbo) { 2550 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2551 tp->phydev->advertising); 2552 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2553 tp->phydev->advertising); 2554 phy_start_aneg(tp->phydev); 2555 } 2556 } 2557 2558 DECLARE_RTL_COND(rtl_chipcmd_cond) 2559 { 2560 return RTL_R8(tp, ChipCmd) & CmdReset; 2561 } 2562 2563 static void rtl_hw_reset(struct rtl8169_private *tp) 2564 { 2565 RTL_W8(tp, ChipCmd, CmdReset); 2566 2567 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2568 } 2569 2570 static void rtl_request_firmware(struct rtl8169_private *tp) 2571 { 2572 struct rtl_fw *rtl_fw; 2573 2574 /* firmware loaded already or no firmware available */ 2575 if (tp->rtl_fw || !tp->fw_name) 2576 return; 2577 2578 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2579 if (!rtl_fw) 2580 return; 2581 2582 rtl_fw->phy_write = rtl_writephy; 2583 rtl_fw->phy_read = rtl_readphy; 2584 rtl_fw->mac_mcu_write = mac_mcu_write; 2585 rtl_fw->mac_mcu_read = mac_mcu_read; 2586 rtl_fw->fw_name = tp->fw_name; 2587 rtl_fw->dev = tp_to_dev(tp); 2588 2589 if (rtl_fw_request_firmware(rtl_fw)) 2590 kfree(rtl_fw); 2591 else 2592 tp->rtl_fw = rtl_fw; 2593 } 2594 2595 static void rtl_rx_close(struct rtl8169_private *tp) 2596 { 2597 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2598 } 2599 2600 DECLARE_RTL_COND(rtl_npq_cond) 2601 { 2602 return RTL_R8(tp, TxPoll) & NPQ; 2603 } 2604 2605 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2606 { 2607 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2608 } 2609 2610 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2611 { 2612 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2613 } 2614 2615 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2616 { 2617 /* IntrMitigate has new functionality on RTL8125 */ 2618 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2619 } 2620 2621 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2622 { 2623 switch (tp->mac_version) { 2624 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2625 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2626 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2627 break; 2628 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2629 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2630 break; 2631 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65: 2632 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2633 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2634 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2635 break; 2636 default: 2637 break; 2638 } 2639 } 2640 2641 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2642 { 2643 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2644 } 2645 2646 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2647 { 2648 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2649 fsleep(2000); 2650 rtl_wait_txrx_fifo_empty(tp); 2651 } 2652 2653 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2654 { 2655 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2656 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2657 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2658 2659 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2660 rtl_disable_rxdvgate(tp); 2661 } 2662 2663 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2664 { 2665 if (tp->dash_enabled) 2666 return; 2667 2668 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2669 tp->mac_version == RTL_GIGA_MAC_VER_33) 2670 rtl_ephy_write(tp, 0x19, 0xff64); 2671 2672 if (device_may_wakeup(tp_to_dev(tp))) { 2673 phy_speed_down(tp->phydev, false); 2674 rtl_wol_enable_rx(tp); 2675 } 2676 } 2677 2678 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2679 { 2680 u32 val = TX_DMA_BURST << TxDMAShift | 2681 InterFrameGap << TxInterFrameGapShift; 2682 2683 if (rtl_is_8168evl_up(tp)) 2684 val |= TXCFG_AUTO_FIFO; 2685 2686 RTL_W32(tp, TxConfig, val); 2687 } 2688 2689 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2690 { 2691 /* Low hurts. Let's disable the filtering. */ 2692 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2693 } 2694 2695 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2696 { 2697 /* 2698 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2699 * register to be written before TxDescAddrLow to work. 2700 * Switching from MMIO to I/O access fixes the issue as well. 2701 */ 2702 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2703 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2704 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2705 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2706 } 2707 2708 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2709 { 2710 u32 val; 2711 2712 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2713 val = 0x000fff00; 2714 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2715 val = 0x00ffff00; 2716 else 2717 return; 2718 2719 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2720 val |= 0xff; 2721 2722 RTL_W32(tp, 0x7c, val); 2723 } 2724 2725 static void rtl_set_rx_mode(struct net_device *dev) 2726 { 2727 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2728 /* Multicast hash filter */ 2729 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2730 struct rtl8169_private *tp = netdev_priv(dev); 2731 u32 tmp; 2732 2733 if (dev->flags & IFF_PROMISC) { 2734 rx_mode |= AcceptAllPhys; 2735 } else if (!(dev->flags & IFF_MULTICAST)) { 2736 rx_mode &= ~AcceptMulticast; 2737 } else if (dev->flags & IFF_ALLMULTI || 2738 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2739 /* accept all multicasts */ 2740 } else if (netdev_mc_empty(dev)) { 2741 rx_mode &= ~AcceptMulticast; 2742 } else { 2743 struct netdev_hw_addr *ha; 2744 2745 mc_filter[1] = mc_filter[0] = 0; 2746 netdev_for_each_mc_addr(ha, dev) { 2747 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2748 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2749 } 2750 2751 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2752 tmp = mc_filter[0]; 2753 mc_filter[0] = swab32(mc_filter[1]); 2754 mc_filter[1] = swab32(tmp); 2755 } 2756 } 2757 2758 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2759 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2760 2761 tmp = RTL_R32(tp, RxConfig); 2762 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2763 } 2764 2765 DECLARE_RTL_COND(rtl_csiar_cond) 2766 { 2767 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2768 } 2769 2770 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2771 { 2772 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2773 2774 RTL_W32(tp, CSIDR, value); 2775 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2776 CSIAR_BYTE_ENABLE | func << 16); 2777 2778 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2779 } 2780 2781 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2782 { 2783 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2784 2785 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2786 CSIAR_BYTE_ENABLE); 2787 2788 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2789 RTL_R32(tp, CSIDR) : ~0; 2790 } 2791 2792 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2793 { 2794 struct pci_dev *pdev = tp->pci_dev; 2795 u32 csi; 2796 2797 /* According to Realtek the value at config space address 0x070f 2798 * controls the L0s/L1 entrance latency. We try standard ECAM access 2799 * first and if it fails fall back to CSI. 2800 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2801 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2802 */ 2803 if (pdev->cfg_size > 0x070f && 2804 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2805 return; 2806 2807 netdev_notice_once(tp->dev, 2808 "No native access to PCI extended config space, falling back to CSI\n"); 2809 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2810 rtl_csi_write(tp, 0x070c, csi | val << 24); 2811 } 2812 2813 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2814 { 2815 /* L0 7us, L1 16us */ 2816 rtl_set_aspm_entry_latency(tp, 0x27); 2817 } 2818 2819 struct ephy_info { 2820 unsigned int offset; 2821 u16 mask; 2822 u16 bits; 2823 }; 2824 2825 static void __rtl_ephy_init(struct rtl8169_private *tp, 2826 const struct ephy_info *e, int len) 2827 { 2828 u16 w; 2829 2830 while (len-- > 0) { 2831 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2832 rtl_ephy_write(tp, e->offset, w); 2833 e++; 2834 } 2835 } 2836 2837 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2838 2839 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2840 { 2841 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2842 PCI_EXP_LNKCTL_CLKREQ_EN); 2843 } 2844 2845 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2846 { 2847 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2848 PCI_EXP_LNKCTL_CLKREQ_EN); 2849 } 2850 2851 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2852 { 2853 /* work around an issue when PCI reset occurs during L2/L3 state */ 2854 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2855 } 2856 2857 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2858 { 2859 /* Bits control which events trigger ASPM L1 exit: 2860 * Bit 12: rxdv 2861 * Bit 11: ltr_msg 2862 * Bit 10: txdma_poll 2863 * Bit 9: xadm 2864 * Bit 8: pktavi 2865 * Bit 7: txpla 2866 */ 2867 switch (tp->mac_version) { 2868 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2869 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2870 break; 2871 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2872 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2873 break; 2874 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 2875 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2876 break; 2877 default: 2878 break; 2879 } 2880 } 2881 2882 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2883 { 2884 switch (tp->mac_version) { 2885 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2886 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2887 break; 2888 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 2889 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2890 break; 2891 default: 2892 break; 2893 } 2894 } 2895 2896 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2897 { 2898 u8 val8; 2899 2900 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2901 return; 2902 2903 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2904 if (enable && tp->aspm_manageable) { 2905 /* On these chip versions ASPM can even harm 2906 * bus communication of other PCI devices. 2907 */ 2908 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2909 tp->mac_version == RTL_GIGA_MAC_VER_43) 2910 return; 2911 2912 rtl_mod_config5(tp, 0, ASPM_en); 2913 switch (tp->mac_version) { 2914 case RTL_GIGA_MAC_VER_65: 2915 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2916 RTL_W8(tp, INT_CFG0_8125, val8); 2917 break; 2918 default: 2919 rtl_mod_config2(tp, 0, ClkReqEn); 2920 break; 2921 } 2922 2923 switch (tp->mac_version) { 2924 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2925 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 2926 /* reset ephy tx/rx disable timer */ 2927 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2928 /* chip can trigger L1.2 */ 2929 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2930 break; 2931 default: 2932 break; 2933 } 2934 } else { 2935 switch (tp->mac_version) { 2936 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2937 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 2938 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2939 break; 2940 default: 2941 break; 2942 } 2943 2944 switch (tp->mac_version) { 2945 case RTL_GIGA_MAC_VER_65: 2946 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2947 RTL_W8(tp, INT_CFG0_8125, val8); 2948 break; 2949 default: 2950 rtl_mod_config2(tp, ClkReqEn, 0); 2951 break; 2952 } 2953 rtl_mod_config5(tp, ASPM_en, 0); 2954 } 2955 } 2956 2957 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2958 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2959 { 2960 /* Usage of dynamic vs. static FIFO is controlled by bit 2961 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2962 */ 2963 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2964 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2965 } 2966 2967 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2968 u8 low, u8 high) 2969 { 2970 /* FIFO thresholds for pause flow control */ 2971 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2972 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2973 } 2974 2975 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2976 { 2977 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2978 } 2979 2980 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2981 { 2982 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2983 2984 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2985 2986 rtl_disable_clock_request(tp); 2987 } 2988 2989 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2990 { 2991 static const struct ephy_info e_info_8168cp[] = { 2992 { 0x01, 0, 0x0001 }, 2993 { 0x02, 0x0800, 0x1000 }, 2994 { 0x03, 0, 0x0042 }, 2995 { 0x06, 0x0080, 0x0000 }, 2996 { 0x07, 0, 0x2000 } 2997 }; 2998 2999 rtl_set_def_aspm_entry_latency(tp); 3000 3001 rtl_ephy_init(tp, e_info_8168cp); 3002 3003 __rtl_hw_start_8168cp(tp); 3004 } 3005 3006 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3007 { 3008 rtl_set_def_aspm_entry_latency(tp); 3009 3010 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3011 } 3012 3013 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3014 { 3015 rtl_set_def_aspm_entry_latency(tp); 3016 3017 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3018 3019 /* Magic. */ 3020 RTL_W8(tp, DBG_REG, 0x20); 3021 } 3022 3023 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3024 { 3025 static const struct ephy_info e_info_8168c_1[] = { 3026 { 0x02, 0x0800, 0x1000 }, 3027 { 0x03, 0, 0x0002 }, 3028 { 0x06, 0x0080, 0x0000 } 3029 }; 3030 3031 rtl_set_def_aspm_entry_latency(tp); 3032 3033 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3034 3035 rtl_ephy_init(tp, e_info_8168c_1); 3036 3037 __rtl_hw_start_8168cp(tp); 3038 } 3039 3040 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3041 { 3042 static const struct ephy_info e_info_8168c_2[] = { 3043 { 0x01, 0, 0x0001 }, 3044 { 0x03, 0x0400, 0x0020 } 3045 }; 3046 3047 rtl_set_def_aspm_entry_latency(tp); 3048 3049 rtl_ephy_init(tp, e_info_8168c_2); 3050 3051 __rtl_hw_start_8168cp(tp); 3052 } 3053 3054 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3055 { 3056 rtl_set_def_aspm_entry_latency(tp); 3057 3058 __rtl_hw_start_8168cp(tp); 3059 } 3060 3061 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3062 { 3063 rtl_set_def_aspm_entry_latency(tp); 3064 3065 rtl_disable_clock_request(tp); 3066 } 3067 3068 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3069 { 3070 static const struct ephy_info e_info_8168d_4[] = { 3071 { 0x0b, 0x0000, 0x0048 }, 3072 { 0x19, 0x0020, 0x0050 }, 3073 { 0x0c, 0x0100, 0x0020 }, 3074 { 0x10, 0x0004, 0x0000 }, 3075 }; 3076 3077 rtl_set_def_aspm_entry_latency(tp); 3078 3079 rtl_ephy_init(tp, e_info_8168d_4); 3080 3081 rtl_enable_clock_request(tp); 3082 } 3083 3084 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3085 { 3086 static const struct ephy_info e_info_8168e_1[] = { 3087 { 0x00, 0x0200, 0x0100 }, 3088 { 0x00, 0x0000, 0x0004 }, 3089 { 0x06, 0x0002, 0x0001 }, 3090 { 0x06, 0x0000, 0x0030 }, 3091 { 0x07, 0x0000, 0x2000 }, 3092 { 0x00, 0x0000, 0x0020 }, 3093 { 0x03, 0x5800, 0x2000 }, 3094 { 0x03, 0x0000, 0x0001 }, 3095 { 0x01, 0x0800, 0x1000 }, 3096 { 0x07, 0x0000, 0x4000 }, 3097 { 0x1e, 0x0000, 0x2000 }, 3098 { 0x19, 0xffff, 0xfe6c }, 3099 { 0x0a, 0x0000, 0x0040 } 3100 }; 3101 3102 rtl_set_def_aspm_entry_latency(tp); 3103 3104 rtl_ephy_init(tp, e_info_8168e_1); 3105 3106 rtl_disable_clock_request(tp); 3107 3108 /* Reset tx FIFO pointer */ 3109 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3110 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3111 3112 rtl_mod_config5(tp, Spi_en, 0); 3113 } 3114 3115 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3116 { 3117 static const struct ephy_info e_info_8168e_2[] = { 3118 { 0x09, 0x0000, 0x0080 }, 3119 { 0x19, 0x0000, 0x0224 }, 3120 { 0x00, 0x0000, 0x0004 }, 3121 { 0x0c, 0x3df0, 0x0200 }, 3122 }; 3123 3124 rtl_set_def_aspm_entry_latency(tp); 3125 3126 rtl_ephy_init(tp, e_info_8168e_2); 3127 3128 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3129 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3130 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3131 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3132 rtl_reset_packet_filter(tp); 3133 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3134 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3135 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3136 3137 rtl_disable_clock_request(tp); 3138 3139 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3140 3141 rtl8168_config_eee_mac(tp); 3142 3143 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3144 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3145 rtl_mod_config5(tp, Spi_en, 0); 3146 } 3147 3148 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3149 { 3150 rtl_set_def_aspm_entry_latency(tp); 3151 3152 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3153 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3154 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3155 rtl_reset_packet_filter(tp); 3156 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3157 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3158 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3159 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3160 3161 rtl_disable_clock_request(tp); 3162 3163 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3164 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3165 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3166 rtl_mod_config5(tp, Spi_en, 0); 3167 3168 rtl8168_config_eee_mac(tp); 3169 } 3170 3171 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3172 { 3173 static const struct ephy_info e_info_8168f_1[] = { 3174 { 0x06, 0x00c0, 0x0020 }, 3175 { 0x08, 0x0001, 0x0002 }, 3176 { 0x09, 0x0000, 0x0080 }, 3177 { 0x19, 0x0000, 0x0224 }, 3178 { 0x00, 0x0000, 0x0008 }, 3179 { 0x0c, 0x3df0, 0x0200 }, 3180 }; 3181 3182 rtl_hw_start_8168f(tp); 3183 3184 rtl_ephy_init(tp, e_info_8168f_1); 3185 } 3186 3187 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3188 { 3189 static const struct ephy_info e_info_8168f_1[] = { 3190 { 0x06, 0x00c0, 0x0020 }, 3191 { 0x0f, 0xffff, 0x5200 }, 3192 { 0x19, 0x0000, 0x0224 }, 3193 { 0x00, 0x0000, 0x0008 }, 3194 { 0x0c, 0x3df0, 0x0200 }, 3195 }; 3196 3197 rtl_hw_start_8168f(tp); 3198 rtl_pcie_state_l2l3_disable(tp); 3199 3200 rtl_ephy_init(tp, e_info_8168f_1); 3201 } 3202 3203 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3204 { 3205 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3206 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3207 3208 rtl_set_def_aspm_entry_latency(tp); 3209 3210 rtl_reset_packet_filter(tp); 3211 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3212 3213 rtl_disable_rxdvgate(tp); 3214 3215 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3216 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3217 3218 rtl8168_config_eee_mac(tp); 3219 3220 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3221 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3222 3223 rtl_pcie_state_l2l3_disable(tp); 3224 } 3225 3226 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3227 { 3228 static const struct ephy_info e_info_8168g_1[] = { 3229 { 0x00, 0x0008, 0x0000 }, 3230 { 0x0c, 0x3ff0, 0x0820 }, 3231 { 0x1e, 0x0000, 0x0001 }, 3232 { 0x19, 0x8000, 0x0000 } 3233 }; 3234 3235 rtl_hw_start_8168g(tp); 3236 rtl_ephy_init(tp, e_info_8168g_1); 3237 } 3238 3239 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3240 { 3241 static const struct ephy_info e_info_8168g_2[] = { 3242 { 0x00, 0x0008, 0x0000 }, 3243 { 0x0c, 0x3ff0, 0x0820 }, 3244 { 0x19, 0xffff, 0x7c00 }, 3245 { 0x1e, 0xffff, 0x20eb }, 3246 { 0x0d, 0xffff, 0x1666 }, 3247 { 0x00, 0xffff, 0x10a3 }, 3248 { 0x06, 0xffff, 0xf050 }, 3249 { 0x04, 0x0000, 0x0010 }, 3250 { 0x1d, 0x4000, 0x0000 }, 3251 }; 3252 3253 rtl_hw_start_8168g(tp); 3254 rtl_ephy_init(tp, e_info_8168g_2); 3255 } 3256 3257 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3258 { 3259 static const u16 fix_data[] = { 3260 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3261 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3262 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3263 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3264 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3265 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3266 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3267 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3268 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3269 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3270 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3271 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3272 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3273 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3274 }; 3275 unsigned long flags; 3276 int i; 3277 3278 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3279 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3280 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3281 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3282 } 3283 3284 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3285 { 3286 static const struct ephy_info e_info_8411_2[] = { 3287 { 0x00, 0x0008, 0x0000 }, 3288 { 0x0c, 0x37d0, 0x0820 }, 3289 { 0x1e, 0x0000, 0x0001 }, 3290 { 0x19, 0x8021, 0x0000 }, 3291 { 0x1e, 0x0000, 0x2000 }, 3292 { 0x0d, 0x0100, 0x0200 }, 3293 { 0x00, 0x0000, 0x0080 }, 3294 { 0x06, 0x0000, 0x0010 }, 3295 { 0x04, 0x0000, 0x0010 }, 3296 { 0x1d, 0x0000, 0x4000 }, 3297 }; 3298 3299 rtl_hw_start_8168g(tp); 3300 3301 rtl_ephy_init(tp, e_info_8411_2); 3302 3303 /* The following Realtek-provided magic fixes an issue with the RX unit 3304 * getting confused after the PHY having been powered-down. 3305 */ 3306 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3307 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3308 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3309 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3310 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3311 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3312 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3313 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3314 mdelay(3); 3315 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3316 3317 rtl8411b_fix_phy_down(tp); 3318 3319 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3320 3321 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3322 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3323 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3324 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3325 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3326 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3327 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3328 } 3329 3330 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3331 { 3332 static const struct ephy_info e_info_8168h_1[] = { 3333 { 0x1e, 0x0800, 0x0001 }, 3334 { 0x1d, 0x0000, 0x0800 }, 3335 { 0x05, 0xffff, 0x2089 }, 3336 { 0x06, 0xffff, 0x5881 }, 3337 { 0x04, 0xffff, 0x854a }, 3338 { 0x01, 0xffff, 0x068b } 3339 }; 3340 int rg_saw_cnt; 3341 3342 rtl_ephy_init(tp, e_info_8168h_1); 3343 3344 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3345 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3346 3347 rtl_set_def_aspm_entry_latency(tp); 3348 3349 rtl_reset_packet_filter(tp); 3350 3351 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3352 3353 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3354 3355 rtl_disable_rxdvgate(tp); 3356 3357 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3358 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3359 3360 rtl8168_config_eee_mac(tp); 3361 3362 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3363 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3364 3365 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3366 3367 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3368 3369 rtl_pcie_state_l2l3_disable(tp); 3370 3371 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3372 if (rg_saw_cnt > 0) { 3373 u16 sw_cnt_1ms_ini; 3374 3375 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3376 sw_cnt_1ms_ini &= 0x0fff; 3377 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3378 } 3379 3380 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3381 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3382 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3383 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3384 3385 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3386 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3387 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3388 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3389 } 3390 3391 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3392 { 3393 rtl8168ep_stop_cmac(tp); 3394 3395 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3396 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3397 3398 rtl_set_def_aspm_entry_latency(tp); 3399 3400 rtl_reset_packet_filter(tp); 3401 3402 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3403 3404 rtl_disable_rxdvgate(tp); 3405 3406 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3407 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3408 3409 rtl8168_config_eee_mac(tp); 3410 3411 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3412 3413 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3414 3415 rtl_pcie_state_l2l3_disable(tp); 3416 } 3417 3418 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3419 { 3420 static const struct ephy_info e_info_8168ep_3[] = { 3421 { 0x00, 0x0000, 0x0080 }, 3422 { 0x0d, 0x0100, 0x0200 }, 3423 { 0x19, 0x8021, 0x0000 }, 3424 { 0x1e, 0x0000, 0x2000 }, 3425 }; 3426 3427 rtl_ephy_init(tp, e_info_8168ep_3); 3428 3429 rtl_hw_start_8168ep(tp); 3430 3431 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3432 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3433 3434 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3435 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3436 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3437 } 3438 3439 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3440 { 3441 static const struct ephy_info e_info_8117[] = { 3442 { 0x19, 0x0040, 0x1100 }, 3443 { 0x59, 0x0040, 0x1100 }, 3444 }; 3445 int rg_saw_cnt; 3446 3447 rtl8168ep_stop_cmac(tp); 3448 rtl_ephy_init(tp, e_info_8117); 3449 3450 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3451 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3452 3453 rtl_set_def_aspm_entry_latency(tp); 3454 3455 rtl_reset_packet_filter(tp); 3456 3457 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3458 3459 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3460 3461 rtl_disable_rxdvgate(tp); 3462 3463 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3464 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3465 3466 rtl8168_config_eee_mac(tp); 3467 3468 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3469 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3470 3471 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3472 3473 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3474 3475 rtl_pcie_state_l2l3_disable(tp); 3476 3477 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3478 if (rg_saw_cnt > 0) { 3479 u16 sw_cnt_1ms_ini; 3480 3481 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3482 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3483 } 3484 3485 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3486 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3487 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3488 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3489 3490 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3491 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3492 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3493 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3494 3495 /* firmware is for MAC only */ 3496 r8169_apply_firmware(tp); 3497 } 3498 3499 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3500 { 3501 static const struct ephy_info e_info_8102e_1[] = { 3502 { 0x01, 0, 0x6e65 }, 3503 { 0x02, 0, 0x091f }, 3504 { 0x03, 0, 0xc2f9 }, 3505 { 0x06, 0, 0xafb5 }, 3506 { 0x07, 0, 0x0e00 }, 3507 { 0x19, 0, 0xec80 }, 3508 { 0x01, 0, 0x2e65 }, 3509 { 0x01, 0, 0x6e65 } 3510 }; 3511 u8 cfg1; 3512 3513 rtl_set_def_aspm_entry_latency(tp); 3514 3515 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3516 3517 RTL_W8(tp, Config1, 3518 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3519 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3520 3521 cfg1 = RTL_R8(tp, Config1); 3522 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3523 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3524 3525 rtl_ephy_init(tp, e_info_8102e_1); 3526 } 3527 3528 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3529 { 3530 rtl_set_def_aspm_entry_latency(tp); 3531 3532 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3533 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3534 } 3535 3536 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3537 { 3538 rtl_hw_start_8102e_2(tp); 3539 3540 rtl_ephy_write(tp, 0x03, 0xc2f9); 3541 } 3542 3543 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3544 { 3545 static const struct ephy_info e_info_8401[] = { 3546 { 0x01, 0xffff, 0x6fe5 }, 3547 { 0x03, 0xffff, 0x0599 }, 3548 { 0x06, 0xffff, 0xaf25 }, 3549 { 0x07, 0xffff, 0x8e68 }, 3550 }; 3551 3552 rtl_ephy_init(tp, e_info_8401); 3553 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3554 } 3555 3556 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3557 { 3558 static const struct ephy_info e_info_8105e_1[] = { 3559 { 0x07, 0, 0x4000 }, 3560 { 0x19, 0, 0x0200 }, 3561 { 0x19, 0, 0x0020 }, 3562 { 0x1e, 0, 0x2000 }, 3563 { 0x03, 0, 0x0001 }, 3564 { 0x19, 0, 0x0100 }, 3565 { 0x19, 0, 0x0004 }, 3566 { 0x0a, 0, 0x0020 } 3567 }; 3568 3569 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3570 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3571 3572 /* Disable Early Tally Counter */ 3573 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3574 3575 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3576 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3577 3578 rtl_ephy_init(tp, e_info_8105e_1); 3579 3580 rtl_pcie_state_l2l3_disable(tp); 3581 } 3582 3583 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3584 { 3585 rtl_hw_start_8105e_1(tp); 3586 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3587 } 3588 3589 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3590 { 3591 static const struct ephy_info e_info_8402[] = { 3592 { 0x19, 0xffff, 0xff64 }, 3593 { 0x1e, 0, 0x4000 } 3594 }; 3595 3596 rtl_set_def_aspm_entry_latency(tp); 3597 3598 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3599 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3600 3601 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3602 3603 rtl_ephy_init(tp, e_info_8402); 3604 3605 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3606 rtl_reset_packet_filter(tp); 3607 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3608 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3609 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3610 3611 /* disable EEE */ 3612 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3613 3614 rtl_pcie_state_l2l3_disable(tp); 3615 } 3616 3617 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3618 { 3619 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3620 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3621 3622 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3623 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3624 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3625 3626 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3627 rtl_set_aspm_entry_latency(tp, 0x2f); 3628 3629 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3630 3631 /* disable EEE */ 3632 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3633 3634 rtl_pcie_state_l2l3_disable(tp); 3635 } 3636 3637 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3638 { 3639 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3640 } 3641 3642 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3643 { 3644 rtl_pcie_state_l2l3_disable(tp); 3645 3646 RTL_W16(tp, 0x382, 0x221b); 3647 RTL_W8(tp, 0x4500, 0); 3648 RTL_W16(tp, 0x4800, 0); 3649 3650 /* disable UPS */ 3651 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3652 3653 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3654 3655 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3656 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3657 3658 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3659 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3660 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3661 3662 /* disable new tx descriptor format */ 3663 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3664 3665 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3666 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3667 3668 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3669 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3670 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3671 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3672 else 3673 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3674 3675 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3676 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3677 else 3678 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3679 3680 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3681 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3682 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3683 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3684 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3685 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3686 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3687 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3688 else 3689 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3690 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3691 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3692 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3693 3694 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3695 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3696 udelay(1); 3697 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3698 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3699 3700 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3701 3702 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3703 3704 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3705 rtl8125a_config_eee_mac(tp); 3706 else 3707 rtl8125b_config_eee_mac(tp); 3708 3709 rtl_disable_rxdvgate(tp); 3710 } 3711 3712 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3713 { 3714 static const struct ephy_info e_info_8125a_2[] = { 3715 { 0x04, 0xffff, 0xd000 }, 3716 { 0x0a, 0xffff, 0x8653 }, 3717 { 0x23, 0xffff, 0xab66 }, 3718 { 0x20, 0xffff, 0x9455 }, 3719 { 0x21, 0xffff, 0x99ff }, 3720 { 0x29, 0xffff, 0xfe04 }, 3721 3722 { 0x44, 0xffff, 0xd000 }, 3723 { 0x4a, 0xffff, 0x8653 }, 3724 { 0x63, 0xffff, 0xab66 }, 3725 { 0x60, 0xffff, 0x9455 }, 3726 { 0x61, 0xffff, 0x99ff }, 3727 { 0x69, 0xffff, 0xfe04 }, 3728 }; 3729 3730 rtl_set_def_aspm_entry_latency(tp); 3731 rtl_ephy_init(tp, e_info_8125a_2); 3732 rtl_hw_start_8125_common(tp); 3733 } 3734 3735 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3736 { 3737 static const struct ephy_info e_info_8125b[] = { 3738 { 0x0b, 0xffff, 0xa908 }, 3739 { 0x1e, 0xffff, 0x20eb }, 3740 { 0x4b, 0xffff, 0xa908 }, 3741 { 0x5e, 0xffff, 0x20eb }, 3742 { 0x22, 0x0030, 0x0020 }, 3743 { 0x62, 0x0030, 0x0020 }, 3744 }; 3745 3746 rtl_set_def_aspm_entry_latency(tp); 3747 rtl_ephy_init(tp, e_info_8125b); 3748 rtl_hw_start_8125_common(tp); 3749 } 3750 3751 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3752 { 3753 rtl_set_def_aspm_entry_latency(tp); 3754 rtl_hw_start_8125_common(tp); 3755 } 3756 3757 static void rtl_hw_config(struct rtl8169_private *tp) 3758 { 3759 static const rtl_generic_fct hw_configs[] = { 3760 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3761 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3762 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3763 [RTL_GIGA_MAC_VER_10] = NULL, 3764 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3765 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3766 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3767 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3768 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3769 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3770 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3771 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3772 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3773 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3774 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3775 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3776 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3777 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3778 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3779 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3780 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3781 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3782 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3783 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3784 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3785 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3786 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3787 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3788 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3789 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3790 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3791 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3792 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3793 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3794 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3795 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3796 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3797 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3798 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3799 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3800 }; 3801 3802 if (hw_configs[tp->mac_version]) 3803 hw_configs[tp->mac_version](tp); 3804 } 3805 3806 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3807 { 3808 int i; 3809 3810 RTL_W8(tp, INT_CFG0_8125, 0x00); 3811 3812 /* disable interrupt coalescing */ 3813 switch (tp->mac_version) { 3814 case RTL_GIGA_MAC_VER_61: 3815 for (i = 0xa00; i < 0xb00; i += 4) 3816 RTL_W32(tp, i, 0); 3817 break; 3818 case RTL_GIGA_MAC_VER_63: 3819 case RTL_GIGA_MAC_VER_65: 3820 for (i = 0xa00; i < 0xa80; i += 4) 3821 RTL_W32(tp, i, 0); 3822 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3823 break; 3824 default: 3825 break; 3826 } 3827 3828 rtl_hw_config(tp); 3829 } 3830 3831 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3832 { 3833 if (rtl_is_8168evl_up(tp)) 3834 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3835 else 3836 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3837 3838 rtl_hw_config(tp); 3839 3840 /* disable interrupt coalescing */ 3841 RTL_W16(tp, IntrMitigate, 0x0000); 3842 } 3843 3844 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3845 { 3846 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3847 3848 tp->cp_cmd |= PCIMulRW; 3849 3850 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3851 tp->mac_version == RTL_GIGA_MAC_VER_03) 3852 tp->cp_cmd |= EnAnaPLL; 3853 3854 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3855 3856 rtl8169_set_magic_reg(tp); 3857 3858 /* disable interrupt coalescing */ 3859 RTL_W16(tp, IntrMitigate, 0x0000); 3860 } 3861 3862 static void rtl_hw_start(struct rtl8169_private *tp) 3863 { 3864 rtl_unlock_config_regs(tp); 3865 /* disable aspm and clock request before ephy access */ 3866 rtl_hw_aspm_clkreq_enable(tp, false); 3867 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3868 3869 rtl_set_eee_txidle_timer(tp); 3870 3871 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3872 rtl_hw_start_8169(tp); 3873 else if (rtl_is_8125(tp)) 3874 rtl_hw_start_8125(tp); 3875 else 3876 rtl_hw_start_8168(tp); 3877 3878 rtl_enable_exit_l1(tp); 3879 rtl_hw_aspm_clkreq_enable(tp, true); 3880 rtl_set_rx_max_size(tp); 3881 rtl_set_rx_tx_desc_registers(tp); 3882 rtl_lock_config_regs(tp); 3883 3884 rtl_jumbo_config(tp); 3885 3886 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3887 rtl_pci_commit(tp); 3888 3889 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3890 rtl_init_rxcfg(tp); 3891 rtl_set_tx_config_registers(tp); 3892 rtl_set_rx_config_features(tp, tp->dev->features); 3893 rtl_set_rx_mode(tp->dev); 3894 rtl_irq_enable(tp); 3895 } 3896 3897 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3898 { 3899 struct rtl8169_private *tp = netdev_priv(dev); 3900 3901 dev->mtu = new_mtu; 3902 netdev_update_features(dev); 3903 rtl_jumbo_config(tp); 3904 rtl_set_eee_txidle_timer(tp); 3905 3906 return 0; 3907 } 3908 3909 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3910 { 3911 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3912 3913 desc->opts2 = 0; 3914 /* Force memory writes to complete before releasing descriptor */ 3915 dma_wmb(); 3916 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3917 } 3918 3919 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3920 struct RxDesc *desc) 3921 { 3922 struct device *d = tp_to_dev(tp); 3923 int node = dev_to_node(d); 3924 dma_addr_t mapping; 3925 struct page *data; 3926 3927 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3928 if (!data) 3929 return NULL; 3930 3931 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3932 if (unlikely(dma_mapping_error(d, mapping))) { 3933 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3934 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3935 return NULL; 3936 } 3937 3938 desc->addr = cpu_to_le64(mapping); 3939 rtl8169_mark_to_asic(desc); 3940 3941 return data; 3942 } 3943 3944 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3945 { 3946 int i; 3947 3948 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3949 dma_unmap_page(tp_to_dev(tp), 3950 le64_to_cpu(tp->RxDescArray[i].addr), 3951 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3952 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3953 tp->Rx_databuff[i] = NULL; 3954 tp->RxDescArray[i].addr = 0; 3955 tp->RxDescArray[i].opts1 = 0; 3956 } 3957 } 3958 3959 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3960 { 3961 int i; 3962 3963 for (i = 0; i < NUM_RX_DESC; i++) { 3964 struct page *data; 3965 3966 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3967 if (!data) { 3968 rtl8169_rx_clear(tp); 3969 return -ENOMEM; 3970 } 3971 tp->Rx_databuff[i] = data; 3972 } 3973 3974 /* mark as last descriptor in the ring */ 3975 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3976 3977 return 0; 3978 } 3979 3980 static int rtl8169_init_ring(struct rtl8169_private *tp) 3981 { 3982 rtl8169_init_ring_indexes(tp); 3983 3984 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3985 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3986 3987 return rtl8169_rx_fill(tp); 3988 } 3989 3990 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3991 { 3992 struct ring_info *tx_skb = tp->tx_skb + entry; 3993 struct TxDesc *desc = tp->TxDescArray + entry; 3994 3995 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3996 DMA_TO_DEVICE); 3997 memset(desc, 0, sizeof(*desc)); 3998 memset(tx_skb, 0, sizeof(*tx_skb)); 3999 } 4000 4001 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4002 unsigned int n) 4003 { 4004 unsigned int i; 4005 4006 for (i = 0; i < n; i++) { 4007 unsigned int entry = (start + i) % NUM_TX_DESC; 4008 struct ring_info *tx_skb = tp->tx_skb + entry; 4009 unsigned int len = tx_skb->len; 4010 4011 if (len) { 4012 struct sk_buff *skb = tx_skb->skb; 4013 4014 rtl8169_unmap_tx_skb(tp, entry); 4015 if (skb) 4016 dev_consume_skb_any(skb); 4017 } 4018 } 4019 } 4020 4021 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4022 { 4023 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4024 netdev_reset_queue(tp->dev); 4025 } 4026 4027 static void rtl8169_cleanup(struct rtl8169_private *tp) 4028 { 4029 napi_disable(&tp->napi); 4030 4031 /* Give a racing hard_start_xmit a few cycles to complete. */ 4032 synchronize_net(); 4033 4034 /* Disable interrupts */ 4035 rtl8169_irq_mask_and_ack(tp); 4036 4037 rtl_rx_close(tp); 4038 4039 switch (tp->mac_version) { 4040 case RTL_GIGA_MAC_VER_28: 4041 case RTL_GIGA_MAC_VER_31: 4042 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4043 break; 4044 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4045 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4046 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4047 break; 4048 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 4049 rtl_enable_rxdvgate(tp); 4050 fsleep(2000); 4051 break; 4052 default: 4053 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4054 fsleep(100); 4055 break; 4056 } 4057 4058 rtl_hw_reset(tp); 4059 4060 rtl8169_tx_clear(tp); 4061 rtl8169_init_ring_indexes(tp); 4062 } 4063 4064 static void rtl_reset_work(struct rtl8169_private *tp) 4065 { 4066 int i; 4067 4068 netif_stop_queue(tp->dev); 4069 4070 rtl8169_cleanup(tp); 4071 4072 for (i = 0; i < NUM_RX_DESC; i++) 4073 rtl8169_mark_to_asic(tp->RxDescArray + i); 4074 4075 napi_enable(&tp->napi); 4076 rtl_hw_start(tp); 4077 } 4078 4079 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4080 { 4081 struct rtl8169_private *tp = netdev_priv(dev); 4082 4083 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4084 } 4085 4086 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4087 void *addr, unsigned int entry, bool desc_own) 4088 { 4089 struct TxDesc *txd = tp->TxDescArray + entry; 4090 struct device *d = tp_to_dev(tp); 4091 dma_addr_t mapping; 4092 u32 opts1; 4093 int ret; 4094 4095 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4096 ret = dma_mapping_error(d, mapping); 4097 if (unlikely(ret)) { 4098 if (net_ratelimit()) 4099 netdev_err(tp->dev, "Failed to map TX data!\n"); 4100 return ret; 4101 } 4102 4103 txd->addr = cpu_to_le64(mapping); 4104 txd->opts2 = cpu_to_le32(opts[1]); 4105 4106 opts1 = opts[0] | len; 4107 if (entry == NUM_TX_DESC - 1) 4108 opts1 |= RingEnd; 4109 if (desc_own) 4110 opts1 |= DescOwn; 4111 txd->opts1 = cpu_to_le32(opts1); 4112 4113 tp->tx_skb[entry].len = len; 4114 4115 return 0; 4116 } 4117 4118 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4119 const u32 *opts, unsigned int entry) 4120 { 4121 struct skb_shared_info *info = skb_shinfo(skb); 4122 unsigned int cur_frag; 4123 4124 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4125 const skb_frag_t *frag = info->frags + cur_frag; 4126 void *addr = skb_frag_address(frag); 4127 u32 len = skb_frag_size(frag); 4128 4129 entry = (entry + 1) % NUM_TX_DESC; 4130 4131 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4132 goto err_out; 4133 } 4134 4135 return 0; 4136 4137 err_out: 4138 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4139 return -EIO; 4140 } 4141 4142 static bool rtl_skb_is_udp(struct sk_buff *skb) 4143 { 4144 int no = skb_network_offset(skb); 4145 struct ipv6hdr *i6h, _i6h; 4146 struct iphdr *ih, _ih; 4147 4148 switch (vlan_get_protocol(skb)) { 4149 case htons(ETH_P_IP): 4150 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4151 return ih && ih->protocol == IPPROTO_UDP; 4152 case htons(ETH_P_IPV6): 4153 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4154 return i6h && i6h->nexthdr == IPPROTO_UDP; 4155 default: 4156 return false; 4157 } 4158 } 4159 4160 #define RTL_MIN_PATCH_LEN 47 4161 4162 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4163 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4164 struct sk_buff *skb) 4165 { 4166 unsigned int padto = 0, len = skb->len; 4167 4168 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4169 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4170 unsigned int trans_data_len = skb_tail_pointer(skb) - 4171 skb_transport_header(skb); 4172 4173 if (trans_data_len >= offsetof(struct udphdr, len) && 4174 trans_data_len < RTL_MIN_PATCH_LEN) { 4175 u16 dest = ntohs(udp_hdr(skb)->dest); 4176 4177 /* dest is a standard PTP port */ 4178 if (dest == 319 || dest == 320) 4179 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4180 } 4181 4182 if (trans_data_len < sizeof(struct udphdr)) 4183 padto = max_t(unsigned int, padto, 4184 len + sizeof(struct udphdr) - trans_data_len); 4185 } 4186 4187 return padto; 4188 } 4189 4190 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4191 struct sk_buff *skb) 4192 { 4193 unsigned int padto; 4194 4195 padto = rtl8125_quirk_udp_padto(tp, skb); 4196 4197 switch (tp->mac_version) { 4198 case RTL_GIGA_MAC_VER_34: 4199 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 4200 padto = max_t(unsigned int, padto, ETH_ZLEN); 4201 break; 4202 default: 4203 break; 4204 } 4205 4206 return padto; 4207 } 4208 4209 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4210 { 4211 u32 mss = skb_shinfo(skb)->gso_size; 4212 4213 if (mss) { 4214 opts[0] |= TD_LSO; 4215 opts[0] |= mss << TD0_MSS_SHIFT; 4216 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4217 const struct iphdr *ip = ip_hdr(skb); 4218 4219 if (ip->protocol == IPPROTO_TCP) 4220 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4221 else if (ip->protocol == IPPROTO_UDP) 4222 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4223 else 4224 WARN_ON_ONCE(1); 4225 } 4226 } 4227 4228 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4229 struct sk_buff *skb, u32 *opts) 4230 { 4231 struct skb_shared_info *shinfo = skb_shinfo(skb); 4232 u32 mss = shinfo->gso_size; 4233 4234 if (mss) { 4235 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4236 opts[0] |= TD1_GTSENV4; 4237 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4238 if (skb_cow_head(skb, 0)) 4239 return false; 4240 4241 tcp_v6_gso_csum_prep(skb); 4242 opts[0] |= TD1_GTSENV6; 4243 } else { 4244 WARN_ON_ONCE(1); 4245 } 4246 4247 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4248 opts[1] |= mss << TD1_MSS_SHIFT; 4249 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4250 u8 ip_protocol; 4251 4252 switch (vlan_get_protocol(skb)) { 4253 case htons(ETH_P_IP): 4254 opts[1] |= TD1_IPv4_CS; 4255 ip_protocol = ip_hdr(skb)->protocol; 4256 break; 4257 4258 case htons(ETH_P_IPV6): 4259 opts[1] |= TD1_IPv6_CS; 4260 ip_protocol = ipv6_hdr(skb)->nexthdr; 4261 break; 4262 4263 default: 4264 ip_protocol = IPPROTO_RAW; 4265 break; 4266 } 4267 4268 if (ip_protocol == IPPROTO_TCP) 4269 opts[1] |= TD1_TCP_CS; 4270 else if (ip_protocol == IPPROTO_UDP) 4271 opts[1] |= TD1_UDP_CS; 4272 else 4273 WARN_ON_ONCE(1); 4274 4275 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4276 } else { 4277 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4278 4279 /* skb_padto would free the skb on error */ 4280 return !__skb_put_padto(skb, padto, false); 4281 } 4282 4283 return true; 4284 } 4285 4286 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4287 { 4288 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4289 } 4290 4291 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4292 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4293 { 4294 switch (tp->mac_version) { 4295 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4296 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4297 return false; 4298 default: 4299 return true; 4300 } 4301 } 4302 4303 static void rtl8169_doorbell(struct rtl8169_private *tp) 4304 { 4305 if (rtl_is_8125(tp)) 4306 RTL_W16(tp, TxPoll_8125, BIT(0)); 4307 else 4308 RTL_W8(tp, TxPoll, NPQ); 4309 } 4310 4311 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4312 struct net_device *dev) 4313 { 4314 unsigned int frags = skb_shinfo(skb)->nr_frags; 4315 struct rtl8169_private *tp = netdev_priv(dev); 4316 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4317 struct TxDesc *txd_first, *txd_last; 4318 bool stop_queue, door_bell; 4319 u32 opts[2]; 4320 4321 if (unlikely(!rtl_tx_slots_avail(tp))) { 4322 if (net_ratelimit()) 4323 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4324 goto err_stop_0; 4325 } 4326 4327 opts[1] = rtl8169_tx_vlan_tag(skb); 4328 opts[0] = 0; 4329 4330 if (!rtl_chip_supports_csum_v2(tp)) 4331 rtl8169_tso_csum_v1(skb, opts); 4332 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4333 goto err_dma_0; 4334 4335 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4336 entry, false))) 4337 goto err_dma_0; 4338 4339 txd_first = tp->TxDescArray + entry; 4340 4341 if (frags) { 4342 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4343 goto err_dma_1; 4344 entry = (entry + frags) % NUM_TX_DESC; 4345 } 4346 4347 txd_last = tp->TxDescArray + entry; 4348 txd_last->opts1 |= cpu_to_le32(LastFrag); 4349 tp->tx_skb[entry].skb = skb; 4350 4351 skb_tx_timestamp(skb); 4352 4353 /* Force memory writes to complete before releasing descriptor */ 4354 dma_wmb(); 4355 4356 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4357 4358 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4359 4360 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4361 smp_wmb(); 4362 4363 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4364 4365 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4366 R8169_TX_STOP_THRS, 4367 R8169_TX_START_THRS); 4368 if (door_bell || stop_queue) 4369 rtl8169_doorbell(tp); 4370 4371 return NETDEV_TX_OK; 4372 4373 err_dma_1: 4374 rtl8169_unmap_tx_skb(tp, entry); 4375 err_dma_0: 4376 dev_kfree_skb_any(skb); 4377 dev->stats.tx_dropped++; 4378 return NETDEV_TX_OK; 4379 4380 err_stop_0: 4381 netif_stop_queue(dev); 4382 dev->stats.tx_dropped++; 4383 return NETDEV_TX_BUSY; 4384 } 4385 4386 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4387 { 4388 struct skb_shared_info *info = skb_shinfo(skb); 4389 unsigned int nr_frags = info->nr_frags; 4390 4391 if (!nr_frags) 4392 return UINT_MAX; 4393 4394 return skb_frag_size(info->frags + nr_frags - 1); 4395 } 4396 4397 /* Workaround for hw issues with TSO on RTL8168evl */ 4398 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4399 netdev_features_t features) 4400 { 4401 /* IPv4 header has options field */ 4402 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4403 ip_hdrlen(skb) > sizeof(struct iphdr)) 4404 features &= ~NETIF_F_ALL_TSO; 4405 4406 /* IPv4 TCP header has options field */ 4407 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4408 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4409 features &= ~NETIF_F_ALL_TSO; 4410 4411 else if (rtl_last_frag_len(skb) <= 6) 4412 features &= ~NETIF_F_ALL_TSO; 4413 4414 return features; 4415 } 4416 4417 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4418 struct net_device *dev, 4419 netdev_features_t features) 4420 { 4421 struct rtl8169_private *tp = netdev_priv(dev); 4422 4423 if (skb_is_gso(skb)) { 4424 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4425 features = rtl8168evl_fix_tso(skb, features); 4426 4427 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4428 rtl_chip_supports_csum_v2(tp)) 4429 features &= ~NETIF_F_ALL_TSO; 4430 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4431 /* work around hw bug on some chip versions */ 4432 if (skb->len < ETH_ZLEN) 4433 features &= ~NETIF_F_CSUM_MASK; 4434 4435 if (rtl_quirk_packet_padto(tp, skb)) 4436 features &= ~NETIF_F_CSUM_MASK; 4437 4438 if (skb_transport_offset(skb) > TCPHO_MAX && 4439 rtl_chip_supports_csum_v2(tp)) 4440 features &= ~NETIF_F_CSUM_MASK; 4441 } 4442 4443 return vlan_features_check(skb, features); 4444 } 4445 4446 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4447 { 4448 struct rtl8169_private *tp = netdev_priv(dev); 4449 struct pci_dev *pdev = tp->pci_dev; 4450 int pci_status_errs; 4451 u16 pci_cmd; 4452 4453 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4454 4455 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4456 4457 if (net_ratelimit()) 4458 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4459 pci_cmd, pci_status_errs); 4460 4461 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4462 } 4463 4464 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4465 int budget) 4466 { 4467 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4468 struct sk_buff *skb; 4469 4470 dirty_tx = tp->dirty_tx; 4471 4472 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4473 unsigned int entry = dirty_tx % NUM_TX_DESC; 4474 u32 status; 4475 4476 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4477 if (status & DescOwn) 4478 break; 4479 4480 skb = tp->tx_skb[entry].skb; 4481 rtl8169_unmap_tx_skb(tp, entry); 4482 4483 if (skb) { 4484 pkts_compl++; 4485 bytes_compl += skb->len; 4486 napi_consume_skb(skb, budget); 4487 } 4488 dirty_tx++; 4489 } 4490 4491 if (tp->dirty_tx != dirty_tx) { 4492 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4493 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4494 4495 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4496 rtl_tx_slots_avail(tp), 4497 R8169_TX_START_THRS); 4498 /* 4499 * 8168 hack: TxPoll requests are lost when the Tx packets are 4500 * too close. Let's kick an extra TxPoll request when a burst 4501 * of start_xmit activity is detected (if it is not detected, 4502 * it is slow enough). -- FR 4503 * If skb is NULL then we come here again once a tx irq is 4504 * triggered after the last fragment is marked transmitted. 4505 */ 4506 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4507 rtl8169_doorbell(tp); 4508 } 4509 } 4510 4511 static inline int rtl8169_fragmented_frame(u32 status) 4512 { 4513 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4514 } 4515 4516 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4517 { 4518 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4519 4520 if (status == RxProtoTCP || status == RxProtoUDP) 4521 skb->ip_summed = CHECKSUM_UNNECESSARY; 4522 else 4523 skb_checksum_none_assert(skb); 4524 } 4525 4526 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4527 { 4528 struct device *d = tp_to_dev(tp); 4529 int count; 4530 4531 for (count = 0; count < budget; count++, tp->cur_rx++) { 4532 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4533 struct RxDesc *desc = tp->RxDescArray + entry; 4534 struct sk_buff *skb; 4535 const void *rx_buf; 4536 dma_addr_t addr; 4537 u32 status; 4538 4539 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4540 if (status & DescOwn) 4541 break; 4542 4543 /* This barrier is needed to keep us from reading 4544 * any other fields out of the Rx descriptor until 4545 * we know the status of DescOwn 4546 */ 4547 dma_rmb(); 4548 4549 if (unlikely(status & RxRES)) { 4550 if (net_ratelimit()) 4551 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4552 status); 4553 dev->stats.rx_errors++; 4554 if (status & (RxRWT | RxRUNT)) 4555 dev->stats.rx_length_errors++; 4556 if (status & RxCRC) 4557 dev->stats.rx_crc_errors++; 4558 4559 if (!(dev->features & NETIF_F_RXALL)) 4560 goto release_descriptor; 4561 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4562 goto release_descriptor; 4563 } 4564 4565 pkt_size = status & GENMASK(13, 0); 4566 if (likely(!(dev->features & NETIF_F_RXFCS))) 4567 pkt_size -= ETH_FCS_LEN; 4568 4569 /* The driver does not support incoming fragmented frames. 4570 * They are seen as a symptom of over-mtu sized frames. 4571 */ 4572 if (unlikely(rtl8169_fragmented_frame(status))) { 4573 dev->stats.rx_dropped++; 4574 dev->stats.rx_length_errors++; 4575 goto release_descriptor; 4576 } 4577 4578 skb = napi_alloc_skb(&tp->napi, pkt_size); 4579 if (unlikely(!skb)) { 4580 dev->stats.rx_dropped++; 4581 goto release_descriptor; 4582 } 4583 4584 addr = le64_to_cpu(desc->addr); 4585 rx_buf = page_address(tp->Rx_databuff[entry]); 4586 4587 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4588 prefetch(rx_buf); 4589 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4590 skb->tail += pkt_size; 4591 skb->len = pkt_size; 4592 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4593 4594 rtl8169_rx_csum(skb, status); 4595 skb->protocol = eth_type_trans(skb, dev); 4596 4597 rtl8169_rx_vlan_tag(desc, skb); 4598 4599 if (skb->pkt_type == PACKET_MULTICAST) 4600 dev->stats.multicast++; 4601 4602 napi_gro_receive(&tp->napi, skb); 4603 4604 dev_sw_netstats_rx_add(dev, pkt_size); 4605 release_descriptor: 4606 rtl8169_mark_to_asic(desc); 4607 } 4608 4609 return count; 4610 } 4611 4612 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4613 { 4614 struct rtl8169_private *tp = dev_instance; 4615 u32 status = rtl_get_events(tp); 4616 4617 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4618 return IRQ_NONE; 4619 4620 if (unlikely(status & SYSErr)) { 4621 rtl8169_pcierr_interrupt(tp->dev); 4622 goto out; 4623 } 4624 4625 if (status & LinkChg) 4626 phy_mac_interrupt(tp->phydev); 4627 4628 if (unlikely(status & RxFIFOOver && 4629 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4630 netif_stop_queue(tp->dev); 4631 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4632 } 4633 4634 if (napi_schedule_prep(&tp->napi)) { 4635 rtl_irq_disable(tp); 4636 __napi_schedule(&tp->napi); 4637 } 4638 out: 4639 rtl_ack_events(tp, status); 4640 4641 return IRQ_HANDLED; 4642 } 4643 4644 static void rtl_task(struct work_struct *work) 4645 { 4646 struct rtl8169_private *tp = 4647 container_of(work, struct rtl8169_private, wk.work); 4648 int ret; 4649 4650 rtnl_lock(); 4651 4652 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4653 goto out_unlock; 4654 4655 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4656 /* if chip isn't accessible, reset bus to revive it */ 4657 if (RTL_R32(tp, TxConfig) == ~0) { 4658 ret = pci_reset_bus(tp->pci_dev); 4659 if (ret < 0) { 4660 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4661 netif_device_detach(tp->dev); 4662 goto out_unlock; 4663 } 4664 } 4665 4666 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4667 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4668 PCIE_LINK_STATE_L0S); 4669 if (!ret) 4670 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4671 goto reset; 4672 } 4673 4674 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4675 reset: 4676 rtl_reset_work(tp); 4677 netif_wake_queue(tp->dev); 4678 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4679 rtl_reset_work(tp); 4680 } 4681 out_unlock: 4682 rtnl_unlock(); 4683 } 4684 4685 static int rtl8169_poll(struct napi_struct *napi, int budget) 4686 { 4687 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4688 struct net_device *dev = tp->dev; 4689 int work_done; 4690 4691 rtl_tx(dev, tp, budget); 4692 4693 work_done = rtl_rx(dev, tp, budget); 4694 4695 if (work_done < budget && napi_complete_done(napi, work_done)) 4696 rtl_irq_enable(tp); 4697 4698 return work_done; 4699 } 4700 4701 static void r8169_phylink_handler(struct net_device *ndev) 4702 { 4703 struct rtl8169_private *tp = netdev_priv(ndev); 4704 struct device *d = tp_to_dev(tp); 4705 4706 if (netif_carrier_ok(ndev)) { 4707 rtl_link_chg_patch(tp); 4708 pm_request_resume(d); 4709 netif_wake_queue(tp->dev); 4710 } else { 4711 /* In few cases rx is broken after link-down otherwise */ 4712 if (rtl_is_8125(tp)) 4713 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4714 pm_runtime_idle(d); 4715 } 4716 4717 phy_print_status(tp->phydev); 4718 } 4719 4720 static int r8169_phy_connect(struct rtl8169_private *tp) 4721 { 4722 struct phy_device *phydev = tp->phydev; 4723 phy_interface_t phy_mode; 4724 int ret; 4725 4726 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4727 PHY_INTERFACE_MODE_MII; 4728 4729 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4730 phy_mode); 4731 if (ret) 4732 return ret; 4733 4734 if (!tp->supports_gmii) 4735 phy_set_max_speed(phydev, SPEED_100); 4736 4737 phy_attached_info(phydev); 4738 4739 return 0; 4740 } 4741 4742 static void rtl8169_down(struct rtl8169_private *tp) 4743 { 4744 /* Clear all task flags */ 4745 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4746 4747 phy_stop(tp->phydev); 4748 4749 rtl8169_update_counters(tp); 4750 4751 pci_clear_master(tp->pci_dev); 4752 rtl_pci_commit(tp); 4753 4754 rtl8169_cleanup(tp); 4755 rtl_disable_exit_l1(tp); 4756 rtl_prepare_power_down(tp); 4757 4758 if (tp->dash_type != RTL_DASH_NONE) 4759 rtl8168_driver_stop(tp); 4760 } 4761 4762 static void rtl8169_up(struct rtl8169_private *tp) 4763 { 4764 if (tp->dash_type != RTL_DASH_NONE) 4765 rtl8168_driver_start(tp); 4766 4767 pci_set_master(tp->pci_dev); 4768 phy_init_hw(tp->phydev); 4769 phy_resume(tp->phydev); 4770 rtl8169_init_phy(tp); 4771 napi_enable(&tp->napi); 4772 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4773 rtl_reset_work(tp); 4774 4775 phy_start(tp->phydev); 4776 } 4777 4778 static int rtl8169_close(struct net_device *dev) 4779 { 4780 struct rtl8169_private *tp = netdev_priv(dev); 4781 struct pci_dev *pdev = tp->pci_dev; 4782 4783 pm_runtime_get_sync(&pdev->dev); 4784 4785 netif_stop_queue(dev); 4786 rtl8169_down(tp); 4787 rtl8169_rx_clear(tp); 4788 4789 cancel_work(&tp->wk.work); 4790 4791 free_irq(tp->irq, tp); 4792 4793 phy_disconnect(tp->phydev); 4794 4795 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4796 tp->RxPhyAddr); 4797 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4798 tp->TxPhyAddr); 4799 tp->TxDescArray = NULL; 4800 tp->RxDescArray = NULL; 4801 4802 pm_runtime_put_sync(&pdev->dev); 4803 4804 return 0; 4805 } 4806 4807 #ifdef CONFIG_NET_POLL_CONTROLLER 4808 static void rtl8169_netpoll(struct net_device *dev) 4809 { 4810 struct rtl8169_private *tp = netdev_priv(dev); 4811 4812 rtl8169_interrupt(tp->irq, tp); 4813 } 4814 #endif 4815 4816 static int rtl_open(struct net_device *dev) 4817 { 4818 struct rtl8169_private *tp = netdev_priv(dev); 4819 struct pci_dev *pdev = tp->pci_dev; 4820 unsigned long irqflags; 4821 int retval = -ENOMEM; 4822 4823 pm_runtime_get_sync(&pdev->dev); 4824 4825 /* 4826 * Rx and Tx descriptors needs 256 bytes alignment. 4827 * dma_alloc_coherent provides more. 4828 */ 4829 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4830 &tp->TxPhyAddr, GFP_KERNEL); 4831 if (!tp->TxDescArray) 4832 goto out; 4833 4834 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4835 &tp->RxPhyAddr, GFP_KERNEL); 4836 if (!tp->RxDescArray) 4837 goto err_free_tx_0; 4838 4839 retval = rtl8169_init_ring(tp); 4840 if (retval < 0) 4841 goto err_free_rx_1; 4842 4843 rtl_request_firmware(tp); 4844 4845 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4846 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4847 if (retval < 0) 4848 goto err_release_fw_2; 4849 4850 retval = r8169_phy_connect(tp); 4851 if (retval) 4852 goto err_free_irq; 4853 4854 rtl8169_up(tp); 4855 rtl8169_init_counter_offsets(tp); 4856 netif_start_queue(dev); 4857 out: 4858 pm_runtime_put_sync(&pdev->dev); 4859 4860 return retval; 4861 4862 err_free_irq: 4863 free_irq(tp->irq, tp); 4864 err_release_fw_2: 4865 rtl_release_firmware(tp); 4866 rtl8169_rx_clear(tp); 4867 err_free_rx_1: 4868 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4869 tp->RxPhyAddr); 4870 tp->RxDescArray = NULL; 4871 err_free_tx_0: 4872 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4873 tp->TxPhyAddr); 4874 tp->TxDescArray = NULL; 4875 goto out; 4876 } 4877 4878 static void 4879 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4880 { 4881 struct rtl8169_private *tp = netdev_priv(dev); 4882 struct pci_dev *pdev = tp->pci_dev; 4883 struct rtl8169_counters *counters = tp->counters; 4884 4885 pm_runtime_get_noresume(&pdev->dev); 4886 4887 netdev_stats_to_stats64(stats, &dev->stats); 4888 dev_fetch_sw_netstats(stats, dev->tstats); 4889 4890 /* 4891 * Fetch additional counter values missing in stats collected by driver 4892 * from tally counters. 4893 */ 4894 if (pm_runtime_active(&pdev->dev)) 4895 rtl8169_update_counters(tp); 4896 4897 /* 4898 * Subtract values fetched during initalization. 4899 * See rtl8169_init_counter_offsets for a description why we do that. 4900 */ 4901 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4902 le64_to_cpu(tp->tc_offset.tx_errors); 4903 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4904 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4905 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4906 le16_to_cpu(tp->tc_offset.tx_aborted); 4907 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4908 le16_to_cpu(tp->tc_offset.rx_missed); 4909 4910 pm_runtime_put_noidle(&pdev->dev); 4911 } 4912 4913 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4914 { 4915 netif_device_detach(tp->dev); 4916 4917 if (netif_running(tp->dev)) 4918 rtl8169_down(tp); 4919 } 4920 4921 static int rtl8169_runtime_resume(struct device *dev) 4922 { 4923 struct rtl8169_private *tp = dev_get_drvdata(dev); 4924 4925 rtl_rar_set(tp, tp->dev->dev_addr); 4926 __rtl8169_set_wol(tp, tp->saved_wolopts); 4927 4928 if (tp->TxDescArray) 4929 rtl8169_up(tp); 4930 4931 netif_device_attach(tp->dev); 4932 4933 return 0; 4934 } 4935 4936 static int rtl8169_suspend(struct device *device) 4937 { 4938 struct rtl8169_private *tp = dev_get_drvdata(device); 4939 4940 rtnl_lock(); 4941 rtl8169_net_suspend(tp); 4942 if (!device_may_wakeup(tp_to_dev(tp))) 4943 clk_disable_unprepare(tp->clk); 4944 rtnl_unlock(); 4945 4946 return 0; 4947 } 4948 4949 static int rtl8169_resume(struct device *device) 4950 { 4951 struct rtl8169_private *tp = dev_get_drvdata(device); 4952 4953 if (!device_may_wakeup(tp_to_dev(tp))) 4954 clk_prepare_enable(tp->clk); 4955 4956 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4957 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4958 rtl_init_rxcfg(tp); 4959 4960 return rtl8169_runtime_resume(device); 4961 } 4962 4963 static int rtl8169_runtime_suspend(struct device *device) 4964 { 4965 struct rtl8169_private *tp = dev_get_drvdata(device); 4966 4967 if (!tp->TxDescArray) { 4968 netif_device_detach(tp->dev); 4969 return 0; 4970 } 4971 4972 rtnl_lock(); 4973 __rtl8169_set_wol(tp, WAKE_PHY); 4974 rtl8169_net_suspend(tp); 4975 rtnl_unlock(); 4976 4977 return 0; 4978 } 4979 4980 static int rtl8169_runtime_idle(struct device *device) 4981 { 4982 struct rtl8169_private *tp = dev_get_drvdata(device); 4983 4984 if (tp->dash_enabled) 4985 return -EBUSY; 4986 4987 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4988 pm_schedule_suspend(device, 10000); 4989 4990 return -EBUSY; 4991 } 4992 4993 static const struct dev_pm_ops rtl8169_pm_ops = { 4994 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4995 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4996 rtl8169_runtime_idle) 4997 }; 4998 4999 static void rtl_shutdown(struct pci_dev *pdev) 5000 { 5001 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5002 5003 rtnl_lock(); 5004 rtl8169_net_suspend(tp); 5005 rtnl_unlock(); 5006 5007 /* Restore original MAC address */ 5008 rtl_rar_set(tp, tp->dev->perm_addr); 5009 5010 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5011 pci_wake_from_d3(pdev, tp->saved_wolopts); 5012 pci_set_power_state(pdev, PCI_D3hot); 5013 } 5014 } 5015 5016 static void rtl_remove_one(struct pci_dev *pdev) 5017 { 5018 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5019 5020 if (pci_dev_run_wake(pdev)) 5021 pm_runtime_get_noresume(&pdev->dev); 5022 5023 cancel_work_sync(&tp->wk.work); 5024 5025 unregister_netdev(tp->dev); 5026 5027 if (tp->dash_type != RTL_DASH_NONE) 5028 rtl8168_driver_stop(tp); 5029 5030 rtl_release_firmware(tp); 5031 5032 /* restore original MAC address */ 5033 rtl_rar_set(tp, tp->dev->perm_addr); 5034 } 5035 5036 static const struct net_device_ops rtl_netdev_ops = { 5037 .ndo_open = rtl_open, 5038 .ndo_stop = rtl8169_close, 5039 .ndo_get_stats64 = rtl8169_get_stats64, 5040 .ndo_start_xmit = rtl8169_start_xmit, 5041 .ndo_features_check = rtl8169_features_check, 5042 .ndo_tx_timeout = rtl8169_tx_timeout, 5043 .ndo_validate_addr = eth_validate_addr, 5044 .ndo_change_mtu = rtl8169_change_mtu, 5045 .ndo_fix_features = rtl8169_fix_features, 5046 .ndo_set_features = rtl8169_set_features, 5047 .ndo_set_mac_address = rtl_set_mac_address, 5048 .ndo_eth_ioctl = phy_do_ioctl_running, 5049 .ndo_set_rx_mode = rtl_set_rx_mode, 5050 #ifdef CONFIG_NET_POLL_CONTROLLER 5051 .ndo_poll_controller = rtl8169_netpoll, 5052 #endif 5053 5054 }; 5055 5056 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5057 { 5058 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5059 5060 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5061 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5062 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5063 /* special workaround needed */ 5064 tp->irq_mask |= RxFIFOOver; 5065 else 5066 tp->irq_mask |= RxOverflow; 5067 } 5068 5069 static int rtl_alloc_irq(struct rtl8169_private *tp) 5070 { 5071 unsigned int flags; 5072 5073 switch (tp->mac_version) { 5074 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5075 rtl_unlock_config_regs(tp); 5076 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5077 rtl_lock_config_regs(tp); 5078 fallthrough; 5079 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5080 flags = PCI_IRQ_LEGACY; 5081 break; 5082 default: 5083 flags = PCI_IRQ_ALL_TYPES; 5084 break; 5085 } 5086 5087 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5088 } 5089 5090 static void rtl_read_mac_address(struct rtl8169_private *tp, 5091 u8 mac_addr[ETH_ALEN]) 5092 { 5093 /* Get MAC address */ 5094 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5095 u32 value; 5096 5097 value = rtl_eri_read(tp, 0xe0); 5098 put_unaligned_le32(value, mac_addr); 5099 value = rtl_eri_read(tp, 0xe4); 5100 put_unaligned_le16(value, mac_addr + 4); 5101 } else if (rtl_is_8125(tp)) { 5102 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5103 } 5104 } 5105 5106 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5107 { 5108 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5109 } 5110 5111 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5112 { 5113 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5114 } 5115 5116 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5117 { 5118 struct rtl8169_private *tp = mii_bus->priv; 5119 5120 if (phyaddr > 0) 5121 return -ENODEV; 5122 5123 return rtl_readphy(tp, phyreg); 5124 } 5125 5126 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5127 int phyreg, u16 val) 5128 { 5129 struct rtl8169_private *tp = mii_bus->priv; 5130 5131 if (phyaddr > 0) 5132 return -ENODEV; 5133 5134 rtl_writephy(tp, phyreg, val); 5135 5136 return 0; 5137 } 5138 5139 static int r8169_mdio_register(struct rtl8169_private *tp) 5140 { 5141 struct pci_dev *pdev = tp->pci_dev; 5142 struct mii_bus *new_bus; 5143 int ret; 5144 5145 new_bus = devm_mdiobus_alloc(&pdev->dev); 5146 if (!new_bus) 5147 return -ENOMEM; 5148 5149 new_bus->name = "r8169"; 5150 new_bus->priv = tp; 5151 new_bus->parent = &pdev->dev; 5152 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5153 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5154 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5155 5156 new_bus->read = r8169_mdio_read_reg; 5157 new_bus->write = r8169_mdio_write_reg; 5158 5159 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5160 if (ret) 5161 return ret; 5162 5163 tp->phydev = mdiobus_get_phy(new_bus, 0); 5164 if (!tp->phydev) { 5165 return -ENODEV; 5166 } else if (!tp->phydev->drv) { 5167 /* Most chip versions fail with the genphy driver. 5168 * Therefore ensure that the dedicated PHY driver is loaded. 5169 */ 5170 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5171 tp->phydev->phy_id); 5172 return -EUNATCH; 5173 } 5174 5175 tp->phydev->mac_managed_pm = true; 5176 if (rtl_supports_eee(tp)) 5177 phy_advertise_eee_all(tp->phydev); 5178 phy_support_asym_pause(tp->phydev); 5179 5180 /* PHY will be woken up in rtl_open() */ 5181 phy_suspend(tp->phydev); 5182 5183 return 0; 5184 } 5185 5186 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5187 { 5188 rtl_enable_rxdvgate(tp); 5189 5190 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5191 msleep(1); 5192 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5193 5194 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5195 r8168g_wait_ll_share_fifo_ready(tp); 5196 5197 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5198 r8168g_wait_ll_share_fifo_ready(tp); 5199 } 5200 5201 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5202 { 5203 rtl_enable_rxdvgate(tp); 5204 5205 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5206 msleep(1); 5207 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5208 5209 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5210 r8168g_wait_ll_share_fifo_ready(tp); 5211 5212 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5213 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5214 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5215 r8168g_wait_ll_share_fifo_ready(tp); 5216 } 5217 5218 static void rtl_hw_initialize(struct rtl8169_private *tp) 5219 { 5220 switch (tp->mac_version) { 5221 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5222 rtl8168ep_stop_cmac(tp); 5223 fallthrough; 5224 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5225 rtl_hw_init_8168g(tp); 5226 break; 5227 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 5228 rtl_hw_init_8125(tp); 5229 break; 5230 default: 5231 break; 5232 } 5233 } 5234 5235 static int rtl_jumbo_max(struct rtl8169_private *tp) 5236 { 5237 /* Non-GBit versions don't support jumbo frames */ 5238 if (!tp->supports_gmii) 5239 return 0; 5240 5241 switch (tp->mac_version) { 5242 /* RTL8169 */ 5243 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5244 return JUMBO_7K; 5245 /* RTL8168b */ 5246 case RTL_GIGA_MAC_VER_11: 5247 case RTL_GIGA_MAC_VER_17: 5248 return JUMBO_4K; 5249 /* RTL8168c */ 5250 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5251 return JUMBO_6K; 5252 default: 5253 return JUMBO_9K; 5254 } 5255 } 5256 5257 static void rtl_init_mac_address(struct rtl8169_private *tp) 5258 { 5259 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5260 struct net_device *dev = tp->dev; 5261 int rc; 5262 5263 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5264 if (!rc) 5265 goto done; 5266 5267 rtl_read_mac_address(tp, mac_addr); 5268 if (is_valid_ether_addr(mac_addr)) 5269 goto done; 5270 5271 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5272 if (is_valid_ether_addr(mac_addr)) 5273 goto done; 5274 5275 eth_random_addr(mac_addr); 5276 dev->addr_assign_type = NET_ADDR_RANDOM; 5277 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5278 done: 5279 eth_hw_addr_set(dev, mac_addr); 5280 rtl_rar_set(tp, mac_addr); 5281 } 5282 5283 /* register is set if system vendor successfully tested ASPM 1.2 */ 5284 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5285 { 5286 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5287 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5288 return true; 5289 5290 return false; 5291 } 5292 5293 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5294 { 5295 struct rtl8169_private *tp; 5296 int jumbo_max, region, rc; 5297 enum mac_version chipset; 5298 struct net_device *dev; 5299 u32 txconfig; 5300 u16 xid; 5301 5302 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5303 if (!dev) 5304 return -ENOMEM; 5305 5306 SET_NETDEV_DEV(dev, &pdev->dev); 5307 dev->netdev_ops = &rtl_netdev_ops; 5308 tp = netdev_priv(dev); 5309 tp->dev = dev; 5310 tp->pci_dev = pdev; 5311 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5312 tp->ocp_base = OCP_STD_PHY_BASE; 5313 5314 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5315 raw_spin_lock_init(&tp->config25_lock); 5316 raw_spin_lock_init(&tp->mac_ocp_lock); 5317 mutex_init(&tp->led_lock); 5318 5319 /* Get the *optional* external "ether_clk" used on some boards */ 5320 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5321 if (IS_ERR(tp->clk)) 5322 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5323 5324 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5325 rc = pcim_enable_device(pdev); 5326 if (rc < 0) 5327 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5328 5329 if (pcim_set_mwi(pdev) < 0) 5330 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5331 5332 /* use first MMIO region */ 5333 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5334 if (region < 0) 5335 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5336 5337 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5338 if (rc < 0) 5339 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5340 5341 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5342 5343 txconfig = RTL_R32(tp, TxConfig); 5344 if (txconfig == ~0U) 5345 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5346 5347 xid = (txconfig >> 20) & 0xfcf; 5348 5349 /* Identify chip attached to board */ 5350 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5351 if (chipset == RTL_GIGA_MAC_NONE) 5352 return dev_err_probe(&pdev->dev, -ENODEV, 5353 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5354 xid); 5355 tp->mac_version = chipset; 5356 5357 /* Disable ASPM L1 as that cause random device stop working 5358 * problems as well as full system hangs for some PCIe devices users. 5359 */ 5360 if (rtl_aspm_is_safe(tp)) 5361 rc = 0; 5362 else 5363 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5364 tp->aspm_manageable = !rc; 5365 5366 tp->dash_type = rtl_get_dash_type(tp); 5367 tp->dash_enabled = rtl_dash_is_enabled(tp); 5368 5369 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5370 5371 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5372 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5373 dev->features |= NETIF_F_HIGHDMA; 5374 5375 rtl_init_rxcfg(tp); 5376 5377 rtl8169_irq_mask_and_ack(tp); 5378 5379 rtl_hw_initialize(tp); 5380 5381 rtl_hw_reset(tp); 5382 5383 rc = rtl_alloc_irq(tp); 5384 if (rc < 0) 5385 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5386 5387 tp->irq = pci_irq_vector(pdev, 0); 5388 5389 INIT_WORK(&tp->wk.work, rtl_task); 5390 5391 rtl_init_mac_address(tp); 5392 5393 dev->ethtool_ops = &rtl8169_ethtool_ops; 5394 5395 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5396 5397 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5398 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5399 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5400 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5401 5402 /* 5403 * Pretend we are using VLANs; This bypasses a nasty bug where 5404 * Interrupts stop flowing on high load on 8110SCd controllers. 5405 */ 5406 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5407 /* Disallow toggling */ 5408 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5409 5410 if (rtl_chip_supports_csum_v2(tp)) 5411 dev->hw_features |= NETIF_F_IPV6_CSUM; 5412 5413 dev->features |= dev->hw_features; 5414 5415 /* There has been a number of reports that using SG/TSO results in 5416 * tx timeouts. However for a lot of people SG/TSO works fine. 5417 * Therefore disable both features by default, but allow users to 5418 * enable them. Use at own risk! 5419 */ 5420 if (rtl_chip_supports_csum_v2(tp)) { 5421 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5422 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5423 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5424 } else { 5425 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5426 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5427 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5428 } 5429 5430 dev->hw_features |= NETIF_F_RXALL; 5431 dev->hw_features |= NETIF_F_RXFCS; 5432 5433 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5434 5435 netdev_sw_irq_coalesce_default_on(dev); 5436 5437 /* configure chip for default features */ 5438 rtl8169_set_features(dev, dev->features); 5439 5440 if (!tp->dash_enabled) { 5441 rtl_set_d3_pll_down(tp, true); 5442 } else { 5443 rtl_set_d3_pll_down(tp, false); 5444 dev->wol_enabled = 1; 5445 } 5446 5447 jumbo_max = rtl_jumbo_max(tp); 5448 if (jumbo_max) 5449 dev->max_mtu = jumbo_max; 5450 5451 rtl_set_irq_mask(tp); 5452 5453 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5454 5455 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5456 &tp->counters_phys_addr, 5457 GFP_KERNEL); 5458 if (!tp->counters) 5459 return -ENOMEM; 5460 5461 pci_set_drvdata(pdev, tp); 5462 5463 rc = r8169_mdio_register(tp); 5464 if (rc) 5465 return rc; 5466 5467 rc = register_netdev(dev); 5468 if (rc) 5469 return rc; 5470 5471 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5472 if (rtl_is_8125(tp)) 5473 rtl8125_init_leds(dev); 5474 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5475 rtl8168_init_leds(dev); 5476 } 5477 5478 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5479 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5480 5481 if (jumbo_max) 5482 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5483 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5484 "ok" : "ko"); 5485 5486 if (tp->dash_type != RTL_DASH_NONE) { 5487 netdev_info(dev, "DASH %s\n", 5488 tp->dash_enabled ? "enabled" : "disabled"); 5489 rtl8168_driver_start(tp); 5490 } 5491 5492 if (pci_dev_run_wake(pdev)) 5493 pm_runtime_put_sync(&pdev->dev); 5494 5495 return 0; 5496 } 5497 5498 static struct pci_driver rtl8169_pci_driver = { 5499 .name = KBUILD_MODNAME, 5500 .id_table = rtl8169_pci_tbl, 5501 .probe = rtl_init_one, 5502 .remove = rtl_remove_one, 5503 .shutdown = rtl_shutdown, 5504 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5505 }; 5506 5507 module_pci_driver(rtl8169_pci_driver); 5508