1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 59 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 60 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 61 62 #define R8169_REGS_SIZE 256 63 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 64 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 65 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 66 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 67 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 68 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 69 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 70 71 #define OCP_STD_PHY_BASE 0xa400 72 73 #define RTL_CFG_NO_GBIT 1 74 75 /* write/read MMIO register */ 76 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 79 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 80 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 81 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 82 83 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 84 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 88 static const struct { 89 const char *name; 90 const char *fw_name; 91 } rtl_chip_infos[] = { 92 /* PCI devices. */ 93 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 94 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 95 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 96 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 97 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 98 /* PCI-E devices. */ 99 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 100 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 102 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 103 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 104 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 105 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 106 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 107 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 108 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 109 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 112 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 114 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 115 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 116 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 117 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 118 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 119 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 120 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 121 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 122 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 123 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 124 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 125 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 126 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 127 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 128 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 129 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 130 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 131 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 132 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 133 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 134 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 135 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 136 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 137 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 138 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 139 }; 140 141 static const struct pci_device_id rtl8169_pci_tbl[] = { 142 { PCI_VDEVICE(REALTEK, 0x2502) }, 143 { PCI_VDEVICE(REALTEK, 0x2600) }, 144 { PCI_VDEVICE(REALTEK, 0x8129) }, 145 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 146 { PCI_VDEVICE(REALTEK, 0x8161) }, 147 { PCI_VDEVICE(REALTEK, 0x8162) }, 148 { PCI_VDEVICE(REALTEK, 0x8167) }, 149 { PCI_VDEVICE(REALTEK, 0x8168) }, 150 { PCI_VDEVICE(NCUBE, 0x8168) }, 151 { PCI_VDEVICE(REALTEK, 0x8169) }, 152 { PCI_VENDOR_ID_DLINK, 0x4300, 153 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 154 { PCI_VDEVICE(DLINK, 0x4300) }, 155 { PCI_VDEVICE(DLINK, 0x4302) }, 156 { PCI_VDEVICE(AT, 0xc107) }, 157 { PCI_VDEVICE(USR, 0x0116) }, 158 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 159 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 160 { PCI_VDEVICE(REALTEK, 0x8125) }, 161 { PCI_VDEVICE(REALTEK, 0x3000) }, 162 {} 163 }; 164 165 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 166 167 enum rtl_registers { 168 MAC0 = 0, /* Ethernet hardware address. */ 169 MAC4 = 4, 170 MAR0 = 8, /* Multicast filter. */ 171 CounterAddrLow = 0x10, 172 CounterAddrHigh = 0x14, 173 TxDescStartAddrLow = 0x20, 174 TxDescStartAddrHigh = 0x24, 175 TxHDescStartAddrLow = 0x28, 176 TxHDescStartAddrHigh = 0x2c, 177 FLASH = 0x30, 178 ERSR = 0x36, 179 ChipCmd = 0x37, 180 TxPoll = 0x38, 181 IntrMask = 0x3c, 182 IntrStatus = 0x3e, 183 184 TxConfig = 0x40, 185 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 186 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 187 188 RxConfig = 0x44, 189 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 190 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 191 #define RXCFG_FIFO_SHIFT 13 192 /* No threshold before first PCI xfer */ 193 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 194 #define RX_EARLY_OFF (1 << 11) 195 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 196 #define RXCFG_DMA_SHIFT 8 197 /* Unlimited maximum PCI burst. */ 198 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 199 200 Cfg9346 = 0x50, 201 Config0 = 0x51, 202 Config1 = 0x52, 203 Config2 = 0x53, 204 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 205 206 Config3 = 0x54, 207 Config4 = 0x55, 208 Config5 = 0x56, 209 PHYAR = 0x60, 210 PHYstatus = 0x6c, 211 RxMaxSize = 0xda, 212 CPlusCmd = 0xe0, 213 IntrMitigate = 0xe2, 214 215 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 216 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 217 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 218 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 219 220 #define RTL_COALESCE_T_MAX 0x0fU 221 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 222 223 RxDescAddrLow = 0xe4, 224 RxDescAddrHigh = 0xe8, 225 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 226 227 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 228 229 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 230 231 #define TxPacketMax (8064 >> 7) 232 #define EarlySize 0x27 233 234 FuncEvent = 0xf0, 235 FuncEventMask = 0xf4, 236 FuncPresetState = 0xf8, 237 IBCR0 = 0xf8, 238 IBCR2 = 0xf9, 239 IBIMR0 = 0xfa, 240 IBISR0 = 0xfb, 241 FuncForceEvent = 0xfc, 242 }; 243 244 enum rtl8168_8101_registers { 245 CSIDR = 0x64, 246 CSIAR = 0x68, 247 #define CSIAR_FLAG 0x80000000 248 #define CSIAR_WRITE_CMD 0x80000000 249 #define CSIAR_BYTE_ENABLE 0x0000f000 250 #define CSIAR_ADDR_MASK 0x00000fff 251 PMCH = 0x6f, 252 #define D3COLD_NO_PLL_DOWN BIT(7) 253 #define D3HOT_NO_PLL_DOWN BIT(6) 254 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 255 EPHYAR = 0x80, 256 #define EPHYAR_FLAG 0x80000000 257 #define EPHYAR_WRITE_CMD 0x80000000 258 #define EPHYAR_REG_MASK 0x1f 259 #define EPHYAR_REG_SHIFT 16 260 #define EPHYAR_DATA_MASK 0xffff 261 DLLPR = 0xd0, 262 #define PFM_EN (1 << 6) 263 #define TX_10M_PS_EN (1 << 7) 264 DBG_REG = 0xd1, 265 #define FIX_NAK_1 (1 << 4) 266 #define FIX_NAK_2 (1 << 3) 267 TWSI = 0xd2, 268 MCU = 0xd3, 269 #define NOW_IS_OOB (1 << 7) 270 #define TX_EMPTY (1 << 5) 271 #define RX_EMPTY (1 << 4) 272 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 273 #define EN_NDP (1 << 3) 274 #define EN_OOB_RESET (1 << 2) 275 #define LINK_LIST_RDY (1 << 1) 276 EFUSEAR = 0xdc, 277 #define EFUSEAR_FLAG 0x80000000 278 #define EFUSEAR_WRITE_CMD 0x80000000 279 #define EFUSEAR_READ_CMD 0x00000000 280 #define EFUSEAR_REG_MASK 0x03ff 281 #define EFUSEAR_REG_SHIFT 8 282 #define EFUSEAR_DATA_MASK 0xff 283 MISC_1 = 0xf2, 284 #define PFM_D3COLD_EN (1 << 6) 285 }; 286 287 enum rtl8168_registers { 288 LED_CTRL = 0x18, 289 LED_FREQ = 0x1a, 290 EEE_LED = 0x1b, 291 ERIDR = 0x70, 292 ERIAR = 0x74, 293 #define ERIAR_FLAG 0x80000000 294 #define ERIAR_WRITE_CMD 0x80000000 295 #define ERIAR_READ_CMD 0x00000000 296 #define ERIAR_ADDR_BYTE_ALIGN 4 297 #define ERIAR_TYPE_SHIFT 16 298 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 299 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 300 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 301 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_MASK_SHIFT 12 303 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 304 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 305 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 306 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 308 EPHY_RXER_NUM = 0x7c, 309 OCPDR = 0xb0, /* OCP GPHY access */ 310 #define OCPDR_WRITE_CMD 0x80000000 311 #define OCPDR_READ_CMD 0x00000000 312 #define OCPDR_REG_MASK 0x7f 313 #define OCPDR_GPHY_REG_SHIFT 16 314 #define OCPDR_DATA_MASK 0xffff 315 OCPAR = 0xb4, 316 #define OCPAR_FLAG 0x80000000 317 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 318 #define OCPAR_GPHY_READ_CMD 0x0000f060 319 GPHY_OCP = 0xb8, 320 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 321 MISC = 0xf0, /* 8168e only. */ 322 #define TXPLA_RST (1 << 29) 323 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 324 #define PWM_EN (1 << 22) 325 #define RXDV_GATED_EN (1 << 19) 326 #define EARLY_TALLY_EN (1 << 16) 327 }; 328 329 enum rtl8125_registers { 330 IntrMask_8125 = 0x38, 331 IntrStatus_8125 = 0x3c, 332 TxPoll_8125 = 0x90, 333 MAC0_BKP = 0x19e0, 334 EEE_TXIDLE_TIMER_8125 = 0x6048, 335 }; 336 337 #define RX_VLAN_INNER_8125 BIT(22) 338 #define RX_VLAN_OUTER_8125 BIT(23) 339 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 340 341 #define RX_FETCH_DFLT_8125 (8 << 27) 342 343 enum rtl_register_content { 344 /* InterruptStatusBits */ 345 SYSErr = 0x8000, 346 PCSTimeout = 0x4000, 347 SWInt = 0x0100, 348 TxDescUnavail = 0x0080, 349 RxFIFOOver = 0x0040, 350 LinkChg = 0x0020, 351 RxOverflow = 0x0010, 352 TxErr = 0x0008, 353 TxOK = 0x0004, 354 RxErr = 0x0002, 355 RxOK = 0x0001, 356 357 /* RxStatusDesc */ 358 RxRWT = (1 << 22), 359 RxRES = (1 << 21), 360 RxRUNT = (1 << 20), 361 RxCRC = (1 << 19), 362 363 /* ChipCmdBits */ 364 StopReq = 0x80, 365 CmdReset = 0x10, 366 CmdRxEnb = 0x08, 367 CmdTxEnb = 0x04, 368 RxBufEmpty = 0x01, 369 370 /* TXPoll register p.5 */ 371 HPQ = 0x80, /* Poll cmd on the high prio queue */ 372 NPQ = 0x40, /* Poll cmd on the low prio queue */ 373 FSWInt = 0x01, /* Forced software interrupt */ 374 375 /* Cfg9346Bits */ 376 Cfg9346_Lock = 0x00, 377 Cfg9346_Unlock = 0xc0, 378 379 /* rx_mode_bits */ 380 AcceptErr = 0x20, 381 AcceptRunt = 0x10, 382 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 383 AcceptBroadcast = 0x08, 384 AcceptMulticast = 0x04, 385 AcceptMyPhys = 0x02, 386 AcceptAllPhys = 0x01, 387 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 388 #define RX_CONFIG_ACCEPT_MASK 0x3f 389 390 /* TxConfigBits */ 391 TxInterFrameGapShift = 24, 392 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 393 394 /* Config1 register p.24 */ 395 LEDS1 = (1 << 7), 396 LEDS0 = (1 << 6), 397 Speed_down = (1 << 4), 398 MEMMAP = (1 << 3), 399 IOMAP = (1 << 2), 400 VPD = (1 << 1), 401 PMEnable = (1 << 0), /* Power Management Enable */ 402 403 /* Config2 register p. 25 */ 404 ClkReqEn = (1 << 7), /* Clock Request Enable */ 405 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 406 PCI_Clock_66MHz = 0x01, 407 PCI_Clock_33MHz = 0x00, 408 409 /* Config3 register p.25 */ 410 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 411 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 412 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 413 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 414 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 415 416 /* Config4 register */ 417 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 418 419 /* Config5 register p.27 */ 420 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 421 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 422 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 423 Spi_en = (1 << 3), 424 LanWake = (1 << 1), /* LanWake enable/disable */ 425 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 426 ASPM_en = (1 << 0), /* ASPM enable */ 427 428 /* CPlusCmd p.31 */ 429 EnableBist = (1 << 15), // 8168 8101 430 Mac_dbgo_oe = (1 << 14), // 8168 8101 431 EnAnaPLL = (1 << 14), // 8169 432 Normal_mode = (1 << 13), // unused 433 Force_half_dup = (1 << 12), // 8168 8101 434 Force_rxflow_en = (1 << 11), // 8168 8101 435 Force_txflow_en = (1 << 10), // 8168 8101 436 Cxpl_dbg_sel = (1 << 9), // 8168 8101 437 ASF = (1 << 8), // 8168 8101 438 PktCntrDisable = (1 << 7), // 8168 8101 439 Mac_dbgo_sel = 0x001c, // 8168 440 RxVlan = (1 << 6), 441 RxChkSum = (1 << 5), 442 PCIDAC = (1 << 4), 443 PCIMulRW = (1 << 3), 444 #define INTT_MASK GENMASK(1, 0) 445 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 446 447 /* rtl8169_PHYstatus */ 448 TBI_Enable = 0x80, 449 TxFlowCtrl = 0x40, 450 RxFlowCtrl = 0x20, 451 _1000bpsF = 0x10, 452 _100bps = 0x08, 453 _10bps = 0x04, 454 LinkStatus = 0x02, 455 FullDup = 0x01, 456 457 /* ResetCounterCommand */ 458 CounterReset = 0x1, 459 460 /* DumpCounterCommand */ 461 CounterDump = 0x8, 462 463 /* magic enable v2 */ 464 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 465 }; 466 467 enum rtl_desc_bit { 468 /* First doubleword. */ 469 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 470 RingEnd = (1 << 30), /* End of descriptor ring */ 471 FirstFrag = (1 << 29), /* First segment of a packet */ 472 LastFrag = (1 << 28), /* Final segment of a packet */ 473 }; 474 475 /* Generic case. */ 476 enum rtl_tx_desc_bit { 477 /* First doubleword. */ 478 TD_LSO = (1 << 27), /* Large Send Offload */ 479 #define TD_MSS_MAX 0x07ffu /* MSS value */ 480 481 /* Second doubleword. */ 482 TxVlanTag = (1 << 17), /* Add VLAN tag */ 483 }; 484 485 /* 8169, 8168b and 810x except 8102e. */ 486 enum rtl_tx_desc_bit_0 { 487 /* First doubleword. */ 488 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 489 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 490 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 491 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 492 }; 493 494 /* 8102e, 8168c and beyond. */ 495 enum rtl_tx_desc_bit_1 { 496 /* First doubleword. */ 497 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 498 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 499 #define GTTCPHO_SHIFT 18 500 #define GTTCPHO_MAX 0x7f 501 502 /* Second doubleword. */ 503 #define TCPHO_SHIFT 18 504 #define TCPHO_MAX 0x3ff 505 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 506 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 507 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 508 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 509 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 510 }; 511 512 enum rtl_rx_desc_bit { 513 /* Rx private */ 514 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 515 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 516 517 #define RxProtoUDP (PID1) 518 #define RxProtoTCP (PID0) 519 #define RxProtoIP (PID1 | PID0) 520 #define RxProtoMask RxProtoIP 521 522 IPFail = (1 << 16), /* IP checksum failed */ 523 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 524 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 525 526 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 527 528 RxVlanTag = (1 << 16), /* VLAN tag available */ 529 }; 530 531 #define RTL_GSO_MAX_SIZE_V1 32000 532 #define RTL_GSO_MAX_SEGS_V1 24 533 #define RTL_GSO_MAX_SIZE_V2 64000 534 #define RTL_GSO_MAX_SEGS_V2 64 535 536 struct TxDesc { 537 __le32 opts1; 538 __le32 opts2; 539 __le64 addr; 540 }; 541 542 struct RxDesc { 543 __le32 opts1; 544 __le32 opts2; 545 __le64 addr; 546 }; 547 548 struct ring_info { 549 struct sk_buff *skb; 550 u32 len; 551 }; 552 553 struct rtl8169_counters { 554 __le64 tx_packets; 555 __le64 rx_packets; 556 __le64 tx_errors; 557 __le32 rx_errors; 558 __le16 rx_missed; 559 __le16 align_errors; 560 __le32 tx_one_collision; 561 __le32 tx_multi_collision; 562 __le64 rx_unicast; 563 __le64 rx_broadcast; 564 __le32 rx_multicast; 565 __le16 tx_aborted; 566 __le16 tx_underun; 567 }; 568 569 struct rtl8169_tc_offsets { 570 bool inited; 571 __le64 tx_errors; 572 __le32 tx_multi_collision; 573 __le16 tx_aborted; 574 __le16 rx_missed; 575 }; 576 577 enum rtl_flag { 578 RTL_FLAG_TASK_ENABLED = 0, 579 RTL_FLAG_TASK_RESET_PENDING, 580 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 581 RTL_FLAG_TASK_TX_TIMEOUT, 582 RTL_FLAG_MAX 583 }; 584 585 enum rtl_dash_type { 586 RTL_DASH_NONE, 587 RTL_DASH_DP, 588 RTL_DASH_EP, 589 }; 590 591 struct rtl8169_private { 592 void __iomem *mmio_addr; /* memory map physical address */ 593 struct pci_dev *pci_dev; 594 struct net_device *dev; 595 struct phy_device *phydev; 596 struct napi_struct napi; 597 enum mac_version mac_version; 598 enum rtl_dash_type dash_type; 599 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 600 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 601 u32 dirty_tx; 602 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 603 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 604 dma_addr_t TxPhyAddr; 605 dma_addr_t RxPhyAddr; 606 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 607 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 608 u16 cp_cmd; 609 u32 irq_mask; 610 int irq; 611 struct clk *clk; 612 613 struct { 614 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 615 struct work_struct work; 616 } wk; 617 618 raw_spinlock_t config25_lock; 619 raw_spinlock_t mac_ocp_lock; 620 struct mutex led_lock; /* serialize LED ctrl RMW access */ 621 622 raw_spinlock_t cfg9346_usage_lock; 623 int cfg9346_usage_count; 624 625 unsigned supports_gmii:1; 626 unsigned aspm_manageable:1; 627 unsigned dash_enabled:1; 628 dma_addr_t counters_phys_addr; 629 struct rtl8169_counters *counters; 630 struct rtl8169_tc_offsets tc_offset; 631 u32 saved_wolopts; 632 int eee_adv; 633 634 const char *fw_name; 635 struct rtl_fw *rtl_fw; 636 637 u32 ocp_base; 638 }; 639 640 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 641 642 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 643 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 644 MODULE_SOFTDEP("pre: realtek"); 645 MODULE_LICENSE("GPL"); 646 MODULE_FIRMWARE(FIRMWARE_8168D_1); 647 MODULE_FIRMWARE(FIRMWARE_8168D_2); 648 MODULE_FIRMWARE(FIRMWARE_8168E_1); 649 MODULE_FIRMWARE(FIRMWARE_8168E_2); 650 MODULE_FIRMWARE(FIRMWARE_8168E_3); 651 MODULE_FIRMWARE(FIRMWARE_8105E_1); 652 MODULE_FIRMWARE(FIRMWARE_8168F_1); 653 MODULE_FIRMWARE(FIRMWARE_8168F_2); 654 MODULE_FIRMWARE(FIRMWARE_8402_1); 655 MODULE_FIRMWARE(FIRMWARE_8411_1); 656 MODULE_FIRMWARE(FIRMWARE_8411_2); 657 MODULE_FIRMWARE(FIRMWARE_8106E_1); 658 MODULE_FIRMWARE(FIRMWARE_8106E_2); 659 MODULE_FIRMWARE(FIRMWARE_8168G_2); 660 MODULE_FIRMWARE(FIRMWARE_8168G_3); 661 MODULE_FIRMWARE(FIRMWARE_8168H_2); 662 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 663 MODULE_FIRMWARE(FIRMWARE_8107E_2); 664 MODULE_FIRMWARE(FIRMWARE_8125A_3); 665 MODULE_FIRMWARE(FIRMWARE_8125B_2); 666 667 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 668 { 669 return &tp->pci_dev->dev; 670 } 671 672 static void rtl_lock_config_regs(struct rtl8169_private *tp) 673 { 674 unsigned long flags; 675 676 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 677 if (!--tp->cfg9346_usage_count) 678 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 679 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 680 } 681 682 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 683 { 684 unsigned long flags; 685 686 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 687 if (!tp->cfg9346_usage_count++) 688 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 689 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 690 } 691 692 static void rtl_pci_commit(struct rtl8169_private *tp) 693 { 694 /* Read an arbitrary register to commit a preceding PCI write */ 695 RTL_R8(tp, ChipCmd); 696 } 697 698 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 699 { 700 unsigned long flags; 701 u8 val; 702 703 raw_spin_lock_irqsave(&tp->config25_lock, flags); 704 val = RTL_R8(tp, Config2); 705 RTL_W8(tp, Config2, (val & ~clear) | set); 706 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 707 } 708 709 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 710 { 711 unsigned long flags; 712 u8 val; 713 714 raw_spin_lock_irqsave(&tp->config25_lock, flags); 715 val = RTL_R8(tp, Config5); 716 RTL_W8(tp, Config5, (val & ~clear) | set); 717 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 718 } 719 720 static bool rtl_is_8125(struct rtl8169_private *tp) 721 { 722 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 723 } 724 725 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 726 { 727 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 728 tp->mac_version != RTL_GIGA_MAC_VER_39 && 729 tp->mac_version <= RTL_GIGA_MAC_VER_53; 730 } 731 732 static bool rtl_supports_eee(struct rtl8169_private *tp) 733 { 734 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 735 tp->mac_version != RTL_GIGA_MAC_VER_37 && 736 tp->mac_version != RTL_GIGA_MAC_VER_39; 737 } 738 739 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 740 { 741 int i; 742 743 for (i = 0; i < ETH_ALEN; i++) 744 mac[i] = RTL_R8(tp, reg + i); 745 } 746 747 struct rtl_cond { 748 bool (*check)(struct rtl8169_private *); 749 const char *msg; 750 }; 751 752 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 753 unsigned long usecs, int n, bool high) 754 { 755 int i; 756 757 for (i = 0; i < n; i++) { 758 if (c->check(tp) == high) 759 return true; 760 fsleep(usecs); 761 } 762 763 if (net_ratelimit()) 764 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 765 c->msg, !high, n, usecs); 766 return false; 767 } 768 769 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 770 const struct rtl_cond *c, 771 unsigned long d, int n) 772 { 773 return rtl_loop_wait(tp, c, d, n, true); 774 } 775 776 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 777 const struct rtl_cond *c, 778 unsigned long d, int n) 779 { 780 return rtl_loop_wait(tp, c, d, n, false); 781 } 782 783 #define DECLARE_RTL_COND(name) \ 784 static bool name ## _check(struct rtl8169_private *); \ 785 \ 786 static const struct rtl_cond name = { \ 787 .check = name ## _check, \ 788 .msg = #name \ 789 }; \ 790 \ 791 static bool name ## _check(struct rtl8169_private *tp) 792 793 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 794 { 795 struct device *dev = tp_to_dev(tp); 796 int ret; 797 798 ret = pm_runtime_resume_and_get(dev); 799 if (ret < 0) 800 return ret; 801 802 mutex_lock(&tp->led_lock); 803 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 804 mutex_unlock(&tp->led_lock); 805 806 pm_runtime_put_sync(dev); 807 808 return 0; 809 } 810 811 int rtl8168_get_led_mode(struct rtl8169_private *tp) 812 { 813 struct device *dev = tp_to_dev(tp); 814 int ret; 815 816 ret = pm_runtime_resume_and_get(dev); 817 if (ret < 0) 818 return ret; 819 820 ret = RTL_R16(tp, LED_CTRL); 821 822 pm_runtime_put_sync(dev); 823 824 return ret; 825 } 826 827 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 828 char *buf, int buf_len) 829 { 830 struct pci_dev *pdev = tp->pci_dev; 831 char pdom[8], pfun[8]; 832 int domain; 833 834 domain = pci_domain_nr(pdev->bus); 835 if (domain) 836 snprintf(pdom, sizeof(pdom), "P%d", domain); 837 else 838 pdom[0] = '\0'; 839 840 if (pdev->multifunction) 841 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 842 else 843 pfun[0] = '\0'; 844 845 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 846 PCI_SLOT(pdev->devfn), pfun, idx); 847 } 848 849 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 850 { 851 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 852 if (type == ERIAR_OOB && 853 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 854 tp->mac_version == RTL_GIGA_MAC_VER_53)) 855 *cmd |= 0xf70 << 18; 856 } 857 858 DECLARE_RTL_COND(rtl_eriar_cond) 859 { 860 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 861 } 862 863 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 864 u32 val, int type) 865 { 866 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 867 868 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 869 return; 870 871 RTL_W32(tp, ERIDR, val); 872 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 873 RTL_W32(tp, ERIAR, cmd); 874 875 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 876 } 877 878 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 879 u32 val) 880 { 881 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 882 } 883 884 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 885 { 886 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 887 888 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 889 RTL_W32(tp, ERIAR, cmd); 890 891 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 892 RTL_R32(tp, ERIDR) : ~0; 893 } 894 895 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 896 { 897 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 898 } 899 900 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 901 { 902 u32 val = rtl_eri_read(tp, addr); 903 904 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 905 } 906 907 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 908 { 909 rtl_w0w1_eri(tp, addr, p, 0); 910 } 911 912 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 913 { 914 rtl_w0w1_eri(tp, addr, 0, m); 915 } 916 917 static bool rtl_ocp_reg_failure(u32 reg) 918 { 919 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 920 } 921 922 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 923 { 924 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 925 } 926 927 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 928 { 929 if (rtl_ocp_reg_failure(reg)) 930 return; 931 932 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 933 934 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 935 } 936 937 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 938 { 939 if (rtl_ocp_reg_failure(reg)) 940 return 0; 941 942 RTL_W32(tp, GPHY_OCP, reg << 15); 943 944 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 945 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 946 } 947 948 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 949 { 950 if (rtl_ocp_reg_failure(reg)) 951 return; 952 953 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 954 } 955 956 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 957 { 958 unsigned long flags; 959 960 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 961 __r8168_mac_ocp_write(tp, reg, data); 962 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 963 } 964 965 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 966 { 967 if (rtl_ocp_reg_failure(reg)) 968 return 0; 969 970 RTL_W32(tp, OCPDR, reg << 15); 971 972 return RTL_R32(tp, OCPDR); 973 } 974 975 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 976 { 977 unsigned long flags; 978 u16 val; 979 980 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 981 val = __r8168_mac_ocp_read(tp, reg); 982 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 983 984 return val; 985 } 986 987 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 988 u16 set) 989 { 990 unsigned long flags; 991 u16 data; 992 993 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 994 data = __r8168_mac_ocp_read(tp, reg); 995 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 996 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 997 } 998 999 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1000 * PHY MCU interrupts before PHY power-down. 1001 */ 1002 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1003 { 1004 switch (tp->mac_version) { 1005 case RTL_GIGA_MAC_VER_40: 1006 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1007 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1008 else 1009 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1010 break; 1011 default: 1012 break; 1013 } 1014 }; 1015 1016 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1017 { 1018 if (reg == 0x1f) { 1019 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1020 return; 1021 } 1022 1023 if (tp->ocp_base != OCP_STD_PHY_BASE) 1024 reg -= 0x10; 1025 1026 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1027 rtl8168g_phy_suspend_quirk(tp, value); 1028 1029 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1030 } 1031 1032 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1033 { 1034 if (reg == 0x1f) 1035 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1036 1037 if (tp->ocp_base != OCP_STD_PHY_BASE) 1038 reg -= 0x10; 1039 1040 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1041 } 1042 1043 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1044 { 1045 if (reg == 0x1f) { 1046 tp->ocp_base = value << 4; 1047 return; 1048 } 1049 1050 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1051 } 1052 1053 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1054 { 1055 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1056 } 1057 1058 DECLARE_RTL_COND(rtl_phyar_cond) 1059 { 1060 return RTL_R32(tp, PHYAR) & 0x80000000; 1061 } 1062 1063 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1064 { 1065 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1066 1067 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1068 /* 1069 * According to hardware specs a 20us delay is required after write 1070 * complete indication, but before sending next command. 1071 */ 1072 udelay(20); 1073 } 1074 1075 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1076 { 1077 int value; 1078 1079 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1080 1081 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1082 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1083 1084 /* 1085 * According to hardware specs a 20us delay is required after read 1086 * complete indication, but before sending next command. 1087 */ 1088 udelay(20); 1089 1090 return value; 1091 } 1092 1093 DECLARE_RTL_COND(rtl_ocpar_cond) 1094 { 1095 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1096 } 1097 1098 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1099 1100 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1101 { 1102 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1103 } 1104 1105 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1106 { 1107 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1108 } 1109 1110 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1111 { 1112 r8168dp_2_mdio_start(tp); 1113 1114 r8169_mdio_write(tp, reg, value); 1115 1116 r8168dp_2_mdio_stop(tp); 1117 } 1118 1119 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1120 { 1121 int value; 1122 1123 /* Work around issue with chip reporting wrong PHY ID */ 1124 if (reg == MII_PHYSID2) 1125 return 0xc912; 1126 1127 r8168dp_2_mdio_start(tp); 1128 1129 value = r8169_mdio_read(tp, reg); 1130 1131 r8168dp_2_mdio_stop(tp); 1132 1133 return value; 1134 } 1135 1136 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1137 { 1138 switch (tp->mac_version) { 1139 case RTL_GIGA_MAC_VER_28: 1140 case RTL_GIGA_MAC_VER_31: 1141 r8168dp_2_mdio_write(tp, location, val); 1142 break; 1143 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1144 r8168g_mdio_write(tp, location, val); 1145 break; 1146 default: 1147 r8169_mdio_write(tp, location, val); 1148 break; 1149 } 1150 } 1151 1152 static int rtl_readphy(struct rtl8169_private *tp, int location) 1153 { 1154 switch (tp->mac_version) { 1155 case RTL_GIGA_MAC_VER_28: 1156 case RTL_GIGA_MAC_VER_31: 1157 return r8168dp_2_mdio_read(tp, location); 1158 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1159 return r8168g_mdio_read(tp, location); 1160 default: 1161 return r8169_mdio_read(tp, location); 1162 } 1163 } 1164 1165 DECLARE_RTL_COND(rtl_ephyar_cond) 1166 { 1167 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1168 } 1169 1170 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1171 { 1172 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1173 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1174 1175 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1176 1177 udelay(10); 1178 } 1179 1180 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1181 { 1182 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1183 1184 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1185 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1186 } 1187 1188 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1189 { 1190 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1191 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1192 RTL_R32(tp, OCPDR) : ~0; 1193 } 1194 1195 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1196 { 1197 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1198 } 1199 1200 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1201 u32 data) 1202 { 1203 RTL_W32(tp, OCPDR, data); 1204 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1205 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1206 } 1207 1208 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1209 u32 data) 1210 { 1211 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1212 data, ERIAR_OOB); 1213 } 1214 1215 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1216 { 1217 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1218 1219 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1220 } 1221 1222 #define OOB_CMD_RESET 0x00 1223 #define OOB_CMD_DRIVER_START 0x05 1224 #define OOB_CMD_DRIVER_STOP 0x06 1225 1226 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1227 { 1228 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1229 } 1230 1231 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1232 { 1233 u16 reg; 1234 1235 reg = rtl8168_get_ocp_reg(tp); 1236 1237 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1238 } 1239 1240 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1241 { 1242 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1243 } 1244 1245 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1246 { 1247 return RTL_R8(tp, IBISR0) & 0x20; 1248 } 1249 1250 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1251 { 1252 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1253 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1254 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1255 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1256 } 1257 1258 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1259 { 1260 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1261 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1262 } 1263 1264 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1265 { 1266 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1267 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1268 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1269 } 1270 1271 static void rtl8168_driver_start(struct rtl8169_private *tp) 1272 { 1273 if (tp->dash_type == RTL_DASH_DP) 1274 rtl8168dp_driver_start(tp); 1275 else 1276 rtl8168ep_driver_start(tp); 1277 } 1278 1279 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1280 { 1281 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1282 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1283 } 1284 1285 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1286 { 1287 rtl8168ep_stop_cmac(tp); 1288 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1289 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1290 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1291 } 1292 1293 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1294 { 1295 if (tp->dash_type == RTL_DASH_DP) 1296 rtl8168dp_driver_stop(tp); 1297 else 1298 rtl8168ep_driver_stop(tp); 1299 } 1300 1301 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1302 { 1303 u16 reg = rtl8168_get_ocp_reg(tp); 1304 1305 return r8168dp_ocp_read(tp, reg) & BIT(15); 1306 } 1307 1308 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1309 { 1310 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1311 } 1312 1313 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1314 { 1315 switch (tp->dash_type) { 1316 case RTL_DASH_DP: 1317 return r8168dp_check_dash(tp); 1318 case RTL_DASH_EP: 1319 return r8168ep_check_dash(tp); 1320 default: 1321 return false; 1322 } 1323 } 1324 1325 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1326 { 1327 switch (tp->mac_version) { 1328 case RTL_GIGA_MAC_VER_28: 1329 case RTL_GIGA_MAC_VER_31: 1330 return RTL_DASH_DP; 1331 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1332 return RTL_DASH_EP; 1333 default: 1334 return RTL_DASH_NONE; 1335 } 1336 } 1337 1338 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1339 { 1340 switch (tp->mac_version) { 1341 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1342 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1343 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1344 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1345 if (enable) 1346 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1347 else 1348 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1349 break; 1350 default: 1351 break; 1352 } 1353 } 1354 1355 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1356 { 1357 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1358 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1359 } 1360 1361 DECLARE_RTL_COND(rtl_efusear_cond) 1362 { 1363 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1364 } 1365 1366 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1367 { 1368 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1369 1370 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1371 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1372 } 1373 1374 static u32 rtl_get_events(struct rtl8169_private *tp) 1375 { 1376 if (rtl_is_8125(tp)) 1377 return RTL_R32(tp, IntrStatus_8125); 1378 else 1379 return RTL_R16(tp, IntrStatus); 1380 } 1381 1382 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1383 { 1384 if (rtl_is_8125(tp)) 1385 RTL_W32(tp, IntrStatus_8125, bits); 1386 else 1387 RTL_W16(tp, IntrStatus, bits); 1388 } 1389 1390 static void rtl_irq_disable(struct rtl8169_private *tp) 1391 { 1392 if (rtl_is_8125(tp)) 1393 RTL_W32(tp, IntrMask_8125, 0); 1394 else 1395 RTL_W16(tp, IntrMask, 0); 1396 } 1397 1398 static void rtl_irq_enable(struct rtl8169_private *tp) 1399 { 1400 if (rtl_is_8125(tp)) 1401 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1402 else 1403 RTL_W16(tp, IntrMask, tp->irq_mask); 1404 } 1405 1406 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1407 { 1408 rtl_irq_disable(tp); 1409 rtl_ack_events(tp, 0xffffffff); 1410 rtl_pci_commit(tp); 1411 } 1412 1413 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1414 { 1415 struct phy_device *phydev = tp->phydev; 1416 1417 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1418 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1419 if (phydev->speed == SPEED_1000) { 1420 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1421 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1422 } else if (phydev->speed == SPEED_100) { 1423 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1424 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1425 } else { 1426 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1427 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1428 } 1429 rtl_reset_packet_filter(tp); 1430 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1431 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1432 if (phydev->speed == SPEED_1000) { 1433 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1434 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1435 } else { 1436 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1437 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1438 } 1439 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1440 if (phydev->speed == SPEED_10) { 1441 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1442 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1443 } else { 1444 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1445 } 1446 } 1447 } 1448 1449 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1450 1451 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1452 { 1453 struct rtl8169_private *tp = netdev_priv(dev); 1454 1455 wol->supported = WAKE_ANY; 1456 wol->wolopts = tp->saved_wolopts; 1457 } 1458 1459 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1460 { 1461 static const struct { 1462 u32 opt; 1463 u16 reg; 1464 u8 mask; 1465 } cfg[] = { 1466 { WAKE_PHY, Config3, LinkUp }, 1467 { WAKE_UCAST, Config5, UWF }, 1468 { WAKE_BCAST, Config5, BWF }, 1469 { WAKE_MCAST, Config5, MWF }, 1470 { WAKE_ANY, Config5, LanWake }, 1471 { WAKE_MAGIC, Config3, MagicPacket } 1472 }; 1473 unsigned int i, tmp = ARRAY_SIZE(cfg); 1474 unsigned long flags; 1475 u8 options; 1476 1477 rtl_unlock_config_regs(tp); 1478 1479 if (rtl_is_8168evl_up(tp)) { 1480 tmp--; 1481 if (wolopts & WAKE_MAGIC) 1482 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1483 else 1484 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1485 } else if (rtl_is_8125(tp)) { 1486 tmp--; 1487 if (wolopts & WAKE_MAGIC) 1488 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1489 else 1490 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1491 } 1492 1493 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1494 for (i = 0; i < tmp; i++) { 1495 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1496 if (wolopts & cfg[i].opt) 1497 options |= cfg[i].mask; 1498 RTL_W8(tp, cfg[i].reg, options); 1499 } 1500 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1501 1502 switch (tp->mac_version) { 1503 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1504 options = RTL_R8(tp, Config1) & ~PMEnable; 1505 if (wolopts) 1506 options |= PMEnable; 1507 RTL_W8(tp, Config1, options); 1508 break; 1509 case RTL_GIGA_MAC_VER_34: 1510 case RTL_GIGA_MAC_VER_37: 1511 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1512 if (wolopts) 1513 rtl_mod_config2(tp, 0, PME_SIGNAL); 1514 else 1515 rtl_mod_config2(tp, PME_SIGNAL, 0); 1516 break; 1517 default: 1518 break; 1519 } 1520 1521 rtl_lock_config_regs(tp); 1522 1523 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1524 1525 if (!tp->dash_enabled) { 1526 rtl_set_d3_pll_down(tp, !wolopts); 1527 tp->dev->wol_enabled = wolopts ? 1 : 0; 1528 } 1529 } 1530 1531 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1532 { 1533 struct rtl8169_private *tp = netdev_priv(dev); 1534 1535 if (wol->wolopts & ~WAKE_ANY) 1536 return -EINVAL; 1537 1538 tp->saved_wolopts = wol->wolopts; 1539 __rtl8169_set_wol(tp, tp->saved_wolopts); 1540 1541 return 0; 1542 } 1543 1544 static void rtl8169_get_drvinfo(struct net_device *dev, 1545 struct ethtool_drvinfo *info) 1546 { 1547 struct rtl8169_private *tp = netdev_priv(dev); 1548 struct rtl_fw *rtl_fw = tp->rtl_fw; 1549 1550 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1551 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1552 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1553 if (rtl_fw) 1554 strscpy(info->fw_version, rtl_fw->version, 1555 sizeof(info->fw_version)); 1556 } 1557 1558 static int rtl8169_get_regs_len(struct net_device *dev) 1559 { 1560 return R8169_REGS_SIZE; 1561 } 1562 1563 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1564 netdev_features_t features) 1565 { 1566 struct rtl8169_private *tp = netdev_priv(dev); 1567 1568 if (dev->mtu > TD_MSS_MAX) 1569 features &= ~NETIF_F_ALL_TSO; 1570 1571 if (dev->mtu > ETH_DATA_LEN && 1572 tp->mac_version > RTL_GIGA_MAC_VER_06) 1573 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1574 1575 return features; 1576 } 1577 1578 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1579 netdev_features_t features) 1580 { 1581 u32 rx_config = RTL_R32(tp, RxConfig); 1582 1583 if (features & NETIF_F_RXALL) 1584 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1585 else 1586 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1587 1588 if (rtl_is_8125(tp)) { 1589 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1590 rx_config |= RX_VLAN_8125; 1591 else 1592 rx_config &= ~RX_VLAN_8125; 1593 } 1594 1595 RTL_W32(tp, RxConfig, rx_config); 1596 } 1597 1598 static int rtl8169_set_features(struct net_device *dev, 1599 netdev_features_t features) 1600 { 1601 struct rtl8169_private *tp = netdev_priv(dev); 1602 1603 rtl_set_rx_config_features(tp, features); 1604 1605 if (features & NETIF_F_RXCSUM) 1606 tp->cp_cmd |= RxChkSum; 1607 else 1608 tp->cp_cmd &= ~RxChkSum; 1609 1610 if (!rtl_is_8125(tp)) { 1611 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1612 tp->cp_cmd |= RxVlan; 1613 else 1614 tp->cp_cmd &= ~RxVlan; 1615 } 1616 1617 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1618 rtl_pci_commit(tp); 1619 1620 return 0; 1621 } 1622 1623 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1624 { 1625 return (skb_vlan_tag_present(skb)) ? 1626 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1627 } 1628 1629 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1630 { 1631 u32 opts2 = le32_to_cpu(desc->opts2); 1632 1633 if (opts2 & RxVlanTag) 1634 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1635 } 1636 1637 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1638 void *p) 1639 { 1640 struct rtl8169_private *tp = netdev_priv(dev); 1641 u32 __iomem *data = tp->mmio_addr; 1642 u32 *dw = p; 1643 int i; 1644 1645 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1646 memcpy_fromio(dw++, data++, 4); 1647 } 1648 1649 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1650 "tx_packets", 1651 "rx_packets", 1652 "tx_errors", 1653 "rx_errors", 1654 "rx_missed", 1655 "align_errors", 1656 "tx_single_collisions", 1657 "tx_multi_collisions", 1658 "unicast", 1659 "broadcast", 1660 "multicast", 1661 "tx_aborted", 1662 "tx_underrun", 1663 }; 1664 1665 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1666 { 1667 switch (sset) { 1668 case ETH_SS_STATS: 1669 return ARRAY_SIZE(rtl8169_gstrings); 1670 default: 1671 return -EOPNOTSUPP; 1672 } 1673 } 1674 1675 DECLARE_RTL_COND(rtl_counters_cond) 1676 { 1677 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1678 } 1679 1680 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1681 { 1682 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1683 1684 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1685 rtl_pci_commit(tp); 1686 RTL_W32(tp, CounterAddrLow, cmd); 1687 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1688 1689 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1690 } 1691 1692 static void rtl8169_update_counters(struct rtl8169_private *tp) 1693 { 1694 u8 val = RTL_R8(tp, ChipCmd); 1695 1696 /* 1697 * Some chips are unable to dump tally counters when the receiver 1698 * is disabled. If 0xff chip may be in a PCI power-save state. 1699 */ 1700 if (val & CmdRxEnb && val != 0xff) 1701 rtl8169_do_counters(tp, CounterDump); 1702 } 1703 1704 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1705 { 1706 struct rtl8169_counters *counters = tp->counters; 1707 1708 /* 1709 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1710 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1711 * reset by a power cycle, while the counter values collected by the 1712 * driver are reset at every driver unload/load cycle. 1713 * 1714 * To make sure the HW values returned by @get_stats64 match the SW 1715 * values, we collect the initial values at first open(*) and use them 1716 * as offsets to normalize the values returned by @get_stats64. 1717 * 1718 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1719 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1720 * set at open time by rtl_hw_start. 1721 */ 1722 1723 if (tp->tc_offset.inited) 1724 return; 1725 1726 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1727 rtl8169_do_counters(tp, CounterReset); 1728 } else { 1729 rtl8169_update_counters(tp); 1730 tp->tc_offset.tx_errors = counters->tx_errors; 1731 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1732 tp->tc_offset.tx_aborted = counters->tx_aborted; 1733 tp->tc_offset.rx_missed = counters->rx_missed; 1734 } 1735 1736 tp->tc_offset.inited = true; 1737 } 1738 1739 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1740 struct ethtool_stats *stats, u64 *data) 1741 { 1742 struct rtl8169_private *tp = netdev_priv(dev); 1743 struct rtl8169_counters *counters; 1744 1745 counters = tp->counters; 1746 rtl8169_update_counters(tp); 1747 1748 data[0] = le64_to_cpu(counters->tx_packets); 1749 data[1] = le64_to_cpu(counters->rx_packets); 1750 data[2] = le64_to_cpu(counters->tx_errors); 1751 data[3] = le32_to_cpu(counters->rx_errors); 1752 data[4] = le16_to_cpu(counters->rx_missed); 1753 data[5] = le16_to_cpu(counters->align_errors); 1754 data[6] = le32_to_cpu(counters->tx_one_collision); 1755 data[7] = le32_to_cpu(counters->tx_multi_collision); 1756 data[8] = le64_to_cpu(counters->rx_unicast); 1757 data[9] = le64_to_cpu(counters->rx_broadcast); 1758 data[10] = le32_to_cpu(counters->rx_multicast); 1759 data[11] = le16_to_cpu(counters->tx_aborted); 1760 data[12] = le16_to_cpu(counters->tx_underun); 1761 } 1762 1763 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1764 { 1765 switch(stringset) { 1766 case ETH_SS_STATS: 1767 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1768 break; 1769 } 1770 } 1771 1772 /* 1773 * Interrupt coalescing 1774 * 1775 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1776 * > 8169, 8168 and 810x line of chipsets 1777 * 1778 * 8169, 8168, and 8136(810x) serial chipsets support it. 1779 * 1780 * > 2 - the Tx timer unit at gigabit speed 1781 * 1782 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1783 * (0xe0) bit 1 and bit 0. 1784 * 1785 * For 8169 1786 * bit[1:0] \ speed 1000M 100M 10M 1787 * 0 0 320ns 2.56us 40.96us 1788 * 0 1 2.56us 20.48us 327.7us 1789 * 1 0 5.12us 40.96us 655.4us 1790 * 1 1 10.24us 81.92us 1.31ms 1791 * 1792 * For the other 1793 * bit[1:0] \ speed 1000M 100M 10M 1794 * 0 0 5us 2.56us 40.96us 1795 * 0 1 40us 20.48us 327.7us 1796 * 1 0 80us 40.96us 655.4us 1797 * 1 1 160us 81.92us 1.31ms 1798 */ 1799 1800 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1801 struct rtl_coalesce_info { 1802 u32 speed; 1803 u32 scale_nsecs[4]; 1804 }; 1805 1806 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1807 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1808 1809 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1810 { SPEED_1000, COALESCE_DELAY(320) }, 1811 { SPEED_100, COALESCE_DELAY(2560) }, 1812 { SPEED_10, COALESCE_DELAY(40960) }, 1813 { 0 }, 1814 }; 1815 1816 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1817 { SPEED_1000, COALESCE_DELAY(5000) }, 1818 { SPEED_100, COALESCE_DELAY(2560) }, 1819 { SPEED_10, COALESCE_DELAY(40960) }, 1820 { 0 }, 1821 }; 1822 #undef COALESCE_DELAY 1823 1824 /* get rx/tx scale vector corresponding to current speed */ 1825 static const struct rtl_coalesce_info * 1826 rtl_coalesce_info(struct rtl8169_private *tp) 1827 { 1828 const struct rtl_coalesce_info *ci; 1829 1830 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1831 ci = rtl_coalesce_info_8169; 1832 else 1833 ci = rtl_coalesce_info_8168_8136; 1834 1835 /* if speed is unknown assume highest one */ 1836 if (tp->phydev->speed == SPEED_UNKNOWN) 1837 return ci; 1838 1839 for (; ci->speed; ci++) { 1840 if (tp->phydev->speed == ci->speed) 1841 return ci; 1842 } 1843 1844 return ERR_PTR(-ELNRNG); 1845 } 1846 1847 static int rtl_get_coalesce(struct net_device *dev, 1848 struct ethtool_coalesce *ec, 1849 struct kernel_ethtool_coalesce *kernel_coal, 1850 struct netlink_ext_ack *extack) 1851 { 1852 struct rtl8169_private *tp = netdev_priv(dev); 1853 const struct rtl_coalesce_info *ci; 1854 u32 scale, c_us, c_fr; 1855 u16 intrmit; 1856 1857 if (rtl_is_8125(tp)) 1858 return -EOPNOTSUPP; 1859 1860 memset(ec, 0, sizeof(*ec)); 1861 1862 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1863 ci = rtl_coalesce_info(tp); 1864 if (IS_ERR(ci)) 1865 return PTR_ERR(ci); 1866 1867 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1868 1869 intrmit = RTL_R16(tp, IntrMitigate); 1870 1871 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1872 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1873 1874 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1875 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1876 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1877 1878 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1879 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1880 1881 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1882 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1883 1884 return 0; 1885 } 1886 1887 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1888 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1889 u16 *cp01) 1890 { 1891 const struct rtl_coalesce_info *ci; 1892 u16 i; 1893 1894 ci = rtl_coalesce_info(tp); 1895 if (IS_ERR(ci)) 1896 return PTR_ERR(ci); 1897 1898 for (i = 0; i < 4; i++) { 1899 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1900 *cp01 = i; 1901 return ci->scale_nsecs[i]; 1902 } 1903 } 1904 1905 return -ERANGE; 1906 } 1907 1908 static int rtl_set_coalesce(struct net_device *dev, 1909 struct ethtool_coalesce *ec, 1910 struct kernel_ethtool_coalesce *kernel_coal, 1911 struct netlink_ext_ack *extack) 1912 { 1913 struct rtl8169_private *tp = netdev_priv(dev); 1914 u32 tx_fr = ec->tx_max_coalesced_frames; 1915 u32 rx_fr = ec->rx_max_coalesced_frames; 1916 u32 coal_usec_max, units; 1917 u16 w = 0, cp01 = 0; 1918 int scale; 1919 1920 if (rtl_is_8125(tp)) 1921 return -EOPNOTSUPP; 1922 1923 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1924 return -ERANGE; 1925 1926 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1927 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1928 if (scale < 0) 1929 return scale; 1930 1931 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1932 * not only when usecs=0 because of e.g. the following scenario: 1933 * 1934 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1935 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1936 * - then user does `ethtool -C eth0 rx-usecs 100` 1937 * 1938 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1939 * if we want to ignore rx_frames then it has to be set to 0. 1940 */ 1941 if (rx_fr == 1) 1942 rx_fr = 0; 1943 if (tx_fr == 1) 1944 tx_fr = 0; 1945 1946 /* HW requires time limit to be set if frame limit is set */ 1947 if ((tx_fr && !ec->tx_coalesce_usecs) || 1948 (rx_fr && !ec->rx_coalesce_usecs)) 1949 return -EINVAL; 1950 1951 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1952 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1953 1954 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1955 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1956 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1957 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1958 1959 RTL_W16(tp, IntrMitigate, w); 1960 1961 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1962 if (rtl_is_8168evl_up(tp)) { 1963 if (!rx_fr && !tx_fr) 1964 /* disable packet counter */ 1965 tp->cp_cmd |= PktCntrDisable; 1966 else 1967 tp->cp_cmd &= ~PktCntrDisable; 1968 } 1969 1970 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1971 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1972 rtl_pci_commit(tp); 1973 1974 return 0; 1975 } 1976 1977 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1978 { 1979 struct rtl8169_private *tp = netdev_priv(dev); 1980 1981 if (!rtl_supports_eee(tp)) 1982 return -EOPNOTSUPP; 1983 1984 return phy_ethtool_get_eee(tp->phydev, data); 1985 } 1986 1987 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1988 { 1989 struct rtl8169_private *tp = netdev_priv(dev); 1990 int ret; 1991 1992 if (!rtl_supports_eee(tp)) 1993 return -EOPNOTSUPP; 1994 1995 ret = phy_ethtool_set_eee(tp->phydev, data); 1996 1997 if (!ret) 1998 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1999 MDIO_AN_EEE_ADV); 2000 return ret; 2001 } 2002 2003 static void rtl8169_get_ringparam(struct net_device *dev, 2004 struct ethtool_ringparam *data, 2005 struct kernel_ethtool_ringparam *kernel_data, 2006 struct netlink_ext_ack *extack) 2007 { 2008 data->rx_max_pending = NUM_RX_DESC; 2009 data->rx_pending = NUM_RX_DESC; 2010 data->tx_max_pending = NUM_TX_DESC; 2011 data->tx_pending = NUM_TX_DESC; 2012 } 2013 2014 static void rtl8169_get_pauseparam(struct net_device *dev, 2015 struct ethtool_pauseparam *data) 2016 { 2017 struct rtl8169_private *tp = netdev_priv(dev); 2018 bool tx_pause, rx_pause; 2019 2020 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2021 2022 data->autoneg = tp->phydev->autoneg; 2023 data->tx_pause = tx_pause ? 1 : 0; 2024 data->rx_pause = rx_pause ? 1 : 0; 2025 } 2026 2027 static int rtl8169_set_pauseparam(struct net_device *dev, 2028 struct ethtool_pauseparam *data) 2029 { 2030 struct rtl8169_private *tp = netdev_priv(dev); 2031 2032 if (dev->mtu > ETH_DATA_LEN) 2033 return -EOPNOTSUPP; 2034 2035 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2036 2037 return 0; 2038 } 2039 2040 static const struct ethtool_ops rtl8169_ethtool_ops = { 2041 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2042 ETHTOOL_COALESCE_MAX_FRAMES, 2043 .get_drvinfo = rtl8169_get_drvinfo, 2044 .get_regs_len = rtl8169_get_regs_len, 2045 .get_link = ethtool_op_get_link, 2046 .get_coalesce = rtl_get_coalesce, 2047 .set_coalesce = rtl_set_coalesce, 2048 .get_regs = rtl8169_get_regs, 2049 .get_wol = rtl8169_get_wol, 2050 .set_wol = rtl8169_set_wol, 2051 .get_strings = rtl8169_get_strings, 2052 .get_sset_count = rtl8169_get_sset_count, 2053 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2054 .get_ts_info = ethtool_op_get_ts_info, 2055 .nway_reset = phy_ethtool_nway_reset, 2056 .get_eee = rtl8169_get_eee, 2057 .set_eee = rtl8169_set_eee, 2058 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2059 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2060 .get_ringparam = rtl8169_get_ringparam, 2061 .get_pauseparam = rtl8169_get_pauseparam, 2062 .set_pauseparam = rtl8169_set_pauseparam, 2063 }; 2064 2065 static void rtl_enable_eee(struct rtl8169_private *tp) 2066 { 2067 struct phy_device *phydev = tp->phydev; 2068 int adv; 2069 2070 /* respect EEE advertisement the user may have set */ 2071 if (tp->eee_adv >= 0) 2072 adv = tp->eee_adv; 2073 else 2074 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2075 2076 if (adv >= 0) 2077 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2078 } 2079 2080 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2081 { 2082 /* 2083 * The driver currently handles the 8168Bf and the 8168Be identically 2084 * but they can be identified more specifically through the test below 2085 * if needed: 2086 * 2087 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2088 * 2089 * Same thing for the 8101Eb and the 8101Ec: 2090 * 2091 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2092 */ 2093 static const struct rtl_mac_info { 2094 u16 mask; 2095 u16 val; 2096 enum mac_version ver; 2097 } mac_info[] = { 2098 /* 8125B family. */ 2099 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2100 2101 /* 8125A family. */ 2102 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2103 /* It seems only XID 609 made it to the mass market. 2104 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2105 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2106 */ 2107 2108 /* RTL8117 */ 2109 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2110 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2111 2112 /* 8168EP family. */ 2113 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2114 /* It seems this chip version never made it to 2115 * the wild. Let's disable detection. 2116 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2117 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2118 */ 2119 2120 /* 8168H family. */ 2121 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2122 /* It seems this chip version never made it to 2123 * the wild. Let's disable detection. 2124 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2125 */ 2126 2127 /* 8168G family. */ 2128 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2129 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2130 /* It seems this chip version never made it to 2131 * the wild. Let's disable detection. 2132 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2133 */ 2134 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2135 2136 /* 8168F family. */ 2137 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2138 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2139 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2140 2141 /* 8168E family. */ 2142 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2143 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2144 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2145 2146 /* 8168D family. */ 2147 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2148 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2149 2150 /* 8168DP family. */ 2151 /* It seems this early RTL8168dp version never made it to 2152 * the wild. Support has been removed. 2153 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2154 */ 2155 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2156 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2157 2158 /* 8168C family. */ 2159 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2160 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2161 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2162 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2163 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2164 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2165 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2166 2167 /* 8168B family. */ 2168 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2169 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2170 2171 /* 8101 family. */ 2172 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2173 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2174 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2175 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2176 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2177 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2178 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2179 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2180 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2181 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2182 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2183 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2184 2185 /* 8110 family. */ 2186 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2187 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2188 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2189 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2190 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2191 2192 /* Catch-all */ 2193 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2194 }; 2195 const struct rtl_mac_info *p = mac_info; 2196 enum mac_version ver; 2197 2198 while ((xid & p->mask) != p->val) 2199 p++; 2200 ver = p->ver; 2201 2202 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2203 if (ver == RTL_GIGA_MAC_VER_42) 2204 ver = RTL_GIGA_MAC_VER_43; 2205 else if (ver == RTL_GIGA_MAC_VER_46) 2206 ver = RTL_GIGA_MAC_VER_48; 2207 } 2208 2209 return ver; 2210 } 2211 2212 static void rtl_release_firmware(struct rtl8169_private *tp) 2213 { 2214 if (tp->rtl_fw) { 2215 rtl_fw_release_firmware(tp->rtl_fw); 2216 kfree(tp->rtl_fw); 2217 tp->rtl_fw = NULL; 2218 } 2219 } 2220 2221 void r8169_apply_firmware(struct rtl8169_private *tp) 2222 { 2223 int val; 2224 2225 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2226 if (tp->rtl_fw) { 2227 rtl_fw_write_firmware(tp, tp->rtl_fw); 2228 /* At least one firmware doesn't reset tp->ocp_base. */ 2229 tp->ocp_base = OCP_STD_PHY_BASE; 2230 2231 /* PHY soft reset may still be in progress */ 2232 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2233 !(val & BMCR_RESET), 2234 50000, 600000, true); 2235 } 2236 } 2237 2238 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2239 { 2240 /* Adjust EEE LED frequency */ 2241 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2242 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2243 2244 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2245 } 2246 2247 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2248 { 2249 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2250 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2251 } 2252 2253 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2254 { 2255 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2256 } 2257 2258 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2259 { 2260 rtl8125_set_eee_txidle_timer(tp); 2261 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2262 } 2263 2264 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2265 { 2266 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2267 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2268 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2269 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2270 } 2271 2272 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2273 { 2274 u16 data1, data2, ioffset; 2275 2276 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2277 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2278 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2279 2280 ioffset = (data2 >> 1) & 0x7ff8; 2281 ioffset |= data2 & 0x0007; 2282 if (data1 & BIT(7)) 2283 ioffset |= BIT(15); 2284 2285 return ioffset; 2286 } 2287 2288 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2289 { 2290 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 2291 return; 2292 2293 set_bit(flag, tp->wk.flags); 2294 schedule_work(&tp->wk.work); 2295 } 2296 2297 static void rtl8169_init_phy(struct rtl8169_private *tp) 2298 { 2299 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2300 2301 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2302 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2303 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2304 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2305 RTL_W8(tp, 0x82, 0x01); 2306 } 2307 2308 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2309 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2310 tp->pci_dev->subsystem_device == 0xe000) 2311 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2312 2313 /* We may have called phy_speed_down before */ 2314 phy_speed_up(tp->phydev); 2315 2316 if (rtl_supports_eee(tp)) 2317 rtl_enable_eee(tp); 2318 2319 genphy_soft_reset(tp->phydev); 2320 } 2321 2322 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2323 { 2324 rtl_unlock_config_regs(tp); 2325 2326 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2327 rtl_pci_commit(tp); 2328 2329 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2330 rtl_pci_commit(tp); 2331 2332 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2333 rtl_rar_exgmac_set(tp, addr); 2334 2335 rtl_lock_config_regs(tp); 2336 } 2337 2338 static int rtl_set_mac_address(struct net_device *dev, void *p) 2339 { 2340 struct rtl8169_private *tp = netdev_priv(dev); 2341 int ret; 2342 2343 ret = eth_mac_addr(dev, p); 2344 if (ret) 2345 return ret; 2346 2347 rtl_rar_set(tp, dev->dev_addr); 2348 2349 return 0; 2350 } 2351 2352 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2353 { 2354 switch (tp->mac_version) { 2355 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2356 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2357 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2358 break; 2359 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2360 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2361 case RTL_GIGA_MAC_VER_38: 2362 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2363 break; 2364 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2365 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2366 break; 2367 case RTL_GIGA_MAC_VER_61: 2368 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2369 break; 2370 case RTL_GIGA_MAC_VER_63: 2371 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2372 RX_PAUSE_SLOT_ON); 2373 break; 2374 default: 2375 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2376 break; 2377 } 2378 } 2379 2380 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2381 { 2382 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2383 } 2384 2385 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2386 { 2387 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2388 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2389 } 2390 2391 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2392 { 2393 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2394 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2395 } 2396 2397 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2398 { 2399 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2400 } 2401 2402 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2403 { 2404 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2405 } 2406 2407 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2408 { 2409 RTL_W8(tp, MaxTxPacketSize, 0x24); 2410 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2411 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2412 } 2413 2414 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2415 { 2416 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2417 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2418 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2419 } 2420 2421 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2422 { 2423 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2424 } 2425 2426 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2427 { 2428 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2429 } 2430 2431 static void rtl_jumbo_config(struct rtl8169_private *tp) 2432 { 2433 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2434 int readrq = 4096; 2435 2436 rtl_unlock_config_regs(tp); 2437 switch (tp->mac_version) { 2438 case RTL_GIGA_MAC_VER_17: 2439 if (jumbo) { 2440 readrq = 512; 2441 r8168b_1_hw_jumbo_enable(tp); 2442 } else { 2443 r8168b_1_hw_jumbo_disable(tp); 2444 } 2445 break; 2446 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2447 if (jumbo) { 2448 readrq = 512; 2449 r8168c_hw_jumbo_enable(tp); 2450 } else { 2451 r8168c_hw_jumbo_disable(tp); 2452 } 2453 break; 2454 case RTL_GIGA_MAC_VER_28: 2455 if (jumbo) 2456 r8168dp_hw_jumbo_enable(tp); 2457 else 2458 r8168dp_hw_jumbo_disable(tp); 2459 break; 2460 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2461 if (jumbo) 2462 r8168e_hw_jumbo_enable(tp); 2463 else 2464 r8168e_hw_jumbo_disable(tp); 2465 break; 2466 default: 2467 break; 2468 } 2469 rtl_lock_config_regs(tp); 2470 2471 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2472 pcie_set_readrq(tp->pci_dev, readrq); 2473 2474 /* Chip doesn't support pause in jumbo mode */ 2475 if (jumbo) { 2476 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2477 tp->phydev->advertising); 2478 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2479 tp->phydev->advertising); 2480 phy_start_aneg(tp->phydev); 2481 } 2482 } 2483 2484 DECLARE_RTL_COND(rtl_chipcmd_cond) 2485 { 2486 return RTL_R8(tp, ChipCmd) & CmdReset; 2487 } 2488 2489 static void rtl_hw_reset(struct rtl8169_private *tp) 2490 { 2491 RTL_W8(tp, ChipCmd, CmdReset); 2492 2493 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2494 } 2495 2496 static void rtl_request_firmware(struct rtl8169_private *tp) 2497 { 2498 struct rtl_fw *rtl_fw; 2499 2500 /* firmware loaded already or no firmware available */ 2501 if (tp->rtl_fw || !tp->fw_name) 2502 return; 2503 2504 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2505 if (!rtl_fw) 2506 return; 2507 2508 rtl_fw->phy_write = rtl_writephy; 2509 rtl_fw->phy_read = rtl_readphy; 2510 rtl_fw->mac_mcu_write = mac_mcu_write; 2511 rtl_fw->mac_mcu_read = mac_mcu_read; 2512 rtl_fw->fw_name = tp->fw_name; 2513 rtl_fw->dev = tp_to_dev(tp); 2514 2515 if (rtl_fw_request_firmware(rtl_fw)) 2516 kfree(rtl_fw); 2517 else 2518 tp->rtl_fw = rtl_fw; 2519 } 2520 2521 static void rtl_rx_close(struct rtl8169_private *tp) 2522 { 2523 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2524 } 2525 2526 DECLARE_RTL_COND(rtl_npq_cond) 2527 { 2528 return RTL_R8(tp, TxPoll) & NPQ; 2529 } 2530 2531 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2532 { 2533 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2534 } 2535 2536 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2537 { 2538 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2539 } 2540 2541 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2542 { 2543 /* IntrMitigate has new functionality on RTL8125 */ 2544 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2545 } 2546 2547 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2548 { 2549 switch (tp->mac_version) { 2550 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2551 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2552 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2553 break; 2554 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2555 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2556 break; 2557 case RTL_GIGA_MAC_VER_63: 2558 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2559 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2560 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2561 break; 2562 default: 2563 break; 2564 } 2565 } 2566 2567 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2568 { 2569 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2570 } 2571 2572 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2573 { 2574 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2575 fsleep(2000); 2576 rtl_wait_txrx_fifo_empty(tp); 2577 } 2578 2579 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2580 { 2581 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2582 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2583 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2584 2585 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2586 rtl_disable_rxdvgate(tp); 2587 } 2588 2589 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2590 { 2591 if (tp->dash_enabled) 2592 return; 2593 2594 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2595 tp->mac_version == RTL_GIGA_MAC_VER_33) 2596 rtl_ephy_write(tp, 0x19, 0xff64); 2597 2598 if (device_may_wakeup(tp_to_dev(tp))) { 2599 phy_speed_down(tp->phydev, false); 2600 rtl_wol_enable_rx(tp); 2601 } 2602 } 2603 2604 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2605 { 2606 u32 val = TX_DMA_BURST << TxDMAShift | 2607 InterFrameGap << TxInterFrameGapShift; 2608 2609 if (rtl_is_8168evl_up(tp)) 2610 val |= TXCFG_AUTO_FIFO; 2611 2612 RTL_W32(tp, TxConfig, val); 2613 } 2614 2615 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2616 { 2617 /* Low hurts. Let's disable the filtering. */ 2618 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2619 } 2620 2621 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2622 { 2623 /* 2624 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2625 * register to be written before TxDescAddrLow to work. 2626 * Switching from MMIO to I/O access fixes the issue as well. 2627 */ 2628 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2629 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2630 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2631 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2632 } 2633 2634 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2635 { 2636 u32 val; 2637 2638 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2639 val = 0x000fff00; 2640 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2641 val = 0x00ffff00; 2642 else 2643 return; 2644 2645 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2646 val |= 0xff; 2647 2648 RTL_W32(tp, 0x7c, val); 2649 } 2650 2651 static void rtl_set_rx_mode(struct net_device *dev) 2652 { 2653 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2654 /* Multicast hash filter */ 2655 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2656 struct rtl8169_private *tp = netdev_priv(dev); 2657 u32 tmp; 2658 2659 if (dev->flags & IFF_PROMISC) { 2660 rx_mode |= AcceptAllPhys; 2661 } else if (!(dev->flags & IFF_MULTICAST)) { 2662 rx_mode &= ~AcceptMulticast; 2663 } else if (dev->flags & IFF_ALLMULTI || 2664 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2665 /* accept all multicasts */ 2666 } else if (netdev_mc_empty(dev)) { 2667 rx_mode &= ~AcceptMulticast; 2668 } else { 2669 struct netdev_hw_addr *ha; 2670 2671 mc_filter[1] = mc_filter[0] = 0; 2672 netdev_for_each_mc_addr(ha, dev) { 2673 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2674 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2675 } 2676 2677 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2678 tmp = mc_filter[0]; 2679 mc_filter[0] = swab32(mc_filter[1]); 2680 mc_filter[1] = swab32(tmp); 2681 } 2682 } 2683 2684 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2685 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2686 2687 tmp = RTL_R32(tp, RxConfig); 2688 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2689 } 2690 2691 DECLARE_RTL_COND(rtl_csiar_cond) 2692 { 2693 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2694 } 2695 2696 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2697 { 2698 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2699 2700 RTL_W32(tp, CSIDR, value); 2701 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2702 CSIAR_BYTE_ENABLE | func << 16); 2703 2704 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2705 } 2706 2707 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2708 { 2709 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2710 2711 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2712 CSIAR_BYTE_ENABLE); 2713 2714 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2715 RTL_R32(tp, CSIDR) : ~0; 2716 } 2717 2718 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2719 { 2720 struct pci_dev *pdev = tp->pci_dev; 2721 u32 csi; 2722 2723 /* According to Realtek the value at config space address 0x070f 2724 * controls the L0s/L1 entrance latency. We try standard ECAM access 2725 * first and if it fails fall back to CSI. 2726 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2727 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2728 */ 2729 if (pdev->cfg_size > 0x070f && 2730 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2731 return; 2732 2733 netdev_notice_once(tp->dev, 2734 "No native access to PCI extended config space, falling back to CSI\n"); 2735 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2736 rtl_csi_write(tp, 0x070c, csi | val << 24); 2737 } 2738 2739 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2740 { 2741 /* L0 7us, L1 16us */ 2742 rtl_set_aspm_entry_latency(tp, 0x27); 2743 } 2744 2745 struct ephy_info { 2746 unsigned int offset; 2747 u16 mask; 2748 u16 bits; 2749 }; 2750 2751 static void __rtl_ephy_init(struct rtl8169_private *tp, 2752 const struct ephy_info *e, int len) 2753 { 2754 u16 w; 2755 2756 while (len-- > 0) { 2757 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2758 rtl_ephy_write(tp, e->offset, w); 2759 e++; 2760 } 2761 } 2762 2763 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2764 2765 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2766 { 2767 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2768 PCI_EXP_LNKCTL_CLKREQ_EN); 2769 } 2770 2771 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2772 { 2773 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2774 PCI_EXP_LNKCTL_CLKREQ_EN); 2775 } 2776 2777 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2778 { 2779 /* work around an issue when PCI reset occurs during L2/L3 state */ 2780 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2781 } 2782 2783 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2784 { 2785 /* Bits control which events trigger ASPM L1 exit: 2786 * Bit 12: rxdv 2787 * Bit 11: ltr_msg 2788 * Bit 10: txdma_poll 2789 * Bit 9: xadm 2790 * Bit 8: pktavi 2791 * Bit 7: txpla 2792 */ 2793 switch (tp->mac_version) { 2794 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2795 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2796 break; 2797 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2798 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2799 break; 2800 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2801 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2802 break; 2803 default: 2804 break; 2805 } 2806 } 2807 2808 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2809 { 2810 switch (tp->mac_version) { 2811 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2812 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2813 break; 2814 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2815 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2816 break; 2817 default: 2818 break; 2819 } 2820 } 2821 2822 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2823 { 2824 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2825 return; 2826 2827 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2828 if (enable && tp->aspm_manageable) { 2829 /* On these chip versions ASPM can even harm 2830 * bus communication of other PCI devices. 2831 */ 2832 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2833 tp->mac_version == RTL_GIGA_MAC_VER_43) 2834 return; 2835 2836 rtl_mod_config5(tp, 0, ASPM_en); 2837 rtl_mod_config2(tp, 0, ClkReqEn); 2838 2839 switch (tp->mac_version) { 2840 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2841 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2842 /* reset ephy tx/rx disable timer */ 2843 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2844 /* chip can trigger L1.2 */ 2845 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2846 break; 2847 default: 2848 break; 2849 } 2850 } else { 2851 switch (tp->mac_version) { 2852 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2853 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2854 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2855 break; 2856 default: 2857 break; 2858 } 2859 2860 rtl_mod_config2(tp, ClkReqEn, 0); 2861 rtl_mod_config5(tp, ASPM_en, 0); 2862 } 2863 } 2864 2865 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2866 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2867 { 2868 /* Usage of dynamic vs. static FIFO is controlled by bit 2869 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2870 */ 2871 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2872 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2873 } 2874 2875 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2876 u8 low, u8 high) 2877 { 2878 /* FIFO thresholds for pause flow control */ 2879 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2880 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2881 } 2882 2883 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2884 { 2885 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2886 } 2887 2888 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2889 { 2890 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2891 2892 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2893 2894 rtl_disable_clock_request(tp); 2895 } 2896 2897 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2898 { 2899 static const struct ephy_info e_info_8168cp[] = { 2900 { 0x01, 0, 0x0001 }, 2901 { 0x02, 0x0800, 0x1000 }, 2902 { 0x03, 0, 0x0042 }, 2903 { 0x06, 0x0080, 0x0000 }, 2904 { 0x07, 0, 0x2000 } 2905 }; 2906 2907 rtl_set_def_aspm_entry_latency(tp); 2908 2909 rtl_ephy_init(tp, e_info_8168cp); 2910 2911 __rtl_hw_start_8168cp(tp); 2912 } 2913 2914 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2915 { 2916 rtl_set_def_aspm_entry_latency(tp); 2917 2918 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2919 } 2920 2921 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2922 { 2923 rtl_set_def_aspm_entry_latency(tp); 2924 2925 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2926 2927 /* Magic. */ 2928 RTL_W8(tp, DBG_REG, 0x20); 2929 } 2930 2931 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2932 { 2933 static const struct ephy_info e_info_8168c_1[] = { 2934 { 0x02, 0x0800, 0x1000 }, 2935 { 0x03, 0, 0x0002 }, 2936 { 0x06, 0x0080, 0x0000 } 2937 }; 2938 2939 rtl_set_def_aspm_entry_latency(tp); 2940 2941 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2942 2943 rtl_ephy_init(tp, e_info_8168c_1); 2944 2945 __rtl_hw_start_8168cp(tp); 2946 } 2947 2948 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2949 { 2950 static const struct ephy_info e_info_8168c_2[] = { 2951 { 0x01, 0, 0x0001 }, 2952 { 0x03, 0x0400, 0x0020 } 2953 }; 2954 2955 rtl_set_def_aspm_entry_latency(tp); 2956 2957 rtl_ephy_init(tp, e_info_8168c_2); 2958 2959 __rtl_hw_start_8168cp(tp); 2960 } 2961 2962 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2963 { 2964 rtl_set_def_aspm_entry_latency(tp); 2965 2966 __rtl_hw_start_8168cp(tp); 2967 } 2968 2969 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2970 { 2971 rtl_set_def_aspm_entry_latency(tp); 2972 2973 rtl_disable_clock_request(tp); 2974 } 2975 2976 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2977 { 2978 static const struct ephy_info e_info_8168d_4[] = { 2979 { 0x0b, 0x0000, 0x0048 }, 2980 { 0x19, 0x0020, 0x0050 }, 2981 { 0x0c, 0x0100, 0x0020 }, 2982 { 0x10, 0x0004, 0x0000 }, 2983 }; 2984 2985 rtl_set_def_aspm_entry_latency(tp); 2986 2987 rtl_ephy_init(tp, e_info_8168d_4); 2988 2989 rtl_enable_clock_request(tp); 2990 } 2991 2992 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2993 { 2994 static const struct ephy_info e_info_8168e_1[] = { 2995 { 0x00, 0x0200, 0x0100 }, 2996 { 0x00, 0x0000, 0x0004 }, 2997 { 0x06, 0x0002, 0x0001 }, 2998 { 0x06, 0x0000, 0x0030 }, 2999 { 0x07, 0x0000, 0x2000 }, 3000 { 0x00, 0x0000, 0x0020 }, 3001 { 0x03, 0x5800, 0x2000 }, 3002 { 0x03, 0x0000, 0x0001 }, 3003 { 0x01, 0x0800, 0x1000 }, 3004 { 0x07, 0x0000, 0x4000 }, 3005 { 0x1e, 0x0000, 0x2000 }, 3006 { 0x19, 0xffff, 0xfe6c }, 3007 { 0x0a, 0x0000, 0x0040 } 3008 }; 3009 3010 rtl_set_def_aspm_entry_latency(tp); 3011 3012 rtl_ephy_init(tp, e_info_8168e_1); 3013 3014 rtl_disable_clock_request(tp); 3015 3016 /* Reset tx FIFO pointer */ 3017 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3018 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3019 3020 rtl_mod_config5(tp, Spi_en, 0); 3021 } 3022 3023 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3024 { 3025 static const struct ephy_info e_info_8168e_2[] = { 3026 { 0x09, 0x0000, 0x0080 }, 3027 { 0x19, 0x0000, 0x0224 }, 3028 { 0x00, 0x0000, 0x0004 }, 3029 { 0x0c, 0x3df0, 0x0200 }, 3030 }; 3031 3032 rtl_set_def_aspm_entry_latency(tp); 3033 3034 rtl_ephy_init(tp, e_info_8168e_2); 3035 3036 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3037 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3038 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3039 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3040 rtl_reset_packet_filter(tp); 3041 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3042 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3043 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3044 3045 rtl_disable_clock_request(tp); 3046 3047 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3048 3049 rtl8168_config_eee_mac(tp); 3050 3051 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3052 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3053 rtl_mod_config5(tp, Spi_en, 0); 3054 } 3055 3056 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3057 { 3058 rtl_set_def_aspm_entry_latency(tp); 3059 3060 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3061 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3062 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3063 rtl_reset_packet_filter(tp); 3064 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3065 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3066 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3067 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3068 3069 rtl_disable_clock_request(tp); 3070 3071 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3072 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3073 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3074 rtl_mod_config5(tp, Spi_en, 0); 3075 3076 rtl8168_config_eee_mac(tp); 3077 } 3078 3079 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3080 { 3081 static const struct ephy_info e_info_8168f_1[] = { 3082 { 0x06, 0x00c0, 0x0020 }, 3083 { 0x08, 0x0001, 0x0002 }, 3084 { 0x09, 0x0000, 0x0080 }, 3085 { 0x19, 0x0000, 0x0224 }, 3086 { 0x00, 0x0000, 0x0008 }, 3087 { 0x0c, 0x3df0, 0x0200 }, 3088 }; 3089 3090 rtl_hw_start_8168f(tp); 3091 3092 rtl_ephy_init(tp, e_info_8168f_1); 3093 } 3094 3095 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3096 { 3097 static const struct ephy_info e_info_8168f_1[] = { 3098 { 0x06, 0x00c0, 0x0020 }, 3099 { 0x0f, 0xffff, 0x5200 }, 3100 { 0x19, 0x0000, 0x0224 }, 3101 { 0x00, 0x0000, 0x0008 }, 3102 { 0x0c, 0x3df0, 0x0200 }, 3103 }; 3104 3105 rtl_hw_start_8168f(tp); 3106 rtl_pcie_state_l2l3_disable(tp); 3107 3108 rtl_ephy_init(tp, e_info_8168f_1); 3109 } 3110 3111 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3112 { 3113 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3114 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3115 3116 rtl_set_def_aspm_entry_latency(tp); 3117 3118 rtl_reset_packet_filter(tp); 3119 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3120 3121 rtl_disable_rxdvgate(tp); 3122 3123 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3124 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3125 3126 rtl8168_config_eee_mac(tp); 3127 3128 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3129 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3130 3131 rtl_pcie_state_l2l3_disable(tp); 3132 } 3133 3134 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3135 { 3136 static const struct ephy_info e_info_8168g_1[] = { 3137 { 0x00, 0x0008, 0x0000 }, 3138 { 0x0c, 0x3ff0, 0x0820 }, 3139 { 0x1e, 0x0000, 0x0001 }, 3140 { 0x19, 0x8000, 0x0000 } 3141 }; 3142 3143 rtl_hw_start_8168g(tp); 3144 rtl_ephy_init(tp, e_info_8168g_1); 3145 } 3146 3147 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3148 { 3149 static const struct ephy_info e_info_8168g_2[] = { 3150 { 0x00, 0x0008, 0x0000 }, 3151 { 0x0c, 0x3ff0, 0x0820 }, 3152 { 0x19, 0xffff, 0x7c00 }, 3153 { 0x1e, 0xffff, 0x20eb }, 3154 { 0x0d, 0xffff, 0x1666 }, 3155 { 0x00, 0xffff, 0x10a3 }, 3156 { 0x06, 0xffff, 0xf050 }, 3157 { 0x04, 0x0000, 0x0010 }, 3158 { 0x1d, 0x4000, 0x0000 }, 3159 }; 3160 3161 rtl_hw_start_8168g(tp); 3162 rtl_ephy_init(tp, e_info_8168g_2); 3163 } 3164 3165 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3166 { 3167 static const u16 fix_data[] = { 3168 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3169 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3170 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3171 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3172 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3173 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3174 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3175 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3176 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3177 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3178 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3179 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3180 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3181 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3182 }; 3183 unsigned long flags; 3184 int i; 3185 3186 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3187 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3188 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3189 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3190 } 3191 3192 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3193 { 3194 static const struct ephy_info e_info_8411_2[] = { 3195 { 0x00, 0x0008, 0x0000 }, 3196 { 0x0c, 0x37d0, 0x0820 }, 3197 { 0x1e, 0x0000, 0x0001 }, 3198 { 0x19, 0x8021, 0x0000 }, 3199 { 0x1e, 0x0000, 0x2000 }, 3200 { 0x0d, 0x0100, 0x0200 }, 3201 { 0x00, 0x0000, 0x0080 }, 3202 { 0x06, 0x0000, 0x0010 }, 3203 { 0x04, 0x0000, 0x0010 }, 3204 { 0x1d, 0x0000, 0x4000 }, 3205 }; 3206 3207 rtl_hw_start_8168g(tp); 3208 3209 rtl_ephy_init(tp, e_info_8411_2); 3210 3211 /* The following Realtek-provided magic fixes an issue with the RX unit 3212 * getting confused after the PHY having been powered-down. 3213 */ 3214 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3215 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3216 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3217 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3218 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3219 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3220 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3221 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3222 mdelay(3); 3223 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3224 3225 rtl8411b_fix_phy_down(tp); 3226 3227 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3228 3229 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3230 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3231 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3232 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3233 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3234 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3235 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3236 } 3237 3238 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3239 { 3240 static const struct ephy_info e_info_8168h_1[] = { 3241 { 0x1e, 0x0800, 0x0001 }, 3242 { 0x1d, 0x0000, 0x0800 }, 3243 { 0x05, 0xffff, 0x2089 }, 3244 { 0x06, 0xffff, 0x5881 }, 3245 { 0x04, 0xffff, 0x854a }, 3246 { 0x01, 0xffff, 0x068b } 3247 }; 3248 int rg_saw_cnt; 3249 3250 rtl_ephy_init(tp, e_info_8168h_1); 3251 3252 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3253 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3254 3255 rtl_set_def_aspm_entry_latency(tp); 3256 3257 rtl_reset_packet_filter(tp); 3258 3259 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3260 3261 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3262 3263 rtl_disable_rxdvgate(tp); 3264 3265 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3266 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3267 3268 rtl8168_config_eee_mac(tp); 3269 3270 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3271 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3272 3273 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3274 3275 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3276 3277 rtl_pcie_state_l2l3_disable(tp); 3278 3279 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3280 if (rg_saw_cnt > 0) { 3281 u16 sw_cnt_1ms_ini; 3282 3283 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3284 sw_cnt_1ms_ini &= 0x0fff; 3285 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3286 } 3287 3288 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3289 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3290 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3291 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3292 3293 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3294 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3295 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3296 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3297 } 3298 3299 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3300 { 3301 rtl8168ep_stop_cmac(tp); 3302 3303 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3304 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3305 3306 rtl_set_def_aspm_entry_latency(tp); 3307 3308 rtl_reset_packet_filter(tp); 3309 3310 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3311 3312 rtl_disable_rxdvgate(tp); 3313 3314 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3315 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3316 3317 rtl8168_config_eee_mac(tp); 3318 3319 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3320 3321 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3322 3323 rtl_pcie_state_l2l3_disable(tp); 3324 } 3325 3326 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3327 { 3328 static const struct ephy_info e_info_8168ep_3[] = { 3329 { 0x00, 0x0000, 0x0080 }, 3330 { 0x0d, 0x0100, 0x0200 }, 3331 { 0x19, 0x8021, 0x0000 }, 3332 { 0x1e, 0x0000, 0x2000 }, 3333 }; 3334 3335 rtl_ephy_init(tp, e_info_8168ep_3); 3336 3337 rtl_hw_start_8168ep(tp); 3338 3339 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3340 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3341 3342 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3343 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3344 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3345 } 3346 3347 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3348 { 3349 static const struct ephy_info e_info_8117[] = { 3350 { 0x19, 0x0040, 0x1100 }, 3351 { 0x59, 0x0040, 0x1100 }, 3352 }; 3353 int rg_saw_cnt; 3354 3355 rtl8168ep_stop_cmac(tp); 3356 rtl_ephy_init(tp, e_info_8117); 3357 3358 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3359 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3360 3361 rtl_set_def_aspm_entry_latency(tp); 3362 3363 rtl_reset_packet_filter(tp); 3364 3365 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3366 3367 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3368 3369 rtl_disable_rxdvgate(tp); 3370 3371 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3372 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3373 3374 rtl8168_config_eee_mac(tp); 3375 3376 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3377 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3378 3379 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3380 3381 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3382 3383 rtl_pcie_state_l2l3_disable(tp); 3384 3385 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3386 if (rg_saw_cnt > 0) { 3387 u16 sw_cnt_1ms_ini; 3388 3389 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3390 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3391 } 3392 3393 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3394 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3395 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3396 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3397 3398 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3399 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3400 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3401 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3402 3403 /* firmware is for MAC only */ 3404 r8169_apply_firmware(tp); 3405 } 3406 3407 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3408 { 3409 static const struct ephy_info e_info_8102e_1[] = { 3410 { 0x01, 0, 0x6e65 }, 3411 { 0x02, 0, 0x091f }, 3412 { 0x03, 0, 0xc2f9 }, 3413 { 0x06, 0, 0xafb5 }, 3414 { 0x07, 0, 0x0e00 }, 3415 { 0x19, 0, 0xec80 }, 3416 { 0x01, 0, 0x2e65 }, 3417 { 0x01, 0, 0x6e65 } 3418 }; 3419 u8 cfg1; 3420 3421 rtl_set_def_aspm_entry_latency(tp); 3422 3423 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3424 3425 RTL_W8(tp, Config1, 3426 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3427 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3428 3429 cfg1 = RTL_R8(tp, Config1); 3430 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3431 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3432 3433 rtl_ephy_init(tp, e_info_8102e_1); 3434 } 3435 3436 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3437 { 3438 rtl_set_def_aspm_entry_latency(tp); 3439 3440 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3441 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3442 } 3443 3444 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3445 { 3446 rtl_hw_start_8102e_2(tp); 3447 3448 rtl_ephy_write(tp, 0x03, 0xc2f9); 3449 } 3450 3451 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3452 { 3453 static const struct ephy_info e_info_8401[] = { 3454 { 0x01, 0xffff, 0x6fe5 }, 3455 { 0x03, 0xffff, 0x0599 }, 3456 { 0x06, 0xffff, 0xaf25 }, 3457 { 0x07, 0xffff, 0x8e68 }, 3458 }; 3459 3460 rtl_ephy_init(tp, e_info_8401); 3461 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3462 } 3463 3464 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3465 { 3466 static const struct ephy_info e_info_8105e_1[] = { 3467 { 0x07, 0, 0x4000 }, 3468 { 0x19, 0, 0x0200 }, 3469 { 0x19, 0, 0x0020 }, 3470 { 0x1e, 0, 0x2000 }, 3471 { 0x03, 0, 0x0001 }, 3472 { 0x19, 0, 0x0100 }, 3473 { 0x19, 0, 0x0004 }, 3474 { 0x0a, 0, 0x0020 } 3475 }; 3476 3477 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3478 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3479 3480 /* Disable Early Tally Counter */ 3481 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3482 3483 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3484 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3485 3486 rtl_ephy_init(tp, e_info_8105e_1); 3487 3488 rtl_pcie_state_l2l3_disable(tp); 3489 } 3490 3491 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3492 { 3493 rtl_hw_start_8105e_1(tp); 3494 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3495 } 3496 3497 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3498 { 3499 static const struct ephy_info e_info_8402[] = { 3500 { 0x19, 0xffff, 0xff64 }, 3501 { 0x1e, 0, 0x4000 } 3502 }; 3503 3504 rtl_set_def_aspm_entry_latency(tp); 3505 3506 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3507 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3508 3509 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3510 3511 rtl_ephy_init(tp, e_info_8402); 3512 3513 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3514 rtl_reset_packet_filter(tp); 3515 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3516 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3517 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3518 3519 /* disable EEE */ 3520 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3521 3522 rtl_pcie_state_l2l3_disable(tp); 3523 } 3524 3525 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3526 { 3527 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3528 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3529 3530 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3531 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3532 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3533 3534 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3535 rtl_set_aspm_entry_latency(tp, 0x2f); 3536 3537 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3538 3539 /* disable EEE */ 3540 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3541 3542 rtl_pcie_state_l2l3_disable(tp); 3543 } 3544 3545 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3546 { 3547 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3548 } 3549 3550 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3551 { 3552 rtl_pcie_state_l2l3_disable(tp); 3553 3554 RTL_W16(tp, 0x382, 0x221b); 3555 RTL_W8(tp, 0x4500, 0); 3556 RTL_W16(tp, 0x4800, 0); 3557 3558 /* disable UPS */ 3559 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3560 3561 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3562 3563 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3564 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3565 3566 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3567 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3568 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3569 3570 /* disable new tx descriptor format */ 3571 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3572 3573 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3574 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3575 else 3576 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3577 3578 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3579 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3580 else 3581 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3582 3583 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3584 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3585 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3586 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3587 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3588 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3589 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3590 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3591 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3592 3593 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3594 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3595 udelay(1); 3596 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3597 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3598 3599 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3600 3601 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3602 3603 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3604 rtl8125b_config_eee_mac(tp); 3605 else 3606 rtl8125a_config_eee_mac(tp); 3607 3608 rtl_disable_rxdvgate(tp); 3609 } 3610 3611 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3612 { 3613 static const struct ephy_info e_info_8125a_2[] = { 3614 { 0x04, 0xffff, 0xd000 }, 3615 { 0x0a, 0xffff, 0x8653 }, 3616 { 0x23, 0xffff, 0xab66 }, 3617 { 0x20, 0xffff, 0x9455 }, 3618 { 0x21, 0xffff, 0x99ff }, 3619 { 0x29, 0xffff, 0xfe04 }, 3620 3621 { 0x44, 0xffff, 0xd000 }, 3622 { 0x4a, 0xffff, 0x8653 }, 3623 { 0x63, 0xffff, 0xab66 }, 3624 { 0x60, 0xffff, 0x9455 }, 3625 { 0x61, 0xffff, 0x99ff }, 3626 { 0x69, 0xffff, 0xfe04 }, 3627 }; 3628 3629 rtl_set_def_aspm_entry_latency(tp); 3630 rtl_ephy_init(tp, e_info_8125a_2); 3631 rtl_hw_start_8125_common(tp); 3632 } 3633 3634 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3635 { 3636 static const struct ephy_info e_info_8125b[] = { 3637 { 0x0b, 0xffff, 0xa908 }, 3638 { 0x1e, 0xffff, 0x20eb }, 3639 { 0x4b, 0xffff, 0xa908 }, 3640 { 0x5e, 0xffff, 0x20eb }, 3641 { 0x22, 0x0030, 0x0020 }, 3642 { 0x62, 0x0030, 0x0020 }, 3643 }; 3644 3645 rtl_set_def_aspm_entry_latency(tp); 3646 rtl_ephy_init(tp, e_info_8125b); 3647 rtl_hw_start_8125_common(tp); 3648 } 3649 3650 static void rtl_hw_config(struct rtl8169_private *tp) 3651 { 3652 static const rtl_generic_fct hw_configs[] = { 3653 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3654 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3655 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3656 [RTL_GIGA_MAC_VER_10] = NULL, 3657 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3658 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3659 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3660 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3661 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3662 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3663 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3664 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3665 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3666 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3667 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3668 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3669 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3670 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3671 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3672 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3673 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3674 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3675 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3676 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3677 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3678 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3679 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3680 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3681 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3682 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3683 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3684 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3685 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3686 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3687 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3688 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3689 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3690 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3691 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3692 }; 3693 3694 if (hw_configs[tp->mac_version]) 3695 hw_configs[tp->mac_version](tp); 3696 } 3697 3698 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3699 { 3700 int i; 3701 3702 /* disable interrupt coalescing */ 3703 for (i = 0xa00; i < 0xb00; i += 4) 3704 RTL_W32(tp, i, 0); 3705 3706 rtl_hw_config(tp); 3707 } 3708 3709 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3710 { 3711 if (rtl_is_8168evl_up(tp)) 3712 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3713 else 3714 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3715 3716 rtl_hw_config(tp); 3717 3718 /* disable interrupt coalescing */ 3719 RTL_W16(tp, IntrMitigate, 0x0000); 3720 } 3721 3722 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3723 { 3724 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3725 3726 tp->cp_cmd |= PCIMulRW; 3727 3728 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3729 tp->mac_version == RTL_GIGA_MAC_VER_03) 3730 tp->cp_cmd |= EnAnaPLL; 3731 3732 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3733 3734 rtl8169_set_magic_reg(tp); 3735 3736 /* disable interrupt coalescing */ 3737 RTL_W16(tp, IntrMitigate, 0x0000); 3738 } 3739 3740 static void rtl_hw_start(struct rtl8169_private *tp) 3741 { 3742 rtl_unlock_config_regs(tp); 3743 /* disable aspm and clock request before ephy access */ 3744 rtl_hw_aspm_clkreq_enable(tp, false); 3745 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3746 3747 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3748 rtl_hw_start_8169(tp); 3749 else if (rtl_is_8125(tp)) 3750 rtl_hw_start_8125(tp); 3751 else 3752 rtl_hw_start_8168(tp); 3753 3754 rtl_enable_exit_l1(tp); 3755 rtl_hw_aspm_clkreq_enable(tp, true); 3756 rtl_set_rx_max_size(tp); 3757 rtl_set_rx_tx_desc_registers(tp); 3758 rtl_lock_config_regs(tp); 3759 3760 rtl_jumbo_config(tp); 3761 3762 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3763 rtl_pci_commit(tp); 3764 3765 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3766 rtl_init_rxcfg(tp); 3767 rtl_set_tx_config_registers(tp); 3768 rtl_set_rx_config_features(tp, tp->dev->features); 3769 rtl_set_rx_mode(tp->dev); 3770 rtl_irq_enable(tp); 3771 } 3772 3773 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3774 { 3775 struct rtl8169_private *tp = netdev_priv(dev); 3776 3777 dev->mtu = new_mtu; 3778 netdev_update_features(dev); 3779 rtl_jumbo_config(tp); 3780 3781 switch (tp->mac_version) { 3782 case RTL_GIGA_MAC_VER_61: 3783 case RTL_GIGA_MAC_VER_63: 3784 rtl8125_set_eee_txidle_timer(tp); 3785 break; 3786 default: 3787 break; 3788 } 3789 3790 return 0; 3791 } 3792 3793 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3794 { 3795 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3796 3797 desc->opts2 = 0; 3798 /* Force memory writes to complete before releasing descriptor */ 3799 dma_wmb(); 3800 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3801 } 3802 3803 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3804 struct RxDesc *desc) 3805 { 3806 struct device *d = tp_to_dev(tp); 3807 int node = dev_to_node(d); 3808 dma_addr_t mapping; 3809 struct page *data; 3810 3811 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3812 if (!data) 3813 return NULL; 3814 3815 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3816 if (unlikely(dma_mapping_error(d, mapping))) { 3817 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3818 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3819 return NULL; 3820 } 3821 3822 desc->addr = cpu_to_le64(mapping); 3823 rtl8169_mark_to_asic(desc); 3824 3825 return data; 3826 } 3827 3828 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3829 { 3830 int i; 3831 3832 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3833 dma_unmap_page(tp_to_dev(tp), 3834 le64_to_cpu(tp->RxDescArray[i].addr), 3835 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3836 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3837 tp->Rx_databuff[i] = NULL; 3838 tp->RxDescArray[i].addr = 0; 3839 tp->RxDescArray[i].opts1 = 0; 3840 } 3841 } 3842 3843 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3844 { 3845 int i; 3846 3847 for (i = 0; i < NUM_RX_DESC; i++) { 3848 struct page *data; 3849 3850 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3851 if (!data) { 3852 rtl8169_rx_clear(tp); 3853 return -ENOMEM; 3854 } 3855 tp->Rx_databuff[i] = data; 3856 } 3857 3858 /* mark as last descriptor in the ring */ 3859 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3860 3861 return 0; 3862 } 3863 3864 static int rtl8169_init_ring(struct rtl8169_private *tp) 3865 { 3866 rtl8169_init_ring_indexes(tp); 3867 3868 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3869 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3870 3871 return rtl8169_rx_fill(tp); 3872 } 3873 3874 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3875 { 3876 struct ring_info *tx_skb = tp->tx_skb + entry; 3877 struct TxDesc *desc = tp->TxDescArray + entry; 3878 3879 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3880 DMA_TO_DEVICE); 3881 memset(desc, 0, sizeof(*desc)); 3882 memset(tx_skb, 0, sizeof(*tx_skb)); 3883 } 3884 3885 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3886 unsigned int n) 3887 { 3888 unsigned int i; 3889 3890 for (i = 0; i < n; i++) { 3891 unsigned int entry = (start + i) % NUM_TX_DESC; 3892 struct ring_info *tx_skb = tp->tx_skb + entry; 3893 unsigned int len = tx_skb->len; 3894 3895 if (len) { 3896 struct sk_buff *skb = tx_skb->skb; 3897 3898 rtl8169_unmap_tx_skb(tp, entry); 3899 if (skb) 3900 dev_consume_skb_any(skb); 3901 } 3902 } 3903 } 3904 3905 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3906 { 3907 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3908 netdev_reset_queue(tp->dev); 3909 } 3910 3911 static void rtl8169_cleanup(struct rtl8169_private *tp) 3912 { 3913 napi_disable(&tp->napi); 3914 3915 /* Give a racing hard_start_xmit a few cycles to complete. */ 3916 synchronize_net(); 3917 3918 /* Disable interrupts */ 3919 rtl8169_irq_mask_and_ack(tp); 3920 3921 rtl_rx_close(tp); 3922 3923 switch (tp->mac_version) { 3924 case RTL_GIGA_MAC_VER_28: 3925 case RTL_GIGA_MAC_VER_31: 3926 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3927 break; 3928 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3929 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3930 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3931 break; 3932 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3933 rtl_enable_rxdvgate(tp); 3934 fsleep(2000); 3935 break; 3936 default: 3937 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3938 fsleep(100); 3939 break; 3940 } 3941 3942 rtl_hw_reset(tp); 3943 3944 rtl8169_tx_clear(tp); 3945 rtl8169_init_ring_indexes(tp); 3946 } 3947 3948 static void rtl_reset_work(struct rtl8169_private *tp) 3949 { 3950 int i; 3951 3952 netif_stop_queue(tp->dev); 3953 3954 rtl8169_cleanup(tp); 3955 3956 for (i = 0; i < NUM_RX_DESC; i++) 3957 rtl8169_mark_to_asic(tp->RxDescArray + i); 3958 3959 napi_enable(&tp->napi); 3960 rtl_hw_start(tp); 3961 } 3962 3963 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3964 { 3965 struct rtl8169_private *tp = netdev_priv(dev); 3966 3967 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 3968 } 3969 3970 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3971 void *addr, unsigned int entry, bool desc_own) 3972 { 3973 struct TxDesc *txd = tp->TxDescArray + entry; 3974 struct device *d = tp_to_dev(tp); 3975 dma_addr_t mapping; 3976 u32 opts1; 3977 int ret; 3978 3979 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3980 ret = dma_mapping_error(d, mapping); 3981 if (unlikely(ret)) { 3982 if (net_ratelimit()) 3983 netdev_err(tp->dev, "Failed to map TX data!\n"); 3984 return ret; 3985 } 3986 3987 txd->addr = cpu_to_le64(mapping); 3988 txd->opts2 = cpu_to_le32(opts[1]); 3989 3990 opts1 = opts[0] | len; 3991 if (entry == NUM_TX_DESC - 1) 3992 opts1 |= RingEnd; 3993 if (desc_own) 3994 opts1 |= DescOwn; 3995 txd->opts1 = cpu_to_le32(opts1); 3996 3997 tp->tx_skb[entry].len = len; 3998 3999 return 0; 4000 } 4001 4002 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4003 const u32 *opts, unsigned int entry) 4004 { 4005 struct skb_shared_info *info = skb_shinfo(skb); 4006 unsigned int cur_frag; 4007 4008 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4009 const skb_frag_t *frag = info->frags + cur_frag; 4010 void *addr = skb_frag_address(frag); 4011 u32 len = skb_frag_size(frag); 4012 4013 entry = (entry + 1) % NUM_TX_DESC; 4014 4015 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4016 goto err_out; 4017 } 4018 4019 return 0; 4020 4021 err_out: 4022 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4023 return -EIO; 4024 } 4025 4026 static bool rtl_skb_is_udp(struct sk_buff *skb) 4027 { 4028 int no = skb_network_offset(skb); 4029 struct ipv6hdr *i6h, _i6h; 4030 struct iphdr *ih, _ih; 4031 4032 switch (vlan_get_protocol(skb)) { 4033 case htons(ETH_P_IP): 4034 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4035 return ih && ih->protocol == IPPROTO_UDP; 4036 case htons(ETH_P_IPV6): 4037 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4038 return i6h && i6h->nexthdr == IPPROTO_UDP; 4039 default: 4040 return false; 4041 } 4042 } 4043 4044 #define RTL_MIN_PATCH_LEN 47 4045 4046 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4047 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4048 struct sk_buff *skb) 4049 { 4050 unsigned int padto = 0, len = skb->len; 4051 4052 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4053 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4054 unsigned int trans_data_len = skb_tail_pointer(skb) - 4055 skb_transport_header(skb); 4056 4057 if (trans_data_len >= offsetof(struct udphdr, len) && 4058 trans_data_len < RTL_MIN_PATCH_LEN) { 4059 u16 dest = ntohs(udp_hdr(skb)->dest); 4060 4061 /* dest is a standard PTP port */ 4062 if (dest == 319 || dest == 320) 4063 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4064 } 4065 4066 if (trans_data_len < sizeof(struct udphdr)) 4067 padto = max_t(unsigned int, padto, 4068 len + sizeof(struct udphdr) - trans_data_len); 4069 } 4070 4071 return padto; 4072 } 4073 4074 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4075 struct sk_buff *skb) 4076 { 4077 unsigned int padto; 4078 4079 padto = rtl8125_quirk_udp_padto(tp, skb); 4080 4081 switch (tp->mac_version) { 4082 case RTL_GIGA_MAC_VER_34: 4083 case RTL_GIGA_MAC_VER_61: 4084 case RTL_GIGA_MAC_VER_63: 4085 padto = max_t(unsigned int, padto, ETH_ZLEN); 4086 break; 4087 default: 4088 break; 4089 } 4090 4091 return padto; 4092 } 4093 4094 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4095 { 4096 u32 mss = skb_shinfo(skb)->gso_size; 4097 4098 if (mss) { 4099 opts[0] |= TD_LSO; 4100 opts[0] |= mss << TD0_MSS_SHIFT; 4101 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4102 const struct iphdr *ip = ip_hdr(skb); 4103 4104 if (ip->protocol == IPPROTO_TCP) 4105 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4106 else if (ip->protocol == IPPROTO_UDP) 4107 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4108 else 4109 WARN_ON_ONCE(1); 4110 } 4111 } 4112 4113 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4114 struct sk_buff *skb, u32 *opts) 4115 { 4116 struct skb_shared_info *shinfo = skb_shinfo(skb); 4117 u32 mss = shinfo->gso_size; 4118 4119 if (mss) { 4120 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4121 opts[0] |= TD1_GTSENV4; 4122 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4123 if (skb_cow_head(skb, 0)) 4124 return false; 4125 4126 tcp_v6_gso_csum_prep(skb); 4127 opts[0] |= TD1_GTSENV6; 4128 } else { 4129 WARN_ON_ONCE(1); 4130 } 4131 4132 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4133 opts[1] |= mss << TD1_MSS_SHIFT; 4134 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4135 u8 ip_protocol; 4136 4137 switch (vlan_get_protocol(skb)) { 4138 case htons(ETH_P_IP): 4139 opts[1] |= TD1_IPv4_CS; 4140 ip_protocol = ip_hdr(skb)->protocol; 4141 break; 4142 4143 case htons(ETH_P_IPV6): 4144 opts[1] |= TD1_IPv6_CS; 4145 ip_protocol = ipv6_hdr(skb)->nexthdr; 4146 break; 4147 4148 default: 4149 ip_protocol = IPPROTO_RAW; 4150 break; 4151 } 4152 4153 if (ip_protocol == IPPROTO_TCP) 4154 opts[1] |= TD1_TCP_CS; 4155 else if (ip_protocol == IPPROTO_UDP) 4156 opts[1] |= TD1_UDP_CS; 4157 else 4158 WARN_ON_ONCE(1); 4159 4160 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4161 } else { 4162 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4163 4164 /* skb_padto would free the skb on error */ 4165 return !__skb_put_padto(skb, padto, false); 4166 } 4167 4168 return true; 4169 } 4170 4171 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4172 { 4173 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4174 } 4175 4176 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4177 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4178 { 4179 switch (tp->mac_version) { 4180 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4181 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4182 return false; 4183 default: 4184 return true; 4185 } 4186 } 4187 4188 static void rtl8169_doorbell(struct rtl8169_private *tp) 4189 { 4190 if (rtl_is_8125(tp)) 4191 RTL_W16(tp, TxPoll_8125, BIT(0)); 4192 else 4193 RTL_W8(tp, TxPoll, NPQ); 4194 } 4195 4196 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4197 struct net_device *dev) 4198 { 4199 unsigned int frags = skb_shinfo(skb)->nr_frags; 4200 struct rtl8169_private *tp = netdev_priv(dev); 4201 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4202 struct TxDesc *txd_first, *txd_last; 4203 bool stop_queue, door_bell; 4204 u32 opts[2]; 4205 4206 if (unlikely(!rtl_tx_slots_avail(tp))) { 4207 if (net_ratelimit()) 4208 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4209 goto err_stop_0; 4210 } 4211 4212 opts[1] = rtl8169_tx_vlan_tag(skb); 4213 opts[0] = 0; 4214 4215 if (!rtl_chip_supports_csum_v2(tp)) 4216 rtl8169_tso_csum_v1(skb, opts); 4217 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4218 goto err_dma_0; 4219 4220 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4221 entry, false))) 4222 goto err_dma_0; 4223 4224 txd_first = tp->TxDescArray + entry; 4225 4226 if (frags) { 4227 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4228 goto err_dma_1; 4229 entry = (entry + frags) % NUM_TX_DESC; 4230 } 4231 4232 txd_last = tp->TxDescArray + entry; 4233 txd_last->opts1 |= cpu_to_le32(LastFrag); 4234 tp->tx_skb[entry].skb = skb; 4235 4236 skb_tx_timestamp(skb); 4237 4238 /* Force memory writes to complete before releasing descriptor */ 4239 dma_wmb(); 4240 4241 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4242 4243 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4244 4245 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4246 smp_wmb(); 4247 4248 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4249 4250 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4251 R8169_TX_STOP_THRS, 4252 R8169_TX_START_THRS); 4253 if (door_bell || stop_queue) 4254 rtl8169_doorbell(tp); 4255 4256 return NETDEV_TX_OK; 4257 4258 err_dma_1: 4259 rtl8169_unmap_tx_skb(tp, entry); 4260 err_dma_0: 4261 dev_kfree_skb_any(skb); 4262 dev->stats.tx_dropped++; 4263 return NETDEV_TX_OK; 4264 4265 err_stop_0: 4266 netif_stop_queue(dev); 4267 dev->stats.tx_dropped++; 4268 return NETDEV_TX_BUSY; 4269 } 4270 4271 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4272 { 4273 struct skb_shared_info *info = skb_shinfo(skb); 4274 unsigned int nr_frags = info->nr_frags; 4275 4276 if (!nr_frags) 4277 return UINT_MAX; 4278 4279 return skb_frag_size(info->frags + nr_frags - 1); 4280 } 4281 4282 /* Workaround for hw issues with TSO on RTL8168evl */ 4283 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4284 netdev_features_t features) 4285 { 4286 /* IPv4 header has options field */ 4287 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4288 ip_hdrlen(skb) > sizeof(struct iphdr)) 4289 features &= ~NETIF_F_ALL_TSO; 4290 4291 /* IPv4 TCP header has options field */ 4292 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4293 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4294 features &= ~NETIF_F_ALL_TSO; 4295 4296 else if (rtl_last_frag_len(skb) <= 6) 4297 features &= ~NETIF_F_ALL_TSO; 4298 4299 return features; 4300 } 4301 4302 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4303 struct net_device *dev, 4304 netdev_features_t features) 4305 { 4306 struct rtl8169_private *tp = netdev_priv(dev); 4307 4308 if (skb_is_gso(skb)) { 4309 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4310 features = rtl8168evl_fix_tso(skb, features); 4311 4312 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4313 rtl_chip_supports_csum_v2(tp)) 4314 features &= ~NETIF_F_ALL_TSO; 4315 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4316 /* work around hw bug on some chip versions */ 4317 if (skb->len < ETH_ZLEN) 4318 features &= ~NETIF_F_CSUM_MASK; 4319 4320 if (rtl_quirk_packet_padto(tp, skb)) 4321 features &= ~NETIF_F_CSUM_MASK; 4322 4323 if (skb_transport_offset(skb) > TCPHO_MAX && 4324 rtl_chip_supports_csum_v2(tp)) 4325 features &= ~NETIF_F_CSUM_MASK; 4326 } 4327 4328 return vlan_features_check(skb, features); 4329 } 4330 4331 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4332 { 4333 struct rtl8169_private *tp = netdev_priv(dev); 4334 struct pci_dev *pdev = tp->pci_dev; 4335 int pci_status_errs; 4336 u16 pci_cmd; 4337 4338 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4339 4340 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4341 4342 if (net_ratelimit()) 4343 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4344 pci_cmd, pci_status_errs); 4345 4346 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4347 } 4348 4349 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4350 int budget) 4351 { 4352 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4353 struct sk_buff *skb; 4354 4355 dirty_tx = tp->dirty_tx; 4356 4357 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4358 unsigned int entry = dirty_tx % NUM_TX_DESC; 4359 u32 status; 4360 4361 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4362 if (status & DescOwn) 4363 break; 4364 4365 skb = tp->tx_skb[entry].skb; 4366 rtl8169_unmap_tx_skb(tp, entry); 4367 4368 if (skb) { 4369 pkts_compl++; 4370 bytes_compl += skb->len; 4371 napi_consume_skb(skb, budget); 4372 } 4373 dirty_tx++; 4374 } 4375 4376 if (tp->dirty_tx != dirty_tx) { 4377 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4378 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4379 4380 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4381 rtl_tx_slots_avail(tp), 4382 R8169_TX_START_THRS); 4383 /* 4384 * 8168 hack: TxPoll requests are lost when the Tx packets are 4385 * too close. Let's kick an extra TxPoll request when a burst 4386 * of start_xmit activity is detected (if it is not detected, 4387 * it is slow enough). -- FR 4388 * If skb is NULL then we come here again once a tx irq is 4389 * triggered after the last fragment is marked transmitted. 4390 */ 4391 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4392 rtl8169_doorbell(tp); 4393 } 4394 } 4395 4396 static inline int rtl8169_fragmented_frame(u32 status) 4397 { 4398 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4399 } 4400 4401 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4402 { 4403 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4404 4405 if (status == RxProtoTCP || status == RxProtoUDP) 4406 skb->ip_summed = CHECKSUM_UNNECESSARY; 4407 else 4408 skb_checksum_none_assert(skb); 4409 } 4410 4411 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4412 { 4413 struct device *d = tp_to_dev(tp); 4414 int count; 4415 4416 for (count = 0; count < budget; count++, tp->cur_rx++) { 4417 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4418 struct RxDesc *desc = tp->RxDescArray + entry; 4419 struct sk_buff *skb; 4420 const void *rx_buf; 4421 dma_addr_t addr; 4422 u32 status; 4423 4424 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4425 if (status & DescOwn) 4426 break; 4427 4428 /* This barrier is needed to keep us from reading 4429 * any other fields out of the Rx descriptor until 4430 * we know the status of DescOwn 4431 */ 4432 dma_rmb(); 4433 4434 if (unlikely(status & RxRES)) { 4435 if (net_ratelimit()) 4436 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4437 status); 4438 dev->stats.rx_errors++; 4439 if (status & (RxRWT | RxRUNT)) 4440 dev->stats.rx_length_errors++; 4441 if (status & RxCRC) 4442 dev->stats.rx_crc_errors++; 4443 4444 if (!(dev->features & NETIF_F_RXALL)) 4445 goto release_descriptor; 4446 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4447 goto release_descriptor; 4448 } 4449 4450 pkt_size = status & GENMASK(13, 0); 4451 if (likely(!(dev->features & NETIF_F_RXFCS))) 4452 pkt_size -= ETH_FCS_LEN; 4453 4454 /* The driver does not support incoming fragmented frames. 4455 * They are seen as a symptom of over-mtu sized frames. 4456 */ 4457 if (unlikely(rtl8169_fragmented_frame(status))) { 4458 dev->stats.rx_dropped++; 4459 dev->stats.rx_length_errors++; 4460 goto release_descriptor; 4461 } 4462 4463 skb = napi_alloc_skb(&tp->napi, pkt_size); 4464 if (unlikely(!skb)) { 4465 dev->stats.rx_dropped++; 4466 goto release_descriptor; 4467 } 4468 4469 addr = le64_to_cpu(desc->addr); 4470 rx_buf = page_address(tp->Rx_databuff[entry]); 4471 4472 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4473 prefetch(rx_buf); 4474 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4475 skb->tail += pkt_size; 4476 skb->len = pkt_size; 4477 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4478 4479 rtl8169_rx_csum(skb, status); 4480 skb->protocol = eth_type_trans(skb, dev); 4481 4482 rtl8169_rx_vlan_tag(desc, skb); 4483 4484 if (skb->pkt_type == PACKET_MULTICAST) 4485 dev->stats.multicast++; 4486 4487 napi_gro_receive(&tp->napi, skb); 4488 4489 dev_sw_netstats_rx_add(dev, pkt_size); 4490 release_descriptor: 4491 rtl8169_mark_to_asic(desc); 4492 } 4493 4494 return count; 4495 } 4496 4497 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4498 { 4499 struct rtl8169_private *tp = dev_instance; 4500 u32 status = rtl_get_events(tp); 4501 4502 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4503 return IRQ_NONE; 4504 4505 if (unlikely(status & SYSErr)) { 4506 rtl8169_pcierr_interrupt(tp->dev); 4507 goto out; 4508 } 4509 4510 if (status & LinkChg) 4511 phy_mac_interrupt(tp->phydev); 4512 4513 if (unlikely(status & RxFIFOOver && 4514 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4515 netif_stop_queue(tp->dev); 4516 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4517 } 4518 4519 if (napi_schedule_prep(&tp->napi)) { 4520 rtl_irq_disable(tp); 4521 __napi_schedule(&tp->napi); 4522 } 4523 out: 4524 rtl_ack_events(tp, status); 4525 4526 return IRQ_HANDLED; 4527 } 4528 4529 static void rtl_task(struct work_struct *work) 4530 { 4531 struct rtl8169_private *tp = 4532 container_of(work, struct rtl8169_private, wk.work); 4533 int ret; 4534 4535 rtnl_lock(); 4536 4537 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4538 goto out_unlock; 4539 4540 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4541 /* if chip isn't accessible, reset bus to revive it */ 4542 if (RTL_R32(tp, TxConfig) == ~0) { 4543 ret = pci_reset_bus(tp->pci_dev); 4544 if (ret < 0) { 4545 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4546 netif_device_detach(tp->dev); 4547 goto out_unlock; 4548 } 4549 } 4550 4551 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4552 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4553 PCIE_LINK_STATE_L0S); 4554 if (!ret) 4555 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4556 goto reset; 4557 } 4558 4559 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4560 reset: 4561 rtl_reset_work(tp); 4562 netif_wake_queue(tp->dev); 4563 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4564 rtl_reset_work(tp); 4565 } 4566 out_unlock: 4567 rtnl_unlock(); 4568 } 4569 4570 static int rtl8169_poll(struct napi_struct *napi, int budget) 4571 { 4572 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4573 struct net_device *dev = tp->dev; 4574 int work_done; 4575 4576 rtl_tx(dev, tp, budget); 4577 4578 work_done = rtl_rx(dev, tp, budget); 4579 4580 if (work_done < budget && napi_complete_done(napi, work_done)) 4581 rtl_irq_enable(tp); 4582 4583 return work_done; 4584 } 4585 4586 static void r8169_phylink_handler(struct net_device *ndev) 4587 { 4588 struct rtl8169_private *tp = netdev_priv(ndev); 4589 struct device *d = tp_to_dev(tp); 4590 4591 if (netif_carrier_ok(ndev)) { 4592 rtl_link_chg_patch(tp); 4593 pm_request_resume(d); 4594 netif_wake_queue(tp->dev); 4595 } else { 4596 /* In few cases rx is broken after link-down otherwise */ 4597 if (rtl_is_8125(tp)) 4598 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4599 pm_runtime_idle(d); 4600 } 4601 4602 phy_print_status(tp->phydev); 4603 } 4604 4605 static int r8169_phy_connect(struct rtl8169_private *tp) 4606 { 4607 struct phy_device *phydev = tp->phydev; 4608 phy_interface_t phy_mode; 4609 int ret; 4610 4611 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4612 PHY_INTERFACE_MODE_MII; 4613 4614 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4615 phy_mode); 4616 if (ret) 4617 return ret; 4618 4619 if (!tp->supports_gmii) 4620 phy_set_max_speed(phydev, SPEED_100); 4621 4622 phy_attached_info(phydev); 4623 4624 return 0; 4625 } 4626 4627 static void rtl8169_down(struct rtl8169_private *tp) 4628 { 4629 /* Clear all task flags */ 4630 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4631 4632 phy_stop(tp->phydev); 4633 4634 rtl8169_update_counters(tp); 4635 4636 pci_clear_master(tp->pci_dev); 4637 rtl_pci_commit(tp); 4638 4639 rtl8169_cleanup(tp); 4640 rtl_disable_exit_l1(tp); 4641 rtl_prepare_power_down(tp); 4642 4643 if (tp->dash_type != RTL_DASH_NONE) 4644 rtl8168_driver_stop(tp); 4645 } 4646 4647 static void rtl8169_up(struct rtl8169_private *tp) 4648 { 4649 if (tp->dash_type != RTL_DASH_NONE) 4650 rtl8168_driver_start(tp); 4651 4652 pci_set_master(tp->pci_dev); 4653 phy_init_hw(tp->phydev); 4654 phy_resume(tp->phydev); 4655 rtl8169_init_phy(tp); 4656 napi_enable(&tp->napi); 4657 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4658 rtl_reset_work(tp); 4659 4660 phy_start(tp->phydev); 4661 } 4662 4663 static int rtl8169_close(struct net_device *dev) 4664 { 4665 struct rtl8169_private *tp = netdev_priv(dev); 4666 struct pci_dev *pdev = tp->pci_dev; 4667 4668 pm_runtime_get_sync(&pdev->dev); 4669 4670 netif_stop_queue(dev); 4671 rtl8169_down(tp); 4672 rtl8169_rx_clear(tp); 4673 4674 cancel_work(&tp->wk.work); 4675 4676 free_irq(tp->irq, tp); 4677 4678 phy_disconnect(tp->phydev); 4679 4680 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4681 tp->RxPhyAddr); 4682 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4683 tp->TxPhyAddr); 4684 tp->TxDescArray = NULL; 4685 tp->RxDescArray = NULL; 4686 4687 pm_runtime_put_sync(&pdev->dev); 4688 4689 return 0; 4690 } 4691 4692 #ifdef CONFIG_NET_POLL_CONTROLLER 4693 static void rtl8169_netpoll(struct net_device *dev) 4694 { 4695 struct rtl8169_private *tp = netdev_priv(dev); 4696 4697 rtl8169_interrupt(tp->irq, tp); 4698 } 4699 #endif 4700 4701 static int rtl_open(struct net_device *dev) 4702 { 4703 struct rtl8169_private *tp = netdev_priv(dev); 4704 struct pci_dev *pdev = tp->pci_dev; 4705 unsigned long irqflags; 4706 int retval = -ENOMEM; 4707 4708 pm_runtime_get_sync(&pdev->dev); 4709 4710 /* 4711 * Rx and Tx descriptors needs 256 bytes alignment. 4712 * dma_alloc_coherent provides more. 4713 */ 4714 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4715 &tp->TxPhyAddr, GFP_KERNEL); 4716 if (!tp->TxDescArray) 4717 goto out; 4718 4719 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4720 &tp->RxPhyAddr, GFP_KERNEL); 4721 if (!tp->RxDescArray) 4722 goto err_free_tx_0; 4723 4724 retval = rtl8169_init_ring(tp); 4725 if (retval < 0) 4726 goto err_free_rx_1; 4727 4728 rtl_request_firmware(tp); 4729 4730 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4731 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4732 if (retval < 0) 4733 goto err_release_fw_2; 4734 4735 retval = r8169_phy_connect(tp); 4736 if (retval) 4737 goto err_free_irq; 4738 4739 rtl8169_up(tp); 4740 rtl8169_init_counter_offsets(tp); 4741 netif_start_queue(dev); 4742 out: 4743 pm_runtime_put_sync(&pdev->dev); 4744 4745 return retval; 4746 4747 err_free_irq: 4748 free_irq(tp->irq, tp); 4749 err_release_fw_2: 4750 rtl_release_firmware(tp); 4751 rtl8169_rx_clear(tp); 4752 err_free_rx_1: 4753 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4754 tp->RxPhyAddr); 4755 tp->RxDescArray = NULL; 4756 err_free_tx_0: 4757 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4758 tp->TxPhyAddr); 4759 tp->TxDescArray = NULL; 4760 goto out; 4761 } 4762 4763 static void 4764 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4765 { 4766 struct rtl8169_private *tp = netdev_priv(dev); 4767 struct pci_dev *pdev = tp->pci_dev; 4768 struct rtl8169_counters *counters = tp->counters; 4769 4770 pm_runtime_get_noresume(&pdev->dev); 4771 4772 netdev_stats_to_stats64(stats, &dev->stats); 4773 dev_fetch_sw_netstats(stats, dev->tstats); 4774 4775 /* 4776 * Fetch additional counter values missing in stats collected by driver 4777 * from tally counters. 4778 */ 4779 if (pm_runtime_active(&pdev->dev)) 4780 rtl8169_update_counters(tp); 4781 4782 /* 4783 * Subtract values fetched during initalization. 4784 * See rtl8169_init_counter_offsets for a description why we do that. 4785 */ 4786 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4787 le64_to_cpu(tp->tc_offset.tx_errors); 4788 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4789 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4790 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4791 le16_to_cpu(tp->tc_offset.tx_aborted); 4792 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4793 le16_to_cpu(tp->tc_offset.rx_missed); 4794 4795 pm_runtime_put_noidle(&pdev->dev); 4796 } 4797 4798 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4799 { 4800 netif_device_detach(tp->dev); 4801 4802 if (netif_running(tp->dev)) 4803 rtl8169_down(tp); 4804 } 4805 4806 static int rtl8169_runtime_resume(struct device *dev) 4807 { 4808 struct rtl8169_private *tp = dev_get_drvdata(dev); 4809 4810 rtl_rar_set(tp, tp->dev->dev_addr); 4811 __rtl8169_set_wol(tp, tp->saved_wolopts); 4812 4813 if (tp->TxDescArray) 4814 rtl8169_up(tp); 4815 4816 netif_device_attach(tp->dev); 4817 4818 return 0; 4819 } 4820 4821 static int rtl8169_suspend(struct device *device) 4822 { 4823 struct rtl8169_private *tp = dev_get_drvdata(device); 4824 4825 rtnl_lock(); 4826 rtl8169_net_suspend(tp); 4827 if (!device_may_wakeup(tp_to_dev(tp))) 4828 clk_disable_unprepare(tp->clk); 4829 rtnl_unlock(); 4830 4831 return 0; 4832 } 4833 4834 static int rtl8169_resume(struct device *device) 4835 { 4836 struct rtl8169_private *tp = dev_get_drvdata(device); 4837 4838 if (!device_may_wakeup(tp_to_dev(tp))) 4839 clk_prepare_enable(tp->clk); 4840 4841 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4842 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4843 rtl_init_rxcfg(tp); 4844 4845 return rtl8169_runtime_resume(device); 4846 } 4847 4848 static int rtl8169_runtime_suspend(struct device *device) 4849 { 4850 struct rtl8169_private *tp = dev_get_drvdata(device); 4851 4852 if (!tp->TxDescArray) { 4853 netif_device_detach(tp->dev); 4854 return 0; 4855 } 4856 4857 rtnl_lock(); 4858 __rtl8169_set_wol(tp, WAKE_PHY); 4859 rtl8169_net_suspend(tp); 4860 rtnl_unlock(); 4861 4862 return 0; 4863 } 4864 4865 static int rtl8169_runtime_idle(struct device *device) 4866 { 4867 struct rtl8169_private *tp = dev_get_drvdata(device); 4868 4869 if (tp->dash_enabled) 4870 return -EBUSY; 4871 4872 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4873 pm_schedule_suspend(device, 10000); 4874 4875 return -EBUSY; 4876 } 4877 4878 static const struct dev_pm_ops rtl8169_pm_ops = { 4879 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4880 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4881 rtl8169_runtime_idle) 4882 }; 4883 4884 static void rtl_shutdown(struct pci_dev *pdev) 4885 { 4886 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4887 4888 rtnl_lock(); 4889 rtl8169_net_suspend(tp); 4890 rtnl_unlock(); 4891 4892 /* Restore original MAC address */ 4893 rtl_rar_set(tp, tp->dev->perm_addr); 4894 4895 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 4896 pci_wake_from_d3(pdev, tp->saved_wolopts); 4897 pci_set_power_state(pdev, PCI_D3hot); 4898 } 4899 } 4900 4901 static void rtl_remove_one(struct pci_dev *pdev) 4902 { 4903 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4904 4905 if (pci_dev_run_wake(pdev)) 4906 pm_runtime_get_noresume(&pdev->dev); 4907 4908 cancel_work_sync(&tp->wk.work); 4909 4910 unregister_netdev(tp->dev); 4911 4912 if (tp->dash_type != RTL_DASH_NONE) 4913 rtl8168_driver_stop(tp); 4914 4915 rtl_release_firmware(tp); 4916 4917 /* restore original MAC address */ 4918 rtl_rar_set(tp, tp->dev->perm_addr); 4919 } 4920 4921 static const struct net_device_ops rtl_netdev_ops = { 4922 .ndo_open = rtl_open, 4923 .ndo_stop = rtl8169_close, 4924 .ndo_get_stats64 = rtl8169_get_stats64, 4925 .ndo_start_xmit = rtl8169_start_xmit, 4926 .ndo_features_check = rtl8169_features_check, 4927 .ndo_tx_timeout = rtl8169_tx_timeout, 4928 .ndo_validate_addr = eth_validate_addr, 4929 .ndo_change_mtu = rtl8169_change_mtu, 4930 .ndo_fix_features = rtl8169_fix_features, 4931 .ndo_set_features = rtl8169_set_features, 4932 .ndo_set_mac_address = rtl_set_mac_address, 4933 .ndo_eth_ioctl = phy_do_ioctl_running, 4934 .ndo_set_rx_mode = rtl_set_rx_mode, 4935 #ifdef CONFIG_NET_POLL_CONTROLLER 4936 .ndo_poll_controller = rtl8169_netpoll, 4937 #endif 4938 4939 }; 4940 4941 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4942 { 4943 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4944 4945 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4946 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4947 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4948 /* special workaround needed */ 4949 tp->irq_mask |= RxFIFOOver; 4950 else 4951 tp->irq_mask |= RxOverflow; 4952 } 4953 4954 static int rtl_alloc_irq(struct rtl8169_private *tp) 4955 { 4956 unsigned int flags; 4957 4958 switch (tp->mac_version) { 4959 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4960 rtl_unlock_config_regs(tp); 4961 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4962 rtl_lock_config_regs(tp); 4963 fallthrough; 4964 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4965 flags = PCI_IRQ_LEGACY; 4966 break; 4967 default: 4968 flags = PCI_IRQ_ALL_TYPES; 4969 break; 4970 } 4971 4972 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4973 } 4974 4975 static void rtl_read_mac_address(struct rtl8169_private *tp, 4976 u8 mac_addr[ETH_ALEN]) 4977 { 4978 /* Get MAC address */ 4979 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 4980 u32 value; 4981 4982 value = rtl_eri_read(tp, 0xe0); 4983 put_unaligned_le32(value, mac_addr); 4984 value = rtl_eri_read(tp, 0xe4); 4985 put_unaligned_le16(value, mac_addr + 4); 4986 } else if (rtl_is_8125(tp)) { 4987 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 4988 } 4989 } 4990 4991 DECLARE_RTL_COND(rtl_link_list_ready_cond) 4992 { 4993 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 4994 } 4995 4996 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 4997 { 4998 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 4999 } 5000 5001 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5002 { 5003 struct rtl8169_private *tp = mii_bus->priv; 5004 5005 if (phyaddr > 0) 5006 return -ENODEV; 5007 5008 return rtl_readphy(tp, phyreg); 5009 } 5010 5011 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5012 int phyreg, u16 val) 5013 { 5014 struct rtl8169_private *tp = mii_bus->priv; 5015 5016 if (phyaddr > 0) 5017 return -ENODEV; 5018 5019 rtl_writephy(tp, phyreg, val); 5020 5021 return 0; 5022 } 5023 5024 static int r8169_mdio_register(struct rtl8169_private *tp) 5025 { 5026 struct pci_dev *pdev = tp->pci_dev; 5027 struct mii_bus *new_bus; 5028 int ret; 5029 5030 new_bus = devm_mdiobus_alloc(&pdev->dev); 5031 if (!new_bus) 5032 return -ENOMEM; 5033 5034 new_bus->name = "r8169"; 5035 new_bus->priv = tp; 5036 new_bus->parent = &pdev->dev; 5037 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5038 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5039 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5040 5041 new_bus->read = r8169_mdio_read_reg; 5042 new_bus->write = r8169_mdio_write_reg; 5043 5044 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5045 if (ret) 5046 return ret; 5047 5048 tp->phydev = mdiobus_get_phy(new_bus, 0); 5049 if (!tp->phydev) { 5050 return -ENODEV; 5051 } else if (!tp->phydev->drv) { 5052 /* Most chip versions fail with the genphy driver. 5053 * Therefore ensure that the dedicated PHY driver is loaded. 5054 */ 5055 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5056 tp->phydev->phy_id); 5057 return -EUNATCH; 5058 } 5059 5060 tp->phydev->mac_managed_pm = true; 5061 5062 phy_support_asym_pause(tp->phydev); 5063 5064 /* PHY will be woken up in rtl_open() */ 5065 phy_suspend(tp->phydev); 5066 5067 return 0; 5068 } 5069 5070 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5071 { 5072 rtl_enable_rxdvgate(tp); 5073 5074 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5075 msleep(1); 5076 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5077 5078 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5079 r8168g_wait_ll_share_fifo_ready(tp); 5080 5081 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5082 r8168g_wait_ll_share_fifo_ready(tp); 5083 } 5084 5085 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5086 { 5087 rtl_enable_rxdvgate(tp); 5088 5089 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5090 msleep(1); 5091 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5092 5093 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5094 r8168g_wait_ll_share_fifo_ready(tp); 5095 5096 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5097 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5098 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5099 r8168g_wait_ll_share_fifo_ready(tp); 5100 } 5101 5102 static void rtl_hw_initialize(struct rtl8169_private *tp) 5103 { 5104 switch (tp->mac_version) { 5105 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5106 rtl8168ep_stop_cmac(tp); 5107 fallthrough; 5108 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5109 rtl_hw_init_8168g(tp); 5110 break; 5111 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5112 rtl_hw_init_8125(tp); 5113 break; 5114 default: 5115 break; 5116 } 5117 } 5118 5119 static int rtl_jumbo_max(struct rtl8169_private *tp) 5120 { 5121 /* Non-GBit versions don't support jumbo frames */ 5122 if (!tp->supports_gmii) 5123 return 0; 5124 5125 switch (tp->mac_version) { 5126 /* RTL8169 */ 5127 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5128 return JUMBO_7K; 5129 /* RTL8168b */ 5130 case RTL_GIGA_MAC_VER_11: 5131 case RTL_GIGA_MAC_VER_17: 5132 return JUMBO_4K; 5133 /* RTL8168c */ 5134 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5135 return JUMBO_6K; 5136 default: 5137 return JUMBO_9K; 5138 } 5139 } 5140 5141 static void rtl_init_mac_address(struct rtl8169_private *tp) 5142 { 5143 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5144 struct net_device *dev = tp->dev; 5145 int rc; 5146 5147 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5148 if (!rc) 5149 goto done; 5150 5151 rtl_read_mac_address(tp, mac_addr); 5152 if (is_valid_ether_addr(mac_addr)) 5153 goto done; 5154 5155 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5156 if (is_valid_ether_addr(mac_addr)) 5157 goto done; 5158 5159 eth_random_addr(mac_addr); 5160 dev->addr_assign_type = NET_ADDR_RANDOM; 5161 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5162 done: 5163 eth_hw_addr_set(dev, mac_addr); 5164 rtl_rar_set(tp, mac_addr); 5165 } 5166 5167 /* register is set if system vendor successfully tested ASPM 1.2 */ 5168 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5169 { 5170 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5171 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5172 return true; 5173 5174 return false; 5175 } 5176 5177 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5178 { 5179 struct rtl8169_private *tp; 5180 int jumbo_max, region, rc; 5181 enum mac_version chipset; 5182 struct net_device *dev; 5183 u32 txconfig; 5184 u16 xid; 5185 5186 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5187 if (!dev) 5188 return -ENOMEM; 5189 5190 SET_NETDEV_DEV(dev, &pdev->dev); 5191 dev->netdev_ops = &rtl_netdev_ops; 5192 tp = netdev_priv(dev); 5193 tp->dev = dev; 5194 tp->pci_dev = pdev; 5195 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5196 tp->eee_adv = -1; 5197 tp->ocp_base = OCP_STD_PHY_BASE; 5198 5199 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5200 raw_spin_lock_init(&tp->config25_lock); 5201 raw_spin_lock_init(&tp->mac_ocp_lock); 5202 mutex_init(&tp->led_lock); 5203 5204 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5205 struct pcpu_sw_netstats); 5206 if (!dev->tstats) 5207 return -ENOMEM; 5208 5209 /* Get the *optional* external "ether_clk" used on some boards */ 5210 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5211 if (IS_ERR(tp->clk)) 5212 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5213 5214 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5215 rc = pcim_enable_device(pdev); 5216 if (rc < 0) 5217 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5218 5219 if (pcim_set_mwi(pdev) < 0) 5220 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5221 5222 /* use first MMIO region */ 5223 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5224 if (region < 0) 5225 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5226 5227 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5228 if (rc < 0) 5229 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5230 5231 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5232 5233 txconfig = RTL_R32(tp, TxConfig); 5234 if (txconfig == ~0U) 5235 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5236 5237 xid = (txconfig >> 20) & 0xfcf; 5238 5239 /* Identify chip attached to board */ 5240 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5241 if (chipset == RTL_GIGA_MAC_NONE) 5242 return dev_err_probe(&pdev->dev, -ENODEV, 5243 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5244 xid); 5245 tp->mac_version = chipset; 5246 5247 /* Disable ASPM L1 as that cause random device stop working 5248 * problems as well as full system hangs for some PCIe devices users. 5249 */ 5250 if (rtl_aspm_is_safe(tp)) 5251 rc = 0; 5252 else 5253 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5254 tp->aspm_manageable = !rc; 5255 5256 tp->dash_type = rtl_get_dash_type(tp); 5257 tp->dash_enabled = rtl_dash_is_enabled(tp); 5258 5259 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5260 5261 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5262 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5263 dev->features |= NETIF_F_HIGHDMA; 5264 5265 rtl_init_rxcfg(tp); 5266 5267 rtl8169_irq_mask_and_ack(tp); 5268 5269 rtl_hw_initialize(tp); 5270 5271 rtl_hw_reset(tp); 5272 5273 rc = rtl_alloc_irq(tp); 5274 if (rc < 0) 5275 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5276 5277 tp->irq = pci_irq_vector(pdev, 0); 5278 5279 INIT_WORK(&tp->wk.work, rtl_task); 5280 5281 rtl_init_mac_address(tp); 5282 5283 dev->ethtool_ops = &rtl8169_ethtool_ops; 5284 5285 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5286 5287 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5288 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5289 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5290 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5291 5292 /* 5293 * Pretend we are using VLANs; This bypasses a nasty bug where 5294 * Interrupts stop flowing on high load on 8110SCd controllers. 5295 */ 5296 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5297 /* Disallow toggling */ 5298 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5299 5300 if (rtl_chip_supports_csum_v2(tp)) 5301 dev->hw_features |= NETIF_F_IPV6_CSUM; 5302 5303 dev->features |= dev->hw_features; 5304 5305 /* There has been a number of reports that using SG/TSO results in 5306 * tx timeouts. However for a lot of people SG/TSO works fine. 5307 * Therefore disable both features by default, but allow users to 5308 * enable them. Use at own risk! 5309 */ 5310 if (rtl_chip_supports_csum_v2(tp)) { 5311 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5312 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5313 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5314 } else { 5315 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5316 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5317 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5318 } 5319 5320 dev->hw_features |= NETIF_F_RXALL; 5321 dev->hw_features |= NETIF_F_RXFCS; 5322 5323 netdev_sw_irq_coalesce_default_on(dev); 5324 5325 /* configure chip for default features */ 5326 rtl8169_set_features(dev, dev->features); 5327 5328 if (!tp->dash_enabled) { 5329 rtl_set_d3_pll_down(tp, true); 5330 } else { 5331 rtl_set_d3_pll_down(tp, false); 5332 dev->wol_enabled = 1; 5333 } 5334 5335 jumbo_max = rtl_jumbo_max(tp); 5336 if (jumbo_max) 5337 dev->max_mtu = jumbo_max; 5338 5339 rtl_set_irq_mask(tp); 5340 5341 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5342 5343 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5344 &tp->counters_phys_addr, 5345 GFP_KERNEL); 5346 if (!tp->counters) 5347 return -ENOMEM; 5348 5349 pci_set_drvdata(pdev, tp); 5350 5351 rc = r8169_mdio_register(tp); 5352 if (rc) 5353 return rc; 5354 5355 rc = register_netdev(dev); 5356 if (rc) 5357 return rc; 5358 5359 if (IS_ENABLED(CONFIG_R8169_LEDS) && 5360 tp->mac_version > RTL_GIGA_MAC_VER_06 && 5361 tp->mac_version < RTL_GIGA_MAC_VER_61) 5362 rtl8168_init_leds(dev); 5363 5364 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5365 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5366 5367 if (jumbo_max) 5368 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5369 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5370 "ok" : "ko"); 5371 5372 if (tp->dash_type != RTL_DASH_NONE) { 5373 netdev_info(dev, "DASH %s\n", 5374 tp->dash_enabled ? "enabled" : "disabled"); 5375 rtl8168_driver_start(tp); 5376 } 5377 5378 if (pci_dev_run_wake(pdev)) 5379 pm_runtime_put_sync(&pdev->dev); 5380 5381 return 0; 5382 } 5383 5384 static struct pci_driver rtl8169_pci_driver = { 5385 .name = KBUILD_MODNAME, 5386 .id_table = rtl8169_pci_tbl, 5387 .probe = rtl_init_one, 5388 .remove = rtl_remove_one, 5389 .shutdown = rtl_shutdown, 5390 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5391 }; 5392 5393 module_pci_driver(rtl8169_pci_driver); 5394