1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <linux/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" 59 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 60 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 61 62 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 63 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 64 65 #define R8169_REGS_SIZE 256 66 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 67 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 68 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 69 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 70 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 71 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 72 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 73 74 #define OCP_STD_PHY_BASE 0xa400 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 91 static const struct { 92 const char *name; 93 const char *fw_name; 94 } rtl_chip_infos[] = { 95 /* PCI devices. */ 96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 101 /* PCI-E devices. */ 102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 108 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 110 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 115 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 117 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 118 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 119 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 120 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 122 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 123 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 124 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 125 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 126 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 127 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 128 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 129 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 130 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 131 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 132 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 133 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 134 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 135 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 136 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 137 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 138 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 139 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 140 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 141 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 142 [RTL_GIGA_MAC_VER_64] = {"RTL8125D", FIRMWARE_8125D_1}, 143 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 144 [RTL_GIGA_MAC_VER_66] = {"RTL8126A", FIRMWARE_8126A_3}, 145 }; 146 147 static const struct pci_device_id rtl8169_pci_tbl[] = { 148 { PCI_VDEVICE(REALTEK, 0x2502) }, 149 { PCI_VDEVICE(REALTEK, 0x2600) }, 150 { PCI_VDEVICE(REALTEK, 0x8129) }, 151 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 152 { PCI_VDEVICE(REALTEK, 0x8161) }, 153 { PCI_VDEVICE(REALTEK, 0x8162) }, 154 { PCI_VDEVICE(REALTEK, 0x8167) }, 155 { PCI_VDEVICE(REALTEK, 0x8168) }, 156 { PCI_VDEVICE(NCUBE, 0x8168) }, 157 { PCI_VDEVICE(REALTEK, 0x8169) }, 158 { PCI_VENDOR_ID_DLINK, 0x4300, 159 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 160 { PCI_VDEVICE(DLINK, 0x4300) }, 161 { PCI_VDEVICE(DLINK, 0x4302) }, 162 { PCI_VDEVICE(AT, 0xc107) }, 163 { PCI_VDEVICE(USR, 0x0116) }, 164 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 165 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 166 { PCI_VDEVICE(REALTEK, 0x8125) }, 167 { PCI_VDEVICE(REALTEK, 0x8126) }, 168 { PCI_VDEVICE(REALTEK, 0x3000) }, 169 {} 170 }; 171 172 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 173 174 enum rtl_registers { 175 MAC0 = 0, /* Ethernet hardware address. */ 176 MAC4 = 4, 177 MAR0 = 8, /* Multicast filter. */ 178 CounterAddrLow = 0x10, 179 CounterAddrHigh = 0x14, 180 TxDescStartAddrLow = 0x20, 181 TxDescStartAddrHigh = 0x24, 182 TxHDescStartAddrLow = 0x28, 183 TxHDescStartAddrHigh = 0x2c, 184 FLASH = 0x30, 185 ERSR = 0x36, 186 ChipCmd = 0x37, 187 TxPoll = 0x38, 188 IntrMask = 0x3c, 189 IntrStatus = 0x3e, 190 191 TxConfig = 0x40, 192 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 193 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 194 195 RxConfig = 0x44, 196 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 197 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 198 #define RXCFG_FIFO_SHIFT 13 199 /* No threshold before first PCI xfer */ 200 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 201 #define RX_EARLY_OFF (1 << 11) 202 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 203 #define RXCFG_DMA_SHIFT 8 204 /* Unlimited maximum PCI burst. */ 205 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 206 207 Cfg9346 = 0x50, 208 Config0 = 0x51, 209 Config1 = 0x52, 210 Config2 = 0x53, 211 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 212 213 Config3 = 0x54, 214 Config4 = 0x55, 215 Config5 = 0x56, 216 PHYAR = 0x60, 217 PHYstatus = 0x6c, 218 RxMaxSize = 0xda, 219 CPlusCmd = 0xe0, 220 IntrMitigate = 0xe2, 221 222 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 223 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 224 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 225 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 226 227 #define RTL_COALESCE_T_MAX 0x0fU 228 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 229 230 RxDescAddrLow = 0xe4, 231 RxDescAddrHigh = 0xe8, 232 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 233 234 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 235 236 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 237 238 #define TxPacketMax (8064 >> 7) 239 #define EarlySize 0x27 240 241 FuncEvent = 0xf0, 242 FuncEventMask = 0xf4, 243 FuncPresetState = 0xf8, 244 IBCR0 = 0xf8, 245 IBCR2 = 0xf9, 246 IBIMR0 = 0xfa, 247 IBISR0 = 0xfb, 248 FuncForceEvent = 0xfc, 249 }; 250 251 enum rtl8168_8101_registers { 252 CSIDR = 0x64, 253 CSIAR = 0x68, 254 #define CSIAR_FLAG 0x80000000 255 #define CSIAR_WRITE_CMD 0x80000000 256 #define CSIAR_BYTE_ENABLE 0x0000f000 257 #define CSIAR_ADDR_MASK 0x00000fff 258 PMCH = 0x6f, 259 #define D3COLD_NO_PLL_DOWN BIT(7) 260 #define D3HOT_NO_PLL_DOWN BIT(6) 261 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 262 EPHYAR = 0x80, 263 #define EPHYAR_FLAG 0x80000000 264 #define EPHYAR_WRITE_CMD 0x80000000 265 #define EPHYAR_REG_MASK 0x1f 266 #define EPHYAR_REG_SHIFT 16 267 #define EPHYAR_DATA_MASK 0xffff 268 DLLPR = 0xd0, 269 #define PFM_EN (1 << 6) 270 #define TX_10M_PS_EN (1 << 7) 271 DBG_REG = 0xd1, 272 #define FIX_NAK_1 (1 << 4) 273 #define FIX_NAK_2 (1 << 3) 274 TWSI = 0xd2, 275 MCU = 0xd3, 276 #define NOW_IS_OOB (1 << 7) 277 #define TX_EMPTY (1 << 5) 278 #define RX_EMPTY (1 << 4) 279 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 280 #define EN_NDP (1 << 3) 281 #define EN_OOB_RESET (1 << 2) 282 #define LINK_LIST_RDY (1 << 1) 283 EFUSEAR = 0xdc, 284 #define EFUSEAR_FLAG 0x80000000 285 #define EFUSEAR_WRITE_CMD 0x80000000 286 #define EFUSEAR_READ_CMD 0x00000000 287 #define EFUSEAR_REG_MASK 0x03ff 288 #define EFUSEAR_REG_SHIFT 8 289 #define EFUSEAR_DATA_MASK 0xff 290 MISC_1 = 0xf2, 291 #define PFM_D3COLD_EN (1 << 6) 292 }; 293 294 enum rtl8168_registers { 295 LED_CTRL = 0x18, 296 LED_FREQ = 0x1a, 297 EEE_LED = 0x1b, 298 ERIDR = 0x70, 299 ERIAR = 0x74, 300 #define ERIAR_FLAG 0x80000000 301 #define ERIAR_WRITE_CMD 0x80000000 302 #define ERIAR_READ_CMD 0x00000000 303 #define ERIAR_ADDR_BYTE_ALIGN 4 304 #define ERIAR_TYPE_SHIFT 16 305 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 306 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_MASK_SHIFT 12 310 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 311 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 315 EPHY_RXER_NUM = 0x7c, 316 OCPDR = 0xb0, /* OCP GPHY access */ 317 #define OCPDR_WRITE_CMD 0x80000000 318 #define OCPDR_READ_CMD 0x00000000 319 #define OCPDR_REG_MASK 0x7f 320 #define OCPDR_GPHY_REG_SHIFT 16 321 #define OCPDR_DATA_MASK 0xffff 322 OCPAR = 0xb4, 323 #define OCPAR_FLAG 0x80000000 324 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 325 #define OCPAR_GPHY_READ_CMD 0x0000f060 326 GPHY_OCP = 0xb8, 327 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 328 MISC = 0xf0, /* 8168e only. */ 329 #define TXPLA_RST (1 << 29) 330 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 331 #define PWM_EN (1 << 22) 332 #define RXDV_GATED_EN (1 << 19) 333 #define EARLY_TALLY_EN (1 << 16) 334 }; 335 336 enum rtl8125_registers { 337 LEDSEL0 = 0x18, 338 INT_CFG0_8125 = 0x34, 339 #define INT_CFG0_ENABLE_8125 BIT(0) 340 #define INT_CFG0_CLKREQEN BIT(3) 341 IntrMask_8125 = 0x38, 342 IntrStatus_8125 = 0x3c, 343 INT_CFG1_8125 = 0x7a, 344 LEDSEL2 = 0x84, 345 LEDSEL1 = 0x86, 346 TxPoll_8125 = 0x90, 347 LEDSEL3 = 0x96, 348 MAC0_BKP = 0x19e0, 349 RSS_CTRL_8125 = 0x4500, 350 Q_NUM_CTRL_8125 = 0x4800, 351 EEE_TXIDLE_TIMER_8125 = 0x6048, 352 }; 353 354 #define LEDSEL_MASK_8125 0x23f 355 356 #define RX_VLAN_INNER_8125 BIT(22) 357 #define RX_VLAN_OUTER_8125 BIT(23) 358 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 359 360 #define RX_FETCH_DFLT_8125 (8 << 27) 361 362 enum rtl_register_content { 363 /* InterruptStatusBits */ 364 SYSErr = 0x8000, 365 PCSTimeout = 0x4000, 366 SWInt = 0x0100, 367 TxDescUnavail = 0x0080, 368 RxFIFOOver = 0x0040, 369 LinkChg = 0x0020, 370 RxOverflow = 0x0010, 371 TxErr = 0x0008, 372 TxOK = 0x0004, 373 RxErr = 0x0002, 374 RxOK = 0x0001, 375 376 /* RxStatusDesc */ 377 RxRWT = (1 << 22), 378 RxRES = (1 << 21), 379 RxRUNT = (1 << 20), 380 RxCRC = (1 << 19), 381 382 /* ChipCmdBits */ 383 StopReq = 0x80, 384 CmdReset = 0x10, 385 CmdRxEnb = 0x08, 386 CmdTxEnb = 0x04, 387 RxBufEmpty = 0x01, 388 389 /* TXPoll register p.5 */ 390 HPQ = 0x80, /* Poll cmd on the high prio queue */ 391 NPQ = 0x40, /* Poll cmd on the low prio queue */ 392 FSWInt = 0x01, /* Forced software interrupt */ 393 394 /* Cfg9346Bits */ 395 Cfg9346_Lock = 0x00, 396 Cfg9346_Unlock = 0xc0, 397 398 /* rx_mode_bits */ 399 AcceptErr = 0x20, 400 AcceptRunt = 0x10, 401 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 402 AcceptBroadcast = 0x08, 403 AcceptMulticast = 0x04, 404 AcceptMyPhys = 0x02, 405 AcceptAllPhys = 0x01, 406 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 407 #define RX_CONFIG_ACCEPT_MASK 0x3f 408 409 /* TxConfigBits */ 410 TxInterFrameGapShift = 24, 411 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 412 413 /* Config1 register p.24 */ 414 LEDS1 = (1 << 7), 415 LEDS0 = (1 << 6), 416 Speed_down = (1 << 4), 417 MEMMAP = (1 << 3), 418 IOMAP = (1 << 2), 419 VPD = (1 << 1), 420 PMEnable = (1 << 0), /* Power Management Enable */ 421 422 /* Config2 register p. 25 */ 423 ClkReqEn = (1 << 7), /* Clock Request Enable */ 424 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 425 PCI_Clock_66MHz = 0x01, 426 PCI_Clock_33MHz = 0x00, 427 428 /* Config3 register p.25 */ 429 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 430 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 431 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 432 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 433 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 434 435 /* Config4 register */ 436 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 437 438 /* Config5 register p.27 */ 439 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 440 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 441 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 442 Spi_en = (1 << 3), 443 LanWake = (1 << 1), /* LanWake enable/disable */ 444 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 445 ASPM_en = (1 << 0), /* ASPM enable */ 446 447 /* CPlusCmd p.31 */ 448 EnableBist = (1 << 15), // 8168 8101 449 Mac_dbgo_oe = (1 << 14), // 8168 8101 450 EnAnaPLL = (1 << 14), // 8169 451 Normal_mode = (1 << 13), // unused 452 Force_half_dup = (1 << 12), // 8168 8101 453 Force_rxflow_en = (1 << 11), // 8168 8101 454 Force_txflow_en = (1 << 10), // 8168 8101 455 Cxpl_dbg_sel = (1 << 9), // 8168 8101 456 ASF = (1 << 8), // 8168 8101 457 PktCntrDisable = (1 << 7), // 8168 8101 458 Mac_dbgo_sel = 0x001c, // 8168 459 RxVlan = (1 << 6), 460 RxChkSum = (1 << 5), 461 PCIDAC = (1 << 4), 462 PCIMulRW = (1 << 3), 463 #define INTT_MASK GENMASK(1, 0) 464 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 465 466 /* rtl8169_PHYstatus */ 467 TBI_Enable = 0x80, 468 TxFlowCtrl = 0x40, 469 RxFlowCtrl = 0x20, 470 _1000bpsF = 0x10, 471 _100bps = 0x08, 472 _10bps = 0x04, 473 LinkStatus = 0x02, 474 FullDup = 0x01, 475 476 /* ResetCounterCommand */ 477 CounterReset = 0x1, 478 479 /* DumpCounterCommand */ 480 CounterDump = 0x8, 481 482 /* magic enable v2 */ 483 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 484 }; 485 486 enum rtl_desc_bit { 487 /* First doubleword. */ 488 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 489 RingEnd = (1 << 30), /* End of descriptor ring */ 490 FirstFrag = (1 << 29), /* First segment of a packet */ 491 LastFrag = (1 << 28), /* Final segment of a packet */ 492 }; 493 494 /* Generic case. */ 495 enum rtl_tx_desc_bit { 496 /* First doubleword. */ 497 TD_LSO = (1 << 27), /* Large Send Offload */ 498 #define TD_MSS_MAX 0x07ffu /* MSS value */ 499 500 /* Second doubleword. */ 501 TxVlanTag = (1 << 17), /* Add VLAN tag */ 502 }; 503 504 /* 8169, 8168b and 810x except 8102e. */ 505 enum rtl_tx_desc_bit_0 { 506 /* First doubleword. */ 507 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 508 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 509 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 510 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 511 }; 512 513 /* 8102e, 8168c and beyond. */ 514 enum rtl_tx_desc_bit_1 { 515 /* First doubleword. */ 516 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 517 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 518 #define GTTCPHO_SHIFT 18 519 #define GTTCPHO_MAX 0x7f 520 521 /* Second doubleword. */ 522 #define TCPHO_SHIFT 18 523 #define TCPHO_MAX 0x3ff 524 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 525 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 526 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 527 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 528 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 529 }; 530 531 enum rtl_rx_desc_bit { 532 /* Rx private */ 533 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 534 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 535 536 #define RxProtoUDP (PID1) 537 #define RxProtoTCP (PID0) 538 #define RxProtoIP (PID1 | PID0) 539 #define RxProtoMask RxProtoIP 540 541 IPFail = (1 << 16), /* IP checksum failed */ 542 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 543 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 544 545 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 546 547 RxVlanTag = (1 << 16), /* VLAN tag available */ 548 }; 549 550 #define RTL_GSO_MAX_SIZE_V1 32000 551 #define RTL_GSO_MAX_SEGS_V1 24 552 #define RTL_GSO_MAX_SIZE_V2 64000 553 #define RTL_GSO_MAX_SEGS_V2 64 554 555 struct TxDesc { 556 __le32 opts1; 557 __le32 opts2; 558 __le64 addr; 559 }; 560 561 struct RxDesc { 562 __le32 opts1; 563 __le32 opts2; 564 __le64 addr; 565 }; 566 567 struct ring_info { 568 struct sk_buff *skb; 569 u32 len; 570 }; 571 572 struct rtl8169_counters { 573 __le64 tx_packets; 574 __le64 rx_packets; 575 __le64 tx_errors; 576 __le32 rx_errors; 577 __le16 rx_missed; 578 __le16 align_errors; 579 __le32 tx_one_collision; 580 __le32 tx_multi_collision; 581 __le64 rx_unicast; 582 __le64 rx_broadcast; 583 __le32 rx_multicast; 584 __le16 tx_aborted; 585 __le16 tx_underrun; 586 /* new since RTL8125 */ 587 __le64 tx_octets; 588 __le64 rx_octets; 589 __le64 rx_multicast64; 590 __le64 tx_unicast64; 591 __le64 tx_broadcast64; 592 __le64 tx_multicast64; 593 __le32 tx_pause_on; 594 __le32 tx_pause_off; 595 __le32 tx_pause_all; 596 __le32 tx_deferred; 597 __le32 tx_late_collision; 598 __le32 tx_all_collision; 599 __le32 tx_aborted32; 600 __le32 align_errors32; 601 __le32 rx_frame_too_long; 602 __le32 rx_runt; 603 __le32 rx_pause_on; 604 __le32 rx_pause_off; 605 __le32 rx_pause_all; 606 __le32 rx_unknown_opcode; 607 __le32 rx_mac_error; 608 __le32 tx_underrun32; 609 __le32 rx_mac_missed; 610 __le32 rx_tcam_dropped; 611 __le32 tdu; 612 __le32 rdu; 613 }; 614 615 struct rtl8169_tc_offsets { 616 bool inited; 617 __le64 tx_errors; 618 __le32 tx_multi_collision; 619 __le16 tx_aborted; 620 __le16 rx_missed; 621 }; 622 623 enum rtl_flag { 624 RTL_FLAG_TASK_RESET_PENDING, 625 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 626 RTL_FLAG_TASK_TX_TIMEOUT, 627 RTL_FLAG_MAX 628 }; 629 630 enum rtl_dash_type { 631 RTL_DASH_NONE, 632 RTL_DASH_DP, 633 RTL_DASH_EP, 634 }; 635 636 struct rtl8169_private { 637 void __iomem *mmio_addr; /* memory map physical address */ 638 struct pci_dev *pci_dev; 639 struct net_device *dev; 640 struct phy_device *phydev; 641 struct napi_struct napi; 642 enum mac_version mac_version; 643 enum rtl_dash_type dash_type; 644 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 645 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 646 u32 dirty_tx; 647 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 648 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 649 dma_addr_t TxPhyAddr; 650 dma_addr_t RxPhyAddr; 651 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 652 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 653 u16 cp_cmd; 654 u16 tx_lpi_timer; 655 u32 irq_mask; 656 int irq; 657 struct clk *clk; 658 659 struct { 660 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 661 struct work_struct work; 662 } wk; 663 664 raw_spinlock_t mac_ocp_lock; 665 struct mutex led_lock; /* serialize LED ctrl RMW access */ 666 667 unsigned supports_gmii:1; 668 unsigned aspm_manageable:1; 669 unsigned dash_enabled:1; 670 dma_addr_t counters_phys_addr; 671 struct rtl8169_counters *counters; 672 struct rtl8169_tc_offsets tc_offset; 673 u32 saved_wolopts; 674 675 const char *fw_name; 676 struct rtl_fw *rtl_fw; 677 678 struct r8169_led_classdev *leds; 679 680 u32 ocp_base; 681 }; 682 683 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 684 685 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 686 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 687 MODULE_SOFTDEP("pre: realtek"); 688 MODULE_LICENSE("GPL"); 689 MODULE_FIRMWARE(FIRMWARE_8168D_1); 690 MODULE_FIRMWARE(FIRMWARE_8168D_2); 691 MODULE_FIRMWARE(FIRMWARE_8168E_1); 692 MODULE_FIRMWARE(FIRMWARE_8168E_2); 693 MODULE_FIRMWARE(FIRMWARE_8168E_3); 694 MODULE_FIRMWARE(FIRMWARE_8105E_1); 695 MODULE_FIRMWARE(FIRMWARE_8168F_1); 696 MODULE_FIRMWARE(FIRMWARE_8168F_2); 697 MODULE_FIRMWARE(FIRMWARE_8402_1); 698 MODULE_FIRMWARE(FIRMWARE_8411_1); 699 MODULE_FIRMWARE(FIRMWARE_8411_2); 700 MODULE_FIRMWARE(FIRMWARE_8106E_1); 701 MODULE_FIRMWARE(FIRMWARE_8106E_2); 702 MODULE_FIRMWARE(FIRMWARE_8168G_2); 703 MODULE_FIRMWARE(FIRMWARE_8168G_3); 704 MODULE_FIRMWARE(FIRMWARE_8168H_2); 705 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 706 MODULE_FIRMWARE(FIRMWARE_8107E_2); 707 MODULE_FIRMWARE(FIRMWARE_8125A_3); 708 MODULE_FIRMWARE(FIRMWARE_8125B_2); 709 MODULE_FIRMWARE(FIRMWARE_8125D_1); 710 MODULE_FIRMWARE(FIRMWARE_8126A_2); 711 MODULE_FIRMWARE(FIRMWARE_8126A_3); 712 713 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 714 { 715 return &tp->pci_dev->dev; 716 } 717 718 static void rtl_lock_config_regs(struct rtl8169_private *tp) 719 { 720 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 721 } 722 723 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 724 { 725 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 726 } 727 728 static void rtl_pci_commit(struct rtl8169_private *tp) 729 { 730 /* Read an arbitrary register to commit a preceding PCI write */ 731 RTL_R8(tp, ChipCmd); 732 } 733 734 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 735 { 736 u8 val; 737 738 val = RTL_R8(tp, Config2); 739 RTL_W8(tp, Config2, (val & ~clear) | set); 740 } 741 742 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 743 { 744 u8 val; 745 746 val = RTL_R8(tp, Config5); 747 RTL_W8(tp, Config5, (val & ~clear) | set); 748 } 749 750 static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg, 751 u8 bits, bool cond) 752 { 753 u8 val, old_val; 754 755 old_val = RTL_R8(tp, reg); 756 if (cond) 757 val = old_val | bits; 758 else 759 val = old_val & ~bits; 760 if (val != old_val) 761 RTL_W8(tp, reg, val); 762 } 763 764 static bool rtl_is_8125(struct rtl8169_private *tp) 765 { 766 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 767 } 768 769 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 770 { 771 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 772 tp->mac_version != RTL_GIGA_MAC_VER_39 && 773 tp->mac_version <= RTL_GIGA_MAC_VER_53; 774 } 775 776 static bool rtl_supports_eee(struct rtl8169_private *tp) 777 { 778 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 779 tp->mac_version != RTL_GIGA_MAC_VER_37 && 780 tp->mac_version != RTL_GIGA_MAC_VER_39; 781 } 782 783 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 784 { 785 int i; 786 787 for (i = 0; i < ETH_ALEN; i++) 788 mac[i] = RTL_R8(tp, reg + i); 789 } 790 791 struct rtl_cond { 792 bool (*check)(struct rtl8169_private *); 793 const char *msg; 794 }; 795 796 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 797 unsigned long usecs, int n, bool high) 798 { 799 int i; 800 801 for (i = 0; i < n; i++) { 802 if (c->check(tp) == high) 803 return true; 804 fsleep(usecs); 805 } 806 807 if (net_ratelimit()) 808 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 809 c->msg, !high, n, usecs); 810 return false; 811 } 812 813 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 814 const struct rtl_cond *c, 815 unsigned long d, int n) 816 { 817 return rtl_loop_wait(tp, c, d, n, true); 818 } 819 820 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 821 const struct rtl_cond *c, 822 unsigned long d, int n) 823 { 824 return rtl_loop_wait(tp, c, d, n, false); 825 } 826 827 #define DECLARE_RTL_COND(name) \ 828 static bool name ## _check(struct rtl8169_private *); \ 829 \ 830 static const struct rtl_cond name = { \ 831 .check = name ## _check, \ 832 .msg = #name \ 833 }; \ 834 \ 835 static bool name ## _check(struct rtl8169_private *tp) 836 837 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 838 { 839 struct device *dev = tp_to_dev(tp); 840 int ret; 841 842 ret = pm_runtime_resume_and_get(dev); 843 if (ret < 0) 844 return ret; 845 846 mutex_lock(&tp->led_lock); 847 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 848 mutex_unlock(&tp->led_lock); 849 850 pm_runtime_put_sync(dev); 851 852 return 0; 853 } 854 855 int rtl8168_get_led_mode(struct rtl8169_private *tp) 856 { 857 struct device *dev = tp_to_dev(tp); 858 int ret; 859 860 ret = pm_runtime_resume_and_get(dev); 861 if (ret < 0) 862 return ret; 863 864 ret = RTL_R16(tp, LED_CTRL); 865 866 pm_runtime_put_sync(dev); 867 868 return ret; 869 } 870 871 static int rtl8125_get_led_reg(int index) 872 { 873 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 874 875 return led_regs[index]; 876 } 877 878 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 879 { 880 int reg = rtl8125_get_led_reg(index); 881 struct device *dev = tp_to_dev(tp); 882 int ret; 883 u16 val; 884 885 ret = pm_runtime_resume_and_get(dev); 886 if (ret < 0) 887 return ret; 888 889 mutex_lock(&tp->led_lock); 890 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 891 RTL_W16(tp, reg, val | mode); 892 mutex_unlock(&tp->led_lock); 893 894 pm_runtime_put_sync(dev); 895 896 return 0; 897 } 898 899 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 900 { 901 int reg = rtl8125_get_led_reg(index); 902 struct device *dev = tp_to_dev(tp); 903 int ret; 904 905 ret = pm_runtime_resume_and_get(dev); 906 if (ret < 0) 907 return ret; 908 909 ret = RTL_R16(tp, reg); 910 911 pm_runtime_put_sync(dev); 912 913 return ret; 914 } 915 916 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 917 char *buf, int buf_len) 918 { 919 struct pci_dev *pdev = tp->pci_dev; 920 char pdom[8], pfun[8]; 921 int domain; 922 923 domain = pci_domain_nr(pdev->bus); 924 if (domain) 925 snprintf(pdom, sizeof(pdom), "P%d", domain); 926 else 927 pdom[0] = '\0'; 928 929 if (pdev->multifunction) 930 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 931 else 932 pfun[0] = '\0'; 933 934 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 935 PCI_SLOT(pdev->devfn), pfun, idx); 936 } 937 938 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 939 { 940 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 941 if (type == ERIAR_OOB && 942 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 943 tp->mac_version == RTL_GIGA_MAC_VER_53)) 944 *cmd |= 0xf70 << 18; 945 } 946 947 DECLARE_RTL_COND(rtl_eriar_cond) 948 { 949 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 950 } 951 952 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 953 u32 val, int type) 954 { 955 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 956 957 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 958 return; 959 960 RTL_W32(tp, ERIDR, val); 961 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 962 RTL_W32(tp, ERIAR, cmd); 963 964 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 965 } 966 967 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 968 u32 val) 969 { 970 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 971 } 972 973 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 974 { 975 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 976 977 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 978 RTL_W32(tp, ERIAR, cmd); 979 980 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 981 RTL_R32(tp, ERIDR) : ~0; 982 } 983 984 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 985 { 986 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 987 } 988 989 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 990 { 991 u32 val = rtl_eri_read(tp, addr); 992 993 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 994 } 995 996 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 997 { 998 rtl_w0w1_eri(tp, addr, p, 0); 999 } 1000 1001 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1002 { 1003 rtl_w0w1_eri(tp, addr, 0, m); 1004 } 1005 1006 static bool rtl_ocp_reg_failure(u32 reg) 1007 { 1008 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1009 } 1010 1011 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1012 { 1013 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1014 } 1015 1016 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1017 { 1018 if (rtl_ocp_reg_failure(reg)) 1019 return; 1020 1021 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1022 1023 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1024 } 1025 1026 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1027 { 1028 if (rtl_ocp_reg_failure(reg)) 1029 return 0; 1030 1031 RTL_W32(tp, GPHY_OCP, reg << 15); 1032 1033 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1034 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1035 } 1036 1037 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1038 { 1039 if (rtl_ocp_reg_failure(reg)) 1040 return; 1041 1042 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1043 } 1044 1045 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1046 { 1047 unsigned long flags; 1048 1049 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1050 __r8168_mac_ocp_write(tp, reg, data); 1051 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1052 } 1053 1054 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1055 { 1056 if (rtl_ocp_reg_failure(reg)) 1057 return 0; 1058 1059 RTL_W32(tp, OCPDR, reg << 15); 1060 1061 return RTL_R32(tp, OCPDR); 1062 } 1063 1064 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1065 { 1066 unsigned long flags; 1067 u16 val; 1068 1069 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1070 val = __r8168_mac_ocp_read(tp, reg); 1071 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1072 1073 return val; 1074 } 1075 1076 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1077 u16 set) 1078 { 1079 unsigned long flags; 1080 u16 data; 1081 1082 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1083 data = __r8168_mac_ocp_read(tp, reg); 1084 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1085 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1086 } 1087 1088 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1089 * PHY MCU interrupts before PHY power-down. 1090 */ 1091 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1092 { 1093 switch (tp->mac_version) { 1094 case RTL_GIGA_MAC_VER_40: 1095 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1096 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1097 else 1098 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1099 break; 1100 default: 1101 break; 1102 } 1103 }; 1104 1105 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1106 { 1107 if (reg == 0x1f) { 1108 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1109 return; 1110 } 1111 1112 if (tp->ocp_base != OCP_STD_PHY_BASE) 1113 reg -= 0x10; 1114 1115 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1116 rtl8168g_phy_suspend_quirk(tp, value); 1117 1118 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1119 } 1120 1121 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1122 { 1123 if (reg == 0x1f) 1124 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1125 1126 if (tp->ocp_base != OCP_STD_PHY_BASE) 1127 reg -= 0x10; 1128 1129 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1130 } 1131 1132 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1133 { 1134 if (reg == 0x1f) { 1135 tp->ocp_base = value << 4; 1136 return; 1137 } 1138 1139 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1140 } 1141 1142 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1143 { 1144 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1145 } 1146 1147 DECLARE_RTL_COND(rtl_phyar_cond) 1148 { 1149 return RTL_R32(tp, PHYAR) & 0x80000000; 1150 } 1151 1152 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1153 { 1154 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1155 1156 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1157 /* 1158 * According to hardware specs a 20us delay is required after write 1159 * complete indication, but before sending next command. 1160 */ 1161 udelay(20); 1162 } 1163 1164 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1165 { 1166 int value; 1167 1168 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1169 1170 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1171 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1172 1173 /* 1174 * According to hardware specs a 20us delay is required after read 1175 * complete indication, but before sending next command. 1176 */ 1177 udelay(20); 1178 1179 return value; 1180 } 1181 1182 DECLARE_RTL_COND(rtl_ocpar_cond) 1183 { 1184 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1185 } 1186 1187 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1188 1189 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1190 { 1191 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1192 } 1193 1194 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1195 { 1196 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1197 } 1198 1199 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1200 { 1201 r8168dp_2_mdio_start(tp); 1202 1203 r8169_mdio_write(tp, reg, value); 1204 1205 r8168dp_2_mdio_stop(tp); 1206 } 1207 1208 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1209 { 1210 int value; 1211 1212 /* Work around issue with chip reporting wrong PHY ID */ 1213 if (reg == MII_PHYSID2) 1214 return 0xc912; 1215 1216 r8168dp_2_mdio_start(tp); 1217 1218 value = r8169_mdio_read(tp, reg); 1219 1220 r8168dp_2_mdio_stop(tp); 1221 1222 return value; 1223 } 1224 1225 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1226 { 1227 switch (tp->mac_version) { 1228 case RTL_GIGA_MAC_VER_28: 1229 case RTL_GIGA_MAC_VER_31: 1230 r8168dp_2_mdio_write(tp, location, val); 1231 break; 1232 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1233 r8168g_mdio_write(tp, location, val); 1234 break; 1235 default: 1236 r8169_mdio_write(tp, location, val); 1237 break; 1238 } 1239 } 1240 1241 static int rtl_readphy(struct rtl8169_private *tp, int location) 1242 { 1243 switch (tp->mac_version) { 1244 case RTL_GIGA_MAC_VER_28: 1245 case RTL_GIGA_MAC_VER_31: 1246 return r8168dp_2_mdio_read(tp, location); 1247 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1248 return r8168g_mdio_read(tp, location); 1249 default: 1250 return r8169_mdio_read(tp, location); 1251 } 1252 } 1253 1254 DECLARE_RTL_COND(rtl_ephyar_cond) 1255 { 1256 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1257 } 1258 1259 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1260 { 1261 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1262 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1263 1264 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1265 1266 udelay(10); 1267 } 1268 1269 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1270 { 1271 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1272 1273 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1274 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1275 } 1276 1277 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1278 { 1279 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1280 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1281 RTL_R32(tp, OCPDR) : ~0; 1282 } 1283 1284 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1285 { 1286 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1287 } 1288 1289 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1290 u32 data) 1291 { 1292 RTL_W32(tp, OCPDR, data); 1293 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1294 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1295 } 1296 1297 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1298 u32 data) 1299 { 1300 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1301 data, ERIAR_OOB); 1302 } 1303 1304 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1305 { 1306 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1307 1308 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1309 } 1310 1311 #define OOB_CMD_RESET 0x00 1312 #define OOB_CMD_DRIVER_START 0x05 1313 #define OOB_CMD_DRIVER_STOP 0x06 1314 1315 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1316 { 1317 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1318 } 1319 1320 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1321 { 1322 u16 reg; 1323 1324 reg = rtl8168_get_ocp_reg(tp); 1325 1326 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1327 } 1328 1329 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1330 { 1331 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1332 } 1333 1334 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1335 { 1336 return RTL_R8(tp, IBISR0) & 0x20; 1337 } 1338 1339 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1340 { 1341 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1342 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1343 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1344 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1345 } 1346 1347 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1348 { 1349 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1350 if (tp->dash_enabled) 1351 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1352 } 1353 1354 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1355 { 1356 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1357 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1358 if (tp->dash_enabled) 1359 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1360 } 1361 1362 static void rtl8168_driver_start(struct rtl8169_private *tp) 1363 { 1364 if (tp->dash_type == RTL_DASH_DP) 1365 rtl8168dp_driver_start(tp); 1366 else 1367 rtl8168ep_driver_start(tp); 1368 } 1369 1370 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1371 { 1372 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1373 if (tp->dash_enabled) 1374 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1375 } 1376 1377 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1378 { 1379 rtl8168ep_stop_cmac(tp); 1380 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1381 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1382 if (tp->dash_enabled) 1383 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1384 } 1385 1386 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1387 { 1388 if (tp->dash_type == RTL_DASH_DP) 1389 rtl8168dp_driver_stop(tp); 1390 else 1391 rtl8168ep_driver_stop(tp); 1392 } 1393 1394 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1395 { 1396 u16 reg = rtl8168_get_ocp_reg(tp); 1397 1398 return r8168dp_ocp_read(tp, reg) & BIT(15); 1399 } 1400 1401 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1402 { 1403 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1404 } 1405 1406 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1407 { 1408 switch (tp->dash_type) { 1409 case RTL_DASH_DP: 1410 return r8168dp_check_dash(tp); 1411 case RTL_DASH_EP: 1412 return r8168ep_check_dash(tp); 1413 default: 1414 return false; 1415 } 1416 } 1417 1418 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1419 { 1420 switch (tp->mac_version) { 1421 case RTL_GIGA_MAC_VER_28: 1422 case RTL_GIGA_MAC_VER_31: 1423 return RTL_DASH_DP; 1424 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1425 return RTL_DASH_EP; 1426 default: 1427 return RTL_DASH_NONE; 1428 } 1429 } 1430 1431 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1432 { 1433 if (tp->mac_version >= RTL_GIGA_MAC_VER_25 && 1434 tp->mac_version != RTL_GIGA_MAC_VER_28 && 1435 tp->mac_version != RTL_GIGA_MAC_VER_31 && 1436 tp->mac_version != RTL_GIGA_MAC_VER_38) 1437 r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, !enable); 1438 } 1439 1440 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1441 { 1442 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1443 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1444 } 1445 1446 DECLARE_RTL_COND(rtl_efusear_cond) 1447 { 1448 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1449 } 1450 1451 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1452 { 1453 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1454 1455 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1456 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1457 } 1458 1459 static u32 rtl_get_events(struct rtl8169_private *tp) 1460 { 1461 if (rtl_is_8125(tp)) 1462 return RTL_R32(tp, IntrStatus_8125); 1463 else 1464 return RTL_R16(tp, IntrStatus); 1465 } 1466 1467 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1468 { 1469 if (rtl_is_8125(tp)) 1470 RTL_W32(tp, IntrStatus_8125, bits); 1471 else 1472 RTL_W16(tp, IntrStatus, bits); 1473 } 1474 1475 static void rtl_irq_disable(struct rtl8169_private *tp) 1476 { 1477 if (rtl_is_8125(tp)) 1478 RTL_W32(tp, IntrMask_8125, 0); 1479 else 1480 RTL_W16(tp, IntrMask, 0); 1481 } 1482 1483 static void rtl_irq_enable(struct rtl8169_private *tp) 1484 { 1485 if (rtl_is_8125(tp)) 1486 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1487 else 1488 RTL_W16(tp, IntrMask, tp->irq_mask); 1489 } 1490 1491 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1492 { 1493 rtl_irq_disable(tp); 1494 rtl_ack_events(tp, 0xffffffff); 1495 rtl_pci_commit(tp); 1496 } 1497 1498 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1499 { 1500 struct phy_device *phydev = tp->phydev; 1501 1502 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1503 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1504 if (phydev->speed == SPEED_1000) { 1505 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1506 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1507 } else if (phydev->speed == SPEED_100) { 1508 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1509 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1510 } else { 1511 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1512 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1513 } 1514 rtl_reset_packet_filter(tp); 1515 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1516 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1517 if (phydev->speed == SPEED_1000) { 1518 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1519 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1520 } else { 1521 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1522 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1523 } 1524 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1525 if (phydev->speed == SPEED_10) { 1526 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1527 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1528 } else { 1529 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1530 } 1531 } 1532 } 1533 1534 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1535 1536 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1537 { 1538 struct rtl8169_private *tp = netdev_priv(dev); 1539 1540 wol->supported = WAKE_ANY; 1541 wol->wolopts = tp->saved_wolopts; 1542 } 1543 1544 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1545 { 1546 rtl_unlock_config_regs(tp); 1547 1548 if (rtl_is_8168evl_up(tp)) { 1549 if (wolopts & WAKE_MAGIC) 1550 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1551 else 1552 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1553 } else if (rtl_is_8125(tp)) { 1554 if (wolopts & WAKE_MAGIC) 1555 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1556 else 1557 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1558 } else { 1559 r8169_mod_reg8_cond(tp, Config3, MagicPacket, 1560 wolopts & WAKE_MAGIC); 1561 } 1562 1563 r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY); 1564 if (rtl_is_8125(tp)) 1565 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, 1566 wolopts & WAKE_PHY ? 0x13 : 0); 1567 r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST); 1568 r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST); 1569 r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST); 1570 r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts); 1571 1572 switch (tp->mac_version) { 1573 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1574 r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts); 1575 break; 1576 case RTL_GIGA_MAC_VER_34: 1577 case RTL_GIGA_MAC_VER_37: 1578 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1579 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); 1580 break; 1581 default: 1582 break; 1583 } 1584 1585 rtl_lock_config_regs(tp); 1586 1587 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1588 1589 if (!tp->dash_enabled) { 1590 rtl_set_d3_pll_down(tp, !wolopts); 1591 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1592 } 1593 } 1594 1595 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1596 { 1597 struct rtl8169_private *tp = netdev_priv(dev); 1598 1599 if (wol->wolopts & ~WAKE_ANY) 1600 return -EINVAL; 1601 1602 tp->saved_wolopts = wol->wolopts; 1603 __rtl8169_set_wol(tp, tp->saved_wolopts); 1604 1605 return 0; 1606 } 1607 1608 static void rtl8169_get_drvinfo(struct net_device *dev, 1609 struct ethtool_drvinfo *info) 1610 { 1611 struct rtl8169_private *tp = netdev_priv(dev); 1612 struct rtl_fw *rtl_fw = tp->rtl_fw; 1613 1614 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1615 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1616 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1617 if (rtl_fw) 1618 strscpy(info->fw_version, rtl_fw->version, 1619 sizeof(info->fw_version)); 1620 } 1621 1622 static int rtl8169_get_regs_len(struct net_device *dev) 1623 { 1624 return R8169_REGS_SIZE; 1625 } 1626 1627 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1628 netdev_features_t features) 1629 { 1630 struct rtl8169_private *tp = netdev_priv(dev); 1631 1632 if (dev->mtu > TD_MSS_MAX) 1633 features &= ~NETIF_F_ALL_TSO; 1634 1635 if (dev->mtu > ETH_DATA_LEN && 1636 tp->mac_version > RTL_GIGA_MAC_VER_06) 1637 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1638 1639 return features; 1640 } 1641 1642 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1643 netdev_features_t features) 1644 { 1645 u32 rx_config = RTL_R32(tp, RxConfig); 1646 1647 if (features & NETIF_F_RXALL) 1648 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1649 else 1650 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1651 1652 if (rtl_is_8125(tp)) { 1653 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1654 rx_config |= RX_VLAN_8125; 1655 else 1656 rx_config &= ~RX_VLAN_8125; 1657 } 1658 1659 RTL_W32(tp, RxConfig, rx_config); 1660 } 1661 1662 static int rtl8169_set_features(struct net_device *dev, 1663 netdev_features_t features) 1664 { 1665 struct rtl8169_private *tp = netdev_priv(dev); 1666 1667 rtl_set_rx_config_features(tp, features); 1668 1669 if (features & NETIF_F_RXCSUM) 1670 tp->cp_cmd |= RxChkSum; 1671 else 1672 tp->cp_cmd &= ~RxChkSum; 1673 1674 if (!rtl_is_8125(tp)) { 1675 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1676 tp->cp_cmd |= RxVlan; 1677 else 1678 tp->cp_cmd &= ~RxVlan; 1679 } 1680 1681 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1682 rtl_pci_commit(tp); 1683 1684 return 0; 1685 } 1686 1687 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1688 { 1689 return (skb_vlan_tag_present(skb)) ? 1690 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1691 } 1692 1693 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1694 { 1695 u32 opts2 = le32_to_cpu(desc->opts2); 1696 1697 if (opts2 & RxVlanTag) 1698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1699 } 1700 1701 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1702 void *p) 1703 { 1704 struct rtl8169_private *tp = netdev_priv(dev); 1705 u32 __iomem *data = tp->mmio_addr; 1706 u32 *dw = p; 1707 int i; 1708 1709 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1710 memcpy_fromio(dw++, data++, 4); 1711 } 1712 1713 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1714 "tx_packets", 1715 "rx_packets", 1716 "tx_errors", 1717 "rx_errors", 1718 "rx_missed", 1719 "align_errors", 1720 "tx_single_collisions", 1721 "tx_multi_collisions", 1722 "unicast", 1723 "broadcast", 1724 "multicast", 1725 "tx_aborted", 1726 "tx_underrun", 1727 }; 1728 1729 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1730 { 1731 switch (sset) { 1732 case ETH_SS_STATS: 1733 return ARRAY_SIZE(rtl8169_gstrings); 1734 default: 1735 return -EOPNOTSUPP; 1736 } 1737 } 1738 1739 DECLARE_RTL_COND(rtl_counters_cond) 1740 { 1741 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1742 } 1743 1744 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1745 { 1746 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1747 1748 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1749 rtl_pci_commit(tp); 1750 RTL_W32(tp, CounterAddrLow, cmd); 1751 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1752 1753 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1754 } 1755 1756 static void rtl8169_update_counters(struct rtl8169_private *tp) 1757 { 1758 u8 val = RTL_R8(tp, ChipCmd); 1759 1760 /* 1761 * Some chips are unable to dump tally counters when the receiver 1762 * is disabled. If 0xff chip may be in a PCI power-save state. 1763 */ 1764 if (val & CmdRxEnb && val != 0xff) 1765 rtl8169_do_counters(tp, CounterDump); 1766 } 1767 1768 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1769 { 1770 struct rtl8169_counters *counters = tp->counters; 1771 1772 /* 1773 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1774 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1775 * reset by a power cycle, while the counter values collected by the 1776 * driver are reset at every driver unload/load cycle. 1777 * 1778 * To make sure the HW values returned by @get_stats64 match the SW 1779 * values, we collect the initial values at first open(*) and use them 1780 * as offsets to normalize the values returned by @get_stats64. 1781 * 1782 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1783 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1784 * set at open time by rtl_hw_start. 1785 */ 1786 1787 if (tp->tc_offset.inited) 1788 return; 1789 1790 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1791 rtl8169_do_counters(tp, CounterReset); 1792 } else { 1793 rtl8169_update_counters(tp); 1794 tp->tc_offset.tx_errors = counters->tx_errors; 1795 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1796 tp->tc_offset.tx_aborted = counters->tx_aborted; 1797 tp->tc_offset.rx_missed = counters->rx_missed; 1798 } 1799 1800 tp->tc_offset.inited = true; 1801 } 1802 1803 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1804 struct ethtool_stats *stats, u64 *data) 1805 { 1806 struct rtl8169_private *tp = netdev_priv(dev); 1807 struct rtl8169_counters *counters; 1808 1809 counters = tp->counters; 1810 rtl8169_update_counters(tp); 1811 1812 data[0] = le64_to_cpu(counters->tx_packets); 1813 data[1] = le64_to_cpu(counters->rx_packets); 1814 data[2] = le64_to_cpu(counters->tx_errors); 1815 data[3] = le32_to_cpu(counters->rx_errors); 1816 data[4] = le16_to_cpu(counters->rx_missed); 1817 data[5] = le16_to_cpu(counters->align_errors); 1818 data[6] = le32_to_cpu(counters->tx_one_collision); 1819 data[7] = le32_to_cpu(counters->tx_multi_collision); 1820 data[8] = le64_to_cpu(counters->rx_unicast); 1821 data[9] = le64_to_cpu(counters->rx_broadcast); 1822 data[10] = le32_to_cpu(counters->rx_multicast); 1823 data[11] = le16_to_cpu(counters->tx_aborted); 1824 data[12] = le16_to_cpu(counters->tx_underrun); 1825 } 1826 1827 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1828 { 1829 switch(stringset) { 1830 case ETH_SS_STATS: 1831 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1832 break; 1833 } 1834 } 1835 1836 /* 1837 * Interrupt coalescing 1838 * 1839 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1840 * > 8169, 8168 and 810x line of chipsets 1841 * 1842 * 8169, 8168, and 8136(810x) serial chipsets support it. 1843 * 1844 * > 2 - the Tx timer unit at gigabit speed 1845 * 1846 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1847 * (0xe0) bit 1 and bit 0. 1848 * 1849 * For 8169 1850 * bit[1:0] \ speed 1000M 100M 10M 1851 * 0 0 320ns 2.56us 40.96us 1852 * 0 1 2.56us 20.48us 327.7us 1853 * 1 0 5.12us 40.96us 655.4us 1854 * 1 1 10.24us 81.92us 1.31ms 1855 * 1856 * For the other 1857 * bit[1:0] \ speed 1000M 100M 10M 1858 * 0 0 5us 2.56us 40.96us 1859 * 0 1 40us 20.48us 327.7us 1860 * 1 0 80us 40.96us 655.4us 1861 * 1 1 160us 81.92us 1.31ms 1862 */ 1863 1864 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1865 struct rtl_coalesce_info { 1866 u32 speed; 1867 u32 scale_nsecs[4]; 1868 }; 1869 1870 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1871 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1872 1873 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1874 { SPEED_1000, COALESCE_DELAY(320) }, 1875 { SPEED_100, COALESCE_DELAY(2560) }, 1876 { SPEED_10, COALESCE_DELAY(40960) }, 1877 { 0 }, 1878 }; 1879 1880 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1881 { SPEED_1000, COALESCE_DELAY(5000) }, 1882 { SPEED_100, COALESCE_DELAY(2560) }, 1883 { SPEED_10, COALESCE_DELAY(40960) }, 1884 { 0 }, 1885 }; 1886 #undef COALESCE_DELAY 1887 1888 /* get rx/tx scale vector corresponding to current speed */ 1889 static const struct rtl_coalesce_info * 1890 rtl_coalesce_info(struct rtl8169_private *tp) 1891 { 1892 const struct rtl_coalesce_info *ci; 1893 1894 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1895 ci = rtl_coalesce_info_8169; 1896 else 1897 ci = rtl_coalesce_info_8168_8136; 1898 1899 /* if speed is unknown assume highest one */ 1900 if (tp->phydev->speed == SPEED_UNKNOWN) 1901 return ci; 1902 1903 for (; ci->speed; ci++) { 1904 if (tp->phydev->speed == ci->speed) 1905 return ci; 1906 } 1907 1908 return ERR_PTR(-ELNRNG); 1909 } 1910 1911 static int rtl_get_coalesce(struct net_device *dev, 1912 struct ethtool_coalesce *ec, 1913 struct kernel_ethtool_coalesce *kernel_coal, 1914 struct netlink_ext_ack *extack) 1915 { 1916 struct rtl8169_private *tp = netdev_priv(dev); 1917 const struct rtl_coalesce_info *ci; 1918 u32 scale, c_us, c_fr; 1919 u16 intrmit; 1920 1921 if (rtl_is_8125(tp)) 1922 return -EOPNOTSUPP; 1923 1924 memset(ec, 0, sizeof(*ec)); 1925 1926 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1927 ci = rtl_coalesce_info(tp); 1928 if (IS_ERR(ci)) 1929 return PTR_ERR(ci); 1930 1931 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1932 1933 intrmit = RTL_R16(tp, IntrMitigate); 1934 1935 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1936 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1937 1938 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1939 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1940 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1941 1942 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1943 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1944 1945 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1946 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1947 1948 return 0; 1949 } 1950 1951 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1952 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1953 u16 *cp01) 1954 { 1955 const struct rtl_coalesce_info *ci; 1956 u16 i; 1957 1958 ci = rtl_coalesce_info(tp); 1959 if (IS_ERR(ci)) 1960 return PTR_ERR(ci); 1961 1962 for (i = 0; i < 4; i++) { 1963 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1964 *cp01 = i; 1965 return ci->scale_nsecs[i]; 1966 } 1967 } 1968 1969 return -ERANGE; 1970 } 1971 1972 static int rtl_set_coalesce(struct net_device *dev, 1973 struct ethtool_coalesce *ec, 1974 struct kernel_ethtool_coalesce *kernel_coal, 1975 struct netlink_ext_ack *extack) 1976 { 1977 struct rtl8169_private *tp = netdev_priv(dev); 1978 u32 tx_fr = ec->tx_max_coalesced_frames; 1979 u32 rx_fr = ec->rx_max_coalesced_frames; 1980 u32 coal_usec_max, units; 1981 u16 w = 0, cp01 = 0; 1982 int scale; 1983 1984 if (rtl_is_8125(tp)) 1985 return -EOPNOTSUPP; 1986 1987 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1988 return -ERANGE; 1989 1990 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1991 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1992 if (scale < 0) 1993 return scale; 1994 1995 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1996 * not only when usecs=0 because of e.g. the following scenario: 1997 * 1998 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1999 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2000 * - then user does `ethtool -C eth0 rx-usecs 100` 2001 * 2002 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2003 * if we want to ignore rx_frames then it has to be set to 0. 2004 */ 2005 if (rx_fr == 1) 2006 rx_fr = 0; 2007 if (tx_fr == 1) 2008 tx_fr = 0; 2009 2010 /* HW requires time limit to be set if frame limit is set */ 2011 if ((tx_fr && !ec->tx_coalesce_usecs) || 2012 (rx_fr && !ec->rx_coalesce_usecs)) 2013 return -EINVAL; 2014 2015 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2016 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2017 2018 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2019 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2020 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2021 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2022 2023 RTL_W16(tp, IntrMitigate, w); 2024 2025 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2026 if (rtl_is_8168evl_up(tp)) { 2027 if (!rx_fr && !tx_fr) 2028 /* disable packet counter */ 2029 tp->cp_cmd |= PktCntrDisable; 2030 else 2031 tp->cp_cmd &= ~PktCntrDisable; 2032 } 2033 2034 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2035 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2036 rtl_pci_commit(tp); 2037 2038 return 0; 2039 } 2040 2041 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2042 { 2043 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2044 2045 switch (tp->mac_version) { 2046 case RTL_GIGA_MAC_VER_46: 2047 case RTL_GIGA_MAC_VER_48: 2048 tp->tx_lpi_timer = timer_val; 2049 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2050 break; 2051 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2052 tp->tx_lpi_timer = timer_val; 2053 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2054 break; 2055 default: 2056 break; 2057 } 2058 } 2059 2060 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2061 { 2062 unsigned int speed = tp->phydev->speed; 2063 unsigned int timer = tp->tx_lpi_timer; 2064 2065 if (!timer || speed == SPEED_UNKNOWN) 2066 return 0; 2067 2068 /* tx_lpi_timer value is in bytes */ 2069 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2070 } 2071 2072 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2073 { 2074 struct rtl8169_private *tp = netdev_priv(dev); 2075 int ret; 2076 2077 if (!rtl_supports_eee(tp)) 2078 return -EOPNOTSUPP; 2079 2080 ret = phy_ethtool_get_eee(tp->phydev, data); 2081 if (ret) 2082 return ret; 2083 2084 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2085 2086 return 0; 2087 } 2088 2089 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2090 { 2091 struct rtl8169_private *tp = netdev_priv(dev); 2092 2093 if (!rtl_supports_eee(tp)) 2094 return -EOPNOTSUPP; 2095 2096 return phy_ethtool_set_eee(tp->phydev, data); 2097 } 2098 2099 static void rtl8169_get_ringparam(struct net_device *dev, 2100 struct ethtool_ringparam *data, 2101 struct kernel_ethtool_ringparam *kernel_data, 2102 struct netlink_ext_ack *extack) 2103 { 2104 data->rx_max_pending = NUM_RX_DESC; 2105 data->rx_pending = NUM_RX_DESC; 2106 data->tx_max_pending = NUM_TX_DESC; 2107 data->tx_pending = NUM_TX_DESC; 2108 } 2109 2110 static void rtl8169_get_pause_stats(struct net_device *dev, 2111 struct ethtool_pause_stats *pause_stats) 2112 { 2113 struct rtl8169_private *tp = netdev_priv(dev); 2114 2115 if (!rtl_is_8125(tp)) 2116 return; 2117 2118 rtl8169_update_counters(tp); 2119 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on); 2120 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on); 2121 } 2122 2123 static void rtl8169_get_pauseparam(struct net_device *dev, 2124 struct ethtool_pauseparam *data) 2125 { 2126 struct rtl8169_private *tp = netdev_priv(dev); 2127 bool tx_pause, rx_pause; 2128 2129 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2130 2131 data->autoneg = tp->phydev->autoneg; 2132 data->tx_pause = tx_pause ? 1 : 0; 2133 data->rx_pause = rx_pause ? 1 : 0; 2134 } 2135 2136 static int rtl8169_set_pauseparam(struct net_device *dev, 2137 struct ethtool_pauseparam *data) 2138 { 2139 struct rtl8169_private *tp = netdev_priv(dev); 2140 2141 if (dev->mtu > ETH_DATA_LEN) 2142 return -EOPNOTSUPP; 2143 2144 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2145 2146 return 0; 2147 } 2148 2149 static void rtl8169_get_eth_mac_stats(struct net_device *dev, 2150 struct ethtool_eth_mac_stats *mac_stats) 2151 { 2152 struct rtl8169_private *tp = netdev_priv(dev); 2153 2154 rtl8169_update_counters(tp); 2155 2156 mac_stats->FramesTransmittedOK = 2157 le64_to_cpu(tp->counters->tx_packets); 2158 mac_stats->SingleCollisionFrames = 2159 le32_to_cpu(tp->counters->tx_one_collision); 2160 mac_stats->MultipleCollisionFrames = 2161 le32_to_cpu(tp->counters->tx_multi_collision); 2162 mac_stats->FramesReceivedOK = 2163 le64_to_cpu(tp->counters->rx_packets); 2164 mac_stats->AlignmentErrors = 2165 le16_to_cpu(tp->counters->align_errors); 2166 mac_stats->FramesLostDueToIntMACXmitError = 2167 le64_to_cpu(tp->counters->tx_errors); 2168 mac_stats->BroadcastFramesReceivedOK = 2169 le64_to_cpu(tp->counters->rx_broadcast); 2170 mac_stats->MulticastFramesReceivedOK = 2171 le32_to_cpu(tp->counters->rx_multicast); 2172 2173 if (!rtl_is_8125(tp)) 2174 return; 2175 2176 mac_stats->AlignmentErrors = 2177 le32_to_cpu(tp->counters->align_errors32); 2178 mac_stats->OctetsTransmittedOK = 2179 le64_to_cpu(tp->counters->tx_octets); 2180 mac_stats->LateCollisions = 2181 le32_to_cpu(tp->counters->tx_late_collision); 2182 mac_stats->FramesAbortedDueToXSColls = 2183 le32_to_cpu(tp->counters->tx_aborted32); 2184 mac_stats->OctetsReceivedOK = 2185 le64_to_cpu(tp->counters->rx_octets); 2186 mac_stats->FramesLostDueToIntMACRcvError = 2187 le32_to_cpu(tp->counters->rx_mac_error); 2188 mac_stats->MulticastFramesXmittedOK = 2189 le64_to_cpu(tp->counters->tx_multicast64); 2190 mac_stats->BroadcastFramesXmittedOK = 2191 le64_to_cpu(tp->counters->tx_broadcast64); 2192 mac_stats->MulticastFramesReceivedOK = 2193 le64_to_cpu(tp->counters->rx_multicast64); 2194 mac_stats->FrameTooLongErrors = 2195 le32_to_cpu(tp->counters->rx_frame_too_long); 2196 } 2197 2198 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, 2199 struct ethtool_eth_ctrl_stats *ctrl_stats) 2200 { 2201 struct rtl8169_private *tp = netdev_priv(dev); 2202 2203 if (!rtl_is_8125(tp)) 2204 return; 2205 2206 rtl8169_update_counters(tp); 2207 2208 ctrl_stats->UnsupportedOpcodesReceived = 2209 le32_to_cpu(tp->counters->rx_unknown_opcode); 2210 } 2211 2212 static const struct ethtool_ops rtl8169_ethtool_ops = { 2213 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2214 ETHTOOL_COALESCE_MAX_FRAMES, 2215 .get_drvinfo = rtl8169_get_drvinfo, 2216 .get_regs_len = rtl8169_get_regs_len, 2217 .get_link = ethtool_op_get_link, 2218 .get_coalesce = rtl_get_coalesce, 2219 .set_coalesce = rtl_set_coalesce, 2220 .get_regs = rtl8169_get_regs, 2221 .get_wol = rtl8169_get_wol, 2222 .set_wol = rtl8169_set_wol, 2223 .get_strings = rtl8169_get_strings, 2224 .get_sset_count = rtl8169_get_sset_count, 2225 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2226 .get_ts_info = ethtool_op_get_ts_info, 2227 .nway_reset = phy_ethtool_nway_reset, 2228 .get_eee = rtl8169_get_eee, 2229 .set_eee = rtl8169_set_eee, 2230 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2231 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2232 .get_ringparam = rtl8169_get_ringparam, 2233 .get_pause_stats = rtl8169_get_pause_stats, 2234 .get_pauseparam = rtl8169_get_pauseparam, 2235 .set_pauseparam = rtl8169_set_pauseparam, 2236 .get_eth_mac_stats = rtl8169_get_eth_mac_stats, 2237 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, 2238 }; 2239 2240 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2241 { 2242 /* 2243 * The driver currently handles the 8168Bf and the 8168Be identically 2244 * but they can be identified more specifically through the test below 2245 * if needed: 2246 * 2247 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2248 * 2249 * Same thing for the 8101Eb and the 8101Ec: 2250 * 2251 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2252 */ 2253 static const struct rtl_mac_info { 2254 u16 mask; 2255 u16 val; 2256 enum mac_version ver; 2257 } mac_info[] = { 2258 /* 8126A family. */ 2259 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 }, 2260 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2261 2262 /* 8125D family. */ 2263 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, 2264 2265 /* 8125B family. */ 2266 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2267 2268 /* 8125A family. */ 2269 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2270 /* It seems only XID 609 made it to the mass market. 2271 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2272 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2273 */ 2274 2275 /* RTL8117 */ 2276 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2277 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2278 2279 /* 8168EP family. */ 2280 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2281 /* It seems this chip version never made it to 2282 * the wild. Let's disable detection. 2283 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2284 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2285 */ 2286 2287 /* 8168H family. */ 2288 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2289 /* It seems this chip version never made it to 2290 * the wild. Let's disable detection. 2291 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2292 */ 2293 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 2294 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, 2295 2296 /* 8168G family. */ 2297 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2298 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2299 /* It seems this chip version never made it to 2300 * the wild. Let's disable detection. 2301 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2302 */ 2303 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2304 2305 /* 8168F family. */ 2306 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2307 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2308 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2309 2310 /* 8168E family. */ 2311 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2312 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2313 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2314 2315 /* 8168D family. */ 2316 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2317 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2318 2319 /* 8168DP family. */ 2320 /* It seems this early RTL8168dp version never made it to 2321 * the wild. Support has been removed. 2322 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2323 */ 2324 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2325 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2326 2327 /* 8168C family. */ 2328 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2329 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2330 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2331 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2332 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2333 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2334 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2335 2336 /* 8168B family. */ 2337 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2338 /* This one is very old and rare, let's see if anybody complains. 2339 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2340 */ 2341 2342 /* 8101 family. */ 2343 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2344 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2345 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2346 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2347 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2348 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2349 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2350 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2351 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2352 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2353 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2354 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2355 2356 /* 8110 family. */ 2357 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2358 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2359 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2360 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2361 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2362 2363 /* Catch-all */ 2364 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2365 }; 2366 const struct rtl_mac_info *p = mac_info; 2367 enum mac_version ver; 2368 2369 while ((xid & p->mask) != p->val) 2370 p++; 2371 ver = p->ver; 2372 2373 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2374 if (ver == RTL_GIGA_MAC_VER_42) 2375 ver = RTL_GIGA_MAC_VER_43; 2376 else if (ver == RTL_GIGA_MAC_VER_46) 2377 ver = RTL_GIGA_MAC_VER_48; 2378 } 2379 2380 return ver; 2381 } 2382 2383 static void rtl_release_firmware(struct rtl8169_private *tp) 2384 { 2385 if (tp->rtl_fw) { 2386 rtl_fw_release_firmware(tp->rtl_fw); 2387 kfree(tp->rtl_fw); 2388 tp->rtl_fw = NULL; 2389 } 2390 } 2391 2392 void r8169_apply_firmware(struct rtl8169_private *tp) 2393 { 2394 int val; 2395 2396 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2397 if (tp->rtl_fw) { 2398 rtl_fw_write_firmware(tp, tp->rtl_fw); 2399 /* At least one firmware doesn't reset tp->ocp_base. */ 2400 tp->ocp_base = OCP_STD_PHY_BASE; 2401 2402 /* PHY soft reset may still be in progress */ 2403 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2404 !(val & BMCR_RESET), 2405 50000, 600000, true); 2406 } 2407 } 2408 2409 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2410 { 2411 /* Adjust EEE LED frequency */ 2412 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2413 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2414 2415 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2416 } 2417 2418 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2419 { 2420 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2421 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2422 } 2423 2424 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2425 { 2426 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2427 } 2428 2429 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2430 { 2431 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2432 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2433 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2434 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2435 } 2436 2437 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2438 { 2439 u16 data1, data2, ioffset; 2440 2441 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2442 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2443 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2444 2445 ioffset = (data2 >> 1) & 0x7ff8; 2446 ioffset |= data2 & 0x0007; 2447 if (data1 & BIT(7)) 2448 ioffset |= BIT(15); 2449 2450 return ioffset; 2451 } 2452 2453 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2454 { 2455 set_bit(flag, tp->wk.flags); 2456 if (!schedule_work(&tp->wk.work)) 2457 clear_bit(flag, tp->wk.flags); 2458 } 2459 2460 static void rtl8169_init_phy(struct rtl8169_private *tp) 2461 { 2462 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2463 2464 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2465 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2466 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2467 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2468 RTL_W8(tp, 0x82, 0x01); 2469 } 2470 2471 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2472 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2473 tp->pci_dev->subsystem_device == 0xe000) 2474 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2475 2476 /* We may have called phy_speed_down before */ 2477 phy_speed_up(tp->phydev); 2478 2479 genphy_soft_reset(tp->phydev); 2480 } 2481 2482 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2483 { 2484 rtl_unlock_config_regs(tp); 2485 2486 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2487 rtl_pci_commit(tp); 2488 2489 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2490 rtl_pci_commit(tp); 2491 2492 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2493 rtl_rar_exgmac_set(tp, addr); 2494 2495 rtl_lock_config_regs(tp); 2496 } 2497 2498 static int rtl_set_mac_address(struct net_device *dev, void *p) 2499 { 2500 struct rtl8169_private *tp = netdev_priv(dev); 2501 int ret; 2502 2503 ret = eth_mac_addr(dev, p); 2504 if (ret) 2505 return ret; 2506 2507 rtl_rar_set(tp, dev->dev_addr); 2508 2509 return 0; 2510 } 2511 2512 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2513 { 2514 switch (tp->mac_version) { 2515 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2516 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2517 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2518 break; 2519 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2520 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2521 case RTL_GIGA_MAC_VER_38: 2522 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2523 break; 2524 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2525 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2526 break; 2527 case RTL_GIGA_MAC_VER_61: 2528 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2529 break; 2530 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2531 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2532 RX_PAUSE_SLOT_ON); 2533 break; 2534 default: 2535 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2536 break; 2537 } 2538 } 2539 2540 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2541 { 2542 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2543 } 2544 2545 static void rtl_jumbo_config(struct rtl8169_private *tp) 2546 { 2547 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2548 int readrq = 4096; 2549 2550 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 && 2551 tp->mac_version <= RTL_GIGA_MAC_VER_26) 2552 readrq = 512; 2553 2554 rtl_unlock_config_regs(tp); 2555 switch (tp->mac_version) { 2556 case RTL_GIGA_MAC_VER_17: 2557 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2558 break; 2559 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2560 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2561 r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo); 2562 break; 2563 case RTL_GIGA_MAC_VER_28: 2564 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2565 break; 2566 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2567 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); 2568 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2569 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2570 break; 2571 default: 2572 break; 2573 } 2574 rtl_lock_config_regs(tp); 2575 2576 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2577 pcie_set_readrq(tp->pci_dev, readrq); 2578 2579 /* Chip doesn't support pause in jumbo mode */ 2580 if (jumbo) { 2581 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2582 tp->phydev->advertising); 2583 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2584 tp->phydev->advertising); 2585 phy_start_aneg(tp->phydev); 2586 } 2587 } 2588 2589 DECLARE_RTL_COND(rtl_chipcmd_cond) 2590 { 2591 return RTL_R8(tp, ChipCmd) & CmdReset; 2592 } 2593 2594 static void rtl_hw_reset(struct rtl8169_private *tp) 2595 { 2596 RTL_W8(tp, ChipCmd, CmdReset); 2597 2598 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2599 } 2600 2601 static void rtl_request_firmware(struct rtl8169_private *tp) 2602 { 2603 struct rtl_fw *rtl_fw; 2604 2605 /* firmware loaded already or no firmware available */ 2606 if (tp->rtl_fw || !tp->fw_name) 2607 return; 2608 2609 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2610 if (!rtl_fw) 2611 return; 2612 2613 rtl_fw->phy_write = rtl_writephy; 2614 rtl_fw->phy_read = rtl_readphy; 2615 rtl_fw->mac_mcu_write = mac_mcu_write; 2616 rtl_fw->mac_mcu_read = mac_mcu_read; 2617 rtl_fw->fw_name = tp->fw_name; 2618 rtl_fw->dev = tp_to_dev(tp); 2619 2620 if (rtl_fw_request_firmware(rtl_fw)) 2621 kfree(rtl_fw); 2622 else 2623 tp->rtl_fw = rtl_fw; 2624 } 2625 2626 static void rtl_rx_close(struct rtl8169_private *tp) 2627 { 2628 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2629 } 2630 2631 DECLARE_RTL_COND(rtl_npq_cond) 2632 { 2633 return RTL_R8(tp, TxPoll) & NPQ; 2634 } 2635 2636 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2637 { 2638 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2639 } 2640 2641 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2642 { 2643 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2644 } 2645 2646 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2647 { 2648 /* IntrMitigate has new functionality on RTL8125 */ 2649 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2650 } 2651 2652 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2653 { 2654 switch (tp->mac_version) { 2655 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2656 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2657 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2658 break; 2659 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2660 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2661 break; 2662 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2663 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2664 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2665 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2666 break; 2667 default: 2668 break; 2669 } 2670 } 2671 2672 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2673 { 2674 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2675 } 2676 2677 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2678 { 2679 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2680 fsleep(2000); 2681 rtl_wait_txrx_fifo_empty(tp); 2682 } 2683 2684 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2685 { 2686 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2687 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2688 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2689 2690 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2691 rtl_disable_rxdvgate(tp); 2692 } 2693 2694 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2695 { 2696 if (tp->dash_enabled) 2697 return; 2698 2699 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2700 tp->mac_version == RTL_GIGA_MAC_VER_33) 2701 rtl_ephy_write(tp, 0x19, 0xff64); 2702 2703 if (device_may_wakeup(tp_to_dev(tp))) { 2704 phy_speed_down(tp->phydev, false); 2705 rtl_wol_enable_rx(tp); 2706 } 2707 } 2708 2709 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2710 { 2711 u32 val = TX_DMA_BURST << TxDMAShift | 2712 InterFrameGap << TxInterFrameGapShift; 2713 2714 if (rtl_is_8168evl_up(tp)) 2715 val |= TXCFG_AUTO_FIFO; 2716 2717 RTL_W32(tp, TxConfig, val); 2718 } 2719 2720 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2721 { 2722 /* Low hurts. Let's disable the filtering. */ 2723 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2724 } 2725 2726 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2727 { 2728 /* 2729 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2730 * register to be written before TxDescAddrLow to work. 2731 * Switching from MMIO to I/O access fixes the issue as well. 2732 */ 2733 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2734 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2735 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2736 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2737 } 2738 2739 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2740 { 2741 u32 val; 2742 2743 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2744 val = 0x000fff00; 2745 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2746 val = 0x00ffff00; 2747 else 2748 return; 2749 2750 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2751 val |= 0xff; 2752 2753 RTL_W32(tp, 0x7c, val); 2754 } 2755 2756 static void rtl_set_rx_mode(struct net_device *dev) 2757 { 2758 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2759 /* Multicast hash filter */ 2760 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2761 struct rtl8169_private *tp = netdev_priv(dev); 2762 u32 tmp; 2763 2764 if (dev->flags & IFF_PROMISC) { 2765 rx_mode |= AcceptAllPhys; 2766 } else if (!(dev->flags & IFF_MULTICAST)) { 2767 rx_mode &= ~AcceptMulticast; 2768 } else if (dev->flags & IFF_ALLMULTI || 2769 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2770 /* accept all multicasts */ 2771 } else if (netdev_mc_empty(dev)) { 2772 rx_mode &= ~AcceptMulticast; 2773 } else { 2774 struct netdev_hw_addr *ha; 2775 2776 mc_filter[1] = mc_filter[0] = 0; 2777 netdev_for_each_mc_addr(ha, dev) { 2778 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2779 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2780 } 2781 2782 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2783 tmp = mc_filter[0]; 2784 mc_filter[0] = swab32(mc_filter[1]); 2785 mc_filter[1] = swab32(tmp); 2786 } 2787 } 2788 2789 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2790 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2791 2792 tmp = RTL_R32(tp, RxConfig); 2793 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2794 } 2795 2796 DECLARE_RTL_COND(rtl_csiar_cond) 2797 { 2798 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2799 } 2800 2801 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2802 { 2803 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2804 2805 RTL_W32(tp, CSIDR, value); 2806 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2807 CSIAR_BYTE_ENABLE | func << 16); 2808 2809 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2810 } 2811 2812 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2813 { 2814 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2815 2816 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2817 CSIAR_BYTE_ENABLE); 2818 2819 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2820 RTL_R32(tp, CSIDR) : ~0; 2821 } 2822 2823 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2824 { 2825 struct pci_dev *pdev = tp->pci_dev; 2826 u32 csi; 2827 2828 /* According to Realtek the value at config space address 0x070f 2829 * controls the L0s/L1 entrance latency. We try standard ECAM access 2830 * first and if it fails fall back to CSI. 2831 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2832 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2833 */ 2834 if (pdev->cfg_size > 0x070f && 2835 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2836 return; 2837 2838 netdev_notice_once(tp->dev, 2839 "No native access to PCI extended config space, falling back to CSI\n"); 2840 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2841 rtl_csi_write(tp, 0x070c, csi | val << 24); 2842 } 2843 2844 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2845 { 2846 /* L0 7us, L1 16us */ 2847 rtl_set_aspm_entry_latency(tp, 0x27); 2848 } 2849 2850 struct ephy_info { 2851 unsigned int offset; 2852 u16 mask; 2853 u16 bits; 2854 }; 2855 2856 static void __rtl_ephy_init(struct rtl8169_private *tp, 2857 const struct ephy_info *e, int len) 2858 { 2859 u16 w; 2860 2861 while (len-- > 0) { 2862 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2863 rtl_ephy_write(tp, e->offset, w); 2864 e++; 2865 } 2866 } 2867 2868 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2869 2870 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2871 { 2872 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2873 PCI_EXP_LNKCTL_CLKREQ_EN); 2874 } 2875 2876 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2877 { 2878 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2879 PCI_EXP_LNKCTL_CLKREQ_EN); 2880 } 2881 2882 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2883 { 2884 /* work around an issue when PCI reset occurs during L2/L3 state */ 2885 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2886 } 2887 2888 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2889 { 2890 /* Bits control which events trigger ASPM L1 exit: 2891 * Bit 12: rxdv 2892 * Bit 11: ltr_msg 2893 * Bit 10: txdma_poll 2894 * Bit 9: xadm 2895 * Bit 8: pktavi 2896 * Bit 7: txpla 2897 */ 2898 switch (tp->mac_version) { 2899 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2900 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2901 break; 2902 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2903 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2904 break; 2905 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2906 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2907 break; 2908 default: 2909 break; 2910 } 2911 } 2912 2913 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2914 { 2915 switch (tp->mac_version) { 2916 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2917 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2918 break; 2919 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2920 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2921 break; 2922 default: 2923 break; 2924 } 2925 } 2926 2927 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2928 { 2929 u8 val8; 2930 2931 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2932 return; 2933 2934 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2935 if (enable && tp->aspm_manageable) { 2936 /* On these chip versions ASPM can even harm 2937 * bus communication of other PCI devices. 2938 */ 2939 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2940 tp->mac_version == RTL_GIGA_MAC_VER_43) 2941 return; 2942 2943 rtl_mod_config5(tp, 0, ASPM_en); 2944 switch (tp->mac_version) { 2945 case RTL_GIGA_MAC_VER_65: 2946 case RTL_GIGA_MAC_VER_66: 2947 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2948 RTL_W8(tp, INT_CFG0_8125, val8); 2949 break; 2950 default: 2951 rtl_mod_config2(tp, 0, ClkReqEn); 2952 break; 2953 } 2954 2955 switch (tp->mac_version) { 2956 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2957 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2958 /* reset ephy tx/rx disable timer */ 2959 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2960 /* chip can trigger L1.2 */ 2961 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2962 break; 2963 default: 2964 break; 2965 } 2966 } else { 2967 switch (tp->mac_version) { 2968 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2969 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2970 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2971 break; 2972 default: 2973 break; 2974 } 2975 2976 switch (tp->mac_version) { 2977 case RTL_GIGA_MAC_VER_65: 2978 case RTL_GIGA_MAC_VER_66: 2979 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2980 RTL_W8(tp, INT_CFG0_8125, val8); 2981 break; 2982 default: 2983 rtl_mod_config2(tp, ClkReqEn, 0); 2984 break; 2985 } 2986 rtl_mod_config5(tp, ASPM_en, 0); 2987 } 2988 } 2989 2990 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2991 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2992 { 2993 /* Usage of dynamic vs. static FIFO is controlled by bit 2994 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2995 */ 2996 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2997 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2998 } 2999 3000 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3001 u8 low, u8 high) 3002 { 3003 /* FIFO thresholds for pause flow control */ 3004 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3005 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3006 } 3007 3008 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3009 { 3010 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3011 } 3012 3013 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3014 { 3015 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3016 3017 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3018 3019 rtl_disable_clock_request(tp); 3020 } 3021 3022 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3023 { 3024 static const struct ephy_info e_info_8168cp[] = { 3025 { 0x01, 0, 0x0001 }, 3026 { 0x02, 0x0800, 0x1000 }, 3027 { 0x03, 0, 0x0042 }, 3028 { 0x06, 0x0080, 0x0000 }, 3029 { 0x07, 0, 0x2000 } 3030 }; 3031 3032 rtl_set_def_aspm_entry_latency(tp); 3033 3034 rtl_ephy_init(tp, e_info_8168cp); 3035 3036 __rtl_hw_start_8168cp(tp); 3037 } 3038 3039 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3040 { 3041 rtl_set_def_aspm_entry_latency(tp); 3042 3043 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3044 } 3045 3046 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3047 { 3048 rtl_set_def_aspm_entry_latency(tp); 3049 3050 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3051 3052 /* Magic. */ 3053 RTL_W8(tp, DBG_REG, 0x20); 3054 } 3055 3056 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3057 { 3058 static const struct ephy_info e_info_8168c_1[] = { 3059 { 0x02, 0x0800, 0x1000 }, 3060 { 0x03, 0, 0x0002 }, 3061 { 0x06, 0x0080, 0x0000 } 3062 }; 3063 3064 rtl_set_def_aspm_entry_latency(tp); 3065 3066 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3067 3068 rtl_ephy_init(tp, e_info_8168c_1); 3069 3070 __rtl_hw_start_8168cp(tp); 3071 } 3072 3073 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3074 { 3075 static const struct ephy_info e_info_8168c_2[] = { 3076 { 0x01, 0, 0x0001 }, 3077 { 0x03, 0x0400, 0x0020 } 3078 }; 3079 3080 rtl_set_def_aspm_entry_latency(tp); 3081 3082 rtl_ephy_init(tp, e_info_8168c_2); 3083 3084 __rtl_hw_start_8168cp(tp); 3085 } 3086 3087 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3088 { 3089 rtl_set_def_aspm_entry_latency(tp); 3090 3091 __rtl_hw_start_8168cp(tp); 3092 } 3093 3094 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3095 { 3096 rtl_set_def_aspm_entry_latency(tp); 3097 3098 rtl_disable_clock_request(tp); 3099 } 3100 3101 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3102 { 3103 static const struct ephy_info e_info_8168d_4[] = { 3104 { 0x0b, 0x0000, 0x0048 }, 3105 { 0x19, 0x0020, 0x0050 }, 3106 { 0x0c, 0x0100, 0x0020 }, 3107 { 0x10, 0x0004, 0x0000 }, 3108 }; 3109 3110 rtl_set_def_aspm_entry_latency(tp); 3111 3112 rtl_ephy_init(tp, e_info_8168d_4); 3113 3114 rtl_enable_clock_request(tp); 3115 } 3116 3117 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3118 { 3119 static const struct ephy_info e_info_8168e_1[] = { 3120 { 0x00, 0x0200, 0x0100 }, 3121 { 0x00, 0x0000, 0x0004 }, 3122 { 0x06, 0x0002, 0x0001 }, 3123 { 0x06, 0x0000, 0x0030 }, 3124 { 0x07, 0x0000, 0x2000 }, 3125 { 0x00, 0x0000, 0x0020 }, 3126 { 0x03, 0x5800, 0x2000 }, 3127 { 0x03, 0x0000, 0x0001 }, 3128 { 0x01, 0x0800, 0x1000 }, 3129 { 0x07, 0x0000, 0x4000 }, 3130 { 0x1e, 0x0000, 0x2000 }, 3131 { 0x19, 0xffff, 0xfe6c }, 3132 { 0x0a, 0x0000, 0x0040 } 3133 }; 3134 3135 rtl_set_def_aspm_entry_latency(tp); 3136 3137 rtl_ephy_init(tp, e_info_8168e_1); 3138 3139 rtl_disable_clock_request(tp); 3140 3141 /* Reset tx FIFO pointer */ 3142 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3143 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3144 3145 rtl_mod_config5(tp, Spi_en, 0); 3146 } 3147 3148 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3149 { 3150 static const struct ephy_info e_info_8168e_2[] = { 3151 { 0x09, 0x0000, 0x0080 }, 3152 { 0x19, 0x0000, 0x0224 }, 3153 { 0x00, 0x0000, 0x0004 }, 3154 { 0x0c, 0x3df0, 0x0200 }, 3155 }; 3156 3157 rtl_set_def_aspm_entry_latency(tp); 3158 3159 rtl_ephy_init(tp, e_info_8168e_2); 3160 3161 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3162 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3163 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3164 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3165 rtl_reset_packet_filter(tp); 3166 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3167 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3168 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3169 3170 rtl_disable_clock_request(tp); 3171 3172 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3173 3174 rtl8168_config_eee_mac(tp); 3175 3176 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3177 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3178 rtl_mod_config5(tp, Spi_en, 0); 3179 } 3180 3181 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3182 { 3183 rtl_set_def_aspm_entry_latency(tp); 3184 3185 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3186 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3187 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3188 rtl_reset_packet_filter(tp); 3189 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3190 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3191 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3192 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3193 3194 rtl_disable_clock_request(tp); 3195 3196 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3197 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3198 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3199 rtl_mod_config5(tp, Spi_en, 0); 3200 3201 rtl8168_config_eee_mac(tp); 3202 } 3203 3204 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3205 { 3206 static const struct ephy_info e_info_8168f_1[] = { 3207 { 0x06, 0x00c0, 0x0020 }, 3208 { 0x08, 0x0001, 0x0002 }, 3209 { 0x09, 0x0000, 0x0080 }, 3210 { 0x19, 0x0000, 0x0224 }, 3211 { 0x00, 0x0000, 0x0008 }, 3212 { 0x0c, 0x3df0, 0x0200 }, 3213 }; 3214 3215 rtl_hw_start_8168f(tp); 3216 3217 rtl_ephy_init(tp, e_info_8168f_1); 3218 } 3219 3220 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3221 { 3222 static const struct ephy_info e_info_8168f_1[] = { 3223 { 0x06, 0x00c0, 0x0020 }, 3224 { 0x0f, 0xffff, 0x5200 }, 3225 { 0x19, 0x0000, 0x0224 }, 3226 { 0x00, 0x0000, 0x0008 }, 3227 { 0x0c, 0x3df0, 0x0200 }, 3228 }; 3229 3230 rtl_hw_start_8168f(tp); 3231 rtl_pcie_state_l2l3_disable(tp); 3232 3233 rtl_ephy_init(tp, e_info_8168f_1); 3234 } 3235 3236 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3237 { 3238 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3239 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3240 3241 rtl_set_def_aspm_entry_latency(tp); 3242 3243 rtl_reset_packet_filter(tp); 3244 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3245 3246 rtl_disable_rxdvgate(tp); 3247 3248 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3249 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3250 3251 rtl8168_config_eee_mac(tp); 3252 3253 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3254 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3255 3256 rtl_pcie_state_l2l3_disable(tp); 3257 } 3258 3259 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3260 { 3261 static const struct ephy_info e_info_8168g_1[] = { 3262 { 0x00, 0x0008, 0x0000 }, 3263 { 0x0c, 0x3ff0, 0x0820 }, 3264 { 0x1e, 0x0000, 0x0001 }, 3265 { 0x19, 0x8000, 0x0000 } 3266 }; 3267 3268 rtl_hw_start_8168g(tp); 3269 rtl_ephy_init(tp, e_info_8168g_1); 3270 } 3271 3272 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3273 { 3274 static const struct ephy_info e_info_8168g_2[] = { 3275 { 0x00, 0x0008, 0x0000 }, 3276 { 0x0c, 0x3ff0, 0x0820 }, 3277 { 0x19, 0xffff, 0x7c00 }, 3278 { 0x1e, 0xffff, 0x20eb }, 3279 { 0x0d, 0xffff, 0x1666 }, 3280 { 0x00, 0xffff, 0x10a3 }, 3281 { 0x06, 0xffff, 0xf050 }, 3282 { 0x04, 0x0000, 0x0010 }, 3283 { 0x1d, 0x4000, 0x0000 }, 3284 }; 3285 3286 rtl_hw_start_8168g(tp); 3287 rtl_ephy_init(tp, e_info_8168g_2); 3288 } 3289 3290 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3291 { 3292 static const u16 fix_data[] = { 3293 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3294 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3295 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3296 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3297 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3298 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3299 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3300 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3301 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3302 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3303 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3304 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3305 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3306 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3307 }; 3308 unsigned long flags; 3309 int i; 3310 3311 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3312 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3313 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3314 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3315 } 3316 3317 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3318 { 3319 static const struct ephy_info e_info_8411_2[] = { 3320 { 0x00, 0x0008, 0x0000 }, 3321 { 0x0c, 0x37d0, 0x0820 }, 3322 { 0x1e, 0x0000, 0x0001 }, 3323 { 0x19, 0x8021, 0x0000 }, 3324 { 0x1e, 0x0000, 0x2000 }, 3325 { 0x0d, 0x0100, 0x0200 }, 3326 { 0x00, 0x0000, 0x0080 }, 3327 { 0x06, 0x0000, 0x0010 }, 3328 { 0x04, 0x0000, 0x0010 }, 3329 { 0x1d, 0x0000, 0x4000 }, 3330 }; 3331 3332 rtl_hw_start_8168g(tp); 3333 3334 rtl_ephy_init(tp, e_info_8411_2); 3335 3336 /* The following Realtek-provided magic fixes an issue with the RX unit 3337 * getting confused after the PHY having been powered-down. 3338 */ 3339 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3340 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3341 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3342 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3343 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3344 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3345 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3346 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3347 mdelay(3); 3348 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3349 3350 rtl8411b_fix_phy_down(tp); 3351 3352 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3353 3354 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3355 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3356 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3357 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3358 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3359 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3360 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3361 } 3362 3363 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3364 { 3365 static const struct ephy_info e_info_8168h_1[] = { 3366 { 0x1e, 0x0800, 0x0001 }, 3367 { 0x1d, 0x0000, 0x0800 }, 3368 { 0x05, 0xffff, 0x2089 }, 3369 { 0x06, 0xffff, 0x5881 }, 3370 { 0x04, 0xffff, 0x854a }, 3371 { 0x01, 0xffff, 0x068b } 3372 }; 3373 int rg_saw_cnt; 3374 3375 rtl_ephy_init(tp, e_info_8168h_1); 3376 3377 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3378 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3379 3380 rtl_set_def_aspm_entry_latency(tp); 3381 3382 rtl_reset_packet_filter(tp); 3383 3384 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3385 3386 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3387 3388 rtl_disable_rxdvgate(tp); 3389 3390 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3391 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3392 3393 rtl8168_config_eee_mac(tp); 3394 3395 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3396 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3397 3398 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3399 3400 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3401 3402 rtl_pcie_state_l2l3_disable(tp); 3403 3404 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3405 if (rg_saw_cnt > 0) { 3406 u16 sw_cnt_1ms_ini; 3407 3408 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3409 sw_cnt_1ms_ini &= 0x0fff; 3410 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3411 } 3412 3413 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3414 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3415 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3416 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3417 3418 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3419 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3420 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3421 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3422 } 3423 3424 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3425 { 3426 rtl8168ep_stop_cmac(tp); 3427 3428 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3429 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3430 3431 rtl_set_def_aspm_entry_latency(tp); 3432 3433 rtl_reset_packet_filter(tp); 3434 3435 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3436 3437 rtl_disable_rxdvgate(tp); 3438 3439 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3440 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3441 3442 rtl8168_config_eee_mac(tp); 3443 3444 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3445 3446 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3447 3448 rtl_pcie_state_l2l3_disable(tp); 3449 } 3450 3451 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3452 { 3453 static const struct ephy_info e_info_8168ep_3[] = { 3454 { 0x00, 0x0000, 0x0080 }, 3455 { 0x0d, 0x0100, 0x0200 }, 3456 { 0x19, 0x8021, 0x0000 }, 3457 { 0x1e, 0x0000, 0x2000 }, 3458 }; 3459 3460 rtl_ephy_init(tp, e_info_8168ep_3); 3461 3462 rtl_hw_start_8168ep(tp); 3463 3464 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3465 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3466 3467 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3468 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3469 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3470 } 3471 3472 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3473 { 3474 static const struct ephy_info e_info_8117[] = { 3475 { 0x19, 0x0040, 0x1100 }, 3476 { 0x59, 0x0040, 0x1100 }, 3477 }; 3478 int rg_saw_cnt; 3479 3480 rtl8168ep_stop_cmac(tp); 3481 rtl_ephy_init(tp, e_info_8117); 3482 3483 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3484 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3485 3486 rtl_set_def_aspm_entry_latency(tp); 3487 3488 rtl_reset_packet_filter(tp); 3489 3490 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3491 3492 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3493 3494 rtl_disable_rxdvgate(tp); 3495 3496 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3497 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3498 3499 rtl8168_config_eee_mac(tp); 3500 3501 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3502 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3503 3504 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3505 3506 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3507 3508 rtl_pcie_state_l2l3_disable(tp); 3509 3510 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3511 if (rg_saw_cnt > 0) { 3512 u16 sw_cnt_1ms_ini; 3513 3514 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3515 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3516 } 3517 3518 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3519 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3520 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3521 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3522 3523 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3524 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3525 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3526 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3527 3528 /* firmware is for MAC only */ 3529 r8169_apply_firmware(tp); 3530 } 3531 3532 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3533 { 3534 static const struct ephy_info e_info_8102e_1[] = { 3535 { 0x01, 0, 0x6e65 }, 3536 { 0x02, 0, 0x091f }, 3537 { 0x03, 0, 0xc2f9 }, 3538 { 0x06, 0, 0xafb5 }, 3539 { 0x07, 0, 0x0e00 }, 3540 { 0x19, 0, 0xec80 }, 3541 { 0x01, 0, 0x2e65 }, 3542 { 0x01, 0, 0x6e65 } 3543 }; 3544 u8 cfg1; 3545 3546 rtl_set_def_aspm_entry_latency(tp); 3547 3548 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3549 3550 RTL_W8(tp, Config1, 3551 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3552 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3553 3554 cfg1 = RTL_R8(tp, Config1); 3555 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3556 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3557 3558 rtl_ephy_init(tp, e_info_8102e_1); 3559 } 3560 3561 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3562 { 3563 rtl_set_def_aspm_entry_latency(tp); 3564 3565 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3566 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3567 } 3568 3569 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3570 { 3571 rtl_hw_start_8102e_2(tp); 3572 3573 rtl_ephy_write(tp, 0x03, 0xc2f9); 3574 } 3575 3576 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3577 { 3578 static const struct ephy_info e_info_8401[] = { 3579 { 0x01, 0xffff, 0x6fe5 }, 3580 { 0x03, 0xffff, 0x0599 }, 3581 { 0x06, 0xffff, 0xaf25 }, 3582 { 0x07, 0xffff, 0x8e68 }, 3583 }; 3584 3585 rtl_ephy_init(tp, e_info_8401); 3586 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3587 } 3588 3589 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3590 { 3591 static const struct ephy_info e_info_8105e_1[] = { 3592 { 0x07, 0, 0x4000 }, 3593 { 0x19, 0, 0x0200 }, 3594 { 0x19, 0, 0x0020 }, 3595 { 0x1e, 0, 0x2000 }, 3596 { 0x03, 0, 0x0001 }, 3597 { 0x19, 0, 0x0100 }, 3598 { 0x19, 0, 0x0004 }, 3599 { 0x0a, 0, 0x0020 } 3600 }; 3601 3602 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3603 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3604 3605 /* Disable Early Tally Counter */ 3606 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3607 3608 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3609 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3610 3611 rtl_ephy_init(tp, e_info_8105e_1); 3612 3613 rtl_pcie_state_l2l3_disable(tp); 3614 } 3615 3616 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3617 { 3618 rtl_hw_start_8105e_1(tp); 3619 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3620 } 3621 3622 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3623 { 3624 static const struct ephy_info e_info_8402[] = { 3625 { 0x19, 0xffff, 0xff64 }, 3626 { 0x1e, 0, 0x4000 } 3627 }; 3628 3629 rtl_set_def_aspm_entry_latency(tp); 3630 3631 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3632 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3633 3634 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3635 3636 rtl_ephy_init(tp, e_info_8402); 3637 3638 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3639 rtl_reset_packet_filter(tp); 3640 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3641 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3642 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3643 3644 /* disable EEE */ 3645 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3646 3647 rtl_pcie_state_l2l3_disable(tp); 3648 } 3649 3650 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3651 { 3652 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3653 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3654 3655 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3656 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3657 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3658 3659 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3660 rtl_set_aspm_entry_latency(tp, 0x2f); 3661 3662 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3663 3664 /* disable EEE */ 3665 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3666 3667 rtl_pcie_state_l2l3_disable(tp); 3668 } 3669 3670 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3671 { 3672 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3673 } 3674 3675 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3676 { 3677 rtl_pcie_state_l2l3_disable(tp); 3678 3679 RTL_W16(tp, 0x382, 0x221b); 3680 RTL_W32(tp, RSS_CTRL_8125, 0); 3681 RTL_W16(tp, Q_NUM_CTRL_8125, 0); 3682 3683 /* disable UPS */ 3684 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3685 3686 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3687 3688 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3689 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3690 3691 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3692 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3693 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3694 3695 /* disable new tx descriptor format */ 3696 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3697 3698 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3699 tp->mac_version == RTL_GIGA_MAC_VER_66) 3700 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3701 3702 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3703 tp->mac_version == RTL_GIGA_MAC_VER_66) 3704 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3705 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3706 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3707 else 3708 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3709 3710 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3711 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3712 else 3713 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3714 3715 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3716 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3717 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3718 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3719 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3720 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3721 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3722 tp->mac_version == RTL_GIGA_MAC_VER_66) 3723 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3724 else 3725 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3726 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3727 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3728 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3729 3730 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3731 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3732 udelay(1); 3733 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3734 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3735 3736 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3737 3738 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3739 3740 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3741 rtl8125a_config_eee_mac(tp); 3742 else 3743 rtl8125b_config_eee_mac(tp); 3744 3745 rtl_disable_rxdvgate(tp); 3746 } 3747 3748 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3749 { 3750 static const struct ephy_info e_info_8125a_2[] = { 3751 { 0x04, 0xffff, 0xd000 }, 3752 { 0x0a, 0xffff, 0x8653 }, 3753 { 0x23, 0xffff, 0xab66 }, 3754 { 0x20, 0xffff, 0x9455 }, 3755 { 0x21, 0xffff, 0x99ff }, 3756 { 0x29, 0xffff, 0xfe04 }, 3757 3758 { 0x44, 0xffff, 0xd000 }, 3759 { 0x4a, 0xffff, 0x8653 }, 3760 { 0x63, 0xffff, 0xab66 }, 3761 { 0x60, 0xffff, 0x9455 }, 3762 { 0x61, 0xffff, 0x99ff }, 3763 { 0x69, 0xffff, 0xfe04 }, 3764 }; 3765 3766 rtl_set_def_aspm_entry_latency(tp); 3767 rtl_ephy_init(tp, e_info_8125a_2); 3768 rtl_hw_start_8125_common(tp); 3769 } 3770 3771 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3772 { 3773 static const struct ephy_info e_info_8125b[] = { 3774 { 0x0b, 0xffff, 0xa908 }, 3775 { 0x1e, 0xffff, 0x20eb }, 3776 { 0x4b, 0xffff, 0xa908 }, 3777 { 0x5e, 0xffff, 0x20eb }, 3778 { 0x22, 0x0030, 0x0020 }, 3779 { 0x62, 0x0030, 0x0020 }, 3780 }; 3781 3782 rtl_set_def_aspm_entry_latency(tp); 3783 rtl_ephy_init(tp, e_info_8125b); 3784 rtl_hw_start_8125_common(tp); 3785 } 3786 3787 static void rtl_hw_start_8125d(struct rtl8169_private *tp) 3788 { 3789 rtl_set_def_aspm_entry_latency(tp); 3790 rtl_hw_start_8125_common(tp); 3791 } 3792 3793 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3794 { 3795 rtl_set_def_aspm_entry_latency(tp); 3796 rtl_hw_start_8125_common(tp); 3797 } 3798 3799 static void rtl_hw_config(struct rtl8169_private *tp) 3800 { 3801 static const rtl_generic_fct hw_configs[] = { 3802 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3803 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3804 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3805 [RTL_GIGA_MAC_VER_10] = NULL, 3806 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3807 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3808 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3809 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3810 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3811 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3812 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3813 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3814 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3815 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3816 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3817 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3818 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3819 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3820 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3821 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3822 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3823 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3824 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3825 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3826 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3827 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3828 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3829 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3830 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3831 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3832 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3833 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3834 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3835 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3836 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3837 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3838 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3839 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3840 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3841 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, 3842 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3843 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a, 3844 }; 3845 3846 if (hw_configs[tp->mac_version]) 3847 hw_configs[tp->mac_version](tp); 3848 } 3849 3850 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3851 { 3852 int i; 3853 3854 RTL_W8(tp, INT_CFG0_8125, 0x00); 3855 3856 /* disable interrupt coalescing */ 3857 switch (tp->mac_version) { 3858 case RTL_GIGA_MAC_VER_61: 3859 case RTL_GIGA_MAC_VER_64: 3860 for (i = 0xa00; i < 0xb00; i += 4) 3861 RTL_W32(tp, i, 0); 3862 break; 3863 case RTL_GIGA_MAC_VER_63: 3864 case RTL_GIGA_MAC_VER_65: 3865 case RTL_GIGA_MAC_VER_66: 3866 for (i = 0xa00; i < 0xa80; i += 4) 3867 RTL_W32(tp, i, 0); 3868 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3869 break; 3870 default: 3871 break; 3872 } 3873 3874 /* enable extended tally counter */ 3875 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); 3876 3877 rtl_hw_config(tp); 3878 } 3879 3880 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3881 { 3882 if (rtl_is_8168evl_up(tp)) 3883 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3884 else 3885 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3886 3887 rtl_hw_config(tp); 3888 3889 /* disable interrupt coalescing */ 3890 RTL_W16(tp, IntrMitigate, 0x0000); 3891 } 3892 3893 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3894 { 3895 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3896 3897 tp->cp_cmd |= PCIMulRW; 3898 3899 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3900 tp->mac_version == RTL_GIGA_MAC_VER_03) 3901 tp->cp_cmd |= EnAnaPLL; 3902 3903 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3904 3905 rtl8169_set_magic_reg(tp); 3906 3907 /* disable interrupt coalescing */ 3908 RTL_W16(tp, IntrMitigate, 0x0000); 3909 } 3910 3911 static void rtl_hw_start(struct rtl8169_private *tp) 3912 { 3913 rtl_unlock_config_regs(tp); 3914 /* disable aspm and clock request before ephy access */ 3915 rtl_hw_aspm_clkreq_enable(tp, false); 3916 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3917 3918 rtl_set_eee_txidle_timer(tp); 3919 3920 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3921 rtl_hw_start_8169(tp); 3922 else if (rtl_is_8125(tp)) 3923 rtl_hw_start_8125(tp); 3924 else 3925 rtl_hw_start_8168(tp); 3926 3927 rtl_enable_exit_l1(tp); 3928 rtl_hw_aspm_clkreq_enable(tp, true); 3929 rtl_set_rx_max_size(tp); 3930 rtl_set_rx_tx_desc_registers(tp); 3931 rtl_lock_config_regs(tp); 3932 3933 rtl_jumbo_config(tp); 3934 3935 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3936 rtl_pci_commit(tp); 3937 3938 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3939 rtl_init_rxcfg(tp); 3940 rtl_set_tx_config_registers(tp); 3941 rtl_set_rx_config_features(tp, tp->dev->features); 3942 rtl_set_rx_mode(tp->dev); 3943 rtl_irq_enable(tp); 3944 } 3945 3946 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3947 { 3948 struct rtl8169_private *tp = netdev_priv(dev); 3949 3950 WRITE_ONCE(dev->mtu, new_mtu); 3951 netdev_update_features(dev); 3952 rtl_jumbo_config(tp); 3953 rtl_set_eee_txidle_timer(tp); 3954 3955 return 0; 3956 } 3957 3958 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3959 { 3960 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3961 3962 desc->opts2 = 0; 3963 /* Force memory writes to complete before releasing descriptor */ 3964 dma_wmb(); 3965 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3966 } 3967 3968 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3969 struct RxDesc *desc) 3970 { 3971 struct device *d = tp_to_dev(tp); 3972 int node = dev_to_node(d); 3973 dma_addr_t mapping; 3974 struct page *data; 3975 3976 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3977 if (!data) 3978 return NULL; 3979 3980 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3981 if (unlikely(dma_mapping_error(d, mapping))) { 3982 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3983 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3984 return NULL; 3985 } 3986 3987 desc->addr = cpu_to_le64(mapping); 3988 rtl8169_mark_to_asic(desc); 3989 3990 return data; 3991 } 3992 3993 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3994 { 3995 int i; 3996 3997 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3998 dma_unmap_page(tp_to_dev(tp), 3999 le64_to_cpu(tp->RxDescArray[i].addr), 4000 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4001 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4002 tp->Rx_databuff[i] = NULL; 4003 tp->RxDescArray[i].addr = 0; 4004 tp->RxDescArray[i].opts1 = 0; 4005 } 4006 } 4007 4008 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4009 { 4010 int i; 4011 4012 for (i = 0; i < NUM_RX_DESC; i++) { 4013 struct page *data; 4014 4015 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4016 if (!data) { 4017 rtl8169_rx_clear(tp); 4018 return -ENOMEM; 4019 } 4020 tp->Rx_databuff[i] = data; 4021 } 4022 4023 /* mark as last descriptor in the ring */ 4024 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4025 4026 return 0; 4027 } 4028 4029 static int rtl8169_init_ring(struct rtl8169_private *tp) 4030 { 4031 rtl8169_init_ring_indexes(tp); 4032 4033 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4034 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4035 4036 return rtl8169_rx_fill(tp); 4037 } 4038 4039 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4040 { 4041 struct ring_info *tx_skb = tp->tx_skb + entry; 4042 struct TxDesc *desc = tp->TxDescArray + entry; 4043 4044 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4045 DMA_TO_DEVICE); 4046 memset(desc, 0, sizeof(*desc)); 4047 memset(tx_skb, 0, sizeof(*tx_skb)); 4048 } 4049 4050 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4051 unsigned int n) 4052 { 4053 unsigned int i; 4054 4055 for (i = 0; i < n; i++) { 4056 unsigned int entry = (start + i) % NUM_TX_DESC; 4057 struct ring_info *tx_skb = tp->tx_skb + entry; 4058 unsigned int len = tx_skb->len; 4059 4060 if (len) { 4061 struct sk_buff *skb = tx_skb->skb; 4062 4063 rtl8169_unmap_tx_skb(tp, entry); 4064 if (skb) 4065 dev_consume_skb_any(skb); 4066 } 4067 } 4068 } 4069 4070 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4071 { 4072 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4073 netdev_reset_queue(tp->dev); 4074 } 4075 4076 static void rtl8169_cleanup(struct rtl8169_private *tp) 4077 { 4078 napi_disable(&tp->napi); 4079 4080 /* Give a racing hard_start_xmit a few cycles to complete. */ 4081 synchronize_net(); 4082 4083 /* Disable interrupts */ 4084 rtl8169_irq_mask_and_ack(tp); 4085 4086 rtl_rx_close(tp); 4087 4088 switch (tp->mac_version) { 4089 case RTL_GIGA_MAC_VER_28: 4090 case RTL_GIGA_MAC_VER_31: 4091 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4092 break; 4093 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4094 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4095 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4096 break; 4097 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 4098 rtl_enable_rxdvgate(tp); 4099 fsleep(2000); 4100 break; 4101 default: 4102 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4103 fsleep(100); 4104 break; 4105 } 4106 4107 rtl_hw_reset(tp); 4108 4109 rtl8169_tx_clear(tp); 4110 rtl8169_init_ring_indexes(tp); 4111 } 4112 4113 static void rtl_reset_work(struct rtl8169_private *tp) 4114 { 4115 int i; 4116 4117 netif_stop_queue(tp->dev); 4118 4119 rtl8169_cleanup(tp); 4120 4121 for (i = 0; i < NUM_RX_DESC; i++) 4122 rtl8169_mark_to_asic(tp->RxDescArray + i); 4123 4124 napi_enable(&tp->napi); 4125 rtl_hw_start(tp); 4126 } 4127 4128 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4129 { 4130 struct rtl8169_private *tp = netdev_priv(dev); 4131 4132 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4133 } 4134 4135 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4136 void *addr, unsigned int entry, bool desc_own) 4137 { 4138 struct TxDesc *txd = tp->TxDescArray + entry; 4139 struct device *d = tp_to_dev(tp); 4140 dma_addr_t mapping; 4141 u32 opts1; 4142 int ret; 4143 4144 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4145 ret = dma_mapping_error(d, mapping); 4146 if (unlikely(ret)) { 4147 if (net_ratelimit()) 4148 netdev_err(tp->dev, "Failed to map TX data!\n"); 4149 return ret; 4150 } 4151 4152 txd->addr = cpu_to_le64(mapping); 4153 txd->opts2 = cpu_to_le32(opts[1]); 4154 4155 opts1 = opts[0] | len; 4156 if (entry == NUM_TX_DESC - 1) 4157 opts1 |= RingEnd; 4158 if (desc_own) 4159 opts1 |= DescOwn; 4160 txd->opts1 = cpu_to_le32(opts1); 4161 4162 tp->tx_skb[entry].len = len; 4163 4164 return 0; 4165 } 4166 4167 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4168 const u32 *opts, unsigned int entry) 4169 { 4170 struct skb_shared_info *info = skb_shinfo(skb); 4171 unsigned int cur_frag; 4172 4173 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4174 const skb_frag_t *frag = info->frags + cur_frag; 4175 void *addr = skb_frag_address(frag); 4176 u32 len = skb_frag_size(frag); 4177 4178 entry = (entry + 1) % NUM_TX_DESC; 4179 4180 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4181 goto err_out; 4182 } 4183 4184 return 0; 4185 4186 err_out: 4187 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4188 return -EIO; 4189 } 4190 4191 static bool rtl_skb_is_udp(struct sk_buff *skb) 4192 { 4193 int no = skb_network_offset(skb); 4194 struct ipv6hdr *i6h, _i6h; 4195 struct iphdr *ih, _ih; 4196 4197 switch (vlan_get_protocol(skb)) { 4198 case htons(ETH_P_IP): 4199 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4200 return ih && ih->protocol == IPPROTO_UDP; 4201 case htons(ETH_P_IPV6): 4202 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4203 return i6h && i6h->nexthdr == IPPROTO_UDP; 4204 default: 4205 return false; 4206 } 4207 } 4208 4209 #define RTL_MIN_PATCH_LEN 47 4210 4211 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4212 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4213 struct sk_buff *skb) 4214 { 4215 unsigned int padto = 0, len = skb->len; 4216 4217 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) && 4218 skb_transport_header_was_set(skb)) { 4219 unsigned int trans_data_len = skb_tail_pointer(skb) - 4220 skb_transport_header(skb); 4221 4222 if (trans_data_len >= offsetof(struct udphdr, len) && 4223 trans_data_len < RTL_MIN_PATCH_LEN) { 4224 u16 dest = ntohs(udp_hdr(skb)->dest); 4225 4226 /* dest is a standard PTP port */ 4227 if (dest == 319 || dest == 320) 4228 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4229 } 4230 4231 if (trans_data_len < sizeof(struct udphdr)) 4232 padto = max_t(unsigned int, padto, 4233 len + sizeof(struct udphdr) - trans_data_len); 4234 } 4235 4236 return padto; 4237 } 4238 4239 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4240 struct sk_buff *skb) 4241 { 4242 unsigned int padto = 0; 4243 4244 switch (tp->mac_version) { 4245 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 4246 padto = rtl8125_quirk_udp_padto(tp, skb); 4247 break; 4248 default: 4249 break; 4250 } 4251 4252 switch (tp->mac_version) { 4253 case RTL_GIGA_MAC_VER_34: 4254 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 4255 padto = max_t(unsigned int, padto, ETH_ZLEN); 4256 break; 4257 default: 4258 break; 4259 } 4260 4261 return padto; 4262 } 4263 4264 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4265 { 4266 u32 mss = skb_shinfo(skb)->gso_size; 4267 4268 if (mss) { 4269 opts[0] |= TD_LSO; 4270 opts[0] |= mss << TD0_MSS_SHIFT; 4271 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4272 const struct iphdr *ip = ip_hdr(skb); 4273 4274 if (ip->protocol == IPPROTO_TCP) 4275 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4276 else if (ip->protocol == IPPROTO_UDP) 4277 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4278 else 4279 WARN_ON_ONCE(1); 4280 } 4281 } 4282 4283 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4284 struct sk_buff *skb, u32 *opts) 4285 { 4286 struct skb_shared_info *shinfo = skb_shinfo(skb); 4287 u32 mss = shinfo->gso_size; 4288 4289 if (mss) { 4290 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4291 opts[0] |= TD1_GTSENV4; 4292 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4293 if (skb_cow_head(skb, 0)) 4294 return false; 4295 4296 tcp_v6_gso_csum_prep(skb); 4297 opts[0] |= TD1_GTSENV6; 4298 } else { 4299 WARN_ON_ONCE(1); 4300 } 4301 4302 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4303 opts[1] |= mss << TD1_MSS_SHIFT; 4304 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4305 u8 ip_protocol; 4306 4307 switch (vlan_get_protocol(skb)) { 4308 case htons(ETH_P_IP): 4309 opts[1] |= TD1_IPv4_CS; 4310 ip_protocol = ip_hdr(skb)->protocol; 4311 break; 4312 4313 case htons(ETH_P_IPV6): 4314 opts[1] |= TD1_IPv6_CS; 4315 ip_protocol = ipv6_hdr(skb)->nexthdr; 4316 break; 4317 4318 default: 4319 ip_protocol = IPPROTO_RAW; 4320 break; 4321 } 4322 4323 if (ip_protocol == IPPROTO_TCP) 4324 opts[1] |= TD1_TCP_CS; 4325 else if (ip_protocol == IPPROTO_UDP) 4326 opts[1] |= TD1_UDP_CS; 4327 else 4328 WARN_ON_ONCE(1); 4329 4330 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4331 } else { 4332 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4333 4334 /* skb_padto would free the skb on error */ 4335 return !__skb_put_padto(skb, padto, false); 4336 } 4337 4338 return true; 4339 } 4340 4341 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4342 { 4343 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4344 } 4345 4346 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4347 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4348 { 4349 switch (tp->mac_version) { 4350 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4351 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4352 return false; 4353 default: 4354 return true; 4355 } 4356 } 4357 4358 static void rtl8169_doorbell(struct rtl8169_private *tp) 4359 { 4360 if (rtl_is_8125(tp)) 4361 RTL_W16(tp, TxPoll_8125, BIT(0)); 4362 else 4363 RTL_W8(tp, TxPoll, NPQ); 4364 } 4365 4366 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4367 struct net_device *dev) 4368 { 4369 struct rtl8169_private *tp = netdev_priv(dev); 4370 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4371 struct TxDesc *txd_first, *txd_last; 4372 bool stop_queue, door_bell; 4373 unsigned int frags; 4374 u32 opts[2]; 4375 4376 if (unlikely(!rtl_tx_slots_avail(tp))) { 4377 if (net_ratelimit()) 4378 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4379 netif_stop_queue(dev); 4380 return NETDEV_TX_BUSY; 4381 } 4382 4383 opts[1] = rtl8169_tx_vlan_tag(skb); 4384 opts[0] = 0; 4385 4386 if (!rtl_chip_supports_csum_v2(tp)) 4387 rtl8169_tso_csum_v1(skb, opts); 4388 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4389 goto err_dma_0; 4390 4391 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4392 entry, false))) 4393 goto err_dma_0; 4394 4395 txd_first = tp->TxDescArray + entry; 4396 4397 frags = skb_shinfo(skb)->nr_frags; 4398 if (frags) { 4399 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4400 goto err_dma_1; 4401 entry = (entry + frags) % NUM_TX_DESC; 4402 } 4403 4404 txd_last = tp->TxDescArray + entry; 4405 txd_last->opts1 |= cpu_to_le32(LastFrag); 4406 tp->tx_skb[entry].skb = skb; 4407 4408 skb_tx_timestamp(skb); 4409 4410 /* Force memory writes to complete before releasing descriptor */ 4411 dma_wmb(); 4412 4413 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4414 4415 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4416 4417 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4418 smp_wmb(); 4419 4420 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4421 4422 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4423 R8169_TX_STOP_THRS, 4424 R8169_TX_START_THRS); 4425 if (door_bell || stop_queue) 4426 rtl8169_doorbell(tp); 4427 4428 return NETDEV_TX_OK; 4429 4430 err_dma_1: 4431 rtl8169_unmap_tx_skb(tp, entry); 4432 err_dma_0: 4433 dev_kfree_skb_any(skb); 4434 dev->stats.tx_dropped++; 4435 return NETDEV_TX_OK; 4436 } 4437 4438 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4439 { 4440 struct skb_shared_info *info = skb_shinfo(skb); 4441 unsigned int nr_frags = info->nr_frags; 4442 4443 if (!nr_frags) 4444 return UINT_MAX; 4445 4446 return skb_frag_size(info->frags + nr_frags - 1); 4447 } 4448 4449 /* Workaround for hw issues with TSO on RTL8168evl */ 4450 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4451 netdev_features_t features) 4452 { 4453 /* IPv4 header has options field */ 4454 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4455 ip_hdrlen(skb) > sizeof(struct iphdr)) 4456 features &= ~NETIF_F_ALL_TSO; 4457 4458 /* IPv4 TCP header has options field */ 4459 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4460 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4461 features &= ~NETIF_F_ALL_TSO; 4462 4463 else if (rtl_last_frag_len(skb) <= 6) 4464 features &= ~NETIF_F_ALL_TSO; 4465 4466 return features; 4467 } 4468 4469 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4470 struct net_device *dev, 4471 netdev_features_t features) 4472 { 4473 struct rtl8169_private *tp = netdev_priv(dev); 4474 4475 if (skb_is_gso(skb)) { 4476 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4477 features = rtl8168evl_fix_tso(skb, features); 4478 4479 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4480 rtl_chip_supports_csum_v2(tp)) 4481 features &= ~NETIF_F_ALL_TSO; 4482 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4483 /* work around hw bug on some chip versions */ 4484 if (skb->len < ETH_ZLEN) 4485 features &= ~NETIF_F_CSUM_MASK; 4486 4487 if (rtl_quirk_packet_padto(tp, skb)) 4488 features &= ~NETIF_F_CSUM_MASK; 4489 4490 if (skb_transport_offset(skb) > TCPHO_MAX && 4491 rtl_chip_supports_csum_v2(tp)) 4492 features &= ~NETIF_F_CSUM_MASK; 4493 } 4494 4495 return vlan_features_check(skb, features); 4496 } 4497 4498 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4499 { 4500 struct rtl8169_private *tp = netdev_priv(dev); 4501 struct pci_dev *pdev = tp->pci_dev; 4502 int pci_status_errs; 4503 u16 pci_cmd; 4504 4505 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4506 4507 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4508 4509 if (net_ratelimit()) 4510 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4511 pci_cmd, pci_status_errs); 4512 4513 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4514 } 4515 4516 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4517 int budget) 4518 { 4519 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4520 struct sk_buff *skb; 4521 4522 dirty_tx = tp->dirty_tx; 4523 4524 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4525 unsigned int entry = dirty_tx % NUM_TX_DESC; 4526 u32 status; 4527 4528 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4529 if (status & DescOwn) 4530 break; 4531 4532 skb = tp->tx_skb[entry].skb; 4533 rtl8169_unmap_tx_skb(tp, entry); 4534 4535 if (skb) { 4536 pkts_compl++; 4537 bytes_compl += skb->len; 4538 napi_consume_skb(skb, budget); 4539 } 4540 dirty_tx++; 4541 } 4542 4543 if (tp->dirty_tx != dirty_tx) { 4544 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4545 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4546 4547 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4548 rtl_tx_slots_avail(tp), 4549 R8169_TX_START_THRS); 4550 /* 4551 * 8168 hack: TxPoll requests are lost when the Tx packets are 4552 * too close. Let's kick an extra TxPoll request when a burst 4553 * of start_xmit activity is detected (if it is not detected, 4554 * it is slow enough). -- FR 4555 * If skb is NULL then we come here again once a tx irq is 4556 * triggered after the last fragment is marked transmitted. 4557 */ 4558 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4559 rtl8169_doorbell(tp); 4560 } 4561 } 4562 4563 static inline int rtl8169_fragmented_frame(u32 status) 4564 { 4565 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4566 } 4567 4568 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4569 { 4570 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4571 4572 if (status == RxProtoTCP || status == RxProtoUDP) 4573 skb->ip_summed = CHECKSUM_UNNECESSARY; 4574 else 4575 skb_checksum_none_assert(skb); 4576 } 4577 4578 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4579 { 4580 struct device *d = tp_to_dev(tp); 4581 int count; 4582 4583 for (count = 0; count < budget; count++, tp->cur_rx++) { 4584 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4585 struct RxDesc *desc = tp->RxDescArray + entry; 4586 struct sk_buff *skb; 4587 const void *rx_buf; 4588 dma_addr_t addr; 4589 u32 status; 4590 4591 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4592 if (status & DescOwn) 4593 break; 4594 4595 /* This barrier is needed to keep us from reading 4596 * any other fields out of the Rx descriptor until 4597 * we know the status of DescOwn 4598 */ 4599 dma_rmb(); 4600 4601 if (unlikely(status & RxRES)) { 4602 if (net_ratelimit()) 4603 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4604 status); 4605 dev->stats.rx_errors++; 4606 if (status & (RxRWT | RxRUNT)) 4607 dev->stats.rx_length_errors++; 4608 if (status & RxCRC) 4609 dev->stats.rx_crc_errors++; 4610 4611 if (!(dev->features & NETIF_F_RXALL)) 4612 goto release_descriptor; 4613 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4614 goto release_descriptor; 4615 } 4616 4617 pkt_size = status & GENMASK(13, 0); 4618 if (likely(!(dev->features & NETIF_F_RXFCS))) 4619 pkt_size -= ETH_FCS_LEN; 4620 4621 /* The driver does not support incoming fragmented frames. 4622 * They are seen as a symptom of over-mtu sized frames. 4623 */ 4624 if (unlikely(rtl8169_fragmented_frame(status))) { 4625 dev->stats.rx_dropped++; 4626 dev->stats.rx_length_errors++; 4627 goto release_descriptor; 4628 } 4629 4630 skb = napi_alloc_skb(&tp->napi, pkt_size); 4631 if (unlikely(!skb)) { 4632 dev->stats.rx_dropped++; 4633 goto release_descriptor; 4634 } 4635 4636 addr = le64_to_cpu(desc->addr); 4637 rx_buf = page_address(tp->Rx_databuff[entry]); 4638 4639 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4640 prefetch(rx_buf); 4641 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4642 skb->tail += pkt_size; 4643 skb->len = pkt_size; 4644 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4645 4646 rtl8169_rx_csum(skb, status); 4647 skb->protocol = eth_type_trans(skb, dev); 4648 4649 rtl8169_rx_vlan_tag(desc, skb); 4650 4651 if (skb->pkt_type == PACKET_MULTICAST) 4652 dev->stats.multicast++; 4653 4654 napi_gro_receive(&tp->napi, skb); 4655 4656 dev_sw_netstats_rx_add(dev, pkt_size); 4657 release_descriptor: 4658 rtl8169_mark_to_asic(desc); 4659 } 4660 4661 return count; 4662 } 4663 4664 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4665 { 4666 struct rtl8169_private *tp = dev_instance; 4667 u32 status = rtl_get_events(tp); 4668 4669 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4670 return IRQ_NONE; 4671 4672 /* At least RTL8168fp may unexpectedly set the SYSErr bit */ 4673 if (unlikely(status & SYSErr && 4674 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { 4675 rtl8169_pcierr_interrupt(tp->dev); 4676 goto out; 4677 } 4678 4679 if (status & LinkChg) 4680 phy_mac_interrupt(tp->phydev); 4681 4682 if (unlikely(status & RxFIFOOver && 4683 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4684 netif_stop_queue(tp->dev); 4685 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4686 } 4687 4688 rtl_irq_disable(tp); 4689 napi_schedule(&tp->napi); 4690 out: 4691 rtl_ack_events(tp, status); 4692 4693 return IRQ_HANDLED; 4694 } 4695 4696 static void rtl_task(struct work_struct *work) 4697 { 4698 struct rtl8169_private *tp = 4699 container_of(work, struct rtl8169_private, wk.work); 4700 int ret; 4701 4702 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4703 /* if chip isn't accessible, reset bus to revive it */ 4704 if (RTL_R32(tp, TxConfig) == ~0) { 4705 ret = pci_reset_bus(tp->pci_dev); 4706 if (ret < 0) { 4707 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4708 netif_device_detach(tp->dev); 4709 return; 4710 } 4711 } 4712 4713 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4714 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4715 PCIE_LINK_STATE_L0S); 4716 if (!ret) 4717 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4718 goto reset; 4719 } 4720 4721 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4722 reset: 4723 rtl_reset_work(tp); 4724 netif_wake_queue(tp->dev); 4725 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4726 rtl_reset_work(tp); 4727 } 4728 } 4729 4730 static int rtl8169_poll(struct napi_struct *napi, int budget) 4731 { 4732 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4733 struct net_device *dev = tp->dev; 4734 int work_done; 4735 4736 rtl_tx(dev, tp, budget); 4737 4738 work_done = rtl_rx(dev, tp, budget); 4739 4740 if (work_done < budget && napi_complete_done(napi, work_done)) 4741 rtl_irq_enable(tp); 4742 4743 return work_done; 4744 } 4745 4746 static void r8169_phylink_handler(struct net_device *ndev) 4747 { 4748 struct rtl8169_private *tp = netdev_priv(ndev); 4749 struct device *d = tp_to_dev(tp); 4750 4751 if (netif_carrier_ok(ndev)) { 4752 rtl_link_chg_patch(tp); 4753 pm_request_resume(d); 4754 } else { 4755 pm_runtime_idle(d); 4756 } 4757 4758 phy_print_status(tp->phydev); 4759 } 4760 4761 static int r8169_phy_connect(struct rtl8169_private *tp) 4762 { 4763 struct phy_device *phydev = tp->phydev; 4764 phy_interface_t phy_mode; 4765 int ret; 4766 4767 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4768 PHY_INTERFACE_MODE_MII; 4769 4770 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4771 phy_mode); 4772 if (ret) 4773 return ret; 4774 4775 if (!tp->supports_gmii) 4776 phy_set_max_speed(phydev, SPEED_100); 4777 4778 phy_attached_info(phydev); 4779 4780 return 0; 4781 } 4782 4783 static void rtl8169_down(struct rtl8169_private *tp) 4784 { 4785 disable_work_sync(&tp->wk.work); 4786 /* Clear all task flags */ 4787 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4788 4789 phy_stop(tp->phydev); 4790 4791 rtl8169_update_counters(tp); 4792 4793 pci_clear_master(tp->pci_dev); 4794 rtl_pci_commit(tp); 4795 4796 rtl8169_cleanup(tp); 4797 rtl_disable_exit_l1(tp); 4798 rtl_prepare_power_down(tp); 4799 4800 if (tp->dash_type != RTL_DASH_NONE) 4801 rtl8168_driver_stop(tp); 4802 } 4803 4804 static void rtl8169_up(struct rtl8169_private *tp) 4805 { 4806 if (tp->dash_type != RTL_DASH_NONE) 4807 rtl8168_driver_start(tp); 4808 4809 pci_set_master(tp->pci_dev); 4810 phy_init_hw(tp->phydev); 4811 phy_resume(tp->phydev); 4812 rtl8169_init_phy(tp); 4813 napi_enable(&tp->napi); 4814 enable_work(&tp->wk.work); 4815 rtl_reset_work(tp); 4816 4817 phy_start(tp->phydev); 4818 } 4819 4820 static int rtl8169_close(struct net_device *dev) 4821 { 4822 struct rtl8169_private *tp = netdev_priv(dev); 4823 struct pci_dev *pdev = tp->pci_dev; 4824 4825 pm_runtime_get_sync(&pdev->dev); 4826 4827 netif_stop_queue(dev); 4828 rtl8169_down(tp); 4829 rtl8169_rx_clear(tp); 4830 4831 free_irq(tp->irq, tp); 4832 4833 phy_disconnect(tp->phydev); 4834 4835 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4836 tp->RxPhyAddr); 4837 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4838 tp->TxPhyAddr); 4839 tp->TxDescArray = NULL; 4840 tp->RxDescArray = NULL; 4841 4842 pm_runtime_put_sync(&pdev->dev); 4843 4844 return 0; 4845 } 4846 4847 #ifdef CONFIG_NET_POLL_CONTROLLER 4848 static void rtl8169_netpoll(struct net_device *dev) 4849 { 4850 struct rtl8169_private *tp = netdev_priv(dev); 4851 4852 rtl8169_interrupt(tp->irq, tp); 4853 } 4854 #endif 4855 4856 static int rtl_open(struct net_device *dev) 4857 { 4858 struct rtl8169_private *tp = netdev_priv(dev); 4859 struct pci_dev *pdev = tp->pci_dev; 4860 unsigned long irqflags; 4861 int retval = -ENOMEM; 4862 4863 pm_runtime_get_sync(&pdev->dev); 4864 4865 /* 4866 * Rx and Tx descriptors needs 256 bytes alignment. 4867 * dma_alloc_coherent provides more. 4868 */ 4869 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4870 &tp->TxPhyAddr, GFP_KERNEL); 4871 if (!tp->TxDescArray) 4872 goto out; 4873 4874 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4875 &tp->RxPhyAddr, GFP_KERNEL); 4876 if (!tp->RxDescArray) 4877 goto err_free_tx_0; 4878 4879 retval = rtl8169_init_ring(tp); 4880 if (retval < 0) 4881 goto err_free_rx_1; 4882 4883 rtl_request_firmware(tp); 4884 4885 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4886 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4887 if (retval < 0) 4888 goto err_release_fw_2; 4889 4890 retval = r8169_phy_connect(tp); 4891 if (retval) 4892 goto err_free_irq; 4893 4894 rtl8169_up(tp); 4895 rtl8169_init_counter_offsets(tp); 4896 netif_start_queue(dev); 4897 out: 4898 pm_runtime_put_sync(&pdev->dev); 4899 4900 return retval; 4901 4902 err_free_irq: 4903 free_irq(tp->irq, tp); 4904 err_release_fw_2: 4905 rtl_release_firmware(tp); 4906 rtl8169_rx_clear(tp); 4907 err_free_rx_1: 4908 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4909 tp->RxPhyAddr); 4910 tp->RxDescArray = NULL; 4911 err_free_tx_0: 4912 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4913 tp->TxPhyAddr); 4914 tp->TxDescArray = NULL; 4915 goto out; 4916 } 4917 4918 static void 4919 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4920 { 4921 struct rtl8169_private *tp = netdev_priv(dev); 4922 struct pci_dev *pdev = tp->pci_dev; 4923 struct rtl8169_counters *counters = tp->counters; 4924 4925 pm_runtime_get_noresume(&pdev->dev); 4926 4927 netdev_stats_to_stats64(stats, &dev->stats); 4928 dev_fetch_sw_netstats(stats, dev->tstats); 4929 4930 /* 4931 * Fetch additional counter values missing in stats collected by driver 4932 * from tally counters. 4933 */ 4934 if (pm_runtime_active(&pdev->dev)) 4935 rtl8169_update_counters(tp); 4936 4937 /* 4938 * Subtract values fetched during initalization. 4939 * See rtl8169_init_counter_offsets for a description why we do that. 4940 */ 4941 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4942 le64_to_cpu(tp->tc_offset.tx_errors); 4943 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4944 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4945 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4946 le16_to_cpu(tp->tc_offset.tx_aborted); 4947 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4948 le16_to_cpu(tp->tc_offset.rx_missed); 4949 4950 pm_runtime_put_noidle(&pdev->dev); 4951 } 4952 4953 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4954 { 4955 netif_device_detach(tp->dev); 4956 4957 if (netif_running(tp->dev)) 4958 rtl8169_down(tp); 4959 } 4960 4961 static int rtl8169_runtime_resume(struct device *dev) 4962 { 4963 struct rtl8169_private *tp = dev_get_drvdata(dev); 4964 4965 rtl_rar_set(tp, tp->dev->dev_addr); 4966 __rtl8169_set_wol(tp, tp->saved_wolopts); 4967 4968 if (tp->TxDescArray) 4969 rtl8169_up(tp); 4970 4971 netif_device_attach(tp->dev); 4972 4973 return 0; 4974 } 4975 4976 static int rtl8169_suspend(struct device *device) 4977 { 4978 struct rtl8169_private *tp = dev_get_drvdata(device); 4979 4980 rtnl_lock(); 4981 rtl8169_net_suspend(tp); 4982 if (!device_may_wakeup(tp_to_dev(tp))) 4983 clk_disable_unprepare(tp->clk); 4984 rtnl_unlock(); 4985 4986 return 0; 4987 } 4988 4989 static int rtl8169_resume(struct device *device) 4990 { 4991 struct rtl8169_private *tp = dev_get_drvdata(device); 4992 4993 if (!device_may_wakeup(tp_to_dev(tp))) 4994 clk_prepare_enable(tp->clk); 4995 4996 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4997 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4998 rtl_init_rxcfg(tp); 4999 5000 return rtl8169_runtime_resume(device); 5001 } 5002 5003 static int rtl8169_runtime_suspend(struct device *device) 5004 { 5005 struct rtl8169_private *tp = dev_get_drvdata(device); 5006 5007 if (!tp->TxDescArray) { 5008 netif_device_detach(tp->dev); 5009 return 0; 5010 } 5011 5012 rtnl_lock(); 5013 __rtl8169_set_wol(tp, WAKE_PHY); 5014 rtl8169_net_suspend(tp); 5015 rtnl_unlock(); 5016 5017 return 0; 5018 } 5019 5020 static int rtl8169_runtime_idle(struct device *device) 5021 { 5022 struct rtl8169_private *tp = dev_get_drvdata(device); 5023 5024 if (tp->dash_enabled) 5025 return -EBUSY; 5026 5027 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5028 pm_schedule_suspend(device, 10000); 5029 5030 return -EBUSY; 5031 } 5032 5033 static const struct dev_pm_ops rtl8169_pm_ops = { 5034 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5035 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5036 rtl8169_runtime_idle) 5037 }; 5038 5039 static void rtl_shutdown(struct pci_dev *pdev) 5040 { 5041 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5042 5043 rtnl_lock(); 5044 rtl8169_net_suspend(tp); 5045 rtnl_unlock(); 5046 5047 /* Restore original MAC address */ 5048 rtl_rar_set(tp, tp->dev->perm_addr); 5049 5050 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5051 pci_wake_from_d3(pdev, tp->saved_wolopts); 5052 pci_set_power_state(pdev, PCI_D3hot); 5053 } 5054 } 5055 5056 static void rtl_remove_one(struct pci_dev *pdev) 5057 { 5058 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5059 5060 if (pci_dev_run_wake(pdev)) 5061 pm_runtime_get_noresume(&pdev->dev); 5062 5063 disable_work_sync(&tp->wk.work); 5064 5065 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5066 r8169_remove_leds(tp->leds); 5067 5068 unregister_netdev(tp->dev); 5069 5070 if (tp->dash_type != RTL_DASH_NONE) 5071 rtl8168_driver_stop(tp); 5072 5073 rtl_release_firmware(tp); 5074 5075 /* restore original MAC address */ 5076 rtl_rar_set(tp, tp->dev->perm_addr); 5077 } 5078 5079 static const struct net_device_ops rtl_netdev_ops = { 5080 .ndo_open = rtl_open, 5081 .ndo_stop = rtl8169_close, 5082 .ndo_get_stats64 = rtl8169_get_stats64, 5083 .ndo_start_xmit = rtl8169_start_xmit, 5084 .ndo_features_check = rtl8169_features_check, 5085 .ndo_tx_timeout = rtl8169_tx_timeout, 5086 .ndo_validate_addr = eth_validate_addr, 5087 .ndo_change_mtu = rtl8169_change_mtu, 5088 .ndo_fix_features = rtl8169_fix_features, 5089 .ndo_set_features = rtl8169_set_features, 5090 .ndo_set_mac_address = rtl_set_mac_address, 5091 .ndo_eth_ioctl = phy_do_ioctl_running, 5092 .ndo_set_rx_mode = rtl_set_rx_mode, 5093 #ifdef CONFIG_NET_POLL_CONTROLLER 5094 .ndo_poll_controller = rtl8169_netpoll, 5095 #endif 5096 5097 }; 5098 5099 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5100 { 5101 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5102 5103 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5104 tp->irq_mask |= SYSErr | RxFIFOOver; 5105 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5106 /* special workaround needed */ 5107 tp->irq_mask |= RxFIFOOver; 5108 } 5109 5110 static int rtl_alloc_irq(struct rtl8169_private *tp) 5111 { 5112 unsigned int flags; 5113 5114 switch (tp->mac_version) { 5115 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5116 rtl_unlock_config_regs(tp); 5117 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5118 rtl_lock_config_regs(tp); 5119 fallthrough; 5120 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5121 flags = PCI_IRQ_INTX; 5122 break; 5123 default: 5124 flags = PCI_IRQ_ALL_TYPES; 5125 break; 5126 } 5127 5128 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5129 } 5130 5131 static void rtl_read_mac_address(struct rtl8169_private *tp, 5132 u8 mac_addr[ETH_ALEN]) 5133 { 5134 /* Get MAC address */ 5135 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5136 u32 value; 5137 5138 value = rtl_eri_read(tp, 0xe0); 5139 put_unaligned_le32(value, mac_addr); 5140 value = rtl_eri_read(tp, 0xe4); 5141 put_unaligned_le16(value, mac_addr + 4); 5142 } else if (rtl_is_8125(tp)) { 5143 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5144 } 5145 } 5146 5147 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5148 { 5149 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5150 } 5151 5152 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5153 { 5154 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5155 } 5156 5157 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5158 { 5159 struct rtl8169_private *tp = mii_bus->priv; 5160 5161 if (phyaddr > 0) 5162 return -ENODEV; 5163 5164 return rtl_readphy(tp, phyreg); 5165 } 5166 5167 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5168 int phyreg, u16 val) 5169 { 5170 struct rtl8169_private *tp = mii_bus->priv; 5171 5172 if (phyaddr > 0) 5173 return -ENODEV; 5174 5175 rtl_writephy(tp, phyreg, val); 5176 5177 return 0; 5178 } 5179 5180 static int r8169_mdio_register(struct rtl8169_private *tp) 5181 { 5182 struct pci_dev *pdev = tp->pci_dev; 5183 struct mii_bus *new_bus; 5184 int ret; 5185 5186 /* On some boards with this chip version the BIOS is buggy and misses 5187 * to reset the PHY page selector. This results in the PHY ID read 5188 * accessing registers on a different page, returning a more or 5189 * less random value. Fix this by resetting the page selector first. 5190 */ 5191 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5192 tp->mac_version == RTL_GIGA_MAC_VER_26) 5193 r8169_mdio_write(tp, 0x1f, 0); 5194 5195 new_bus = devm_mdiobus_alloc(&pdev->dev); 5196 if (!new_bus) 5197 return -ENOMEM; 5198 5199 new_bus->name = "r8169"; 5200 new_bus->priv = tp; 5201 new_bus->parent = &pdev->dev; 5202 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5203 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5204 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5205 5206 new_bus->read = r8169_mdio_read_reg; 5207 new_bus->write = r8169_mdio_write_reg; 5208 5209 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5210 if (ret) 5211 return ret; 5212 5213 tp->phydev = mdiobus_get_phy(new_bus, 0); 5214 if (!tp->phydev) { 5215 return -ENODEV; 5216 } else if (!tp->phydev->drv) { 5217 /* Most chip versions fail with the genphy driver. 5218 * Therefore ensure that the dedicated PHY driver is loaded. 5219 */ 5220 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5221 tp->phydev->phy_id); 5222 return -EUNATCH; 5223 } 5224 5225 tp->phydev->mac_managed_pm = true; 5226 if (rtl_supports_eee(tp)) 5227 phy_support_eee(tp->phydev); 5228 phy_support_asym_pause(tp->phydev); 5229 5230 /* mimic behavior of r8125/r8126 vendor drivers */ 5231 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 5232 phy_set_eee_broken(tp->phydev, 5233 ETHTOOL_LINK_MODE_2500baseT_Full_BIT); 5234 phy_set_eee_broken(tp->phydev, ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 5235 5236 /* PHY will be woken up in rtl_open() */ 5237 phy_suspend(tp->phydev); 5238 5239 return 0; 5240 } 5241 5242 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5243 { 5244 rtl_enable_rxdvgate(tp); 5245 5246 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5247 msleep(1); 5248 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5249 5250 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5251 r8168g_wait_ll_share_fifo_ready(tp); 5252 5253 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5254 r8168g_wait_ll_share_fifo_ready(tp); 5255 } 5256 5257 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5258 { 5259 rtl_enable_rxdvgate(tp); 5260 5261 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5262 msleep(1); 5263 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5264 5265 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5266 r8168g_wait_ll_share_fifo_ready(tp); 5267 5268 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5269 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5270 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5271 r8168g_wait_ll_share_fifo_ready(tp); 5272 } 5273 5274 static void rtl_hw_initialize(struct rtl8169_private *tp) 5275 { 5276 switch (tp->mac_version) { 5277 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5278 rtl8168ep_stop_cmac(tp); 5279 fallthrough; 5280 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5281 rtl_hw_init_8168g(tp); 5282 break; 5283 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 5284 rtl_hw_init_8125(tp); 5285 break; 5286 default: 5287 break; 5288 } 5289 } 5290 5291 static int rtl_jumbo_max(struct rtl8169_private *tp) 5292 { 5293 /* Non-GBit versions don't support jumbo frames */ 5294 if (!tp->supports_gmii) 5295 return 0; 5296 5297 switch (tp->mac_version) { 5298 /* RTL8169 */ 5299 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5300 return JUMBO_7K; 5301 /* RTL8168b */ 5302 case RTL_GIGA_MAC_VER_11: 5303 case RTL_GIGA_MAC_VER_17: 5304 return JUMBO_4K; 5305 /* RTL8168c */ 5306 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5307 return JUMBO_6K; 5308 default: 5309 return JUMBO_9K; 5310 } 5311 } 5312 5313 static void rtl_init_mac_address(struct rtl8169_private *tp) 5314 { 5315 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5316 struct net_device *dev = tp->dev; 5317 int rc; 5318 5319 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5320 if (!rc) 5321 goto done; 5322 5323 rtl_read_mac_address(tp, mac_addr); 5324 if (is_valid_ether_addr(mac_addr)) 5325 goto done; 5326 5327 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5328 if (is_valid_ether_addr(mac_addr)) 5329 goto done; 5330 5331 eth_random_addr(mac_addr); 5332 dev->addr_assign_type = NET_ADDR_RANDOM; 5333 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5334 done: 5335 eth_hw_addr_set(dev, mac_addr); 5336 rtl_rar_set(tp, mac_addr); 5337 } 5338 5339 /* register is set if system vendor successfully tested ASPM 1.2 */ 5340 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5341 { 5342 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5343 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5344 return true; 5345 5346 return false; 5347 } 5348 5349 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5350 { 5351 struct rtl8169_private *tp; 5352 int jumbo_max, region, rc; 5353 enum mac_version chipset; 5354 struct net_device *dev; 5355 u32 txconfig; 5356 u16 xid; 5357 5358 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5359 if (!dev) 5360 return -ENOMEM; 5361 5362 SET_NETDEV_DEV(dev, &pdev->dev); 5363 dev->netdev_ops = &rtl_netdev_ops; 5364 tp = netdev_priv(dev); 5365 tp->dev = dev; 5366 tp->pci_dev = pdev; 5367 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5368 tp->ocp_base = OCP_STD_PHY_BASE; 5369 5370 raw_spin_lock_init(&tp->mac_ocp_lock); 5371 mutex_init(&tp->led_lock); 5372 5373 /* Get the *optional* external "ether_clk" used on some boards */ 5374 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5375 if (IS_ERR(tp->clk)) 5376 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5377 5378 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5379 rc = pcim_enable_device(pdev); 5380 if (rc < 0) 5381 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5382 5383 if (pcim_set_mwi(pdev) < 0) 5384 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5385 5386 /* use first MMIO region */ 5387 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5388 if (region < 0) 5389 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5390 5391 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5392 if (rc < 0) 5393 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5394 5395 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5396 5397 txconfig = RTL_R32(tp, TxConfig); 5398 if (txconfig == ~0U) 5399 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5400 5401 xid = (txconfig >> 20) & 0xfcf; 5402 5403 /* Identify chip attached to board */ 5404 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5405 if (chipset == RTL_GIGA_MAC_NONE) 5406 return dev_err_probe(&pdev->dev, -ENODEV, 5407 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5408 xid); 5409 tp->mac_version = chipset; 5410 5411 /* Disable ASPM L1 as that cause random device stop working 5412 * problems as well as full system hangs for some PCIe devices users. 5413 */ 5414 if (rtl_aspm_is_safe(tp)) 5415 rc = 0; 5416 else 5417 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5418 tp->aspm_manageable = !rc; 5419 5420 tp->dash_type = rtl_get_dash_type(tp); 5421 tp->dash_enabled = rtl_dash_is_enabled(tp); 5422 5423 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5424 5425 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5426 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5427 dev->features |= NETIF_F_HIGHDMA; 5428 5429 rtl_init_rxcfg(tp); 5430 5431 rtl8169_irq_mask_and_ack(tp); 5432 5433 rtl_hw_initialize(tp); 5434 5435 rtl_hw_reset(tp); 5436 5437 rc = rtl_alloc_irq(tp); 5438 if (rc < 0) 5439 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5440 5441 tp->irq = pci_irq_vector(pdev, 0); 5442 5443 INIT_WORK(&tp->wk.work, rtl_task); 5444 disable_work(&tp->wk.work); 5445 5446 rtl_init_mac_address(tp); 5447 5448 dev->ethtool_ops = &rtl8169_ethtool_ops; 5449 5450 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5451 5452 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5453 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5454 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5455 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5456 5457 /* 5458 * Pretend we are using VLANs; This bypasses a nasty bug where 5459 * Interrupts stop flowing on high load on 8110SCd controllers. 5460 */ 5461 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5462 /* Disallow toggling */ 5463 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5464 5465 if (rtl_chip_supports_csum_v2(tp)) 5466 dev->hw_features |= NETIF_F_IPV6_CSUM; 5467 5468 dev->features |= dev->hw_features; 5469 5470 if (rtl_chip_supports_csum_v2(tp)) { 5471 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5472 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5473 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5474 } else { 5475 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5476 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5477 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5478 } 5479 5480 /* There has been a number of reports that using SG/TSO results in 5481 * tx timeouts. However for a lot of people SG/TSO works fine. 5482 * It's not fully clear which chip versions are affected. Vendor 5483 * drivers enable SG/TSO for certain chip versions per default, 5484 * let's mimic this here. On other chip versions users can 5485 * use ethtool to enable SG/TSO, use at own risk! 5486 */ 5487 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5488 tp->mac_version != RTL_GIGA_MAC_VER_61) 5489 dev->features |= dev->hw_features; 5490 5491 dev->hw_features |= NETIF_F_RXALL; 5492 dev->hw_features |= NETIF_F_RXFCS; 5493 5494 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5495 5496 netdev_sw_irq_coalesce_default_on(dev); 5497 5498 /* configure chip for default features */ 5499 rtl8169_set_features(dev, dev->features); 5500 5501 if (!tp->dash_enabled) { 5502 rtl_set_d3_pll_down(tp, true); 5503 } else { 5504 rtl_set_d3_pll_down(tp, false); 5505 dev->ethtool->wol_enabled = 1; 5506 } 5507 5508 jumbo_max = rtl_jumbo_max(tp); 5509 if (jumbo_max) 5510 dev->max_mtu = jumbo_max; 5511 5512 rtl_set_irq_mask(tp); 5513 5514 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5515 5516 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5517 &tp->counters_phys_addr, 5518 GFP_KERNEL); 5519 if (!tp->counters) 5520 return -ENOMEM; 5521 5522 pci_set_drvdata(pdev, tp); 5523 5524 rc = r8169_mdio_register(tp); 5525 if (rc) 5526 return rc; 5527 5528 rc = register_netdev(dev); 5529 if (rc) 5530 return rc; 5531 5532 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5533 if (rtl_is_8125(tp)) 5534 tp->leds = rtl8125_init_leds(dev); 5535 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5536 tp->leds = rtl8168_init_leds(dev); 5537 } 5538 5539 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5540 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5541 5542 if (jumbo_max) 5543 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5544 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5545 "ok" : "ko"); 5546 5547 if (tp->dash_type != RTL_DASH_NONE) { 5548 netdev_info(dev, "DASH %s\n", 5549 tp->dash_enabled ? "enabled" : "disabled"); 5550 rtl8168_driver_start(tp); 5551 } 5552 5553 if (pci_dev_run_wake(pdev)) 5554 pm_runtime_put_sync(&pdev->dev); 5555 5556 return 0; 5557 } 5558 5559 static struct pci_driver rtl8169_pci_driver = { 5560 .name = KBUILD_MODNAME, 5561 .id_table = rtl8169_pci_tbl, 5562 .probe = rtl_init_one, 5563 .remove = rtl_remove_one, 5564 .shutdown = rtl_shutdown, 5565 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5566 }; 5567 5568 module_pci_driver(rtl8169_pci_driver); 5569