1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <linux/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 #include <net/phy/realtek_phy.h> 35 36 #include "r8169.h" 37 #include "r8169_firmware.h" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 59 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" 60 #define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw" 61 #define FIRMWARE_8125K_1 "rtl_nic/rtl8125k-1.fw" 62 #define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw" 63 #define FIRMWARE_9151A_1 "rtl_nic/rtl9151a-1.fw" 64 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 65 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 66 #define FIRMWARE_8127A_1 "rtl_nic/rtl8127a-1.fw" 67 68 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 69 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 70 71 #define R8169_REGS_SIZE 256 72 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 73 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 74 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 77 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 78 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 79 80 #define OCP_STD_PHY_BASE 0xa400 81 82 #define RTL_CFG_NO_GBIT 1 83 84 /* write/read MMIO register */ 85 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 86 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 87 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 88 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 89 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 90 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 91 92 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 93 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 94 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 95 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 96 #define JUMBO_16K (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN) 97 98 static const struct rtl_chip_info { 99 u32 mask; 100 u32 val; 101 enum mac_version mac_version; 102 const char *name; 103 const char *fw_name; 104 } rtl_chip_infos[] = { 105 /* 8127A family. */ 106 { 0x7cf, 0x6c9, RTL_GIGA_MAC_VER_80, "RTL8127A", FIRMWARE_8127A_1 }, 107 108 /* 8126A family. */ 109 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_3 }, 110 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70, "RTL8126A", FIRMWARE_8126A_2 }, 111 112 /* 8125BP family. */ 113 { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66, "RTL8125BP", FIRMWARE_8125BP_2 }, 114 115 /* 8125D family. */ 116 { 0x7cf, 0x68b, RTL_GIGA_MAC_VER_64, "RTL9151A", FIRMWARE_9151A_1 }, 117 { 0x7cf, 0x68a, RTL_GIGA_MAC_VER_64, "RTL8125K", FIRMWARE_8125K_1 }, 118 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_2 }, 119 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64, "RTL8125D", FIRMWARE_8125D_1 }, 120 121 /* 8125B family. */ 122 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63, "RTL8125B", FIRMWARE_8125B_2 }, 123 124 /* 8125A family. */ 125 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61, "RTL8125A", FIRMWARE_8125A_3 }, 126 127 /* RTL8117 */ 128 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117" }, 129 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52, "RTL8168fp/RTL8117", 130 FIRMWARE_8168FP_3 }, 131 132 /* 8168EP family. */ 133 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51, "RTL8168ep/8111ep" }, 134 135 /* 8168H family. */ 136 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46, "RTL8168h/8111h", 137 FIRMWARE_8168H_2 }, 138 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 139 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46, "RTL8168M", FIRMWARE_8168H_2 }, 140 141 /* 8168G family. */ 142 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44, "RTL8411b", FIRMWARE_8411_2 }, 143 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42, "RTL8168gu/8111gu", 144 FIRMWARE_8168G_3 }, 145 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40, "RTL8168g/8111g", 146 FIRMWARE_8168G_2 }, 147 148 /* 8168F family. */ 149 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38, "RTL8411", FIRMWARE_8411_1 }, 150 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36, "RTL8168f/8111f", 151 FIRMWARE_8168F_2 }, 152 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35, "RTL8168f/8111f", 153 FIRMWARE_8168F_1 }, 154 155 /* 8168E family. */ 156 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34, "RTL8168evl/8111evl", 157 FIRMWARE_8168E_3 }, 158 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32, "RTL8168e/8111e", 159 FIRMWARE_8168E_1 }, 160 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33, "RTL8168e/8111e", 161 FIRMWARE_8168E_2 }, 162 163 /* 8168D family. */ 164 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25, "RTL8168d/8111d", 165 FIRMWARE_8168D_1 }, 166 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26, "RTL8168d/8111d", 167 FIRMWARE_8168D_2 }, 168 169 /* 8168DP family. */ 170 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28, "RTL8168dp/8111dp" }, 171 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31, "RTL8168dp/8111dp" }, 172 173 /* 8168C family. */ 174 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23, "RTL8168cp/8111cp" }, 175 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18, "RTL8168cp/8111cp" }, 176 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24, "RTL8168cp/8111cp" }, 177 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19, "RTL8168c/8111c" }, 178 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20, "RTL8168c/8111c" }, 179 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21, "RTL8168c/8111c" }, 180 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22, "RTL8168c/8111c" }, 181 182 /* 8168B family. */ 183 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17, "RTL8168b/8111b" }, 184 /* This one is very old and rare, support has been removed. 185 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11, "RTL8168b/8111b" }, 186 */ 187 188 /* 8101 family. */ 189 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39, "RTL8106e", FIRMWARE_8106E_1 }, 190 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37, "RTL8402", FIRMWARE_8402_1 }, 191 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29, "RTL8105e", FIRMWARE_8105E_1 }, 192 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30, "RTL8105e", FIRMWARE_8105E_1 }, 193 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08, "RTL8102e" }, 194 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08, "RTL8102e" }, 195 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07, "RTL8102e" }, 196 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07, "RTL8102e" }, 197 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14, "RTL8401" }, 198 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, 199 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09, "RTL8102e/RTL8103e" }, 200 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10, "RTL8101e/RTL8100e" }, 201 202 /* 8110 family. */ 203 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06, "RTL8169sc/8110sc" }, 204 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05, "RTL8169sc/8110sc" }, 205 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04, "RTL8169sb/8110sb" }, 206 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" }, 207 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" }, 208 209 /* extended chip version*/ 210 { 0x7cf, 0x7c8, RTL_GIGA_MAC_VER_EXTENDED }, 211 212 /* Catch-all */ 213 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 214 }; 215 216 static const struct rtl_chip_info rtl_chip_infos_extended[] = { 217 { 0x7fffffff, 0x00000000, RTL_GIGA_MAC_VER_64, "RTL9151AS", 218 FIRMWARE_9151A_1}, 219 220 /* Catch-all */ 221 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } 222 }; 223 224 static const struct pci_device_id rtl8169_pci_tbl[] = { 225 { PCI_VDEVICE(REALTEK, 0x2502) }, 226 { PCI_VDEVICE(REALTEK, 0x2600) }, 227 { PCI_VDEVICE(REALTEK, 0x8129) }, 228 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 229 { PCI_VDEVICE(REALTEK, 0x8161) }, 230 { PCI_VDEVICE(REALTEK, 0x8162) }, 231 { PCI_VDEVICE(REALTEK, 0x8167) }, 232 { PCI_VDEVICE(REALTEK, 0x8168) }, 233 { PCI_VDEVICE(NCUBE, 0x8168) }, 234 { PCI_VDEVICE(REALTEK, 0x8169) }, 235 { PCI_VDEVICE(DLINK, 0x4300) }, 236 { PCI_VDEVICE(DLINK, 0x4302) }, 237 { PCI_VDEVICE(AT, 0xc107) }, 238 { PCI_VDEVICE(USR, 0x0116) }, 239 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 240 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 241 { PCI_VDEVICE(REALTEK, 0x8125) }, 242 { PCI_VDEVICE(REALTEK, 0x8126) }, 243 { PCI_VDEVICE(REALTEK, 0x8127) }, 244 { PCI_VDEVICE(REALTEK, 0x3000) }, 245 { PCI_VDEVICE(REALTEK, 0x5000) }, 246 { PCI_VDEVICE(REALTEK, 0x0e10) }, 247 {} 248 }; 249 250 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 251 252 enum rtl_registers { 253 MAC0 = 0, /* Ethernet hardware address. */ 254 MAC4 = 4, 255 MAR0 = 8, /* Multicast filter. */ 256 CounterAddrLow = 0x10, 257 CounterAddrHigh = 0x14, 258 TxDescStartAddrLow = 0x20, 259 TxDescStartAddrHigh = 0x24, 260 TxHDescStartAddrLow = 0x28, 261 TxHDescStartAddrHigh = 0x2c, 262 FLASH = 0x30, 263 ERSR = 0x36, 264 ChipCmd = 0x37, 265 TxPoll = 0x38, 266 IntrMask = 0x3c, 267 IntrStatus = 0x3e, 268 269 TxConfig = 0x40, 270 /* Extended chip version id */ 271 TX_CONFIG_V2 = 0x60b0, 272 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 273 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 274 275 RxConfig = 0x44, 276 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 277 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 278 #define RXCFG_FIFO_SHIFT 13 279 /* No threshold before first PCI xfer */ 280 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 281 #define RX_EARLY_OFF (1 << 11) 282 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 283 #define RXCFG_DMA_SHIFT 8 284 /* Unlimited maximum PCI burst. */ 285 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 286 287 Cfg9346 = 0x50, 288 Config0 = 0x51, 289 Config1 = 0x52, 290 Config2 = 0x53, 291 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 292 293 Config3 = 0x54, 294 Config4 = 0x55, 295 Config5 = 0x56, 296 PHYAR = 0x60, 297 PHYstatus = 0x6c, 298 RxMaxSize = 0xda, 299 CPlusCmd = 0xe0, 300 IntrMitigate = 0xe2, 301 302 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 303 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 304 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 305 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 306 307 #define RTL_COALESCE_T_MAX 0x0fU 308 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 309 310 RxDescAddrLow = 0xe4, 311 RxDescAddrHigh = 0xe8, 312 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 313 314 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 315 316 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 317 318 #define TxPacketMax (8064 >> 7) 319 #define EarlySize 0x27 320 321 FuncEvent = 0xf0, 322 FuncEventMask = 0xf4, 323 FuncPresetState = 0xf8, 324 IBCR0 = 0xf8, 325 IBCR2 = 0xf9, 326 IBIMR0 = 0xfa, 327 IBISR0 = 0xfb, 328 FuncForceEvent = 0xfc, 329 330 ALDPS_LTR = 0xe0a2, 331 LTR_OBFF_LOCK = 0xe032, 332 LTR_SNOOP = 0xe034, 333 334 #define ALDPS_LTR_EN BIT(0) 335 #define LTR_OBFF_LOCK_EN BIT(0) 336 #define LINK_SPEED_CHANGE_EN BIT(14) 337 #define LTR_SNOOP_EN GENMASK(15, 14) 338 }; 339 340 enum rtl8168_8101_registers { 341 CSIDR = 0x64, 342 CSIAR = 0x68, 343 #define CSIAR_FLAG 0x80000000 344 #define CSIAR_WRITE_CMD 0x80000000 345 #define CSIAR_BYTE_ENABLE 0x0000f000 346 #define CSIAR_ADDR_MASK 0x00000fff 347 PMCH = 0x6f, 348 #define D3COLD_NO_PLL_DOWN BIT(7) 349 #define D3HOT_NO_PLL_DOWN BIT(6) 350 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 351 EPHYAR = 0x80, 352 #define EPHYAR_FLAG 0x80000000 353 #define EPHYAR_WRITE_CMD 0x80000000 354 #define EPHYAR_REG_MASK 0x1f 355 #define EPHYAR_REG_SHIFT 16 356 #define EPHYAR_DATA_MASK 0xffff 357 DLLPR = 0xd0, 358 #define PFM_EN (1 << 6) 359 #define TX_10M_PS_EN (1 << 7) 360 DBG_REG = 0xd1, 361 #define FIX_NAK_1 (1 << 4) 362 #define FIX_NAK_2 (1 << 3) 363 TWSI = 0xd2, 364 MCU = 0xd3, 365 #define NOW_IS_OOB (1 << 7) 366 #define TX_EMPTY (1 << 5) 367 #define RX_EMPTY (1 << 4) 368 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 369 #define EN_NDP (1 << 3) 370 #define EN_OOB_RESET (1 << 2) 371 #define LINK_LIST_RDY (1 << 1) 372 EFUSEAR = 0xdc, 373 #define EFUSEAR_FLAG 0x80000000 374 #define EFUSEAR_WRITE_CMD 0x80000000 375 #define EFUSEAR_READ_CMD 0x00000000 376 #define EFUSEAR_REG_MASK 0x03ff 377 #define EFUSEAR_REG_SHIFT 8 378 #define EFUSEAR_DATA_MASK 0xff 379 MISC_1 = 0xf2, 380 #define PFM_D3COLD_EN (1 << 6) 381 }; 382 383 enum rtl8168_registers { 384 LED_CTRL = 0x18, 385 LED_FREQ = 0x1a, 386 EEE_LED = 0x1b, 387 ERIDR = 0x70, 388 ERIAR = 0x74, 389 #define ERIAR_FLAG 0x80000000 390 #define ERIAR_WRITE_CMD 0x80000000 391 #define ERIAR_READ_CMD 0x00000000 392 #define ERIAR_ADDR_BYTE_ALIGN 4 393 #define ERIAR_TYPE_SHIFT 16 394 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 395 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 396 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 397 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 398 #define ERIAR_MASK_SHIFT 12 399 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 400 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 401 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 402 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 403 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 404 EPHY_RXER_NUM = 0x7c, 405 OCPDR = 0xb0, /* OCP GPHY access */ 406 #define OCPDR_WRITE_CMD 0x80000000 407 #define OCPDR_READ_CMD 0x00000000 408 #define OCPDR_REG_MASK 0x7f 409 #define OCPDR_GPHY_REG_SHIFT 16 410 #define OCPDR_DATA_MASK 0xffff 411 OCPAR = 0xb4, 412 #define OCPAR_FLAG 0x80000000 413 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 414 #define OCPAR_GPHY_READ_CMD 0x0000f060 415 GPHY_OCP = 0xb8, 416 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 417 MISC = 0xf0, /* 8168e only. */ 418 #define TXPLA_RST (1 << 29) 419 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 420 #define PWM_EN (1 << 22) 421 #define RXDV_GATED_EN (1 << 19) 422 #define EARLY_TALLY_EN (1 << 16) 423 COMBO_LTR_EXTEND = 0xb6, 424 #define COMBO_LTR_EXTEND_EN BIT(0) 425 }; 426 427 enum rtl8125_registers { 428 LEDSEL0 = 0x18, 429 INT_CFG0_8125 = 0x34, 430 #define INT_CFG0_ENABLE_8125 BIT(0) 431 #define INT_CFG0_CLKREQEN BIT(3) 432 IntrMask_8125 = 0x38, 433 IntrStatus_8125 = 0x3c, 434 INT_CFG1_8125 = 0x7a, 435 LEDSEL2 = 0x84, 436 LEDSEL1 = 0x86, 437 TxPoll_8125 = 0x90, 438 LEDSEL3 = 0x96, 439 MAC0_BKP = 0x19e0, 440 RSS_CTRL_8125 = 0x4500, 441 Q_NUM_CTRL_8125 = 0x4800, 442 EEE_TXIDLE_TIMER_8125 = 0x6048, 443 }; 444 445 #define LEDSEL_MASK_8125 0x23f 446 447 #define RX_VLAN_INNER_8125 BIT(22) 448 #define RX_VLAN_OUTER_8125 BIT(23) 449 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 450 451 #define RX_FETCH_DFLT_8125 (8 << 27) 452 453 enum rtl_register_content { 454 /* InterruptStatusBits */ 455 SYSErr = 0x8000, 456 PCSTimeout = 0x4000, 457 SWInt = 0x0100, 458 TxDescUnavail = 0x0080, 459 RxFIFOOver = 0x0040, 460 LinkChg = 0x0020, 461 RxOverflow = 0x0010, 462 TxErr = 0x0008, 463 TxOK = 0x0004, 464 RxErr = 0x0002, 465 RxOK = 0x0001, 466 467 /* RxStatusDesc */ 468 RxRWT = (1 << 22), 469 RxRES = (1 << 21), 470 RxRUNT = (1 << 20), 471 RxCRC = (1 << 19), 472 473 /* ChipCmdBits */ 474 StopReq = 0x80, 475 CmdReset = 0x10, 476 CmdRxEnb = 0x08, 477 CmdTxEnb = 0x04, 478 RxBufEmpty = 0x01, 479 480 /* TXPoll register p.5 */ 481 HPQ = 0x80, /* Poll cmd on the high prio queue */ 482 NPQ = 0x40, /* Poll cmd on the low prio queue */ 483 FSWInt = 0x01, /* Forced software interrupt */ 484 485 /* Cfg9346Bits */ 486 Cfg9346_Lock = 0x00, 487 Cfg9346_Unlock = 0xc0, 488 489 /* rx_mode_bits */ 490 AcceptErr = 0x20, 491 AcceptRunt = 0x10, 492 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 493 AcceptBroadcast = 0x08, 494 AcceptMulticast = 0x04, 495 AcceptMyPhys = 0x02, 496 AcceptAllPhys = 0x01, 497 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 498 #define RX_CONFIG_ACCEPT_MASK 0x3f 499 500 /* TxConfigBits */ 501 TxInterFrameGapShift = 24, 502 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 503 504 /* Config1 register p.24 */ 505 LEDS1 = (1 << 7), 506 LEDS0 = (1 << 6), 507 Speed_down = (1 << 4), 508 MEMMAP = (1 << 3), 509 IOMAP = (1 << 2), 510 VPD = (1 << 1), 511 PMEnable = (1 << 0), /* Power Management Enable */ 512 513 /* Config2 register p. 25 */ 514 ClkReqEn = (1 << 7), /* Clock Request Enable */ 515 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 516 PCI_Clock_66MHz = 0x01, 517 PCI_Clock_33MHz = 0x00, 518 519 /* Config3 register p.25 */ 520 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 521 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 522 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 523 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 524 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 525 526 /* Config4 register */ 527 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 528 529 /* Config5 register p.27 */ 530 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 531 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 532 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 533 Spi_en = (1 << 3), 534 LanWake = (1 << 1), /* LanWake enable/disable */ 535 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 536 ASPM_en = (1 << 0), /* ASPM enable */ 537 538 /* CPlusCmd p.31 */ 539 EnableBist = (1 << 15), // 8168 8101 540 Mac_dbgo_oe = (1 << 14), // 8168 8101 541 EnAnaPLL = (1 << 14), // 8169 542 Normal_mode = (1 << 13), // unused 543 Force_half_dup = (1 << 12), // 8168 8101 544 Force_rxflow_en = (1 << 11), // 8168 8101 545 Force_txflow_en = (1 << 10), // 8168 8101 546 Cxpl_dbg_sel = (1 << 9), // 8168 8101 547 ASF = (1 << 8), // 8168 8101 548 PktCntrDisable = (1 << 7), // 8168 8101 549 Mac_dbgo_sel = 0x001c, // 8168 550 RxVlan = (1 << 6), 551 RxChkSum = (1 << 5), 552 PCIDAC = (1 << 4), 553 PCIMulRW = (1 << 3), 554 #define INTT_MASK GENMASK(1, 0) 555 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 556 557 /* rtl8169_PHYstatus */ 558 TBI_Enable = 0x80, 559 TxFlowCtrl = 0x40, 560 RxFlowCtrl = 0x20, 561 _1000bpsF = 0x10, 562 _100bps = 0x08, 563 _10bps = 0x04, 564 LinkStatus = 0x02, 565 FullDup = 0x01, 566 567 /* ResetCounterCommand */ 568 CounterReset = 0x1, 569 570 /* DumpCounterCommand */ 571 CounterDump = 0x8, 572 573 /* magic enable v2 */ 574 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 575 }; 576 577 enum rtl_desc_bit { 578 /* First doubleword. */ 579 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 580 RingEnd = (1 << 30), /* End of descriptor ring */ 581 FirstFrag = (1 << 29), /* First segment of a packet */ 582 LastFrag = (1 << 28), /* Final segment of a packet */ 583 }; 584 585 /* Generic case. */ 586 enum rtl_tx_desc_bit { 587 /* First doubleword. */ 588 TD_LSO = (1 << 27), /* Large Send Offload */ 589 #define TD_MSS_MAX 0x07ffu /* MSS value */ 590 591 /* Second doubleword. */ 592 TxVlanTag = (1 << 17), /* Add VLAN tag */ 593 }; 594 595 /* 8169, 8168b and 810x except 8102e. */ 596 enum rtl_tx_desc_bit_0 { 597 /* First doubleword. */ 598 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 599 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 600 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 601 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 602 }; 603 604 /* 8102e, 8168c and beyond. */ 605 enum rtl_tx_desc_bit_1 { 606 /* First doubleword. */ 607 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 608 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 609 #define GTTCPHO_SHIFT 18 610 #define GTTCPHO_MAX 0x7f 611 612 /* Second doubleword. */ 613 #define TCPHO_SHIFT 18 614 #define TCPHO_MAX 0x3ff 615 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 616 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 617 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 618 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 619 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 620 }; 621 622 enum rtl_rx_desc_bit { 623 /* Rx private */ 624 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 625 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 626 627 #define RxProtoUDP (PID1) 628 #define RxProtoTCP (PID0) 629 #define RxProtoIP (PID1 | PID0) 630 #define RxProtoMask RxProtoIP 631 632 IPFail = (1 << 16), /* IP checksum failed */ 633 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 634 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 635 636 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 637 638 RxVlanTag = (1 << 16), /* VLAN tag available */ 639 }; 640 641 #define RTL_GSO_MAX_SIZE_V1 32000 642 #define RTL_GSO_MAX_SEGS_V1 24 643 #define RTL_GSO_MAX_SIZE_V2 64000 644 #define RTL_GSO_MAX_SEGS_V2 64 645 646 struct TxDesc { 647 __le32 opts1; 648 __le32 opts2; 649 __le64 addr; 650 }; 651 652 struct RxDesc { 653 __le32 opts1; 654 __le32 opts2; 655 __le64 addr; 656 }; 657 658 struct ring_info { 659 struct sk_buff *skb; 660 u32 len; 661 }; 662 663 struct rtl8169_counters { 664 __le64 tx_packets; 665 __le64 rx_packets; 666 __le64 tx_errors; 667 __le32 rx_errors; 668 __le16 rx_missed; 669 __le16 align_errors; 670 __le32 tx_one_collision; 671 __le32 tx_multi_collision; 672 __le64 rx_unicast; 673 __le64 rx_broadcast; 674 __le32 rx_multicast; 675 __le16 tx_aborted; 676 __le16 tx_underrun; 677 /* new since RTL8125 */ 678 __le64 tx_octets; 679 __le64 rx_octets; 680 __le64 rx_multicast64; 681 __le64 tx_unicast64; 682 __le64 tx_broadcast64; 683 __le64 tx_multicast64; 684 __le32 tx_pause_on; 685 __le32 tx_pause_off; 686 __le32 tx_pause_all; 687 __le32 tx_deferred; 688 __le32 tx_late_collision; 689 __le32 tx_all_collision; 690 __le32 tx_aborted32; 691 __le32 align_errors32; 692 __le32 rx_frame_too_long; 693 __le32 rx_runt; 694 __le32 rx_pause_on; 695 __le32 rx_pause_off; 696 __le32 rx_pause_all; 697 __le32 rx_unknown_opcode; 698 __le32 rx_mac_error; 699 __le32 tx_underrun32; 700 __le32 rx_mac_missed; 701 __le32 rx_tcam_dropped; 702 __le32 tdu; 703 __le32 rdu; 704 }; 705 706 struct rtl8169_tc_offsets { 707 bool inited; 708 __le64 tx_errors; 709 __le32 tx_multi_collision; 710 __le16 tx_aborted; 711 __le16 rx_missed; 712 }; 713 714 enum rtl_flag { 715 RTL_FLAG_TASK_RESET_PENDING, 716 RTL_FLAG_TASK_TX_TIMEOUT, 717 RTL_FLAG_MAX 718 }; 719 720 enum rtl_dash_type { 721 RTL_DASH_NONE, 722 RTL_DASH_DP, 723 RTL_DASH_EP, 724 RTL_DASH_25_BP, 725 }; 726 727 struct rtl8169_private { 728 void __iomem *mmio_addr; /* memory map physical address */ 729 struct pci_dev *pci_dev; 730 struct net_device *dev; 731 struct phy_device *phydev; 732 struct napi_struct napi; 733 enum mac_version mac_version; 734 enum rtl_dash_type dash_type; 735 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 736 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 737 u32 dirty_tx; 738 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 739 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 740 dma_addr_t TxPhyAddr; 741 dma_addr_t RxPhyAddr; 742 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 743 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 744 u16 cp_cmd; 745 u16 tx_lpi_timer; 746 u32 irq_mask; 747 int irq; 748 struct clk *clk; 749 750 struct { 751 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 752 struct work_struct work; 753 } wk; 754 755 raw_spinlock_t mac_ocp_lock; 756 struct mutex led_lock; /* serialize LED ctrl RMW access */ 757 758 unsigned supports_gmii:1; 759 unsigned aspm_manageable:1; 760 unsigned dash_enabled:1; 761 bool sfp_mode:1; 762 dma_addr_t counters_phys_addr; 763 struct rtl8169_counters *counters; 764 struct rtl8169_tc_offsets tc_offset; 765 u32 saved_wolopts; 766 767 const char *fw_name; 768 struct rtl_fw *rtl_fw; 769 770 struct r8169_led_classdev *leds; 771 772 u32 ocp_base; 773 }; 774 775 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 776 777 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 778 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 779 MODULE_SOFTDEP("pre: realtek"); 780 MODULE_LICENSE("GPL"); 781 MODULE_FIRMWARE(FIRMWARE_8168D_1); 782 MODULE_FIRMWARE(FIRMWARE_8168D_2); 783 MODULE_FIRMWARE(FIRMWARE_8168E_1); 784 MODULE_FIRMWARE(FIRMWARE_8168E_2); 785 MODULE_FIRMWARE(FIRMWARE_8168E_3); 786 MODULE_FIRMWARE(FIRMWARE_8105E_1); 787 MODULE_FIRMWARE(FIRMWARE_8168F_1); 788 MODULE_FIRMWARE(FIRMWARE_8168F_2); 789 MODULE_FIRMWARE(FIRMWARE_8402_1); 790 MODULE_FIRMWARE(FIRMWARE_8411_1); 791 MODULE_FIRMWARE(FIRMWARE_8411_2); 792 MODULE_FIRMWARE(FIRMWARE_8106E_1); 793 MODULE_FIRMWARE(FIRMWARE_8106E_2); 794 MODULE_FIRMWARE(FIRMWARE_8168G_2); 795 MODULE_FIRMWARE(FIRMWARE_8168G_3); 796 MODULE_FIRMWARE(FIRMWARE_8168H_2); 797 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 798 MODULE_FIRMWARE(FIRMWARE_8107E_2); 799 MODULE_FIRMWARE(FIRMWARE_8125A_3); 800 MODULE_FIRMWARE(FIRMWARE_8125B_2); 801 MODULE_FIRMWARE(FIRMWARE_8125D_1); 802 MODULE_FIRMWARE(FIRMWARE_8125D_2); 803 MODULE_FIRMWARE(FIRMWARE_8125K_1); 804 MODULE_FIRMWARE(FIRMWARE_8125BP_2); 805 MODULE_FIRMWARE(FIRMWARE_9151A_1); 806 MODULE_FIRMWARE(FIRMWARE_8126A_2); 807 MODULE_FIRMWARE(FIRMWARE_8126A_3); 808 MODULE_FIRMWARE(FIRMWARE_8127A_1); 809 810 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 811 { 812 return &tp->pci_dev->dev; 813 } 814 815 static void rtl_lock_config_regs(struct rtl8169_private *tp) 816 { 817 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 818 } 819 820 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 821 { 822 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 823 } 824 825 static void rtl_pci_commit(struct rtl8169_private *tp) 826 { 827 /* Read an arbitrary register to commit a preceding PCI write */ 828 RTL_R8(tp, ChipCmd); 829 } 830 831 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 832 { 833 u8 val; 834 835 val = RTL_R8(tp, Config2); 836 RTL_W8(tp, Config2, (val & ~clear) | set); 837 } 838 839 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 840 { 841 u8 val; 842 843 val = RTL_R8(tp, Config5); 844 RTL_W8(tp, Config5, (val & ~clear) | set); 845 } 846 847 static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg, 848 u8 bits, bool cond) 849 { 850 u8 val, old_val; 851 852 old_val = RTL_R8(tp, reg); 853 if (cond) 854 val = old_val | bits; 855 else 856 val = old_val & ~bits; 857 if (val != old_val) 858 RTL_W8(tp, reg, val); 859 } 860 861 static bool rtl_is_8125(struct rtl8169_private *tp) 862 { 863 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 864 } 865 866 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 867 { 868 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 869 tp->mac_version != RTL_GIGA_MAC_VER_39 && 870 tp->mac_version <= RTL_GIGA_MAC_VER_52; 871 } 872 873 static bool rtl_supports_eee(struct rtl8169_private *tp) 874 { 875 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 876 tp->mac_version != RTL_GIGA_MAC_VER_37 && 877 tp->mac_version != RTL_GIGA_MAC_VER_39; 878 } 879 880 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 881 { 882 int i; 883 884 for (i = 0; i < ETH_ALEN; i++) 885 mac[i] = RTL_R8(tp, reg + i); 886 } 887 888 struct rtl_cond { 889 bool (*check)(struct rtl8169_private *); 890 const char *msg; 891 }; 892 893 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 894 unsigned long usecs, int n, bool high) 895 { 896 int i; 897 898 for (i = 0; i < n; i++) { 899 if (c->check(tp) == high) 900 return true; 901 fsleep(usecs); 902 } 903 904 if (net_ratelimit()) 905 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 906 c->msg, !high, n, usecs); 907 return false; 908 } 909 910 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 911 const struct rtl_cond *c, 912 unsigned long d, int n) 913 { 914 return rtl_loop_wait(tp, c, d, n, true); 915 } 916 917 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 918 const struct rtl_cond *c, 919 unsigned long d, int n) 920 { 921 return rtl_loop_wait(tp, c, d, n, false); 922 } 923 924 #define DECLARE_RTL_COND(name) \ 925 static bool name ## _check(struct rtl8169_private *); \ 926 \ 927 static const struct rtl_cond name = { \ 928 .check = name ## _check, \ 929 .msg = #name \ 930 }; \ 931 \ 932 static bool name ## _check(struct rtl8169_private *tp) 933 934 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 935 { 936 struct device *dev = tp_to_dev(tp); 937 int ret; 938 939 ret = pm_runtime_resume_and_get(dev); 940 if (ret < 0) 941 return ret; 942 943 mutex_lock(&tp->led_lock); 944 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 945 mutex_unlock(&tp->led_lock); 946 947 pm_runtime_put_sync(dev); 948 949 return 0; 950 } 951 952 int rtl8168_get_led_mode(struct rtl8169_private *tp) 953 { 954 struct device *dev = tp_to_dev(tp); 955 int ret; 956 957 ret = pm_runtime_resume_and_get(dev); 958 if (ret < 0) 959 return ret; 960 961 ret = RTL_R16(tp, LED_CTRL); 962 963 pm_runtime_put_sync(dev); 964 965 return ret; 966 } 967 968 static int rtl8125_get_led_reg(int index) 969 { 970 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 971 972 return led_regs[index]; 973 } 974 975 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 976 { 977 int reg = rtl8125_get_led_reg(index); 978 struct device *dev = tp_to_dev(tp); 979 int ret; 980 u16 val; 981 982 ret = pm_runtime_resume_and_get(dev); 983 if (ret < 0) 984 return ret; 985 986 mutex_lock(&tp->led_lock); 987 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 988 RTL_W16(tp, reg, val | mode); 989 mutex_unlock(&tp->led_lock); 990 991 pm_runtime_put_sync(dev); 992 993 return 0; 994 } 995 996 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 997 { 998 int reg = rtl8125_get_led_reg(index); 999 struct device *dev = tp_to_dev(tp); 1000 int ret; 1001 1002 ret = pm_runtime_resume_and_get(dev); 1003 if (ret < 0) 1004 return ret; 1005 1006 ret = RTL_R16(tp, reg); 1007 1008 pm_runtime_put_sync(dev); 1009 1010 return ret; 1011 } 1012 1013 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 1014 char *buf, int buf_len) 1015 { 1016 struct pci_dev *pdev = tp->pci_dev; 1017 char pdom[8], pfun[8]; 1018 int domain; 1019 1020 domain = pci_domain_nr(pdev->bus); 1021 if (domain) 1022 snprintf(pdom, sizeof(pdom), "P%d", domain); 1023 else 1024 pdom[0] = '\0'; 1025 1026 if (pdev->multifunction) 1027 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 1028 else 1029 pfun[0] = '\0'; 1030 1031 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 1032 PCI_SLOT(pdev->devfn), pfun, idx); 1033 } 1034 1035 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 1036 { 1037 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 1038 if (type == ERIAR_OOB && tp->mac_version == RTL_GIGA_MAC_VER_52) 1039 *cmd |= 0xf70 << 18; 1040 } 1041 1042 DECLARE_RTL_COND(rtl_eriar_cond) 1043 { 1044 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1045 } 1046 1047 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1048 u32 val, int type) 1049 { 1050 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 1051 1052 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 1053 return; 1054 1055 RTL_W32(tp, ERIDR, val); 1056 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1057 RTL_W32(tp, ERIAR, cmd); 1058 1059 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1060 } 1061 1062 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1063 u32 val) 1064 { 1065 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1066 } 1067 1068 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1069 { 1070 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 1071 1072 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1073 RTL_W32(tp, ERIAR, cmd); 1074 1075 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1076 RTL_R32(tp, ERIDR) : ~0; 1077 } 1078 1079 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1080 { 1081 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1082 } 1083 1084 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 1085 { 1086 u32 val = rtl_eri_read(tp, addr); 1087 1088 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 1089 } 1090 1091 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1092 { 1093 rtl_w0w1_eri(tp, addr, p, 0); 1094 } 1095 1096 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1097 { 1098 rtl_w0w1_eri(tp, addr, 0, m); 1099 } 1100 1101 static bool rtl_ocp_reg_failure(u32 reg) 1102 { 1103 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1104 } 1105 1106 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1107 { 1108 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1109 } 1110 1111 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1112 { 1113 if (rtl_ocp_reg_failure(reg)) 1114 return; 1115 1116 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1117 1118 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1119 } 1120 1121 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1122 { 1123 if (rtl_ocp_reg_failure(reg)) 1124 return 0; 1125 1126 /* Return dummy MII_PHYSID2 in SFP mode to match SFP PHY driver */ 1127 if (tp->sfp_mode && reg == (OCP_STD_PHY_BASE + 2 * MII_PHYSID2)) 1128 return PHY_ID_RTL_DUMMY_SFP & 0xffff; 1129 1130 RTL_W32(tp, GPHY_OCP, reg << 15); 1131 1132 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1133 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1134 } 1135 1136 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1137 { 1138 if (rtl_ocp_reg_failure(reg)) 1139 return; 1140 1141 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1142 } 1143 1144 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1145 { 1146 unsigned long flags; 1147 1148 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1149 __r8168_mac_ocp_write(tp, reg, data); 1150 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1151 } 1152 1153 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1154 { 1155 if (rtl_ocp_reg_failure(reg)) 1156 return 0; 1157 1158 RTL_W32(tp, OCPDR, reg << 15); 1159 1160 return RTL_R32(tp, OCPDR); 1161 } 1162 1163 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1164 { 1165 unsigned long flags; 1166 u16 val; 1167 1168 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1169 val = __r8168_mac_ocp_read(tp, reg); 1170 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1171 1172 return val; 1173 } 1174 1175 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1176 u16 set) 1177 { 1178 unsigned long flags; 1179 u16 data; 1180 1181 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1182 data = __r8168_mac_ocp_read(tp, reg); 1183 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1184 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1185 } 1186 1187 static void r8127_sfp_sds_phy_reset(struct rtl8169_private *tp) 1188 { 1189 RTL_W8(tp, 0x2350, RTL_R8(tp, 0x2350) & ~BIT(0)); 1190 udelay(1); 1191 1192 RTL_W16(tp, 0x233a, 0x801f); 1193 RTL_W8(tp, 0x2350, RTL_R8(tp, 0x2350) | BIT(0)); 1194 usleep_range(10, 20); 1195 } 1196 1197 static void r8127_sfp_init_10g(struct rtl8169_private *tp) 1198 { 1199 int val; 1200 1201 r8127_sfp_sds_phy_reset(tp); 1202 1203 RTL_W16(tp, 0x233a, 0x801a); 1204 RTL_W16(tp, 0x233e, (RTL_R16(tp, 0x233e) & ~0x3003) | 0x1000); 1205 1206 r8168_phy_ocp_write(tp, 0xc40a, 0x0000); 1207 r8168_phy_ocp_write(tp, 0xc466, 0x0003); 1208 r8168_phy_ocp_write(tp, 0xc808, 0x0000); 1209 r8168_phy_ocp_write(tp, 0xc80a, 0x0000); 1210 1211 val = r8168_phy_ocp_read(tp, 0xc804); 1212 r8168_phy_ocp_write(tp, 0xc804, (val & ~0x000f) | 0x000c); 1213 } 1214 1215 static void rtl_sfp_init(struct rtl8169_private *tp) 1216 { 1217 if (tp->mac_version == RTL_GIGA_MAC_VER_80) 1218 r8127_sfp_init_10g(tp); 1219 } 1220 1221 static void rtl_sfp_reset(struct rtl8169_private *tp) 1222 { 1223 if (tp->mac_version == RTL_GIGA_MAC_VER_80) 1224 r8127_sfp_sds_phy_reset(tp); 1225 } 1226 1227 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1228 * PHY MCU interrupts before PHY power-down. 1229 */ 1230 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1231 { 1232 switch (tp->mac_version) { 1233 case RTL_GIGA_MAC_VER_40: 1234 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1235 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1236 else 1237 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1238 break; 1239 default: 1240 break; 1241 } 1242 }; 1243 1244 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1245 { 1246 if (reg == 0x1f) { 1247 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1248 return; 1249 } 1250 1251 if (tp->ocp_base != OCP_STD_PHY_BASE) 1252 reg -= 0x10; 1253 1254 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1255 rtl8168g_phy_suspend_quirk(tp, value); 1256 1257 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1258 } 1259 1260 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1261 { 1262 if (reg == 0x1f) 1263 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1264 1265 if (tp->ocp_base != OCP_STD_PHY_BASE) 1266 reg -= 0x10; 1267 1268 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1269 } 1270 1271 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1272 { 1273 if (reg == 0x1f) { 1274 tp->ocp_base = value << 4; 1275 return; 1276 } 1277 1278 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1279 } 1280 1281 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1282 { 1283 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1284 } 1285 1286 DECLARE_RTL_COND(rtl_phyar_cond) 1287 { 1288 return RTL_R32(tp, PHYAR) & 0x80000000; 1289 } 1290 1291 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1292 { 1293 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1294 1295 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1296 /* 1297 * According to hardware specs a 20us delay is required after write 1298 * complete indication, but before sending next command. 1299 */ 1300 udelay(20); 1301 } 1302 1303 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1304 { 1305 int value; 1306 1307 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1308 1309 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1310 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1311 1312 /* 1313 * According to hardware specs a 20us delay is required after read 1314 * complete indication, but before sending next command. 1315 */ 1316 udelay(20); 1317 1318 return value; 1319 } 1320 1321 DECLARE_RTL_COND(rtl_ocpar_cond) 1322 { 1323 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1324 } 1325 1326 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1327 1328 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1329 { 1330 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1331 } 1332 1333 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1334 { 1335 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1336 } 1337 1338 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1339 { 1340 r8168dp_2_mdio_start(tp); 1341 1342 r8169_mdio_write(tp, reg, value); 1343 1344 r8168dp_2_mdio_stop(tp); 1345 } 1346 1347 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1348 { 1349 int value; 1350 1351 /* Work around issue with chip reporting wrong PHY ID */ 1352 if (reg == MII_PHYSID2) 1353 return 0xc912; 1354 1355 r8168dp_2_mdio_start(tp); 1356 1357 value = r8169_mdio_read(tp, reg); 1358 1359 r8168dp_2_mdio_stop(tp); 1360 1361 return value; 1362 } 1363 1364 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1365 { 1366 switch (tp->mac_version) { 1367 case RTL_GIGA_MAC_VER_28: 1368 case RTL_GIGA_MAC_VER_31: 1369 r8168dp_2_mdio_write(tp, location, val); 1370 break; 1371 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 1372 r8168g_mdio_write(tp, location, val); 1373 break; 1374 default: 1375 r8169_mdio_write(tp, location, val); 1376 break; 1377 } 1378 } 1379 1380 static int rtl_readphy(struct rtl8169_private *tp, int location) 1381 { 1382 switch (tp->mac_version) { 1383 case RTL_GIGA_MAC_VER_28: 1384 case RTL_GIGA_MAC_VER_31: 1385 return r8168dp_2_mdio_read(tp, location); 1386 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 1387 return r8168g_mdio_read(tp, location); 1388 default: 1389 return r8169_mdio_read(tp, location); 1390 } 1391 } 1392 1393 DECLARE_RTL_COND(rtl_ephyar_cond) 1394 { 1395 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1396 } 1397 1398 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1399 { 1400 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1401 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1402 1403 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1404 1405 udelay(10); 1406 } 1407 1408 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1409 { 1410 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1411 1412 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1413 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1414 } 1415 1416 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1417 { 1418 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1419 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1420 RTL_R32(tp, OCPDR) : ~0; 1421 } 1422 1423 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1424 { 1425 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1426 } 1427 1428 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1429 u32 data) 1430 { 1431 RTL_W32(tp, OCPDR, data); 1432 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1433 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1434 } 1435 1436 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1437 u32 data) 1438 { 1439 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1440 data, ERIAR_OOB); 1441 } 1442 1443 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1444 { 1445 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1446 1447 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1448 } 1449 1450 #define OOB_CMD_RESET 0x00 1451 #define OOB_CMD_DRIVER_START 0x05 1452 #define OOB_CMD_DRIVER_STOP 0x06 1453 1454 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1455 { 1456 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1457 } 1458 1459 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1460 { 1461 u16 reg; 1462 1463 reg = rtl8168_get_ocp_reg(tp); 1464 1465 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1466 } 1467 1468 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1469 { 1470 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1471 } 1472 1473 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1474 { 1475 return RTL_R8(tp, IBISR0) & 0x20; 1476 } 1477 1478 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1479 { 1480 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1481 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1482 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1483 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1484 } 1485 1486 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1487 { 1488 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1489 if (tp->dash_enabled) 1490 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1491 } 1492 1493 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1494 { 1495 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1496 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1497 if (tp->dash_enabled) 1498 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1499 } 1500 1501 static void rtl8125bp_driver_start(struct rtl8169_private *tp) 1502 { 1503 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_START); 1504 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); 1505 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); 1506 } 1507 1508 static void rtl8168_driver_start(struct rtl8169_private *tp) 1509 { 1510 if (tp->dash_type == RTL_DASH_DP) 1511 rtl8168dp_driver_start(tp); 1512 else if (tp->dash_type == RTL_DASH_25_BP) 1513 rtl8125bp_driver_start(tp); 1514 else 1515 rtl8168ep_driver_start(tp); 1516 } 1517 1518 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1519 { 1520 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1521 if (tp->dash_enabled) 1522 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1523 } 1524 1525 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1526 { 1527 rtl8168ep_stop_cmac(tp); 1528 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1529 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1530 if (tp->dash_enabled) 1531 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1532 } 1533 1534 static void rtl8125bp_driver_stop(struct rtl8169_private *tp) 1535 { 1536 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_STOP); 1537 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); 1538 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); 1539 } 1540 1541 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1542 { 1543 if (tp->dash_type == RTL_DASH_DP) 1544 rtl8168dp_driver_stop(tp); 1545 else if (tp->dash_type == RTL_DASH_25_BP) 1546 rtl8125bp_driver_stop(tp); 1547 else 1548 rtl8168ep_driver_stop(tp); 1549 } 1550 1551 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1552 { 1553 u16 reg = rtl8168_get_ocp_reg(tp); 1554 1555 return r8168dp_ocp_read(tp, reg) & BIT(15); 1556 } 1557 1558 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1559 { 1560 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1561 } 1562 1563 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1564 { 1565 switch (tp->dash_type) { 1566 case RTL_DASH_DP: 1567 return r8168dp_check_dash(tp); 1568 case RTL_DASH_EP: 1569 case RTL_DASH_25_BP: 1570 return r8168ep_check_dash(tp); 1571 default: 1572 return false; 1573 } 1574 } 1575 1576 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1577 { 1578 switch (tp->mac_version) { 1579 case RTL_GIGA_MAC_VER_28: 1580 case RTL_GIGA_MAC_VER_31: 1581 return RTL_DASH_DP; 1582 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: 1583 return RTL_DASH_EP; 1584 case RTL_GIGA_MAC_VER_66: 1585 return RTL_DASH_25_BP; 1586 case RTL_GIGA_MAC_VER_80: 1587 return (tp->pci_dev->revision == 0x04) 1588 ? RTL_DASH_25_BP 1589 : RTL_DASH_NONE; 1590 default: 1591 return RTL_DASH_NONE; 1592 } 1593 } 1594 1595 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1596 { 1597 switch (tp->mac_version) { 1598 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_24: 1599 case RTL_GIGA_MAC_VER_28: 1600 case RTL_GIGA_MAC_VER_31: 1601 case RTL_GIGA_MAC_VER_38: 1602 break; 1603 case RTL_GIGA_MAC_VER_80: 1604 r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, true); 1605 break; 1606 default: 1607 r8169_mod_reg8_cond(tp, PMCH, D3HOT_NO_PLL_DOWN, true); 1608 r8169_mod_reg8_cond(tp, PMCH, D3COLD_NO_PLL_DOWN, !enable); 1609 break; 1610 } 1611 } 1612 1613 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1614 { 1615 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1616 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1617 } 1618 1619 DECLARE_RTL_COND(rtl_efusear_cond) 1620 { 1621 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1622 } 1623 1624 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1625 { 1626 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1627 1628 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1629 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1630 } 1631 1632 static u32 rtl_get_events(struct rtl8169_private *tp) 1633 { 1634 if (rtl_is_8125(tp)) 1635 return RTL_R32(tp, IntrStatus_8125); 1636 else 1637 return RTL_R16(tp, IntrStatus); 1638 } 1639 1640 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1641 { 1642 if (rtl_is_8125(tp)) 1643 RTL_W32(tp, IntrStatus_8125, bits); 1644 else 1645 RTL_W16(tp, IntrStatus, bits); 1646 } 1647 1648 static void rtl_irq_disable(struct rtl8169_private *tp) 1649 { 1650 if (rtl_is_8125(tp)) 1651 RTL_W32(tp, IntrMask_8125, 0); 1652 else 1653 RTL_W16(tp, IntrMask, 0); 1654 } 1655 1656 static void rtl_irq_enable(struct rtl8169_private *tp) 1657 { 1658 if (rtl_is_8125(tp)) 1659 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1660 else 1661 RTL_W16(tp, IntrMask, tp->irq_mask); 1662 } 1663 1664 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1665 { 1666 rtl_irq_disable(tp); 1667 rtl_ack_events(tp, 0xffffffff); 1668 rtl_pci_commit(tp); 1669 } 1670 1671 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1672 { 1673 struct phy_device *phydev = tp->phydev; 1674 1675 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1676 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1677 if (phydev->speed == SPEED_1000) { 1678 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1679 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1680 } else if (phydev->speed == SPEED_100) { 1681 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1682 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1683 } else { 1684 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1685 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1686 } 1687 rtl_reset_packet_filter(tp); 1688 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1689 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1690 if (phydev->speed == SPEED_1000) { 1691 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1692 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1693 } else { 1694 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1695 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1696 } 1697 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1698 if (phydev->speed == SPEED_10) { 1699 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1700 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1701 } else { 1702 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1703 } 1704 } 1705 } 1706 1707 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1708 1709 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1710 { 1711 struct rtl8169_private *tp = netdev_priv(dev); 1712 1713 wol->supported = WAKE_ANY; 1714 wol->wolopts = tp->saved_wolopts; 1715 } 1716 1717 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1718 { 1719 rtl_unlock_config_regs(tp); 1720 1721 if (rtl_is_8168evl_up(tp)) { 1722 if (wolopts & WAKE_MAGIC) 1723 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1724 else 1725 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1726 } else if (rtl_is_8125(tp)) { 1727 if (wolopts & WAKE_MAGIC) 1728 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1729 else 1730 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1731 } else { 1732 r8169_mod_reg8_cond(tp, Config3, MagicPacket, 1733 wolopts & WAKE_MAGIC); 1734 } 1735 1736 r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY); 1737 if (rtl_is_8125(tp)) 1738 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, 1739 wolopts & WAKE_PHY ? 0x13 : 0); 1740 r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST); 1741 r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST); 1742 r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST); 1743 r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts); 1744 1745 switch (tp->mac_version) { 1746 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1747 r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts); 1748 break; 1749 case RTL_GIGA_MAC_VER_34: 1750 case RTL_GIGA_MAC_VER_37: 1751 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_LAST: 1752 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); 1753 break; 1754 default: 1755 break; 1756 } 1757 1758 rtl_lock_config_regs(tp); 1759 1760 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1761 1762 if (!tp->dash_enabled) { 1763 rtl_set_d3_pll_down(tp, !wolopts); 1764 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1765 } 1766 } 1767 1768 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1769 { 1770 struct rtl8169_private *tp = netdev_priv(dev); 1771 1772 if (wol->wolopts & ~WAKE_ANY) 1773 return -EINVAL; 1774 1775 tp->saved_wolopts = wol->wolopts; 1776 __rtl8169_set_wol(tp, tp->saved_wolopts); 1777 1778 return 0; 1779 } 1780 1781 static void rtl8169_get_drvinfo(struct net_device *dev, 1782 struct ethtool_drvinfo *info) 1783 { 1784 struct rtl8169_private *tp = netdev_priv(dev); 1785 struct rtl_fw *rtl_fw = tp->rtl_fw; 1786 1787 strscpy(info->driver, KBUILD_MODNAME); 1788 strscpy(info->bus_info, pci_name(tp->pci_dev)); 1789 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1790 if (rtl_fw) 1791 strscpy(info->fw_version, rtl_fw->version); 1792 } 1793 1794 static int rtl8169_get_regs_len(struct net_device *dev) 1795 { 1796 return R8169_REGS_SIZE; 1797 } 1798 1799 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1800 netdev_features_t features) 1801 { 1802 struct rtl8169_private *tp = netdev_priv(dev); 1803 1804 if (dev->mtu > TD_MSS_MAX) 1805 features &= ~NETIF_F_ALL_TSO; 1806 1807 if (dev->mtu > ETH_DATA_LEN && 1808 tp->mac_version > RTL_GIGA_MAC_VER_06) 1809 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1810 1811 return features; 1812 } 1813 1814 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1815 netdev_features_t features) 1816 { 1817 u32 rx_config = RTL_R32(tp, RxConfig); 1818 1819 if (features & NETIF_F_RXALL) 1820 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1821 else 1822 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1823 1824 if (rtl_is_8125(tp)) { 1825 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1826 rx_config |= RX_VLAN_8125; 1827 else 1828 rx_config &= ~RX_VLAN_8125; 1829 } 1830 1831 RTL_W32(tp, RxConfig, rx_config); 1832 } 1833 1834 static int rtl8169_set_features(struct net_device *dev, 1835 netdev_features_t features) 1836 { 1837 struct rtl8169_private *tp = netdev_priv(dev); 1838 1839 rtl_set_rx_config_features(tp, features); 1840 1841 if (features & NETIF_F_RXCSUM) 1842 tp->cp_cmd |= RxChkSum; 1843 else 1844 tp->cp_cmd &= ~RxChkSum; 1845 1846 if (!rtl_is_8125(tp)) { 1847 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1848 tp->cp_cmd |= RxVlan; 1849 else 1850 tp->cp_cmd &= ~RxVlan; 1851 } 1852 1853 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1854 rtl_pci_commit(tp); 1855 1856 return 0; 1857 } 1858 1859 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1860 { 1861 return (skb_vlan_tag_present(skb)) ? 1862 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1863 } 1864 1865 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1866 { 1867 u32 opts2 = le32_to_cpu(desc->opts2); 1868 1869 if (opts2 & RxVlanTag) 1870 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1871 } 1872 1873 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1874 void *p) 1875 { 1876 struct rtl8169_private *tp = netdev_priv(dev); 1877 u32 __iomem *data = tp->mmio_addr; 1878 u32 *dw = p; 1879 int i; 1880 1881 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1882 memcpy_fromio(dw++, data++, 4); 1883 } 1884 1885 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1886 "tx_packets", 1887 "rx_packets", 1888 "tx_errors", 1889 "rx_errors", 1890 "rx_missed", 1891 "align_errors", 1892 "tx_single_collisions", 1893 "tx_multi_collisions", 1894 "unicast", 1895 "broadcast", 1896 "multicast", 1897 "tx_aborted", 1898 "tx_underrun", 1899 }; 1900 1901 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1902 { 1903 switch (sset) { 1904 case ETH_SS_STATS: 1905 return ARRAY_SIZE(rtl8169_gstrings); 1906 default: 1907 return -EOPNOTSUPP; 1908 } 1909 } 1910 1911 DECLARE_RTL_COND(rtl_counters_cond) 1912 { 1913 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1914 } 1915 1916 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1917 { 1918 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1919 1920 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1921 rtl_pci_commit(tp); 1922 RTL_W32(tp, CounterAddrLow, cmd); 1923 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1924 1925 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1926 } 1927 1928 static void rtl8169_update_counters(struct rtl8169_private *tp) 1929 { 1930 u8 val = RTL_R8(tp, ChipCmd); 1931 1932 /* 1933 * Some chips are unable to dump tally counters when the receiver 1934 * is disabled. If 0xff chip may be in a PCI power-save state. 1935 */ 1936 if (val & CmdRxEnb && val != 0xff) 1937 rtl8169_do_counters(tp, CounterDump); 1938 } 1939 1940 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1941 { 1942 struct rtl8169_counters *counters = tp->counters; 1943 1944 /* 1945 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1946 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1947 * reset by a power cycle, while the counter values collected by the 1948 * driver are reset at every driver unload/load cycle. 1949 * 1950 * To make sure the HW values returned by @get_stats64 match the SW 1951 * values, we collect the initial values at first open(*) and use them 1952 * as offsets to normalize the values returned by @get_stats64. 1953 * 1954 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1955 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1956 * set at open time by rtl_hw_start. 1957 */ 1958 1959 if (tp->tc_offset.inited) 1960 return; 1961 1962 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1963 rtl8169_do_counters(tp, CounterReset); 1964 } else { 1965 rtl8169_update_counters(tp); 1966 tp->tc_offset.tx_errors = counters->tx_errors; 1967 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1968 tp->tc_offset.tx_aborted = counters->tx_aborted; 1969 tp->tc_offset.rx_missed = counters->rx_missed; 1970 } 1971 1972 tp->tc_offset.inited = true; 1973 } 1974 1975 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1976 struct ethtool_stats *stats, u64 *data) 1977 { 1978 struct rtl8169_private *tp = netdev_priv(dev); 1979 struct rtl8169_counters *counters; 1980 1981 counters = tp->counters; 1982 rtl8169_update_counters(tp); 1983 1984 data[0] = le64_to_cpu(counters->tx_packets); 1985 data[1] = le64_to_cpu(counters->rx_packets); 1986 data[2] = le64_to_cpu(counters->tx_errors); 1987 data[3] = le32_to_cpu(counters->rx_errors); 1988 data[4] = le16_to_cpu(counters->rx_missed); 1989 data[5] = le16_to_cpu(counters->align_errors); 1990 data[6] = le32_to_cpu(counters->tx_one_collision); 1991 data[7] = le32_to_cpu(counters->tx_multi_collision); 1992 data[8] = le64_to_cpu(counters->rx_unicast); 1993 data[9] = le64_to_cpu(counters->rx_broadcast); 1994 data[10] = le32_to_cpu(counters->rx_multicast); 1995 data[11] = le16_to_cpu(counters->tx_aborted); 1996 data[12] = le16_to_cpu(counters->tx_underrun); 1997 } 1998 1999 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2000 { 2001 switch(stringset) { 2002 case ETH_SS_STATS: 2003 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 2004 break; 2005 } 2006 } 2007 2008 /* 2009 * Interrupt coalescing 2010 * 2011 * > 1 - the availability of the IntrMitigate (0xe2) register through the 2012 * > 8169, 8168 and 810x line of chipsets 2013 * 2014 * 8169, 8168, and 8136(810x) serial chipsets support it. 2015 * 2016 * > 2 - the Tx timer unit at gigabit speed 2017 * 2018 * The unit of the timer depends on both the speed and the setting of CPlusCmd 2019 * (0xe0) bit 1 and bit 0. 2020 * 2021 * For 8169 2022 * bit[1:0] \ speed 1000M 100M 10M 2023 * 0 0 320ns 2.56us 40.96us 2024 * 0 1 2.56us 20.48us 327.7us 2025 * 1 0 5.12us 40.96us 655.4us 2026 * 1 1 10.24us 81.92us 1.31ms 2027 * 2028 * For the other 2029 * bit[1:0] \ speed 1000M 100M 10M 2030 * 0 0 5us 2.56us 40.96us 2031 * 0 1 40us 20.48us 327.7us 2032 * 1 0 80us 40.96us 655.4us 2033 * 1 1 160us 81.92us 1.31ms 2034 */ 2035 2036 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 2037 struct rtl_coalesce_info { 2038 u32 speed; 2039 u32 scale_nsecs[4]; 2040 }; 2041 2042 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 2043 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 2044 2045 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 2046 { SPEED_1000, COALESCE_DELAY(320) }, 2047 { SPEED_100, COALESCE_DELAY(2560) }, 2048 { SPEED_10, COALESCE_DELAY(40960) }, 2049 { 0 }, 2050 }; 2051 2052 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 2053 { SPEED_1000, COALESCE_DELAY(5000) }, 2054 { SPEED_100, COALESCE_DELAY(2560) }, 2055 { SPEED_10, COALESCE_DELAY(40960) }, 2056 { 0 }, 2057 }; 2058 #undef COALESCE_DELAY 2059 2060 /* get rx/tx scale vector corresponding to current speed */ 2061 static const struct rtl_coalesce_info * 2062 rtl_coalesce_info(struct rtl8169_private *tp) 2063 { 2064 const struct rtl_coalesce_info *ci; 2065 2066 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 2067 ci = rtl_coalesce_info_8169; 2068 else 2069 ci = rtl_coalesce_info_8168_8136; 2070 2071 /* if speed is unknown assume highest one */ 2072 if (tp->phydev->speed == SPEED_UNKNOWN) 2073 return ci; 2074 2075 for (; ci->speed; ci++) { 2076 if (tp->phydev->speed == ci->speed) 2077 return ci; 2078 } 2079 2080 return ERR_PTR(-ELNRNG); 2081 } 2082 2083 static int rtl_get_coalesce(struct net_device *dev, 2084 struct ethtool_coalesce *ec, 2085 struct kernel_ethtool_coalesce *kernel_coal, 2086 struct netlink_ext_ack *extack) 2087 { 2088 struct rtl8169_private *tp = netdev_priv(dev); 2089 const struct rtl_coalesce_info *ci; 2090 u32 scale, c_us, c_fr; 2091 u16 intrmit; 2092 2093 if (rtl_is_8125(tp)) 2094 return -EOPNOTSUPP; 2095 2096 memset(ec, 0, sizeof(*ec)); 2097 2098 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 2099 ci = rtl_coalesce_info(tp); 2100 if (IS_ERR(ci)) 2101 return PTR_ERR(ci); 2102 2103 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 2104 2105 intrmit = RTL_R16(tp, IntrMitigate); 2106 2107 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 2108 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 2109 2110 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 2111 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 2112 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 2113 2114 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 2115 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 2116 2117 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 2118 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 2119 2120 return 0; 2121 } 2122 2123 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 2124 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 2125 u16 *cp01) 2126 { 2127 const struct rtl_coalesce_info *ci; 2128 u16 i; 2129 2130 ci = rtl_coalesce_info(tp); 2131 if (IS_ERR(ci)) 2132 return PTR_ERR(ci); 2133 2134 for (i = 0; i < 4; i++) { 2135 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 2136 *cp01 = i; 2137 return ci->scale_nsecs[i]; 2138 } 2139 } 2140 2141 return -ERANGE; 2142 } 2143 2144 static int rtl_set_coalesce(struct net_device *dev, 2145 struct ethtool_coalesce *ec, 2146 struct kernel_ethtool_coalesce *kernel_coal, 2147 struct netlink_ext_ack *extack) 2148 { 2149 struct rtl8169_private *tp = netdev_priv(dev); 2150 u32 tx_fr = ec->tx_max_coalesced_frames; 2151 u32 rx_fr = ec->rx_max_coalesced_frames; 2152 u32 coal_usec_max, units; 2153 u16 w = 0, cp01 = 0; 2154 int scale; 2155 2156 if (rtl_is_8125(tp)) 2157 return -EOPNOTSUPP; 2158 2159 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 2160 return -ERANGE; 2161 2162 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 2163 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 2164 if (scale < 0) 2165 return scale; 2166 2167 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 2168 * not only when usecs=0 because of e.g. the following scenario: 2169 * 2170 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2171 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2172 * - then user does `ethtool -C eth0 rx-usecs 100` 2173 * 2174 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2175 * if we want to ignore rx_frames then it has to be set to 0. 2176 */ 2177 if (rx_fr == 1) 2178 rx_fr = 0; 2179 if (tx_fr == 1) 2180 tx_fr = 0; 2181 2182 /* HW requires time limit to be set if frame limit is set */ 2183 if ((tx_fr && !ec->tx_coalesce_usecs) || 2184 (rx_fr && !ec->rx_coalesce_usecs)) 2185 return -EINVAL; 2186 2187 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2188 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2189 2190 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2191 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2192 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2193 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2194 2195 RTL_W16(tp, IntrMitigate, w); 2196 2197 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2198 if (rtl_is_8168evl_up(tp)) { 2199 if (!rx_fr && !tx_fr) 2200 /* disable packet counter */ 2201 tp->cp_cmd |= PktCntrDisable; 2202 else 2203 tp->cp_cmd &= ~PktCntrDisable; 2204 } 2205 2206 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2207 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2208 rtl_pci_commit(tp); 2209 2210 return 0; 2211 } 2212 2213 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2214 { 2215 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2216 2217 switch (tp->mac_version) { 2218 case RTL_GIGA_MAC_VER_46: 2219 case RTL_GIGA_MAC_VER_48: 2220 tp->tx_lpi_timer = timer_val; 2221 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2222 break; 2223 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 2224 tp->tx_lpi_timer = timer_val; 2225 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2226 break; 2227 default: 2228 break; 2229 } 2230 } 2231 2232 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2233 { 2234 unsigned int speed = tp->phydev->speed; 2235 unsigned int timer = tp->tx_lpi_timer; 2236 2237 if (!timer || speed == SPEED_UNKNOWN) 2238 return 0; 2239 2240 /* tx_lpi_timer value is in bytes */ 2241 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2242 } 2243 2244 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2245 { 2246 struct rtl8169_private *tp = netdev_priv(dev); 2247 int ret; 2248 2249 if (!rtl_supports_eee(tp)) 2250 return -EOPNOTSUPP; 2251 2252 ret = phy_ethtool_get_eee(tp->phydev, data); 2253 if (ret) 2254 return ret; 2255 2256 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2257 2258 return 0; 2259 } 2260 2261 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2262 { 2263 struct rtl8169_private *tp = netdev_priv(dev); 2264 2265 if (!rtl_supports_eee(tp)) 2266 return -EOPNOTSUPP; 2267 2268 return phy_ethtool_set_eee(tp->phydev, data); 2269 } 2270 2271 static void rtl8169_get_ringparam(struct net_device *dev, 2272 struct ethtool_ringparam *data, 2273 struct kernel_ethtool_ringparam *kernel_data, 2274 struct netlink_ext_ack *extack) 2275 { 2276 data->rx_max_pending = NUM_RX_DESC; 2277 data->rx_pending = NUM_RX_DESC; 2278 data->tx_max_pending = NUM_TX_DESC; 2279 data->tx_pending = NUM_TX_DESC; 2280 } 2281 2282 static void rtl8169_get_pause_stats(struct net_device *dev, 2283 struct ethtool_pause_stats *pause_stats) 2284 { 2285 struct rtl8169_private *tp = netdev_priv(dev); 2286 2287 if (!rtl_is_8125(tp)) 2288 return; 2289 2290 rtl8169_update_counters(tp); 2291 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on); 2292 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on); 2293 } 2294 2295 static void rtl8169_get_pauseparam(struct net_device *dev, 2296 struct ethtool_pauseparam *data) 2297 { 2298 struct rtl8169_private *tp = netdev_priv(dev); 2299 bool tx_pause, rx_pause; 2300 2301 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2302 2303 data->autoneg = tp->phydev->autoneg; 2304 data->tx_pause = tx_pause ? 1 : 0; 2305 data->rx_pause = rx_pause ? 1 : 0; 2306 } 2307 2308 static int rtl8169_set_pauseparam(struct net_device *dev, 2309 struct ethtool_pauseparam *data) 2310 { 2311 struct rtl8169_private *tp = netdev_priv(dev); 2312 2313 if (dev->mtu > ETH_DATA_LEN) 2314 return -EOPNOTSUPP; 2315 2316 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2317 2318 return 0; 2319 } 2320 2321 static void rtl8169_get_eth_mac_stats(struct net_device *dev, 2322 struct ethtool_eth_mac_stats *mac_stats) 2323 { 2324 struct rtl8169_private *tp = netdev_priv(dev); 2325 2326 rtl8169_update_counters(tp); 2327 2328 mac_stats->FramesTransmittedOK = 2329 le64_to_cpu(tp->counters->tx_packets); 2330 mac_stats->SingleCollisionFrames = 2331 le32_to_cpu(tp->counters->tx_one_collision); 2332 mac_stats->MultipleCollisionFrames = 2333 le32_to_cpu(tp->counters->tx_multi_collision); 2334 mac_stats->FramesReceivedOK = 2335 le64_to_cpu(tp->counters->rx_packets); 2336 mac_stats->AlignmentErrors = 2337 le16_to_cpu(tp->counters->align_errors); 2338 mac_stats->FramesLostDueToIntMACXmitError = 2339 le64_to_cpu(tp->counters->tx_errors); 2340 mac_stats->BroadcastFramesReceivedOK = 2341 le64_to_cpu(tp->counters->rx_broadcast); 2342 mac_stats->MulticastFramesReceivedOK = 2343 le32_to_cpu(tp->counters->rx_multicast); 2344 2345 if (!rtl_is_8125(tp)) 2346 return; 2347 2348 mac_stats->AlignmentErrors = 2349 le32_to_cpu(tp->counters->align_errors32); 2350 mac_stats->OctetsTransmittedOK = 2351 le64_to_cpu(tp->counters->tx_octets); 2352 mac_stats->LateCollisions = 2353 le32_to_cpu(tp->counters->tx_late_collision); 2354 mac_stats->FramesAbortedDueToXSColls = 2355 le32_to_cpu(tp->counters->tx_aborted32); 2356 mac_stats->OctetsReceivedOK = 2357 le64_to_cpu(tp->counters->rx_octets); 2358 mac_stats->FramesLostDueToIntMACRcvError = 2359 le32_to_cpu(tp->counters->rx_mac_error); 2360 mac_stats->MulticastFramesXmittedOK = 2361 le64_to_cpu(tp->counters->tx_multicast64); 2362 mac_stats->BroadcastFramesXmittedOK = 2363 le64_to_cpu(tp->counters->tx_broadcast64); 2364 mac_stats->MulticastFramesReceivedOK = 2365 le64_to_cpu(tp->counters->rx_multicast64); 2366 mac_stats->FrameTooLongErrors = 2367 le32_to_cpu(tp->counters->rx_frame_too_long); 2368 } 2369 2370 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, 2371 struct ethtool_eth_ctrl_stats *ctrl_stats) 2372 { 2373 struct rtl8169_private *tp = netdev_priv(dev); 2374 2375 if (!rtl_is_8125(tp)) 2376 return; 2377 2378 rtl8169_update_counters(tp); 2379 2380 ctrl_stats->UnsupportedOpcodesReceived = 2381 le32_to_cpu(tp->counters->rx_unknown_opcode); 2382 } 2383 2384 static int rtl8169_set_link_ksettings(struct net_device *ndev, 2385 const struct ethtool_link_ksettings *cmd) 2386 { 2387 struct rtl8169_private *tp = netdev_priv(ndev); 2388 struct phy_device *phydev = tp->phydev; 2389 int duplex = cmd->base.duplex; 2390 int speed = cmd->base.speed; 2391 2392 if (!tp->sfp_mode) 2393 return phy_ethtool_ksettings_set(phydev, cmd); 2394 2395 if (cmd->base.autoneg != AUTONEG_DISABLE) 2396 return -EINVAL; 2397 2398 if (!phy_check_valid(speed, duplex, phydev->supported)) 2399 return -EINVAL; 2400 2401 mutex_lock(&phydev->lock); 2402 2403 phydev->autoneg = AUTONEG_DISABLE; 2404 phydev->speed = speed; 2405 phydev->duplex = duplex; 2406 2407 rtl_sfp_init(tp); 2408 2409 mutex_unlock(&phydev->lock); 2410 2411 return 0; 2412 } 2413 2414 static const struct ethtool_ops rtl8169_ethtool_ops = { 2415 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2416 ETHTOOL_COALESCE_MAX_FRAMES, 2417 .get_drvinfo = rtl8169_get_drvinfo, 2418 .get_regs_len = rtl8169_get_regs_len, 2419 .get_link = ethtool_op_get_link, 2420 .get_coalesce = rtl_get_coalesce, 2421 .set_coalesce = rtl_set_coalesce, 2422 .get_regs = rtl8169_get_regs, 2423 .get_wol = rtl8169_get_wol, 2424 .set_wol = rtl8169_set_wol, 2425 .get_strings = rtl8169_get_strings, 2426 .get_sset_count = rtl8169_get_sset_count, 2427 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2428 .get_ts_info = ethtool_op_get_ts_info, 2429 .nway_reset = phy_ethtool_nway_reset, 2430 .get_eee = rtl8169_get_eee, 2431 .set_eee = rtl8169_set_eee, 2432 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2433 .set_link_ksettings = rtl8169_set_link_ksettings, 2434 .get_ringparam = rtl8169_get_ringparam, 2435 .get_pause_stats = rtl8169_get_pause_stats, 2436 .get_pauseparam = rtl8169_get_pauseparam, 2437 .set_pauseparam = rtl8169_set_pauseparam, 2438 .get_eth_mac_stats = rtl8169_get_eth_mac_stats, 2439 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, 2440 }; 2441 2442 static const struct rtl_chip_info *rtl8169_get_chip_version(u32 xid, bool gmii) 2443 { 2444 /* Chips combining a 1Gbps MAC with a 100Mbps PHY */ 2445 static const struct rtl_chip_info rtl8106eus_info = { 2446 .mac_version = RTL_GIGA_MAC_VER_43, 2447 .name = "RTL8106eus", 2448 .fw_name = FIRMWARE_8106E_2, 2449 }; 2450 static const struct rtl_chip_info rtl8107e_info = { 2451 .mac_version = RTL_GIGA_MAC_VER_48, 2452 .name = "RTL8107e", 2453 .fw_name = FIRMWARE_8107E_2, 2454 }; 2455 const struct rtl_chip_info *p = rtl_chip_infos; 2456 2457 while ((xid & p->mask) != p->val) 2458 p++; 2459 2460 if (p->mac_version == RTL_GIGA_MAC_VER_42 && !gmii) 2461 return &rtl8106eus_info; 2462 if (p->mac_version == RTL_GIGA_MAC_VER_46 && !gmii) 2463 return &rtl8107e_info; 2464 2465 return p; 2466 } 2467 2468 static const struct rtl_chip_info *rtl8169_get_extended_chip_version(u32 xid2) 2469 { 2470 const struct rtl_chip_info *p = rtl_chip_infos_extended; 2471 2472 while ((xid2 & p->mask) != p->val) 2473 p++; 2474 return p; 2475 } 2476 2477 static void rtl_release_firmware(struct rtl8169_private *tp) 2478 { 2479 if (tp->rtl_fw) { 2480 rtl_fw_release_firmware(tp->rtl_fw); 2481 kfree(tp->rtl_fw); 2482 tp->rtl_fw = NULL; 2483 } 2484 } 2485 2486 void r8169_apply_firmware(struct rtl8169_private *tp) 2487 { 2488 int val; 2489 2490 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2491 if (tp->rtl_fw) { 2492 rtl_fw_write_firmware(tp, tp->rtl_fw); 2493 /* At least one firmware doesn't reset tp->ocp_base. */ 2494 tp->ocp_base = OCP_STD_PHY_BASE; 2495 2496 /* PHY soft reset may still be in progress */ 2497 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2498 !(val & BMCR_RESET), 2499 50000, 600000, true); 2500 } 2501 } 2502 2503 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2504 { 2505 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2506 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2507 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2508 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2509 } 2510 2511 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2512 { 2513 u16 data1, data2, ioffset; 2514 2515 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2516 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2517 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2518 2519 ioffset = (data2 >> 1) & 0x7ff8; 2520 ioffset |= data2 & 0x0007; 2521 if (data1 & BIT(7)) 2522 ioffset |= BIT(15); 2523 2524 return ioffset; 2525 } 2526 2527 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2528 { 2529 set_bit(flag, tp->wk.flags); 2530 if (!schedule_work(&tp->wk.work)) 2531 clear_bit(flag, tp->wk.flags); 2532 } 2533 2534 static void rtl8169_init_phy(struct rtl8169_private *tp) 2535 { 2536 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2537 2538 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2539 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2540 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2541 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2542 RTL_W8(tp, 0x82, 0x01); 2543 } 2544 2545 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2546 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2547 tp->pci_dev->subsystem_device == 0xe000) 2548 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2549 2550 if (tp->sfp_mode) 2551 rtl_sfp_init(tp); 2552 2553 /* We may have called phy_speed_down before */ 2554 phy_speed_up(tp->phydev); 2555 2556 genphy_soft_reset(tp->phydev); 2557 } 2558 2559 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2560 { 2561 rtl_unlock_config_regs(tp); 2562 2563 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2564 rtl_pci_commit(tp); 2565 2566 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2567 rtl_pci_commit(tp); 2568 2569 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2570 rtl_rar_exgmac_set(tp, addr); 2571 2572 rtl_lock_config_regs(tp); 2573 } 2574 2575 static int rtl_set_mac_address(struct net_device *dev, void *p) 2576 { 2577 struct rtl8169_private *tp = netdev_priv(dev); 2578 int ret; 2579 2580 ret = eth_mac_addr(dev, p); 2581 if (ret) 2582 return ret; 2583 2584 rtl_rar_set(tp, dev->dev_addr); 2585 2586 return 0; 2587 } 2588 2589 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2590 { 2591 switch (tp->mac_version) { 2592 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2593 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2594 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2595 break; 2596 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2597 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2598 case RTL_GIGA_MAC_VER_38: 2599 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2600 break; 2601 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2602 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2603 break; 2604 case RTL_GIGA_MAC_VER_61: 2605 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2606 break; 2607 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 2608 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2609 RX_PAUSE_SLOT_ON); 2610 break; 2611 default: 2612 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2613 break; 2614 } 2615 } 2616 2617 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2618 { 2619 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2620 } 2621 2622 static void rtl_jumbo_config(struct rtl8169_private *tp) 2623 { 2624 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2625 int readrq = 4096; 2626 2627 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 && 2628 tp->mac_version <= RTL_GIGA_MAC_VER_26) 2629 readrq = 512; 2630 2631 rtl_unlock_config_regs(tp); 2632 switch (tp->mac_version) { 2633 case RTL_GIGA_MAC_VER_17: 2634 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2635 break; 2636 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2637 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2638 r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo); 2639 break; 2640 case RTL_GIGA_MAC_VER_28: 2641 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2642 break; 2643 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2644 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); 2645 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2646 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2647 break; 2648 default: 2649 break; 2650 } 2651 rtl_lock_config_regs(tp); 2652 2653 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2654 pcie_set_readrq(tp->pci_dev, readrq); 2655 2656 /* Chip doesn't support pause in jumbo mode */ 2657 if (jumbo) { 2658 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2659 tp->phydev->advertising); 2660 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2661 tp->phydev->advertising); 2662 phy_start_aneg(tp->phydev); 2663 } 2664 } 2665 2666 DECLARE_RTL_COND(rtl_chipcmd_cond) 2667 { 2668 return RTL_R8(tp, ChipCmd) & CmdReset; 2669 } 2670 2671 static void rtl_hw_reset(struct rtl8169_private *tp) 2672 { 2673 RTL_W8(tp, ChipCmd, CmdReset); 2674 2675 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2676 } 2677 2678 static void rtl_request_firmware(struct rtl8169_private *tp) 2679 { 2680 struct rtl_fw *rtl_fw; 2681 2682 /* firmware loaded already or no firmware available */ 2683 if (tp->rtl_fw || !tp->fw_name) 2684 return; 2685 2686 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2687 if (!rtl_fw) 2688 return; 2689 2690 rtl_fw->phy_write = rtl_writephy; 2691 rtl_fw->phy_read = rtl_readphy; 2692 rtl_fw->mac_mcu_write = mac_mcu_write; 2693 rtl_fw->mac_mcu_read = mac_mcu_read; 2694 rtl_fw->fw_name = tp->fw_name; 2695 rtl_fw->dev = tp_to_dev(tp); 2696 2697 if (rtl_fw_request_firmware(rtl_fw)) 2698 kfree(rtl_fw); 2699 else 2700 tp->rtl_fw = rtl_fw; 2701 } 2702 2703 static void rtl_rx_close(struct rtl8169_private *tp) 2704 { 2705 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2706 } 2707 2708 DECLARE_RTL_COND(rtl_npq_cond) 2709 { 2710 return RTL_R8(tp, TxPoll) & NPQ; 2711 } 2712 2713 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2714 { 2715 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2716 } 2717 2718 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2719 { 2720 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2721 } 2722 2723 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2724 { 2725 /* IntrMitigate has new functionality on RTL8125 */ 2726 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2727 } 2728 2729 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2730 { 2731 switch (tp->mac_version) { 2732 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2733 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2734 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2735 break; 2736 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2737 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2738 break; 2739 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 2740 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2741 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2742 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2743 break; 2744 default: 2745 break; 2746 } 2747 } 2748 2749 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2750 { 2751 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2752 } 2753 2754 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2755 { 2756 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2757 fsleep(2000); 2758 rtl_wait_txrx_fifo_empty(tp); 2759 } 2760 2761 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2762 { 2763 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2764 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2765 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2766 2767 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2768 rtl_disable_rxdvgate(tp); 2769 } 2770 2771 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2772 { 2773 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2774 tp->mac_version == RTL_GIGA_MAC_VER_33) 2775 rtl_ephy_write(tp, 0x19, 0xff64); 2776 2777 if (device_may_wakeup(tp_to_dev(tp))) { 2778 phy_speed_down(tp->phydev, false); 2779 rtl_wol_enable_rx(tp); 2780 } 2781 } 2782 2783 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2784 { 2785 u32 val = TX_DMA_BURST << TxDMAShift | 2786 InterFrameGap << TxInterFrameGapShift; 2787 2788 if (rtl_is_8168evl_up(tp)) 2789 val |= TXCFG_AUTO_FIFO; 2790 2791 RTL_W32(tp, TxConfig, val); 2792 } 2793 2794 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2795 { 2796 /* Low hurts. Let's disable the filtering. */ 2797 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2798 } 2799 2800 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2801 { 2802 /* 2803 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2804 * register to be written before TxDescAddrLow to work. 2805 * Switching from MMIO to I/O access fixes the issue as well. 2806 */ 2807 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2808 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2809 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2810 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2811 } 2812 2813 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2814 { 2815 u32 val; 2816 2817 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2818 val = 0x000fff00; 2819 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2820 val = 0x00ffff00; 2821 else 2822 return; 2823 2824 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2825 val |= 0xff; 2826 2827 RTL_W32(tp, 0x7c, val); 2828 } 2829 2830 static void rtl_set_rx_mode(struct net_device *dev) 2831 { 2832 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2833 /* Multicast hash filter */ 2834 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2835 struct rtl8169_private *tp = netdev_priv(dev); 2836 u32 tmp; 2837 2838 if (dev->flags & IFF_PROMISC) { 2839 rx_mode |= AcceptAllPhys; 2840 } else if (!(dev->flags & IFF_MULTICAST)) { 2841 rx_mode &= ~AcceptMulticast; 2842 } else if (dev->flags & IFF_ALLMULTI || 2843 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2844 /* accept all multicasts */ 2845 } else if (netdev_mc_empty(dev)) { 2846 rx_mode &= ~AcceptMulticast; 2847 } else { 2848 struct netdev_hw_addr *ha; 2849 2850 mc_filter[1] = mc_filter[0] = 0; 2851 netdev_for_each_mc_addr(ha, dev) { 2852 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2853 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2854 } 2855 2856 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2857 tmp = mc_filter[0]; 2858 mc_filter[0] = swab32(mc_filter[1]); 2859 mc_filter[1] = swab32(tmp); 2860 } 2861 } 2862 2863 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2864 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2865 2866 tmp = RTL_R32(tp, RxConfig); 2867 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2868 } 2869 2870 DECLARE_RTL_COND(rtl_csiar_cond) 2871 { 2872 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2873 } 2874 2875 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2876 { 2877 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2878 2879 RTL_W32(tp, CSIDR, value); 2880 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2881 CSIAR_BYTE_ENABLE | func << 16); 2882 2883 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2884 } 2885 2886 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2887 { 2888 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2889 2890 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2891 CSIAR_BYTE_ENABLE); 2892 2893 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2894 RTL_R32(tp, CSIDR) : ~0; 2895 } 2896 2897 static void rtl_csi_mod(struct rtl8169_private *tp, int addr, 2898 u32 mask, u32 set) 2899 { 2900 u32 val; 2901 2902 WARN(addr % 4, "Invalid CSI address %#x\n", addr); 2903 2904 netdev_notice_once(tp->dev, 2905 "No native access to PCI extended config space, falling back to CSI\n"); 2906 2907 val = rtl_csi_read(tp, addr); 2908 rtl_csi_write(tp, addr, (val & ~mask) | set); 2909 } 2910 2911 static void rtl_disable_zrxdc_timeout(struct rtl8169_private *tp) 2912 { 2913 struct pci_dev *pdev = tp->pci_dev; 2914 int rc; 2915 u8 val; 2916 2917 #define RTL_GEN3_RELATED_OFF 0x0890 2918 #define RTL_GEN3_ZRXDC_NONCOMPL 0x1 2919 if (pdev->cfg_size > RTL_GEN3_RELATED_OFF) { 2920 rc = pci_read_config_byte(pdev, RTL_GEN3_RELATED_OFF, &val); 2921 if (rc == PCIBIOS_SUCCESSFUL) { 2922 val &= ~RTL_GEN3_ZRXDC_NONCOMPL; 2923 rc = pci_write_config_byte(pdev, RTL_GEN3_RELATED_OFF, 2924 val); 2925 if (rc == PCIBIOS_SUCCESSFUL) 2926 return; 2927 } 2928 } 2929 2930 rtl_csi_mod(tp, RTL_GEN3_RELATED_OFF, RTL_GEN3_ZRXDC_NONCOMPL, 0); 2931 } 2932 2933 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2934 { 2935 struct pci_dev *pdev = tp->pci_dev; 2936 2937 /* According to Realtek the value at config space address 0x070f 2938 * controls the L0s/L1 entrance latency. We try standard ECAM access 2939 * first and if it fails fall back to CSI. 2940 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2941 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2942 */ 2943 if (pdev->cfg_size > 0x070f && 2944 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2945 return; 2946 2947 rtl_csi_mod(tp, 0x070c, 0xff000000, val << 24); 2948 } 2949 2950 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2951 { 2952 /* L0 7us, L1 16us */ 2953 rtl_set_aspm_entry_latency(tp, 0x27); 2954 } 2955 2956 struct ephy_info { 2957 unsigned int offset; 2958 u16 mask; 2959 u16 bits; 2960 }; 2961 2962 static void __rtl_ephy_init(struct rtl8169_private *tp, 2963 const struct ephy_info *e, int len) 2964 { 2965 u16 w; 2966 2967 while (len-- > 0) { 2968 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2969 rtl_ephy_write(tp, e->offset, w); 2970 e++; 2971 } 2972 } 2973 2974 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2975 2976 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2977 { 2978 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2979 PCI_EXP_LNKCTL_CLKREQ_EN); 2980 } 2981 2982 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2983 { 2984 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2985 PCI_EXP_LNKCTL_CLKREQ_EN); 2986 } 2987 2988 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2989 { 2990 /* work around an issue when PCI reset occurs during L2/L3 state */ 2991 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2992 } 2993 2994 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2995 { 2996 /* Bits control which events trigger ASPM L1 exit: 2997 * Bit 12: rxdv 2998 * Bit 11: ltr_msg 2999 * Bit 10: txdma_poll 3000 * Bit 9: xadm 3001 * Bit 8: pktavi 3002 * Bit 7: txpla 3003 */ 3004 switch (tp->mac_version) { 3005 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 3006 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3007 break; 3008 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 3009 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 3010 break; 3011 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 3012 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 3013 break; 3014 default: 3015 break; 3016 } 3017 } 3018 3019 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 3020 { 3021 switch (tp->mac_version) { 3022 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3023 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 3024 break; 3025 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 3026 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 3027 break; 3028 default: 3029 break; 3030 } 3031 } 3032 3033 static void rtl_enable_ltr(struct rtl8169_private *tp) 3034 { 3035 switch (tp->mac_version) { 3036 case RTL_GIGA_MAC_VER_80: 3037 r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); 3038 r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); 3039 r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); 3040 r8168_mac_ocp_write(tp, 0xcdd2, 0x8c09); 3041 r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); 3042 r8168_mac_ocp_write(tp, 0xcdd4, 0x9003); 3043 r8168_mac_ocp_write(tp, 0xcdda, 0x9003); 3044 r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); 3045 r8168_mac_ocp_write(tp, 0xcddc, 0x9003); 3046 r8168_mac_ocp_write(tp, 0xcde8, 0x887a); 3047 r8168_mac_ocp_write(tp, 0xcdea, 0x9003); 3048 r8168_mac_ocp_write(tp, 0xcdec, 0x8c09); 3049 r8168_mac_ocp_write(tp, 0xcdee, 0x9003); 3050 r8168_mac_ocp_write(tp, 0xcdf0, 0x8a62); 3051 r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); 3052 r8168_mac_ocp_write(tp, 0xcdf4, 0x883e); 3053 r8168_mac_ocp_write(tp, 0xcdf6, 0x9003); 3054 r8168_mac_ocp_write(tp, 0xcdf8, 0x8849); 3055 r8168_mac_ocp_write(tp, 0xcdfa, 0x9003); 3056 r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN); 3057 break; 3058 case RTL_GIGA_MAC_VER_70: 3059 r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); 3060 r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); 3061 r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); 3062 r8168_mac_ocp_write(tp, 0xcdd2, 0x8c09); 3063 r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); 3064 r8168_mac_ocp_write(tp, 0xcdd4, 0x9003); 3065 r8168_mac_ocp_write(tp, 0xcdda, 0x9003); 3066 r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); 3067 r8168_mac_ocp_write(tp, 0xcddc, 0x9003); 3068 r8168_mac_ocp_write(tp, 0xcde8, 0x887a); 3069 r8168_mac_ocp_write(tp, 0xcdea, 0x9003); 3070 r8168_mac_ocp_write(tp, 0xcdec, 0x8c09); 3071 r8168_mac_ocp_write(tp, 0xcdee, 0x9003); 3072 r8168_mac_ocp_write(tp, 0xcdf0, 0x8a62); 3073 r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); 3074 r8168_mac_ocp_write(tp, 0xcdf4, 0x883e); 3075 r8168_mac_ocp_write(tp, 0xcdf6, 0x9003); 3076 r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN); 3077 break; 3078 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 3079 r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); 3080 r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); 3081 r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); 3082 r8168_mac_ocp_write(tp, 0xcdd2, 0x889c); 3083 r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); 3084 r8168_mac_ocp_write(tp, 0xcdd4, 0x8c30); 3085 r8168_mac_ocp_write(tp, 0xcdda, 0x9003); 3086 r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); 3087 r8168_mac_ocp_write(tp, 0xcddc, 0x9003); 3088 r8168_mac_ocp_write(tp, 0xcde8, 0x883e); 3089 r8168_mac_ocp_write(tp, 0xcdea, 0x9003); 3090 r8168_mac_ocp_write(tp, 0xcdec, 0x889c); 3091 r8168_mac_ocp_write(tp, 0xcdee, 0x9003); 3092 r8168_mac_ocp_write(tp, 0xcdf0, 0x8C09); 3093 r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); 3094 r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN); 3095 break; 3096 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 3097 case RTL_GIGA_MAC_VER_52: 3098 r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); 3099 RTL_W8(tp, COMBO_LTR_EXTEND, RTL_R8(tp, COMBO_LTR_EXTEND) | COMBO_LTR_EXTEND_EN); 3100 fallthrough; 3101 case RTL_GIGA_MAC_VER_51: 3102 r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); 3103 r8168_mac_ocp_write(tp, 0xe02c, 0x1880); 3104 r8168_mac_ocp_write(tp, 0xe02e, 0x4880); 3105 r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); 3106 r8168_mac_ocp_write(tp, 0xcdda, 0x9003); 3107 r8168_mac_ocp_write(tp, 0xcddc, 0x9003); 3108 r8168_mac_ocp_write(tp, 0xcdd2, 0x883c); 3109 r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12); 3110 r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); 3111 break; 3112 default: 3113 return; 3114 } 3115 /* chip can trigger LTR */ 3116 r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0003, LTR_OBFF_LOCK_EN); 3117 } 3118 3119 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 3120 { 3121 u8 val8; 3122 3123 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 3124 return; 3125 3126 /* Don't enable ASPM in the chip if OS can't control ASPM */ 3127 if (enable && tp->aspm_manageable) { 3128 /* On these chip versions ASPM can even harm 3129 * bus communication of other PCI devices. 3130 */ 3131 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 3132 tp->mac_version == RTL_GIGA_MAC_VER_43) 3133 return; 3134 3135 rtl_mod_config5(tp, 0, ASPM_en); 3136 switch (tp->mac_version) { 3137 case RTL_GIGA_MAC_VER_70: 3138 case RTL_GIGA_MAC_VER_80: 3139 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 3140 RTL_W8(tp, INT_CFG0_8125, val8); 3141 break; 3142 default: 3143 rtl_mod_config2(tp, 0, ClkReqEn); 3144 break; 3145 } 3146 3147 rtl_enable_ltr(tp); 3148 switch (tp->mac_version) { 3149 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 3150 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 3151 /* reset ephy tx/rx disable timer */ 3152 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 3153 /* chip can trigger L1.2 */ 3154 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 3155 break; 3156 default: 3157 break; 3158 } 3159 } else { 3160 switch (tp->mac_version) { 3161 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 3162 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 3163 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 3164 break; 3165 default: 3166 break; 3167 } 3168 3169 switch (tp->mac_version) { 3170 case RTL_GIGA_MAC_VER_70: 3171 case RTL_GIGA_MAC_VER_80: 3172 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 3173 RTL_W8(tp, INT_CFG0_8125, val8); 3174 break; 3175 default: 3176 rtl_mod_config2(tp, ClkReqEn, 0); 3177 break; 3178 } 3179 rtl_mod_config5(tp, ASPM_en, 0); 3180 } 3181 } 3182 3183 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 3184 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 3185 { 3186 /* Usage of dynamic vs. static FIFO is controlled by bit 3187 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 3188 */ 3189 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 3190 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 3191 } 3192 3193 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3194 u8 low, u8 high) 3195 { 3196 /* FIFO thresholds for pause flow control */ 3197 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3198 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3199 } 3200 3201 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3202 { 3203 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3204 } 3205 3206 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3207 { 3208 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3209 3210 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3211 3212 rtl_disable_clock_request(tp); 3213 } 3214 3215 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3216 { 3217 static const struct ephy_info e_info_8168cp[] = { 3218 { 0x01, 0, 0x0001 }, 3219 { 0x02, 0x0800, 0x1000 }, 3220 { 0x03, 0, 0x0042 }, 3221 { 0x06, 0x0080, 0x0000 }, 3222 { 0x07, 0, 0x2000 } 3223 }; 3224 3225 rtl_set_def_aspm_entry_latency(tp); 3226 3227 rtl_ephy_init(tp, e_info_8168cp); 3228 3229 __rtl_hw_start_8168cp(tp); 3230 } 3231 3232 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3233 { 3234 rtl_set_def_aspm_entry_latency(tp); 3235 3236 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3237 } 3238 3239 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3240 { 3241 rtl_set_def_aspm_entry_latency(tp); 3242 3243 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3244 3245 /* Magic. */ 3246 RTL_W8(tp, DBG_REG, 0x20); 3247 } 3248 3249 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3250 { 3251 static const struct ephy_info e_info_8168c_1[] = { 3252 { 0x02, 0x0800, 0x1000 }, 3253 { 0x03, 0, 0x0002 }, 3254 { 0x06, 0x0080, 0x0000 } 3255 }; 3256 3257 rtl_set_def_aspm_entry_latency(tp); 3258 3259 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3260 3261 rtl_ephy_init(tp, e_info_8168c_1); 3262 3263 __rtl_hw_start_8168cp(tp); 3264 } 3265 3266 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3267 { 3268 static const struct ephy_info e_info_8168c_2[] = { 3269 { 0x01, 0, 0x0001 }, 3270 { 0x03, 0x0400, 0x0020 } 3271 }; 3272 3273 rtl_set_def_aspm_entry_latency(tp); 3274 3275 rtl_ephy_init(tp, e_info_8168c_2); 3276 3277 __rtl_hw_start_8168cp(tp); 3278 } 3279 3280 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3281 { 3282 rtl_set_def_aspm_entry_latency(tp); 3283 3284 __rtl_hw_start_8168cp(tp); 3285 } 3286 3287 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3288 { 3289 rtl_set_def_aspm_entry_latency(tp); 3290 3291 rtl_disable_clock_request(tp); 3292 } 3293 3294 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3295 { 3296 static const struct ephy_info e_info_8168d_4[] = { 3297 { 0x0b, 0x0000, 0x0048 }, 3298 { 0x19, 0x0020, 0x0050 }, 3299 { 0x0c, 0x0100, 0x0020 }, 3300 { 0x10, 0x0004, 0x0000 }, 3301 }; 3302 3303 rtl_set_def_aspm_entry_latency(tp); 3304 3305 rtl_ephy_init(tp, e_info_8168d_4); 3306 3307 rtl_enable_clock_request(tp); 3308 } 3309 3310 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3311 { 3312 static const struct ephy_info e_info_8168e_1[] = { 3313 { 0x00, 0x0200, 0x0100 }, 3314 { 0x00, 0x0000, 0x0004 }, 3315 { 0x06, 0x0002, 0x0001 }, 3316 { 0x06, 0x0000, 0x0030 }, 3317 { 0x07, 0x0000, 0x2000 }, 3318 { 0x00, 0x0000, 0x0020 }, 3319 { 0x03, 0x5800, 0x2000 }, 3320 { 0x03, 0x0000, 0x0001 }, 3321 { 0x01, 0x0800, 0x1000 }, 3322 { 0x07, 0x0000, 0x4000 }, 3323 { 0x1e, 0x0000, 0x2000 }, 3324 { 0x19, 0xffff, 0xfe6c }, 3325 { 0x0a, 0x0000, 0x0040 } 3326 }; 3327 3328 rtl_set_def_aspm_entry_latency(tp); 3329 3330 rtl_ephy_init(tp, e_info_8168e_1); 3331 3332 rtl_disable_clock_request(tp); 3333 3334 /* Reset tx FIFO pointer */ 3335 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3336 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3337 3338 rtl_mod_config5(tp, Spi_en, 0); 3339 } 3340 3341 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3342 { 3343 static const struct ephy_info e_info_8168e_2[] = { 3344 { 0x09, 0x0000, 0x0080 }, 3345 { 0x19, 0x0000, 0x0224 }, 3346 { 0x00, 0x0000, 0x0004 }, 3347 { 0x0c, 0x3df0, 0x0200 }, 3348 }; 3349 3350 rtl_set_def_aspm_entry_latency(tp); 3351 3352 rtl_ephy_init(tp, e_info_8168e_2); 3353 3354 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3355 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3356 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3357 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3358 rtl_reset_packet_filter(tp); 3359 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3360 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3361 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3362 3363 rtl_disable_clock_request(tp); 3364 3365 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3366 3367 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3368 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3369 rtl_mod_config5(tp, Spi_en, 0); 3370 } 3371 3372 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3373 { 3374 rtl_set_def_aspm_entry_latency(tp); 3375 3376 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3377 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3378 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3379 rtl_reset_packet_filter(tp); 3380 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3381 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3382 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3383 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3384 3385 rtl_disable_clock_request(tp); 3386 3387 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3388 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3389 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3390 rtl_mod_config5(tp, Spi_en, 0); 3391 } 3392 3393 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3394 { 3395 static const struct ephy_info e_info_8168f_1[] = { 3396 { 0x06, 0x00c0, 0x0020 }, 3397 { 0x08, 0x0001, 0x0002 }, 3398 { 0x09, 0x0000, 0x0080 }, 3399 { 0x19, 0x0000, 0x0224 }, 3400 { 0x00, 0x0000, 0x0008 }, 3401 { 0x0c, 0x3df0, 0x0200 }, 3402 }; 3403 3404 rtl_hw_start_8168f(tp); 3405 3406 rtl_ephy_init(tp, e_info_8168f_1); 3407 } 3408 3409 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3410 { 3411 static const struct ephy_info e_info_8168f_1[] = { 3412 { 0x06, 0x00c0, 0x0020 }, 3413 { 0x0f, 0xffff, 0x5200 }, 3414 { 0x19, 0x0000, 0x0224 }, 3415 { 0x00, 0x0000, 0x0008 }, 3416 { 0x0c, 0x3df0, 0x0200 }, 3417 }; 3418 3419 rtl_hw_start_8168f(tp); 3420 rtl_pcie_state_l2l3_disable(tp); 3421 3422 rtl_ephy_init(tp, e_info_8168f_1); 3423 } 3424 3425 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3426 { 3427 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3428 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3429 3430 rtl_set_def_aspm_entry_latency(tp); 3431 3432 rtl_reset_packet_filter(tp); 3433 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3434 3435 rtl_disable_rxdvgate(tp); 3436 3437 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3438 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3439 3440 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3441 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3442 3443 rtl_pcie_state_l2l3_disable(tp); 3444 } 3445 3446 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3447 { 3448 static const struct ephy_info e_info_8168g_1[] = { 3449 { 0x00, 0x0008, 0x0000 }, 3450 { 0x0c, 0x3ff0, 0x0820 }, 3451 { 0x1e, 0x0000, 0x0001 }, 3452 { 0x19, 0x8000, 0x0000 } 3453 }; 3454 3455 rtl_hw_start_8168g(tp); 3456 rtl_ephy_init(tp, e_info_8168g_1); 3457 } 3458 3459 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3460 { 3461 static const struct ephy_info e_info_8168g_2[] = { 3462 { 0x00, 0x0008, 0x0000 }, 3463 { 0x0c, 0x3ff0, 0x0820 }, 3464 { 0x19, 0xffff, 0x7c00 }, 3465 { 0x1e, 0xffff, 0x20eb }, 3466 { 0x0d, 0xffff, 0x1666 }, 3467 { 0x00, 0xffff, 0x10a3 }, 3468 { 0x06, 0xffff, 0xf050 }, 3469 { 0x04, 0x0000, 0x0010 }, 3470 { 0x1d, 0x4000, 0x0000 }, 3471 }; 3472 3473 rtl_hw_start_8168g(tp); 3474 rtl_ephy_init(tp, e_info_8168g_2); 3475 } 3476 3477 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3478 { 3479 static const u16 fix_data[] = { 3480 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3481 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3482 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3483 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3484 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3485 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3486 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3487 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3488 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3489 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3490 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3491 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3492 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3493 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3494 }; 3495 unsigned long flags; 3496 int i; 3497 3498 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3499 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3500 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3501 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3502 } 3503 3504 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3505 { 3506 static const struct ephy_info e_info_8411_2[] = { 3507 { 0x00, 0x0008, 0x0000 }, 3508 { 0x0c, 0x37d0, 0x0820 }, 3509 { 0x1e, 0x0000, 0x0001 }, 3510 { 0x19, 0x8021, 0x0000 }, 3511 { 0x1e, 0x0000, 0x2000 }, 3512 { 0x0d, 0x0100, 0x0200 }, 3513 { 0x00, 0x0000, 0x0080 }, 3514 { 0x06, 0x0000, 0x0010 }, 3515 { 0x04, 0x0000, 0x0010 }, 3516 { 0x1d, 0x0000, 0x4000 }, 3517 }; 3518 3519 rtl_hw_start_8168g(tp); 3520 3521 rtl_ephy_init(tp, e_info_8411_2); 3522 3523 /* The following Realtek-provided magic fixes an issue with the RX unit 3524 * getting confused after the PHY having been powered-down. 3525 */ 3526 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3527 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3528 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3529 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3530 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3531 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3532 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3533 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3534 mdelay(3); 3535 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3536 3537 rtl8411b_fix_phy_down(tp); 3538 3539 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3540 3541 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3542 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3543 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3544 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3545 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3546 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3547 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3548 } 3549 3550 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3551 { 3552 static const struct ephy_info e_info_8168h_1[] = { 3553 { 0x1e, 0x0800, 0x0001 }, 3554 { 0x1d, 0x0000, 0x0800 }, 3555 { 0x05, 0xffff, 0x2089 }, 3556 { 0x06, 0xffff, 0x5881 }, 3557 { 0x04, 0xffff, 0x854a }, 3558 { 0x01, 0xffff, 0x068b } 3559 }; 3560 int rg_saw_cnt; 3561 3562 rtl_ephy_init(tp, e_info_8168h_1); 3563 3564 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3565 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3566 3567 rtl_set_def_aspm_entry_latency(tp); 3568 3569 rtl_reset_packet_filter(tp); 3570 3571 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3572 3573 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3574 3575 rtl_disable_rxdvgate(tp); 3576 3577 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3578 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3579 3580 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3581 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3582 3583 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3584 3585 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3586 3587 rtl_pcie_state_l2l3_disable(tp); 3588 3589 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3590 if (rg_saw_cnt > 0) { 3591 u16 sw_cnt_1ms_ini; 3592 3593 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3594 sw_cnt_1ms_ini &= 0x0fff; 3595 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3596 } 3597 3598 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); 3599 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3600 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3601 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3602 3603 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3604 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3605 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3606 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3607 } 3608 3609 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3610 { 3611 rtl8168ep_stop_cmac(tp); 3612 3613 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3614 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3615 3616 rtl_set_def_aspm_entry_latency(tp); 3617 3618 rtl_reset_packet_filter(tp); 3619 3620 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3621 3622 rtl_disable_rxdvgate(tp); 3623 3624 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3625 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3626 3627 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3628 3629 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3630 3631 rtl_pcie_state_l2l3_disable(tp); 3632 } 3633 3634 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3635 { 3636 static const struct ephy_info e_info_8168ep_3[] = { 3637 { 0x00, 0x0000, 0x0080 }, 3638 { 0x0d, 0x0100, 0x0200 }, 3639 { 0x19, 0x8021, 0x0000 }, 3640 { 0x1e, 0x0000, 0x2000 }, 3641 }; 3642 3643 rtl_ephy_init(tp, e_info_8168ep_3); 3644 3645 rtl_hw_start_8168ep(tp); 3646 3647 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3648 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3649 3650 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3651 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3652 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3653 } 3654 3655 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3656 { 3657 static const struct ephy_info e_info_8117[] = { 3658 { 0x19, 0x0040, 0x1100 }, 3659 { 0x59, 0x0040, 0x1100 }, 3660 }; 3661 int rg_saw_cnt; 3662 3663 rtl8168ep_stop_cmac(tp); 3664 rtl_ephy_init(tp, e_info_8117); 3665 3666 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3667 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3668 3669 rtl_set_def_aspm_entry_latency(tp); 3670 3671 rtl_reset_packet_filter(tp); 3672 3673 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3674 3675 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3676 3677 rtl_disable_rxdvgate(tp); 3678 3679 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3680 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3681 3682 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3683 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3684 3685 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3686 3687 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3688 3689 rtl_pcie_state_l2l3_disable(tp); 3690 3691 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3692 if (rg_saw_cnt > 0) { 3693 u16 sw_cnt_1ms_ini; 3694 3695 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3696 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3697 } 3698 3699 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); 3700 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3701 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3702 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3703 3704 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3705 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3706 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3707 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3708 3709 /* firmware is for MAC only */ 3710 r8169_apply_firmware(tp); 3711 } 3712 3713 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3714 { 3715 static const struct ephy_info e_info_8102e_1[] = { 3716 { 0x01, 0, 0x6e65 }, 3717 { 0x02, 0, 0x091f }, 3718 { 0x03, 0, 0xc2f9 }, 3719 { 0x06, 0, 0xafb5 }, 3720 { 0x07, 0, 0x0e00 }, 3721 { 0x19, 0, 0xec80 }, 3722 { 0x01, 0, 0x2e65 }, 3723 { 0x01, 0, 0x6e65 } 3724 }; 3725 u8 cfg1; 3726 3727 rtl_set_def_aspm_entry_latency(tp); 3728 3729 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3730 3731 RTL_W8(tp, Config1, 3732 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3733 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3734 3735 cfg1 = RTL_R8(tp, Config1); 3736 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3737 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3738 3739 rtl_ephy_init(tp, e_info_8102e_1); 3740 } 3741 3742 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3743 { 3744 rtl_set_def_aspm_entry_latency(tp); 3745 3746 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3747 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3748 } 3749 3750 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3751 { 3752 rtl_hw_start_8102e_2(tp); 3753 3754 rtl_ephy_write(tp, 0x03, 0xc2f9); 3755 } 3756 3757 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3758 { 3759 static const struct ephy_info e_info_8401[] = { 3760 { 0x01, 0xffff, 0x6fe5 }, 3761 { 0x03, 0xffff, 0x0599 }, 3762 { 0x06, 0xffff, 0xaf25 }, 3763 { 0x07, 0xffff, 0x8e68 }, 3764 }; 3765 3766 rtl_ephy_init(tp, e_info_8401); 3767 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3768 } 3769 3770 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3771 { 3772 static const struct ephy_info e_info_8105e_1[] = { 3773 { 0x07, 0, 0x4000 }, 3774 { 0x19, 0, 0x0200 }, 3775 { 0x19, 0, 0x0020 }, 3776 { 0x1e, 0, 0x2000 }, 3777 { 0x03, 0, 0x0001 }, 3778 { 0x19, 0, 0x0100 }, 3779 { 0x19, 0, 0x0004 }, 3780 { 0x0a, 0, 0x0020 } 3781 }; 3782 3783 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3784 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3785 3786 /* Disable Early Tally Counter */ 3787 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3788 3789 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3790 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3791 3792 rtl_ephy_init(tp, e_info_8105e_1); 3793 3794 rtl_pcie_state_l2l3_disable(tp); 3795 } 3796 3797 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3798 { 3799 rtl_hw_start_8105e_1(tp); 3800 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3801 } 3802 3803 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3804 { 3805 static const struct ephy_info e_info_8402[] = { 3806 { 0x19, 0xffff, 0xff64 }, 3807 { 0x1e, 0, 0x4000 } 3808 }; 3809 3810 rtl_set_def_aspm_entry_latency(tp); 3811 3812 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3813 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3814 3815 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3816 3817 rtl_ephy_init(tp, e_info_8402); 3818 3819 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3820 rtl_reset_packet_filter(tp); 3821 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3822 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3823 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3824 3825 /* disable EEE */ 3826 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3827 3828 rtl_pcie_state_l2l3_disable(tp); 3829 } 3830 3831 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3832 { 3833 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3834 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3835 3836 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3837 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3838 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3839 3840 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3841 rtl_set_aspm_entry_latency(tp, 0x2f); 3842 3843 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3844 3845 /* disable EEE */ 3846 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3847 3848 rtl_pcie_state_l2l3_disable(tp); 3849 } 3850 3851 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3852 { 3853 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3854 } 3855 3856 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3857 { 3858 rtl_pcie_state_l2l3_disable(tp); 3859 3860 RTL_W16(tp, 0x382, 0x221b); 3861 RTL_W32(tp, RSS_CTRL_8125, 0); 3862 RTL_W16(tp, Q_NUM_CTRL_8125, 0); 3863 3864 /* disable UPS */ 3865 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3866 3867 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3868 3869 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3870 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3871 3872 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3873 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3874 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3875 3876 /* disable new tx descriptor format */ 3877 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3878 3879 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3880 tp->mac_version == RTL_GIGA_MAC_VER_80) 3881 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3882 3883 if (tp->mac_version == RTL_GIGA_MAC_VER_80) 3884 r8168_mac_ocp_modify(tp, 0xe614, 0x0f00, 0x0f00); 3885 else if (tp->mac_version == RTL_GIGA_MAC_VER_70) 3886 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3887 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3888 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3889 else 3890 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3891 3892 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3893 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3894 else 3895 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3896 3897 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3898 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3899 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3900 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); 3901 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3902 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3903 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3904 tp->mac_version == RTL_GIGA_MAC_VER_80) 3905 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3906 else 3907 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3908 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3909 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3910 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3911 3912 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3913 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3914 udelay(1); 3915 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3916 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3917 3918 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3919 3920 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3921 3922 rtl_disable_rxdvgate(tp); 3923 } 3924 3925 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3926 { 3927 static const struct ephy_info e_info_8125a_2[] = { 3928 { 0x04, 0xffff, 0xd000 }, 3929 { 0x0a, 0xffff, 0x8653 }, 3930 { 0x23, 0xffff, 0xab66 }, 3931 { 0x20, 0xffff, 0x9455 }, 3932 { 0x21, 0xffff, 0x99ff }, 3933 { 0x29, 0xffff, 0xfe04 }, 3934 3935 { 0x44, 0xffff, 0xd000 }, 3936 { 0x4a, 0xffff, 0x8653 }, 3937 { 0x63, 0xffff, 0xab66 }, 3938 { 0x60, 0xffff, 0x9455 }, 3939 { 0x61, 0xffff, 0x99ff }, 3940 { 0x69, 0xffff, 0xfe04 }, 3941 }; 3942 3943 rtl_set_def_aspm_entry_latency(tp); 3944 rtl_ephy_init(tp, e_info_8125a_2); 3945 rtl_hw_start_8125_common(tp); 3946 } 3947 3948 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3949 { 3950 static const struct ephy_info e_info_8125b[] = { 3951 { 0x0b, 0xffff, 0xa908 }, 3952 { 0x1e, 0xffff, 0x20eb }, 3953 { 0x4b, 0xffff, 0xa908 }, 3954 { 0x5e, 0xffff, 0x20eb }, 3955 { 0x22, 0x0030, 0x0020 }, 3956 { 0x62, 0x0030, 0x0020 }, 3957 }; 3958 3959 rtl_set_def_aspm_entry_latency(tp); 3960 rtl_ephy_init(tp, e_info_8125b); 3961 rtl_hw_start_8125_common(tp); 3962 } 3963 3964 static void rtl_hw_start_8125d(struct rtl8169_private *tp) 3965 { 3966 rtl_set_def_aspm_entry_latency(tp); 3967 rtl_hw_start_8125_common(tp); 3968 } 3969 3970 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3971 { 3972 rtl_disable_zrxdc_timeout(tp); 3973 rtl_set_def_aspm_entry_latency(tp); 3974 rtl_hw_start_8125_common(tp); 3975 } 3976 3977 static void rtl_hw_start_8127a(struct rtl8169_private *tp) 3978 { 3979 rtl_set_def_aspm_entry_latency(tp); 3980 rtl_hw_start_8125_common(tp); 3981 } 3982 3983 static void rtl_hw_config(struct rtl8169_private *tp) 3984 { 3985 static const rtl_generic_fct hw_configs[] = { 3986 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3987 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3988 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3989 [RTL_GIGA_MAC_VER_10] = NULL, 3990 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3991 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3992 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3993 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3994 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3995 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3996 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3997 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3998 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3999 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 4000 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 4001 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 4002 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 4003 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 4004 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 4005 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 4006 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 4007 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 4008 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 4009 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 4010 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 4011 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 4012 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 4013 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 4014 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 4015 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 4016 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 4017 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 4018 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 4019 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 4020 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 4021 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 4022 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 4023 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, 4024 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d, 4025 [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, 4026 [RTL_GIGA_MAC_VER_80] = rtl_hw_start_8127a, 4027 }; 4028 4029 if (hw_configs[tp->mac_version]) 4030 hw_configs[tp->mac_version](tp); 4031 } 4032 4033 static void rtl_hw_start_8125(struct rtl8169_private *tp) 4034 { 4035 int i; 4036 4037 RTL_W8(tp, INT_CFG0_8125, 0x00); 4038 4039 /* disable interrupt coalescing */ 4040 switch (tp->mac_version) { 4041 case RTL_GIGA_MAC_VER_61: 4042 case RTL_GIGA_MAC_VER_64: 4043 case RTL_GIGA_MAC_VER_66: 4044 case RTL_GIGA_MAC_VER_80: 4045 for (i = 0xa00; i < 0xb00; i += 4) 4046 RTL_W32(tp, i, 0); 4047 if (tp->mac_version == RTL_GIGA_MAC_VER_80) 4048 RTL_W16(tp, INT_CFG1_8125, 0x0000); 4049 break; 4050 case RTL_GIGA_MAC_VER_63: 4051 case RTL_GIGA_MAC_VER_70: 4052 for (i = 0xa00; i < 0xa80; i += 4) 4053 RTL_W32(tp, i, 0); 4054 RTL_W16(tp, INT_CFG1_8125, 0x0000); 4055 break; 4056 default: 4057 break; 4058 } 4059 4060 /* enable extended tally counter */ 4061 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); 4062 4063 rtl_hw_config(tp); 4064 } 4065 4066 static void rtl_hw_start_8168(struct rtl8169_private *tp) 4067 { 4068 if (rtl_is_8168evl_up(tp)) 4069 RTL_W8(tp, MaxTxPacketSize, EarlySize); 4070 else 4071 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 4072 4073 rtl_hw_config(tp); 4074 4075 /* disable interrupt coalescing */ 4076 RTL_W16(tp, IntrMitigate, 0x0000); 4077 } 4078 4079 static void rtl_hw_start_8169(struct rtl8169_private *tp) 4080 { 4081 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 4082 4083 tp->cp_cmd |= PCIMulRW; 4084 4085 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 4086 tp->mac_version == RTL_GIGA_MAC_VER_03) 4087 tp->cp_cmd |= EnAnaPLL; 4088 4089 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 4090 4091 rtl8169_set_magic_reg(tp); 4092 4093 /* disable interrupt coalescing */ 4094 RTL_W16(tp, IntrMitigate, 0x0000); 4095 } 4096 4097 static void rtl_hw_start(struct rtl8169_private *tp) 4098 { 4099 rtl_unlock_config_regs(tp); 4100 /* disable aspm and clock request before ephy access */ 4101 rtl_hw_aspm_clkreq_enable(tp, false); 4102 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 4103 4104 rtl_set_eee_txidle_timer(tp); 4105 4106 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4107 rtl_hw_start_8169(tp); 4108 else if (rtl_is_8125(tp)) 4109 rtl_hw_start_8125(tp); 4110 else 4111 rtl_hw_start_8168(tp); 4112 4113 rtl_enable_exit_l1(tp); 4114 rtl_hw_aspm_clkreq_enable(tp, true); 4115 rtl_set_rx_max_size(tp); 4116 rtl_set_rx_tx_desc_registers(tp); 4117 rtl_lock_config_regs(tp); 4118 4119 rtl_jumbo_config(tp); 4120 4121 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 4122 rtl_pci_commit(tp); 4123 4124 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 4125 rtl_init_rxcfg(tp); 4126 rtl_set_tx_config_registers(tp); 4127 rtl_set_rx_config_features(tp, tp->dev->features); 4128 rtl_set_rx_mode(tp->dev); 4129 rtl_irq_enable(tp); 4130 } 4131 4132 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 4133 { 4134 struct rtl8169_private *tp = netdev_priv(dev); 4135 4136 WRITE_ONCE(dev->mtu, new_mtu); 4137 netdev_update_features(dev); 4138 rtl_jumbo_config(tp); 4139 rtl_set_eee_txidle_timer(tp); 4140 4141 return 0; 4142 } 4143 4144 static void rtl8169_mark_to_asic(struct RxDesc *desc) 4145 { 4146 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 4147 4148 desc->opts2 = 0; 4149 /* Force memory writes to complete before releasing descriptor */ 4150 dma_wmb(); 4151 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 4152 } 4153 4154 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 4155 struct RxDesc *desc) 4156 { 4157 struct device *d = tp_to_dev(tp); 4158 int node = dev_to_node(d); 4159 dma_addr_t mapping; 4160 struct page *data; 4161 4162 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 4163 if (!data) 4164 return NULL; 4165 4166 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4167 if (unlikely(dma_mapping_error(d, mapping))) { 4168 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 4169 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 4170 return NULL; 4171 } 4172 4173 desc->addr = cpu_to_le64(mapping); 4174 rtl8169_mark_to_asic(desc); 4175 4176 return data; 4177 } 4178 4179 static void rtl8169_rx_clear(struct rtl8169_private *tp) 4180 { 4181 int i; 4182 4183 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 4184 dma_unmap_page(tp_to_dev(tp), 4185 le64_to_cpu(tp->RxDescArray[i].addr), 4186 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4187 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4188 tp->Rx_databuff[i] = NULL; 4189 tp->RxDescArray[i].addr = 0; 4190 tp->RxDescArray[i].opts1 = 0; 4191 } 4192 } 4193 4194 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4195 { 4196 int i; 4197 4198 for (i = 0; i < NUM_RX_DESC; i++) { 4199 struct page *data; 4200 4201 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4202 if (!data) { 4203 rtl8169_rx_clear(tp); 4204 return -ENOMEM; 4205 } 4206 tp->Rx_databuff[i] = data; 4207 } 4208 4209 /* mark as last descriptor in the ring */ 4210 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4211 4212 return 0; 4213 } 4214 4215 static int rtl8169_init_ring(struct rtl8169_private *tp) 4216 { 4217 rtl8169_init_ring_indexes(tp); 4218 4219 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4220 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4221 4222 return rtl8169_rx_fill(tp); 4223 } 4224 4225 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4226 { 4227 struct ring_info *tx_skb = tp->tx_skb + entry; 4228 struct TxDesc *desc = tp->TxDescArray + entry; 4229 4230 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4231 DMA_TO_DEVICE); 4232 memset(desc, 0, sizeof(*desc)); 4233 memset(tx_skb, 0, sizeof(*tx_skb)); 4234 } 4235 4236 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4237 unsigned int n) 4238 { 4239 unsigned int i; 4240 4241 for (i = 0; i < n; i++) { 4242 unsigned int entry = (start + i) % NUM_TX_DESC; 4243 struct ring_info *tx_skb = tp->tx_skb + entry; 4244 unsigned int len = tx_skb->len; 4245 4246 if (len) { 4247 struct sk_buff *skb = tx_skb->skb; 4248 4249 rtl8169_unmap_tx_skb(tp, entry); 4250 if (skb) 4251 dev_consume_skb_any(skb); 4252 } 4253 } 4254 } 4255 4256 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4257 { 4258 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4259 netdev_reset_queue(tp->dev); 4260 } 4261 4262 static void rtl8169_cleanup(struct rtl8169_private *tp) 4263 { 4264 napi_disable(&tp->napi); 4265 4266 /* Give a racing hard_start_xmit a few cycles to complete. */ 4267 synchronize_net(); 4268 4269 /* Disable interrupts */ 4270 rtl8169_irq_mask_and_ack(tp); 4271 4272 rtl_rx_close(tp); 4273 4274 switch (tp->mac_version) { 4275 case RTL_GIGA_MAC_VER_28: 4276 case RTL_GIGA_MAC_VER_31: 4277 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4278 break; 4279 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4280 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4281 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4282 break; 4283 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_LAST: 4284 rtl_enable_rxdvgate(tp); 4285 fsleep(2000); 4286 break; 4287 default: 4288 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4289 fsleep(100); 4290 break; 4291 } 4292 4293 rtl_hw_reset(tp); 4294 4295 rtl8169_tx_clear(tp); 4296 rtl8169_init_ring_indexes(tp); 4297 } 4298 4299 static void rtl_reset_work(struct rtl8169_private *tp) 4300 { 4301 int i; 4302 4303 netif_stop_queue(tp->dev); 4304 4305 rtl8169_cleanup(tp); 4306 4307 for (i = 0; i < NUM_RX_DESC; i++) 4308 rtl8169_mark_to_asic(tp->RxDescArray + i); 4309 4310 napi_enable(&tp->napi); 4311 rtl_hw_start(tp); 4312 } 4313 4314 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4315 { 4316 struct rtl8169_private *tp = netdev_priv(dev); 4317 4318 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4319 } 4320 4321 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4322 void *addr, unsigned int entry, bool desc_own) 4323 { 4324 struct TxDesc *txd = tp->TxDescArray + entry; 4325 struct device *d = tp_to_dev(tp); 4326 dma_addr_t mapping; 4327 u32 opts1; 4328 int ret; 4329 4330 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4331 ret = dma_mapping_error(d, mapping); 4332 if (unlikely(ret)) { 4333 if (net_ratelimit()) 4334 netdev_err(tp->dev, "Failed to map TX data!\n"); 4335 return ret; 4336 } 4337 4338 txd->addr = cpu_to_le64(mapping); 4339 txd->opts2 = cpu_to_le32(opts[1]); 4340 4341 opts1 = opts[0] | len; 4342 if (entry == NUM_TX_DESC - 1) 4343 opts1 |= RingEnd; 4344 if (desc_own) 4345 opts1 |= DescOwn; 4346 txd->opts1 = cpu_to_le32(opts1); 4347 4348 tp->tx_skb[entry].len = len; 4349 4350 return 0; 4351 } 4352 4353 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4354 const u32 *opts, unsigned int entry) 4355 { 4356 struct skb_shared_info *info = skb_shinfo(skb); 4357 unsigned int cur_frag; 4358 4359 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4360 const skb_frag_t *frag = info->frags + cur_frag; 4361 void *addr = skb_frag_address(frag); 4362 u32 len = skb_frag_size(frag); 4363 4364 entry = (entry + 1) % NUM_TX_DESC; 4365 4366 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4367 goto err_out; 4368 } 4369 4370 return 0; 4371 4372 err_out: 4373 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4374 return -EIO; 4375 } 4376 4377 static bool rtl_skb_is_udp(struct sk_buff *skb) 4378 { 4379 int no = skb_network_offset(skb); 4380 struct ipv6hdr *i6h, _i6h; 4381 struct iphdr *ih, _ih; 4382 4383 switch (vlan_get_protocol(skb)) { 4384 case htons(ETH_P_IP): 4385 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4386 return ih && ih->protocol == IPPROTO_UDP; 4387 case htons(ETH_P_IPV6): 4388 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4389 return i6h && i6h->nexthdr == IPPROTO_UDP; 4390 default: 4391 return false; 4392 } 4393 } 4394 4395 #define RTL_MIN_PATCH_LEN 47 4396 4397 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4398 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4399 struct sk_buff *skb) 4400 { 4401 unsigned int padto = 0, len = skb->len; 4402 4403 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) && 4404 skb_transport_header_was_set(skb)) { 4405 unsigned int trans_data_len = skb_tail_pointer(skb) - 4406 skb_transport_header(skb); 4407 4408 if (trans_data_len >= offsetof(struct udphdr, len) && 4409 trans_data_len < RTL_MIN_PATCH_LEN) { 4410 u16 dest = ntohs(udp_hdr(skb)->dest); 4411 4412 /* dest is a standard PTP port */ 4413 if (dest == 319 || dest == 320) 4414 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4415 } 4416 4417 if (trans_data_len < sizeof(struct udphdr)) 4418 padto = max_t(unsigned int, padto, 4419 len + sizeof(struct udphdr) - trans_data_len); 4420 } 4421 4422 return padto; 4423 } 4424 4425 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4426 struct sk_buff *skb) 4427 { 4428 unsigned int padto = 0; 4429 4430 switch (tp->mac_version) { 4431 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 4432 padto = rtl8125_quirk_udp_padto(tp, skb); 4433 break; 4434 default: 4435 break; 4436 } 4437 4438 switch (tp->mac_version) { 4439 case RTL_GIGA_MAC_VER_34: 4440 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 4441 padto = max_t(unsigned int, padto, ETH_ZLEN); 4442 break; 4443 default: 4444 break; 4445 } 4446 4447 return padto; 4448 } 4449 4450 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4451 { 4452 u32 mss = skb_shinfo(skb)->gso_size; 4453 4454 if (mss) { 4455 opts[0] |= TD_LSO; 4456 opts[0] |= mss << TD0_MSS_SHIFT; 4457 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4458 const struct iphdr *ip = ip_hdr(skb); 4459 4460 if (ip->protocol == IPPROTO_TCP) 4461 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4462 else if (ip->protocol == IPPROTO_UDP) 4463 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4464 else 4465 WARN_ON_ONCE(1); 4466 } 4467 } 4468 4469 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4470 struct sk_buff *skb, u32 *opts) 4471 { 4472 struct skb_shared_info *shinfo = skb_shinfo(skb); 4473 u32 mss = shinfo->gso_size; 4474 4475 if (mss) { 4476 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4477 opts[0] |= TD1_GTSENV4; 4478 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4479 if (skb_cow_head(skb, 0)) 4480 return false; 4481 4482 tcp_v6_gso_csum_prep(skb); 4483 opts[0] |= TD1_GTSENV6; 4484 } else { 4485 WARN_ON_ONCE(1); 4486 } 4487 4488 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4489 opts[1] |= mss << TD1_MSS_SHIFT; 4490 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4491 u8 ip_protocol; 4492 4493 switch (vlan_get_protocol(skb)) { 4494 case htons(ETH_P_IP): 4495 opts[1] |= TD1_IPv4_CS; 4496 ip_protocol = ip_hdr(skb)->protocol; 4497 break; 4498 4499 case htons(ETH_P_IPV6): 4500 opts[1] |= TD1_IPv6_CS; 4501 ip_protocol = ipv6_hdr(skb)->nexthdr; 4502 break; 4503 4504 default: 4505 ip_protocol = IPPROTO_RAW; 4506 break; 4507 } 4508 4509 if (ip_protocol == IPPROTO_TCP) 4510 opts[1] |= TD1_TCP_CS; 4511 else if (ip_protocol == IPPROTO_UDP) 4512 opts[1] |= TD1_UDP_CS; 4513 else 4514 WARN_ON_ONCE(1); 4515 4516 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4517 } else { 4518 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4519 4520 /* skb_padto would free the skb on error */ 4521 return !__skb_put_padto(skb, padto, false); 4522 } 4523 4524 return true; 4525 } 4526 4527 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4528 { 4529 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4530 } 4531 4532 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4533 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4534 { 4535 switch (tp->mac_version) { 4536 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4537 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4538 return false; 4539 default: 4540 return true; 4541 } 4542 } 4543 4544 static void rtl8169_doorbell(struct rtl8169_private *tp) 4545 { 4546 if (rtl_is_8125(tp)) 4547 RTL_W16(tp, TxPoll_8125, BIT(0)); 4548 else 4549 RTL_W8(tp, TxPoll, NPQ); 4550 } 4551 4552 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4553 struct net_device *dev) 4554 { 4555 struct rtl8169_private *tp = netdev_priv(dev); 4556 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4557 struct TxDesc *txd_first, *txd_last; 4558 bool stop_queue, door_bell; 4559 unsigned int frags; 4560 u32 opts[2]; 4561 4562 if (unlikely(!rtl_tx_slots_avail(tp))) { 4563 if (net_ratelimit()) 4564 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4565 netif_stop_queue(dev); 4566 return NETDEV_TX_BUSY; 4567 } 4568 4569 opts[1] = rtl8169_tx_vlan_tag(skb); 4570 opts[0] = 0; 4571 4572 if (!rtl_chip_supports_csum_v2(tp)) 4573 rtl8169_tso_csum_v1(skb, opts); 4574 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4575 goto err_dma_0; 4576 4577 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4578 entry, false))) 4579 goto err_dma_0; 4580 4581 txd_first = tp->TxDescArray + entry; 4582 4583 frags = skb_shinfo(skb)->nr_frags; 4584 if (frags) { 4585 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4586 goto err_dma_1; 4587 entry = (entry + frags) % NUM_TX_DESC; 4588 } 4589 4590 txd_last = tp->TxDescArray + entry; 4591 txd_last->opts1 |= cpu_to_le32(LastFrag); 4592 tp->tx_skb[entry].skb = skb; 4593 4594 skb_tx_timestamp(skb); 4595 4596 /* Force memory writes to complete before releasing descriptor */ 4597 dma_wmb(); 4598 4599 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4600 4601 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4602 4603 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4604 smp_wmb(); 4605 4606 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4607 4608 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4609 R8169_TX_STOP_THRS, 4610 R8169_TX_START_THRS); 4611 if (door_bell || stop_queue) 4612 rtl8169_doorbell(tp); 4613 4614 return NETDEV_TX_OK; 4615 4616 err_dma_1: 4617 rtl8169_unmap_tx_skb(tp, entry); 4618 err_dma_0: 4619 dev_kfree_skb_any(skb); 4620 dev->stats.tx_dropped++; 4621 return NETDEV_TX_OK; 4622 } 4623 4624 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4625 { 4626 struct skb_shared_info *info = skb_shinfo(skb); 4627 unsigned int nr_frags = info->nr_frags; 4628 4629 if (!nr_frags) 4630 return UINT_MAX; 4631 4632 return skb_frag_size(info->frags + nr_frags - 1); 4633 } 4634 4635 /* Workaround for hw issues with TSO on RTL8168evl */ 4636 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4637 netdev_features_t features) 4638 { 4639 /* IPv4 header has options field */ 4640 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4641 ip_hdrlen(skb) > sizeof(struct iphdr)) 4642 features &= ~NETIF_F_ALL_TSO; 4643 4644 /* IPv4 TCP header has options field */ 4645 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4646 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4647 features &= ~NETIF_F_ALL_TSO; 4648 4649 else if (rtl_last_frag_len(skb) <= 6) 4650 features &= ~NETIF_F_ALL_TSO; 4651 4652 return features; 4653 } 4654 4655 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4656 struct net_device *dev, 4657 netdev_features_t features) 4658 { 4659 struct rtl8169_private *tp = netdev_priv(dev); 4660 4661 if (skb_is_gso(skb)) { 4662 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4663 features = rtl8168evl_fix_tso(skb, features); 4664 4665 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4666 rtl_chip_supports_csum_v2(tp)) 4667 features &= ~NETIF_F_ALL_TSO; 4668 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4669 /* work around hw bug on some chip versions */ 4670 if (skb->len < ETH_ZLEN) 4671 features &= ~NETIF_F_CSUM_MASK; 4672 4673 if (rtl_quirk_packet_padto(tp, skb)) 4674 features &= ~NETIF_F_CSUM_MASK; 4675 4676 if (skb_transport_offset(skb) > TCPHO_MAX && 4677 rtl_chip_supports_csum_v2(tp)) 4678 features &= ~NETIF_F_CSUM_MASK; 4679 } 4680 4681 return vlan_features_check(skb, features); 4682 } 4683 4684 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4685 { 4686 struct rtl8169_private *tp = netdev_priv(dev); 4687 struct pci_dev *pdev = tp->pci_dev; 4688 int pci_status_errs; 4689 u16 pci_cmd; 4690 4691 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4692 4693 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4694 4695 if (net_ratelimit()) 4696 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4697 pci_cmd, pci_status_errs); 4698 4699 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4700 } 4701 4702 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4703 int budget) 4704 { 4705 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4706 struct sk_buff *skb; 4707 4708 dirty_tx = tp->dirty_tx; 4709 4710 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4711 unsigned int entry = dirty_tx % NUM_TX_DESC; 4712 u32 status; 4713 4714 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4715 if (status & DescOwn) 4716 break; 4717 4718 skb = tp->tx_skb[entry].skb; 4719 rtl8169_unmap_tx_skb(tp, entry); 4720 4721 if (skb) { 4722 pkts_compl++; 4723 bytes_compl += skb->len; 4724 napi_consume_skb(skb, budget); 4725 } 4726 dirty_tx++; 4727 } 4728 4729 if (tp->dirty_tx != dirty_tx) { 4730 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4731 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4732 4733 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4734 rtl_tx_slots_avail(tp), 4735 R8169_TX_START_THRS); 4736 /* 4737 * 8168 hack: TxPoll requests are lost when the Tx packets are 4738 * too close. Let's kick an extra TxPoll request when a burst 4739 * of start_xmit activity is detected (if it is not detected, 4740 * it is slow enough). -- FR 4741 * If skb is NULL then we come here again once a tx irq is 4742 * triggered after the last fragment is marked transmitted. 4743 */ 4744 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4745 rtl8169_doorbell(tp); 4746 } 4747 } 4748 4749 static inline int rtl8169_fragmented_frame(u32 status) 4750 { 4751 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4752 } 4753 4754 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4755 { 4756 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4757 4758 if (status == RxProtoTCP || status == RxProtoUDP) 4759 skb->ip_summed = CHECKSUM_UNNECESSARY; 4760 else 4761 skb_checksum_none_assert(skb); 4762 } 4763 4764 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4765 { 4766 struct device *d = tp_to_dev(tp); 4767 int count; 4768 4769 for (count = 0; count < budget; count++, tp->cur_rx++) { 4770 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4771 struct RxDesc *desc = tp->RxDescArray + entry; 4772 struct sk_buff *skb; 4773 const void *rx_buf; 4774 dma_addr_t addr; 4775 u32 status; 4776 4777 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4778 if (status & DescOwn) 4779 break; 4780 4781 /* This barrier is needed to keep us from reading 4782 * any other fields out of the Rx descriptor until 4783 * we know the status of DescOwn 4784 */ 4785 dma_rmb(); 4786 4787 if (unlikely(status & RxRES)) { 4788 if (net_ratelimit()) 4789 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4790 status); 4791 dev->stats.rx_errors++; 4792 if (status & (RxRWT | RxRUNT)) 4793 dev->stats.rx_length_errors++; 4794 if (status & RxCRC) 4795 dev->stats.rx_crc_errors++; 4796 4797 if (!(dev->features & NETIF_F_RXALL)) 4798 goto release_descriptor; 4799 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4800 goto release_descriptor; 4801 } 4802 4803 pkt_size = status & GENMASK(13, 0); 4804 if (likely(!(dev->features & NETIF_F_RXFCS))) 4805 pkt_size -= ETH_FCS_LEN; 4806 4807 /* The driver does not support incoming fragmented frames. 4808 * They are seen as a symptom of over-mtu sized frames. 4809 */ 4810 if (unlikely(rtl8169_fragmented_frame(status))) { 4811 dev->stats.rx_dropped++; 4812 dev->stats.rx_length_errors++; 4813 goto release_descriptor; 4814 } 4815 4816 skb = napi_alloc_skb(&tp->napi, pkt_size); 4817 if (unlikely(!skb)) { 4818 dev->stats.rx_dropped++; 4819 goto release_descriptor; 4820 } 4821 4822 addr = le64_to_cpu(desc->addr); 4823 rx_buf = page_address(tp->Rx_databuff[entry]); 4824 4825 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4826 prefetch(rx_buf); 4827 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4828 skb->tail += pkt_size; 4829 skb->len = pkt_size; 4830 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4831 4832 rtl8169_rx_csum(skb, status); 4833 skb->protocol = eth_type_trans(skb, dev); 4834 4835 rtl8169_rx_vlan_tag(desc, skb); 4836 4837 if (skb->pkt_type == PACKET_MULTICAST) 4838 dev->stats.multicast++; 4839 4840 napi_gro_receive(&tp->napi, skb); 4841 4842 dev_sw_netstats_rx_add(dev, pkt_size); 4843 release_descriptor: 4844 rtl8169_mark_to_asic(desc); 4845 } 4846 4847 return count; 4848 } 4849 4850 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4851 { 4852 struct rtl8169_private *tp = dev_instance; 4853 u32 status = rtl_get_events(tp); 4854 4855 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4856 return IRQ_NONE; 4857 4858 /* At least RTL8168fp may unexpectedly set the SYSErr bit */ 4859 if (unlikely(status & SYSErr && 4860 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { 4861 rtl8169_pcierr_interrupt(tp->dev); 4862 goto out; 4863 } 4864 4865 if (status & LinkChg) 4866 phy_mac_interrupt(tp->phydev); 4867 4868 rtl_irq_disable(tp); 4869 napi_schedule(&tp->napi); 4870 out: 4871 rtl_ack_events(tp, status); 4872 4873 return IRQ_HANDLED; 4874 } 4875 4876 static void rtl_task(struct work_struct *work) 4877 { 4878 struct rtl8169_private *tp = 4879 container_of(work, struct rtl8169_private, wk.work); 4880 int ret; 4881 4882 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4883 /* if chip isn't accessible, reset bus to revive it */ 4884 if (RTL_R32(tp, TxConfig) == ~0) { 4885 ret = pci_reset_bus(tp->pci_dev); 4886 if (ret < 0) { 4887 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4888 netif_device_detach(tp->dev); 4889 return; 4890 } 4891 } 4892 4893 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4894 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4895 PCIE_LINK_STATE_L0S); 4896 if (!ret) 4897 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4898 goto reset; 4899 } 4900 4901 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4902 reset: 4903 rtl_reset_work(tp); 4904 netif_wake_queue(tp->dev); 4905 } 4906 } 4907 4908 static int rtl8169_poll(struct napi_struct *napi, int budget) 4909 { 4910 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4911 struct net_device *dev = tp->dev; 4912 int work_done; 4913 4914 rtl_tx(dev, tp, budget); 4915 4916 work_done = rtl_rx(dev, tp, budget); 4917 4918 if (work_done < budget && napi_complete_done(napi, work_done)) 4919 rtl_irq_enable(tp); 4920 4921 return work_done; 4922 } 4923 4924 static void rtl_enable_tx_lpi(struct rtl8169_private *tp, bool enable) 4925 { 4926 if (!rtl_supports_eee(tp)) 4927 return; 4928 4929 switch (tp->mac_version) { 4930 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_52: 4931 /* Adjust EEE LED frequency */ 4932 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 4933 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 4934 if (enable) 4935 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 4936 else 4937 rtl_eri_clear_bits(tp, 0x1b0, 0x0003); 4938 break; 4939 case RTL_GIGA_MAC_VER_61: 4940 if (enable) { 4941 r8168_mac_ocp_modify(tp, 0xe040, 0, 0x0003); 4942 r8168_mac_ocp_modify(tp, 0xeb62, 0, 0x0006); 4943 } else { 4944 r8168_mac_ocp_modify(tp, 0xe040, 0x0003, 0); 4945 r8168_mac_ocp_modify(tp, 0xeb62, 0x0006, 0); 4946 } 4947 break; 4948 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_LAST: 4949 if (enable) 4950 r8168_mac_ocp_modify(tp, 0xe040, 0, 0x0003); 4951 else 4952 r8168_mac_ocp_modify(tp, 0xe040, 0x0003, 0); 4953 break; 4954 default: 4955 break; 4956 } 4957 } 4958 4959 static void r8169_phylink_handler(struct net_device *ndev) 4960 { 4961 struct rtl8169_private *tp = netdev_priv(ndev); 4962 struct device *d = tp_to_dev(tp); 4963 4964 if (netif_carrier_ok(ndev)) { 4965 rtl_link_chg_patch(tp); 4966 rtl_enable_tx_lpi(tp, tp->phydev->enable_tx_lpi); 4967 pm_request_resume(d); 4968 } else { 4969 pm_runtime_idle(d); 4970 } 4971 4972 phy_print_status(tp->phydev); 4973 } 4974 4975 static int r8169_phy_connect(struct rtl8169_private *tp) 4976 { 4977 struct phy_device *phydev = tp->phydev; 4978 phy_interface_t phy_mode; 4979 int ret; 4980 4981 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4982 PHY_INTERFACE_MODE_MII; 4983 4984 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4985 phy_mode); 4986 if (ret) 4987 return ret; 4988 4989 if (!tp->supports_gmii) 4990 phy_set_max_speed(phydev, SPEED_100); 4991 4992 phy_attached_info(phydev); 4993 4994 return 0; 4995 } 4996 4997 static void rtl8169_down(struct rtl8169_private *tp) 4998 { 4999 disable_work_sync(&tp->wk.work); 5000 /* Clear all task flags */ 5001 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 5002 5003 phy_stop(tp->phydev); 5004 5005 /* Reset SerDes PHY to bring down fiber link */ 5006 if (tp->sfp_mode) 5007 rtl_sfp_reset(tp); 5008 5009 rtl8169_update_counters(tp); 5010 5011 pci_clear_master(tp->pci_dev); 5012 rtl_pci_commit(tp); 5013 5014 rtl8169_cleanup(tp); 5015 rtl_disable_exit_l1(tp); 5016 rtl_prepare_power_down(tp); 5017 5018 if (tp->dash_type != RTL_DASH_NONE && !tp->saved_wolopts) 5019 rtl8168_driver_stop(tp); 5020 } 5021 5022 static void rtl8169_up(struct rtl8169_private *tp) 5023 { 5024 if (tp->dash_type != RTL_DASH_NONE) 5025 rtl8168_driver_start(tp); 5026 5027 pci_set_master(tp->pci_dev); 5028 phy_init_hw(tp->phydev); 5029 phy_resume(tp->phydev); 5030 rtl8169_init_phy(tp); 5031 napi_enable(&tp->napi); 5032 enable_work(&tp->wk.work); 5033 rtl_reset_work(tp); 5034 5035 phy_start(tp->phydev); 5036 } 5037 5038 static int rtl8169_close(struct net_device *dev) 5039 { 5040 struct rtl8169_private *tp = netdev_priv(dev); 5041 struct pci_dev *pdev = tp->pci_dev; 5042 5043 pm_runtime_get_sync(&pdev->dev); 5044 5045 netif_stop_queue(dev); 5046 rtl8169_down(tp); 5047 rtl8169_rx_clear(tp); 5048 5049 free_irq(tp->irq, tp); 5050 5051 phy_disconnect(tp->phydev); 5052 5053 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 5054 tp->RxPhyAddr); 5055 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 5056 tp->TxPhyAddr); 5057 tp->TxDescArray = NULL; 5058 tp->RxDescArray = NULL; 5059 5060 pm_runtime_put_sync(&pdev->dev); 5061 5062 return 0; 5063 } 5064 5065 #ifdef CONFIG_NET_POLL_CONTROLLER 5066 static void rtl8169_netpoll(struct net_device *dev) 5067 { 5068 struct rtl8169_private *tp = netdev_priv(dev); 5069 5070 rtl8169_interrupt(tp->irq, tp); 5071 } 5072 #endif 5073 5074 static int rtl_open(struct net_device *dev) 5075 { 5076 struct rtl8169_private *tp = netdev_priv(dev); 5077 struct pci_dev *pdev = tp->pci_dev; 5078 unsigned long irqflags; 5079 int retval = -ENOMEM; 5080 5081 pm_runtime_get_sync(&pdev->dev); 5082 5083 /* 5084 * Rx and Tx descriptors needs 256 bytes alignment. 5085 * dma_alloc_coherent provides more. 5086 */ 5087 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 5088 &tp->TxPhyAddr, GFP_KERNEL); 5089 if (!tp->TxDescArray) 5090 goto out; 5091 5092 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 5093 &tp->RxPhyAddr, GFP_KERNEL); 5094 if (!tp->RxDescArray) 5095 goto err_free_tx_0; 5096 5097 retval = rtl8169_init_ring(tp); 5098 if (retval < 0) 5099 goto err_free_rx_1; 5100 5101 rtl_request_firmware(tp); 5102 5103 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 5104 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 5105 if (retval < 0) 5106 goto err_release_fw_2; 5107 5108 retval = r8169_phy_connect(tp); 5109 if (retval) 5110 goto err_free_irq; 5111 5112 rtl8169_up(tp); 5113 rtl8169_init_counter_offsets(tp); 5114 netif_start_queue(dev); 5115 out: 5116 pm_runtime_put_sync(&pdev->dev); 5117 5118 return retval; 5119 5120 err_free_irq: 5121 free_irq(tp->irq, tp); 5122 err_release_fw_2: 5123 rtl_release_firmware(tp); 5124 rtl8169_rx_clear(tp); 5125 err_free_rx_1: 5126 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 5127 tp->RxPhyAddr); 5128 tp->RxDescArray = NULL; 5129 err_free_tx_0: 5130 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 5131 tp->TxPhyAddr); 5132 tp->TxDescArray = NULL; 5133 goto out; 5134 } 5135 5136 static void 5137 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 5138 { 5139 struct rtl8169_private *tp = netdev_priv(dev); 5140 struct pci_dev *pdev = tp->pci_dev; 5141 struct rtl8169_counters *counters = tp->counters; 5142 5143 pm_runtime_get_noresume(&pdev->dev); 5144 5145 netdev_stats_to_stats64(stats, &dev->stats); 5146 dev_fetch_sw_netstats(stats, dev->tstats); 5147 5148 /* 5149 * Fetch additional counter values missing in stats collected by driver 5150 * from tally counters. 5151 */ 5152 if (pm_runtime_active(&pdev->dev)) 5153 rtl8169_update_counters(tp); 5154 5155 /* 5156 * Subtract values fetched during initalization. 5157 * See rtl8169_init_counter_offsets for a description why we do that. 5158 */ 5159 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 5160 le64_to_cpu(tp->tc_offset.tx_errors); 5161 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 5162 le32_to_cpu(tp->tc_offset.tx_multi_collision); 5163 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 5164 le16_to_cpu(tp->tc_offset.tx_aborted); 5165 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 5166 le16_to_cpu(tp->tc_offset.rx_missed); 5167 5168 pm_runtime_put_noidle(&pdev->dev); 5169 } 5170 5171 static void rtl8169_net_suspend(struct rtl8169_private *tp) 5172 { 5173 netif_device_detach(tp->dev); 5174 5175 if (netif_running(tp->dev)) 5176 rtl8169_down(tp); 5177 } 5178 5179 static int rtl8169_runtime_resume(struct device *dev) 5180 { 5181 struct rtl8169_private *tp = dev_get_drvdata(dev); 5182 5183 rtl_rar_set(tp, tp->dev->dev_addr); 5184 __rtl8169_set_wol(tp, tp->saved_wolopts); 5185 5186 if (tp->TxDescArray) 5187 rtl8169_up(tp); 5188 5189 netif_device_attach(tp->dev); 5190 5191 return 0; 5192 } 5193 5194 static int rtl8169_suspend(struct device *device) 5195 { 5196 struct rtl8169_private *tp = dev_get_drvdata(device); 5197 5198 rtnl_lock(); 5199 rtl8169_net_suspend(tp); 5200 if (!device_may_wakeup(tp_to_dev(tp))) 5201 clk_disable_unprepare(tp->clk); 5202 rtnl_unlock(); 5203 5204 return 0; 5205 } 5206 5207 static int rtl8169_resume(struct device *device) 5208 { 5209 struct rtl8169_private *tp = dev_get_drvdata(device); 5210 5211 if (!device_may_wakeup(tp_to_dev(tp))) 5212 clk_prepare_enable(tp->clk); 5213 5214 /* Some chip versions may truncate packets without this initialization */ 5215 rtl_init_rxcfg(tp); 5216 5217 return rtl8169_runtime_resume(device); 5218 } 5219 5220 static int rtl8169_runtime_suspend(struct device *device) 5221 { 5222 struct rtl8169_private *tp = dev_get_drvdata(device); 5223 5224 if (!tp->TxDescArray) { 5225 netif_device_detach(tp->dev); 5226 return 0; 5227 } 5228 5229 rtnl_lock(); 5230 __rtl8169_set_wol(tp, WAKE_PHY); 5231 rtl8169_net_suspend(tp); 5232 rtnl_unlock(); 5233 5234 return 0; 5235 } 5236 5237 static int rtl8169_runtime_idle(struct device *device) 5238 { 5239 struct rtl8169_private *tp = dev_get_drvdata(device); 5240 5241 if (tp->dash_enabled) 5242 return -EBUSY; 5243 5244 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5245 pm_schedule_suspend(device, 10000); 5246 5247 return -EBUSY; 5248 } 5249 5250 static const struct dev_pm_ops rtl8169_pm_ops = { 5251 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5252 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5253 rtl8169_runtime_idle) 5254 }; 5255 5256 static void rtl_shutdown(struct pci_dev *pdev) 5257 { 5258 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5259 5260 rtnl_lock(); 5261 rtl8169_net_suspend(tp); 5262 rtnl_unlock(); 5263 5264 /* Restore original MAC address */ 5265 rtl_rar_set(tp, tp->dev->perm_addr); 5266 5267 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) 5268 pci_prepare_to_sleep(pdev); 5269 } 5270 5271 static void rtl_remove_one(struct pci_dev *pdev) 5272 { 5273 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5274 5275 if (pci_dev_run_wake(pdev)) 5276 pm_runtime_get_noresume(&pdev->dev); 5277 5278 disable_work_sync(&tp->wk.work); 5279 5280 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5281 r8169_remove_leds(tp->leds); 5282 5283 unregister_netdev(tp->dev); 5284 5285 if (tp->dash_type != RTL_DASH_NONE) 5286 rtl8168_driver_stop(tp); 5287 5288 rtl_release_firmware(tp); 5289 5290 /* restore original MAC address */ 5291 rtl_rar_set(tp, tp->dev->perm_addr); 5292 } 5293 5294 static const struct net_device_ops rtl_netdev_ops = { 5295 .ndo_open = rtl_open, 5296 .ndo_stop = rtl8169_close, 5297 .ndo_get_stats64 = rtl8169_get_stats64, 5298 .ndo_start_xmit = rtl8169_start_xmit, 5299 .ndo_features_check = rtl8169_features_check, 5300 .ndo_tx_timeout = rtl8169_tx_timeout, 5301 .ndo_validate_addr = eth_validate_addr, 5302 .ndo_change_mtu = rtl8169_change_mtu, 5303 .ndo_fix_features = rtl8169_fix_features, 5304 .ndo_set_features = rtl8169_set_features, 5305 .ndo_set_mac_address = rtl_set_mac_address, 5306 .ndo_eth_ioctl = phy_do_ioctl_running, 5307 .ndo_set_rx_mode = rtl_set_rx_mode, 5308 #ifdef CONFIG_NET_POLL_CONTROLLER 5309 .ndo_poll_controller = rtl8169_netpoll, 5310 #endif 5311 5312 }; 5313 5314 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5315 { 5316 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5317 5318 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5319 tp->irq_mask |= SYSErr | RxFIFOOver; 5320 } 5321 5322 static int rtl_alloc_irq(struct rtl8169_private *tp) 5323 { 5324 unsigned int flags; 5325 5326 switch (tp->mac_version) { 5327 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5328 rtl_unlock_config_regs(tp); 5329 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5330 rtl_lock_config_regs(tp); 5331 fallthrough; 5332 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5333 flags = PCI_IRQ_INTX; 5334 break; 5335 default: 5336 flags = PCI_IRQ_ALL_TYPES; 5337 break; 5338 } 5339 5340 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5341 } 5342 5343 static void rtl_read_mac_address(struct rtl8169_private *tp, 5344 u8 mac_addr[ETH_ALEN]) 5345 { 5346 /* Get MAC address */ 5347 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5348 u32 value; 5349 5350 value = rtl_eri_read(tp, 0xe0); 5351 put_unaligned_le32(value, mac_addr); 5352 value = rtl_eri_read(tp, 0xe4); 5353 put_unaligned_le16(value, mac_addr + 4); 5354 } else if (rtl_is_8125(tp)) { 5355 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5356 } 5357 } 5358 5359 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5360 { 5361 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5362 } 5363 5364 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5365 { 5366 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5367 } 5368 5369 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5370 { 5371 struct rtl8169_private *tp = mii_bus->priv; 5372 5373 if (phyaddr > 0) 5374 return -ENODEV; 5375 5376 return rtl_readphy(tp, phyreg); 5377 } 5378 5379 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5380 int phyreg, u16 val) 5381 { 5382 struct rtl8169_private *tp = mii_bus->priv; 5383 5384 if (phyaddr > 0) 5385 return -ENODEV; 5386 5387 rtl_writephy(tp, phyreg, val); 5388 5389 return 0; 5390 } 5391 5392 static int r8169_mdio_read_reg_c45(struct mii_bus *mii_bus, int addr, 5393 int devnum, int regnum) 5394 { 5395 struct rtl8169_private *tp = mii_bus->priv; 5396 5397 if (addr > 0) 5398 return -ENODEV; 5399 5400 if (devnum == MDIO_MMD_VEND2 && regnum > MDIO_STAT2) 5401 return r8168_phy_ocp_read(tp, regnum); 5402 5403 return 0; 5404 } 5405 5406 static int r8169_mdio_write_reg_c45(struct mii_bus *mii_bus, int addr, 5407 int devnum, int regnum, u16 val) 5408 { 5409 struct rtl8169_private *tp = mii_bus->priv; 5410 5411 if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2) 5412 return -ENODEV; 5413 5414 r8168_phy_ocp_write(tp, regnum, val); 5415 5416 return 0; 5417 } 5418 5419 static int r8169_mdio_register(struct rtl8169_private *tp) 5420 { 5421 struct pci_dev *pdev = tp->pci_dev; 5422 struct mii_bus *new_bus; 5423 int ret; 5424 5425 /* On some boards with this chip version the BIOS is buggy and misses 5426 * to reset the PHY page selector. This results in the PHY ID read 5427 * accessing registers on a different page, returning a more or 5428 * less random value. Fix this by resetting the page selector first. 5429 */ 5430 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5431 tp->mac_version == RTL_GIGA_MAC_VER_26) 5432 r8169_mdio_write(tp, 0x1f, 0); 5433 5434 new_bus = devm_mdiobus_alloc(&pdev->dev); 5435 if (!new_bus) 5436 return -ENOMEM; 5437 5438 new_bus->name = "r8169"; 5439 new_bus->priv = tp; 5440 new_bus->parent = &pdev->dev; 5441 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5442 new_bus->phy_mask = GENMASK(31, 1); 5443 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5444 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5445 5446 new_bus->read = r8169_mdio_read_reg; 5447 new_bus->write = r8169_mdio_write_reg; 5448 5449 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) { 5450 new_bus->read_c45 = r8169_mdio_read_reg_c45; 5451 new_bus->write_c45 = r8169_mdio_write_reg_c45; 5452 } 5453 5454 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5455 if (ret) 5456 return ret; 5457 5458 tp->phydev = mdiobus_get_phy(new_bus, 0); 5459 if (!tp->phydev) { 5460 return -ENODEV; 5461 } else if (!tp->phydev->drv) { 5462 /* Most chip versions fail with the genphy driver. 5463 * Therefore ensure that the dedicated PHY driver is loaded. 5464 */ 5465 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5466 tp->phydev->phy_id); 5467 return -EUNATCH; 5468 } 5469 5470 tp->phydev->mac_managed_pm = true; 5471 if (rtl_supports_eee(tp)) 5472 phy_support_eee(tp->phydev); 5473 phy_support_asym_pause(tp->phydev); 5474 5475 /* mimic behavior of r8125/r8126 vendor drivers */ 5476 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 5477 phy_disable_eee_mode(tp->phydev, 5478 ETHTOOL_LINK_MODE_2500baseT_Full_BIT); 5479 5480 /* PHY will be woken up in rtl_open() */ 5481 phy_suspend(tp->phydev); 5482 5483 return 0; 5484 } 5485 5486 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5487 { 5488 rtl_enable_rxdvgate(tp); 5489 5490 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5491 msleep(1); 5492 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5493 5494 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5495 r8168g_wait_ll_share_fifo_ready(tp); 5496 5497 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5498 r8168g_wait_ll_share_fifo_ready(tp); 5499 } 5500 5501 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5502 { 5503 rtl_enable_rxdvgate(tp); 5504 5505 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5506 msleep(1); 5507 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5508 5509 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5510 r8168g_wait_ll_share_fifo_ready(tp); 5511 5512 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5513 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5514 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5515 r8168g_wait_ll_share_fifo_ready(tp); 5516 } 5517 5518 static void rtl_hw_initialize(struct rtl8169_private *tp) 5519 { 5520 switch (tp->mac_version) { 5521 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_52: 5522 rtl8168ep_stop_cmac(tp); 5523 fallthrough; 5524 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5525 rtl_hw_init_8168g(tp); 5526 break; 5527 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 5528 rtl_hw_init_8125(tp); 5529 break; 5530 default: 5531 break; 5532 } 5533 } 5534 5535 static int rtl_jumbo_max(struct rtl8169_private *tp) 5536 { 5537 /* Non-GBit versions don't support jumbo frames */ 5538 if (!tp->supports_gmii) 5539 return 0; 5540 5541 switch (tp->mac_version) { 5542 /* RTL8169 */ 5543 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5544 return JUMBO_7K; 5545 /* RTL8168b */ 5546 case RTL_GIGA_MAC_VER_17: 5547 return JUMBO_4K; 5548 /* RTL8168c */ 5549 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5550 return JUMBO_6K; 5551 /* RTL8125/8126 */ 5552 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: 5553 return JUMBO_16K; 5554 default: 5555 return JUMBO_9K; 5556 } 5557 } 5558 5559 static void rtl_init_mac_address(struct rtl8169_private *tp) 5560 { 5561 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5562 struct net_device *dev = tp->dev; 5563 int rc; 5564 5565 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5566 if (!rc) 5567 goto done; 5568 5569 rtl_read_mac_address(tp, mac_addr); 5570 if (is_valid_ether_addr(mac_addr)) 5571 goto done; 5572 5573 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5574 if (is_valid_ether_addr(mac_addr)) 5575 goto done; 5576 5577 eth_random_addr(mac_addr); 5578 dev->addr_assign_type = NET_ADDR_RANDOM; 5579 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5580 done: 5581 eth_hw_addr_set(dev, mac_addr); 5582 rtl_rar_set(tp, mac_addr); 5583 } 5584 5585 /* register is set if system vendor successfully tested ASPM 1.2 */ 5586 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5587 { 5588 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5589 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5590 return true; 5591 5592 return false; 5593 } 5594 5595 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5596 { 5597 const struct rtl_chip_info *chip; 5598 const char *ext_xid_str = ""; 5599 struct rtl8169_private *tp; 5600 int jumbo_max, region, rc; 5601 struct net_device *dev; 5602 u32 txconfig; 5603 u32 xid; 5604 5605 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5606 if (!dev) 5607 return -ENOMEM; 5608 5609 SET_NETDEV_DEV(dev, &pdev->dev); 5610 dev->netdev_ops = &rtl_netdev_ops; 5611 tp = netdev_priv(dev); 5612 tp->dev = dev; 5613 tp->pci_dev = pdev; 5614 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5615 tp->ocp_base = OCP_STD_PHY_BASE; 5616 5617 raw_spin_lock_init(&tp->mac_ocp_lock); 5618 mutex_init(&tp->led_lock); 5619 5620 /* Get the *optional* external "ether_clk" used on some boards */ 5621 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5622 if (IS_ERR(tp->clk)) 5623 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5624 5625 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5626 rc = pcim_enable_device(pdev); 5627 if (rc < 0) 5628 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5629 5630 if (pcim_set_mwi(pdev) < 0) 5631 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5632 5633 /* use first MMIO region */ 5634 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5635 if (region < 0) 5636 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5637 5638 tp->mmio_addr = pcim_iomap_region(pdev, region, KBUILD_MODNAME); 5639 if (IS_ERR(tp->mmio_addr)) 5640 return dev_err_probe(&pdev->dev, PTR_ERR(tp->mmio_addr), 5641 "cannot remap MMIO, aborting\n"); 5642 5643 txconfig = RTL_R32(tp, TxConfig); 5644 if (txconfig == ~0U) 5645 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5646 5647 xid = (txconfig >> 20) & 0xfcf; 5648 5649 /* Identify chip attached to board */ 5650 chip = rtl8169_get_chip_version(xid, tp->supports_gmii); 5651 5652 if (chip->mac_version == RTL_GIGA_MAC_VER_EXTENDED) { 5653 ext_xid_str = "ext"; 5654 xid = RTL_R32(tp, TX_CONFIG_V2); 5655 chip = rtl8169_get_extended_chip_version(xid); 5656 } 5657 if (chip->mac_version == RTL_GIGA_MAC_NONE) 5658 return dev_err_probe(&pdev->dev, -ENODEV, 5659 "unknown chip %sXID %x, contact r8169 maintainers (see MAINTAINERS file)\n", 5660 ext_xid_str, xid); 5661 tp->mac_version = chip->mac_version; 5662 tp->fw_name = chip->fw_name; 5663 5664 /* Disable ASPM L1 as that cause random device stop working 5665 * problems as well as full system hangs for some PCIe devices users. 5666 */ 5667 if (rtl_aspm_is_safe(tp)) { 5668 dev_info(&pdev->dev, "System vendor flags ASPM as safe\n"); 5669 rc = 0; 5670 } else { 5671 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5672 } 5673 tp->aspm_manageable = !rc; 5674 5675 if (rtl_is_8125(tp)) { 5676 u16 data = r8168_mac_ocp_read(tp, 0xd006); 5677 5678 if ((data & 0xff) == 0x07) 5679 tp->sfp_mode = true; 5680 } 5681 5682 tp->dash_type = rtl_get_dash_type(tp); 5683 tp->dash_enabled = rtl_dash_is_enabled(tp); 5684 5685 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5686 5687 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5688 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5689 dev->features |= NETIF_F_HIGHDMA; 5690 5691 rtl_init_rxcfg(tp); 5692 5693 rtl8169_irq_mask_and_ack(tp); 5694 5695 rtl_hw_initialize(tp); 5696 5697 rtl_hw_reset(tp); 5698 5699 rc = rtl_alloc_irq(tp); 5700 if (rc < 0) 5701 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5702 5703 tp->irq = pci_irq_vector(pdev, 0); 5704 5705 INIT_WORK(&tp->wk.work, rtl_task); 5706 disable_work(&tp->wk.work); 5707 5708 rtl_init_mac_address(tp); 5709 5710 dev->ethtool_ops = &rtl8169_ethtool_ops; 5711 5712 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5713 5714 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5715 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5716 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5717 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5718 5719 /* 5720 * Pretend we are using VLANs; This bypasses a nasty bug where 5721 * Interrupts stop flowing on high load on 8110SCd controllers. 5722 */ 5723 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5724 /* Disallow toggling */ 5725 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5726 5727 if (rtl_chip_supports_csum_v2(tp)) 5728 dev->hw_features |= NETIF_F_IPV6_CSUM; 5729 5730 dev->features |= dev->hw_features; 5731 5732 if (rtl_chip_supports_csum_v2(tp)) { 5733 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5734 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5735 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5736 } else { 5737 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5738 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5739 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5740 } 5741 5742 /* There has been a number of reports that using SG/TSO results in 5743 * tx timeouts. However for a lot of people SG/TSO works fine. 5744 * It's not fully clear which chip versions are affected. Vendor 5745 * drivers enable SG/TSO for certain chip versions per default, 5746 * let's mimic this here. On other chip versions users can 5747 * use ethtool to enable SG/TSO, use at own risk! 5748 */ 5749 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5750 tp->mac_version != RTL_GIGA_MAC_VER_61) 5751 dev->features |= dev->hw_features; 5752 5753 dev->hw_features |= NETIF_F_RXALL; 5754 dev->hw_features |= NETIF_F_RXFCS; 5755 5756 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5757 5758 netdev_sw_irq_coalesce_default_on(dev); 5759 5760 /* configure chip for default features */ 5761 rtl8169_set_features(dev, dev->features); 5762 5763 if (!tp->dash_enabled) { 5764 rtl_set_d3_pll_down(tp, true); 5765 } else { 5766 rtl_set_d3_pll_down(tp, false); 5767 dev->ethtool->wol_enabled = 1; 5768 } 5769 5770 jumbo_max = rtl_jumbo_max(tp); 5771 if (jumbo_max) 5772 dev->max_mtu = jumbo_max; 5773 5774 rtl_set_irq_mask(tp); 5775 5776 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5777 &tp->counters_phys_addr, 5778 GFP_KERNEL); 5779 if (!tp->counters) 5780 return -ENOMEM; 5781 5782 pci_set_drvdata(pdev, tp); 5783 5784 rc = r8169_mdio_register(tp); 5785 if (rc) 5786 return rc; 5787 5788 rc = register_netdev(dev); 5789 if (rc) 5790 return rc; 5791 5792 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5793 if (rtl_is_8125(tp)) 5794 tp->leds = rtl8125_init_leds(dev); 5795 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5796 tp->leds = rtl8168_init_leds(dev); 5797 } 5798 5799 netdev_info(dev, "%s, %pM, %sXID %x, IRQ %d\n", 5800 chip->name, dev->dev_addr, ext_xid_str, xid, tp->irq); 5801 5802 if (jumbo_max) 5803 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5804 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5805 "ok" : "ko"); 5806 5807 if (tp->dash_type != RTL_DASH_NONE) { 5808 netdev_info(dev, "DASH %s\n", 5809 tp->dash_enabled ? "enabled" : "disabled"); 5810 rtl8168_driver_start(tp); 5811 } 5812 5813 if (pci_dev_run_wake(pdev)) 5814 pm_runtime_put_sync(&pdev->dev); 5815 5816 return 0; 5817 } 5818 5819 static struct pci_driver rtl8169_pci_driver = { 5820 .name = KBUILD_MODNAME, 5821 .id_table = rtl8169_pci_tbl, 5822 .probe = rtl_init_one, 5823 .remove = rtl_remove_one, 5824 .shutdown = rtl_shutdown, 5825 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5826 }; 5827 5828 module_pci_driver(rtl8169_pci_driver); 5829