1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 59 60 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 61 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 62 63 #define R8169_REGS_SIZE 256 64 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 65 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 66 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 67 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 68 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 69 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 70 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 71 72 #define OCP_STD_PHY_BASE 0xa400 73 74 #define RTL_CFG_NO_GBIT 1 75 76 /* write/read MMIO register */ 77 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 81 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 82 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 83 84 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 89 static const struct { 90 const char *name; 91 const char *fw_name; 92 } rtl_chip_infos[] = { 93 /* PCI devices. */ 94 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 95 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 96 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 97 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 98 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 99 /* PCI-E devices. */ 100 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 102 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 103 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 104 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 105 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 106 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 108 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 109 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 115 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 116 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 117 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 118 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 119 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 121 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 122 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 123 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 124 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 125 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 126 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 127 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 128 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 129 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 130 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 131 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 132 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 133 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 134 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 135 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 136 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 137 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 138 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 139 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 140 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 141 }; 142 143 static const struct pci_device_id rtl8169_pci_tbl[] = { 144 { PCI_VDEVICE(REALTEK, 0x2502) }, 145 { PCI_VDEVICE(REALTEK, 0x2600) }, 146 { PCI_VDEVICE(REALTEK, 0x8129) }, 147 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 148 { PCI_VDEVICE(REALTEK, 0x8161) }, 149 { PCI_VDEVICE(REALTEK, 0x8162) }, 150 { PCI_VDEVICE(REALTEK, 0x8167) }, 151 { PCI_VDEVICE(REALTEK, 0x8168) }, 152 { PCI_VDEVICE(NCUBE, 0x8168) }, 153 { PCI_VDEVICE(REALTEK, 0x8169) }, 154 { PCI_VENDOR_ID_DLINK, 0x4300, 155 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 156 { PCI_VDEVICE(DLINK, 0x4300) }, 157 { PCI_VDEVICE(DLINK, 0x4302) }, 158 { PCI_VDEVICE(AT, 0xc107) }, 159 { PCI_VDEVICE(USR, 0x0116) }, 160 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 161 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 162 { PCI_VDEVICE(REALTEK, 0x8125) }, 163 { PCI_VDEVICE(REALTEK, 0x8126) }, 164 { PCI_VDEVICE(REALTEK, 0x3000) }, 165 {} 166 }; 167 168 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 169 170 enum rtl_registers { 171 MAC0 = 0, /* Ethernet hardware address. */ 172 MAC4 = 4, 173 MAR0 = 8, /* Multicast filter. */ 174 CounterAddrLow = 0x10, 175 CounterAddrHigh = 0x14, 176 TxDescStartAddrLow = 0x20, 177 TxDescStartAddrHigh = 0x24, 178 TxHDescStartAddrLow = 0x28, 179 TxHDescStartAddrHigh = 0x2c, 180 FLASH = 0x30, 181 ERSR = 0x36, 182 ChipCmd = 0x37, 183 TxPoll = 0x38, 184 IntrMask = 0x3c, 185 IntrStatus = 0x3e, 186 187 TxConfig = 0x40, 188 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 189 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 190 191 RxConfig = 0x44, 192 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 193 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 194 #define RXCFG_FIFO_SHIFT 13 195 /* No threshold before first PCI xfer */ 196 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 197 #define RX_EARLY_OFF (1 << 11) 198 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 199 #define RXCFG_DMA_SHIFT 8 200 /* Unlimited maximum PCI burst. */ 201 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 202 203 Cfg9346 = 0x50, 204 Config0 = 0x51, 205 Config1 = 0x52, 206 Config2 = 0x53, 207 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 208 209 Config3 = 0x54, 210 Config4 = 0x55, 211 Config5 = 0x56, 212 PHYAR = 0x60, 213 PHYstatus = 0x6c, 214 RxMaxSize = 0xda, 215 CPlusCmd = 0xe0, 216 IntrMitigate = 0xe2, 217 218 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 219 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 220 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 221 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 222 223 #define RTL_COALESCE_T_MAX 0x0fU 224 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 225 226 RxDescAddrLow = 0xe4, 227 RxDescAddrHigh = 0xe8, 228 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 229 230 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 231 232 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 233 234 #define TxPacketMax (8064 >> 7) 235 #define EarlySize 0x27 236 237 FuncEvent = 0xf0, 238 FuncEventMask = 0xf4, 239 FuncPresetState = 0xf8, 240 IBCR0 = 0xf8, 241 IBCR2 = 0xf9, 242 IBIMR0 = 0xfa, 243 IBISR0 = 0xfb, 244 FuncForceEvent = 0xfc, 245 }; 246 247 enum rtl8168_8101_registers { 248 CSIDR = 0x64, 249 CSIAR = 0x68, 250 #define CSIAR_FLAG 0x80000000 251 #define CSIAR_WRITE_CMD 0x80000000 252 #define CSIAR_BYTE_ENABLE 0x0000f000 253 #define CSIAR_ADDR_MASK 0x00000fff 254 PMCH = 0x6f, 255 #define D3COLD_NO_PLL_DOWN BIT(7) 256 #define D3HOT_NO_PLL_DOWN BIT(6) 257 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 258 EPHYAR = 0x80, 259 #define EPHYAR_FLAG 0x80000000 260 #define EPHYAR_WRITE_CMD 0x80000000 261 #define EPHYAR_REG_MASK 0x1f 262 #define EPHYAR_REG_SHIFT 16 263 #define EPHYAR_DATA_MASK 0xffff 264 DLLPR = 0xd0, 265 #define PFM_EN (1 << 6) 266 #define TX_10M_PS_EN (1 << 7) 267 DBG_REG = 0xd1, 268 #define FIX_NAK_1 (1 << 4) 269 #define FIX_NAK_2 (1 << 3) 270 TWSI = 0xd2, 271 MCU = 0xd3, 272 #define NOW_IS_OOB (1 << 7) 273 #define TX_EMPTY (1 << 5) 274 #define RX_EMPTY (1 << 4) 275 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 276 #define EN_NDP (1 << 3) 277 #define EN_OOB_RESET (1 << 2) 278 #define LINK_LIST_RDY (1 << 1) 279 EFUSEAR = 0xdc, 280 #define EFUSEAR_FLAG 0x80000000 281 #define EFUSEAR_WRITE_CMD 0x80000000 282 #define EFUSEAR_READ_CMD 0x00000000 283 #define EFUSEAR_REG_MASK 0x03ff 284 #define EFUSEAR_REG_SHIFT 8 285 #define EFUSEAR_DATA_MASK 0xff 286 MISC_1 = 0xf2, 287 #define PFM_D3COLD_EN (1 << 6) 288 }; 289 290 enum rtl8168_registers { 291 LED_CTRL = 0x18, 292 LED_FREQ = 0x1a, 293 EEE_LED = 0x1b, 294 ERIDR = 0x70, 295 ERIAR = 0x74, 296 #define ERIAR_FLAG 0x80000000 297 #define ERIAR_WRITE_CMD 0x80000000 298 #define ERIAR_READ_CMD 0x00000000 299 #define ERIAR_ADDR_BYTE_ALIGN 4 300 #define ERIAR_TYPE_SHIFT 16 301 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 303 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_MASK_SHIFT 12 306 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 308 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 311 EPHY_RXER_NUM = 0x7c, 312 OCPDR = 0xb0, /* OCP GPHY access */ 313 #define OCPDR_WRITE_CMD 0x80000000 314 #define OCPDR_READ_CMD 0x00000000 315 #define OCPDR_REG_MASK 0x7f 316 #define OCPDR_GPHY_REG_SHIFT 16 317 #define OCPDR_DATA_MASK 0xffff 318 OCPAR = 0xb4, 319 #define OCPAR_FLAG 0x80000000 320 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 321 #define OCPAR_GPHY_READ_CMD 0x0000f060 322 GPHY_OCP = 0xb8, 323 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 324 MISC = 0xf0, /* 8168e only. */ 325 #define TXPLA_RST (1 << 29) 326 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 327 #define PWM_EN (1 << 22) 328 #define RXDV_GATED_EN (1 << 19) 329 #define EARLY_TALLY_EN (1 << 16) 330 }; 331 332 enum rtl8125_registers { 333 LEDSEL0 = 0x18, 334 INT_CFG0_8125 = 0x34, 335 #define INT_CFG0_ENABLE_8125 BIT(0) 336 #define INT_CFG0_CLKREQEN BIT(3) 337 IntrMask_8125 = 0x38, 338 IntrStatus_8125 = 0x3c, 339 INT_CFG1_8125 = 0x7a, 340 LEDSEL2 = 0x84, 341 LEDSEL1 = 0x86, 342 TxPoll_8125 = 0x90, 343 LEDSEL3 = 0x96, 344 MAC0_BKP = 0x19e0, 345 EEE_TXIDLE_TIMER_8125 = 0x6048, 346 }; 347 348 #define LEDSEL_MASK_8125 0x23f 349 350 #define RX_VLAN_INNER_8125 BIT(22) 351 #define RX_VLAN_OUTER_8125 BIT(23) 352 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 353 354 #define RX_FETCH_DFLT_8125 (8 << 27) 355 356 enum rtl_register_content { 357 /* InterruptStatusBits */ 358 SYSErr = 0x8000, 359 PCSTimeout = 0x4000, 360 SWInt = 0x0100, 361 TxDescUnavail = 0x0080, 362 RxFIFOOver = 0x0040, 363 LinkChg = 0x0020, 364 RxOverflow = 0x0010, 365 TxErr = 0x0008, 366 TxOK = 0x0004, 367 RxErr = 0x0002, 368 RxOK = 0x0001, 369 370 /* RxStatusDesc */ 371 RxRWT = (1 << 22), 372 RxRES = (1 << 21), 373 RxRUNT = (1 << 20), 374 RxCRC = (1 << 19), 375 376 /* ChipCmdBits */ 377 StopReq = 0x80, 378 CmdReset = 0x10, 379 CmdRxEnb = 0x08, 380 CmdTxEnb = 0x04, 381 RxBufEmpty = 0x01, 382 383 /* TXPoll register p.5 */ 384 HPQ = 0x80, /* Poll cmd on the high prio queue */ 385 NPQ = 0x40, /* Poll cmd on the low prio queue */ 386 FSWInt = 0x01, /* Forced software interrupt */ 387 388 /* Cfg9346Bits */ 389 Cfg9346_Lock = 0x00, 390 Cfg9346_Unlock = 0xc0, 391 392 /* rx_mode_bits */ 393 AcceptErr = 0x20, 394 AcceptRunt = 0x10, 395 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 396 AcceptBroadcast = 0x08, 397 AcceptMulticast = 0x04, 398 AcceptMyPhys = 0x02, 399 AcceptAllPhys = 0x01, 400 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 401 #define RX_CONFIG_ACCEPT_MASK 0x3f 402 403 /* TxConfigBits */ 404 TxInterFrameGapShift = 24, 405 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 406 407 /* Config1 register p.24 */ 408 LEDS1 = (1 << 7), 409 LEDS0 = (1 << 6), 410 Speed_down = (1 << 4), 411 MEMMAP = (1 << 3), 412 IOMAP = (1 << 2), 413 VPD = (1 << 1), 414 PMEnable = (1 << 0), /* Power Management Enable */ 415 416 /* Config2 register p. 25 */ 417 ClkReqEn = (1 << 7), /* Clock Request Enable */ 418 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 419 PCI_Clock_66MHz = 0x01, 420 PCI_Clock_33MHz = 0x00, 421 422 /* Config3 register p.25 */ 423 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 424 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 425 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 426 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 427 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 428 429 /* Config4 register */ 430 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 431 432 /* Config5 register p.27 */ 433 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 434 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 435 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 436 Spi_en = (1 << 3), 437 LanWake = (1 << 1), /* LanWake enable/disable */ 438 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 439 ASPM_en = (1 << 0), /* ASPM enable */ 440 441 /* CPlusCmd p.31 */ 442 EnableBist = (1 << 15), // 8168 8101 443 Mac_dbgo_oe = (1 << 14), // 8168 8101 444 EnAnaPLL = (1 << 14), // 8169 445 Normal_mode = (1 << 13), // unused 446 Force_half_dup = (1 << 12), // 8168 8101 447 Force_rxflow_en = (1 << 11), // 8168 8101 448 Force_txflow_en = (1 << 10), // 8168 8101 449 Cxpl_dbg_sel = (1 << 9), // 8168 8101 450 ASF = (1 << 8), // 8168 8101 451 PktCntrDisable = (1 << 7), // 8168 8101 452 Mac_dbgo_sel = 0x001c, // 8168 453 RxVlan = (1 << 6), 454 RxChkSum = (1 << 5), 455 PCIDAC = (1 << 4), 456 PCIMulRW = (1 << 3), 457 #define INTT_MASK GENMASK(1, 0) 458 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 459 460 /* rtl8169_PHYstatus */ 461 TBI_Enable = 0x80, 462 TxFlowCtrl = 0x40, 463 RxFlowCtrl = 0x20, 464 _1000bpsF = 0x10, 465 _100bps = 0x08, 466 _10bps = 0x04, 467 LinkStatus = 0x02, 468 FullDup = 0x01, 469 470 /* ResetCounterCommand */ 471 CounterReset = 0x1, 472 473 /* DumpCounterCommand */ 474 CounterDump = 0x8, 475 476 /* magic enable v2 */ 477 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 478 }; 479 480 enum rtl_desc_bit { 481 /* First doubleword. */ 482 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 483 RingEnd = (1 << 30), /* End of descriptor ring */ 484 FirstFrag = (1 << 29), /* First segment of a packet */ 485 LastFrag = (1 << 28), /* Final segment of a packet */ 486 }; 487 488 /* Generic case. */ 489 enum rtl_tx_desc_bit { 490 /* First doubleword. */ 491 TD_LSO = (1 << 27), /* Large Send Offload */ 492 #define TD_MSS_MAX 0x07ffu /* MSS value */ 493 494 /* Second doubleword. */ 495 TxVlanTag = (1 << 17), /* Add VLAN tag */ 496 }; 497 498 /* 8169, 8168b and 810x except 8102e. */ 499 enum rtl_tx_desc_bit_0 { 500 /* First doubleword. */ 501 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 502 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 503 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 504 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 505 }; 506 507 /* 8102e, 8168c and beyond. */ 508 enum rtl_tx_desc_bit_1 { 509 /* First doubleword. */ 510 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 511 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 512 #define GTTCPHO_SHIFT 18 513 #define GTTCPHO_MAX 0x7f 514 515 /* Second doubleword. */ 516 #define TCPHO_SHIFT 18 517 #define TCPHO_MAX 0x3ff 518 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 519 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 520 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 521 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 522 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 523 }; 524 525 enum rtl_rx_desc_bit { 526 /* Rx private */ 527 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 528 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 529 530 #define RxProtoUDP (PID1) 531 #define RxProtoTCP (PID0) 532 #define RxProtoIP (PID1 | PID0) 533 #define RxProtoMask RxProtoIP 534 535 IPFail = (1 << 16), /* IP checksum failed */ 536 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 537 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 538 539 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 540 541 RxVlanTag = (1 << 16), /* VLAN tag available */ 542 }; 543 544 #define RTL_GSO_MAX_SIZE_V1 32000 545 #define RTL_GSO_MAX_SEGS_V1 24 546 #define RTL_GSO_MAX_SIZE_V2 64000 547 #define RTL_GSO_MAX_SEGS_V2 64 548 549 struct TxDesc { 550 __le32 opts1; 551 __le32 opts2; 552 __le64 addr; 553 }; 554 555 struct RxDesc { 556 __le32 opts1; 557 __le32 opts2; 558 __le64 addr; 559 }; 560 561 struct ring_info { 562 struct sk_buff *skb; 563 u32 len; 564 }; 565 566 struct rtl8169_counters { 567 __le64 tx_packets; 568 __le64 rx_packets; 569 __le64 tx_errors; 570 __le32 rx_errors; 571 __le16 rx_missed; 572 __le16 align_errors; 573 __le32 tx_one_collision; 574 __le32 tx_multi_collision; 575 __le64 rx_unicast; 576 __le64 rx_broadcast; 577 __le32 rx_multicast; 578 __le16 tx_aborted; 579 __le16 tx_underun; 580 }; 581 582 struct rtl8169_tc_offsets { 583 bool inited; 584 __le64 tx_errors; 585 __le32 tx_multi_collision; 586 __le16 tx_aborted; 587 __le16 rx_missed; 588 }; 589 590 enum rtl_flag { 591 RTL_FLAG_TASK_ENABLED = 0, 592 RTL_FLAG_TASK_RESET_PENDING, 593 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 594 RTL_FLAG_TASK_TX_TIMEOUT, 595 RTL_FLAG_MAX 596 }; 597 598 enum rtl_dash_type { 599 RTL_DASH_NONE, 600 RTL_DASH_DP, 601 RTL_DASH_EP, 602 }; 603 604 struct rtl8169_private { 605 void __iomem *mmio_addr; /* memory map physical address */ 606 struct pci_dev *pci_dev; 607 struct net_device *dev; 608 struct phy_device *phydev; 609 struct napi_struct napi; 610 enum mac_version mac_version; 611 enum rtl_dash_type dash_type; 612 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 613 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 614 u32 dirty_tx; 615 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 616 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 617 dma_addr_t TxPhyAddr; 618 dma_addr_t RxPhyAddr; 619 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 620 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 621 u16 cp_cmd; 622 u16 tx_lpi_timer; 623 u32 irq_mask; 624 int irq; 625 struct clk *clk; 626 627 struct { 628 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 629 struct work_struct work; 630 } wk; 631 632 raw_spinlock_t config25_lock; 633 raw_spinlock_t mac_ocp_lock; 634 struct mutex led_lock; /* serialize LED ctrl RMW access */ 635 636 raw_spinlock_t cfg9346_usage_lock; 637 int cfg9346_usage_count; 638 639 unsigned supports_gmii:1; 640 unsigned aspm_manageable:1; 641 unsigned dash_enabled:1; 642 dma_addr_t counters_phys_addr; 643 struct rtl8169_counters *counters; 644 struct rtl8169_tc_offsets tc_offset; 645 u32 saved_wolopts; 646 647 const char *fw_name; 648 struct rtl_fw *rtl_fw; 649 650 u32 ocp_base; 651 }; 652 653 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 654 655 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 656 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 657 MODULE_SOFTDEP("pre: realtek"); 658 MODULE_LICENSE("GPL"); 659 MODULE_FIRMWARE(FIRMWARE_8168D_1); 660 MODULE_FIRMWARE(FIRMWARE_8168D_2); 661 MODULE_FIRMWARE(FIRMWARE_8168E_1); 662 MODULE_FIRMWARE(FIRMWARE_8168E_2); 663 MODULE_FIRMWARE(FIRMWARE_8168E_3); 664 MODULE_FIRMWARE(FIRMWARE_8105E_1); 665 MODULE_FIRMWARE(FIRMWARE_8168F_1); 666 MODULE_FIRMWARE(FIRMWARE_8168F_2); 667 MODULE_FIRMWARE(FIRMWARE_8402_1); 668 MODULE_FIRMWARE(FIRMWARE_8411_1); 669 MODULE_FIRMWARE(FIRMWARE_8411_2); 670 MODULE_FIRMWARE(FIRMWARE_8106E_1); 671 MODULE_FIRMWARE(FIRMWARE_8106E_2); 672 MODULE_FIRMWARE(FIRMWARE_8168G_2); 673 MODULE_FIRMWARE(FIRMWARE_8168G_3); 674 MODULE_FIRMWARE(FIRMWARE_8168H_2); 675 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 676 MODULE_FIRMWARE(FIRMWARE_8107E_2); 677 MODULE_FIRMWARE(FIRMWARE_8125A_3); 678 MODULE_FIRMWARE(FIRMWARE_8125B_2); 679 MODULE_FIRMWARE(FIRMWARE_8126A_2); 680 681 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 682 { 683 return &tp->pci_dev->dev; 684 } 685 686 static void rtl_lock_config_regs(struct rtl8169_private *tp) 687 { 688 unsigned long flags; 689 690 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 691 if (!--tp->cfg9346_usage_count) 692 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 693 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 694 } 695 696 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 697 { 698 unsigned long flags; 699 700 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 701 if (!tp->cfg9346_usage_count++) 702 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 703 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 704 } 705 706 static void rtl_pci_commit(struct rtl8169_private *tp) 707 { 708 /* Read an arbitrary register to commit a preceding PCI write */ 709 RTL_R8(tp, ChipCmd); 710 } 711 712 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 713 { 714 unsigned long flags; 715 u8 val; 716 717 raw_spin_lock_irqsave(&tp->config25_lock, flags); 718 val = RTL_R8(tp, Config2); 719 RTL_W8(tp, Config2, (val & ~clear) | set); 720 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 721 } 722 723 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 724 { 725 unsigned long flags; 726 u8 val; 727 728 raw_spin_lock_irqsave(&tp->config25_lock, flags); 729 val = RTL_R8(tp, Config5); 730 RTL_W8(tp, Config5, (val & ~clear) | set); 731 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 732 } 733 734 static bool rtl_is_8125(struct rtl8169_private *tp) 735 { 736 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 737 } 738 739 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 740 { 741 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 742 tp->mac_version != RTL_GIGA_MAC_VER_39 && 743 tp->mac_version <= RTL_GIGA_MAC_VER_53; 744 } 745 746 static bool rtl_supports_eee(struct rtl8169_private *tp) 747 { 748 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 749 tp->mac_version != RTL_GIGA_MAC_VER_37 && 750 tp->mac_version != RTL_GIGA_MAC_VER_39; 751 } 752 753 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 754 { 755 int i; 756 757 for (i = 0; i < ETH_ALEN; i++) 758 mac[i] = RTL_R8(tp, reg + i); 759 } 760 761 struct rtl_cond { 762 bool (*check)(struct rtl8169_private *); 763 const char *msg; 764 }; 765 766 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 767 unsigned long usecs, int n, bool high) 768 { 769 int i; 770 771 for (i = 0; i < n; i++) { 772 if (c->check(tp) == high) 773 return true; 774 fsleep(usecs); 775 } 776 777 if (net_ratelimit()) 778 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 779 c->msg, !high, n, usecs); 780 return false; 781 } 782 783 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 784 const struct rtl_cond *c, 785 unsigned long d, int n) 786 { 787 return rtl_loop_wait(tp, c, d, n, true); 788 } 789 790 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 791 const struct rtl_cond *c, 792 unsigned long d, int n) 793 { 794 return rtl_loop_wait(tp, c, d, n, false); 795 } 796 797 #define DECLARE_RTL_COND(name) \ 798 static bool name ## _check(struct rtl8169_private *); \ 799 \ 800 static const struct rtl_cond name = { \ 801 .check = name ## _check, \ 802 .msg = #name \ 803 }; \ 804 \ 805 static bool name ## _check(struct rtl8169_private *tp) 806 807 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 808 { 809 struct device *dev = tp_to_dev(tp); 810 int ret; 811 812 ret = pm_runtime_resume_and_get(dev); 813 if (ret < 0) 814 return ret; 815 816 mutex_lock(&tp->led_lock); 817 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 818 mutex_unlock(&tp->led_lock); 819 820 pm_runtime_put_sync(dev); 821 822 return 0; 823 } 824 825 int rtl8168_get_led_mode(struct rtl8169_private *tp) 826 { 827 struct device *dev = tp_to_dev(tp); 828 int ret; 829 830 ret = pm_runtime_resume_and_get(dev); 831 if (ret < 0) 832 return ret; 833 834 ret = RTL_R16(tp, LED_CTRL); 835 836 pm_runtime_put_sync(dev); 837 838 return ret; 839 } 840 841 static int rtl8125_get_led_reg(int index) 842 { 843 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 844 845 return led_regs[index]; 846 } 847 848 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 849 { 850 int reg = rtl8125_get_led_reg(index); 851 struct device *dev = tp_to_dev(tp); 852 int ret; 853 u16 val; 854 855 ret = pm_runtime_resume_and_get(dev); 856 if (ret < 0) 857 return ret; 858 859 mutex_lock(&tp->led_lock); 860 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 861 RTL_W16(tp, reg, val | mode); 862 mutex_unlock(&tp->led_lock); 863 864 pm_runtime_put_sync(dev); 865 866 return 0; 867 } 868 869 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 870 { 871 int reg = rtl8125_get_led_reg(index); 872 struct device *dev = tp_to_dev(tp); 873 int ret; 874 875 ret = pm_runtime_resume_and_get(dev); 876 if (ret < 0) 877 return ret; 878 879 ret = RTL_R16(tp, reg); 880 881 pm_runtime_put_sync(dev); 882 883 return ret; 884 } 885 886 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 887 char *buf, int buf_len) 888 { 889 struct pci_dev *pdev = tp->pci_dev; 890 char pdom[8], pfun[8]; 891 int domain; 892 893 domain = pci_domain_nr(pdev->bus); 894 if (domain) 895 snprintf(pdom, sizeof(pdom), "P%d", domain); 896 else 897 pdom[0] = '\0'; 898 899 if (pdev->multifunction) 900 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 901 else 902 pfun[0] = '\0'; 903 904 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 905 PCI_SLOT(pdev->devfn), pfun, idx); 906 } 907 908 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 909 { 910 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 911 if (type == ERIAR_OOB && 912 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 913 tp->mac_version == RTL_GIGA_MAC_VER_53)) 914 *cmd |= 0xf70 << 18; 915 } 916 917 DECLARE_RTL_COND(rtl_eriar_cond) 918 { 919 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 920 } 921 922 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 923 u32 val, int type) 924 { 925 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 926 927 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 928 return; 929 930 RTL_W32(tp, ERIDR, val); 931 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 932 RTL_W32(tp, ERIAR, cmd); 933 934 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 935 } 936 937 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 938 u32 val) 939 { 940 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 941 } 942 943 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 944 { 945 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 946 947 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 948 RTL_W32(tp, ERIAR, cmd); 949 950 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 951 RTL_R32(tp, ERIDR) : ~0; 952 } 953 954 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 955 { 956 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 957 } 958 959 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 960 { 961 u32 val = rtl_eri_read(tp, addr); 962 963 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 964 } 965 966 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 967 { 968 rtl_w0w1_eri(tp, addr, p, 0); 969 } 970 971 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 972 { 973 rtl_w0w1_eri(tp, addr, 0, m); 974 } 975 976 static bool rtl_ocp_reg_failure(u32 reg) 977 { 978 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 979 } 980 981 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 982 { 983 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 984 } 985 986 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 987 { 988 if (rtl_ocp_reg_failure(reg)) 989 return; 990 991 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 992 993 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 994 } 995 996 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 997 { 998 if (rtl_ocp_reg_failure(reg)) 999 return 0; 1000 1001 RTL_W32(tp, GPHY_OCP, reg << 15); 1002 1003 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1004 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1005 } 1006 1007 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1008 { 1009 if (rtl_ocp_reg_failure(reg)) 1010 return; 1011 1012 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1013 } 1014 1015 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1016 { 1017 unsigned long flags; 1018 1019 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1020 __r8168_mac_ocp_write(tp, reg, data); 1021 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1022 } 1023 1024 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1025 { 1026 if (rtl_ocp_reg_failure(reg)) 1027 return 0; 1028 1029 RTL_W32(tp, OCPDR, reg << 15); 1030 1031 return RTL_R32(tp, OCPDR); 1032 } 1033 1034 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1035 { 1036 unsigned long flags; 1037 u16 val; 1038 1039 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1040 val = __r8168_mac_ocp_read(tp, reg); 1041 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1042 1043 return val; 1044 } 1045 1046 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1047 u16 set) 1048 { 1049 unsigned long flags; 1050 u16 data; 1051 1052 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1053 data = __r8168_mac_ocp_read(tp, reg); 1054 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1055 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1056 } 1057 1058 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1059 * PHY MCU interrupts before PHY power-down. 1060 */ 1061 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1062 { 1063 switch (tp->mac_version) { 1064 case RTL_GIGA_MAC_VER_40: 1065 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1066 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1067 else 1068 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1069 break; 1070 default: 1071 break; 1072 } 1073 }; 1074 1075 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1076 { 1077 if (reg == 0x1f) { 1078 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1079 return; 1080 } 1081 1082 if (tp->ocp_base != OCP_STD_PHY_BASE) 1083 reg -= 0x10; 1084 1085 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1086 rtl8168g_phy_suspend_quirk(tp, value); 1087 1088 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1089 } 1090 1091 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1092 { 1093 if (reg == 0x1f) 1094 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1095 1096 if (tp->ocp_base != OCP_STD_PHY_BASE) 1097 reg -= 0x10; 1098 1099 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1100 } 1101 1102 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1103 { 1104 if (reg == 0x1f) { 1105 tp->ocp_base = value << 4; 1106 return; 1107 } 1108 1109 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1110 } 1111 1112 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1113 { 1114 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1115 } 1116 1117 DECLARE_RTL_COND(rtl_phyar_cond) 1118 { 1119 return RTL_R32(tp, PHYAR) & 0x80000000; 1120 } 1121 1122 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1123 { 1124 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1125 1126 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1127 /* 1128 * According to hardware specs a 20us delay is required after write 1129 * complete indication, but before sending next command. 1130 */ 1131 udelay(20); 1132 } 1133 1134 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1135 { 1136 int value; 1137 1138 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1139 1140 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1141 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1142 1143 /* 1144 * According to hardware specs a 20us delay is required after read 1145 * complete indication, but before sending next command. 1146 */ 1147 udelay(20); 1148 1149 return value; 1150 } 1151 1152 DECLARE_RTL_COND(rtl_ocpar_cond) 1153 { 1154 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1155 } 1156 1157 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1158 1159 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1160 { 1161 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1162 } 1163 1164 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1165 { 1166 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1167 } 1168 1169 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1170 { 1171 r8168dp_2_mdio_start(tp); 1172 1173 r8169_mdio_write(tp, reg, value); 1174 1175 r8168dp_2_mdio_stop(tp); 1176 } 1177 1178 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1179 { 1180 int value; 1181 1182 /* Work around issue with chip reporting wrong PHY ID */ 1183 if (reg == MII_PHYSID2) 1184 return 0xc912; 1185 1186 r8168dp_2_mdio_start(tp); 1187 1188 value = r8169_mdio_read(tp, reg); 1189 1190 r8168dp_2_mdio_stop(tp); 1191 1192 return value; 1193 } 1194 1195 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1196 { 1197 switch (tp->mac_version) { 1198 case RTL_GIGA_MAC_VER_28: 1199 case RTL_GIGA_MAC_VER_31: 1200 r8168dp_2_mdio_write(tp, location, val); 1201 break; 1202 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 1203 r8168g_mdio_write(tp, location, val); 1204 break; 1205 default: 1206 r8169_mdio_write(tp, location, val); 1207 break; 1208 } 1209 } 1210 1211 static int rtl_readphy(struct rtl8169_private *tp, int location) 1212 { 1213 switch (tp->mac_version) { 1214 case RTL_GIGA_MAC_VER_28: 1215 case RTL_GIGA_MAC_VER_31: 1216 return r8168dp_2_mdio_read(tp, location); 1217 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 1218 return r8168g_mdio_read(tp, location); 1219 default: 1220 return r8169_mdio_read(tp, location); 1221 } 1222 } 1223 1224 DECLARE_RTL_COND(rtl_ephyar_cond) 1225 { 1226 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1227 } 1228 1229 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1230 { 1231 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1232 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1233 1234 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1235 1236 udelay(10); 1237 } 1238 1239 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1240 { 1241 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1242 1243 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1244 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1245 } 1246 1247 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1248 { 1249 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1250 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1251 RTL_R32(tp, OCPDR) : ~0; 1252 } 1253 1254 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1255 { 1256 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1257 } 1258 1259 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1260 u32 data) 1261 { 1262 RTL_W32(tp, OCPDR, data); 1263 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1264 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1265 } 1266 1267 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1268 u32 data) 1269 { 1270 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1271 data, ERIAR_OOB); 1272 } 1273 1274 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1275 { 1276 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1277 1278 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1279 } 1280 1281 #define OOB_CMD_RESET 0x00 1282 #define OOB_CMD_DRIVER_START 0x05 1283 #define OOB_CMD_DRIVER_STOP 0x06 1284 1285 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1286 { 1287 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1288 } 1289 1290 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1291 { 1292 u16 reg; 1293 1294 reg = rtl8168_get_ocp_reg(tp); 1295 1296 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1297 } 1298 1299 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1300 { 1301 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1302 } 1303 1304 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1305 { 1306 return RTL_R8(tp, IBISR0) & 0x20; 1307 } 1308 1309 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1310 { 1311 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1312 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1313 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1314 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1315 } 1316 1317 static void rtl_dash_loop_wait(struct rtl8169_private *tp, 1318 const struct rtl_cond *c, 1319 unsigned long usecs, int n, bool high) 1320 { 1321 if (!tp->dash_enabled) 1322 return; 1323 rtl_loop_wait(tp, c, usecs, n, high); 1324 } 1325 1326 static void rtl_dash_loop_wait_high(struct rtl8169_private *tp, 1327 const struct rtl_cond *c, 1328 unsigned long d, int n) 1329 { 1330 rtl_dash_loop_wait(tp, c, d, n, true); 1331 } 1332 1333 static void rtl_dash_loop_wait_low(struct rtl8169_private *tp, 1334 const struct rtl_cond *c, 1335 unsigned long d, int n) 1336 { 1337 rtl_dash_loop_wait(tp, c, d, n, false); 1338 } 1339 1340 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1341 { 1342 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1343 rtl_dash_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1344 } 1345 1346 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1347 { 1348 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1349 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1350 rtl_dash_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1351 } 1352 1353 static void rtl8168_driver_start(struct rtl8169_private *tp) 1354 { 1355 if (tp->dash_type == RTL_DASH_DP) 1356 rtl8168dp_driver_start(tp); 1357 else 1358 rtl8168ep_driver_start(tp); 1359 } 1360 1361 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1362 { 1363 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1364 rtl_dash_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1365 } 1366 1367 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1368 { 1369 rtl8168ep_stop_cmac(tp); 1370 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1371 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1372 rtl_dash_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1373 } 1374 1375 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1376 { 1377 if (tp->dash_type == RTL_DASH_DP) 1378 rtl8168dp_driver_stop(tp); 1379 else 1380 rtl8168ep_driver_stop(tp); 1381 } 1382 1383 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1384 { 1385 u16 reg = rtl8168_get_ocp_reg(tp); 1386 1387 return r8168dp_ocp_read(tp, reg) & BIT(15); 1388 } 1389 1390 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1391 { 1392 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1393 } 1394 1395 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1396 { 1397 switch (tp->dash_type) { 1398 case RTL_DASH_DP: 1399 return r8168dp_check_dash(tp); 1400 case RTL_DASH_EP: 1401 return r8168ep_check_dash(tp); 1402 default: 1403 return false; 1404 } 1405 } 1406 1407 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1408 { 1409 switch (tp->mac_version) { 1410 case RTL_GIGA_MAC_VER_28: 1411 case RTL_GIGA_MAC_VER_31: 1412 return RTL_DASH_DP; 1413 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1414 return RTL_DASH_EP; 1415 default: 1416 return RTL_DASH_NONE; 1417 } 1418 } 1419 1420 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1421 { 1422 switch (tp->mac_version) { 1423 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1424 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1425 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1426 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65: 1427 if (enable) 1428 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1429 else 1430 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1431 break; 1432 default: 1433 break; 1434 } 1435 } 1436 1437 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1438 { 1439 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1440 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1441 } 1442 1443 DECLARE_RTL_COND(rtl_efusear_cond) 1444 { 1445 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1446 } 1447 1448 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1449 { 1450 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1451 1452 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1453 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1454 } 1455 1456 static u32 rtl_get_events(struct rtl8169_private *tp) 1457 { 1458 if (rtl_is_8125(tp)) 1459 return RTL_R32(tp, IntrStatus_8125); 1460 else 1461 return RTL_R16(tp, IntrStatus); 1462 } 1463 1464 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1465 { 1466 if (rtl_is_8125(tp)) 1467 RTL_W32(tp, IntrStatus_8125, bits); 1468 else 1469 RTL_W16(tp, IntrStatus, bits); 1470 } 1471 1472 static void rtl_irq_disable(struct rtl8169_private *tp) 1473 { 1474 if (rtl_is_8125(tp)) 1475 RTL_W32(tp, IntrMask_8125, 0); 1476 else 1477 RTL_W16(tp, IntrMask, 0); 1478 } 1479 1480 static void rtl_irq_enable(struct rtl8169_private *tp) 1481 { 1482 if (rtl_is_8125(tp)) 1483 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1484 else 1485 RTL_W16(tp, IntrMask, tp->irq_mask); 1486 } 1487 1488 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1489 { 1490 rtl_irq_disable(tp); 1491 rtl_ack_events(tp, 0xffffffff); 1492 rtl_pci_commit(tp); 1493 } 1494 1495 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1496 { 1497 struct phy_device *phydev = tp->phydev; 1498 1499 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1500 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1501 if (phydev->speed == SPEED_1000) { 1502 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1503 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1504 } else if (phydev->speed == SPEED_100) { 1505 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1506 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1507 } else { 1508 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1509 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1510 } 1511 rtl_reset_packet_filter(tp); 1512 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1513 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1514 if (phydev->speed == SPEED_1000) { 1515 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1516 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1517 } else { 1518 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1519 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1520 } 1521 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1522 if (phydev->speed == SPEED_10) { 1523 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1524 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1525 } else { 1526 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1527 } 1528 } 1529 } 1530 1531 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1532 1533 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1534 { 1535 struct rtl8169_private *tp = netdev_priv(dev); 1536 1537 wol->supported = WAKE_ANY; 1538 wol->wolopts = tp->saved_wolopts; 1539 } 1540 1541 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1542 { 1543 static const struct { 1544 u32 opt; 1545 u16 reg; 1546 u8 mask; 1547 } cfg[] = { 1548 { WAKE_PHY, Config3, LinkUp }, 1549 { WAKE_UCAST, Config5, UWF }, 1550 { WAKE_BCAST, Config5, BWF }, 1551 { WAKE_MCAST, Config5, MWF }, 1552 { WAKE_ANY, Config5, LanWake }, 1553 { WAKE_MAGIC, Config3, MagicPacket } 1554 }; 1555 unsigned int i, tmp = ARRAY_SIZE(cfg); 1556 unsigned long flags; 1557 u8 options; 1558 1559 rtl_unlock_config_regs(tp); 1560 1561 if (rtl_is_8168evl_up(tp)) { 1562 tmp--; 1563 if (wolopts & WAKE_MAGIC) 1564 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1565 else 1566 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1567 } else if (rtl_is_8125(tp)) { 1568 tmp--; 1569 if (wolopts & WAKE_MAGIC) 1570 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1571 else 1572 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1573 } 1574 1575 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1576 for (i = 0; i < tmp; i++) { 1577 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1578 if (wolopts & cfg[i].opt) 1579 options |= cfg[i].mask; 1580 RTL_W8(tp, cfg[i].reg, options); 1581 } 1582 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1583 1584 switch (tp->mac_version) { 1585 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1586 options = RTL_R8(tp, Config1) & ~PMEnable; 1587 if (wolopts) 1588 options |= PMEnable; 1589 RTL_W8(tp, Config1, options); 1590 break; 1591 case RTL_GIGA_MAC_VER_34: 1592 case RTL_GIGA_MAC_VER_37: 1593 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65: 1594 if (wolopts) 1595 rtl_mod_config2(tp, 0, PME_SIGNAL); 1596 else 1597 rtl_mod_config2(tp, PME_SIGNAL, 0); 1598 break; 1599 default: 1600 break; 1601 } 1602 1603 rtl_lock_config_regs(tp); 1604 1605 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1606 1607 if (!tp->dash_enabled) { 1608 rtl_set_d3_pll_down(tp, !wolopts); 1609 tp->dev->wol_enabled = wolopts ? 1 : 0; 1610 } 1611 } 1612 1613 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1614 { 1615 struct rtl8169_private *tp = netdev_priv(dev); 1616 1617 if (wol->wolopts & ~WAKE_ANY) 1618 return -EINVAL; 1619 1620 tp->saved_wolopts = wol->wolopts; 1621 __rtl8169_set_wol(tp, tp->saved_wolopts); 1622 1623 return 0; 1624 } 1625 1626 static void rtl8169_get_drvinfo(struct net_device *dev, 1627 struct ethtool_drvinfo *info) 1628 { 1629 struct rtl8169_private *tp = netdev_priv(dev); 1630 struct rtl_fw *rtl_fw = tp->rtl_fw; 1631 1632 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1633 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1634 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1635 if (rtl_fw) 1636 strscpy(info->fw_version, rtl_fw->version, 1637 sizeof(info->fw_version)); 1638 } 1639 1640 static int rtl8169_get_regs_len(struct net_device *dev) 1641 { 1642 return R8169_REGS_SIZE; 1643 } 1644 1645 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1646 netdev_features_t features) 1647 { 1648 struct rtl8169_private *tp = netdev_priv(dev); 1649 1650 if (dev->mtu > TD_MSS_MAX) 1651 features &= ~NETIF_F_ALL_TSO; 1652 1653 if (dev->mtu > ETH_DATA_LEN && 1654 tp->mac_version > RTL_GIGA_MAC_VER_06) 1655 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1656 1657 return features; 1658 } 1659 1660 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1661 netdev_features_t features) 1662 { 1663 u32 rx_config = RTL_R32(tp, RxConfig); 1664 1665 if (features & NETIF_F_RXALL) 1666 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1667 else 1668 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1669 1670 if (rtl_is_8125(tp)) { 1671 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1672 rx_config |= RX_VLAN_8125; 1673 else 1674 rx_config &= ~RX_VLAN_8125; 1675 } 1676 1677 RTL_W32(tp, RxConfig, rx_config); 1678 } 1679 1680 static int rtl8169_set_features(struct net_device *dev, 1681 netdev_features_t features) 1682 { 1683 struct rtl8169_private *tp = netdev_priv(dev); 1684 1685 rtl_set_rx_config_features(tp, features); 1686 1687 if (features & NETIF_F_RXCSUM) 1688 tp->cp_cmd |= RxChkSum; 1689 else 1690 tp->cp_cmd &= ~RxChkSum; 1691 1692 if (!rtl_is_8125(tp)) { 1693 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1694 tp->cp_cmd |= RxVlan; 1695 else 1696 tp->cp_cmd &= ~RxVlan; 1697 } 1698 1699 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1700 rtl_pci_commit(tp); 1701 1702 return 0; 1703 } 1704 1705 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1706 { 1707 return (skb_vlan_tag_present(skb)) ? 1708 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1709 } 1710 1711 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1712 { 1713 u32 opts2 = le32_to_cpu(desc->opts2); 1714 1715 if (opts2 & RxVlanTag) 1716 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1717 } 1718 1719 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1720 void *p) 1721 { 1722 struct rtl8169_private *tp = netdev_priv(dev); 1723 u32 __iomem *data = tp->mmio_addr; 1724 u32 *dw = p; 1725 int i; 1726 1727 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1728 memcpy_fromio(dw++, data++, 4); 1729 } 1730 1731 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1732 "tx_packets", 1733 "rx_packets", 1734 "tx_errors", 1735 "rx_errors", 1736 "rx_missed", 1737 "align_errors", 1738 "tx_single_collisions", 1739 "tx_multi_collisions", 1740 "unicast", 1741 "broadcast", 1742 "multicast", 1743 "tx_aborted", 1744 "tx_underrun", 1745 }; 1746 1747 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1748 { 1749 switch (sset) { 1750 case ETH_SS_STATS: 1751 return ARRAY_SIZE(rtl8169_gstrings); 1752 default: 1753 return -EOPNOTSUPP; 1754 } 1755 } 1756 1757 DECLARE_RTL_COND(rtl_counters_cond) 1758 { 1759 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1760 } 1761 1762 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1763 { 1764 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1765 1766 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1767 rtl_pci_commit(tp); 1768 RTL_W32(tp, CounterAddrLow, cmd); 1769 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1770 1771 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1772 } 1773 1774 static void rtl8169_update_counters(struct rtl8169_private *tp) 1775 { 1776 u8 val = RTL_R8(tp, ChipCmd); 1777 1778 /* 1779 * Some chips are unable to dump tally counters when the receiver 1780 * is disabled. If 0xff chip may be in a PCI power-save state. 1781 */ 1782 if (val & CmdRxEnb && val != 0xff) 1783 rtl8169_do_counters(tp, CounterDump); 1784 } 1785 1786 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1787 { 1788 struct rtl8169_counters *counters = tp->counters; 1789 1790 /* 1791 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1792 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1793 * reset by a power cycle, while the counter values collected by the 1794 * driver are reset at every driver unload/load cycle. 1795 * 1796 * To make sure the HW values returned by @get_stats64 match the SW 1797 * values, we collect the initial values at first open(*) and use them 1798 * as offsets to normalize the values returned by @get_stats64. 1799 * 1800 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1801 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1802 * set at open time by rtl_hw_start. 1803 */ 1804 1805 if (tp->tc_offset.inited) 1806 return; 1807 1808 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1809 rtl8169_do_counters(tp, CounterReset); 1810 } else { 1811 rtl8169_update_counters(tp); 1812 tp->tc_offset.tx_errors = counters->tx_errors; 1813 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1814 tp->tc_offset.tx_aborted = counters->tx_aborted; 1815 tp->tc_offset.rx_missed = counters->rx_missed; 1816 } 1817 1818 tp->tc_offset.inited = true; 1819 } 1820 1821 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1822 struct ethtool_stats *stats, u64 *data) 1823 { 1824 struct rtl8169_private *tp = netdev_priv(dev); 1825 struct rtl8169_counters *counters; 1826 1827 counters = tp->counters; 1828 rtl8169_update_counters(tp); 1829 1830 data[0] = le64_to_cpu(counters->tx_packets); 1831 data[1] = le64_to_cpu(counters->rx_packets); 1832 data[2] = le64_to_cpu(counters->tx_errors); 1833 data[3] = le32_to_cpu(counters->rx_errors); 1834 data[4] = le16_to_cpu(counters->rx_missed); 1835 data[5] = le16_to_cpu(counters->align_errors); 1836 data[6] = le32_to_cpu(counters->tx_one_collision); 1837 data[7] = le32_to_cpu(counters->tx_multi_collision); 1838 data[8] = le64_to_cpu(counters->rx_unicast); 1839 data[9] = le64_to_cpu(counters->rx_broadcast); 1840 data[10] = le32_to_cpu(counters->rx_multicast); 1841 data[11] = le16_to_cpu(counters->tx_aborted); 1842 data[12] = le16_to_cpu(counters->tx_underun); 1843 } 1844 1845 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1846 { 1847 switch(stringset) { 1848 case ETH_SS_STATS: 1849 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1850 break; 1851 } 1852 } 1853 1854 /* 1855 * Interrupt coalescing 1856 * 1857 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1858 * > 8169, 8168 and 810x line of chipsets 1859 * 1860 * 8169, 8168, and 8136(810x) serial chipsets support it. 1861 * 1862 * > 2 - the Tx timer unit at gigabit speed 1863 * 1864 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1865 * (0xe0) bit 1 and bit 0. 1866 * 1867 * For 8169 1868 * bit[1:0] \ speed 1000M 100M 10M 1869 * 0 0 320ns 2.56us 40.96us 1870 * 0 1 2.56us 20.48us 327.7us 1871 * 1 0 5.12us 40.96us 655.4us 1872 * 1 1 10.24us 81.92us 1.31ms 1873 * 1874 * For the other 1875 * bit[1:0] \ speed 1000M 100M 10M 1876 * 0 0 5us 2.56us 40.96us 1877 * 0 1 40us 20.48us 327.7us 1878 * 1 0 80us 40.96us 655.4us 1879 * 1 1 160us 81.92us 1.31ms 1880 */ 1881 1882 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1883 struct rtl_coalesce_info { 1884 u32 speed; 1885 u32 scale_nsecs[4]; 1886 }; 1887 1888 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1889 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1890 1891 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1892 { SPEED_1000, COALESCE_DELAY(320) }, 1893 { SPEED_100, COALESCE_DELAY(2560) }, 1894 { SPEED_10, COALESCE_DELAY(40960) }, 1895 { 0 }, 1896 }; 1897 1898 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1899 { SPEED_1000, COALESCE_DELAY(5000) }, 1900 { SPEED_100, COALESCE_DELAY(2560) }, 1901 { SPEED_10, COALESCE_DELAY(40960) }, 1902 { 0 }, 1903 }; 1904 #undef COALESCE_DELAY 1905 1906 /* get rx/tx scale vector corresponding to current speed */ 1907 static const struct rtl_coalesce_info * 1908 rtl_coalesce_info(struct rtl8169_private *tp) 1909 { 1910 const struct rtl_coalesce_info *ci; 1911 1912 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1913 ci = rtl_coalesce_info_8169; 1914 else 1915 ci = rtl_coalesce_info_8168_8136; 1916 1917 /* if speed is unknown assume highest one */ 1918 if (tp->phydev->speed == SPEED_UNKNOWN) 1919 return ci; 1920 1921 for (; ci->speed; ci++) { 1922 if (tp->phydev->speed == ci->speed) 1923 return ci; 1924 } 1925 1926 return ERR_PTR(-ELNRNG); 1927 } 1928 1929 static int rtl_get_coalesce(struct net_device *dev, 1930 struct ethtool_coalesce *ec, 1931 struct kernel_ethtool_coalesce *kernel_coal, 1932 struct netlink_ext_ack *extack) 1933 { 1934 struct rtl8169_private *tp = netdev_priv(dev); 1935 const struct rtl_coalesce_info *ci; 1936 u32 scale, c_us, c_fr; 1937 u16 intrmit; 1938 1939 if (rtl_is_8125(tp)) 1940 return -EOPNOTSUPP; 1941 1942 memset(ec, 0, sizeof(*ec)); 1943 1944 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1945 ci = rtl_coalesce_info(tp); 1946 if (IS_ERR(ci)) 1947 return PTR_ERR(ci); 1948 1949 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1950 1951 intrmit = RTL_R16(tp, IntrMitigate); 1952 1953 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1954 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1955 1956 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1957 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1958 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1959 1960 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1961 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1962 1963 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1964 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1965 1966 return 0; 1967 } 1968 1969 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1970 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1971 u16 *cp01) 1972 { 1973 const struct rtl_coalesce_info *ci; 1974 u16 i; 1975 1976 ci = rtl_coalesce_info(tp); 1977 if (IS_ERR(ci)) 1978 return PTR_ERR(ci); 1979 1980 for (i = 0; i < 4; i++) { 1981 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1982 *cp01 = i; 1983 return ci->scale_nsecs[i]; 1984 } 1985 } 1986 1987 return -ERANGE; 1988 } 1989 1990 static int rtl_set_coalesce(struct net_device *dev, 1991 struct ethtool_coalesce *ec, 1992 struct kernel_ethtool_coalesce *kernel_coal, 1993 struct netlink_ext_ack *extack) 1994 { 1995 struct rtl8169_private *tp = netdev_priv(dev); 1996 u32 tx_fr = ec->tx_max_coalesced_frames; 1997 u32 rx_fr = ec->rx_max_coalesced_frames; 1998 u32 coal_usec_max, units; 1999 u16 w = 0, cp01 = 0; 2000 int scale; 2001 2002 if (rtl_is_8125(tp)) 2003 return -EOPNOTSUPP; 2004 2005 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 2006 return -ERANGE; 2007 2008 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 2009 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 2010 if (scale < 0) 2011 return scale; 2012 2013 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 2014 * not only when usecs=0 because of e.g. the following scenario: 2015 * 2016 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2017 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2018 * - then user does `ethtool -C eth0 rx-usecs 100` 2019 * 2020 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2021 * if we want to ignore rx_frames then it has to be set to 0. 2022 */ 2023 if (rx_fr == 1) 2024 rx_fr = 0; 2025 if (tx_fr == 1) 2026 tx_fr = 0; 2027 2028 /* HW requires time limit to be set if frame limit is set */ 2029 if ((tx_fr && !ec->tx_coalesce_usecs) || 2030 (rx_fr && !ec->rx_coalesce_usecs)) 2031 return -EINVAL; 2032 2033 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2034 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2035 2036 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2037 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2038 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2039 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2040 2041 RTL_W16(tp, IntrMitigate, w); 2042 2043 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2044 if (rtl_is_8168evl_up(tp)) { 2045 if (!rx_fr && !tx_fr) 2046 /* disable packet counter */ 2047 tp->cp_cmd |= PktCntrDisable; 2048 else 2049 tp->cp_cmd &= ~PktCntrDisable; 2050 } 2051 2052 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2053 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2054 rtl_pci_commit(tp); 2055 2056 return 0; 2057 } 2058 2059 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2060 { 2061 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2062 2063 switch (tp->mac_version) { 2064 case RTL_GIGA_MAC_VER_46: 2065 case RTL_GIGA_MAC_VER_48: 2066 tp->tx_lpi_timer = timer_val; 2067 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2068 break; 2069 case RTL_GIGA_MAC_VER_61: 2070 case RTL_GIGA_MAC_VER_63: 2071 case RTL_GIGA_MAC_VER_65: 2072 tp->tx_lpi_timer = timer_val; 2073 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2074 break; 2075 default: 2076 break; 2077 } 2078 } 2079 2080 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2081 { 2082 unsigned int speed = tp->phydev->speed; 2083 unsigned int timer = tp->tx_lpi_timer; 2084 2085 if (!timer || speed == SPEED_UNKNOWN) 2086 return 0; 2087 2088 /* tx_lpi_timer value is in bytes */ 2089 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2090 } 2091 2092 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2093 { 2094 struct rtl8169_private *tp = netdev_priv(dev); 2095 int ret; 2096 2097 if (!rtl_supports_eee(tp)) 2098 return -EOPNOTSUPP; 2099 2100 ret = phy_ethtool_get_eee(tp->phydev, data); 2101 if (ret) 2102 return ret; 2103 2104 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2105 2106 return 0; 2107 } 2108 2109 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2110 { 2111 struct rtl8169_private *tp = netdev_priv(dev); 2112 2113 if (!rtl_supports_eee(tp)) 2114 return -EOPNOTSUPP; 2115 2116 return phy_ethtool_set_eee(tp->phydev, data); 2117 } 2118 2119 static void rtl8169_get_ringparam(struct net_device *dev, 2120 struct ethtool_ringparam *data, 2121 struct kernel_ethtool_ringparam *kernel_data, 2122 struct netlink_ext_ack *extack) 2123 { 2124 data->rx_max_pending = NUM_RX_DESC; 2125 data->rx_pending = NUM_RX_DESC; 2126 data->tx_max_pending = NUM_TX_DESC; 2127 data->tx_pending = NUM_TX_DESC; 2128 } 2129 2130 static void rtl8169_get_pauseparam(struct net_device *dev, 2131 struct ethtool_pauseparam *data) 2132 { 2133 struct rtl8169_private *tp = netdev_priv(dev); 2134 bool tx_pause, rx_pause; 2135 2136 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2137 2138 data->autoneg = tp->phydev->autoneg; 2139 data->tx_pause = tx_pause ? 1 : 0; 2140 data->rx_pause = rx_pause ? 1 : 0; 2141 } 2142 2143 static int rtl8169_set_pauseparam(struct net_device *dev, 2144 struct ethtool_pauseparam *data) 2145 { 2146 struct rtl8169_private *tp = netdev_priv(dev); 2147 2148 if (dev->mtu > ETH_DATA_LEN) 2149 return -EOPNOTSUPP; 2150 2151 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2152 2153 return 0; 2154 } 2155 2156 static const struct ethtool_ops rtl8169_ethtool_ops = { 2157 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2158 ETHTOOL_COALESCE_MAX_FRAMES, 2159 .get_drvinfo = rtl8169_get_drvinfo, 2160 .get_regs_len = rtl8169_get_regs_len, 2161 .get_link = ethtool_op_get_link, 2162 .get_coalesce = rtl_get_coalesce, 2163 .set_coalesce = rtl_set_coalesce, 2164 .get_regs = rtl8169_get_regs, 2165 .get_wol = rtl8169_get_wol, 2166 .set_wol = rtl8169_set_wol, 2167 .get_strings = rtl8169_get_strings, 2168 .get_sset_count = rtl8169_get_sset_count, 2169 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2170 .get_ts_info = ethtool_op_get_ts_info, 2171 .nway_reset = phy_ethtool_nway_reset, 2172 .get_eee = rtl8169_get_eee, 2173 .set_eee = rtl8169_set_eee, 2174 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2175 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2176 .get_ringparam = rtl8169_get_ringparam, 2177 .get_pauseparam = rtl8169_get_pauseparam, 2178 .set_pauseparam = rtl8169_set_pauseparam, 2179 }; 2180 2181 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2182 { 2183 /* 2184 * The driver currently handles the 8168Bf and the 8168Be identically 2185 * but they can be identified more specifically through the test below 2186 * if needed: 2187 * 2188 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2189 * 2190 * Same thing for the 8101Eb and the 8101Ec: 2191 * 2192 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2193 */ 2194 static const struct rtl_mac_info { 2195 u16 mask; 2196 u16 val; 2197 enum mac_version ver; 2198 } mac_info[] = { 2199 /* 8126A family. */ 2200 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2201 2202 /* 8125B family. */ 2203 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2204 2205 /* 8125A family. */ 2206 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2207 /* It seems only XID 609 made it to the mass market. 2208 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2209 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2210 */ 2211 2212 /* RTL8117 */ 2213 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2214 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2215 2216 /* 8168EP family. */ 2217 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2218 /* It seems this chip version never made it to 2219 * the wild. Let's disable detection. 2220 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2221 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2222 */ 2223 2224 /* 8168H family. */ 2225 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2226 /* It seems this chip version never made it to 2227 * the wild. Let's disable detection. 2228 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2229 */ 2230 2231 /* 8168G family. */ 2232 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2233 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2234 /* It seems this chip version never made it to 2235 * the wild. Let's disable detection. 2236 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2237 */ 2238 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2239 2240 /* 8168F family. */ 2241 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2242 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2243 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2244 2245 /* 8168E family. */ 2246 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2247 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2248 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2249 2250 /* 8168D family. */ 2251 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2252 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2253 2254 /* 8168DP family. */ 2255 /* It seems this early RTL8168dp version never made it to 2256 * the wild. Support has been removed. 2257 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2258 */ 2259 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2260 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2261 2262 /* 8168C family. */ 2263 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2264 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2265 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2266 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2267 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2268 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2269 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2270 2271 /* 8168B family. */ 2272 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2273 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2274 2275 /* 8101 family. */ 2276 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2277 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2278 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2279 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2280 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2281 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2282 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2283 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2284 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2285 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2286 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2287 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2288 2289 /* 8110 family. */ 2290 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2291 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2292 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2293 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2294 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2295 2296 /* Catch-all */ 2297 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2298 }; 2299 const struct rtl_mac_info *p = mac_info; 2300 enum mac_version ver; 2301 2302 while ((xid & p->mask) != p->val) 2303 p++; 2304 ver = p->ver; 2305 2306 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2307 if (ver == RTL_GIGA_MAC_VER_42) 2308 ver = RTL_GIGA_MAC_VER_43; 2309 else if (ver == RTL_GIGA_MAC_VER_46) 2310 ver = RTL_GIGA_MAC_VER_48; 2311 } 2312 2313 return ver; 2314 } 2315 2316 static void rtl_release_firmware(struct rtl8169_private *tp) 2317 { 2318 if (tp->rtl_fw) { 2319 rtl_fw_release_firmware(tp->rtl_fw); 2320 kfree(tp->rtl_fw); 2321 tp->rtl_fw = NULL; 2322 } 2323 } 2324 2325 void r8169_apply_firmware(struct rtl8169_private *tp) 2326 { 2327 int val; 2328 2329 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2330 if (tp->rtl_fw) { 2331 rtl_fw_write_firmware(tp, tp->rtl_fw); 2332 /* At least one firmware doesn't reset tp->ocp_base. */ 2333 tp->ocp_base = OCP_STD_PHY_BASE; 2334 2335 /* PHY soft reset may still be in progress */ 2336 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2337 !(val & BMCR_RESET), 2338 50000, 600000, true); 2339 } 2340 } 2341 2342 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2343 { 2344 /* Adjust EEE LED frequency */ 2345 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2346 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2347 2348 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2349 } 2350 2351 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2352 { 2353 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2354 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2355 } 2356 2357 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2358 { 2359 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2360 } 2361 2362 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2363 { 2364 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2365 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2366 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2367 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2368 } 2369 2370 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2371 { 2372 u16 data1, data2, ioffset; 2373 2374 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2375 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2376 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2377 2378 ioffset = (data2 >> 1) & 0x7ff8; 2379 ioffset |= data2 & 0x0007; 2380 if (data1 & BIT(7)) 2381 ioffset |= BIT(15); 2382 2383 return ioffset; 2384 } 2385 2386 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2387 { 2388 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 2389 return; 2390 2391 set_bit(flag, tp->wk.flags); 2392 schedule_work(&tp->wk.work); 2393 } 2394 2395 static void rtl8169_init_phy(struct rtl8169_private *tp) 2396 { 2397 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2398 2399 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2400 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2401 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2402 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2403 RTL_W8(tp, 0x82, 0x01); 2404 } 2405 2406 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2407 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2408 tp->pci_dev->subsystem_device == 0xe000) 2409 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2410 2411 /* We may have called phy_speed_down before */ 2412 phy_speed_up(tp->phydev); 2413 2414 genphy_soft_reset(tp->phydev); 2415 } 2416 2417 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2418 { 2419 rtl_unlock_config_regs(tp); 2420 2421 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2422 rtl_pci_commit(tp); 2423 2424 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2425 rtl_pci_commit(tp); 2426 2427 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2428 rtl_rar_exgmac_set(tp, addr); 2429 2430 rtl_lock_config_regs(tp); 2431 } 2432 2433 static int rtl_set_mac_address(struct net_device *dev, void *p) 2434 { 2435 struct rtl8169_private *tp = netdev_priv(dev); 2436 int ret; 2437 2438 ret = eth_mac_addr(dev, p); 2439 if (ret) 2440 return ret; 2441 2442 rtl_rar_set(tp, dev->dev_addr); 2443 2444 return 0; 2445 } 2446 2447 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2448 { 2449 switch (tp->mac_version) { 2450 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2451 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2452 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2453 break; 2454 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2455 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2456 case RTL_GIGA_MAC_VER_38: 2457 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2458 break; 2459 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2460 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2461 break; 2462 case RTL_GIGA_MAC_VER_61: 2463 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2464 break; 2465 case RTL_GIGA_MAC_VER_63: 2466 case RTL_GIGA_MAC_VER_65: 2467 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2468 RX_PAUSE_SLOT_ON); 2469 break; 2470 default: 2471 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2472 break; 2473 } 2474 } 2475 2476 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2477 { 2478 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2479 } 2480 2481 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2482 { 2483 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2484 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2485 } 2486 2487 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2488 { 2489 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2490 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2491 } 2492 2493 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2494 { 2495 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2496 } 2497 2498 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2499 { 2500 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2501 } 2502 2503 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2504 { 2505 RTL_W8(tp, MaxTxPacketSize, 0x24); 2506 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2507 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2508 } 2509 2510 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2511 { 2512 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2513 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2514 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2515 } 2516 2517 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2518 { 2519 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2520 } 2521 2522 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2523 { 2524 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2525 } 2526 2527 static void rtl_jumbo_config(struct rtl8169_private *tp) 2528 { 2529 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2530 int readrq = 4096; 2531 2532 rtl_unlock_config_regs(tp); 2533 switch (tp->mac_version) { 2534 case RTL_GIGA_MAC_VER_17: 2535 if (jumbo) { 2536 readrq = 512; 2537 r8168b_1_hw_jumbo_enable(tp); 2538 } else { 2539 r8168b_1_hw_jumbo_disable(tp); 2540 } 2541 break; 2542 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2543 if (jumbo) { 2544 readrq = 512; 2545 r8168c_hw_jumbo_enable(tp); 2546 } else { 2547 r8168c_hw_jumbo_disable(tp); 2548 } 2549 break; 2550 case RTL_GIGA_MAC_VER_28: 2551 if (jumbo) 2552 r8168dp_hw_jumbo_enable(tp); 2553 else 2554 r8168dp_hw_jumbo_disable(tp); 2555 break; 2556 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2557 if (jumbo) 2558 r8168e_hw_jumbo_enable(tp); 2559 else 2560 r8168e_hw_jumbo_disable(tp); 2561 break; 2562 default: 2563 break; 2564 } 2565 rtl_lock_config_regs(tp); 2566 2567 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2568 pcie_set_readrq(tp->pci_dev, readrq); 2569 2570 /* Chip doesn't support pause in jumbo mode */ 2571 if (jumbo) { 2572 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2573 tp->phydev->advertising); 2574 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2575 tp->phydev->advertising); 2576 phy_start_aneg(tp->phydev); 2577 } 2578 } 2579 2580 DECLARE_RTL_COND(rtl_chipcmd_cond) 2581 { 2582 return RTL_R8(tp, ChipCmd) & CmdReset; 2583 } 2584 2585 static void rtl_hw_reset(struct rtl8169_private *tp) 2586 { 2587 RTL_W8(tp, ChipCmd, CmdReset); 2588 2589 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2590 } 2591 2592 static void rtl_request_firmware(struct rtl8169_private *tp) 2593 { 2594 struct rtl_fw *rtl_fw; 2595 2596 /* firmware loaded already or no firmware available */ 2597 if (tp->rtl_fw || !tp->fw_name) 2598 return; 2599 2600 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2601 if (!rtl_fw) 2602 return; 2603 2604 rtl_fw->phy_write = rtl_writephy; 2605 rtl_fw->phy_read = rtl_readphy; 2606 rtl_fw->mac_mcu_write = mac_mcu_write; 2607 rtl_fw->mac_mcu_read = mac_mcu_read; 2608 rtl_fw->fw_name = tp->fw_name; 2609 rtl_fw->dev = tp_to_dev(tp); 2610 2611 if (rtl_fw_request_firmware(rtl_fw)) 2612 kfree(rtl_fw); 2613 else 2614 tp->rtl_fw = rtl_fw; 2615 } 2616 2617 static void rtl_rx_close(struct rtl8169_private *tp) 2618 { 2619 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2620 } 2621 2622 DECLARE_RTL_COND(rtl_npq_cond) 2623 { 2624 return RTL_R8(tp, TxPoll) & NPQ; 2625 } 2626 2627 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2628 { 2629 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2630 } 2631 2632 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2633 { 2634 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2635 } 2636 2637 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2638 { 2639 /* IntrMitigate has new functionality on RTL8125 */ 2640 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2641 } 2642 2643 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2644 { 2645 switch (tp->mac_version) { 2646 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2647 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2648 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2649 break; 2650 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2651 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2652 break; 2653 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65: 2654 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2655 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2656 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2657 break; 2658 default: 2659 break; 2660 } 2661 } 2662 2663 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2664 { 2665 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2666 } 2667 2668 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2669 { 2670 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2671 fsleep(2000); 2672 rtl_wait_txrx_fifo_empty(tp); 2673 } 2674 2675 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2676 { 2677 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2678 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2679 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2680 2681 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2682 rtl_disable_rxdvgate(tp); 2683 } 2684 2685 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2686 { 2687 if (tp->dash_enabled) 2688 return; 2689 2690 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2691 tp->mac_version == RTL_GIGA_MAC_VER_33) 2692 rtl_ephy_write(tp, 0x19, 0xff64); 2693 2694 if (device_may_wakeup(tp_to_dev(tp))) { 2695 phy_speed_down(tp->phydev, false); 2696 rtl_wol_enable_rx(tp); 2697 } 2698 } 2699 2700 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2701 { 2702 u32 val = TX_DMA_BURST << TxDMAShift | 2703 InterFrameGap << TxInterFrameGapShift; 2704 2705 if (rtl_is_8168evl_up(tp)) 2706 val |= TXCFG_AUTO_FIFO; 2707 2708 RTL_W32(tp, TxConfig, val); 2709 } 2710 2711 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2712 { 2713 /* Low hurts. Let's disable the filtering. */ 2714 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2715 } 2716 2717 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2718 { 2719 /* 2720 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2721 * register to be written before TxDescAddrLow to work. 2722 * Switching from MMIO to I/O access fixes the issue as well. 2723 */ 2724 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2725 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2726 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2727 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2728 } 2729 2730 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2731 { 2732 u32 val; 2733 2734 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2735 val = 0x000fff00; 2736 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2737 val = 0x00ffff00; 2738 else 2739 return; 2740 2741 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2742 val |= 0xff; 2743 2744 RTL_W32(tp, 0x7c, val); 2745 } 2746 2747 static void rtl_set_rx_mode(struct net_device *dev) 2748 { 2749 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2750 /* Multicast hash filter */ 2751 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2752 struct rtl8169_private *tp = netdev_priv(dev); 2753 u32 tmp; 2754 2755 if (dev->flags & IFF_PROMISC) { 2756 rx_mode |= AcceptAllPhys; 2757 } else if (!(dev->flags & IFF_MULTICAST)) { 2758 rx_mode &= ~AcceptMulticast; 2759 } else if (dev->flags & IFF_ALLMULTI || 2760 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2761 /* accept all multicasts */ 2762 } else if (netdev_mc_empty(dev)) { 2763 rx_mode &= ~AcceptMulticast; 2764 } else { 2765 struct netdev_hw_addr *ha; 2766 2767 mc_filter[1] = mc_filter[0] = 0; 2768 netdev_for_each_mc_addr(ha, dev) { 2769 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2770 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2771 } 2772 2773 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2774 tmp = mc_filter[0]; 2775 mc_filter[0] = swab32(mc_filter[1]); 2776 mc_filter[1] = swab32(tmp); 2777 } 2778 } 2779 2780 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2781 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2782 2783 tmp = RTL_R32(tp, RxConfig); 2784 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2785 } 2786 2787 DECLARE_RTL_COND(rtl_csiar_cond) 2788 { 2789 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2790 } 2791 2792 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2793 { 2794 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2795 2796 RTL_W32(tp, CSIDR, value); 2797 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2798 CSIAR_BYTE_ENABLE | func << 16); 2799 2800 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2801 } 2802 2803 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2804 { 2805 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2806 2807 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2808 CSIAR_BYTE_ENABLE); 2809 2810 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2811 RTL_R32(tp, CSIDR) : ~0; 2812 } 2813 2814 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2815 { 2816 struct pci_dev *pdev = tp->pci_dev; 2817 u32 csi; 2818 2819 /* According to Realtek the value at config space address 0x070f 2820 * controls the L0s/L1 entrance latency. We try standard ECAM access 2821 * first and if it fails fall back to CSI. 2822 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2823 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2824 */ 2825 if (pdev->cfg_size > 0x070f && 2826 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2827 return; 2828 2829 netdev_notice_once(tp->dev, 2830 "No native access to PCI extended config space, falling back to CSI\n"); 2831 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2832 rtl_csi_write(tp, 0x070c, csi | val << 24); 2833 } 2834 2835 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2836 { 2837 /* L0 7us, L1 16us */ 2838 rtl_set_aspm_entry_latency(tp, 0x27); 2839 } 2840 2841 struct ephy_info { 2842 unsigned int offset; 2843 u16 mask; 2844 u16 bits; 2845 }; 2846 2847 static void __rtl_ephy_init(struct rtl8169_private *tp, 2848 const struct ephy_info *e, int len) 2849 { 2850 u16 w; 2851 2852 while (len-- > 0) { 2853 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2854 rtl_ephy_write(tp, e->offset, w); 2855 e++; 2856 } 2857 } 2858 2859 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2860 2861 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2862 { 2863 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2864 PCI_EXP_LNKCTL_CLKREQ_EN); 2865 } 2866 2867 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2868 { 2869 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2870 PCI_EXP_LNKCTL_CLKREQ_EN); 2871 } 2872 2873 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2874 { 2875 /* work around an issue when PCI reset occurs during L2/L3 state */ 2876 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2877 } 2878 2879 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2880 { 2881 /* Bits control which events trigger ASPM L1 exit: 2882 * Bit 12: rxdv 2883 * Bit 11: ltr_msg 2884 * Bit 10: txdma_poll 2885 * Bit 9: xadm 2886 * Bit 8: pktavi 2887 * Bit 7: txpla 2888 */ 2889 switch (tp->mac_version) { 2890 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2891 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2892 break; 2893 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2894 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2895 break; 2896 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 2897 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2898 break; 2899 default: 2900 break; 2901 } 2902 } 2903 2904 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2905 { 2906 switch (tp->mac_version) { 2907 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2908 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2909 break; 2910 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 2911 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2912 break; 2913 default: 2914 break; 2915 } 2916 } 2917 2918 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2919 { 2920 u8 val8; 2921 2922 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2923 return; 2924 2925 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2926 if (enable && tp->aspm_manageable) { 2927 /* On these chip versions ASPM can even harm 2928 * bus communication of other PCI devices. 2929 */ 2930 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2931 tp->mac_version == RTL_GIGA_MAC_VER_43) 2932 return; 2933 2934 rtl_mod_config5(tp, 0, ASPM_en); 2935 switch (tp->mac_version) { 2936 case RTL_GIGA_MAC_VER_65: 2937 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2938 RTL_W8(tp, INT_CFG0_8125, val8); 2939 break; 2940 default: 2941 rtl_mod_config2(tp, 0, ClkReqEn); 2942 break; 2943 } 2944 2945 switch (tp->mac_version) { 2946 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2947 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 2948 /* reset ephy tx/rx disable timer */ 2949 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2950 /* chip can trigger L1.2 */ 2951 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2952 break; 2953 default: 2954 break; 2955 } 2956 } else { 2957 switch (tp->mac_version) { 2958 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2959 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 2960 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2961 break; 2962 default: 2963 break; 2964 } 2965 2966 switch (tp->mac_version) { 2967 case RTL_GIGA_MAC_VER_65: 2968 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2969 RTL_W8(tp, INT_CFG0_8125, val8); 2970 break; 2971 default: 2972 rtl_mod_config2(tp, ClkReqEn, 0); 2973 break; 2974 } 2975 rtl_mod_config5(tp, ASPM_en, 0); 2976 } 2977 } 2978 2979 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2980 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2981 { 2982 /* Usage of dynamic vs. static FIFO is controlled by bit 2983 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2984 */ 2985 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2986 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2987 } 2988 2989 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2990 u8 low, u8 high) 2991 { 2992 /* FIFO thresholds for pause flow control */ 2993 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2994 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2995 } 2996 2997 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2998 { 2999 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3000 } 3001 3002 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3003 { 3004 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3005 3006 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3007 3008 rtl_disable_clock_request(tp); 3009 } 3010 3011 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3012 { 3013 static const struct ephy_info e_info_8168cp[] = { 3014 { 0x01, 0, 0x0001 }, 3015 { 0x02, 0x0800, 0x1000 }, 3016 { 0x03, 0, 0x0042 }, 3017 { 0x06, 0x0080, 0x0000 }, 3018 { 0x07, 0, 0x2000 } 3019 }; 3020 3021 rtl_set_def_aspm_entry_latency(tp); 3022 3023 rtl_ephy_init(tp, e_info_8168cp); 3024 3025 __rtl_hw_start_8168cp(tp); 3026 } 3027 3028 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3029 { 3030 rtl_set_def_aspm_entry_latency(tp); 3031 3032 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3033 } 3034 3035 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3036 { 3037 rtl_set_def_aspm_entry_latency(tp); 3038 3039 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3040 3041 /* Magic. */ 3042 RTL_W8(tp, DBG_REG, 0x20); 3043 } 3044 3045 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3046 { 3047 static const struct ephy_info e_info_8168c_1[] = { 3048 { 0x02, 0x0800, 0x1000 }, 3049 { 0x03, 0, 0x0002 }, 3050 { 0x06, 0x0080, 0x0000 } 3051 }; 3052 3053 rtl_set_def_aspm_entry_latency(tp); 3054 3055 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3056 3057 rtl_ephy_init(tp, e_info_8168c_1); 3058 3059 __rtl_hw_start_8168cp(tp); 3060 } 3061 3062 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3063 { 3064 static const struct ephy_info e_info_8168c_2[] = { 3065 { 0x01, 0, 0x0001 }, 3066 { 0x03, 0x0400, 0x0020 } 3067 }; 3068 3069 rtl_set_def_aspm_entry_latency(tp); 3070 3071 rtl_ephy_init(tp, e_info_8168c_2); 3072 3073 __rtl_hw_start_8168cp(tp); 3074 } 3075 3076 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3077 { 3078 rtl_set_def_aspm_entry_latency(tp); 3079 3080 __rtl_hw_start_8168cp(tp); 3081 } 3082 3083 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3084 { 3085 rtl_set_def_aspm_entry_latency(tp); 3086 3087 rtl_disable_clock_request(tp); 3088 } 3089 3090 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3091 { 3092 static const struct ephy_info e_info_8168d_4[] = { 3093 { 0x0b, 0x0000, 0x0048 }, 3094 { 0x19, 0x0020, 0x0050 }, 3095 { 0x0c, 0x0100, 0x0020 }, 3096 { 0x10, 0x0004, 0x0000 }, 3097 }; 3098 3099 rtl_set_def_aspm_entry_latency(tp); 3100 3101 rtl_ephy_init(tp, e_info_8168d_4); 3102 3103 rtl_enable_clock_request(tp); 3104 } 3105 3106 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3107 { 3108 static const struct ephy_info e_info_8168e_1[] = { 3109 { 0x00, 0x0200, 0x0100 }, 3110 { 0x00, 0x0000, 0x0004 }, 3111 { 0x06, 0x0002, 0x0001 }, 3112 { 0x06, 0x0000, 0x0030 }, 3113 { 0x07, 0x0000, 0x2000 }, 3114 { 0x00, 0x0000, 0x0020 }, 3115 { 0x03, 0x5800, 0x2000 }, 3116 { 0x03, 0x0000, 0x0001 }, 3117 { 0x01, 0x0800, 0x1000 }, 3118 { 0x07, 0x0000, 0x4000 }, 3119 { 0x1e, 0x0000, 0x2000 }, 3120 { 0x19, 0xffff, 0xfe6c }, 3121 { 0x0a, 0x0000, 0x0040 } 3122 }; 3123 3124 rtl_set_def_aspm_entry_latency(tp); 3125 3126 rtl_ephy_init(tp, e_info_8168e_1); 3127 3128 rtl_disable_clock_request(tp); 3129 3130 /* Reset tx FIFO pointer */ 3131 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3132 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3133 3134 rtl_mod_config5(tp, Spi_en, 0); 3135 } 3136 3137 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3138 { 3139 static const struct ephy_info e_info_8168e_2[] = { 3140 { 0x09, 0x0000, 0x0080 }, 3141 { 0x19, 0x0000, 0x0224 }, 3142 { 0x00, 0x0000, 0x0004 }, 3143 { 0x0c, 0x3df0, 0x0200 }, 3144 }; 3145 3146 rtl_set_def_aspm_entry_latency(tp); 3147 3148 rtl_ephy_init(tp, e_info_8168e_2); 3149 3150 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3151 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3152 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3153 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3154 rtl_reset_packet_filter(tp); 3155 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3156 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3157 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3158 3159 rtl_disable_clock_request(tp); 3160 3161 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3162 3163 rtl8168_config_eee_mac(tp); 3164 3165 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3166 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3167 rtl_mod_config5(tp, Spi_en, 0); 3168 } 3169 3170 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3171 { 3172 rtl_set_def_aspm_entry_latency(tp); 3173 3174 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3175 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3176 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3177 rtl_reset_packet_filter(tp); 3178 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3179 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3180 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3181 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3182 3183 rtl_disable_clock_request(tp); 3184 3185 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3186 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3187 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3188 rtl_mod_config5(tp, Spi_en, 0); 3189 3190 rtl8168_config_eee_mac(tp); 3191 } 3192 3193 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3194 { 3195 static const struct ephy_info e_info_8168f_1[] = { 3196 { 0x06, 0x00c0, 0x0020 }, 3197 { 0x08, 0x0001, 0x0002 }, 3198 { 0x09, 0x0000, 0x0080 }, 3199 { 0x19, 0x0000, 0x0224 }, 3200 { 0x00, 0x0000, 0x0008 }, 3201 { 0x0c, 0x3df0, 0x0200 }, 3202 }; 3203 3204 rtl_hw_start_8168f(tp); 3205 3206 rtl_ephy_init(tp, e_info_8168f_1); 3207 } 3208 3209 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3210 { 3211 static const struct ephy_info e_info_8168f_1[] = { 3212 { 0x06, 0x00c0, 0x0020 }, 3213 { 0x0f, 0xffff, 0x5200 }, 3214 { 0x19, 0x0000, 0x0224 }, 3215 { 0x00, 0x0000, 0x0008 }, 3216 { 0x0c, 0x3df0, 0x0200 }, 3217 }; 3218 3219 rtl_hw_start_8168f(tp); 3220 rtl_pcie_state_l2l3_disable(tp); 3221 3222 rtl_ephy_init(tp, e_info_8168f_1); 3223 } 3224 3225 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3226 { 3227 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3228 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3229 3230 rtl_set_def_aspm_entry_latency(tp); 3231 3232 rtl_reset_packet_filter(tp); 3233 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3234 3235 rtl_disable_rxdvgate(tp); 3236 3237 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3238 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3239 3240 rtl8168_config_eee_mac(tp); 3241 3242 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3243 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3244 3245 rtl_pcie_state_l2l3_disable(tp); 3246 } 3247 3248 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3249 { 3250 static const struct ephy_info e_info_8168g_1[] = { 3251 { 0x00, 0x0008, 0x0000 }, 3252 { 0x0c, 0x3ff0, 0x0820 }, 3253 { 0x1e, 0x0000, 0x0001 }, 3254 { 0x19, 0x8000, 0x0000 } 3255 }; 3256 3257 rtl_hw_start_8168g(tp); 3258 rtl_ephy_init(tp, e_info_8168g_1); 3259 } 3260 3261 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3262 { 3263 static const struct ephy_info e_info_8168g_2[] = { 3264 { 0x00, 0x0008, 0x0000 }, 3265 { 0x0c, 0x3ff0, 0x0820 }, 3266 { 0x19, 0xffff, 0x7c00 }, 3267 { 0x1e, 0xffff, 0x20eb }, 3268 { 0x0d, 0xffff, 0x1666 }, 3269 { 0x00, 0xffff, 0x10a3 }, 3270 { 0x06, 0xffff, 0xf050 }, 3271 { 0x04, 0x0000, 0x0010 }, 3272 { 0x1d, 0x4000, 0x0000 }, 3273 }; 3274 3275 rtl_hw_start_8168g(tp); 3276 rtl_ephy_init(tp, e_info_8168g_2); 3277 } 3278 3279 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3280 { 3281 static const u16 fix_data[] = { 3282 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3283 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3284 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3285 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3286 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3287 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3288 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3289 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3290 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3291 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3292 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3293 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3294 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3295 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3296 }; 3297 unsigned long flags; 3298 int i; 3299 3300 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3301 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3302 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3303 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3304 } 3305 3306 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3307 { 3308 static const struct ephy_info e_info_8411_2[] = { 3309 { 0x00, 0x0008, 0x0000 }, 3310 { 0x0c, 0x37d0, 0x0820 }, 3311 { 0x1e, 0x0000, 0x0001 }, 3312 { 0x19, 0x8021, 0x0000 }, 3313 { 0x1e, 0x0000, 0x2000 }, 3314 { 0x0d, 0x0100, 0x0200 }, 3315 { 0x00, 0x0000, 0x0080 }, 3316 { 0x06, 0x0000, 0x0010 }, 3317 { 0x04, 0x0000, 0x0010 }, 3318 { 0x1d, 0x0000, 0x4000 }, 3319 }; 3320 3321 rtl_hw_start_8168g(tp); 3322 3323 rtl_ephy_init(tp, e_info_8411_2); 3324 3325 /* The following Realtek-provided magic fixes an issue with the RX unit 3326 * getting confused after the PHY having been powered-down. 3327 */ 3328 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3329 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3330 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3331 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3332 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3333 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3334 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3335 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3336 mdelay(3); 3337 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3338 3339 rtl8411b_fix_phy_down(tp); 3340 3341 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3342 3343 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3344 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3345 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3346 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3347 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3348 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3349 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3350 } 3351 3352 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3353 { 3354 static const struct ephy_info e_info_8168h_1[] = { 3355 { 0x1e, 0x0800, 0x0001 }, 3356 { 0x1d, 0x0000, 0x0800 }, 3357 { 0x05, 0xffff, 0x2089 }, 3358 { 0x06, 0xffff, 0x5881 }, 3359 { 0x04, 0xffff, 0x854a }, 3360 { 0x01, 0xffff, 0x068b } 3361 }; 3362 int rg_saw_cnt; 3363 3364 rtl_ephy_init(tp, e_info_8168h_1); 3365 3366 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3367 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3368 3369 rtl_set_def_aspm_entry_latency(tp); 3370 3371 rtl_reset_packet_filter(tp); 3372 3373 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3374 3375 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3376 3377 rtl_disable_rxdvgate(tp); 3378 3379 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3380 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3381 3382 rtl8168_config_eee_mac(tp); 3383 3384 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3385 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3386 3387 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3388 3389 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3390 3391 rtl_pcie_state_l2l3_disable(tp); 3392 3393 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3394 if (rg_saw_cnt > 0) { 3395 u16 sw_cnt_1ms_ini; 3396 3397 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3398 sw_cnt_1ms_ini &= 0x0fff; 3399 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3400 } 3401 3402 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3403 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3404 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3405 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3406 3407 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3408 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3409 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3410 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3411 } 3412 3413 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3414 { 3415 rtl8168ep_stop_cmac(tp); 3416 3417 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3418 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3419 3420 rtl_set_def_aspm_entry_latency(tp); 3421 3422 rtl_reset_packet_filter(tp); 3423 3424 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3425 3426 rtl_disable_rxdvgate(tp); 3427 3428 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3429 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3430 3431 rtl8168_config_eee_mac(tp); 3432 3433 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3434 3435 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3436 3437 rtl_pcie_state_l2l3_disable(tp); 3438 } 3439 3440 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3441 { 3442 static const struct ephy_info e_info_8168ep_3[] = { 3443 { 0x00, 0x0000, 0x0080 }, 3444 { 0x0d, 0x0100, 0x0200 }, 3445 { 0x19, 0x8021, 0x0000 }, 3446 { 0x1e, 0x0000, 0x2000 }, 3447 }; 3448 3449 rtl_ephy_init(tp, e_info_8168ep_3); 3450 3451 rtl_hw_start_8168ep(tp); 3452 3453 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3454 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3455 3456 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3457 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3458 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3459 } 3460 3461 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3462 { 3463 static const struct ephy_info e_info_8117[] = { 3464 { 0x19, 0x0040, 0x1100 }, 3465 { 0x59, 0x0040, 0x1100 }, 3466 }; 3467 int rg_saw_cnt; 3468 3469 rtl8168ep_stop_cmac(tp); 3470 rtl_ephy_init(tp, e_info_8117); 3471 3472 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3473 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3474 3475 rtl_set_def_aspm_entry_latency(tp); 3476 3477 rtl_reset_packet_filter(tp); 3478 3479 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3480 3481 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3482 3483 rtl_disable_rxdvgate(tp); 3484 3485 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3486 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3487 3488 rtl8168_config_eee_mac(tp); 3489 3490 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3491 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3492 3493 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3494 3495 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3496 3497 rtl_pcie_state_l2l3_disable(tp); 3498 3499 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3500 if (rg_saw_cnt > 0) { 3501 u16 sw_cnt_1ms_ini; 3502 3503 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3504 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3505 } 3506 3507 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3508 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3509 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3510 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3511 3512 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3513 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3514 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3515 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3516 3517 /* firmware is for MAC only */ 3518 r8169_apply_firmware(tp); 3519 } 3520 3521 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3522 { 3523 static const struct ephy_info e_info_8102e_1[] = { 3524 { 0x01, 0, 0x6e65 }, 3525 { 0x02, 0, 0x091f }, 3526 { 0x03, 0, 0xc2f9 }, 3527 { 0x06, 0, 0xafb5 }, 3528 { 0x07, 0, 0x0e00 }, 3529 { 0x19, 0, 0xec80 }, 3530 { 0x01, 0, 0x2e65 }, 3531 { 0x01, 0, 0x6e65 } 3532 }; 3533 u8 cfg1; 3534 3535 rtl_set_def_aspm_entry_latency(tp); 3536 3537 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3538 3539 RTL_W8(tp, Config1, 3540 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3541 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3542 3543 cfg1 = RTL_R8(tp, Config1); 3544 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3545 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3546 3547 rtl_ephy_init(tp, e_info_8102e_1); 3548 } 3549 3550 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3551 { 3552 rtl_set_def_aspm_entry_latency(tp); 3553 3554 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3555 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3556 } 3557 3558 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3559 { 3560 rtl_hw_start_8102e_2(tp); 3561 3562 rtl_ephy_write(tp, 0x03, 0xc2f9); 3563 } 3564 3565 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3566 { 3567 static const struct ephy_info e_info_8401[] = { 3568 { 0x01, 0xffff, 0x6fe5 }, 3569 { 0x03, 0xffff, 0x0599 }, 3570 { 0x06, 0xffff, 0xaf25 }, 3571 { 0x07, 0xffff, 0x8e68 }, 3572 }; 3573 3574 rtl_ephy_init(tp, e_info_8401); 3575 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3576 } 3577 3578 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3579 { 3580 static const struct ephy_info e_info_8105e_1[] = { 3581 { 0x07, 0, 0x4000 }, 3582 { 0x19, 0, 0x0200 }, 3583 { 0x19, 0, 0x0020 }, 3584 { 0x1e, 0, 0x2000 }, 3585 { 0x03, 0, 0x0001 }, 3586 { 0x19, 0, 0x0100 }, 3587 { 0x19, 0, 0x0004 }, 3588 { 0x0a, 0, 0x0020 } 3589 }; 3590 3591 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3592 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3593 3594 /* Disable Early Tally Counter */ 3595 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3596 3597 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3598 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3599 3600 rtl_ephy_init(tp, e_info_8105e_1); 3601 3602 rtl_pcie_state_l2l3_disable(tp); 3603 } 3604 3605 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3606 { 3607 rtl_hw_start_8105e_1(tp); 3608 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3609 } 3610 3611 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3612 { 3613 static const struct ephy_info e_info_8402[] = { 3614 { 0x19, 0xffff, 0xff64 }, 3615 { 0x1e, 0, 0x4000 } 3616 }; 3617 3618 rtl_set_def_aspm_entry_latency(tp); 3619 3620 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3621 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3622 3623 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3624 3625 rtl_ephy_init(tp, e_info_8402); 3626 3627 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3628 rtl_reset_packet_filter(tp); 3629 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3630 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3631 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3632 3633 /* disable EEE */ 3634 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3635 3636 rtl_pcie_state_l2l3_disable(tp); 3637 } 3638 3639 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3640 { 3641 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3642 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3643 3644 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3645 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3646 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3647 3648 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3649 rtl_set_aspm_entry_latency(tp, 0x2f); 3650 3651 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3652 3653 /* disable EEE */ 3654 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3655 3656 rtl_pcie_state_l2l3_disable(tp); 3657 } 3658 3659 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3660 { 3661 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3662 } 3663 3664 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3665 { 3666 rtl_pcie_state_l2l3_disable(tp); 3667 3668 RTL_W16(tp, 0x382, 0x221b); 3669 RTL_W8(tp, 0x4500, 0); 3670 RTL_W16(tp, 0x4800, 0); 3671 3672 /* disable UPS */ 3673 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3674 3675 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3676 3677 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3678 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3679 3680 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3681 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3682 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3683 3684 /* disable new tx descriptor format */ 3685 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3686 3687 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3688 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3689 3690 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3691 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3692 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3693 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3694 else 3695 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3696 3697 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3698 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3699 else 3700 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3701 3702 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3703 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3704 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3705 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3706 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3707 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3708 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3709 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3710 else 3711 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3712 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3713 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3714 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3715 3716 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3717 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3718 udelay(1); 3719 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3720 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3721 3722 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3723 3724 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3725 3726 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3727 rtl8125a_config_eee_mac(tp); 3728 else 3729 rtl8125b_config_eee_mac(tp); 3730 3731 rtl_disable_rxdvgate(tp); 3732 } 3733 3734 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3735 { 3736 static const struct ephy_info e_info_8125a_2[] = { 3737 { 0x04, 0xffff, 0xd000 }, 3738 { 0x0a, 0xffff, 0x8653 }, 3739 { 0x23, 0xffff, 0xab66 }, 3740 { 0x20, 0xffff, 0x9455 }, 3741 { 0x21, 0xffff, 0x99ff }, 3742 { 0x29, 0xffff, 0xfe04 }, 3743 3744 { 0x44, 0xffff, 0xd000 }, 3745 { 0x4a, 0xffff, 0x8653 }, 3746 { 0x63, 0xffff, 0xab66 }, 3747 { 0x60, 0xffff, 0x9455 }, 3748 { 0x61, 0xffff, 0x99ff }, 3749 { 0x69, 0xffff, 0xfe04 }, 3750 }; 3751 3752 rtl_set_def_aspm_entry_latency(tp); 3753 rtl_ephy_init(tp, e_info_8125a_2); 3754 rtl_hw_start_8125_common(tp); 3755 } 3756 3757 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3758 { 3759 static const struct ephy_info e_info_8125b[] = { 3760 { 0x0b, 0xffff, 0xa908 }, 3761 { 0x1e, 0xffff, 0x20eb }, 3762 { 0x4b, 0xffff, 0xa908 }, 3763 { 0x5e, 0xffff, 0x20eb }, 3764 { 0x22, 0x0030, 0x0020 }, 3765 { 0x62, 0x0030, 0x0020 }, 3766 }; 3767 3768 rtl_set_def_aspm_entry_latency(tp); 3769 rtl_ephy_init(tp, e_info_8125b); 3770 rtl_hw_start_8125_common(tp); 3771 } 3772 3773 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3774 { 3775 rtl_set_def_aspm_entry_latency(tp); 3776 rtl_hw_start_8125_common(tp); 3777 } 3778 3779 static void rtl_hw_config(struct rtl8169_private *tp) 3780 { 3781 static const rtl_generic_fct hw_configs[] = { 3782 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3783 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3784 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3785 [RTL_GIGA_MAC_VER_10] = NULL, 3786 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3787 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3788 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3789 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3790 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3791 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3792 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3793 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3794 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3795 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3796 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3797 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3798 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3799 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3800 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3801 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3802 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3803 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3804 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3805 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3806 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3807 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3808 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3809 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3810 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3811 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3812 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3813 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3814 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3815 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3816 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3817 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3818 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3819 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3820 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3821 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3822 }; 3823 3824 if (hw_configs[tp->mac_version]) 3825 hw_configs[tp->mac_version](tp); 3826 } 3827 3828 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3829 { 3830 int i; 3831 3832 RTL_W8(tp, INT_CFG0_8125, 0x00); 3833 3834 /* disable interrupt coalescing */ 3835 switch (tp->mac_version) { 3836 case RTL_GIGA_MAC_VER_61: 3837 for (i = 0xa00; i < 0xb00; i += 4) 3838 RTL_W32(tp, i, 0); 3839 break; 3840 case RTL_GIGA_MAC_VER_63: 3841 case RTL_GIGA_MAC_VER_65: 3842 for (i = 0xa00; i < 0xa80; i += 4) 3843 RTL_W32(tp, i, 0); 3844 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3845 break; 3846 default: 3847 break; 3848 } 3849 3850 rtl_hw_config(tp); 3851 } 3852 3853 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3854 { 3855 if (rtl_is_8168evl_up(tp)) 3856 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3857 else 3858 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3859 3860 rtl_hw_config(tp); 3861 3862 /* disable interrupt coalescing */ 3863 RTL_W16(tp, IntrMitigate, 0x0000); 3864 } 3865 3866 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3867 { 3868 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3869 3870 tp->cp_cmd |= PCIMulRW; 3871 3872 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3873 tp->mac_version == RTL_GIGA_MAC_VER_03) 3874 tp->cp_cmd |= EnAnaPLL; 3875 3876 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3877 3878 rtl8169_set_magic_reg(tp); 3879 3880 /* disable interrupt coalescing */ 3881 RTL_W16(tp, IntrMitigate, 0x0000); 3882 } 3883 3884 static void rtl_hw_start(struct rtl8169_private *tp) 3885 { 3886 rtl_unlock_config_regs(tp); 3887 /* disable aspm and clock request before ephy access */ 3888 rtl_hw_aspm_clkreq_enable(tp, false); 3889 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3890 3891 rtl_set_eee_txidle_timer(tp); 3892 3893 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3894 rtl_hw_start_8169(tp); 3895 else if (rtl_is_8125(tp)) 3896 rtl_hw_start_8125(tp); 3897 else 3898 rtl_hw_start_8168(tp); 3899 3900 rtl_enable_exit_l1(tp); 3901 rtl_hw_aspm_clkreq_enable(tp, true); 3902 rtl_set_rx_max_size(tp); 3903 rtl_set_rx_tx_desc_registers(tp); 3904 rtl_lock_config_regs(tp); 3905 3906 rtl_jumbo_config(tp); 3907 3908 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3909 rtl_pci_commit(tp); 3910 3911 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3912 rtl_init_rxcfg(tp); 3913 rtl_set_tx_config_registers(tp); 3914 rtl_set_rx_config_features(tp, tp->dev->features); 3915 rtl_set_rx_mode(tp->dev); 3916 rtl_irq_enable(tp); 3917 } 3918 3919 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3920 { 3921 struct rtl8169_private *tp = netdev_priv(dev); 3922 3923 dev->mtu = new_mtu; 3924 netdev_update_features(dev); 3925 rtl_jumbo_config(tp); 3926 rtl_set_eee_txidle_timer(tp); 3927 3928 return 0; 3929 } 3930 3931 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3932 { 3933 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3934 3935 desc->opts2 = 0; 3936 /* Force memory writes to complete before releasing descriptor */ 3937 dma_wmb(); 3938 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3939 } 3940 3941 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3942 struct RxDesc *desc) 3943 { 3944 struct device *d = tp_to_dev(tp); 3945 int node = dev_to_node(d); 3946 dma_addr_t mapping; 3947 struct page *data; 3948 3949 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3950 if (!data) 3951 return NULL; 3952 3953 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3954 if (unlikely(dma_mapping_error(d, mapping))) { 3955 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3956 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3957 return NULL; 3958 } 3959 3960 desc->addr = cpu_to_le64(mapping); 3961 rtl8169_mark_to_asic(desc); 3962 3963 return data; 3964 } 3965 3966 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3967 { 3968 int i; 3969 3970 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3971 dma_unmap_page(tp_to_dev(tp), 3972 le64_to_cpu(tp->RxDescArray[i].addr), 3973 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3974 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3975 tp->Rx_databuff[i] = NULL; 3976 tp->RxDescArray[i].addr = 0; 3977 tp->RxDescArray[i].opts1 = 0; 3978 } 3979 } 3980 3981 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3982 { 3983 int i; 3984 3985 for (i = 0; i < NUM_RX_DESC; i++) { 3986 struct page *data; 3987 3988 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3989 if (!data) { 3990 rtl8169_rx_clear(tp); 3991 return -ENOMEM; 3992 } 3993 tp->Rx_databuff[i] = data; 3994 } 3995 3996 /* mark as last descriptor in the ring */ 3997 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3998 3999 return 0; 4000 } 4001 4002 static int rtl8169_init_ring(struct rtl8169_private *tp) 4003 { 4004 rtl8169_init_ring_indexes(tp); 4005 4006 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4007 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4008 4009 return rtl8169_rx_fill(tp); 4010 } 4011 4012 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4013 { 4014 struct ring_info *tx_skb = tp->tx_skb + entry; 4015 struct TxDesc *desc = tp->TxDescArray + entry; 4016 4017 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4018 DMA_TO_DEVICE); 4019 memset(desc, 0, sizeof(*desc)); 4020 memset(tx_skb, 0, sizeof(*tx_skb)); 4021 } 4022 4023 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4024 unsigned int n) 4025 { 4026 unsigned int i; 4027 4028 for (i = 0; i < n; i++) { 4029 unsigned int entry = (start + i) % NUM_TX_DESC; 4030 struct ring_info *tx_skb = tp->tx_skb + entry; 4031 unsigned int len = tx_skb->len; 4032 4033 if (len) { 4034 struct sk_buff *skb = tx_skb->skb; 4035 4036 rtl8169_unmap_tx_skb(tp, entry); 4037 if (skb) 4038 dev_consume_skb_any(skb); 4039 } 4040 } 4041 } 4042 4043 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4044 { 4045 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4046 netdev_reset_queue(tp->dev); 4047 } 4048 4049 static void rtl8169_cleanup(struct rtl8169_private *tp) 4050 { 4051 napi_disable(&tp->napi); 4052 4053 /* Give a racing hard_start_xmit a few cycles to complete. */ 4054 synchronize_net(); 4055 4056 /* Disable interrupts */ 4057 rtl8169_irq_mask_and_ack(tp); 4058 4059 rtl_rx_close(tp); 4060 4061 switch (tp->mac_version) { 4062 case RTL_GIGA_MAC_VER_28: 4063 case RTL_GIGA_MAC_VER_31: 4064 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4065 break; 4066 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4067 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4068 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4069 break; 4070 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 4071 rtl_enable_rxdvgate(tp); 4072 fsleep(2000); 4073 break; 4074 default: 4075 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4076 fsleep(100); 4077 break; 4078 } 4079 4080 rtl_hw_reset(tp); 4081 4082 rtl8169_tx_clear(tp); 4083 rtl8169_init_ring_indexes(tp); 4084 } 4085 4086 static void rtl_reset_work(struct rtl8169_private *tp) 4087 { 4088 int i; 4089 4090 netif_stop_queue(tp->dev); 4091 4092 rtl8169_cleanup(tp); 4093 4094 for (i = 0; i < NUM_RX_DESC; i++) 4095 rtl8169_mark_to_asic(tp->RxDescArray + i); 4096 4097 napi_enable(&tp->napi); 4098 rtl_hw_start(tp); 4099 } 4100 4101 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4102 { 4103 struct rtl8169_private *tp = netdev_priv(dev); 4104 4105 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4106 } 4107 4108 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4109 void *addr, unsigned int entry, bool desc_own) 4110 { 4111 struct TxDesc *txd = tp->TxDescArray + entry; 4112 struct device *d = tp_to_dev(tp); 4113 dma_addr_t mapping; 4114 u32 opts1; 4115 int ret; 4116 4117 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4118 ret = dma_mapping_error(d, mapping); 4119 if (unlikely(ret)) { 4120 if (net_ratelimit()) 4121 netdev_err(tp->dev, "Failed to map TX data!\n"); 4122 return ret; 4123 } 4124 4125 txd->addr = cpu_to_le64(mapping); 4126 txd->opts2 = cpu_to_le32(opts[1]); 4127 4128 opts1 = opts[0] | len; 4129 if (entry == NUM_TX_DESC - 1) 4130 opts1 |= RingEnd; 4131 if (desc_own) 4132 opts1 |= DescOwn; 4133 txd->opts1 = cpu_to_le32(opts1); 4134 4135 tp->tx_skb[entry].len = len; 4136 4137 return 0; 4138 } 4139 4140 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4141 const u32 *opts, unsigned int entry) 4142 { 4143 struct skb_shared_info *info = skb_shinfo(skb); 4144 unsigned int cur_frag; 4145 4146 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4147 const skb_frag_t *frag = info->frags + cur_frag; 4148 void *addr = skb_frag_address(frag); 4149 u32 len = skb_frag_size(frag); 4150 4151 entry = (entry + 1) % NUM_TX_DESC; 4152 4153 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4154 goto err_out; 4155 } 4156 4157 return 0; 4158 4159 err_out: 4160 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4161 return -EIO; 4162 } 4163 4164 static bool rtl_skb_is_udp(struct sk_buff *skb) 4165 { 4166 int no = skb_network_offset(skb); 4167 struct ipv6hdr *i6h, _i6h; 4168 struct iphdr *ih, _ih; 4169 4170 switch (vlan_get_protocol(skb)) { 4171 case htons(ETH_P_IP): 4172 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4173 return ih && ih->protocol == IPPROTO_UDP; 4174 case htons(ETH_P_IPV6): 4175 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4176 return i6h && i6h->nexthdr == IPPROTO_UDP; 4177 default: 4178 return false; 4179 } 4180 } 4181 4182 #define RTL_MIN_PATCH_LEN 47 4183 4184 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4185 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4186 struct sk_buff *skb) 4187 { 4188 unsigned int padto = 0, len = skb->len; 4189 4190 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4191 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4192 unsigned int trans_data_len = skb_tail_pointer(skb) - 4193 skb_transport_header(skb); 4194 4195 if (trans_data_len >= offsetof(struct udphdr, len) && 4196 trans_data_len < RTL_MIN_PATCH_LEN) { 4197 u16 dest = ntohs(udp_hdr(skb)->dest); 4198 4199 /* dest is a standard PTP port */ 4200 if (dest == 319 || dest == 320) 4201 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4202 } 4203 4204 if (trans_data_len < sizeof(struct udphdr)) 4205 padto = max_t(unsigned int, padto, 4206 len + sizeof(struct udphdr) - trans_data_len); 4207 } 4208 4209 return padto; 4210 } 4211 4212 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4213 struct sk_buff *skb) 4214 { 4215 unsigned int padto; 4216 4217 padto = rtl8125_quirk_udp_padto(tp, skb); 4218 4219 switch (tp->mac_version) { 4220 case RTL_GIGA_MAC_VER_34: 4221 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 4222 padto = max_t(unsigned int, padto, ETH_ZLEN); 4223 break; 4224 default: 4225 break; 4226 } 4227 4228 return padto; 4229 } 4230 4231 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4232 { 4233 u32 mss = skb_shinfo(skb)->gso_size; 4234 4235 if (mss) { 4236 opts[0] |= TD_LSO; 4237 opts[0] |= mss << TD0_MSS_SHIFT; 4238 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4239 const struct iphdr *ip = ip_hdr(skb); 4240 4241 if (ip->protocol == IPPROTO_TCP) 4242 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4243 else if (ip->protocol == IPPROTO_UDP) 4244 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4245 else 4246 WARN_ON_ONCE(1); 4247 } 4248 } 4249 4250 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4251 struct sk_buff *skb, u32 *opts) 4252 { 4253 struct skb_shared_info *shinfo = skb_shinfo(skb); 4254 u32 mss = shinfo->gso_size; 4255 4256 if (mss) { 4257 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4258 opts[0] |= TD1_GTSENV4; 4259 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4260 if (skb_cow_head(skb, 0)) 4261 return false; 4262 4263 tcp_v6_gso_csum_prep(skb); 4264 opts[0] |= TD1_GTSENV6; 4265 } else { 4266 WARN_ON_ONCE(1); 4267 } 4268 4269 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4270 opts[1] |= mss << TD1_MSS_SHIFT; 4271 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4272 u8 ip_protocol; 4273 4274 switch (vlan_get_protocol(skb)) { 4275 case htons(ETH_P_IP): 4276 opts[1] |= TD1_IPv4_CS; 4277 ip_protocol = ip_hdr(skb)->protocol; 4278 break; 4279 4280 case htons(ETH_P_IPV6): 4281 opts[1] |= TD1_IPv6_CS; 4282 ip_protocol = ipv6_hdr(skb)->nexthdr; 4283 break; 4284 4285 default: 4286 ip_protocol = IPPROTO_RAW; 4287 break; 4288 } 4289 4290 if (ip_protocol == IPPROTO_TCP) 4291 opts[1] |= TD1_TCP_CS; 4292 else if (ip_protocol == IPPROTO_UDP) 4293 opts[1] |= TD1_UDP_CS; 4294 else 4295 WARN_ON_ONCE(1); 4296 4297 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4298 } else { 4299 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4300 4301 /* skb_padto would free the skb on error */ 4302 return !__skb_put_padto(skb, padto, false); 4303 } 4304 4305 return true; 4306 } 4307 4308 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4309 { 4310 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4311 } 4312 4313 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4314 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4315 { 4316 switch (tp->mac_version) { 4317 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4318 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4319 return false; 4320 default: 4321 return true; 4322 } 4323 } 4324 4325 static void rtl8169_doorbell(struct rtl8169_private *tp) 4326 { 4327 if (rtl_is_8125(tp)) 4328 RTL_W16(tp, TxPoll_8125, BIT(0)); 4329 else 4330 RTL_W8(tp, TxPoll, NPQ); 4331 } 4332 4333 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4334 struct net_device *dev) 4335 { 4336 unsigned int frags = skb_shinfo(skb)->nr_frags; 4337 struct rtl8169_private *tp = netdev_priv(dev); 4338 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4339 struct TxDesc *txd_first, *txd_last; 4340 bool stop_queue, door_bell; 4341 u32 opts[2]; 4342 4343 if (unlikely(!rtl_tx_slots_avail(tp))) { 4344 if (net_ratelimit()) 4345 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4346 goto err_stop_0; 4347 } 4348 4349 opts[1] = rtl8169_tx_vlan_tag(skb); 4350 opts[0] = 0; 4351 4352 if (!rtl_chip_supports_csum_v2(tp)) 4353 rtl8169_tso_csum_v1(skb, opts); 4354 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4355 goto err_dma_0; 4356 4357 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4358 entry, false))) 4359 goto err_dma_0; 4360 4361 txd_first = tp->TxDescArray + entry; 4362 4363 if (frags) { 4364 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4365 goto err_dma_1; 4366 entry = (entry + frags) % NUM_TX_DESC; 4367 } 4368 4369 txd_last = tp->TxDescArray + entry; 4370 txd_last->opts1 |= cpu_to_le32(LastFrag); 4371 tp->tx_skb[entry].skb = skb; 4372 4373 skb_tx_timestamp(skb); 4374 4375 /* Force memory writes to complete before releasing descriptor */ 4376 dma_wmb(); 4377 4378 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4379 4380 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4381 4382 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4383 smp_wmb(); 4384 4385 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4386 4387 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4388 R8169_TX_STOP_THRS, 4389 R8169_TX_START_THRS); 4390 if (door_bell || stop_queue) 4391 rtl8169_doorbell(tp); 4392 4393 return NETDEV_TX_OK; 4394 4395 err_dma_1: 4396 rtl8169_unmap_tx_skb(tp, entry); 4397 err_dma_0: 4398 dev_kfree_skb_any(skb); 4399 dev->stats.tx_dropped++; 4400 return NETDEV_TX_OK; 4401 4402 err_stop_0: 4403 netif_stop_queue(dev); 4404 dev->stats.tx_dropped++; 4405 return NETDEV_TX_BUSY; 4406 } 4407 4408 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4409 { 4410 struct skb_shared_info *info = skb_shinfo(skb); 4411 unsigned int nr_frags = info->nr_frags; 4412 4413 if (!nr_frags) 4414 return UINT_MAX; 4415 4416 return skb_frag_size(info->frags + nr_frags - 1); 4417 } 4418 4419 /* Workaround for hw issues with TSO on RTL8168evl */ 4420 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4421 netdev_features_t features) 4422 { 4423 /* IPv4 header has options field */ 4424 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4425 ip_hdrlen(skb) > sizeof(struct iphdr)) 4426 features &= ~NETIF_F_ALL_TSO; 4427 4428 /* IPv4 TCP header has options field */ 4429 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4430 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4431 features &= ~NETIF_F_ALL_TSO; 4432 4433 else if (rtl_last_frag_len(skb) <= 6) 4434 features &= ~NETIF_F_ALL_TSO; 4435 4436 return features; 4437 } 4438 4439 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4440 struct net_device *dev, 4441 netdev_features_t features) 4442 { 4443 struct rtl8169_private *tp = netdev_priv(dev); 4444 4445 if (skb_is_gso(skb)) { 4446 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4447 features = rtl8168evl_fix_tso(skb, features); 4448 4449 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4450 rtl_chip_supports_csum_v2(tp)) 4451 features &= ~NETIF_F_ALL_TSO; 4452 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4453 /* work around hw bug on some chip versions */ 4454 if (skb->len < ETH_ZLEN) 4455 features &= ~NETIF_F_CSUM_MASK; 4456 4457 if (rtl_quirk_packet_padto(tp, skb)) 4458 features &= ~NETIF_F_CSUM_MASK; 4459 4460 if (skb_transport_offset(skb) > TCPHO_MAX && 4461 rtl_chip_supports_csum_v2(tp)) 4462 features &= ~NETIF_F_CSUM_MASK; 4463 } 4464 4465 return vlan_features_check(skb, features); 4466 } 4467 4468 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4469 { 4470 struct rtl8169_private *tp = netdev_priv(dev); 4471 struct pci_dev *pdev = tp->pci_dev; 4472 int pci_status_errs; 4473 u16 pci_cmd; 4474 4475 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4476 4477 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4478 4479 if (net_ratelimit()) 4480 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4481 pci_cmd, pci_status_errs); 4482 4483 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4484 } 4485 4486 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4487 int budget) 4488 { 4489 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4490 struct sk_buff *skb; 4491 4492 dirty_tx = tp->dirty_tx; 4493 4494 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4495 unsigned int entry = dirty_tx % NUM_TX_DESC; 4496 u32 status; 4497 4498 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4499 if (status & DescOwn) 4500 break; 4501 4502 skb = tp->tx_skb[entry].skb; 4503 rtl8169_unmap_tx_skb(tp, entry); 4504 4505 if (skb) { 4506 pkts_compl++; 4507 bytes_compl += skb->len; 4508 napi_consume_skb(skb, budget); 4509 } 4510 dirty_tx++; 4511 } 4512 4513 if (tp->dirty_tx != dirty_tx) { 4514 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4515 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4516 4517 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4518 rtl_tx_slots_avail(tp), 4519 R8169_TX_START_THRS); 4520 /* 4521 * 8168 hack: TxPoll requests are lost when the Tx packets are 4522 * too close. Let's kick an extra TxPoll request when a burst 4523 * of start_xmit activity is detected (if it is not detected, 4524 * it is slow enough). -- FR 4525 * If skb is NULL then we come here again once a tx irq is 4526 * triggered after the last fragment is marked transmitted. 4527 */ 4528 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4529 rtl8169_doorbell(tp); 4530 } 4531 } 4532 4533 static inline int rtl8169_fragmented_frame(u32 status) 4534 { 4535 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4536 } 4537 4538 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4539 { 4540 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4541 4542 if (status == RxProtoTCP || status == RxProtoUDP) 4543 skb->ip_summed = CHECKSUM_UNNECESSARY; 4544 else 4545 skb_checksum_none_assert(skb); 4546 } 4547 4548 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4549 { 4550 struct device *d = tp_to_dev(tp); 4551 int count; 4552 4553 for (count = 0; count < budget; count++, tp->cur_rx++) { 4554 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4555 struct RxDesc *desc = tp->RxDescArray + entry; 4556 struct sk_buff *skb; 4557 const void *rx_buf; 4558 dma_addr_t addr; 4559 u32 status; 4560 4561 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4562 if (status & DescOwn) 4563 break; 4564 4565 /* This barrier is needed to keep us from reading 4566 * any other fields out of the Rx descriptor until 4567 * we know the status of DescOwn 4568 */ 4569 dma_rmb(); 4570 4571 if (unlikely(status & RxRES)) { 4572 if (net_ratelimit()) 4573 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4574 status); 4575 dev->stats.rx_errors++; 4576 if (status & (RxRWT | RxRUNT)) 4577 dev->stats.rx_length_errors++; 4578 if (status & RxCRC) 4579 dev->stats.rx_crc_errors++; 4580 4581 if (!(dev->features & NETIF_F_RXALL)) 4582 goto release_descriptor; 4583 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4584 goto release_descriptor; 4585 } 4586 4587 pkt_size = status & GENMASK(13, 0); 4588 if (likely(!(dev->features & NETIF_F_RXFCS))) 4589 pkt_size -= ETH_FCS_LEN; 4590 4591 /* The driver does not support incoming fragmented frames. 4592 * They are seen as a symptom of over-mtu sized frames. 4593 */ 4594 if (unlikely(rtl8169_fragmented_frame(status))) { 4595 dev->stats.rx_dropped++; 4596 dev->stats.rx_length_errors++; 4597 goto release_descriptor; 4598 } 4599 4600 skb = napi_alloc_skb(&tp->napi, pkt_size); 4601 if (unlikely(!skb)) { 4602 dev->stats.rx_dropped++; 4603 goto release_descriptor; 4604 } 4605 4606 addr = le64_to_cpu(desc->addr); 4607 rx_buf = page_address(tp->Rx_databuff[entry]); 4608 4609 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4610 prefetch(rx_buf); 4611 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4612 skb->tail += pkt_size; 4613 skb->len = pkt_size; 4614 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4615 4616 rtl8169_rx_csum(skb, status); 4617 skb->protocol = eth_type_trans(skb, dev); 4618 4619 rtl8169_rx_vlan_tag(desc, skb); 4620 4621 if (skb->pkt_type == PACKET_MULTICAST) 4622 dev->stats.multicast++; 4623 4624 napi_gro_receive(&tp->napi, skb); 4625 4626 dev_sw_netstats_rx_add(dev, pkt_size); 4627 release_descriptor: 4628 rtl8169_mark_to_asic(desc); 4629 } 4630 4631 return count; 4632 } 4633 4634 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4635 { 4636 struct rtl8169_private *tp = dev_instance; 4637 u32 status = rtl_get_events(tp); 4638 4639 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4640 return IRQ_NONE; 4641 4642 if (unlikely(status & SYSErr)) { 4643 rtl8169_pcierr_interrupt(tp->dev); 4644 goto out; 4645 } 4646 4647 if (status & LinkChg) 4648 phy_mac_interrupt(tp->phydev); 4649 4650 if (unlikely(status & RxFIFOOver && 4651 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4652 netif_stop_queue(tp->dev); 4653 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4654 } 4655 4656 if (napi_schedule_prep(&tp->napi)) { 4657 rtl_irq_disable(tp); 4658 __napi_schedule(&tp->napi); 4659 } 4660 out: 4661 rtl_ack_events(tp, status); 4662 4663 return IRQ_HANDLED; 4664 } 4665 4666 static void rtl_task(struct work_struct *work) 4667 { 4668 struct rtl8169_private *tp = 4669 container_of(work, struct rtl8169_private, wk.work); 4670 int ret; 4671 4672 rtnl_lock(); 4673 4674 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4675 goto out_unlock; 4676 4677 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4678 /* if chip isn't accessible, reset bus to revive it */ 4679 if (RTL_R32(tp, TxConfig) == ~0) { 4680 ret = pci_reset_bus(tp->pci_dev); 4681 if (ret < 0) { 4682 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4683 netif_device_detach(tp->dev); 4684 goto out_unlock; 4685 } 4686 } 4687 4688 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4689 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4690 PCIE_LINK_STATE_L0S); 4691 if (!ret) 4692 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4693 goto reset; 4694 } 4695 4696 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4697 reset: 4698 rtl_reset_work(tp); 4699 netif_wake_queue(tp->dev); 4700 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4701 rtl_reset_work(tp); 4702 } 4703 out_unlock: 4704 rtnl_unlock(); 4705 } 4706 4707 static int rtl8169_poll(struct napi_struct *napi, int budget) 4708 { 4709 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4710 struct net_device *dev = tp->dev; 4711 int work_done; 4712 4713 rtl_tx(dev, tp, budget); 4714 4715 work_done = rtl_rx(dev, tp, budget); 4716 4717 if (work_done < budget && napi_complete_done(napi, work_done)) 4718 rtl_irq_enable(tp); 4719 4720 return work_done; 4721 } 4722 4723 static void r8169_phylink_handler(struct net_device *ndev) 4724 { 4725 struct rtl8169_private *tp = netdev_priv(ndev); 4726 struct device *d = tp_to_dev(tp); 4727 4728 if (netif_carrier_ok(ndev)) { 4729 rtl_link_chg_patch(tp); 4730 pm_request_resume(d); 4731 netif_wake_queue(tp->dev); 4732 } else { 4733 /* In few cases rx is broken after link-down otherwise */ 4734 if (rtl_is_8125(tp)) 4735 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4736 pm_runtime_idle(d); 4737 } 4738 4739 phy_print_status(tp->phydev); 4740 } 4741 4742 static int r8169_phy_connect(struct rtl8169_private *tp) 4743 { 4744 struct phy_device *phydev = tp->phydev; 4745 phy_interface_t phy_mode; 4746 int ret; 4747 4748 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4749 PHY_INTERFACE_MODE_MII; 4750 4751 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4752 phy_mode); 4753 if (ret) 4754 return ret; 4755 4756 if (!tp->supports_gmii) 4757 phy_set_max_speed(phydev, SPEED_100); 4758 4759 phy_attached_info(phydev); 4760 4761 return 0; 4762 } 4763 4764 static void rtl8169_down(struct rtl8169_private *tp) 4765 { 4766 /* Clear all task flags */ 4767 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4768 4769 phy_stop(tp->phydev); 4770 4771 rtl8169_update_counters(tp); 4772 4773 pci_clear_master(tp->pci_dev); 4774 rtl_pci_commit(tp); 4775 4776 rtl8169_cleanup(tp); 4777 rtl_disable_exit_l1(tp); 4778 rtl_prepare_power_down(tp); 4779 4780 if (tp->dash_type != RTL_DASH_NONE) 4781 rtl8168_driver_stop(tp); 4782 } 4783 4784 static void rtl8169_up(struct rtl8169_private *tp) 4785 { 4786 if (tp->dash_type != RTL_DASH_NONE) 4787 rtl8168_driver_start(tp); 4788 4789 pci_set_master(tp->pci_dev); 4790 phy_init_hw(tp->phydev); 4791 phy_resume(tp->phydev); 4792 rtl8169_init_phy(tp); 4793 napi_enable(&tp->napi); 4794 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4795 rtl_reset_work(tp); 4796 4797 phy_start(tp->phydev); 4798 } 4799 4800 static int rtl8169_close(struct net_device *dev) 4801 { 4802 struct rtl8169_private *tp = netdev_priv(dev); 4803 struct pci_dev *pdev = tp->pci_dev; 4804 4805 pm_runtime_get_sync(&pdev->dev); 4806 4807 netif_stop_queue(dev); 4808 rtl8169_down(tp); 4809 rtl8169_rx_clear(tp); 4810 4811 cancel_work(&tp->wk.work); 4812 4813 free_irq(tp->irq, tp); 4814 4815 phy_disconnect(tp->phydev); 4816 4817 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4818 tp->RxPhyAddr); 4819 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4820 tp->TxPhyAddr); 4821 tp->TxDescArray = NULL; 4822 tp->RxDescArray = NULL; 4823 4824 pm_runtime_put_sync(&pdev->dev); 4825 4826 return 0; 4827 } 4828 4829 #ifdef CONFIG_NET_POLL_CONTROLLER 4830 static void rtl8169_netpoll(struct net_device *dev) 4831 { 4832 struct rtl8169_private *tp = netdev_priv(dev); 4833 4834 rtl8169_interrupt(tp->irq, tp); 4835 } 4836 #endif 4837 4838 static int rtl_open(struct net_device *dev) 4839 { 4840 struct rtl8169_private *tp = netdev_priv(dev); 4841 struct pci_dev *pdev = tp->pci_dev; 4842 unsigned long irqflags; 4843 int retval = -ENOMEM; 4844 4845 pm_runtime_get_sync(&pdev->dev); 4846 4847 /* 4848 * Rx and Tx descriptors needs 256 bytes alignment. 4849 * dma_alloc_coherent provides more. 4850 */ 4851 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4852 &tp->TxPhyAddr, GFP_KERNEL); 4853 if (!tp->TxDescArray) 4854 goto out; 4855 4856 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4857 &tp->RxPhyAddr, GFP_KERNEL); 4858 if (!tp->RxDescArray) 4859 goto err_free_tx_0; 4860 4861 retval = rtl8169_init_ring(tp); 4862 if (retval < 0) 4863 goto err_free_rx_1; 4864 4865 rtl_request_firmware(tp); 4866 4867 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4868 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4869 if (retval < 0) 4870 goto err_release_fw_2; 4871 4872 retval = r8169_phy_connect(tp); 4873 if (retval) 4874 goto err_free_irq; 4875 4876 rtl8169_up(tp); 4877 rtl8169_init_counter_offsets(tp); 4878 netif_start_queue(dev); 4879 out: 4880 pm_runtime_put_sync(&pdev->dev); 4881 4882 return retval; 4883 4884 err_free_irq: 4885 free_irq(tp->irq, tp); 4886 err_release_fw_2: 4887 rtl_release_firmware(tp); 4888 rtl8169_rx_clear(tp); 4889 err_free_rx_1: 4890 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4891 tp->RxPhyAddr); 4892 tp->RxDescArray = NULL; 4893 err_free_tx_0: 4894 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4895 tp->TxPhyAddr); 4896 tp->TxDescArray = NULL; 4897 goto out; 4898 } 4899 4900 static void 4901 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4902 { 4903 struct rtl8169_private *tp = netdev_priv(dev); 4904 struct pci_dev *pdev = tp->pci_dev; 4905 struct rtl8169_counters *counters = tp->counters; 4906 4907 pm_runtime_get_noresume(&pdev->dev); 4908 4909 netdev_stats_to_stats64(stats, &dev->stats); 4910 dev_fetch_sw_netstats(stats, dev->tstats); 4911 4912 /* 4913 * Fetch additional counter values missing in stats collected by driver 4914 * from tally counters. 4915 */ 4916 if (pm_runtime_active(&pdev->dev)) 4917 rtl8169_update_counters(tp); 4918 4919 /* 4920 * Subtract values fetched during initalization. 4921 * See rtl8169_init_counter_offsets for a description why we do that. 4922 */ 4923 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4924 le64_to_cpu(tp->tc_offset.tx_errors); 4925 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4926 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4927 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4928 le16_to_cpu(tp->tc_offset.tx_aborted); 4929 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4930 le16_to_cpu(tp->tc_offset.rx_missed); 4931 4932 pm_runtime_put_noidle(&pdev->dev); 4933 } 4934 4935 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4936 { 4937 netif_device_detach(tp->dev); 4938 4939 if (netif_running(tp->dev)) 4940 rtl8169_down(tp); 4941 } 4942 4943 static int rtl8169_runtime_resume(struct device *dev) 4944 { 4945 struct rtl8169_private *tp = dev_get_drvdata(dev); 4946 4947 rtl_rar_set(tp, tp->dev->dev_addr); 4948 __rtl8169_set_wol(tp, tp->saved_wolopts); 4949 4950 if (tp->TxDescArray) 4951 rtl8169_up(tp); 4952 4953 netif_device_attach(tp->dev); 4954 4955 return 0; 4956 } 4957 4958 static int rtl8169_suspend(struct device *device) 4959 { 4960 struct rtl8169_private *tp = dev_get_drvdata(device); 4961 4962 rtnl_lock(); 4963 rtl8169_net_suspend(tp); 4964 if (!device_may_wakeup(tp_to_dev(tp))) 4965 clk_disable_unprepare(tp->clk); 4966 rtnl_unlock(); 4967 4968 return 0; 4969 } 4970 4971 static int rtl8169_resume(struct device *device) 4972 { 4973 struct rtl8169_private *tp = dev_get_drvdata(device); 4974 4975 if (!device_may_wakeup(tp_to_dev(tp))) 4976 clk_prepare_enable(tp->clk); 4977 4978 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4979 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4980 rtl_init_rxcfg(tp); 4981 4982 return rtl8169_runtime_resume(device); 4983 } 4984 4985 static int rtl8169_runtime_suspend(struct device *device) 4986 { 4987 struct rtl8169_private *tp = dev_get_drvdata(device); 4988 4989 if (!tp->TxDescArray) { 4990 netif_device_detach(tp->dev); 4991 return 0; 4992 } 4993 4994 rtnl_lock(); 4995 __rtl8169_set_wol(tp, WAKE_PHY); 4996 rtl8169_net_suspend(tp); 4997 rtnl_unlock(); 4998 4999 return 0; 5000 } 5001 5002 static int rtl8169_runtime_idle(struct device *device) 5003 { 5004 struct rtl8169_private *tp = dev_get_drvdata(device); 5005 5006 if (tp->dash_enabled) 5007 return -EBUSY; 5008 5009 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5010 pm_schedule_suspend(device, 10000); 5011 5012 return -EBUSY; 5013 } 5014 5015 static const struct dev_pm_ops rtl8169_pm_ops = { 5016 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5017 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5018 rtl8169_runtime_idle) 5019 }; 5020 5021 static void rtl_shutdown(struct pci_dev *pdev) 5022 { 5023 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5024 5025 rtnl_lock(); 5026 rtl8169_net_suspend(tp); 5027 rtnl_unlock(); 5028 5029 /* Restore original MAC address */ 5030 rtl_rar_set(tp, tp->dev->perm_addr); 5031 5032 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5033 pci_wake_from_d3(pdev, tp->saved_wolopts); 5034 pci_set_power_state(pdev, PCI_D3hot); 5035 } 5036 } 5037 5038 static void rtl_remove_one(struct pci_dev *pdev) 5039 { 5040 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5041 5042 if (pci_dev_run_wake(pdev)) 5043 pm_runtime_get_noresume(&pdev->dev); 5044 5045 cancel_work_sync(&tp->wk.work); 5046 5047 unregister_netdev(tp->dev); 5048 5049 if (tp->dash_type != RTL_DASH_NONE) 5050 rtl8168_driver_stop(tp); 5051 5052 rtl_release_firmware(tp); 5053 5054 /* restore original MAC address */ 5055 rtl_rar_set(tp, tp->dev->perm_addr); 5056 } 5057 5058 static const struct net_device_ops rtl_netdev_ops = { 5059 .ndo_open = rtl_open, 5060 .ndo_stop = rtl8169_close, 5061 .ndo_get_stats64 = rtl8169_get_stats64, 5062 .ndo_start_xmit = rtl8169_start_xmit, 5063 .ndo_features_check = rtl8169_features_check, 5064 .ndo_tx_timeout = rtl8169_tx_timeout, 5065 .ndo_validate_addr = eth_validate_addr, 5066 .ndo_change_mtu = rtl8169_change_mtu, 5067 .ndo_fix_features = rtl8169_fix_features, 5068 .ndo_set_features = rtl8169_set_features, 5069 .ndo_set_mac_address = rtl_set_mac_address, 5070 .ndo_eth_ioctl = phy_do_ioctl_running, 5071 .ndo_set_rx_mode = rtl_set_rx_mode, 5072 #ifdef CONFIG_NET_POLL_CONTROLLER 5073 .ndo_poll_controller = rtl8169_netpoll, 5074 #endif 5075 5076 }; 5077 5078 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5079 { 5080 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5081 5082 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5083 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5084 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5085 /* special workaround needed */ 5086 tp->irq_mask |= RxFIFOOver; 5087 else 5088 tp->irq_mask |= RxOverflow; 5089 } 5090 5091 static int rtl_alloc_irq(struct rtl8169_private *tp) 5092 { 5093 unsigned int flags; 5094 5095 switch (tp->mac_version) { 5096 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5097 rtl_unlock_config_regs(tp); 5098 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5099 rtl_lock_config_regs(tp); 5100 fallthrough; 5101 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5102 flags = PCI_IRQ_LEGACY; 5103 break; 5104 default: 5105 flags = PCI_IRQ_ALL_TYPES; 5106 break; 5107 } 5108 5109 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5110 } 5111 5112 static void rtl_read_mac_address(struct rtl8169_private *tp, 5113 u8 mac_addr[ETH_ALEN]) 5114 { 5115 /* Get MAC address */ 5116 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5117 u32 value; 5118 5119 value = rtl_eri_read(tp, 0xe0); 5120 put_unaligned_le32(value, mac_addr); 5121 value = rtl_eri_read(tp, 0xe4); 5122 put_unaligned_le16(value, mac_addr + 4); 5123 } else if (rtl_is_8125(tp)) { 5124 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5125 } 5126 } 5127 5128 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5129 { 5130 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5131 } 5132 5133 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5134 { 5135 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5136 } 5137 5138 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5139 { 5140 struct rtl8169_private *tp = mii_bus->priv; 5141 5142 if (phyaddr > 0) 5143 return -ENODEV; 5144 5145 return rtl_readphy(tp, phyreg); 5146 } 5147 5148 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5149 int phyreg, u16 val) 5150 { 5151 struct rtl8169_private *tp = mii_bus->priv; 5152 5153 if (phyaddr > 0) 5154 return -ENODEV; 5155 5156 rtl_writephy(tp, phyreg, val); 5157 5158 return 0; 5159 } 5160 5161 static int r8169_mdio_register(struct rtl8169_private *tp) 5162 { 5163 struct pci_dev *pdev = tp->pci_dev; 5164 struct mii_bus *new_bus; 5165 int ret; 5166 5167 /* On some boards with this chip version the BIOS is buggy and misses 5168 * to reset the PHY page selector. This results in the PHY ID read 5169 * accessing registers on a different page, returning a more or 5170 * less random value. Fix this by resetting the page selector first. 5171 */ 5172 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5173 tp->mac_version == RTL_GIGA_MAC_VER_26) 5174 r8169_mdio_write(tp, 0x1f, 0); 5175 5176 new_bus = devm_mdiobus_alloc(&pdev->dev); 5177 if (!new_bus) 5178 return -ENOMEM; 5179 5180 new_bus->name = "r8169"; 5181 new_bus->priv = tp; 5182 new_bus->parent = &pdev->dev; 5183 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5184 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5185 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5186 5187 new_bus->read = r8169_mdio_read_reg; 5188 new_bus->write = r8169_mdio_write_reg; 5189 5190 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5191 if (ret) 5192 return ret; 5193 5194 tp->phydev = mdiobus_get_phy(new_bus, 0); 5195 if (!tp->phydev) { 5196 return -ENODEV; 5197 } else if (!tp->phydev->drv) { 5198 /* Most chip versions fail with the genphy driver. 5199 * Therefore ensure that the dedicated PHY driver is loaded. 5200 */ 5201 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5202 tp->phydev->phy_id); 5203 return -EUNATCH; 5204 } 5205 5206 tp->phydev->mac_managed_pm = true; 5207 if (rtl_supports_eee(tp)) 5208 phy_support_eee(tp->phydev); 5209 phy_support_asym_pause(tp->phydev); 5210 5211 /* PHY will be woken up in rtl_open() */ 5212 phy_suspend(tp->phydev); 5213 5214 return 0; 5215 } 5216 5217 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5218 { 5219 rtl_enable_rxdvgate(tp); 5220 5221 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5222 msleep(1); 5223 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5224 5225 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5226 r8168g_wait_ll_share_fifo_ready(tp); 5227 5228 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5229 r8168g_wait_ll_share_fifo_ready(tp); 5230 } 5231 5232 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5233 { 5234 rtl_enable_rxdvgate(tp); 5235 5236 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5237 msleep(1); 5238 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5239 5240 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5241 r8168g_wait_ll_share_fifo_ready(tp); 5242 5243 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5244 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5245 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5246 r8168g_wait_ll_share_fifo_ready(tp); 5247 } 5248 5249 static void rtl_hw_initialize(struct rtl8169_private *tp) 5250 { 5251 switch (tp->mac_version) { 5252 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5253 rtl8168ep_stop_cmac(tp); 5254 fallthrough; 5255 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5256 rtl_hw_init_8168g(tp); 5257 break; 5258 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 5259 rtl_hw_init_8125(tp); 5260 break; 5261 default: 5262 break; 5263 } 5264 } 5265 5266 static int rtl_jumbo_max(struct rtl8169_private *tp) 5267 { 5268 /* Non-GBit versions don't support jumbo frames */ 5269 if (!tp->supports_gmii) 5270 return 0; 5271 5272 switch (tp->mac_version) { 5273 /* RTL8169 */ 5274 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5275 return JUMBO_7K; 5276 /* RTL8168b */ 5277 case RTL_GIGA_MAC_VER_11: 5278 case RTL_GIGA_MAC_VER_17: 5279 return JUMBO_4K; 5280 /* RTL8168c */ 5281 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5282 return JUMBO_6K; 5283 default: 5284 return JUMBO_9K; 5285 } 5286 } 5287 5288 static void rtl_init_mac_address(struct rtl8169_private *tp) 5289 { 5290 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5291 struct net_device *dev = tp->dev; 5292 int rc; 5293 5294 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5295 if (!rc) 5296 goto done; 5297 5298 rtl_read_mac_address(tp, mac_addr); 5299 if (is_valid_ether_addr(mac_addr)) 5300 goto done; 5301 5302 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5303 if (is_valid_ether_addr(mac_addr)) 5304 goto done; 5305 5306 eth_random_addr(mac_addr); 5307 dev->addr_assign_type = NET_ADDR_RANDOM; 5308 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5309 done: 5310 eth_hw_addr_set(dev, mac_addr); 5311 rtl_rar_set(tp, mac_addr); 5312 } 5313 5314 /* register is set if system vendor successfully tested ASPM 1.2 */ 5315 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5316 { 5317 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5318 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5319 return true; 5320 5321 return false; 5322 } 5323 5324 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5325 { 5326 struct rtl8169_private *tp; 5327 int jumbo_max, region, rc; 5328 enum mac_version chipset; 5329 struct net_device *dev; 5330 u32 txconfig; 5331 u16 xid; 5332 5333 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5334 if (!dev) 5335 return -ENOMEM; 5336 5337 SET_NETDEV_DEV(dev, &pdev->dev); 5338 dev->netdev_ops = &rtl_netdev_ops; 5339 tp = netdev_priv(dev); 5340 tp->dev = dev; 5341 tp->pci_dev = pdev; 5342 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5343 tp->ocp_base = OCP_STD_PHY_BASE; 5344 5345 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5346 raw_spin_lock_init(&tp->config25_lock); 5347 raw_spin_lock_init(&tp->mac_ocp_lock); 5348 mutex_init(&tp->led_lock); 5349 5350 /* Get the *optional* external "ether_clk" used on some boards */ 5351 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5352 if (IS_ERR(tp->clk)) 5353 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5354 5355 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5356 rc = pcim_enable_device(pdev); 5357 if (rc < 0) 5358 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5359 5360 if (pcim_set_mwi(pdev) < 0) 5361 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5362 5363 /* use first MMIO region */ 5364 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5365 if (region < 0) 5366 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5367 5368 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5369 if (rc < 0) 5370 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5371 5372 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5373 5374 txconfig = RTL_R32(tp, TxConfig); 5375 if (txconfig == ~0U) 5376 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5377 5378 xid = (txconfig >> 20) & 0xfcf; 5379 5380 /* Identify chip attached to board */ 5381 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5382 if (chipset == RTL_GIGA_MAC_NONE) 5383 return dev_err_probe(&pdev->dev, -ENODEV, 5384 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5385 xid); 5386 tp->mac_version = chipset; 5387 5388 /* Disable ASPM L1 as that cause random device stop working 5389 * problems as well as full system hangs for some PCIe devices users. 5390 */ 5391 if (rtl_aspm_is_safe(tp)) 5392 rc = 0; 5393 else 5394 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5395 tp->aspm_manageable = !rc; 5396 5397 tp->dash_type = rtl_get_dash_type(tp); 5398 tp->dash_enabled = rtl_dash_is_enabled(tp); 5399 5400 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5401 5402 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5403 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5404 dev->features |= NETIF_F_HIGHDMA; 5405 5406 rtl_init_rxcfg(tp); 5407 5408 rtl8169_irq_mask_and_ack(tp); 5409 5410 rtl_hw_initialize(tp); 5411 5412 rtl_hw_reset(tp); 5413 5414 rc = rtl_alloc_irq(tp); 5415 if (rc < 0) 5416 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5417 5418 tp->irq = pci_irq_vector(pdev, 0); 5419 5420 INIT_WORK(&tp->wk.work, rtl_task); 5421 5422 rtl_init_mac_address(tp); 5423 5424 dev->ethtool_ops = &rtl8169_ethtool_ops; 5425 5426 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5427 5428 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5429 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5430 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5431 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5432 5433 /* 5434 * Pretend we are using VLANs; This bypasses a nasty bug where 5435 * Interrupts stop flowing on high load on 8110SCd controllers. 5436 */ 5437 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5438 /* Disallow toggling */ 5439 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5440 5441 if (rtl_chip_supports_csum_v2(tp)) 5442 dev->hw_features |= NETIF_F_IPV6_CSUM; 5443 5444 dev->features |= dev->hw_features; 5445 5446 /* There has been a number of reports that using SG/TSO results in 5447 * tx timeouts. However for a lot of people SG/TSO works fine. 5448 * Therefore disable both features by default, but allow users to 5449 * enable them. Use at own risk! 5450 */ 5451 if (rtl_chip_supports_csum_v2(tp)) { 5452 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5453 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5454 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5455 } else { 5456 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5457 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5458 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5459 } 5460 5461 dev->hw_features |= NETIF_F_RXALL; 5462 dev->hw_features |= NETIF_F_RXFCS; 5463 5464 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5465 5466 netdev_sw_irq_coalesce_default_on(dev); 5467 5468 /* configure chip for default features */ 5469 rtl8169_set_features(dev, dev->features); 5470 5471 if (!tp->dash_enabled) { 5472 rtl_set_d3_pll_down(tp, true); 5473 } else { 5474 rtl_set_d3_pll_down(tp, false); 5475 dev->wol_enabled = 1; 5476 } 5477 5478 jumbo_max = rtl_jumbo_max(tp); 5479 if (jumbo_max) 5480 dev->max_mtu = jumbo_max; 5481 5482 rtl_set_irq_mask(tp); 5483 5484 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5485 5486 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5487 &tp->counters_phys_addr, 5488 GFP_KERNEL); 5489 if (!tp->counters) 5490 return -ENOMEM; 5491 5492 pci_set_drvdata(pdev, tp); 5493 5494 rc = r8169_mdio_register(tp); 5495 if (rc) 5496 return rc; 5497 5498 rc = register_netdev(dev); 5499 if (rc) 5500 return rc; 5501 5502 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5503 if (rtl_is_8125(tp)) 5504 rtl8125_init_leds(dev); 5505 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5506 rtl8168_init_leds(dev); 5507 } 5508 5509 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5510 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5511 5512 if (jumbo_max) 5513 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5514 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5515 "ok" : "ko"); 5516 5517 if (tp->dash_type != RTL_DASH_NONE) { 5518 netdev_info(dev, "DASH %s\n", 5519 tp->dash_enabled ? "enabled" : "disabled"); 5520 rtl8168_driver_start(tp); 5521 } 5522 5523 if (pci_dev_run_wake(pdev)) 5524 pm_runtime_put_sync(&pdev->dev); 5525 5526 return 0; 5527 } 5528 5529 static struct pci_driver rtl8169_pci_driver = { 5530 .name = KBUILD_MODNAME, 5531 .id_table = rtl8169_pci_tbl, 5532 .probe = rtl_init_one, 5533 .remove = rtl_remove_one, 5534 .shutdown = rtl_shutdown, 5535 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5536 }; 5537 5538 module_pci_driver(rtl8169_pci_driver); 5539