1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/hwmon.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/in.h> 23 #include <linux/io.h> 24 #include <linux/ip.h> 25 #include <linux/tcp.h> 26 #include <linux/interrupt.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/bitfield.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <linux/unaligned.h> 33 #include <net/ip6_checksum.h> 34 #include <net/netdev_queues.h> 35 36 #include "r8169.h" 37 #include "r8169_firmware.h" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 59 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 60 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 61 62 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 63 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 64 65 #define R8169_REGS_SIZE 256 66 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 67 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 68 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 69 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 70 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 71 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 72 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 73 74 #define OCP_STD_PHY_BASE 0xa400 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 91 static const struct { 92 const char *name; 93 const char *fw_name; 94 } rtl_chip_infos[] = { 95 /* PCI devices. */ 96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 101 /* PCI-E devices. */ 102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 108 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 110 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 115 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 117 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 118 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 119 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 120 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 122 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 123 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 124 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 125 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 126 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 127 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 128 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 129 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 130 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 131 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 132 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 133 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 134 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 135 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 136 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 137 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 138 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 139 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 140 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 141 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 142 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 143 [RTL_GIGA_MAC_VER_66] = {"RTL8126A", FIRMWARE_8126A_3}, 144 }; 145 146 static const struct pci_device_id rtl8169_pci_tbl[] = { 147 { PCI_VDEVICE(REALTEK, 0x2502) }, 148 { PCI_VDEVICE(REALTEK, 0x2600) }, 149 { PCI_VDEVICE(REALTEK, 0x8129) }, 150 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 151 { PCI_VDEVICE(REALTEK, 0x8161) }, 152 { PCI_VDEVICE(REALTEK, 0x8162) }, 153 { PCI_VDEVICE(REALTEK, 0x8167) }, 154 { PCI_VDEVICE(REALTEK, 0x8168) }, 155 { PCI_VDEVICE(NCUBE, 0x8168) }, 156 { PCI_VDEVICE(REALTEK, 0x8169) }, 157 { PCI_VENDOR_ID_DLINK, 0x4300, 158 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 159 { PCI_VDEVICE(DLINK, 0x4300) }, 160 { PCI_VDEVICE(DLINK, 0x4302) }, 161 { PCI_VDEVICE(AT, 0xc107) }, 162 { PCI_VDEVICE(USR, 0x0116) }, 163 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 164 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 165 { PCI_VDEVICE(REALTEK, 0x8125) }, 166 { PCI_VDEVICE(REALTEK, 0x8126) }, 167 { PCI_VDEVICE(REALTEK, 0x3000) }, 168 {} 169 }; 170 171 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 172 173 enum rtl_registers { 174 MAC0 = 0, /* Ethernet hardware address. */ 175 MAC4 = 4, 176 MAR0 = 8, /* Multicast filter. */ 177 CounterAddrLow = 0x10, 178 CounterAddrHigh = 0x14, 179 TxDescStartAddrLow = 0x20, 180 TxDescStartAddrHigh = 0x24, 181 TxHDescStartAddrLow = 0x28, 182 TxHDescStartAddrHigh = 0x2c, 183 FLASH = 0x30, 184 ERSR = 0x36, 185 ChipCmd = 0x37, 186 TxPoll = 0x38, 187 IntrMask = 0x3c, 188 IntrStatus = 0x3e, 189 190 TxConfig = 0x40, 191 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 192 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 193 194 RxConfig = 0x44, 195 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 196 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 197 #define RXCFG_FIFO_SHIFT 13 198 /* No threshold before first PCI xfer */ 199 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 200 #define RX_EARLY_OFF (1 << 11) 201 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 202 #define RXCFG_DMA_SHIFT 8 203 /* Unlimited maximum PCI burst. */ 204 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 205 206 Cfg9346 = 0x50, 207 Config0 = 0x51, 208 Config1 = 0x52, 209 Config2 = 0x53, 210 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 211 212 Config3 = 0x54, 213 Config4 = 0x55, 214 Config5 = 0x56, 215 PHYAR = 0x60, 216 PHYstatus = 0x6c, 217 RxMaxSize = 0xda, 218 CPlusCmd = 0xe0, 219 IntrMitigate = 0xe2, 220 221 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 222 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 223 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 224 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 225 226 #define RTL_COALESCE_T_MAX 0x0fU 227 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 228 229 RxDescAddrLow = 0xe4, 230 RxDescAddrHigh = 0xe8, 231 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 232 233 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 234 235 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 236 237 #define TxPacketMax (8064 >> 7) 238 #define EarlySize 0x27 239 240 FuncEvent = 0xf0, 241 FuncEventMask = 0xf4, 242 FuncPresetState = 0xf8, 243 IBCR0 = 0xf8, 244 IBCR2 = 0xf9, 245 IBIMR0 = 0xfa, 246 IBISR0 = 0xfb, 247 FuncForceEvent = 0xfc, 248 }; 249 250 enum rtl8168_8101_registers { 251 CSIDR = 0x64, 252 CSIAR = 0x68, 253 #define CSIAR_FLAG 0x80000000 254 #define CSIAR_WRITE_CMD 0x80000000 255 #define CSIAR_BYTE_ENABLE 0x0000f000 256 #define CSIAR_ADDR_MASK 0x00000fff 257 PMCH = 0x6f, 258 #define D3COLD_NO_PLL_DOWN BIT(7) 259 #define D3HOT_NO_PLL_DOWN BIT(6) 260 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 261 EPHYAR = 0x80, 262 #define EPHYAR_FLAG 0x80000000 263 #define EPHYAR_WRITE_CMD 0x80000000 264 #define EPHYAR_REG_MASK 0x1f 265 #define EPHYAR_REG_SHIFT 16 266 #define EPHYAR_DATA_MASK 0xffff 267 DLLPR = 0xd0, 268 #define PFM_EN (1 << 6) 269 #define TX_10M_PS_EN (1 << 7) 270 DBG_REG = 0xd1, 271 #define FIX_NAK_1 (1 << 4) 272 #define FIX_NAK_2 (1 << 3) 273 TWSI = 0xd2, 274 MCU = 0xd3, 275 #define NOW_IS_OOB (1 << 7) 276 #define TX_EMPTY (1 << 5) 277 #define RX_EMPTY (1 << 4) 278 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 279 #define EN_NDP (1 << 3) 280 #define EN_OOB_RESET (1 << 2) 281 #define LINK_LIST_RDY (1 << 1) 282 EFUSEAR = 0xdc, 283 #define EFUSEAR_FLAG 0x80000000 284 #define EFUSEAR_WRITE_CMD 0x80000000 285 #define EFUSEAR_READ_CMD 0x00000000 286 #define EFUSEAR_REG_MASK 0x03ff 287 #define EFUSEAR_REG_SHIFT 8 288 #define EFUSEAR_DATA_MASK 0xff 289 MISC_1 = 0xf2, 290 #define PFM_D3COLD_EN (1 << 6) 291 }; 292 293 enum rtl8168_registers { 294 LED_CTRL = 0x18, 295 LED_FREQ = 0x1a, 296 EEE_LED = 0x1b, 297 ERIDR = 0x70, 298 ERIAR = 0x74, 299 #define ERIAR_FLAG 0x80000000 300 #define ERIAR_WRITE_CMD 0x80000000 301 #define ERIAR_READ_CMD 0x00000000 302 #define ERIAR_ADDR_BYTE_ALIGN 4 303 #define ERIAR_TYPE_SHIFT 16 304 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 306 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_MASK_SHIFT 12 309 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 311 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 314 EPHY_RXER_NUM = 0x7c, 315 OCPDR = 0xb0, /* OCP GPHY access */ 316 #define OCPDR_WRITE_CMD 0x80000000 317 #define OCPDR_READ_CMD 0x00000000 318 #define OCPDR_REG_MASK 0x7f 319 #define OCPDR_GPHY_REG_SHIFT 16 320 #define OCPDR_DATA_MASK 0xffff 321 OCPAR = 0xb4, 322 #define OCPAR_FLAG 0x80000000 323 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 324 #define OCPAR_GPHY_READ_CMD 0x0000f060 325 GPHY_OCP = 0xb8, 326 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 327 MISC = 0xf0, /* 8168e only. */ 328 #define TXPLA_RST (1 << 29) 329 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 330 #define PWM_EN (1 << 22) 331 #define RXDV_GATED_EN (1 << 19) 332 #define EARLY_TALLY_EN (1 << 16) 333 }; 334 335 enum rtl8125_registers { 336 LEDSEL0 = 0x18, 337 INT_CFG0_8125 = 0x34, 338 #define INT_CFG0_ENABLE_8125 BIT(0) 339 #define INT_CFG0_CLKREQEN BIT(3) 340 IntrMask_8125 = 0x38, 341 IntrStatus_8125 = 0x3c, 342 INT_CFG1_8125 = 0x7a, 343 LEDSEL2 = 0x84, 344 LEDSEL1 = 0x86, 345 TxPoll_8125 = 0x90, 346 LEDSEL3 = 0x96, 347 MAC0_BKP = 0x19e0, 348 EEE_TXIDLE_TIMER_8125 = 0x6048, 349 }; 350 351 #define LEDSEL_MASK_8125 0x23f 352 353 #define RX_VLAN_INNER_8125 BIT(22) 354 #define RX_VLAN_OUTER_8125 BIT(23) 355 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 356 357 #define RX_FETCH_DFLT_8125 (8 << 27) 358 359 enum rtl_register_content { 360 /* InterruptStatusBits */ 361 SYSErr = 0x8000, 362 PCSTimeout = 0x4000, 363 SWInt = 0x0100, 364 TxDescUnavail = 0x0080, 365 RxFIFOOver = 0x0040, 366 LinkChg = 0x0020, 367 RxOverflow = 0x0010, 368 TxErr = 0x0008, 369 TxOK = 0x0004, 370 RxErr = 0x0002, 371 RxOK = 0x0001, 372 373 /* RxStatusDesc */ 374 RxRWT = (1 << 22), 375 RxRES = (1 << 21), 376 RxRUNT = (1 << 20), 377 RxCRC = (1 << 19), 378 379 /* ChipCmdBits */ 380 StopReq = 0x80, 381 CmdReset = 0x10, 382 CmdRxEnb = 0x08, 383 CmdTxEnb = 0x04, 384 RxBufEmpty = 0x01, 385 386 /* TXPoll register p.5 */ 387 HPQ = 0x80, /* Poll cmd on the high prio queue */ 388 NPQ = 0x40, /* Poll cmd on the low prio queue */ 389 FSWInt = 0x01, /* Forced software interrupt */ 390 391 /* Cfg9346Bits */ 392 Cfg9346_Lock = 0x00, 393 Cfg9346_Unlock = 0xc0, 394 395 /* rx_mode_bits */ 396 AcceptErr = 0x20, 397 AcceptRunt = 0x10, 398 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 399 AcceptBroadcast = 0x08, 400 AcceptMulticast = 0x04, 401 AcceptMyPhys = 0x02, 402 AcceptAllPhys = 0x01, 403 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 404 #define RX_CONFIG_ACCEPT_MASK 0x3f 405 406 /* TxConfigBits */ 407 TxInterFrameGapShift = 24, 408 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 409 410 /* Config1 register p.24 */ 411 LEDS1 = (1 << 7), 412 LEDS0 = (1 << 6), 413 Speed_down = (1 << 4), 414 MEMMAP = (1 << 3), 415 IOMAP = (1 << 2), 416 VPD = (1 << 1), 417 PMEnable = (1 << 0), /* Power Management Enable */ 418 419 /* Config2 register p. 25 */ 420 ClkReqEn = (1 << 7), /* Clock Request Enable */ 421 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 422 PCI_Clock_66MHz = 0x01, 423 PCI_Clock_33MHz = 0x00, 424 425 /* Config3 register p.25 */ 426 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 427 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 428 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 429 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 430 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 431 432 /* Config4 register */ 433 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 434 435 /* Config5 register p.27 */ 436 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 437 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 438 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 439 Spi_en = (1 << 3), 440 LanWake = (1 << 1), /* LanWake enable/disable */ 441 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 442 ASPM_en = (1 << 0), /* ASPM enable */ 443 444 /* CPlusCmd p.31 */ 445 EnableBist = (1 << 15), // 8168 8101 446 Mac_dbgo_oe = (1 << 14), // 8168 8101 447 EnAnaPLL = (1 << 14), // 8169 448 Normal_mode = (1 << 13), // unused 449 Force_half_dup = (1 << 12), // 8168 8101 450 Force_rxflow_en = (1 << 11), // 8168 8101 451 Force_txflow_en = (1 << 10), // 8168 8101 452 Cxpl_dbg_sel = (1 << 9), // 8168 8101 453 ASF = (1 << 8), // 8168 8101 454 PktCntrDisable = (1 << 7), // 8168 8101 455 Mac_dbgo_sel = 0x001c, // 8168 456 RxVlan = (1 << 6), 457 RxChkSum = (1 << 5), 458 PCIDAC = (1 << 4), 459 PCIMulRW = (1 << 3), 460 #define INTT_MASK GENMASK(1, 0) 461 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 462 463 /* rtl8169_PHYstatus */ 464 TBI_Enable = 0x80, 465 TxFlowCtrl = 0x40, 466 RxFlowCtrl = 0x20, 467 _1000bpsF = 0x10, 468 _100bps = 0x08, 469 _10bps = 0x04, 470 LinkStatus = 0x02, 471 FullDup = 0x01, 472 473 /* ResetCounterCommand */ 474 CounterReset = 0x1, 475 476 /* DumpCounterCommand */ 477 CounterDump = 0x8, 478 479 /* magic enable v2 */ 480 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 481 }; 482 483 enum rtl_desc_bit { 484 /* First doubleword. */ 485 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 486 RingEnd = (1 << 30), /* End of descriptor ring */ 487 FirstFrag = (1 << 29), /* First segment of a packet */ 488 LastFrag = (1 << 28), /* Final segment of a packet */ 489 }; 490 491 /* Generic case. */ 492 enum rtl_tx_desc_bit { 493 /* First doubleword. */ 494 TD_LSO = (1 << 27), /* Large Send Offload */ 495 #define TD_MSS_MAX 0x07ffu /* MSS value */ 496 497 /* Second doubleword. */ 498 TxVlanTag = (1 << 17), /* Add VLAN tag */ 499 }; 500 501 /* 8169, 8168b and 810x except 8102e. */ 502 enum rtl_tx_desc_bit_0 { 503 /* First doubleword. */ 504 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 505 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 506 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 507 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 508 }; 509 510 /* 8102e, 8168c and beyond. */ 511 enum rtl_tx_desc_bit_1 { 512 /* First doubleword. */ 513 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 514 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 515 #define GTTCPHO_SHIFT 18 516 #define GTTCPHO_MAX 0x7f 517 518 /* Second doubleword. */ 519 #define TCPHO_SHIFT 18 520 #define TCPHO_MAX 0x3ff 521 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 522 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 523 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 524 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 525 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 526 }; 527 528 enum rtl_rx_desc_bit { 529 /* Rx private */ 530 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 531 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 532 533 #define RxProtoUDP (PID1) 534 #define RxProtoTCP (PID0) 535 #define RxProtoIP (PID1 | PID0) 536 #define RxProtoMask RxProtoIP 537 538 IPFail = (1 << 16), /* IP checksum failed */ 539 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 540 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 541 542 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 543 544 RxVlanTag = (1 << 16), /* VLAN tag available */ 545 }; 546 547 #define RTL_GSO_MAX_SIZE_V1 32000 548 #define RTL_GSO_MAX_SEGS_V1 24 549 #define RTL_GSO_MAX_SIZE_V2 64000 550 #define RTL_GSO_MAX_SEGS_V2 64 551 552 struct TxDesc { 553 __le32 opts1; 554 __le32 opts2; 555 __le64 addr; 556 }; 557 558 struct RxDesc { 559 __le32 opts1; 560 __le32 opts2; 561 __le64 addr; 562 }; 563 564 struct ring_info { 565 struct sk_buff *skb; 566 u32 len; 567 }; 568 569 struct rtl8169_counters { 570 __le64 tx_packets; 571 __le64 rx_packets; 572 __le64 tx_errors; 573 __le32 rx_errors; 574 __le16 rx_missed; 575 __le16 align_errors; 576 __le32 tx_one_collision; 577 __le32 tx_multi_collision; 578 __le64 rx_unicast; 579 __le64 rx_broadcast; 580 __le32 rx_multicast; 581 __le16 tx_aborted; 582 __le16 tx_underrun; 583 /* new since RTL8125 */ 584 __le64 tx_octets; 585 __le64 rx_octets; 586 __le64 rx_multicast64; 587 __le64 tx_unicast64; 588 __le64 tx_broadcast64; 589 __le64 tx_multicast64; 590 __le32 tx_pause_on; 591 __le32 tx_pause_off; 592 __le32 tx_pause_all; 593 __le32 tx_deferred; 594 __le32 tx_late_collision; 595 __le32 tx_all_collision; 596 __le32 tx_aborted32; 597 __le32 align_errors32; 598 __le32 rx_frame_too_long; 599 __le32 rx_runt; 600 __le32 rx_pause_on; 601 __le32 rx_pause_off; 602 __le32 rx_pause_all; 603 __le32 rx_unknown_opcode; 604 __le32 rx_mac_error; 605 __le32 tx_underrun32; 606 __le32 rx_mac_missed; 607 __le32 rx_tcam_dropped; 608 __le32 tdu; 609 __le32 rdu; 610 }; 611 612 struct rtl8169_tc_offsets { 613 bool inited; 614 __le64 tx_errors; 615 __le32 tx_multi_collision; 616 __le16 tx_aborted; 617 __le16 rx_missed; 618 }; 619 620 enum rtl_flag { 621 RTL_FLAG_TASK_ENABLED = 0, 622 RTL_FLAG_TASK_RESET_PENDING, 623 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 624 RTL_FLAG_TASK_TX_TIMEOUT, 625 RTL_FLAG_MAX 626 }; 627 628 enum rtl_dash_type { 629 RTL_DASH_NONE, 630 RTL_DASH_DP, 631 RTL_DASH_EP, 632 }; 633 634 struct rtl8169_private { 635 void __iomem *mmio_addr; /* memory map physical address */ 636 struct pci_dev *pci_dev; 637 struct net_device *dev; 638 struct phy_device *phydev; 639 struct napi_struct napi; 640 enum mac_version mac_version; 641 enum rtl_dash_type dash_type; 642 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 643 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 644 u32 dirty_tx; 645 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 646 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 647 dma_addr_t TxPhyAddr; 648 dma_addr_t RxPhyAddr; 649 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 650 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 651 u16 cp_cmd; 652 u16 tx_lpi_timer; 653 u32 irq_mask; 654 int irq; 655 struct clk *clk; 656 657 struct { 658 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 659 struct work_struct work; 660 } wk; 661 662 raw_spinlock_t config25_lock; 663 raw_spinlock_t mac_ocp_lock; 664 struct mutex led_lock; /* serialize LED ctrl RMW access */ 665 666 raw_spinlock_t cfg9346_usage_lock; 667 int cfg9346_usage_count; 668 669 unsigned supports_gmii:1; 670 unsigned aspm_manageable:1; 671 unsigned dash_enabled:1; 672 dma_addr_t counters_phys_addr; 673 struct rtl8169_counters *counters; 674 struct rtl8169_tc_offsets tc_offset; 675 u32 saved_wolopts; 676 677 const char *fw_name; 678 struct rtl_fw *rtl_fw; 679 680 struct r8169_led_classdev *leds; 681 682 u32 ocp_base; 683 }; 684 685 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 686 687 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 688 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 689 MODULE_SOFTDEP("pre: realtek"); 690 MODULE_LICENSE("GPL"); 691 MODULE_FIRMWARE(FIRMWARE_8168D_1); 692 MODULE_FIRMWARE(FIRMWARE_8168D_2); 693 MODULE_FIRMWARE(FIRMWARE_8168E_1); 694 MODULE_FIRMWARE(FIRMWARE_8168E_2); 695 MODULE_FIRMWARE(FIRMWARE_8168E_3); 696 MODULE_FIRMWARE(FIRMWARE_8105E_1); 697 MODULE_FIRMWARE(FIRMWARE_8168F_1); 698 MODULE_FIRMWARE(FIRMWARE_8168F_2); 699 MODULE_FIRMWARE(FIRMWARE_8402_1); 700 MODULE_FIRMWARE(FIRMWARE_8411_1); 701 MODULE_FIRMWARE(FIRMWARE_8411_2); 702 MODULE_FIRMWARE(FIRMWARE_8106E_1); 703 MODULE_FIRMWARE(FIRMWARE_8106E_2); 704 MODULE_FIRMWARE(FIRMWARE_8168G_2); 705 MODULE_FIRMWARE(FIRMWARE_8168G_3); 706 MODULE_FIRMWARE(FIRMWARE_8168H_2); 707 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 708 MODULE_FIRMWARE(FIRMWARE_8107E_2); 709 MODULE_FIRMWARE(FIRMWARE_8125A_3); 710 MODULE_FIRMWARE(FIRMWARE_8125B_2); 711 MODULE_FIRMWARE(FIRMWARE_8126A_2); 712 MODULE_FIRMWARE(FIRMWARE_8126A_3); 713 714 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 715 { 716 return &tp->pci_dev->dev; 717 } 718 719 static void rtl_lock_config_regs(struct rtl8169_private *tp) 720 { 721 unsigned long flags; 722 723 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 724 if (!--tp->cfg9346_usage_count) 725 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 726 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 727 } 728 729 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 730 { 731 unsigned long flags; 732 733 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 734 if (!tp->cfg9346_usage_count++) 735 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 736 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 737 } 738 739 static void rtl_pci_commit(struct rtl8169_private *tp) 740 { 741 /* Read an arbitrary register to commit a preceding PCI write */ 742 RTL_R8(tp, ChipCmd); 743 } 744 745 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 746 { 747 unsigned long flags; 748 u8 val; 749 750 raw_spin_lock_irqsave(&tp->config25_lock, flags); 751 val = RTL_R8(tp, Config2); 752 RTL_W8(tp, Config2, (val & ~clear) | set); 753 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 754 } 755 756 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 757 { 758 unsigned long flags; 759 u8 val; 760 761 raw_spin_lock_irqsave(&tp->config25_lock, flags); 762 val = RTL_R8(tp, Config5); 763 RTL_W8(tp, Config5, (val & ~clear) | set); 764 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 765 } 766 767 static bool rtl_is_8125(struct rtl8169_private *tp) 768 { 769 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 770 } 771 772 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 773 { 774 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 775 tp->mac_version != RTL_GIGA_MAC_VER_39 && 776 tp->mac_version <= RTL_GIGA_MAC_VER_53; 777 } 778 779 static bool rtl_supports_eee(struct rtl8169_private *tp) 780 { 781 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 782 tp->mac_version != RTL_GIGA_MAC_VER_37 && 783 tp->mac_version != RTL_GIGA_MAC_VER_39; 784 } 785 786 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 787 { 788 int i; 789 790 for (i = 0; i < ETH_ALEN; i++) 791 mac[i] = RTL_R8(tp, reg + i); 792 } 793 794 struct rtl_cond { 795 bool (*check)(struct rtl8169_private *); 796 const char *msg; 797 }; 798 799 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 800 unsigned long usecs, int n, bool high) 801 { 802 int i; 803 804 for (i = 0; i < n; i++) { 805 if (c->check(tp) == high) 806 return true; 807 fsleep(usecs); 808 } 809 810 if (net_ratelimit()) 811 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 812 c->msg, !high, n, usecs); 813 return false; 814 } 815 816 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 817 const struct rtl_cond *c, 818 unsigned long d, int n) 819 { 820 return rtl_loop_wait(tp, c, d, n, true); 821 } 822 823 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 824 const struct rtl_cond *c, 825 unsigned long d, int n) 826 { 827 return rtl_loop_wait(tp, c, d, n, false); 828 } 829 830 #define DECLARE_RTL_COND(name) \ 831 static bool name ## _check(struct rtl8169_private *); \ 832 \ 833 static const struct rtl_cond name = { \ 834 .check = name ## _check, \ 835 .msg = #name \ 836 }; \ 837 \ 838 static bool name ## _check(struct rtl8169_private *tp) 839 840 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 841 { 842 struct device *dev = tp_to_dev(tp); 843 int ret; 844 845 ret = pm_runtime_resume_and_get(dev); 846 if (ret < 0) 847 return ret; 848 849 mutex_lock(&tp->led_lock); 850 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 851 mutex_unlock(&tp->led_lock); 852 853 pm_runtime_put_sync(dev); 854 855 return 0; 856 } 857 858 int rtl8168_get_led_mode(struct rtl8169_private *tp) 859 { 860 struct device *dev = tp_to_dev(tp); 861 int ret; 862 863 ret = pm_runtime_resume_and_get(dev); 864 if (ret < 0) 865 return ret; 866 867 ret = RTL_R16(tp, LED_CTRL); 868 869 pm_runtime_put_sync(dev); 870 871 return ret; 872 } 873 874 static int rtl8125_get_led_reg(int index) 875 { 876 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 877 878 return led_regs[index]; 879 } 880 881 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 882 { 883 int reg = rtl8125_get_led_reg(index); 884 struct device *dev = tp_to_dev(tp); 885 int ret; 886 u16 val; 887 888 ret = pm_runtime_resume_and_get(dev); 889 if (ret < 0) 890 return ret; 891 892 mutex_lock(&tp->led_lock); 893 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 894 RTL_W16(tp, reg, val | mode); 895 mutex_unlock(&tp->led_lock); 896 897 pm_runtime_put_sync(dev); 898 899 return 0; 900 } 901 902 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 903 { 904 int reg = rtl8125_get_led_reg(index); 905 struct device *dev = tp_to_dev(tp); 906 int ret; 907 908 ret = pm_runtime_resume_and_get(dev); 909 if (ret < 0) 910 return ret; 911 912 ret = RTL_R16(tp, reg); 913 914 pm_runtime_put_sync(dev); 915 916 return ret; 917 } 918 919 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 920 char *buf, int buf_len) 921 { 922 struct pci_dev *pdev = tp->pci_dev; 923 char pdom[8], pfun[8]; 924 int domain; 925 926 domain = pci_domain_nr(pdev->bus); 927 if (domain) 928 snprintf(pdom, sizeof(pdom), "P%d", domain); 929 else 930 pdom[0] = '\0'; 931 932 if (pdev->multifunction) 933 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 934 else 935 pfun[0] = '\0'; 936 937 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 938 PCI_SLOT(pdev->devfn), pfun, idx); 939 } 940 941 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 942 { 943 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 944 if (type == ERIAR_OOB && 945 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 946 tp->mac_version == RTL_GIGA_MAC_VER_53)) 947 *cmd |= 0xf70 << 18; 948 } 949 950 DECLARE_RTL_COND(rtl_eriar_cond) 951 { 952 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 953 } 954 955 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 956 u32 val, int type) 957 { 958 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 959 960 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 961 return; 962 963 RTL_W32(tp, ERIDR, val); 964 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 965 RTL_W32(tp, ERIAR, cmd); 966 967 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 968 } 969 970 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 971 u32 val) 972 { 973 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 974 } 975 976 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 977 { 978 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 979 980 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 981 RTL_W32(tp, ERIAR, cmd); 982 983 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 984 RTL_R32(tp, ERIDR) : ~0; 985 } 986 987 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 988 { 989 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 990 } 991 992 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 993 { 994 u32 val = rtl_eri_read(tp, addr); 995 996 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 997 } 998 999 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1000 { 1001 rtl_w0w1_eri(tp, addr, p, 0); 1002 } 1003 1004 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1005 { 1006 rtl_w0w1_eri(tp, addr, 0, m); 1007 } 1008 1009 static bool rtl_ocp_reg_failure(u32 reg) 1010 { 1011 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1012 } 1013 1014 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1015 { 1016 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1017 } 1018 1019 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1020 { 1021 if (rtl_ocp_reg_failure(reg)) 1022 return; 1023 1024 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1025 1026 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1027 } 1028 1029 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1030 { 1031 if (rtl_ocp_reg_failure(reg)) 1032 return 0; 1033 1034 RTL_W32(tp, GPHY_OCP, reg << 15); 1035 1036 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1037 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1038 } 1039 1040 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1041 { 1042 if (rtl_ocp_reg_failure(reg)) 1043 return; 1044 1045 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1046 } 1047 1048 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1049 { 1050 unsigned long flags; 1051 1052 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1053 __r8168_mac_ocp_write(tp, reg, data); 1054 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1055 } 1056 1057 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1058 { 1059 if (rtl_ocp_reg_failure(reg)) 1060 return 0; 1061 1062 RTL_W32(tp, OCPDR, reg << 15); 1063 1064 return RTL_R32(tp, OCPDR); 1065 } 1066 1067 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1068 { 1069 unsigned long flags; 1070 u16 val; 1071 1072 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1073 val = __r8168_mac_ocp_read(tp, reg); 1074 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1075 1076 return val; 1077 } 1078 1079 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1080 u16 set) 1081 { 1082 unsigned long flags; 1083 u16 data; 1084 1085 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1086 data = __r8168_mac_ocp_read(tp, reg); 1087 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1088 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1089 } 1090 1091 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1092 * PHY MCU interrupts before PHY power-down. 1093 */ 1094 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1095 { 1096 switch (tp->mac_version) { 1097 case RTL_GIGA_MAC_VER_40: 1098 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1099 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1100 else 1101 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1102 break; 1103 default: 1104 break; 1105 } 1106 }; 1107 1108 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1109 { 1110 if (reg == 0x1f) { 1111 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1112 return; 1113 } 1114 1115 if (tp->ocp_base != OCP_STD_PHY_BASE) 1116 reg -= 0x10; 1117 1118 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1119 rtl8168g_phy_suspend_quirk(tp, value); 1120 1121 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1122 } 1123 1124 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1125 { 1126 if (reg == 0x1f) 1127 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1128 1129 if (tp->ocp_base != OCP_STD_PHY_BASE) 1130 reg -= 0x10; 1131 1132 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1133 } 1134 1135 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1136 { 1137 if (reg == 0x1f) { 1138 tp->ocp_base = value << 4; 1139 return; 1140 } 1141 1142 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1143 } 1144 1145 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1146 { 1147 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1148 } 1149 1150 DECLARE_RTL_COND(rtl_phyar_cond) 1151 { 1152 return RTL_R32(tp, PHYAR) & 0x80000000; 1153 } 1154 1155 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1156 { 1157 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1158 1159 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1160 /* 1161 * According to hardware specs a 20us delay is required after write 1162 * complete indication, but before sending next command. 1163 */ 1164 udelay(20); 1165 } 1166 1167 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1168 { 1169 int value; 1170 1171 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1172 1173 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1174 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1175 1176 /* 1177 * According to hardware specs a 20us delay is required after read 1178 * complete indication, but before sending next command. 1179 */ 1180 udelay(20); 1181 1182 return value; 1183 } 1184 1185 DECLARE_RTL_COND(rtl_ocpar_cond) 1186 { 1187 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1188 } 1189 1190 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1191 1192 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1193 { 1194 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1195 } 1196 1197 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1198 { 1199 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1200 } 1201 1202 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1203 { 1204 r8168dp_2_mdio_start(tp); 1205 1206 r8169_mdio_write(tp, reg, value); 1207 1208 r8168dp_2_mdio_stop(tp); 1209 } 1210 1211 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1212 { 1213 int value; 1214 1215 /* Work around issue with chip reporting wrong PHY ID */ 1216 if (reg == MII_PHYSID2) 1217 return 0xc912; 1218 1219 r8168dp_2_mdio_start(tp); 1220 1221 value = r8169_mdio_read(tp, reg); 1222 1223 r8168dp_2_mdio_stop(tp); 1224 1225 return value; 1226 } 1227 1228 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1229 { 1230 switch (tp->mac_version) { 1231 case RTL_GIGA_MAC_VER_28: 1232 case RTL_GIGA_MAC_VER_31: 1233 r8168dp_2_mdio_write(tp, location, val); 1234 break; 1235 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1236 r8168g_mdio_write(tp, location, val); 1237 break; 1238 default: 1239 r8169_mdio_write(tp, location, val); 1240 break; 1241 } 1242 } 1243 1244 static int rtl_readphy(struct rtl8169_private *tp, int location) 1245 { 1246 switch (tp->mac_version) { 1247 case RTL_GIGA_MAC_VER_28: 1248 case RTL_GIGA_MAC_VER_31: 1249 return r8168dp_2_mdio_read(tp, location); 1250 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1251 return r8168g_mdio_read(tp, location); 1252 default: 1253 return r8169_mdio_read(tp, location); 1254 } 1255 } 1256 1257 DECLARE_RTL_COND(rtl_ephyar_cond) 1258 { 1259 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1260 } 1261 1262 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1263 { 1264 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1265 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1266 1267 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1268 1269 udelay(10); 1270 } 1271 1272 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1273 { 1274 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1275 1276 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1277 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1278 } 1279 1280 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1281 { 1282 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1283 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1284 RTL_R32(tp, OCPDR) : ~0; 1285 } 1286 1287 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1288 { 1289 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1290 } 1291 1292 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1293 u32 data) 1294 { 1295 RTL_W32(tp, OCPDR, data); 1296 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1297 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1298 } 1299 1300 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1301 u32 data) 1302 { 1303 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1304 data, ERIAR_OOB); 1305 } 1306 1307 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1308 { 1309 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1310 1311 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1312 } 1313 1314 #define OOB_CMD_RESET 0x00 1315 #define OOB_CMD_DRIVER_START 0x05 1316 #define OOB_CMD_DRIVER_STOP 0x06 1317 1318 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1319 { 1320 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1321 } 1322 1323 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1324 { 1325 u16 reg; 1326 1327 reg = rtl8168_get_ocp_reg(tp); 1328 1329 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1330 } 1331 1332 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1333 { 1334 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1335 } 1336 1337 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1338 { 1339 return RTL_R8(tp, IBISR0) & 0x20; 1340 } 1341 1342 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1343 { 1344 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1345 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1346 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1347 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1348 } 1349 1350 static void rtl_dash_loop_wait(struct rtl8169_private *tp, 1351 const struct rtl_cond *c, 1352 unsigned long usecs, int n, bool high) 1353 { 1354 if (!tp->dash_enabled) 1355 return; 1356 rtl_loop_wait(tp, c, usecs, n, high); 1357 } 1358 1359 static void rtl_dash_loop_wait_high(struct rtl8169_private *tp, 1360 const struct rtl_cond *c, 1361 unsigned long d, int n) 1362 { 1363 rtl_dash_loop_wait(tp, c, d, n, true); 1364 } 1365 1366 static void rtl_dash_loop_wait_low(struct rtl8169_private *tp, 1367 const struct rtl_cond *c, 1368 unsigned long d, int n) 1369 { 1370 rtl_dash_loop_wait(tp, c, d, n, false); 1371 } 1372 1373 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1374 { 1375 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1376 rtl_dash_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1377 } 1378 1379 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1380 { 1381 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1382 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1383 rtl_dash_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1384 } 1385 1386 static void rtl8168_driver_start(struct rtl8169_private *tp) 1387 { 1388 if (tp->dash_type == RTL_DASH_DP) 1389 rtl8168dp_driver_start(tp); 1390 else 1391 rtl8168ep_driver_start(tp); 1392 } 1393 1394 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1395 { 1396 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1397 rtl_dash_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1398 } 1399 1400 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1401 { 1402 rtl8168ep_stop_cmac(tp); 1403 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1404 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1405 rtl_dash_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1406 } 1407 1408 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1409 { 1410 if (tp->dash_type == RTL_DASH_DP) 1411 rtl8168dp_driver_stop(tp); 1412 else 1413 rtl8168ep_driver_stop(tp); 1414 } 1415 1416 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1417 { 1418 u16 reg = rtl8168_get_ocp_reg(tp); 1419 1420 return r8168dp_ocp_read(tp, reg) & BIT(15); 1421 } 1422 1423 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1424 { 1425 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1426 } 1427 1428 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1429 { 1430 switch (tp->dash_type) { 1431 case RTL_DASH_DP: 1432 return r8168dp_check_dash(tp); 1433 case RTL_DASH_EP: 1434 return r8168ep_check_dash(tp); 1435 default: 1436 return false; 1437 } 1438 } 1439 1440 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1441 { 1442 switch (tp->mac_version) { 1443 case RTL_GIGA_MAC_VER_28: 1444 case RTL_GIGA_MAC_VER_31: 1445 return RTL_DASH_DP; 1446 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1447 return RTL_DASH_EP; 1448 default: 1449 return RTL_DASH_NONE; 1450 } 1451 } 1452 1453 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1454 { 1455 switch (tp->mac_version) { 1456 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1457 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1458 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1459 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1460 if (enable) 1461 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1462 else 1463 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1464 break; 1465 default: 1466 break; 1467 } 1468 } 1469 1470 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1471 { 1472 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1473 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1474 } 1475 1476 DECLARE_RTL_COND(rtl_efusear_cond) 1477 { 1478 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1479 } 1480 1481 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1482 { 1483 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1484 1485 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1486 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1487 } 1488 1489 static u32 rtl_get_events(struct rtl8169_private *tp) 1490 { 1491 if (rtl_is_8125(tp)) 1492 return RTL_R32(tp, IntrStatus_8125); 1493 else 1494 return RTL_R16(tp, IntrStatus); 1495 } 1496 1497 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1498 { 1499 if (rtl_is_8125(tp)) 1500 RTL_W32(tp, IntrStatus_8125, bits); 1501 else 1502 RTL_W16(tp, IntrStatus, bits); 1503 } 1504 1505 static void rtl_irq_disable(struct rtl8169_private *tp) 1506 { 1507 if (rtl_is_8125(tp)) 1508 RTL_W32(tp, IntrMask_8125, 0); 1509 else 1510 RTL_W16(tp, IntrMask, 0); 1511 } 1512 1513 static void rtl_irq_enable(struct rtl8169_private *tp) 1514 { 1515 if (rtl_is_8125(tp)) 1516 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1517 else 1518 RTL_W16(tp, IntrMask, tp->irq_mask); 1519 } 1520 1521 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1522 { 1523 rtl_irq_disable(tp); 1524 rtl_ack_events(tp, 0xffffffff); 1525 rtl_pci_commit(tp); 1526 } 1527 1528 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1529 { 1530 struct phy_device *phydev = tp->phydev; 1531 1532 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1533 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1534 if (phydev->speed == SPEED_1000) { 1535 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1536 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1537 } else if (phydev->speed == SPEED_100) { 1538 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1539 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1540 } else { 1541 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1542 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1543 } 1544 rtl_reset_packet_filter(tp); 1545 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1546 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1547 if (phydev->speed == SPEED_1000) { 1548 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1549 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1550 } else { 1551 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1552 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1553 } 1554 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1555 if (phydev->speed == SPEED_10) { 1556 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1557 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1558 } else { 1559 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1560 } 1561 } 1562 } 1563 1564 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1565 1566 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1567 { 1568 struct rtl8169_private *tp = netdev_priv(dev); 1569 1570 wol->supported = WAKE_ANY; 1571 wol->wolopts = tp->saved_wolopts; 1572 } 1573 1574 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1575 { 1576 static const struct { 1577 u32 opt; 1578 u16 reg; 1579 u8 mask; 1580 } cfg[] = { 1581 { WAKE_PHY, Config3, LinkUp }, 1582 { WAKE_UCAST, Config5, UWF }, 1583 { WAKE_BCAST, Config5, BWF }, 1584 { WAKE_MCAST, Config5, MWF }, 1585 { WAKE_ANY, Config5, LanWake }, 1586 { WAKE_MAGIC, Config3, MagicPacket } 1587 }; 1588 unsigned int i, tmp = ARRAY_SIZE(cfg); 1589 unsigned long flags; 1590 u8 options; 1591 1592 rtl_unlock_config_regs(tp); 1593 1594 if (rtl_is_8168evl_up(tp)) { 1595 tmp--; 1596 if (wolopts & WAKE_MAGIC) 1597 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1598 else 1599 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1600 } else if (rtl_is_8125(tp)) { 1601 tmp--; 1602 if (wolopts & WAKE_MAGIC) 1603 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1604 else 1605 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1606 } 1607 1608 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1609 for (i = 0; i < tmp; i++) { 1610 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1611 if (wolopts & cfg[i].opt) 1612 options |= cfg[i].mask; 1613 RTL_W8(tp, cfg[i].reg, options); 1614 } 1615 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1616 1617 switch (tp->mac_version) { 1618 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1619 options = RTL_R8(tp, Config1) & ~PMEnable; 1620 if (wolopts) 1621 options |= PMEnable; 1622 RTL_W8(tp, Config1, options); 1623 break; 1624 case RTL_GIGA_MAC_VER_34: 1625 case RTL_GIGA_MAC_VER_37: 1626 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1627 if (wolopts) 1628 rtl_mod_config2(tp, 0, PME_SIGNAL); 1629 else 1630 rtl_mod_config2(tp, PME_SIGNAL, 0); 1631 break; 1632 default: 1633 break; 1634 } 1635 1636 rtl_lock_config_regs(tp); 1637 1638 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1639 1640 if (!tp->dash_enabled) { 1641 rtl_set_d3_pll_down(tp, !wolopts); 1642 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1643 } 1644 } 1645 1646 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1647 { 1648 struct rtl8169_private *tp = netdev_priv(dev); 1649 1650 if (wol->wolopts & ~WAKE_ANY) 1651 return -EINVAL; 1652 1653 tp->saved_wolopts = wol->wolopts; 1654 __rtl8169_set_wol(tp, tp->saved_wolopts); 1655 1656 return 0; 1657 } 1658 1659 static void rtl8169_get_drvinfo(struct net_device *dev, 1660 struct ethtool_drvinfo *info) 1661 { 1662 struct rtl8169_private *tp = netdev_priv(dev); 1663 struct rtl_fw *rtl_fw = tp->rtl_fw; 1664 1665 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1666 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1667 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1668 if (rtl_fw) 1669 strscpy(info->fw_version, rtl_fw->version, 1670 sizeof(info->fw_version)); 1671 } 1672 1673 static int rtl8169_get_regs_len(struct net_device *dev) 1674 { 1675 return R8169_REGS_SIZE; 1676 } 1677 1678 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1679 netdev_features_t features) 1680 { 1681 struct rtl8169_private *tp = netdev_priv(dev); 1682 1683 if (dev->mtu > TD_MSS_MAX) 1684 features &= ~NETIF_F_ALL_TSO; 1685 1686 if (dev->mtu > ETH_DATA_LEN && 1687 tp->mac_version > RTL_GIGA_MAC_VER_06) 1688 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1689 1690 return features; 1691 } 1692 1693 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1694 netdev_features_t features) 1695 { 1696 u32 rx_config = RTL_R32(tp, RxConfig); 1697 1698 if (features & NETIF_F_RXALL) 1699 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1700 else 1701 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1702 1703 if (rtl_is_8125(tp)) { 1704 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1705 rx_config |= RX_VLAN_8125; 1706 else 1707 rx_config &= ~RX_VLAN_8125; 1708 } 1709 1710 RTL_W32(tp, RxConfig, rx_config); 1711 } 1712 1713 static int rtl8169_set_features(struct net_device *dev, 1714 netdev_features_t features) 1715 { 1716 struct rtl8169_private *tp = netdev_priv(dev); 1717 1718 rtl_set_rx_config_features(tp, features); 1719 1720 if (features & NETIF_F_RXCSUM) 1721 tp->cp_cmd |= RxChkSum; 1722 else 1723 tp->cp_cmd &= ~RxChkSum; 1724 1725 if (!rtl_is_8125(tp)) { 1726 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1727 tp->cp_cmd |= RxVlan; 1728 else 1729 tp->cp_cmd &= ~RxVlan; 1730 } 1731 1732 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1733 rtl_pci_commit(tp); 1734 1735 return 0; 1736 } 1737 1738 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1739 { 1740 return (skb_vlan_tag_present(skb)) ? 1741 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1742 } 1743 1744 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1745 { 1746 u32 opts2 = le32_to_cpu(desc->opts2); 1747 1748 if (opts2 & RxVlanTag) 1749 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1750 } 1751 1752 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1753 void *p) 1754 { 1755 struct rtl8169_private *tp = netdev_priv(dev); 1756 u32 __iomem *data = tp->mmio_addr; 1757 u32 *dw = p; 1758 int i; 1759 1760 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1761 memcpy_fromio(dw++, data++, 4); 1762 } 1763 1764 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1765 "tx_packets", 1766 "rx_packets", 1767 "tx_errors", 1768 "rx_errors", 1769 "rx_missed", 1770 "align_errors", 1771 "tx_single_collisions", 1772 "tx_multi_collisions", 1773 "unicast", 1774 "broadcast", 1775 "multicast", 1776 "tx_aborted", 1777 "tx_underrun", 1778 }; 1779 1780 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1781 { 1782 switch (sset) { 1783 case ETH_SS_STATS: 1784 return ARRAY_SIZE(rtl8169_gstrings); 1785 default: 1786 return -EOPNOTSUPP; 1787 } 1788 } 1789 1790 DECLARE_RTL_COND(rtl_counters_cond) 1791 { 1792 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1793 } 1794 1795 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1796 { 1797 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1798 1799 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1800 rtl_pci_commit(tp); 1801 RTL_W32(tp, CounterAddrLow, cmd); 1802 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1803 1804 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1805 } 1806 1807 static void rtl8169_update_counters(struct rtl8169_private *tp) 1808 { 1809 u8 val = RTL_R8(tp, ChipCmd); 1810 1811 /* 1812 * Some chips are unable to dump tally counters when the receiver 1813 * is disabled. If 0xff chip may be in a PCI power-save state. 1814 */ 1815 if (val & CmdRxEnb && val != 0xff) 1816 rtl8169_do_counters(tp, CounterDump); 1817 } 1818 1819 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1820 { 1821 struct rtl8169_counters *counters = tp->counters; 1822 1823 /* 1824 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1825 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1826 * reset by a power cycle, while the counter values collected by the 1827 * driver are reset at every driver unload/load cycle. 1828 * 1829 * To make sure the HW values returned by @get_stats64 match the SW 1830 * values, we collect the initial values at first open(*) and use them 1831 * as offsets to normalize the values returned by @get_stats64. 1832 * 1833 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1834 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1835 * set at open time by rtl_hw_start. 1836 */ 1837 1838 if (tp->tc_offset.inited) 1839 return; 1840 1841 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1842 rtl8169_do_counters(tp, CounterReset); 1843 } else { 1844 rtl8169_update_counters(tp); 1845 tp->tc_offset.tx_errors = counters->tx_errors; 1846 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1847 tp->tc_offset.tx_aborted = counters->tx_aborted; 1848 tp->tc_offset.rx_missed = counters->rx_missed; 1849 } 1850 1851 tp->tc_offset.inited = true; 1852 } 1853 1854 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1855 struct ethtool_stats *stats, u64 *data) 1856 { 1857 struct rtl8169_private *tp = netdev_priv(dev); 1858 struct rtl8169_counters *counters; 1859 1860 counters = tp->counters; 1861 rtl8169_update_counters(tp); 1862 1863 data[0] = le64_to_cpu(counters->tx_packets); 1864 data[1] = le64_to_cpu(counters->rx_packets); 1865 data[2] = le64_to_cpu(counters->tx_errors); 1866 data[3] = le32_to_cpu(counters->rx_errors); 1867 data[4] = le16_to_cpu(counters->rx_missed); 1868 data[5] = le16_to_cpu(counters->align_errors); 1869 data[6] = le32_to_cpu(counters->tx_one_collision); 1870 data[7] = le32_to_cpu(counters->tx_multi_collision); 1871 data[8] = le64_to_cpu(counters->rx_unicast); 1872 data[9] = le64_to_cpu(counters->rx_broadcast); 1873 data[10] = le32_to_cpu(counters->rx_multicast); 1874 data[11] = le16_to_cpu(counters->tx_aborted); 1875 data[12] = le16_to_cpu(counters->tx_underrun); 1876 } 1877 1878 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1879 { 1880 switch(stringset) { 1881 case ETH_SS_STATS: 1882 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1883 break; 1884 } 1885 } 1886 1887 /* 1888 * Interrupt coalescing 1889 * 1890 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1891 * > 8169, 8168 and 810x line of chipsets 1892 * 1893 * 8169, 8168, and 8136(810x) serial chipsets support it. 1894 * 1895 * > 2 - the Tx timer unit at gigabit speed 1896 * 1897 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1898 * (0xe0) bit 1 and bit 0. 1899 * 1900 * For 8169 1901 * bit[1:0] \ speed 1000M 100M 10M 1902 * 0 0 320ns 2.56us 40.96us 1903 * 0 1 2.56us 20.48us 327.7us 1904 * 1 0 5.12us 40.96us 655.4us 1905 * 1 1 10.24us 81.92us 1.31ms 1906 * 1907 * For the other 1908 * bit[1:0] \ speed 1000M 100M 10M 1909 * 0 0 5us 2.56us 40.96us 1910 * 0 1 40us 20.48us 327.7us 1911 * 1 0 80us 40.96us 655.4us 1912 * 1 1 160us 81.92us 1.31ms 1913 */ 1914 1915 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1916 struct rtl_coalesce_info { 1917 u32 speed; 1918 u32 scale_nsecs[4]; 1919 }; 1920 1921 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1922 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1923 1924 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1925 { SPEED_1000, COALESCE_DELAY(320) }, 1926 { SPEED_100, COALESCE_DELAY(2560) }, 1927 { SPEED_10, COALESCE_DELAY(40960) }, 1928 { 0 }, 1929 }; 1930 1931 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1932 { SPEED_1000, COALESCE_DELAY(5000) }, 1933 { SPEED_100, COALESCE_DELAY(2560) }, 1934 { SPEED_10, COALESCE_DELAY(40960) }, 1935 { 0 }, 1936 }; 1937 #undef COALESCE_DELAY 1938 1939 /* get rx/tx scale vector corresponding to current speed */ 1940 static const struct rtl_coalesce_info * 1941 rtl_coalesce_info(struct rtl8169_private *tp) 1942 { 1943 const struct rtl_coalesce_info *ci; 1944 1945 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1946 ci = rtl_coalesce_info_8169; 1947 else 1948 ci = rtl_coalesce_info_8168_8136; 1949 1950 /* if speed is unknown assume highest one */ 1951 if (tp->phydev->speed == SPEED_UNKNOWN) 1952 return ci; 1953 1954 for (; ci->speed; ci++) { 1955 if (tp->phydev->speed == ci->speed) 1956 return ci; 1957 } 1958 1959 return ERR_PTR(-ELNRNG); 1960 } 1961 1962 static int rtl_get_coalesce(struct net_device *dev, 1963 struct ethtool_coalesce *ec, 1964 struct kernel_ethtool_coalesce *kernel_coal, 1965 struct netlink_ext_ack *extack) 1966 { 1967 struct rtl8169_private *tp = netdev_priv(dev); 1968 const struct rtl_coalesce_info *ci; 1969 u32 scale, c_us, c_fr; 1970 u16 intrmit; 1971 1972 if (rtl_is_8125(tp)) 1973 return -EOPNOTSUPP; 1974 1975 memset(ec, 0, sizeof(*ec)); 1976 1977 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1978 ci = rtl_coalesce_info(tp); 1979 if (IS_ERR(ci)) 1980 return PTR_ERR(ci); 1981 1982 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1983 1984 intrmit = RTL_R16(tp, IntrMitigate); 1985 1986 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1987 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1988 1989 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1990 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1991 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1992 1993 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1994 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1995 1996 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1997 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1998 1999 return 0; 2000 } 2001 2002 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 2003 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 2004 u16 *cp01) 2005 { 2006 const struct rtl_coalesce_info *ci; 2007 u16 i; 2008 2009 ci = rtl_coalesce_info(tp); 2010 if (IS_ERR(ci)) 2011 return PTR_ERR(ci); 2012 2013 for (i = 0; i < 4; i++) { 2014 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 2015 *cp01 = i; 2016 return ci->scale_nsecs[i]; 2017 } 2018 } 2019 2020 return -ERANGE; 2021 } 2022 2023 static int rtl_set_coalesce(struct net_device *dev, 2024 struct ethtool_coalesce *ec, 2025 struct kernel_ethtool_coalesce *kernel_coal, 2026 struct netlink_ext_ack *extack) 2027 { 2028 struct rtl8169_private *tp = netdev_priv(dev); 2029 u32 tx_fr = ec->tx_max_coalesced_frames; 2030 u32 rx_fr = ec->rx_max_coalesced_frames; 2031 u32 coal_usec_max, units; 2032 u16 w = 0, cp01 = 0; 2033 int scale; 2034 2035 if (rtl_is_8125(tp)) 2036 return -EOPNOTSUPP; 2037 2038 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 2039 return -ERANGE; 2040 2041 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 2042 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 2043 if (scale < 0) 2044 return scale; 2045 2046 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 2047 * not only when usecs=0 because of e.g. the following scenario: 2048 * 2049 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2050 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2051 * - then user does `ethtool -C eth0 rx-usecs 100` 2052 * 2053 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2054 * if we want to ignore rx_frames then it has to be set to 0. 2055 */ 2056 if (rx_fr == 1) 2057 rx_fr = 0; 2058 if (tx_fr == 1) 2059 tx_fr = 0; 2060 2061 /* HW requires time limit to be set if frame limit is set */ 2062 if ((tx_fr && !ec->tx_coalesce_usecs) || 2063 (rx_fr && !ec->rx_coalesce_usecs)) 2064 return -EINVAL; 2065 2066 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2067 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2068 2069 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2070 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2071 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2072 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2073 2074 RTL_W16(tp, IntrMitigate, w); 2075 2076 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2077 if (rtl_is_8168evl_up(tp)) { 2078 if (!rx_fr && !tx_fr) 2079 /* disable packet counter */ 2080 tp->cp_cmd |= PktCntrDisable; 2081 else 2082 tp->cp_cmd &= ~PktCntrDisable; 2083 } 2084 2085 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2086 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2087 rtl_pci_commit(tp); 2088 2089 return 0; 2090 } 2091 2092 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2093 { 2094 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2095 2096 switch (tp->mac_version) { 2097 case RTL_GIGA_MAC_VER_46: 2098 case RTL_GIGA_MAC_VER_48: 2099 tp->tx_lpi_timer = timer_val; 2100 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2101 break; 2102 case RTL_GIGA_MAC_VER_61: 2103 case RTL_GIGA_MAC_VER_63: 2104 case RTL_GIGA_MAC_VER_65: 2105 case RTL_GIGA_MAC_VER_66: 2106 tp->tx_lpi_timer = timer_val; 2107 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2108 break; 2109 default: 2110 break; 2111 } 2112 } 2113 2114 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2115 { 2116 unsigned int speed = tp->phydev->speed; 2117 unsigned int timer = tp->tx_lpi_timer; 2118 2119 if (!timer || speed == SPEED_UNKNOWN) 2120 return 0; 2121 2122 /* tx_lpi_timer value is in bytes */ 2123 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2124 } 2125 2126 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2127 { 2128 struct rtl8169_private *tp = netdev_priv(dev); 2129 int ret; 2130 2131 if (!rtl_supports_eee(tp)) 2132 return -EOPNOTSUPP; 2133 2134 ret = phy_ethtool_get_eee(tp->phydev, data); 2135 if (ret) 2136 return ret; 2137 2138 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2139 2140 return 0; 2141 } 2142 2143 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2144 { 2145 struct rtl8169_private *tp = netdev_priv(dev); 2146 2147 if (!rtl_supports_eee(tp)) 2148 return -EOPNOTSUPP; 2149 2150 return phy_ethtool_set_eee(tp->phydev, data); 2151 } 2152 2153 static void rtl8169_get_ringparam(struct net_device *dev, 2154 struct ethtool_ringparam *data, 2155 struct kernel_ethtool_ringparam *kernel_data, 2156 struct netlink_ext_ack *extack) 2157 { 2158 data->rx_max_pending = NUM_RX_DESC; 2159 data->rx_pending = NUM_RX_DESC; 2160 data->tx_max_pending = NUM_TX_DESC; 2161 data->tx_pending = NUM_TX_DESC; 2162 } 2163 2164 static void rtl8169_get_pauseparam(struct net_device *dev, 2165 struct ethtool_pauseparam *data) 2166 { 2167 struct rtl8169_private *tp = netdev_priv(dev); 2168 bool tx_pause, rx_pause; 2169 2170 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2171 2172 data->autoneg = tp->phydev->autoneg; 2173 data->tx_pause = tx_pause ? 1 : 0; 2174 data->rx_pause = rx_pause ? 1 : 0; 2175 } 2176 2177 static int rtl8169_set_pauseparam(struct net_device *dev, 2178 struct ethtool_pauseparam *data) 2179 { 2180 struct rtl8169_private *tp = netdev_priv(dev); 2181 2182 if (dev->mtu > ETH_DATA_LEN) 2183 return -EOPNOTSUPP; 2184 2185 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2186 2187 return 0; 2188 } 2189 2190 static const struct ethtool_ops rtl8169_ethtool_ops = { 2191 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2192 ETHTOOL_COALESCE_MAX_FRAMES, 2193 .get_drvinfo = rtl8169_get_drvinfo, 2194 .get_regs_len = rtl8169_get_regs_len, 2195 .get_link = ethtool_op_get_link, 2196 .get_coalesce = rtl_get_coalesce, 2197 .set_coalesce = rtl_set_coalesce, 2198 .get_regs = rtl8169_get_regs, 2199 .get_wol = rtl8169_get_wol, 2200 .set_wol = rtl8169_set_wol, 2201 .get_strings = rtl8169_get_strings, 2202 .get_sset_count = rtl8169_get_sset_count, 2203 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2204 .get_ts_info = ethtool_op_get_ts_info, 2205 .nway_reset = phy_ethtool_nway_reset, 2206 .get_eee = rtl8169_get_eee, 2207 .set_eee = rtl8169_set_eee, 2208 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2209 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2210 .get_ringparam = rtl8169_get_ringparam, 2211 .get_pauseparam = rtl8169_get_pauseparam, 2212 .set_pauseparam = rtl8169_set_pauseparam, 2213 }; 2214 2215 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2216 { 2217 /* 2218 * The driver currently handles the 8168Bf and the 8168Be identically 2219 * but they can be identified more specifically through the test below 2220 * if needed: 2221 * 2222 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2223 * 2224 * Same thing for the 8101Eb and the 8101Ec: 2225 * 2226 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2227 */ 2228 static const struct rtl_mac_info { 2229 u16 mask; 2230 u16 val; 2231 enum mac_version ver; 2232 } mac_info[] = { 2233 /* 8126A family. */ 2234 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 }, 2235 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2236 2237 /* 8125B family. */ 2238 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2239 2240 /* 8125A family. */ 2241 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2242 /* It seems only XID 609 made it to the mass market. 2243 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2244 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2245 */ 2246 2247 /* RTL8117 */ 2248 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2249 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2250 2251 /* 8168EP family. */ 2252 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2253 /* It seems this chip version never made it to 2254 * the wild. Let's disable detection. 2255 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2256 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2257 */ 2258 2259 /* 8168H family. */ 2260 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2261 /* It seems this chip version never made it to 2262 * the wild. Let's disable detection. 2263 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2264 */ 2265 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 2266 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, 2267 2268 /* 8168G family. */ 2269 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2270 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2271 /* It seems this chip version never made it to 2272 * the wild. Let's disable detection. 2273 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2274 */ 2275 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2276 2277 /* 8168F family. */ 2278 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2279 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2280 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2281 2282 /* 8168E family. */ 2283 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2284 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2285 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2286 2287 /* 8168D family. */ 2288 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2289 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2290 2291 /* 8168DP family. */ 2292 /* It seems this early RTL8168dp version never made it to 2293 * the wild. Support has been removed. 2294 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2295 */ 2296 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2297 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2298 2299 /* 8168C family. */ 2300 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2301 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2302 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2303 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2304 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2305 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2306 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2307 2308 /* 8168B family. */ 2309 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2310 /* This one is very old and rare, let's see if anybody complains. 2311 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2312 */ 2313 2314 /* 8101 family. */ 2315 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2316 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2317 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2318 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2319 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2320 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2321 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2322 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2323 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2324 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2325 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2326 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2327 2328 /* 8110 family. */ 2329 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2330 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2331 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2332 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2333 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2334 2335 /* Catch-all */ 2336 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2337 }; 2338 const struct rtl_mac_info *p = mac_info; 2339 enum mac_version ver; 2340 2341 while ((xid & p->mask) != p->val) 2342 p++; 2343 ver = p->ver; 2344 2345 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2346 if (ver == RTL_GIGA_MAC_VER_42) 2347 ver = RTL_GIGA_MAC_VER_43; 2348 else if (ver == RTL_GIGA_MAC_VER_46) 2349 ver = RTL_GIGA_MAC_VER_48; 2350 } 2351 2352 return ver; 2353 } 2354 2355 static void rtl_release_firmware(struct rtl8169_private *tp) 2356 { 2357 if (tp->rtl_fw) { 2358 rtl_fw_release_firmware(tp->rtl_fw); 2359 kfree(tp->rtl_fw); 2360 tp->rtl_fw = NULL; 2361 } 2362 } 2363 2364 void r8169_apply_firmware(struct rtl8169_private *tp) 2365 { 2366 int val; 2367 2368 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2369 if (tp->rtl_fw) { 2370 rtl_fw_write_firmware(tp, tp->rtl_fw); 2371 /* At least one firmware doesn't reset tp->ocp_base. */ 2372 tp->ocp_base = OCP_STD_PHY_BASE; 2373 2374 /* PHY soft reset may still be in progress */ 2375 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2376 !(val & BMCR_RESET), 2377 50000, 600000, true); 2378 } 2379 } 2380 2381 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2382 { 2383 /* Adjust EEE LED frequency */ 2384 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2385 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2386 2387 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2388 } 2389 2390 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2391 { 2392 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2393 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2394 } 2395 2396 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2397 { 2398 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2399 } 2400 2401 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2402 { 2403 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2404 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2405 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2406 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2407 } 2408 2409 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2410 { 2411 u16 data1, data2, ioffset; 2412 2413 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2414 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2415 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2416 2417 ioffset = (data2 >> 1) & 0x7ff8; 2418 ioffset |= data2 & 0x0007; 2419 if (data1 & BIT(7)) 2420 ioffset |= BIT(15); 2421 2422 return ioffset; 2423 } 2424 2425 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2426 { 2427 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 2428 return; 2429 2430 set_bit(flag, tp->wk.flags); 2431 schedule_work(&tp->wk.work); 2432 } 2433 2434 static void rtl8169_init_phy(struct rtl8169_private *tp) 2435 { 2436 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2437 2438 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2439 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2440 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2441 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2442 RTL_W8(tp, 0x82, 0x01); 2443 } 2444 2445 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2446 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2447 tp->pci_dev->subsystem_device == 0xe000) 2448 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2449 2450 /* We may have called phy_speed_down before */ 2451 phy_speed_up(tp->phydev); 2452 2453 genphy_soft_reset(tp->phydev); 2454 } 2455 2456 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2457 { 2458 rtl_unlock_config_regs(tp); 2459 2460 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2461 rtl_pci_commit(tp); 2462 2463 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2464 rtl_pci_commit(tp); 2465 2466 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2467 rtl_rar_exgmac_set(tp, addr); 2468 2469 rtl_lock_config_regs(tp); 2470 } 2471 2472 static int rtl_set_mac_address(struct net_device *dev, void *p) 2473 { 2474 struct rtl8169_private *tp = netdev_priv(dev); 2475 int ret; 2476 2477 ret = eth_mac_addr(dev, p); 2478 if (ret) 2479 return ret; 2480 2481 rtl_rar_set(tp, dev->dev_addr); 2482 2483 return 0; 2484 } 2485 2486 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2487 { 2488 switch (tp->mac_version) { 2489 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2490 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2491 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2492 break; 2493 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2494 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2495 case RTL_GIGA_MAC_VER_38: 2496 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2497 break; 2498 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2499 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2500 break; 2501 case RTL_GIGA_MAC_VER_61: 2502 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2503 break; 2504 case RTL_GIGA_MAC_VER_63: 2505 case RTL_GIGA_MAC_VER_65: 2506 case RTL_GIGA_MAC_VER_66: 2507 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2508 RX_PAUSE_SLOT_ON); 2509 break; 2510 default: 2511 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2512 break; 2513 } 2514 } 2515 2516 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2517 { 2518 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2519 } 2520 2521 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2522 { 2523 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2524 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2525 } 2526 2527 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2528 { 2529 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2530 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2531 } 2532 2533 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2534 { 2535 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2536 } 2537 2538 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2539 { 2540 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2541 } 2542 2543 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2544 { 2545 RTL_W8(tp, MaxTxPacketSize, 0x24); 2546 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2547 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2548 } 2549 2550 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2551 { 2552 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2553 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2554 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2555 } 2556 2557 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2558 { 2559 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2560 } 2561 2562 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2563 { 2564 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2565 } 2566 2567 static void rtl_jumbo_config(struct rtl8169_private *tp) 2568 { 2569 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2570 int readrq = 4096; 2571 2572 rtl_unlock_config_regs(tp); 2573 switch (tp->mac_version) { 2574 case RTL_GIGA_MAC_VER_17: 2575 if (jumbo) { 2576 readrq = 512; 2577 r8168b_1_hw_jumbo_enable(tp); 2578 } else { 2579 r8168b_1_hw_jumbo_disable(tp); 2580 } 2581 break; 2582 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2583 if (jumbo) { 2584 readrq = 512; 2585 r8168c_hw_jumbo_enable(tp); 2586 } else { 2587 r8168c_hw_jumbo_disable(tp); 2588 } 2589 break; 2590 case RTL_GIGA_MAC_VER_28: 2591 if (jumbo) 2592 r8168dp_hw_jumbo_enable(tp); 2593 else 2594 r8168dp_hw_jumbo_disable(tp); 2595 break; 2596 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2597 if (jumbo) 2598 r8168e_hw_jumbo_enable(tp); 2599 else 2600 r8168e_hw_jumbo_disable(tp); 2601 break; 2602 default: 2603 break; 2604 } 2605 rtl_lock_config_regs(tp); 2606 2607 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2608 pcie_set_readrq(tp->pci_dev, readrq); 2609 2610 /* Chip doesn't support pause in jumbo mode */ 2611 if (jumbo) { 2612 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2613 tp->phydev->advertising); 2614 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2615 tp->phydev->advertising); 2616 phy_start_aneg(tp->phydev); 2617 } 2618 } 2619 2620 DECLARE_RTL_COND(rtl_chipcmd_cond) 2621 { 2622 return RTL_R8(tp, ChipCmd) & CmdReset; 2623 } 2624 2625 static void rtl_hw_reset(struct rtl8169_private *tp) 2626 { 2627 RTL_W8(tp, ChipCmd, CmdReset); 2628 2629 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2630 } 2631 2632 static void rtl_request_firmware(struct rtl8169_private *tp) 2633 { 2634 struct rtl_fw *rtl_fw; 2635 2636 /* firmware loaded already or no firmware available */ 2637 if (tp->rtl_fw || !tp->fw_name) 2638 return; 2639 2640 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2641 if (!rtl_fw) 2642 return; 2643 2644 rtl_fw->phy_write = rtl_writephy; 2645 rtl_fw->phy_read = rtl_readphy; 2646 rtl_fw->mac_mcu_write = mac_mcu_write; 2647 rtl_fw->mac_mcu_read = mac_mcu_read; 2648 rtl_fw->fw_name = tp->fw_name; 2649 rtl_fw->dev = tp_to_dev(tp); 2650 2651 if (rtl_fw_request_firmware(rtl_fw)) 2652 kfree(rtl_fw); 2653 else 2654 tp->rtl_fw = rtl_fw; 2655 } 2656 2657 static void rtl_rx_close(struct rtl8169_private *tp) 2658 { 2659 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2660 } 2661 2662 DECLARE_RTL_COND(rtl_npq_cond) 2663 { 2664 return RTL_R8(tp, TxPoll) & NPQ; 2665 } 2666 2667 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2668 { 2669 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2670 } 2671 2672 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2673 { 2674 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2675 } 2676 2677 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2678 { 2679 /* IntrMitigate has new functionality on RTL8125 */ 2680 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2681 } 2682 2683 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2684 { 2685 switch (tp->mac_version) { 2686 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2687 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2688 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2689 break; 2690 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2691 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2692 break; 2693 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2694 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2695 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2696 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2697 break; 2698 default: 2699 break; 2700 } 2701 } 2702 2703 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2704 { 2705 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2706 } 2707 2708 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2709 { 2710 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2711 fsleep(2000); 2712 rtl_wait_txrx_fifo_empty(tp); 2713 } 2714 2715 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2716 { 2717 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2718 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2719 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2720 2721 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2722 rtl_disable_rxdvgate(tp); 2723 } 2724 2725 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2726 { 2727 if (tp->dash_enabled) 2728 return; 2729 2730 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2731 tp->mac_version == RTL_GIGA_MAC_VER_33) 2732 rtl_ephy_write(tp, 0x19, 0xff64); 2733 2734 if (device_may_wakeup(tp_to_dev(tp))) { 2735 phy_speed_down(tp->phydev, false); 2736 rtl_wol_enable_rx(tp); 2737 } 2738 } 2739 2740 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2741 { 2742 u32 val = TX_DMA_BURST << TxDMAShift | 2743 InterFrameGap << TxInterFrameGapShift; 2744 2745 if (rtl_is_8168evl_up(tp)) 2746 val |= TXCFG_AUTO_FIFO; 2747 2748 RTL_W32(tp, TxConfig, val); 2749 } 2750 2751 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2752 { 2753 /* Low hurts. Let's disable the filtering. */ 2754 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2755 } 2756 2757 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2758 { 2759 /* 2760 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2761 * register to be written before TxDescAddrLow to work. 2762 * Switching from MMIO to I/O access fixes the issue as well. 2763 */ 2764 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2765 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2766 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2767 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2768 } 2769 2770 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2771 { 2772 u32 val; 2773 2774 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2775 val = 0x000fff00; 2776 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2777 val = 0x00ffff00; 2778 else 2779 return; 2780 2781 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2782 val |= 0xff; 2783 2784 RTL_W32(tp, 0x7c, val); 2785 } 2786 2787 static void rtl_set_rx_mode(struct net_device *dev) 2788 { 2789 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2790 /* Multicast hash filter */ 2791 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2792 struct rtl8169_private *tp = netdev_priv(dev); 2793 u32 tmp; 2794 2795 if (dev->flags & IFF_PROMISC) { 2796 rx_mode |= AcceptAllPhys; 2797 } else if (!(dev->flags & IFF_MULTICAST)) { 2798 rx_mode &= ~AcceptMulticast; 2799 } else if (dev->flags & IFF_ALLMULTI || 2800 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2801 /* accept all multicasts */ 2802 } else if (netdev_mc_empty(dev)) { 2803 rx_mode &= ~AcceptMulticast; 2804 } else { 2805 struct netdev_hw_addr *ha; 2806 2807 mc_filter[1] = mc_filter[0] = 0; 2808 netdev_for_each_mc_addr(ha, dev) { 2809 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2810 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2811 } 2812 2813 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2814 tmp = mc_filter[0]; 2815 mc_filter[0] = swab32(mc_filter[1]); 2816 mc_filter[1] = swab32(tmp); 2817 } 2818 } 2819 2820 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2821 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2822 2823 tmp = RTL_R32(tp, RxConfig); 2824 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2825 } 2826 2827 DECLARE_RTL_COND(rtl_csiar_cond) 2828 { 2829 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2830 } 2831 2832 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2833 { 2834 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2835 2836 RTL_W32(tp, CSIDR, value); 2837 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2838 CSIAR_BYTE_ENABLE | func << 16); 2839 2840 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2841 } 2842 2843 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2844 { 2845 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2846 2847 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2848 CSIAR_BYTE_ENABLE); 2849 2850 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2851 RTL_R32(tp, CSIDR) : ~0; 2852 } 2853 2854 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2855 { 2856 struct pci_dev *pdev = tp->pci_dev; 2857 u32 csi; 2858 2859 /* According to Realtek the value at config space address 0x070f 2860 * controls the L0s/L1 entrance latency. We try standard ECAM access 2861 * first and if it fails fall back to CSI. 2862 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2863 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2864 */ 2865 if (pdev->cfg_size > 0x070f && 2866 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2867 return; 2868 2869 netdev_notice_once(tp->dev, 2870 "No native access to PCI extended config space, falling back to CSI\n"); 2871 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2872 rtl_csi_write(tp, 0x070c, csi | val << 24); 2873 } 2874 2875 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2876 { 2877 /* L0 7us, L1 16us */ 2878 rtl_set_aspm_entry_latency(tp, 0x27); 2879 } 2880 2881 struct ephy_info { 2882 unsigned int offset; 2883 u16 mask; 2884 u16 bits; 2885 }; 2886 2887 static void __rtl_ephy_init(struct rtl8169_private *tp, 2888 const struct ephy_info *e, int len) 2889 { 2890 u16 w; 2891 2892 while (len-- > 0) { 2893 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2894 rtl_ephy_write(tp, e->offset, w); 2895 e++; 2896 } 2897 } 2898 2899 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2900 2901 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2902 { 2903 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2904 PCI_EXP_LNKCTL_CLKREQ_EN); 2905 } 2906 2907 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2908 { 2909 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2910 PCI_EXP_LNKCTL_CLKREQ_EN); 2911 } 2912 2913 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2914 { 2915 /* work around an issue when PCI reset occurs during L2/L3 state */ 2916 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2917 } 2918 2919 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2920 { 2921 /* Bits control which events trigger ASPM L1 exit: 2922 * Bit 12: rxdv 2923 * Bit 11: ltr_msg 2924 * Bit 10: txdma_poll 2925 * Bit 9: xadm 2926 * Bit 8: pktavi 2927 * Bit 7: txpla 2928 */ 2929 switch (tp->mac_version) { 2930 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2931 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2932 break; 2933 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2934 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2935 break; 2936 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2937 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2938 break; 2939 default: 2940 break; 2941 } 2942 } 2943 2944 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2945 { 2946 switch (tp->mac_version) { 2947 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2948 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2949 break; 2950 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2951 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2952 break; 2953 default: 2954 break; 2955 } 2956 } 2957 2958 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2959 { 2960 u8 val8; 2961 2962 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2963 return; 2964 2965 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2966 if (enable && tp->aspm_manageable) { 2967 /* On these chip versions ASPM can even harm 2968 * bus communication of other PCI devices. 2969 */ 2970 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2971 tp->mac_version == RTL_GIGA_MAC_VER_43) 2972 return; 2973 2974 rtl_mod_config5(tp, 0, ASPM_en); 2975 switch (tp->mac_version) { 2976 case RTL_GIGA_MAC_VER_65: 2977 case RTL_GIGA_MAC_VER_66: 2978 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2979 RTL_W8(tp, INT_CFG0_8125, val8); 2980 break; 2981 default: 2982 rtl_mod_config2(tp, 0, ClkReqEn); 2983 break; 2984 } 2985 2986 switch (tp->mac_version) { 2987 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2988 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2989 /* reset ephy tx/rx disable timer */ 2990 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2991 /* chip can trigger L1.2 */ 2992 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2993 break; 2994 default: 2995 break; 2996 } 2997 } else { 2998 switch (tp->mac_version) { 2999 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 3000 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 3001 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 3002 break; 3003 default: 3004 break; 3005 } 3006 3007 switch (tp->mac_version) { 3008 case RTL_GIGA_MAC_VER_65: 3009 case RTL_GIGA_MAC_VER_66: 3010 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 3011 RTL_W8(tp, INT_CFG0_8125, val8); 3012 break; 3013 default: 3014 rtl_mod_config2(tp, ClkReqEn, 0); 3015 break; 3016 } 3017 rtl_mod_config5(tp, ASPM_en, 0); 3018 } 3019 } 3020 3021 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 3022 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 3023 { 3024 /* Usage of dynamic vs. static FIFO is controlled by bit 3025 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 3026 */ 3027 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 3028 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 3029 } 3030 3031 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3032 u8 low, u8 high) 3033 { 3034 /* FIFO thresholds for pause flow control */ 3035 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3036 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3037 } 3038 3039 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3040 { 3041 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3042 } 3043 3044 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3045 { 3046 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3047 3048 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3049 3050 rtl_disable_clock_request(tp); 3051 } 3052 3053 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3054 { 3055 static const struct ephy_info e_info_8168cp[] = { 3056 { 0x01, 0, 0x0001 }, 3057 { 0x02, 0x0800, 0x1000 }, 3058 { 0x03, 0, 0x0042 }, 3059 { 0x06, 0x0080, 0x0000 }, 3060 { 0x07, 0, 0x2000 } 3061 }; 3062 3063 rtl_set_def_aspm_entry_latency(tp); 3064 3065 rtl_ephy_init(tp, e_info_8168cp); 3066 3067 __rtl_hw_start_8168cp(tp); 3068 } 3069 3070 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3071 { 3072 rtl_set_def_aspm_entry_latency(tp); 3073 3074 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3075 } 3076 3077 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3078 { 3079 rtl_set_def_aspm_entry_latency(tp); 3080 3081 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3082 3083 /* Magic. */ 3084 RTL_W8(tp, DBG_REG, 0x20); 3085 } 3086 3087 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3088 { 3089 static const struct ephy_info e_info_8168c_1[] = { 3090 { 0x02, 0x0800, 0x1000 }, 3091 { 0x03, 0, 0x0002 }, 3092 { 0x06, 0x0080, 0x0000 } 3093 }; 3094 3095 rtl_set_def_aspm_entry_latency(tp); 3096 3097 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3098 3099 rtl_ephy_init(tp, e_info_8168c_1); 3100 3101 __rtl_hw_start_8168cp(tp); 3102 } 3103 3104 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3105 { 3106 static const struct ephy_info e_info_8168c_2[] = { 3107 { 0x01, 0, 0x0001 }, 3108 { 0x03, 0x0400, 0x0020 } 3109 }; 3110 3111 rtl_set_def_aspm_entry_latency(tp); 3112 3113 rtl_ephy_init(tp, e_info_8168c_2); 3114 3115 __rtl_hw_start_8168cp(tp); 3116 } 3117 3118 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3119 { 3120 rtl_set_def_aspm_entry_latency(tp); 3121 3122 __rtl_hw_start_8168cp(tp); 3123 } 3124 3125 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3126 { 3127 rtl_set_def_aspm_entry_latency(tp); 3128 3129 rtl_disable_clock_request(tp); 3130 } 3131 3132 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3133 { 3134 static const struct ephy_info e_info_8168d_4[] = { 3135 { 0x0b, 0x0000, 0x0048 }, 3136 { 0x19, 0x0020, 0x0050 }, 3137 { 0x0c, 0x0100, 0x0020 }, 3138 { 0x10, 0x0004, 0x0000 }, 3139 }; 3140 3141 rtl_set_def_aspm_entry_latency(tp); 3142 3143 rtl_ephy_init(tp, e_info_8168d_4); 3144 3145 rtl_enable_clock_request(tp); 3146 } 3147 3148 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3149 { 3150 static const struct ephy_info e_info_8168e_1[] = { 3151 { 0x00, 0x0200, 0x0100 }, 3152 { 0x00, 0x0000, 0x0004 }, 3153 { 0x06, 0x0002, 0x0001 }, 3154 { 0x06, 0x0000, 0x0030 }, 3155 { 0x07, 0x0000, 0x2000 }, 3156 { 0x00, 0x0000, 0x0020 }, 3157 { 0x03, 0x5800, 0x2000 }, 3158 { 0x03, 0x0000, 0x0001 }, 3159 { 0x01, 0x0800, 0x1000 }, 3160 { 0x07, 0x0000, 0x4000 }, 3161 { 0x1e, 0x0000, 0x2000 }, 3162 { 0x19, 0xffff, 0xfe6c }, 3163 { 0x0a, 0x0000, 0x0040 } 3164 }; 3165 3166 rtl_set_def_aspm_entry_latency(tp); 3167 3168 rtl_ephy_init(tp, e_info_8168e_1); 3169 3170 rtl_disable_clock_request(tp); 3171 3172 /* Reset tx FIFO pointer */ 3173 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3174 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3175 3176 rtl_mod_config5(tp, Spi_en, 0); 3177 } 3178 3179 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3180 { 3181 static const struct ephy_info e_info_8168e_2[] = { 3182 { 0x09, 0x0000, 0x0080 }, 3183 { 0x19, 0x0000, 0x0224 }, 3184 { 0x00, 0x0000, 0x0004 }, 3185 { 0x0c, 0x3df0, 0x0200 }, 3186 }; 3187 3188 rtl_set_def_aspm_entry_latency(tp); 3189 3190 rtl_ephy_init(tp, e_info_8168e_2); 3191 3192 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3193 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3194 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3195 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3196 rtl_reset_packet_filter(tp); 3197 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3198 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3199 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3200 3201 rtl_disable_clock_request(tp); 3202 3203 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3204 3205 rtl8168_config_eee_mac(tp); 3206 3207 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3208 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3209 rtl_mod_config5(tp, Spi_en, 0); 3210 } 3211 3212 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3213 { 3214 rtl_set_def_aspm_entry_latency(tp); 3215 3216 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3217 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3218 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3219 rtl_reset_packet_filter(tp); 3220 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3221 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3222 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3223 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3224 3225 rtl_disable_clock_request(tp); 3226 3227 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3228 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3229 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3230 rtl_mod_config5(tp, Spi_en, 0); 3231 3232 rtl8168_config_eee_mac(tp); 3233 } 3234 3235 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3236 { 3237 static const struct ephy_info e_info_8168f_1[] = { 3238 { 0x06, 0x00c0, 0x0020 }, 3239 { 0x08, 0x0001, 0x0002 }, 3240 { 0x09, 0x0000, 0x0080 }, 3241 { 0x19, 0x0000, 0x0224 }, 3242 { 0x00, 0x0000, 0x0008 }, 3243 { 0x0c, 0x3df0, 0x0200 }, 3244 }; 3245 3246 rtl_hw_start_8168f(tp); 3247 3248 rtl_ephy_init(tp, e_info_8168f_1); 3249 } 3250 3251 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3252 { 3253 static const struct ephy_info e_info_8168f_1[] = { 3254 { 0x06, 0x00c0, 0x0020 }, 3255 { 0x0f, 0xffff, 0x5200 }, 3256 { 0x19, 0x0000, 0x0224 }, 3257 { 0x00, 0x0000, 0x0008 }, 3258 { 0x0c, 0x3df0, 0x0200 }, 3259 }; 3260 3261 rtl_hw_start_8168f(tp); 3262 rtl_pcie_state_l2l3_disable(tp); 3263 3264 rtl_ephy_init(tp, e_info_8168f_1); 3265 } 3266 3267 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3268 { 3269 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3270 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3271 3272 rtl_set_def_aspm_entry_latency(tp); 3273 3274 rtl_reset_packet_filter(tp); 3275 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3276 3277 rtl_disable_rxdvgate(tp); 3278 3279 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3280 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3281 3282 rtl8168_config_eee_mac(tp); 3283 3284 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3285 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3286 3287 rtl_pcie_state_l2l3_disable(tp); 3288 } 3289 3290 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3291 { 3292 static const struct ephy_info e_info_8168g_1[] = { 3293 { 0x00, 0x0008, 0x0000 }, 3294 { 0x0c, 0x3ff0, 0x0820 }, 3295 { 0x1e, 0x0000, 0x0001 }, 3296 { 0x19, 0x8000, 0x0000 } 3297 }; 3298 3299 rtl_hw_start_8168g(tp); 3300 rtl_ephy_init(tp, e_info_8168g_1); 3301 } 3302 3303 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3304 { 3305 static const struct ephy_info e_info_8168g_2[] = { 3306 { 0x00, 0x0008, 0x0000 }, 3307 { 0x0c, 0x3ff0, 0x0820 }, 3308 { 0x19, 0xffff, 0x7c00 }, 3309 { 0x1e, 0xffff, 0x20eb }, 3310 { 0x0d, 0xffff, 0x1666 }, 3311 { 0x00, 0xffff, 0x10a3 }, 3312 { 0x06, 0xffff, 0xf050 }, 3313 { 0x04, 0x0000, 0x0010 }, 3314 { 0x1d, 0x4000, 0x0000 }, 3315 }; 3316 3317 rtl_hw_start_8168g(tp); 3318 rtl_ephy_init(tp, e_info_8168g_2); 3319 } 3320 3321 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3322 { 3323 static const u16 fix_data[] = { 3324 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3325 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3326 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3327 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3328 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3329 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3330 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3331 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3332 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3333 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3334 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3335 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3336 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3337 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3338 }; 3339 unsigned long flags; 3340 int i; 3341 3342 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3343 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3344 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3345 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3346 } 3347 3348 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3349 { 3350 static const struct ephy_info e_info_8411_2[] = { 3351 { 0x00, 0x0008, 0x0000 }, 3352 { 0x0c, 0x37d0, 0x0820 }, 3353 { 0x1e, 0x0000, 0x0001 }, 3354 { 0x19, 0x8021, 0x0000 }, 3355 { 0x1e, 0x0000, 0x2000 }, 3356 { 0x0d, 0x0100, 0x0200 }, 3357 { 0x00, 0x0000, 0x0080 }, 3358 { 0x06, 0x0000, 0x0010 }, 3359 { 0x04, 0x0000, 0x0010 }, 3360 { 0x1d, 0x0000, 0x4000 }, 3361 }; 3362 3363 rtl_hw_start_8168g(tp); 3364 3365 rtl_ephy_init(tp, e_info_8411_2); 3366 3367 /* The following Realtek-provided magic fixes an issue with the RX unit 3368 * getting confused after the PHY having been powered-down. 3369 */ 3370 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3371 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3372 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3373 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3374 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3375 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3376 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3377 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3378 mdelay(3); 3379 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3380 3381 rtl8411b_fix_phy_down(tp); 3382 3383 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3384 3385 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3386 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3387 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3388 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3389 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3390 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3391 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3392 } 3393 3394 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3395 { 3396 static const struct ephy_info e_info_8168h_1[] = { 3397 { 0x1e, 0x0800, 0x0001 }, 3398 { 0x1d, 0x0000, 0x0800 }, 3399 { 0x05, 0xffff, 0x2089 }, 3400 { 0x06, 0xffff, 0x5881 }, 3401 { 0x04, 0xffff, 0x854a }, 3402 { 0x01, 0xffff, 0x068b } 3403 }; 3404 int rg_saw_cnt; 3405 3406 rtl_ephy_init(tp, e_info_8168h_1); 3407 3408 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3409 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3410 3411 rtl_set_def_aspm_entry_latency(tp); 3412 3413 rtl_reset_packet_filter(tp); 3414 3415 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3416 3417 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3418 3419 rtl_disable_rxdvgate(tp); 3420 3421 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3422 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3423 3424 rtl8168_config_eee_mac(tp); 3425 3426 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3427 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3428 3429 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3430 3431 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3432 3433 rtl_pcie_state_l2l3_disable(tp); 3434 3435 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3436 if (rg_saw_cnt > 0) { 3437 u16 sw_cnt_1ms_ini; 3438 3439 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3440 sw_cnt_1ms_ini &= 0x0fff; 3441 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3442 } 3443 3444 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3445 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3446 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3447 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3448 3449 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3450 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3451 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3452 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3453 } 3454 3455 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3456 { 3457 rtl8168ep_stop_cmac(tp); 3458 3459 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3460 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3461 3462 rtl_set_def_aspm_entry_latency(tp); 3463 3464 rtl_reset_packet_filter(tp); 3465 3466 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3467 3468 rtl_disable_rxdvgate(tp); 3469 3470 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3471 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3472 3473 rtl8168_config_eee_mac(tp); 3474 3475 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3476 3477 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3478 3479 rtl_pcie_state_l2l3_disable(tp); 3480 } 3481 3482 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3483 { 3484 static const struct ephy_info e_info_8168ep_3[] = { 3485 { 0x00, 0x0000, 0x0080 }, 3486 { 0x0d, 0x0100, 0x0200 }, 3487 { 0x19, 0x8021, 0x0000 }, 3488 { 0x1e, 0x0000, 0x2000 }, 3489 }; 3490 3491 rtl_ephy_init(tp, e_info_8168ep_3); 3492 3493 rtl_hw_start_8168ep(tp); 3494 3495 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3496 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3497 3498 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3499 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3500 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3501 } 3502 3503 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3504 { 3505 static const struct ephy_info e_info_8117[] = { 3506 { 0x19, 0x0040, 0x1100 }, 3507 { 0x59, 0x0040, 0x1100 }, 3508 }; 3509 int rg_saw_cnt; 3510 3511 rtl8168ep_stop_cmac(tp); 3512 rtl_ephy_init(tp, e_info_8117); 3513 3514 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3515 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3516 3517 rtl_set_def_aspm_entry_latency(tp); 3518 3519 rtl_reset_packet_filter(tp); 3520 3521 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3522 3523 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3524 3525 rtl_disable_rxdvgate(tp); 3526 3527 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3528 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3529 3530 rtl8168_config_eee_mac(tp); 3531 3532 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3533 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3534 3535 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3536 3537 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3538 3539 rtl_pcie_state_l2l3_disable(tp); 3540 3541 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3542 if (rg_saw_cnt > 0) { 3543 u16 sw_cnt_1ms_ini; 3544 3545 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3546 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3547 } 3548 3549 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3550 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3551 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3552 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3553 3554 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3555 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3556 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3557 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3558 3559 /* firmware is for MAC only */ 3560 r8169_apply_firmware(tp); 3561 } 3562 3563 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3564 { 3565 static const struct ephy_info e_info_8102e_1[] = { 3566 { 0x01, 0, 0x6e65 }, 3567 { 0x02, 0, 0x091f }, 3568 { 0x03, 0, 0xc2f9 }, 3569 { 0x06, 0, 0xafb5 }, 3570 { 0x07, 0, 0x0e00 }, 3571 { 0x19, 0, 0xec80 }, 3572 { 0x01, 0, 0x2e65 }, 3573 { 0x01, 0, 0x6e65 } 3574 }; 3575 u8 cfg1; 3576 3577 rtl_set_def_aspm_entry_latency(tp); 3578 3579 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3580 3581 RTL_W8(tp, Config1, 3582 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3583 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3584 3585 cfg1 = RTL_R8(tp, Config1); 3586 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3587 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3588 3589 rtl_ephy_init(tp, e_info_8102e_1); 3590 } 3591 3592 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3593 { 3594 rtl_set_def_aspm_entry_latency(tp); 3595 3596 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3597 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3598 } 3599 3600 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3601 { 3602 rtl_hw_start_8102e_2(tp); 3603 3604 rtl_ephy_write(tp, 0x03, 0xc2f9); 3605 } 3606 3607 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3608 { 3609 static const struct ephy_info e_info_8401[] = { 3610 { 0x01, 0xffff, 0x6fe5 }, 3611 { 0x03, 0xffff, 0x0599 }, 3612 { 0x06, 0xffff, 0xaf25 }, 3613 { 0x07, 0xffff, 0x8e68 }, 3614 }; 3615 3616 rtl_ephy_init(tp, e_info_8401); 3617 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3618 } 3619 3620 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3621 { 3622 static const struct ephy_info e_info_8105e_1[] = { 3623 { 0x07, 0, 0x4000 }, 3624 { 0x19, 0, 0x0200 }, 3625 { 0x19, 0, 0x0020 }, 3626 { 0x1e, 0, 0x2000 }, 3627 { 0x03, 0, 0x0001 }, 3628 { 0x19, 0, 0x0100 }, 3629 { 0x19, 0, 0x0004 }, 3630 { 0x0a, 0, 0x0020 } 3631 }; 3632 3633 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3634 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3635 3636 /* Disable Early Tally Counter */ 3637 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3638 3639 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3640 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3641 3642 rtl_ephy_init(tp, e_info_8105e_1); 3643 3644 rtl_pcie_state_l2l3_disable(tp); 3645 } 3646 3647 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3648 { 3649 rtl_hw_start_8105e_1(tp); 3650 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3651 } 3652 3653 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3654 { 3655 static const struct ephy_info e_info_8402[] = { 3656 { 0x19, 0xffff, 0xff64 }, 3657 { 0x1e, 0, 0x4000 } 3658 }; 3659 3660 rtl_set_def_aspm_entry_latency(tp); 3661 3662 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3663 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3664 3665 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3666 3667 rtl_ephy_init(tp, e_info_8402); 3668 3669 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3670 rtl_reset_packet_filter(tp); 3671 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3672 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3673 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3674 3675 /* disable EEE */ 3676 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3677 3678 rtl_pcie_state_l2l3_disable(tp); 3679 } 3680 3681 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3682 { 3683 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3684 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3685 3686 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3687 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3688 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3689 3690 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3691 rtl_set_aspm_entry_latency(tp, 0x2f); 3692 3693 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3694 3695 /* disable EEE */ 3696 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3697 3698 rtl_pcie_state_l2l3_disable(tp); 3699 } 3700 3701 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3702 { 3703 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3704 } 3705 3706 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3707 { 3708 rtl_pcie_state_l2l3_disable(tp); 3709 3710 RTL_W16(tp, 0x382, 0x221b); 3711 RTL_W8(tp, 0x4500, 0); 3712 RTL_W16(tp, 0x4800, 0); 3713 3714 /* disable UPS */ 3715 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3716 3717 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3718 3719 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3720 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3721 3722 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3723 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3724 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3725 3726 /* disable new tx descriptor format */ 3727 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3728 3729 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3730 tp->mac_version == RTL_GIGA_MAC_VER_66) 3731 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3732 3733 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3734 tp->mac_version == RTL_GIGA_MAC_VER_66) 3735 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3736 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3737 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3738 else 3739 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3740 3741 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3742 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3743 else 3744 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3745 3746 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3747 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3748 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3749 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3750 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3751 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3752 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3753 tp->mac_version == RTL_GIGA_MAC_VER_66) 3754 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3755 else 3756 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3757 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3758 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3759 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3760 3761 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3762 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3763 udelay(1); 3764 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3765 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3766 3767 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3768 3769 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3770 3771 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3772 rtl8125a_config_eee_mac(tp); 3773 else 3774 rtl8125b_config_eee_mac(tp); 3775 3776 rtl_disable_rxdvgate(tp); 3777 } 3778 3779 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3780 { 3781 static const struct ephy_info e_info_8125a_2[] = { 3782 { 0x04, 0xffff, 0xd000 }, 3783 { 0x0a, 0xffff, 0x8653 }, 3784 { 0x23, 0xffff, 0xab66 }, 3785 { 0x20, 0xffff, 0x9455 }, 3786 { 0x21, 0xffff, 0x99ff }, 3787 { 0x29, 0xffff, 0xfe04 }, 3788 3789 { 0x44, 0xffff, 0xd000 }, 3790 { 0x4a, 0xffff, 0x8653 }, 3791 { 0x63, 0xffff, 0xab66 }, 3792 { 0x60, 0xffff, 0x9455 }, 3793 { 0x61, 0xffff, 0x99ff }, 3794 { 0x69, 0xffff, 0xfe04 }, 3795 }; 3796 3797 rtl_set_def_aspm_entry_latency(tp); 3798 rtl_ephy_init(tp, e_info_8125a_2); 3799 rtl_hw_start_8125_common(tp); 3800 } 3801 3802 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3803 { 3804 static const struct ephy_info e_info_8125b[] = { 3805 { 0x0b, 0xffff, 0xa908 }, 3806 { 0x1e, 0xffff, 0x20eb }, 3807 { 0x4b, 0xffff, 0xa908 }, 3808 { 0x5e, 0xffff, 0x20eb }, 3809 { 0x22, 0x0030, 0x0020 }, 3810 { 0x62, 0x0030, 0x0020 }, 3811 }; 3812 3813 rtl_set_def_aspm_entry_latency(tp); 3814 rtl_ephy_init(tp, e_info_8125b); 3815 rtl_hw_start_8125_common(tp); 3816 } 3817 3818 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3819 { 3820 rtl_set_def_aspm_entry_latency(tp); 3821 rtl_hw_start_8125_common(tp); 3822 } 3823 3824 static void rtl_hw_config(struct rtl8169_private *tp) 3825 { 3826 static const rtl_generic_fct hw_configs[] = { 3827 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3828 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3829 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3830 [RTL_GIGA_MAC_VER_10] = NULL, 3831 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3832 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3833 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3834 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3835 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3836 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3837 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3838 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3839 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3840 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3841 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3842 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3843 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3844 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3845 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3846 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3847 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3848 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3849 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3850 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3851 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3852 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3853 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3854 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3855 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3856 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3857 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3858 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3859 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3860 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3861 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3862 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3863 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3864 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3865 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3866 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3867 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a, 3868 }; 3869 3870 if (hw_configs[tp->mac_version]) 3871 hw_configs[tp->mac_version](tp); 3872 } 3873 3874 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3875 { 3876 int i; 3877 3878 RTL_W8(tp, INT_CFG0_8125, 0x00); 3879 3880 /* disable interrupt coalescing */ 3881 switch (tp->mac_version) { 3882 case RTL_GIGA_MAC_VER_61: 3883 for (i = 0xa00; i < 0xb00; i += 4) 3884 RTL_W32(tp, i, 0); 3885 break; 3886 case RTL_GIGA_MAC_VER_63: 3887 case RTL_GIGA_MAC_VER_65: 3888 case RTL_GIGA_MAC_VER_66: 3889 for (i = 0xa00; i < 0xa80; i += 4) 3890 RTL_W32(tp, i, 0); 3891 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3892 break; 3893 default: 3894 break; 3895 } 3896 3897 rtl_hw_config(tp); 3898 } 3899 3900 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3901 { 3902 if (rtl_is_8168evl_up(tp)) 3903 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3904 else 3905 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3906 3907 rtl_hw_config(tp); 3908 3909 /* disable interrupt coalescing */ 3910 RTL_W16(tp, IntrMitigate, 0x0000); 3911 } 3912 3913 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3914 { 3915 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3916 3917 tp->cp_cmd |= PCIMulRW; 3918 3919 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3920 tp->mac_version == RTL_GIGA_MAC_VER_03) 3921 tp->cp_cmd |= EnAnaPLL; 3922 3923 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3924 3925 rtl8169_set_magic_reg(tp); 3926 3927 /* disable interrupt coalescing */ 3928 RTL_W16(tp, IntrMitigate, 0x0000); 3929 } 3930 3931 static void rtl_hw_start(struct rtl8169_private *tp) 3932 { 3933 rtl_unlock_config_regs(tp); 3934 /* disable aspm and clock request before ephy access */ 3935 rtl_hw_aspm_clkreq_enable(tp, false); 3936 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3937 3938 rtl_set_eee_txidle_timer(tp); 3939 3940 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3941 rtl_hw_start_8169(tp); 3942 else if (rtl_is_8125(tp)) 3943 rtl_hw_start_8125(tp); 3944 else 3945 rtl_hw_start_8168(tp); 3946 3947 rtl_enable_exit_l1(tp); 3948 rtl_hw_aspm_clkreq_enable(tp, true); 3949 rtl_set_rx_max_size(tp); 3950 rtl_set_rx_tx_desc_registers(tp); 3951 rtl_lock_config_regs(tp); 3952 3953 rtl_jumbo_config(tp); 3954 3955 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3956 rtl_pci_commit(tp); 3957 3958 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3959 rtl_init_rxcfg(tp); 3960 rtl_set_tx_config_registers(tp); 3961 rtl_set_rx_config_features(tp, tp->dev->features); 3962 rtl_set_rx_mode(tp->dev); 3963 rtl_irq_enable(tp); 3964 } 3965 3966 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3967 { 3968 struct rtl8169_private *tp = netdev_priv(dev); 3969 3970 WRITE_ONCE(dev->mtu, new_mtu); 3971 netdev_update_features(dev); 3972 rtl_jumbo_config(tp); 3973 rtl_set_eee_txidle_timer(tp); 3974 3975 return 0; 3976 } 3977 3978 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3979 { 3980 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3981 3982 desc->opts2 = 0; 3983 /* Force memory writes to complete before releasing descriptor */ 3984 dma_wmb(); 3985 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3986 } 3987 3988 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3989 struct RxDesc *desc) 3990 { 3991 struct device *d = tp_to_dev(tp); 3992 int node = dev_to_node(d); 3993 dma_addr_t mapping; 3994 struct page *data; 3995 3996 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3997 if (!data) 3998 return NULL; 3999 4000 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4001 if (unlikely(dma_mapping_error(d, mapping))) { 4002 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 4003 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 4004 return NULL; 4005 } 4006 4007 desc->addr = cpu_to_le64(mapping); 4008 rtl8169_mark_to_asic(desc); 4009 4010 return data; 4011 } 4012 4013 static void rtl8169_rx_clear(struct rtl8169_private *tp) 4014 { 4015 int i; 4016 4017 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 4018 dma_unmap_page(tp_to_dev(tp), 4019 le64_to_cpu(tp->RxDescArray[i].addr), 4020 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4021 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4022 tp->Rx_databuff[i] = NULL; 4023 tp->RxDescArray[i].addr = 0; 4024 tp->RxDescArray[i].opts1 = 0; 4025 } 4026 } 4027 4028 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4029 { 4030 int i; 4031 4032 for (i = 0; i < NUM_RX_DESC; i++) { 4033 struct page *data; 4034 4035 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4036 if (!data) { 4037 rtl8169_rx_clear(tp); 4038 return -ENOMEM; 4039 } 4040 tp->Rx_databuff[i] = data; 4041 } 4042 4043 /* mark as last descriptor in the ring */ 4044 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4045 4046 return 0; 4047 } 4048 4049 static int rtl8169_init_ring(struct rtl8169_private *tp) 4050 { 4051 rtl8169_init_ring_indexes(tp); 4052 4053 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4054 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4055 4056 return rtl8169_rx_fill(tp); 4057 } 4058 4059 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4060 { 4061 struct ring_info *tx_skb = tp->tx_skb + entry; 4062 struct TxDesc *desc = tp->TxDescArray + entry; 4063 4064 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4065 DMA_TO_DEVICE); 4066 memset(desc, 0, sizeof(*desc)); 4067 memset(tx_skb, 0, sizeof(*tx_skb)); 4068 } 4069 4070 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4071 unsigned int n) 4072 { 4073 unsigned int i; 4074 4075 for (i = 0; i < n; i++) { 4076 unsigned int entry = (start + i) % NUM_TX_DESC; 4077 struct ring_info *tx_skb = tp->tx_skb + entry; 4078 unsigned int len = tx_skb->len; 4079 4080 if (len) { 4081 struct sk_buff *skb = tx_skb->skb; 4082 4083 rtl8169_unmap_tx_skb(tp, entry); 4084 if (skb) 4085 dev_consume_skb_any(skb); 4086 } 4087 } 4088 } 4089 4090 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4091 { 4092 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4093 netdev_reset_queue(tp->dev); 4094 } 4095 4096 static void rtl8169_cleanup(struct rtl8169_private *tp) 4097 { 4098 napi_disable(&tp->napi); 4099 4100 /* Give a racing hard_start_xmit a few cycles to complete. */ 4101 synchronize_net(); 4102 4103 /* Disable interrupts */ 4104 rtl8169_irq_mask_and_ack(tp); 4105 4106 rtl_rx_close(tp); 4107 4108 switch (tp->mac_version) { 4109 case RTL_GIGA_MAC_VER_28: 4110 case RTL_GIGA_MAC_VER_31: 4111 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4112 break; 4113 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4114 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4115 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4116 break; 4117 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 4118 rtl_enable_rxdvgate(tp); 4119 fsleep(2000); 4120 break; 4121 default: 4122 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4123 fsleep(100); 4124 break; 4125 } 4126 4127 rtl_hw_reset(tp); 4128 4129 rtl8169_tx_clear(tp); 4130 rtl8169_init_ring_indexes(tp); 4131 } 4132 4133 static void rtl_reset_work(struct rtl8169_private *tp) 4134 { 4135 int i; 4136 4137 netif_stop_queue(tp->dev); 4138 4139 rtl8169_cleanup(tp); 4140 4141 for (i = 0; i < NUM_RX_DESC; i++) 4142 rtl8169_mark_to_asic(tp->RxDescArray + i); 4143 4144 napi_enable(&tp->napi); 4145 rtl_hw_start(tp); 4146 } 4147 4148 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4149 { 4150 struct rtl8169_private *tp = netdev_priv(dev); 4151 4152 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4153 } 4154 4155 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4156 void *addr, unsigned int entry, bool desc_own) 4157 { 4158 struct TxDesc *txd = tp->TxDescArray + entry; 4159 struct device *d = tp_to_dev(tp); 4160 dma_addr_t mapping; 4161 u32 opts1; 4162 int ret; 4163 4164 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4165 ret = dma_mapping_error(d, mapping); 4166 if (unlikely(ret)) { 4167 if (net_ratelimit()) 4168 netdev_err(tp->dev, "Failed to map TX data!\n"); 4169 return ret; 4170 } 4171 4172 txd->addr = cpu_to_le64(mapping); 4173 txd->opts2 = cpu_to_le32(opts[1]); 4174 4175 opts1 = opts[0] | len; 4176 if (entry == NUM_TX_DESC - 1) 4177 opts1 |= RingEnd; 4178 if (desc_own) 4179 opts1 |= DescOwn; 4180 txd->opts1 = cpu_to_le32(opts1); 4181 4182 tp->tx_skb[entry].len = len; 4183 4184 return 0; 4185 } 4186 4187 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4188 const u32 *opts, unsigned int entry) 4189 { 4190 struct skb_shared_info *info = skb_shinfo(skb); 4191 unsigned int cur_frag; 4192 4193 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4194 const skb_frag_t *frag = info->frags + cur_frag; 4195 void *addr = skb_frag_address(frag); 4196 u32 len = skb_frag_size(frag); 4197 4198 entry = (entry + 1) % NUM_TX_DESC; 4199 4200 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4201 goto err_out; 4202 } 4203 4204 return 0; 4205 4206 err_out: 4207 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4208 return -EIO; 4209 } 4210 4211 static bool rtl_skb_is_udp(struct sk_buff *skb) 4212 { 4213 int no = skb_network_offset(skb); 4214 struct ipv6hdr *i6h, _i6h; 4215 struct iphdr *ih, _ih; 4216 4217 switch (vlan_get_protocol(skb)) { 4218 case htons(ETH_P_IP): 4219 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4220 return ih && ih->protocol == IPPROTO_UDP; 4221 case htons(ETH_P_IPV6): 4222 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4223 return i6h && i6h->nexthdr == IPPROTO_UDP; 4224 default: 4225 return false; 4226 } 4227 } 4228 4229 #define RTL_MIN_PATCH_LEN 47 4230 4231 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4232 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4233 struct sk_buff *skb) 4234 { 4235 unsigned int padto = 0, len = skb->len; 4236 4237 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4238 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4239 unsigned int trans_data_len = skb_tail_pointer(skb) - 4240 skb_transport_header(skb); 4241 4242 if (trans_data_len >= offsetof(struct udphdr, len) && 4243 trans_data_len < RTL_MIN_PATCH_LEN) { 4244 u16 dest = ntohs(udp_hdr(skb)->dest); 4245 4246 /* dest is a standard PTP port */ 4247 if (dest == 319 || dest == 320) 4248 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4249 } 4250 4251 if (trans_data_len < sizeof(struct udphdr)) 4252 padto = max_t(unsigned int, padto, 4253 len + sizeof(struct udphdr) - trans_data_len); 4254 } 4255 4256 return padto; 4257 } 4258 4259 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4260 struct sk_buff *skb) 4261 { 4262 unsigned int padto; 4263 4264 padto = rtl8125_quirk_udp_padto(tp, skb); 4265 4266 switch (tp->mac_version) { 4267 case RTL_GIGA_MAC_VER_34: 4268 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 4269 padto = max_t(unsigned int, padto, ETH_ZLEN); 4270 break; 4271 default: 4272 break; 4273 } 4274 4275 return padto; 4276 } 4277 4278 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4279 { 4280 u32 mss = skb_shinfo(skb)->gso_size; 4281 4282 if (mss) { 4283 opts[0] |= TD_LSO; 4284 opts[0] |= mss << TD0_MSS_SHIFT; 4285 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4286 const struct iphdr *ip = ip_hdr(skb); 4287 4288 if (ip->protocol == IPPROTO_TCP) 4289 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4290 else if (ip->protocol == IPPROTO_UDP) 4291 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4292 else 4293 WARN_ON_ONCE(1); 4294 } 4295 } 4296 4297 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4298 struct sk_buff *skb, u32 *opts) 4299 { 4300 struct skb_shared_info *shinfo = skb_shinfo(skb); 4301 u32 mss = shinfo->gso_size; 4302 4303 if (mss) { 4304 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4305 opts[0] |= TD1_GTSENV4; 4306 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4307 if (skb_cow_head(skb, 0)) 4308 return false; 4309 4310 tcp_v6_gso_csum_prep(skb); 4311 opts[0] |= TD1_GTSENV6; 4312 } else { 4313 WARN_ON_ONCE(1); 4314 } 4315 4316 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4317 opts[1] |= mss << TD1_MSS_SHIFT; 4318 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4319 u8 ip_protocol; 4320 4321 switch (vlan_get_protocol(skb)) { 4322 case htons(ETH_P_IP): 4323 opts[1] |= TD1_IPv4_CS; 4324 ip_protocol = ip_hdr(skb)->protocol; 4325 break; 4326 4327 case htons(ETH_P_IPV6): 4328 opts[1] |= TD1_IPv6_CS; 4329 ip_protocol = ipv6_hdr(skb)->nexthdr; 4330 break; 4331 4332 default: 4333 ip_protocol = IPPROTO_RAW; 4334 break; 4335 } 4336 4337 if (ip_protocol == IPPROTO_TCP) 4338 opts[1] |= TD1_TCP_CS; 4339 else if (ip_protocol == IPPROTO_UDP) 4340 opts[1] |= TD1_UDP_CS; 4341 else 4342 WARN_ON_ONCE(1); 4343 4344 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4345 } else { 4346 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4347 4348 /* skb_padto would free the skb on error */ 4349 return !__skb_put_padto(skb, padto, false); 4350 } 4351 4352 return true; 4353 } 4354 4355 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4356 { 4357 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4358 } 4359 4360 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4361 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4362 { 4363 switch (tp->mac_version) { 4364 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4365 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4366 return false; 4367 default: 4368 return true; 4369 } 4370 } 4371 4372 static void rtl8169_doorbell(struct rtl8169_private *tp) 4373 { 4374 if (rtl_is_8125(tp)) 4375 RTL_W16(tp, TxPoll_8125, BIT(0)); 4376 else 4377 RTL_W8(tp, TxPoll, NPQ); 4378 } 4379 4380 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4381 struct net_device *dev) 4382 { 4383 struct rtl8169_private *tp = netdev_priv(dev); 4384 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4385 struct TxDesc *txd_first, *txd_last; 4386 bool stop_queue, door_bell; 4387 unsigned int frags; 4388 u32 opts[2]; 4389 4390 if (unlikely(!rtl_tx_slots_avail(tp))) { 4391 if (net_ratelimit()) 4392 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4393 netif_stop_queue(dev); 4394 return NETDEV_TX_BUSY; 4395 } 4396 4397 opts[1] = rtl8169_tx_vlan_tag(skb); 4398 opts[0] = 0; 4399 4400 if (!rtl_chip_supports_csum_v2(tp)) 4401 rtl8169_tso_csum_v1(skb, opts); 4402 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4403 goto err_dma_0; 4404 4405 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4406 entry, false))) 4407 goto err_dma_0; 4408 4409 txd_first = tp->TxDescArray + entry; 4410 4411 frags = skb_shinfo(skb)->nr_frags; 4412 if (frags) { 4413 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4414 goto err_dma_1; 4415 entry = (entry + frags) % NUM_TX_DESC; 4416 } 4417 4418 txd_last = tp->TxDescArray + entry; 4419 txd_last->opts1 |= cpu_to_le32(LastFrag); 4420 tp->tx_skb[entry].skb = skb; 4421 4422 skb_tx_timestamp(skb); 4423 4424 /* Force memory writes to complete before releasing descriptor */ 4425 dma_wmb(); 4426 4427 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4428 4429 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4430 4431 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4432 smp_wmb(); 4433 4434 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4435 4436 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4437 R8169_TX_STOP_THRS, 4438 R8169_TX_START_THRS); 4439 if (door_bell || stop_queue) 4440 rtl8169_doorbell(tp); 4441 4442 return NETDEV_TX_OK; 4443 4444 err_dma_1: 4445 rtl8169_unmap_tx_skb(tp, entry); 4446 err_dma_0: 4447 dev_kfree_skb_any(skb); 4448 dev->stats.tx_dropped++; 4449 return NETDEV_TX_OK; 4450 } 4451 4452 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4453 { 4454 struct skb_shared_info *info = skb_shinfo(skb); 4455 unsigned int nr_frags = info->nr_frags; 4456 4457 if (!nr_frags) 4458 return UINT_MAX; 4459 4460 return skb_frag_size(info->frags + nr_frags - 1); 4461 } 4462 4463 /* Workaround for hw issues with TSO on RTL8168evl */ 4464 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4465 netdev_features_t features) 4466 { 4467 /* IPv4 header has options field */ 4468 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4469 ip_hdrlen(skb) > sizeof(struct iphdr)) 4470 features &= ~NETIF_F_ALL_TSO; 4471 4472 /* IPv4 TCP header has options field */ 4473 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4474 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4475 features &= ~NETIF_F_ALL_TSO; 4476 4477 else if (rtl_last_frag_len(skb) <= 6) 4478 features &= ~NETIF_F_ALL_TSO; 4479 4480 return features; 4481 } 4482 4483 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4484 struct net_device *dev, 4485 netdev_features_t features) 4486 { 4487 struct rtl8169_private *tp = netdev_priv(dev); 4488 4489 if (skb_is_gso(skb)) { 4490 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4491 features = rtl8168evl_fix_tso(skb, features); 4492 4493 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4494 rtl_chip_supports_csum_v2(tp)) 4495 features &= ~NETIF_F_ALL_TSO; 4496 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4497 /* work around hw bug on some chip versions */ 4498 if (skb->len < ETH_ZLEN) 4499 features &= ~NETIF_F_CSUM_MASK; 4500 4501 if (rtl_quirk_packet_padto(tp, skb)) 4502 features &= ~NETIF_F_CSUM_MASK; 4503 4504 if (skb_transport_offset(skb) > TCPHO_MAX && 4505 rtl_chip_supports_csum_v2(tp)) 4506 features &= ~NETIF_F_CSUM_MASK; 4507 } 4508 4509 return vlan_features_check(skb, features); 4510 } 4511 4512 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4513 { 4514 struct rtl8169_private *tp = netdev_priv(dev); 4515 struct pci_dev *pdev = tp->pci_dev; 4516 int pci_status_errs; 4517 u16 pci_cmd; 4518 4519 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4520 4521 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4522 4523 if (net_ratelimit()) 4524 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4525 pci_cmd, pci_status_errs); 4526 4527 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4528 } 4529 4530 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4531 int budget) 4532 { 4533 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4534 struct sk_buff *skb; 4535 4536 dirty_tx = tp->dirty_tx; 4537 4538 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4539 unsigned int entry = dirty_tx % NUM_TX_DESC; 4540 u32 status; 4541 4542 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4543 if (status & DescOwn) 4544 break; 4545 4546 skb = tp->tx_skb[entry].skb; 4547 rtl8169_unmap_tx_skb(tp, entry); 4548 4549 if (skb) { 4550 pkts_compl++; 4551 bytes_compl += skb->len; 4552 napi_consume_skb(skb, budget); 4553 } 4554 dirty_tx++; 4555 } 4556 4557 if (tp->dirty_tx != dirty_tx) { 4558 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4559 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4560 4561 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4562 rtl_tx_slots_avail(tp), 4563 R8169_TX_START_THRS); 4564 /* 4565 * 8168 hack: TxPoll requests are lost when the Tx packets are 4566 * too close. Let's kick an extra TxPoll request when a burst 4567 * of start_xmit activity is detected (if it is not detected, 4568 * it is slow enough). -- FR 4569 * If skb is NULL then we come here again once a tx irq is 4570 * triggered after the last fragment is marked transmitted. 4571 */ 4572 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4573 rtl8169_doorbell(tp); 4574 } 4575 } 4576 4577 static inline int rtl8169_fragmented_frame(u32 status) 4578 { 4579 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4580 } 4581 4582 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4583 { 4584 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4585 4586 if (status == RxProtoTCP || status == RxProtoUDP) 4587 skb->ip_summed = CHECKSUM_UNNECESSARY; 4588 else 4589 skb_checksum_none_assert(skb); 4590 } 4591 4592 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4593 { 4594 struct device *d = tp_to_dev(tp); 4595 int count; 4596 4597 for (count = 0; count < budget; count++, tp->cur_rx++) { 4598 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4599 struct RxDesc *desc = tp->RxDescArray + entry; 4600 struct sk_buff *skb; 4601 const void *rx_buf; 4602 dma_addr_t addr; 4603 u32 status; 4604 4605 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4606 if (status & DescOwn) 4607 break; 4608 4609 /* This barrier is needed to keep us from reading 4610 * any other fields out of the Rx descriptor until 4611 * we know the status of DescOwn 4612 */ 4613 dma_rmb(); 4614 4615 if (unlikely(status & RxRES)) { 4616 if (net_ratelimit()) 4617 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4618 status); 4619 dev->stats.rx_errors++; 4620 if (status & (RxRWT | RxRUNT)) 4621 dev->stats.rx_length_errors++; 4622 if (status & RxCRC) 4623 dev->stats.rx_crc_errors++; 4624 4625 if (!(dev->features & NETIF_F_RXALL)) 4626 goto release_descriptor; 4627 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4628 goto release_descriptor; 4629 } 4630 4631 pkt_size = status & GENMASK(13, 0); 4632 if (likely(!(dev->features & NETIF_F_RXFCS))) 4633 pkt_size -= ETH_FCS_LEN; 4634 4635 /* The driver does not support incoming fragmented frames. 4636 * They are seen as a symptom of over-mtu sized frames. 4637 */ 4638 if (unlikely(rtl8169_fragmented_frame(status))) { 4639 dev->stats.rx_dropped++; 4640 dev->stats.rx_length_errors++; 4641 goto release_descriptor; 4642 } 4643 4644 skb = napi_alloc_skb(&tp->napi, pkt_size); 4645 if (unlikely(!skb)) { 4646 dev->stats.rx_dropped++; 4647 goto release_descriptor; 4648 } 4649 4650 addr = le64_to_cpu(desc->addr); 4651 rx_buf = page_address(tp->Rx_databuff[entry]); 4652 4653 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4654 prefetch(rx_buf); 4655 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4656 skb->tail += pkt_size; 4657 skb->len = pkt_size; 4658 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4659 4660 rtl8169_rx_csum(skb, status); 4661 skb->protocol = eth_type_trans(skb, dev); 4662 4663 rtl8169_rx_vlan_tag(desc, skb); 4664 4665 if (skb->pkt_type == PACKET_MULTICAST) 4666 dev->stats.multicast++; 4667 4668 napi_gro_receive(&tp->napi, skb); 4669 4670 dev_sw_netstats_rx_add(dev, pkt_size); 4671 release_descriptor: 4672 rtl8169_mark_to_asic(desc); 4673 } 4674 4675 return count; 4676 } 4677 4678 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4679 { 4680 struct rtl8169_private *tp = dev_instance; 4681 u32 status = rtl_get_events(tp); 4682 4683 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4684 return IRQ_NONE; 4685 4686 if (unlikely(status & SYSErr)) { 4687 rtl8169_pcierr_interrupt(tp->dev); 4688 goto out; 4689 } 4690 4691 if (status & LinkChg) 4692 phy_mac_interrupt(tp->phydev); 4693 4694 if (unlikely(status & RxFIFOOver && 4695 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4696 netif_stop_queue(tp->dev); 4697 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4698 } 4699 4700 rtl_irq_disable(tp); 4701 napi_schedule(&tp->napi); 4702 out: 4703 rtl_ack_events(tp, status); 4704 4705 return IRQ_HANDLED; 4706 } 4707 4708 static void rtl_task(struct work_struct *work) 4709 { 4710 struct rtl8169_private *tp = 4711 container_of(work, struct rtl8169_private, wk.work); 4712 int ret; 4713 4714 rtnl_lock(); 4715 4716 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4717 goto out_unlock; 4718 4719 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4720 /* if chip isn't accessible, reset bus to revive it */ 4721 if (RTL_R32(tp, TxConfig) == ~0) { 4722 ret = pci_reset_bus(tp->pci_dev); 4723 if (ret < 0) { 4724 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4725 netif_device_detach(tp->dev); 4726 goto out_unlock; 4727 } 4728 } 4729 4730 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4731 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4732 PCIE_LINK_STATE_L0S); 4733 if (!ret) 4734 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4735 goto reset; 4736 } 4737 4738 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4739 reset: 4740 rtl_reset_work(tp); 4741 netif_wake_queue(tp->dev); 4742 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4743 rtl_reset_work(tp); 4744 } 4745 out_unlock: 4746 rtnl_unlock(); 4747 } 4748 4749 static int rtl8169_poll(struct napi_struct *napi, int budget) 4750 { 4751 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4752 struct net_device *dev = tp->dev; 4753 int work_done; 4754 4755 rtl_tx(dev, tp, budget); 4756 4757 work_done = rtl_rx(dev, tp, budget); 4758 4759 if (work_done < budget && napi_complete_done(napi, work_done)) 4760 rtl_irq_enable(tp); 4761 4762 return work_done; 4763 } 4764 4765 static void r8169_phylink_handler(struct net_device *ndev) 4766 { 4767 struct rtl8169_private *tp = netdev_priv(ndev); 4768 struct device *d = tp_to_dev(tp); 4769 4770 if (netif_carrier_ok(ndev)) { 4771 rtl_link_chg_patch(tp); 4772 pm_request_resume(d); 4773 netif_wake_queue(tp->dev); 4774 } else { 4775 /* In few cases rx is broken after link-down otherwise */ 4776 if (rtl_is_8125(tp)) 4777 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4778 pm_runtime_idle(d); 4779 } 4780 4781 phy_print_status(tp->phydev); 4782 } 4783 4784 static int r8169_phy_connect(struct rtl8169_private *tp) 4785 { 4786 struct phy_device *phydev = tp->phydev; 4787 phy_interface_t phy_mode; 4788 int ret; 4789 4790 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4791 PHY_INTERFACE_MODE_MII; 4792 4793 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4794 phy_mode); 4795 if (ret) 4796 return ret; 4797 4798 if (!tp->supports_gmii) 4799 phy_set_max_speed(phydev, SPEED_100); 4800 4801 phy_attached_info(phydev); 4802 4803 return 0; 4804 } 4805 4806 static void rtl8169_down(struct rtl8169_private *tp) 4807 { 4808 /* Clear all task flags */ 4809 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4810 4811 phy_stop(tp->phydev); 4812 4813 rtl8169_update_counters(tp); 4814 4815 pci_clear_master(tp->pci_dev); 4816 rtl_pci_commit(tp); 4817 4818 rtl8169_cleanup(tp); 4819 rtl_disable_exit_l1(tp); 4820 rtl_prepare_power_down(tp); 4821 4822 if (tp->dash_type != RTL_DASH_NONE) 4823 rtl8168_driver_stop(tp); 4824 } 4825 4826 static void rtl8169_up(struct rtl8169_private *tp) 4827 { 4828 if (tp->dash_type != RTL_DASH_NONE) 4829 rtl8168_driver_start(tp); 4830 4831 pci_set_master(tp->pci_dev); 4832 phy_init_hw(tp->phydev); 4833 phy_resume(tp->phydev); 4834 rtl8169_init_phy(tp); 4835 napi_enable(&tp->napi); 4836 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4837 rtl_reset_work(tp); 4838 4839 phy_start(tp->phydev); 4840 } 4841 4842 static int rtl8169_close(struct net_device *dev) 4843 { 4844 struct rtl8169_private *tp = netdev_priv(dev); 4845 struct pci_dev *pdev = tp->pci_dev; 4846 4847 pm_runtime_get_sync(&pdev->dev); 4848 4849 netif_stop_queue(dev); 4850 rtl8169_down(tp); 4851 rtl8169_rx_clear(tp); 4852 4853 cancel_work(&tp->wk.work); 4854 4855 free_irq(tp->irq, tp); 4856 4857 phy_disconnect(tp->phydev); 4858 4859 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4860 tp->RxPhyAddr); 4861 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4862 tp->TxPhyAddr); 4863 tp->TxDescArray = NULL; 4864 tp->RxDescArray = NULL; 4865 4866 pm_runtime_put_sync(&pdev->dev); 4867 4868 return 0; 4869 } 4870 4871 #ifdef CONFIG_NET_POLL_CONTROLLER 4872 static void rtl8169_netpoll(struct net_device *dev) 4873 { 4874 struct rtl8169_private *tp = netdev_priv(dev); 4875 4876 rtl8169_interrupt(tp->irq, tp); 4877 } 4878 #endif 4879 4880 static int rtl_open(struct net_device *dev) 4881 { 4882 struct rtl8169_private *tp = netdev_priv(dev); 4883 struct pci_dev *pdev = tp->pci_dev; 4884 unsigned long irqflags; 4885 int retval = -ENOMEM; 4886 4887 pm_runtime_get_sync(&pdev->dev); 4888 4889 /* 4890 * Rx and Tx descriptors needs 256 bytes alignment. 4891 * dma_alloc_coherent provides more. 4892 */ 4893 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4894 &tp->TxPhyAddr, GFP_KERNEL); 4895 if (!tp->TxDescArray) 4896 goto out; 4897 4898 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4899 &tp->RxPhyAddr, GFP_KERNEL); 4900 if (!tp->RxDescArray) 4901 goto err_free_tx_0; 4902 4903 retval = rtl8169_init_ring(tp); 4904 if (retval < 0) 4905 goto err_free_rx_1; 4906 4907 rtl_request_firmware(tp); 4908 4909 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4910 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4911 if (retval < 0) 4912 goto err_release_fw_2; 4913 4914 retval = r8169_phy_connect(tp); 4915 if (retval) 4916 goto err_free_irq; 4917 4918 rtl8169_up(tp); 4919 rtl8169_init_counter_offsets(tp); 4920 netif_start_queue(dev); 4921 out: 4922 pm_runtime_put_sync(&pdev->dev); 4923 4924 return retval; 4925 4926 err_free_irq: 4927 free_irq(tp->irq, tp); 4928 err_release_fw_2: 4929 rtl_release_firmware(tp); 4930 rtl8169_rx_clear(tp); 4931 err_free_rx_1: 4932 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4933 tp->RxPhyAddr); 4934 tp->RxDescArray = NULL; 4935 err_free_tx_0: 4936 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4937 tp->TxPhyAddr); 4938 tp->TxDescArray = NULL; 4939 goto out; 4940 } 4941 4942 static void 4943 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4944 { 4945 struct rtl8169_private *tp = netdev_priv(dev); 4946 struct pci_dev *pdev = tp->pci_dev; 4947 struct rtl8169_counters *counters = tp->counters; 4948 4949 pm_runtime_get_noresume(&pdev->dev); 4950 4951 netdev_stats_to_stats64(stats, &dev->stats); 4952 dev_fetch_sw_netstats(stats, dev->tstats); 4953 4954 /* 4955 * Fetch additional counter values missing in stats collected by driver 4956 * from tally counters. 4957 */ 4958 if (pm_runtime_active(&pdev->dev)) 4959 rtl8169_update_counters(tp); 4960 4961 /* 4962 * Subtract values fetched during initalization. 4963 * See rtl8169_init_counter_offsets for a description why we do that. 4964 */ 4965 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4966 le64_to_cpu(tp->tc_offset.tx_errors); 4967 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4968 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4969 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4970 le16_to_cpu(tp->tc_offset.tx_aborted); 4971 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4972 le16_to_cpu(tp->tc_offset.rx_missed); 4973 4974 pm_runtime_put_noidle(&pdev->dev); 4975 } 4976 4977 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4978 { 4979 netif_device_detach(tp->dev); 4980 4981 if (netif_running(tp->dev)) 4982 rtl8169_down(tp); 4983 } 4984 4985 static int rtl8169_runtime_resume(struct device *dev) 4986 { 4987 struct rtl8169_private *tp = dev_get_drvdata(dev); 4988 4989 rtl_rar_set(tp, tp->dev->dev_addr); 4990 __rtl8169_set_wol(tp, tp->saved_wolopts); 4991 4992 if (tp->TxDescArray) 4993 rtl8169_up(tp); 4994 4995 netif_device_attach(tp->dev); 4996 4997 return 0; 4998 } 4999 5000 static int rtl8169_suspend(struct device *device) 5001 { 5002 struct rtl8169_private *tp = dev_get_drvdata(device); 5003 5004 rtnl_lock(); 5005 rtl8169_net_suspend(tp); 5006 if (!device_may_wakeup(tp_to_dev(tp))) 5007 clk_disable_unprepare(tp->clk); 5008 rtnl_unlock(); 5009 5010 return 0; 5011 } 5012 5013 static int rtl8169_resume(struct device *device) 5014 { 5015 struct rtl8169_private *tp = dev_get_drvdata(device); 5016 5017 if (!device_may_wakeup(tp_to_dev(tp))) 5018 clk_prepare_enable(tp->clk); 5019 5020 /* Reportedly at least Asus X453MA truncates packets otherwise */ 5021 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 5022 rtl_init_rxcfg(tp); 5023 5024 return rtl8169_runtime_resume(device); 5025 } 5026 5027 static int rtl8169_runtime_suspend(struct device *device) 5028 { 5029 struct rtl8169_private *tp = dev_get_drvdata(device); 5030 5031 if (!tp->TxDescArray) { 5032 netif_device_detach(tp->dev); 5033 return 0; 5034 } 5035 5036 rtnl_lock(); 5037 __rtl8169_set_wol(tp, WAKE_PHY); 5038 rtl8169_net_suspend(tp); 5039 rtnl_unlock(); 5040 5041 return 0; 5042 } 5043 5044 static int rtl8169_runtime_idle(struct device *device) 5045 { 5046 struct rtl8169_private *tp = dev_get_drvdata(device); 5047 5048 if (tp->dash_enabled) 5049 return -EBUSY; 5050 5051 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5052 pm_schedule_suspend(device, 10000); 5053 5054 return -EBUSY; 5055 } 5056 5057 static const struct dev_pm_ops rtl8169_pm_ops = { 5058 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5059 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5060 rtl8169_runtime_idle) 5061 }; 5062 5063 static void rtl_shutdown(struct pci_dev *pdev) 5064 { 5065 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5066 5067 rtnl_lock(); 5068 rtl8169_net_suspend(tp); 5069 rtnl_unlock(); 5070 5071 /* Restore original MAC address */ 5072 rtl_rar_set(tp, tp->dev->perm_addr); 5073 5074 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5075 pci_wake_from_d3(pdev, tp->saved_wolopts); 5076 pci_set_power_state(pdev, PCI_D3hot); 5077 } 5078 } 5079 5080 static void rtl_remove_one(struct pci_dev *pdev) 5081 { 5082 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5083 5084 if (pci_dev_run_wake(pdev)) 5085 pm_runtime_get_noresume(&pdev->dev); 5086 5087 cancel_work_sync(&tp->wk.work); 5088 5089 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5090 r8169_remove_leds(tp->leds); 5091 5092 unregister_netdev(tp->dev); 5093 5094 if (tp->dash_type != RTL_DASH_NONE) 5095 rtl8168_driver_stop(tp); 5096 5097 rtl_release_firmware(tp); 5098 5099 /* restore original MAC address */ 5100 rtl_rar_set(tp, tp->dev->perm_addr); 5101 } 5102 5103 static const struct net_device_ops rtl_netdev_ops = { 5104 .ndo_open = rtl_open, 5105 .ndo_stop = rtl8169_close, 5106 .ndo_get_stats64 = rtl8169_get_stats64, 5107 .ndo_start_xmit = rtl8169_start_xmit, 5108 .ndo_features_check = rtl8169_features_check, 5109 .ndo_tx_timeout = rtl8169_tx_timeout, 5110 .ndo_validate_addr = eth_validate_addr, 5111 .ndo_change_mtu = rtl8169_change_mtu, 5112 .ndo_fix_features = rtl8169_fix_features, 5113 .ndo_set_features = rtl8169_set_features, 5114 .ndo_set_mac_address = rtl_set_mac_address, 5115 .ndo_eth_ioctl = phy_do_ioctl_running, 5116 .ndo_set_rx_mode = rtl_set_rx_mode, 5117 #ifdef CONFIG_NET_POLL_CONTROLLER 5118 .ndo_poll_controller = rtl8169_netpoll, 5119 #endif 5120 5121 }; 5122 5123 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5124 { 5125 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5126 5127 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5128 tp->irq_mask |= SYSErr | RxFIFOOver; 5129 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5130 /* special workaround needed */ 5131 tp->irq_mask |= RxFIFOOver; 5132 } 5133 5134 static int rtl_alloc_irq(struct rtl8169_private *tp) 5135 { 5136 unsigned int flags; 5137 5138 switch (tp->mac_version) { 5139 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5140 rtl_unlock_config_regs(tp); 5141 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5142 rtl_lock_config_regs(tp); 5143 fallthrough; 5144 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5145 flags = PCI_IRQ_INTX; 5146 break; 5147 default: 5148 flags = PCI_IRQ_ALL_TYPES; 5149 break; 5150 } 5151 5152 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5153 } 5154 5155 static void rtl_read_mac_address(struct rtl8169_private *tp, 5156 u8 mac_addr[ETH_ALEN]) 5157 { 5158 /* Get MAC address */ 5159 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5160 u32 value; 5161 5162 value = rtl_eri_read(tp, 0xe0); 5163 put_unaligned_le32(value, mac_addr); 5164 value = rtl_eri_read(tp, 0xe4); 5165 put_unaligned_le16(value, mac_addr + 4); 5166 } else if (rtl_is_8125(tp)) { 5167 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5168 } 5169 } 5170 5171 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5172 { 5173 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5174 } 5175 5176 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5177 { 5178 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5179 } 5180 5181 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5182 { 5183 struct rtl8169_private *tp = mii_bus->priv; 5184 5185 if (phyaddr > 0) 5186 return -ENODEV; 5187 5188 return rtl_readphy(tp, phyreg); 5189 } 5190 5191 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5192 int phyreg, u16 val) 5193 { 5194 struct rtl8169_private *tp = mii_bus->priv; 5195 5196 if (phyaddr > 0) 5197 return -ENODEV; 5198 5199 rtl_writephy(tp, phyreg, val); 5200 5201 return 0; 5202 } 5203 5204 static int r8169_mdio_register(struct rtl8169_private *tp) 5205 { 5206 struct pci_dev *pdev = tp->pci_dev; 5207 struct mii_bus *new_bus; 5208 int ret; 5209 5210 /* On some boards with this chip version the BIOS is buggy and misses 5211 * to reset the PHY page selector. This results in the PHY ID read 5212 * accessing registers on a different page, returning a more or 5213 * less random value. Fix this by resetting the page selector first. 5214 */ 5215 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5216 tp->mac_version == RTL_GIGA_MAC_VER_26) 5217 r8169_mdio_write(tp, 0x1f, 0); 5218 5219 new_bus = devm_mdiobus_alloc(&pdev->dev); 5220 if (!new_bus) 5221 return -ENOMEM; 5222 5223 new_bus->name = "r8169"; 5224 new_bus->priv = tp; 5225 new_bus->parent = &pdev->dev; 5226 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5227 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5228 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5229 5230 new_bus->read = r8169_mdio_read_reg; 5231 new_bus->write = r8169_mdio_write_reg; 5232 5233 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5234 if (ret) 5235 return ret; 5236 5237 tp->phydev = mdiobus_get_phy(new_bus, 0); 5238 if (!tp->phydev) { 5239 return -ENODEV; 5240 } else if (!tp->phydev->drv) { 5241 /* Most chip versions fail with the genphy driver. 5242 * Therefore ensure that the dedicated PHY driver is loaded. 5243 */ 5244 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5245 tp->phydev->phy_id); 5246 return -EUNATCH; 5247 } 5248 5249 tp->phydev->mac_managed_pm = true; 5250 if (rtl_supports_eee(tp)) 5251 phy_support_eee(tp->phydev); 5252 phy_support_asym_pause(tp->phydev); 5253 5254 /* PHY will be woken up in rtl_open() */ 5255 phy_suspend(tp->phydev); 5256 5257 return 0; 5258 } 5259 5260 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5261 { 5262 rtl_enable_rxdvgate(tp); 5263 5264 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5265 msleep(1); 5266 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5267 5268 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5269 r8168g_wait_ll_share_fifo_ready(tp); 5270 5271 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5272 r8168g_wait_ll_share_fifo_ready(tp); 5273 } 5274 5275 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5276 { 5277 rtl_enable_rxdvgate(tp); 5278 5279 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5280 msleep(1); 5281 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5282 5283 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5284 r8168g_wait_ll_share_fifo_ready(tp); 5285 5286 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5287 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5288 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5289 r8168g_wait_ll_share_fifo_ready(tp); 5290 } 5291 5292 static void rtl_hw_initialize(struct rtl8169_private *tp) 5293 { 5294 switch (tp->mac_version) { 5295 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5296 rtl8168ep_stop_cmac(tp); 5297 fallthrough; 5298 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5299 rtl_hw_init_8168g(tp); 5300 break; 5301 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 5302 rtl_hw_init_8125(tp); 5303 break; 5304 default: 5305 break; 5306 } 5307 } 5308 5309 static int rtl_jumbo_max(struct rtl8169_private *tp) 5310 { 5311 /* Non-GBit versions don't support jumbo frames */ 5312 if (!tp->supports_gmii) 5313 return 0; 5314 5315 switch (tp->mac_version) { 5316 /* RTL8169 */ 5317 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5318 return JUMBO_7K; 5319 /* RTL8168b */ 5320 case RTL_GIGA_MAC_VER_11: 5321 case RTL_GIGA_MAC_VER_17: 5322 return JUMBO_4K; 5323 /* RTL8168c */ 5324 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5325 return JUMBO_6K; 5326 default: 5327 return JUMBO_9K; 5328 } 5329 } 5330 5331 static void rtl_init_mac_address(struct rtl8169_private *tp) 5332 { 5333 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5334 struct net_device *dev = tp->dev; 5335 int rc; 5336 5337 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5338 if (!rc) 5339 goto done; 5340 5341 rtl_read_mac_address(tp, mac_addr); 5342 if (is_valid_ether_addr(mac_addr)) 5343 goto done; 5344 5345 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5346 if (is_valid_ether_addr(mac_addr)) 5347 goto done; 5348 5349 eth_random_addr(mac_addr); 5350 dev->addr_assign_type = NET_ADDR_RANDOM; 5351 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5352 done: 5353 eth_hw_addr_set(dev, mac_addr); 5354 rtl_rar_set(tp, mac_addr); 5355 } 5356 5357 /* register is set if system vendor successfully tested ASPM 1.2 */ 5358 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5359 { 5360 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5361 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5362 return true; 5363 5364 return false; 5365 } 5366 5367 static umode_t r8169_hwmon_is_visible(const void *drvdata, 5368 enum hwmon_sensor_types type, 5369 u32 attr, int channel) 5370 { 5371 return 0444; 5372 } 5373 5374 static int r8169_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 5375 u32 attr, int channel, long *val) 5376 { 5377 struct rtl8169_private *tp = dev_get_drvdata(dev); 5378 int val_raw; 5379 5380 val_raw = phy_read_paged(tp->phydev, 0xbd8, 0x12) & 0x3ff; 5381 if (val_raw >= 512) 5382 val_raw -= 1024; 5383 5384 *val = 1000 * val_raw / 2; 5385 5386 return 0; 5387 } 5388 5389 static const struct hwmon_ops r8169_hwmon_ops = { 5390 .is_visible = r8169_hwmon_is_visible, 5391 .read = r8169_hwmon_read, 5392 }; 5393 5394 static const struct hwmon_channel_info * const r8169_hwmon_info[] = { 5395 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 5396 NULL 5397 }; 5398 5399 static const struct hwmon_chip_info r8169_hwmon_chip_info = { 5400 .ops = &r8169_hwmon_ops, 5401 .info = r8169_hwmon_info, 5402 }; 5403 5404 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5405 { 5406 struct rtl8169_private *tp; 5407 int jumbo_max, region, rc; 5408 enum mac_version chipset; 5409 struct net_device *dev; 5410 u32 txconfig; 5411 u16 xid; 5412 5413 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5414 if (!dev) 5415 return -ENOMEM; 5416 5417 SET_NETDEV_DEV(dev, &pdev->dev); 5418 dev->netdev_ops = &rtl_netdev_ops; 5419 tp = netdev_priv(dev); 5420 tp->dev = dev; 5421 tp->pci_dev = pdev; 5422 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5423 tp->ocp_base = OCP_STD_PHY_BASE; 5424 5425 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5426 raw_spin_lock_init(&tp->config25_lock); 5427 raw_spin_lock_init(&tp->mac_ocp_lock); 5428 mutex_init(&tp->led_lock); 5429 5430 /* Get the *optional* external "ether_clk" used on some boards */ 5431 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5432 if (IS_ERR(tp->clk)) 5433 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5434 5435 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5436 rc = pcim_enable_device(pdev); 5437 if (rc < 0) 5438 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5439 5440 if (pcim_set_mwi(pdev) < 0) 5441 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5442 5443 /* use first MMIO region */ 5444 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5445 if (region < 0) 5446 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5447 5448 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5449 if (rc < 0) 5450 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5451 5452 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5453 5454 txconfig = RTL_R32(tp, TxConfig); 5455 if (txconfig == ~0U) 5456 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5457 5458 xid = (txconfig >> 20) & 0xfcf; 5459 5460 /* Identify chip attached to board */ 5461 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5462 if (chipset == RTL_GIGA_MAC_NONE) 5463 return dev_err_probe(&pdev->dev, -ENODEV, 5464 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5465 xid); 5466 tp->mac_version = chipset; 5467 5468 /* Disable ASPM L1 as that cause random device stop working 5469 * problems as well as full system hangs for some PCIe devices users. 5470 */ 5471 if (rtl_aspm_is_safe(tp)) 5472 rc = 0; 5473 else 5474 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5475 tp->aspm_manageable = !rc; 5476 5477 tp->dash_type = rtl_get_dash_type(tp); 5478 tp->dash_enabled = rtl_dash_is_enabled(tp); 5479 5480 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5481 5482 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5483 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5484 dev->features |= NETIF_F_HIGHDMA; 5485 5486 rtl_init_rxcfg(tp); 5487 5488 rtl8169_irq_mask_and_ack(tp); 5489 5490 rtl_hw_initialize(tp); 5491 5492 rtl_hw_reset(tp); 5493 5494 rc = rtl_alloc_irq(tp); 5495 if (rc < 0) 5496 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5497 5498 tp->irq = pci_irq_vector(pdev, 0); 5499 5500 INIT_WORK(&tp->wk.work, rtl_task); 5501 5502 rtl_init_mac_address(tp); 5503 5504 dev->ethtool_ops = &rtl8169_ethtool_ops; 5505 5506 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5507 5508 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5509 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5510 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5511 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5512 5513 /* 5514 * Pretend we are using VLANs; This bypasses a nasty bug where 5515 * Interrupts stop flowing on high load on 8110SCd controllers. 5516 */ 5517 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5518 /* Disallow toggling */ 5519 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5520 5521 if (rtl_chip_supports_csum_v2(tp)) 5522 dev->hw_features |= NETIF_F_IPV6_CSUM; 5523 5524 dev->features |= dev->hw_features; 5525 5526 /* There has been a number of reports that using SG/TSO results in 5527 * tx timeouts. However for a lot of people SG/TSO works fine. 5528 * Therefore disable both features by default, but allow users to 5529 * enable them. Use at own risk! 5530 */ 5531 if (rtl_chip_supports_csum_v2(tp)) { 5532 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5533 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5534 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5535 } else { 5536 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5537 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5538 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5539 } 5540 5541 dev->hw_features |= NETIF_F_RXALL; 5542 dev->hw_features |= NETIF_F_RXFCS; 5543 5544 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5545 5546 netdev_sw_irq_coalesce_default_on(dev); 5547 5548 /* configure chip for default features */ 5549 rtl8169_set_features(dev, dev->features); 5550 5551 if (!tp->dash_enabled) { 5552 rtl_set_d3_pll_down(tp, true); 5553 } else { 5554 rtl_set_d3_pll_down(tp, false); 5555 dev->ethtool->wol_enabled = 1; 5556 } 5557 5558 jumbo_max = rtl_jumbo_max(tp); 5559 if (jumbo_max) 5560 dev->max_mtu = jumbo_max; 5561 5562 rtl_set_irq_mask(tp); 5563 5564 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5565 5566 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5567 &tp->counters_phys_addr, 5568 GFP_KERNEL); 5569 if (!tp->counters) 5570 return -ENOMEM; 5571 5572 pci_set_drvdata(pdev, tp); 5573 5574 rc = r8169_mdio_register(tp); 5575 if (rc) 5576 return rc; 5577 5578 /* The temperature sensor is available from RTl8125B */ 5579 if (IS_REACHABLE(CONFIG_HWMON) && tp->mac_version >= RTL_GIGA_MAC_VER_63) 5580 /* ignore errors */ 5581 devm_hwmon_device_register_with_info(&pdev->dev, "nic_temp", tp, 5582 &r8169_hwmon_chip_info, 5583 NULL); 5584 rc = register_netdev(dev); 5585 if (rc) 5586 return rc; 5587 5588 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5589 if (rtl_is_8125(tp)) 5590 tp->leds = rtl8125_init_leds(dev); 5591 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5592 tp->leds = rtl8168_init_leds(dev); 5593 } 5594 5595 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5596 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5597 5598 if (jumbo_max) 5599 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5600 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5601 "ok" : "ko"); 5602 5603 if (tp->dash_type != RTL_DASH_NONE) { 5604 netdev_info(dev, "DASH %s\n", 5605 tp->dash_enabled ? "enabled" : "disabled"); 5606 rtl8168_driver_start(tp); 5607 } 5608 5609 if (pci_dev_run_wake(pdev)) 5610 pm_runtime_put_sync(&pdev->dev); 5611 5612 return 0; 5613 } 5614 5615 static struct pci_driver rtl8169_pci_driver = { 5616 .name = KBUILD_MODNAME, 5617 .id_table = rtl8169_pci_tbl, 5618 .probe = rtl_init_one, 5619 .remove = rtl_remove_one, 5620 .shutdown = rtl_shutdown, 5621 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5622 }; 5623 5624 module_pci_driver(rtl8169_pci_driver); 5625