1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 59 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 60 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 61 62 #define R8169_REGS_SIZE 256 63 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 64 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 65 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 66 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 67 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 68 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 69 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 70 71 #define OCP_STD_PHY_BASE 0xa400 72 73 #define RTL_CFG_NO_GBIT 1 74 75 /* write/read MMIO register */ 76 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 79 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 80 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 81 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 82 83 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 84 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 88 static const struct { 89 const char *name; 90 const char *fw_name; 91 } rtl_chip_infos[] = { 92 /* PCI devices. */ 93 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 94 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 95 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 96 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 97 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 98 /* PCI-E devices. */ 99 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 100 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 102 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 103 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 104 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 105 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 106 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 107 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 108 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 109 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 112 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 114 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 115 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 116 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 117 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 118 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 119 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 120 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 121 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 122 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 123 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 124 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 125 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 126 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 127 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 128 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 129 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 130 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 131 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 132 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 133 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 134 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 135 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 136 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 137 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 138 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 139 }; 140 141 static const struct pci_device_id rtl8169_pci_tbl[] = { 142 { PCI_VDEVICE(REALTEK, 0x2502) }, 143 { PCI_VDEVICE(REALTEK, 0x2600) }, 144 { PCI_VDEVICE(REALTEK, 0x8129) }, 145 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 146 { PCI_VDEVICE(REALTEK, 0x8161) }, 147 { PCI_VDEVICE(REALTEK, 0x8162) }, 148 { PCI_VDEVICE(REALTEK, 0x8167) }, 149 { PCI_VDEVICE(REALTEK, 0x8168) }, 150 { PCI_VDEVICE(NCUBE, 0x8168) }, 151 { PCI_VDEVICE(REALTEK, 0x8169) }, 152 { PCI_VENDOR_ID_DLINK, 0x4300, 153 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 154 { PCI_VDEVICE(DLINK, 0x4300) }, 155 { PCI_VDEVICE(DLINK, 0x4302) }, 156 { PCI_VDEVICE(AT, 0xc107) }, 157 { PCI_VDEVICE(USR, 0x0116) }, 158 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 159 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 160 { PCI_VDEVICE(REALTEK, 0x8125) }, 161 { PCI_VDEVICE(REALTEK, 0x3000) }, 162 {} 163 }; 164 165 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 166 167 enum rtl_registers { 168 MAC0 = 0, /* Ethernet hardware address. */ 169 MAC4 = 4, 170 MAR0 = 8, /* Multicast filter. */ 171 CounterAddrLow = 0x10, 172 CounterAddrHigh = 0x14, 173 TxDescStartAddrLow = 0x20, 174 TxDescStartAddrHigh = 0x24, 175 TxHDescStartAddrLow = 0x28, 176 TxHDescStartAddrHigh = 0x2c, 177 FLASH = 0x30, 178 ERSR = 0x36, 179 ChipCmd = 0x37, 180 TxPoll = 0x38, 181 IntrMask = 0x3c, 182 IntrStatus = 0x3e, 183 184 TxConfig = 0x40, 185 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 186 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 187 188 RxConfig = 0x44, 189 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 190 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 191 #define RXCFG_FIFO_SHIFT 13 192 /* No threshold before first PCI xfer */ 193 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 194 #define RX_EARLY_OFF (1 << 11) 195 #define RXCFG_DMA_SHIFT 8 196 /* Unlimited maximum PCI burst. */ 197 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 198 199 Cfg9346 = 0x50, 200 Config0 = 0x51, 201 Config1 = 0x52, 202 Config2 = 0x53, 203 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 204 205 Config3 = 0x54, 206 Config4 = 0x55, 207 Config5 = 0x56, 208 PHYAR = 0x60, 209 PHYstatus = 0x6c, 210 RxMaxSize = 0xda, 211 CPlusCmd = 0xe0, 212 IntrMitigate = 0xe2, 213 214 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 215 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 216 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 217 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 218 219 #define RTL_COALESCE_T_MAX 0x0fU 220 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 221 222 RxDescAddrLow = 0xe4, 223 RxDescAddrHigh = 0xe8, 224 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 225 226 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 227 228 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 229 230 #define TxPacketMax (8064 >> 7) 231 #define EarlySize 0x27 232 233 FuncEvent = 0xf0, 234 FuncEventMask = 0xf4, 235 FuncPresetState = 0xf8, 236 IBCR0 = 0xf8, 237 IBCR2 = 0xf9, 238 IBIMR0 = 0xfa, 239 IBISR0 = 0xfb, 240 FuncForceEvent = 0xfc, 241 }; 242 243 enum rtl8168_8101_registers { 244 CSIDR = 0x64, 245 CSIAR = 0x68, 246 #define CSIAR_FLAG 0x80000000 247 #define CSIAR_WRITE_CMD 0x80000000 248 #define CSIAR_BYTE_ENABLE 0x0000f000 249 #define CSIAR_ADDR_MASK 0x00000fff 250 PMCH = 0x6f, 251 #define D3COLD_NO_PLL_DOWN BIT(7) 252 #define D3HOT_NO_PLL_DOWN BIT(6) 253 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 254 EPHYAR = 0x80, 255 #define EPHYAR_FLAG 0x80000000 256 #define EPHYAR_WRITE_CMD 0x80000000 257 #define EPHYAR_REG_MASK 0x1f 258 #define EPHYAR_REG_SHIFT 16 259 #define EPHYAR_DATA_MASK 0xffff 260 DLLPR = 0xd0, 261 #define PFM_EN (1 << 6) 262 #define TX_10M_PS_EN (1 << 7) 263 DBG_REG = 0xd1, 264 #define FIX_NAK_1 (1 << 4) 265 #define FIX_NAK_2 (1 << 3) 266 TWSI = 0xd2, 267 MCU = 0xd3, 268 #define NOW_IS_OOB (1 << 7) 269 #define TX_EMPTY (1 << 5) 270 #define RX_EMPTY (1 << 4) 271 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 272 #define EN_NDP (1 << 3) 273 #define EN_OOB_RESET (1 << 2) 274 #define LINK_LIST_RDY (1 << 1) 275 EFUSEAR = 0xdc, 276 #define EFUSEAR_FLAG 0x80000000 277 #define EFUSEAR_WRITE_CMD 0x80000000 278 #define EFUSEAR_READ_CMD 0x00000000 279 #define EFUSEAR_REG_MASK 0x03ff 280 #define EFUSEAR_REG_SHIFT 8 281 #define EFUSEAR_DATA_MASK 0xff 282 MISC_1 = 0xf2, 283 #define PFM_D3COLD_EN (1 << 6) 284 }; 285 286 enum rtl8168_registers { 287 LED_FREQ = 0x1a, 288 EEE_LED = 0x1b, 289 ERIDR = 0x70, 290 ERIAR = 0x74, 291 #define ERIAR_FLAG 0x80000000 292 #define ERIAR_WRITE_CMD 0x80000000 293 #define ERIAR_READ_CMD 0x00000000 294 #define ERIAR_ADDR_BYTE_ALIGN 4 295 #define ERIAR_TYPE_SHIFT 16 296 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 297 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 298 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 299 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 300 #define ERIAR_MASK_SHIFT 12 301 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 302 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 303 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 304 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 305 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 306 EPHY_RXER_NUM = 0x7c, 307 OCPDR = 0xb0, /* OCP GPHY access */ 308 #define OCPDR_WRITE_CMD 0x80000000 309 #define OCPDR_READ_CMD 0x00000000 310 #define OCPDR_REG_MASK 0x7f 311 #define OCPDR_GPHY_REG_SHIFT 16 312 #define OCPDR_DATA_MASK 0xffff 313 OCPAR = 0xb4, 314 #define OCPAR_FLAG 0x80000000 315 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 316 #define OCPAR_GPHY_READ_CMD 0x0000f060 317 GPHY_OCP = 0xb8, 318 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 319 MISC = 0xf0, /* 8168e only. */ 320 #define TXPLA_RST (1 << 29) 321 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 322 #define PWM_EN (1 << 22) 323 #define RXDV_GATED_EN (1 << 19) 324 #define EARLY_TALLY_EN (1 << 16) 325 }; 326 327 enum rtl8125_registers { 328 IntrMask_8125 = 0x38, 329 IntrStatus_8125 = 0x3c, 330 TxPoll_8125 = 0x90, 331 MAC0_BKP = 0x19e0, 332 EEE_TXIDLE_TIMER_8125 = 0x6048, 333 }; 334 335 #define RX_VLAN_INNER_8125 BIT(22) 336 #define RX_VLAN_OUTER_8125 BIT(23) 337 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 338 339 #define RX_FETCH_DFLT_8125 (8 << 27) 340 341 enum rtl_register_content { 342 /* InterruptStatusBits */ 343 SYSErr = 0x8000, 344 PCSTimeout = 0x4000, 345 SWInt = 0x0100, 346 TxDescUnavail = 0x0080, 347 RxFIFOOver = 0x0040, 348 LinkChg = 0x0020, 349 RxOverflow = 0x0010, 350 TxErr = 0x0008, 351 TxOK = 0x0004, 352 RxErr = 0x0002, 353 RxOK = 0x0001, 354 355 /* RxStatusDesc */ 356 RxRWT = (1 << 22), 357 RxRES = (1 << 21), 358 RxRUNT = (1 << 20), 359 RxCRC = (1 << 19), 360 361 /* ChipCmdBits */ 362 StopReq = 0x80, 363 CmdReset = 0x10, 364 CmdRxEnb = 0x08, 365 CmdTxEnb = 0x04, 366 RxBufEmpty = 0x01, 367 368 /* TXPoll register p.5 */ 369 HPQ = 0x80, /* Poll cmd on the high prio queue */ 370 NPQ = 0x40, /* Poll cmd on the low prio queue */ 371 FSWInt = 0x01, /* Forced software interrupt */ 372 373 /* Cfg9346Bits */ 374 Cfg9346_Lock = 0x00, 375 Cfg9346_Unlock = 0xc0, 376 377 /* rx_mode_bits */ 378 AcceptErr = 0x20, 379 AcceptRunt = 0x10, 380 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 381 AcceptBroadcast = 0x08, 382 AcceptMulticast = 0x04, 383 AcceptMyPhys = 0x02, 384 AcceptAllPhys = 0x01, 385 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 386 #define RX_CONFIG_ACCEPT_MASK 0x3f 387 388 /* TxConfigBits */ 389 TxInterFrameGapShift = 24, 390 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 391 392 /* Config1 register p.24 */ 393 LEDS1 = (1 << 7), 394 LEDS0 = (1 << 6), 395 Speed_down = (1 << 4), 396 MEMMAP = (1 << 3), 397 IOMAP = (1 << 2), 398 VPD = (1 << 1), 399 PMEnable = (1 << 0), /* Power Management Enable */ 400 401 /* Config2 register p. 25 */ 402 ClkReqEn = (1 << 7), /* Clock Request Enable */ 403 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 404 PCI_Clock_66MHz = 0x01, 405 PCI_Clock_33MHz = 0x00, 406 407 /* Config3 register p.25 */ 408 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 409 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 410 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 411 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 412 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 413 414 /* Config4 register */ 415 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 416 417 /* Config5 register p.27 */ 418 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 419 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 420 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 421 Spi_en = (1 << 3), 422 LanWake = (1 << 1), /* LanWake enable/disable */ 423 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 424 ASPM_en = (1 << 0), /* ASPM enable */ 425 426 /* CPlusCmd p.31 */ 427 EnableBist = (1 << 15), // 8168 8101 428 Mac_dbgo_oe = (1 << 14), // 8168 8101 429 EnAnaPLL = (1 << 14), // 8169 430 Normal_mode = (1 << 13), // unused 431 Force_half_dup = (1 << 12), // 8168 8101 432 Force_rxflow_en = (1 << 11), // 8168 8101 433 Force_txflow_en = (1 << 10), // 8168 8101 434 Cxpl_dbg_sel = (1 << 9), // 8168 8101 435 ASF = (1 << 8), // 8168 8101 436 PktCntrDisable = (1 << 7), // 8168 8101 437 Mac_dbgo_sel = 0x001c, // 8168 438 RxVlan = (1 << 6), 439 RxChkSum = (1 << 5), 440 PCIDAC = (1 << 4), 441 PCIMulRW = (1 << 3), 442 #define INTT_MASK GENMASK(1, 0) 443 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 444 445 /* rtl8169_PHYstatus */ 446 TBI_Enable = 0x80, 447 TxFlowCtrl = 0x40, 448 RxFlowCtrl = 0x20, 449 _1000bpsF = 0x10, 450 _100bps = 0x08, 451 _10bps = 0x04, 452 LinkStatus = 0x02, 453 FullDup = 0x01, 454 455 /* ResetCounterCommand */ 456 CounterReset = 0x1, 457 458 /* DumpCounterCommand */ 459 CounterDump = 0x8, 460 461 /* magic enable v2 */ 462 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 463 }; 464 465 enum rtl_desc_bit { 466 /* First doubleword. */ 467 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 468 RingEnd = (1 << 30), /* End of descriptor ring */ 469 FirstFrag = (1 << 29), /* First segment of a packet */ 470 LastFrag = (1 << 28), /* Final segment of a packet */ 471 }; 472 473 /* Generic case. */ 474 enum rtl_tx_desc_bit { 475 /* First doubleword. */ 476 TD_LSO = (1 << 27), /* Large Send Offload */ 477 #define TD_MSS_MAX 0x07ffu /* MSS value */ 478 479 /* Second doubleword. */ 480 TxVlanTag = (1 << 17), /* Add VLAN tag */ 481 }; 482 483 /* 8169, 8168b and 810x except 8102e. */ 484 enum rtl_tx_desc_bit_0 { 485 /* First doubleword. */ 486 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 487 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 488 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 489 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 490 }; 491 492 /* 8102e, 8168c and beyond. */ 493 enum rtl_tx_desc_bit_1 { 494 /* First doubleword. */ 495 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 496 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 497 #define GTTCPHO_SHIFT 18 498 #define GTTCPHO_MAX 0x7f 499 500 /* Second doubleword. */ 501 #define TCPHO_SHIFT 18 502 #define TCPHO_MAX 0x3ff 503 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 504 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 505 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 506 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 507 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 508 }; 509 510 enum rtl_rx_desc_bit { 511 /* Rx private */ 512 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 513 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 514 515 #define RxProtoUDP (PID1) 516 #define RxProtoTCP (PID0) 517 #define RxProtoIP (PID1 | PID0) 518 #define RxProtoMask RxProtoIP 519 520 IPFail = (1 << 16), /* IP checksum failed */ 521 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 522 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 523 524 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 525 526 RxVlanTag = (1 << 16), /* VLAN tag available */ 527 }; 528 529 #define RTL_GSO_MAX_SIZE_V1 32000 530 #define RTL_GSO_MAX_SEGS_V1 24 531 #define RTL_GSO_MAX_SIZE_V2 64000 532 #define RTL_GSO_MAX_SEGS_V2 64 533 534 struct TxDesc { 535 __le32 opts1; 536 __le32 opts2; 537 __le64 addr; 538 }; 539 540 struct RxDesc { 541 __le32 opts1; 542 __le32 opts2; 543 __le64 addr; 544 }; 545 546 struct ring_info { 547 struct sk_buff *skb; 548 u32 len; 549 }; 550 551 struct rtl8169_counters { 552 __le64 tx_packets; 553 __le64 rx_packets; 554 __le64 tx_errors; 555 __le32 rx_errors; 556 __le16 rx_missed; 557 __le16 align_errors; 558 __le32 tx_one_collision; 559 __le32 tx_multi_collision; 560 __le64 rx_unicast; 561 __le64 rx_broadcast; 562 __le32 rx_multicast; 563 __le16 tx_aborted; 564 __le16 tx_underun; 565 }; 566 567 struct rtl8169_tc_offsets { 568 bool inited; 569 __le64 tx_errors; 570 __le32 tx_multi_collision; 571 __le16 tx_aborted; 572 __le16 rx_missed; 573 }; 574 575 enum rtl_flag { 576 RTL_FLAG_TASK_ENABLED = 0, 577 RTL_FLAG_TASK_RESET_PENDING, 578 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 579 RTL_FLAG_TASK_TX_TIMEOUT, 580 RTL_FLAG_MAX 581 }; 582 583 enum rtl_dash_type { 584 RTL_DASH_NONE, 585 RTL_DASH_DP, 586 RTL_DASH_EP, 587 }; 588 589 struct rtl8169_private { 590 void __iomem *mmio_addr; /* memory map physical address */ 591 struct pci_dev *pci_dev; 592 struct net_device *dev; 593 struct phy_device *phydev; 594 struct napi_struct napi; 595 enum mac_version mac_version; 596 enum rtl_dash_type dash_type; 597 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 598 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 599 u32 dirty_tx; 600 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 601 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 602 dma_addr_t TxPhyAddr; 603 dma_addr_t RxPhyAddr; 604 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 605 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 606 u16 cp_cmd; 607 u32 irq_mask; 608 int irq; 609 struct clk *clk; 610 611 struct { 612 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 613 struct work_struct work; 614 } wk; 615 616 raw_spinlock_t config25_lock; 617 raw_spinlock_t mac_ocp_lock; 618 619 raw_spinlock_t cfg9346_usage_lock; 620 int cfg9346_usage_count; 621 622 unsigned supports_gmii:1; 623 unsigned aspm_manageable:1; 624 unsigned dash_enabled:1; 625 dma_addr_t counters_phys_addr; 626 struct rtl8169_counters *counters; 627 struct rtl8169_tc_offsets tc_offset; 628 u32 saved_wolopts; 629 int eee_adv; 630 631 const char *fw_name; 632 struct rtl_fw *rtl_fw; 633 634 u32 ocp_base; 635 }; 636 637 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 638 639 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 640 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 641 MODULE_SOFTDEP("pre: realtek"); 642 MODULE_LICENSE("GPL"); 643 MODULE_FIRMWARE(FIRMWARE_8168D_1); 644 MODULE_FIRMWARE(FIRMWARE_8168D_2); 645 MODULE_FIRMWARE(FIRMWARE_8168E_1); 646 MODULE_FIRMWARE(FIRMWARE_8168E_2); 647 MODULE_FIRMWARE(FIRMWARE_8168E_3); 648 MODULE_FIRMWARE(FIRMWARE_8105E_1); 649 MODULE_FIRMWARE(FIRMWARE_8168F_1); 650 MODULE_FIRMWARE(FIRMWARE_8168F_2); 651 MODULE_FIRMWARE(FIRMWARE_8402_1); 652 MODULE_FIRMWARE(FIRMWARE_8411_1); 653 MODULE_FIRMWARE(FIRMWARE_8411_2); 654 MODULE_FIRMWARE(FIRMWARE_8106E_1); 655 MODULE_FIRMWARE(FIRMWARE_8106E_2); 656 MODULE_FIRMWARE(FIRMWARE_8168G_2); 657 MODULE_FIRMWARE(FIRMWARE_8168G_3); 658 MODULE_FIRMWARE(FIRMWARE_8168H_2); 659 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 660 MODULE_FIRMWARE(FIRMWARE_8107E_2); 661 MODULE_FIRMWARE(FIRMWARE_8125A_3); 662 MODULE_FIRMWARE(FIRMWARE_8125B_2); 663 664 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 665 { 666 return &tp->pci_dev->dev; 667 } 668 669 static void rtl_lock_config_regs(struct rtl8169_private *tp) 670 { 671 unsigned long flags; 672 673 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 674 if (!--tp->cfg9346_usage_count) 675 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 676 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 677 } 678 679 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 680 { 681 unsigned long flags; 682 683 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 684 if (!tp->cfg9346_usage_count++) 685 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 686 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 687 } 688 689 static void rtl_pci_commit(struct rtl8169_private *tp) 690 { 691 /* Read an arbitrary register to commit a preceding PCI write */ 692 RTL_R8(tp, ChipCmd); 693 } 694 695 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 696 { 697 unsigned long flags; 698 u8 val; 699 700 raw_spin_lock_irqsave(&tp->config25_lock, flags); 701 val = RTL_R8(tp, Config2); 702 RTL_W8(tp, Config2, (val & ~clear) | set); 703 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 704 } 705 706 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 707 { 708 unsigned long flags; 709 u8 val; 710 711 raw_spin_lock_irqsave(&tp->config25_lock, flags); 712 val = RTL_R8(tp, Config5); 713 RTL_W8(tp, Config5, (val & ~clear) | set); 714 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 715 } 716 717 static bool rtl_is_8125(struct rtl8169_private *tp) 718 { 719 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 720 } 721 722 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 723 { 724 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 725 tp->mac_version != RTL_GIGA_MAC_VER_39 && 726 tp->mac_version <= RTL_GIGA_MAC_VER_53; 727 } 728 729 static bool rtl_supports_eee(struct rtl8169_private *tp) 730 { 731 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 732 tp->mac_version != RTL_GIGA_MAC_VER_37 && 733 tp->mac_version != RTL_GIGA_MAC_VER_39; 734 } 735 736 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 737 { 738 int i; 739 740 for (i = 0; i < ETH_ALEN; i++) 741 mac[i] = RTL_R8(tp, reg + i); 742 } 743 744 struct rtl_cond { 745 bool (*check)(struct rtl8169_private *); 746 const char *msg; 747 }; 748 749 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 750 unsigned long usecs, int n, bool high) 751 { 752 int i; 753 754 for (i = 0; i < n; i++) { 755 if (c->check(tp) == high) 756 return true; 757 fsleep(usecs); 758 } 759 760 if (net_ratelimit()) 761 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 762 c->msg, !high, n, usecs); 763 return false; 764 } 765 766 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 767 const struct rtl_cond *c, 768 unsigned long d, int n) 769 { 770 return rtl_loop_wait(tp, c, d, n, true); 771 } 772 773 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 774 const struct rtl_cond *c, 775 unsigned long d, int n) 776 { 777 return rtl_loop_wait(tp, c, d, n, false); 778 } 779 780 #define DECLARE_RTL_COND(name) \ 781 static bool name ## _check(struct rtl8169_private *); \ 782 \ 783 static const struct rtl_cond name = { \ 784 .check = name ## _check, \ 785 .msg = #name \ 786 }; \ 787 \ 788 static bool name ## _check(struct rtl8169_private *tp) 789 790 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 791 { 792 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 793 if (type == ERIAR_OOB && 794 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 795 tp->mac_version == RTL_GIGA_MAC_VER_53)) 796 *cmd |= 0xf70 << 18; 797 } 798 799 DECLARE_RTL_COND(rtl_eriar_cond) 800 { 801 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 802 } 803 804 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 805 u32 val, int type) 806 { 807 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 808 809 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 810 return; 811 812 RTL_W32(tp, ERIDR, val); 813 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 814 RTL_W32(tp, ERIAR, cmd); 815 816 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 817 } 818 819 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 820 u32 val) 821 { 822 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 823 } 824 825 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 826 { 827 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 828 829 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 830 RTL_W32(tp, ERIAR, cmd); 831 832 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 833 RTL_R32(tp, ERIDR) : ~0; 834 } 835 836 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 837 { 838 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 839 } 840 841 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 842 { 843 u32 val = rtl_eri_read(tp, addr); 844 845 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 846 } 847 848 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 849 { 850 rtl_w0w1_eri(tp, addr, p, 0); 851 } 852 853 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 854 { 855 rtl_w0w1_eri(tp, addr, 0, m); 856 } 857 858 static bool rtl_ocp_reg_failure(u32 reg) 859 { 860 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 861 } 862 863 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 864 { 865 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 866 } 867 868 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 869 { 870 if (rtl_ocp_reg_failure(reg)) 871 return; 872 873 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 874 875 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 876 } 877 878 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 879 { 880 if (rtl_ocp_reg_failure(reg)) 881 return 0; 882 883 RTL_W32(tp, GPHY_OCP, reg << 15); 884 885 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 886 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 887 } 888 889 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 890 { 891 if (rtl_ocp_reg_failure(reg)) 892 return; 893 894 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 895 } 896 897 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 898 { 899 unsigned long flags; 900 901 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 902 __r8168_mac_ocp_write(tp, reg, data); 903 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 904 } 905 906 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 907 { 908 if (rtl_ocp_reg_failure(reg)) 909 return 0; 910 911 RTL_W32(tp, OCPDR, reg << 15); 912 913 return RTL_R32(tp, OCPDR); 914 } 915 916 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 917 { 918 unsigned long flags; 919 u16 val; 920 921 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 922 val = __r8168_mac_ocp_read(tp, reg); 923 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 924 925 return val; 926 } 927 928 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 929 u16 set) 930 { 931 unsigned long flags; 932 u16 data; 933 934 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 935 data = __r8168_mac_ocp_read(tp, reg); 936 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 937 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 938 } 939 940 /* Work around a hw issue with RTL8168g PHY, the quirk disables 941 * PHY MCU interrupts before PHY power-down. 942 */ 943 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 944 { 945 switch (tp->mac_version) { 946 case RTL_GIGA_MAC_VER_40: 947 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 948 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 949 else 950 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 951 break; 952 default: 953 break; 954 } 955 }; 956 957 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 958 { 959 if (reg == 0x1f) { 960 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 961 return; 962 } 963 964 if (tp->ocp_base != OCP_STD_PHY_BASE) 965 reg -= 0x10; 966 967 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 968 rtl8168g_phy_suspend_quirk(tp, value); 969 970 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 971 } 972 973 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 974 { 975 if (reg == 0x1f) 976 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 977 978 if (tp->ocp_base != OCP_STD_PHY_BASE) 979 reg -= 0x10; 980 981 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 982 } 983 984 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 985 { 986 if (reg == 0x1f) { 987 tp->ocp_base = value << 4; 988 return; 989 } 990 991 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 992 } 993 994 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 995 { 996 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 997 } 998 999 DECLARE_RTL_COND(rtl_phyar_cond) 1000 { 1001 return RTL_R32(tp, PHYAR) & 0x80000000; 1002 } 1003 1004 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1005 { 1006 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1007 1008 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1009 /* 1010 * According to hardware specs a 20us delay is required after write 1011 * complete indication, but before sending next command. 1012 */ 1013 udelay(20); 1014 } 1015 1016 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1017 { 1018 int value; 1019 1020 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1021 1022 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1023 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1024 1025 /* 1026 * According to hardware specs a 20us delay is required after read 1027 * complete indication, but before sending next command. 1028 */ 1029 udelay(20); 1030 1031 return value; 1032 } 1033 1034 DECLARE_RTL_COND(rtl_ocpar_cond) 1035 { 1036 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1037 } 1038 1039 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1040 1041 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1042 { 1043 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1044 } 1045 1046 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1047 { 1048 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1049 } 1050 1051 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1052 { 1053 r8168dp_2_mdio_start(tp); 1054 1055 r8169_mdio_write(tp, reg, value); 1056 1057 r8168dp_2_mdio_stop(tp); 1058 } 1059 1060 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1061 { 1062 int value; 1063 1064 /* Work around issue with chip reporting wrong PHY ID */ 1065 if (reg == MII_PHYSID2) 1066 return 0xc912; 1067 1068 r8168dp_2_mdio_start(tp); 1069 1070 value = r8169_mdio_read(tp, reg); 1071 1072 r8168dp_2_mdio_stop(tp); 1073 1074 return value; 1075 } 1076 1077 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1078 { 1079 switch (tp->mac_version) { 1080 case RTL_GIGA_MAC_VER_28: 1081 case RTL_GIGA_MAC_VER_31: 1082 r8168dp_2_mdio_write(tp, location, val); 1083 break; 1084 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1085 r8168g_mdio_write(tp, location, val); 1086 break; 1087 default: 1088 r8169_mdio_write(tp, location, val); 1089 break; 1090 } 1091 } 1092 1093 static int rtl_readphy(struct rtl8169_private *tp, int location) 1094 { 1095 switch (tp->mac_version) { 1096 case RTL_GIGA_MAC_VER_28: 1097 case RTL_GIGA_MAC_VER_31: 1098 return r8168dp_2_mdio_read(tp, location); 1099 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1100 return r8168g_mdio_read(tp, location); 1101 default: 1102 return r8169_mdio_read(tp, location); 1103 } 1104 } 1105 1106 DECLARE_RTL_COND(rtl_ephyar_cond) 1107 { 1108 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1109 } 1110 1111 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1112 { 1113 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1114 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1115 1116 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1117 1118 udelay(10); 1119 } 1120 1121 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1122 { 1123 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1124 1125 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1126 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1127 } 1128 1129 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1130 { 1131 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1132 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1133 RTL_R32(tp, OCPDR) : ~0; 1134 } 1135 1136 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1137 { 1138 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1139 } 1140 1141 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1142 u32 data) 1143 { 1144 RTL_W32(tp, OCPDR, data); 1145 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1146 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1147 } 1148 1149 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1150 u32 data) 1151 { 1152 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1153 data, ERIAR_OOB); 1154 } 1155 1156 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1157 { 1158 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1159 1160 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1161 } 1162 1163 #define OOB_CMD_RESET 0x00 1164 #define OOB_CMD_DRIVER_START 0x05 1165 #define OOB_CMD_DRIVER_STOP 0x06 1166 1167 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1168 { 1169 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1170 } 1171 1172 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1173 { 1174 u16 reg; 1175 1176 reg = rtl8168_get_ocp_reg(tp); 1177 1178 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1179 } 1180 1181 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1182 { 1183 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1184 } 1185 1186 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1187 { 1188 return RTL_R8(tp, IBISR0) & 0x20; 1189 } 1190 1191 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1192 { 1193 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1194 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1195 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1196 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1197 } 1198 1199 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1200 { 1201 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1202 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1203 } 1204 1205 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1206 { 1207 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1208 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1209 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1210 } 1211 1212 static void rtl8168_driver_start(struct rtl8169_private *tp) 1213 { 1214 if (tp->dash_type == RTL_DASH_DP) 1215 rtl8168dp_driver_start(tp); 1216 else 1217 rtl8168ep_driver_start(tp); 1218 } 1219 1220 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1221 { 1222 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1223 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1224 } 1225 1226 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1227 { 1228 rtl8168ep_stop_cmac(tp); 1229 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1230 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1231 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1232 } 1233 1234 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1235 { 1236 if (tp->dash_type == RTL_DASH_DP) 1237 rtl8168dp_driver_stop(tp); 1238 else 1239 rtl8168ep_driver_stop(tp); 1240 } 1241 1242 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1243 { 1244 u16 reg = rtl8168_get_ocp_reg(tp); 1245 1246 return r8168dp_ocp_read(tp, reg) & BIT(15); 1247 } 1248 1249 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1250 { 1251 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1252 } 1253 1254 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1255 { 1256 switch (tp->dash_type) { 1257 case RTL_DASH_DP: 1258 return r8168dp_check_dash(tp); 1259 case RTL_DASH_EP: 1260 return r8168ep_check_dash(tp); 1261 default: 1262 return false; 1263 } 1264 } 1265 1266 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1267 { 1268 switch (tp->mac_version) { 1269 case RTL_GIGA_MAC_VER_28: 1270 case RTL_GIGA_MAC_VER_31: 1271 return RTL_DASH_DP; 1272 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1273 return RTL_DASH_EP; 1274 default: 1275 return RTL_DASH_NONE; 1276 } 1277 } 1278 1279 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1280 { 1281 switch (tp->mac_version) { 1282 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1283 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1284 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1285 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1286 if (enable) 1287 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1288 else 1289 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1290 break; 1291 default: 1292 break; 1293 } 1294 } 1295 1296 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1297 { 1298 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1299 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1300 } 1301 1302 DECLARE_RTL_COND(rtl_efusear_cond) 1303 { 1304 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1305 } 1306 1307 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1308 { 1309 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1310 1311 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1312 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1313 } 1314 1315 static u32 rtl_get_events(struct rtl8169_private *tp) 1316 { 1317 if (rtl_is_8125(tp)) 1318 return RTL_R32(tp, IntrStatus_8125); 1319 else 1320 return RTL_R16(tp, IntrStatus); 1321 } 1322 1323 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1324 { 1325 if (rtl_is_8125(tp)) 1326 RTL_W32(tp, IntrStatus_8125, bits); 1327 else 1328 RTL_W16(tp, IntrStatus, bits); 1329 } 1330 1331 static void rtl_irq_disable(struct rtl8169_private *tp) 1332 { 1333 if (rtl_is_8125(tp)) 1334 RTL_W32(tp, IntrMask_8125, 0); 1335 else 1336 RTL_W16(tp, IntrMask, 0); 1337 } 1338 1339 static void rtl_irq_enable(struct rtl8169_private *tp) 1340 { 1341 if (rtl_is_8125(tp)) 1342 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1343 else 1344 RTL_W16(tp, IntrMask, tp->irq_mask); 1345 } 1346 1347 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1348 { 1349 rtl_irq_disable(tp); 1350 rtl_ack_events(tp, 0xffffffff); 1351 rtl_pci_commit(tp); 1352 } 1353 1354 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1355 { 1356 struct phy_device *phydev = tp->phydev; 1357 1358 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1359 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1360 if (phydev->speed == SPEED_1000) { 1361 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1362 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1363 } else if (phydev->speed == SPEED_100) { 1364 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1365 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1366 } else { 1367 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1368 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1369 } 1370 rtl_reset_packet_filter(tp); 1371 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1372 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1373 if (phydev->speed == SPEED_1000) { 1374 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1375 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1376 } else { 1377 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1378 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1379 } 1380 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1381 if (phydev->speed == SPEED_10) { 1382 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1383 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1384 } else { 1385 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1386 } 1387 } 1388 } 1389 1390 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1391 1392 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1393 { 1394 struct rtl8169_private *tp = netdev_priv(dev); 1395 1396 wol->supported = WAKE_ANY; 1397 wol->wolopts = tp->saved_wolopts; 1398 } 1399 1400 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1401 { 1402 static const struct { 1403 u32 opt; 1404 u16 reg; 1405 u8 mask; 1406 } cfg[] = { 1407 { WAKE_PHY, Config3, LinkUp }, 1408 { WAKE_UCAST, Config5, UWF }, 1409 { WAKE_BCAST, Config5, BWF }, 1410 { WAKE_MCAST, Config5, MWF }, 1411 { WAKE_ANY, Config5, LanWake }, 1412 { WAKE_MAGIC, Config3, MagicPacket } 1413 }; 1414 unsigned int i, tmp = ARRAY_SIZE(cfg); 1415 unsigned long flags; 1416 u8 options; 1417 1418 rtl_unlock_config_regs(tp); 1419 1420 if (rtl_is_8168evl_up(tp)) { 1421 tmp--; 1422 if (wolopts & WAKE_MAGIC) 1423 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1424 else 1425 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1426 } else if (rtl_is_8125(tp)) { 1427 tmp--; 1428 if (wolopts & WAKE_MAGIC) 1429 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1430 else 1431 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1432 } 1433 1434 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1435 for (i = 0; i < tmp; i++) { 1436 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1437 if (wolopts & cfg[i].opt) 1438 options |= cfg[i].mask; 1439 RTL_W8(tp, cfg[i].reg, options); 1440 } 1441 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1442 1443 switch (tp->mac_version) { 1444 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1445 options = RTL_R8(tp, Config1) & ~PMEnable; 1446 if (wolopts) 1447 options |= PMEnable; 1448 RTL_W8(tp, Config1, options); 1449 break; 1450 case RTL_GIGA_MAC_VER_34: 1451 case RTL_GIGA_MAC_VER_37: 1452 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1453 if (wolopts) 1454 rtl_mod_config2(tp, 0, PME_SIGNAL); 1455 else 1456 rtl_mod_config2(tp, PME_SIGNAL, 0); 1457 break; 1458 default: 1459 break; 1460 } 1461 1462 rtl_lock_config_regs(tp); 1463 1464 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1465 1466 if (!tp->dash_enabled) { 1467 rtl_set_d3_pll_down(tp, !wolopts); 1468 tp->dev->wol_enabled = wolopts ? 1 : 0; 1469 } 1470 } 1471 1472 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1473 { 1474 struct rtl8169_private *tp = netdev_priv(dev); 1475 1476 if (wol->wolopts & ~WAKE_ANY) 1477 return -EINVAL; 1478 1479 tp->saved_wolopts = wol->wolopts; 1480 __rtl8169_set_wol(tp, tp->saved_wolopts); 1481 1482 return 0; 1483 } 1484 1485 static void rtl8169_get_drvinfo(struct net_device *dev, 1486 struct ethtool_drvinfo *info) 1487 { 1488 struct rtl8169_private *tp = netdev_priv(dev); 1489 struct rtl_fw *rtl_fw = tp->rtl_fw; 1490 1491 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1492 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1493 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1494 if (rtl_fw) 1495 strscpy(info->fw_version, rtl_fw->version, 1496 sizeof(info->fw_version)); 1497 } 1498 1499 static int rtl8169_get_regs_len(struct net_device *dev) 1500 { 1501 return R8169_REGS_SIZE; 1502 } 1503 1504 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1505 netdev_features_t features) 1506 { 1507 struct rtl8169_private *tp = netdev_priv(dev); 1508 1509 if (dev->mtu > TD_MSS_MAX) 1510 features &= ~NETIF_F_ALL_TSO; 1511 1512 if (dev->mtu > ETH_DATA_LEN && 1513 tp->mac_version > RTL_GIGA_MAC_VER_06) 1514 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1515 1516 return features; 1517 } 1518 1519 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1520 netdev_features_t features) 1521 { 1522 u32 rx_config = RTL_R32(tp, RxConfig); 1523 1524 if (features & NETIF_F_RXALL) 1525 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1526 else 1527 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1528 1529 if (rtl_is_8125(tp)) { 1530 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1531 rx_config |= RX_VLAN_8125; 1532 else 1533 rx_config &= ~RX_VLAN_8125; 1534 } 1535 1536 RTL_W32(tp, RxConfig, rx_config); 1537 } 1538 1539 static int rtl8169_set_features(struct net_device *dev, 1540 netdev_features_t features) 1541 { 1542 struct rtl8169_private *tp = netdev_priv(dev); 1543 1544 rtl_set_rx_config_features(tp, features); 1545 1546 if (features & NETIF_F_RXCSUM) 1547 tp->cp_cmd |= RxChkSum; 1548 else 1549 tp->cp_cmd &= ~RxChkSum; 1550 1551 if (!rtl_is_8125(tp)) { 1552 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1553 tp->cp_cmd |= RxVlan; 1554 else 1555 tp->cp_cmd &= ~RxVlan; 1556 } 1557 1558 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1559 rtl_pci_commit(tp); 1560 1561 return 0; 1562 } 1563 1564 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1565 { 1566 return (skb_vlan_tag_present(skb)) ? 1567 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1568 } 1569 1570 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1571 { 1572 u32 opts2 = le32_to_cpu(desc->opts2); 1573 1574 if (opts2 & RxVlanTag) 1575 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1576 } 1577 1578 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1579 void *p) 1580 { 1581 struct rtl8169_private *tp = netdev_priv(dev); 1582 u32 __iomem *data = tp->mmio_addr; 1583 u32 *dw = p; 1584 int i; 1585 1586 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1587 memcpy_fromio(dw++, data++, 4); 1588 } 1589 1590 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1591 "tx_packets", 1592 "rx_packets", 1593 "tx_errors", 1594 "rx_errors", 1595 "rx_missed", 1596 "align_errors", 1597 "tx_single_collisions", 1598 "tx_multi_collisions", 1599 "unicast", 1600 "broadcast", 1601 "multicast", 1602 "tx_aborted", 1603 "tx_underrun", 1604 }; 1605 1606 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1607 { 1608 switch (sset) { 1609 case ETH_SS_STATS: 1610 return ARRAY_SIZE(rtl8169_gstrings); 1611 default: 1612 return -EOPNOTSUPP; 1613 } 1614 } 1615 1616 DECLARE_RTL_COND(rtl_counters_cond) 1617 { 1618 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1619 } 1620 1621 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1622 { 1623 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1624 1625 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1626 rtl_pci_commit(tp); 1627 RTL_W32(tp, CounterAddrLow, cmd); 1628 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1629 1630 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1631 } 1632 1633 static void rtl8169_update_counters(struct rtl8169_private *tp) 1634 { 1635 u8 val = RTL_R8(tp, ChipCmd); 1636 1637 /* 1638 * Some chips are unable to dump tally counters when the receiver 1639 * is disabled. If 0xff chip may be in a PCI power-save state. 1640 */ 1641 if (val & CmdRxEnb && val != 0xff) 1642 rtl8169_do_counters(tp, CounterDump); 1643 } 1644 1645 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1646 { 1647 struct rtl8169_counters *counters = tp->counters; 1648 1649 /* 1650 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1651 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1652 * reset by a power cycle, while the counter values collected by the 1653 * driver are reset at every driver unload/load cycle. 1654 * 1655 * To make sure the HW values returned by @get_stats64 match the SW 1656 * values, we collect the initial values at first open(*) and use them 1657 * as offsets to normalize the values returned by @get_stats64. 1658 * 1659 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1660 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1661 * set at open time by rtl_hw_start. 1662 */ 1663 1664 if (tp->tc_offset.inited) 1665 return; 1666 1667 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1668 rtl8169_do_counters(tp, CounterReset); 1669 } else { 1670 rtl8169_update_counters(tp); 1671 tp->tc_offset.tx_errors = counters->tx_errors; 1672 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1673 tp->tc_offset.tx_aborted = counters->tx_aborted; 1674 tp->tc_offset.rx_missed = counters->rx_missed; 1675 } 1676 1677 tp->tc_offset.inited = true; 1678 } 1679 1680 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1681 struct ethtool_stats *stats, u64 *data) 1682 { 1683 struct rtl8169_private *tp = netdev_priv(dev); 1684 struct rtl8169_counters *counters; 1685 1686 counters = tp->counters; 1687 rtl8169_update_counters(tp); 1688 1689 data[0] = le64_to_cpu(counters->tx_packets); 1690 data[1] = le64_to_cpu(counters->rx_packets); 1691 data[2] = le64_to_cpu(counters->tx_errors); 1692 data[3] = le32_to_cpu(counters->rx_errors); 1693 data[4] = le16_to_cpu(counters->rx_missed); 1694 data[5] = le16_to_cpu(counters->align_errors); 1695 data[6] = le32_to_cpu(counters->tx_one_collision); 1696 data[7] = le32_to_cpu(counters->tx_multi_collision); 1697 data[8] = le64_to_cpu(counters->rx_unicast); 1698 data[9] = le64_to_cpu(counters->rx_broadcast); 1699 data[10] = le32_to_cpu(counters->rx_multicast); 1700 data[11] = le16_to_cpu(counters->tx_aborted); 1701 data[12] = le16_to_cpu(counters->tx_underun); 1702 } 1703 1704 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1705 { 1706 switch(stringset) { 1707 case ETH_SS_STATS: 1708 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1709 break; 1710 } 1711 } 1712 1713 /* 1714 * Interrupt coalescing 1715 * 1716 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1717 * > 8169, 8168 and 810x line of chipsets 1718 * 1719 * 8169, 8168, and 8136(810x) serial chipsets support it. 1720 * 1721 * > 2 - the Tx timer unit at gigabit speed 1722 * 1723 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1724 * (0xe0) bit 1 and bit 0. 1725 * 1726 * For 8169 1727 * bit[1:0] \ speed 1000M 100M 10M 1728 * 0 0 320ns 2.56us 40.96us 1729 * 0 1 2.56us 20.48us 327.7us 1730 * 1 0 5.12us 40.96us 655.4us 1731 * 1 1 10.24us 81.92us 1.31ms 1732 * 1733 * For the other 1734 * bit[1:0] \ speed 1000M 100M 10M 1735 * 0 0 5us 2.56us 40.96us 1736 * 0 1 40us 20.48us 327.7us 1737 * 1 0 80us 40.96us 655.4us 1738 * 1 1 160us 81.92us 1.31ms 1739 */ 1740 1741 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1742 struct rtl_coalesce_info { 1743 u32 speed; 1744 u32 scale_nsecs[4]; 1745 }; 1746 1747 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1748 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1749 1750 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1751 { SPEED_1000, COALESCE_DELAY(320) }, 1752 { SPEED_100, COALESCE_DELAY(2560) }, 1753 { SPEED_10, COALESCE_DELAY(40960) }, 1754 { 0 }, 1755 }; 1756 1757 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1758 { SPEED_1000, COALESCE_DELAY(5000) }, 1759 { SPEED_100, COALESCE_DELAY(2560) }, 1760 { SPEED_10, COALESCE_DELAY(40960) }, 1761 { 0 }, 1762 }; 1763 #undef COALESCE_DELAY 1764 1765 /* get rx/tx scale vector corresponding to current speed */ 1766 static const struct rtl_coalesce_info * 1767 rtl_coalesce_info(struct rtl8169_private *tp) 1768 { 1769 const struct rtl_coalesce_info *ci; 1770 1771 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1772 ci = rtl_coalesce_info_8169; 1773 else 1774 ci = rtl_coalesce_info_8168_8136; 1775 1776 /* if speed is unknown assume highest one */ 1777 if (tp->phydev->speed == SPEED_UNKNOWN) 1778 return ci; 1779 1780 for (; ci->speed; ci++) { 1781 if (tp->phydev->speed == ci->speed) 1782 return ci; 1783 } 1784 1785 return ERR_PTR(-ELNRNG); 1786 } 1787 1788 static int rtl_get_coalesce(struct net_device *dev, 1789 struct ethtool_coalesce *ec, 1790 struct kernel_ethtool_coalesce *kernel_coal, 1791 struct netlink_ext_ack *extack) 1792 { 1793 struct rtl8169_private *tp = netdev_priv(dev); 1794 const struct rtl_coalesce_info *ci; 1795 u32 scale, c_us, c_fr; 1796 u16 intrmit; 1797 1798 if (rtl_is_8125(tp)) 1799 return -EOPNOTSUPP; 1800 1801 memset(ec, 0, sizeof(*ec)); 1802 1803 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1804 ci = rtl_coalesce_info(tp); 1805 if (IS_ERR(ci)) 1806 return PTR_ERR(ci); 1807 1808 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1809 1810 intrmit = RTL_R16(tp, IntrMitigate); 1811 1812 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1813 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1814 1815 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1816 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1817 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1818 1819 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1820 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1821 1822 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1823 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1824 1825 return 0; 1826 } 1827 1828 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1829 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1830 u16 *cp01) 1831 { 1832 const struct rtl_coalesce_info *ci; 1833 u16 i; 1834 1835 ci = rtl_coalesce_info(tp); 1836 if (IS_ERR(ci)) 1837 return PTR_ERR(ci); 1838 1839 for (i = 0; i < 4; i++) { 1840 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1841 *cp01 = i; 1842 return ci->scale_nsecs[i]; 1843 } 1844 } 1845 1846 return -ERANGE; 1847 } 1848 1849 static int rtl_set_coalesce(struct net_device *dev, 1850 struct ethtool_coalesce *ec, 1851 struct kernel_ethtool_coalesce *kernel_coal, 1852 struct netlink_ext_ack *extack) 1853 { 1854 struct rtl8169_private *tp = netdev_priv(dev); 1855 u32 tx_fr = ec->tx_max_coalesced_frames; 1856 u32 rx_fr = ec->rx_max_coalesced_frames; 1857 u32 coal_usec_max, units; 1858 u16 w = 0, cp01 = 0; 1859 int scale; 1860 1861 if (rtl_is_8125(tp)) 1862 return -EOPNOTSUPP; 1863 1864 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1865 return -ERANGE; 1866 1867 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1868 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1869 if (scale < 0) 1870 return scale; 1871 1872 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1873 * not only when usecs=0 because of e.g. the following scenario: 1874 * 1875 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1876 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1877 * - then user does `ethtool -C eth0 rx-usecs 100` 1878 * 1879 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1880 * if we want to ignore rx_frames then it has to be set to 0. 1881 */ 1882 if (rx_fr == 1) 1883 rx_fr = 0; 1884 if (tx_fr == 1) 1885 tx_fr = 0; 1886 1887 /* HW requires time limit to be set if frame limit is set */ 1888 if ((tx_fr && !ec->tx_coalesce_usecs) || 1889 (rx_fr && !ec->rx_coalesce_usecs)) 1890 return -EINVAL; 1891 1892 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1893 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1894 1895 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1896 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1897 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1898 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1899 1900 RTL_W16(tp, IntrMitigate, w); 1901 1902 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1903 if (rtl_is_8168evl_up(tp)) { 1904 if (!rx_fr && !tx_fr) 1905 /* disable packet counter */ 1906 tp->cp_cmd |= PktCntrDisable; 1907 else 1908 tp->cp_cmd &= ~PktCntrDisable; 1909 } 1910 1911 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1912 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1913 rtl_pci_commit(tp); 1914 1915 return 0; 1916 } 1917 1918 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1919 { 1920 struct rtl8169_private *tp = netdev_priv(dev); 1921 1922 if (!rtl_supports_eee(tp)) 1923 return -EOPNOTSUPP; 1924 1925 return phy_ethtool_get_eee(tp->phydev, data); 1926 } 1927 1928 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1929 { 1930 struct rtl8169_private *tp = netdev_priv(dev); 1931 int ret; 1932 1933 if (!rtl_supports_eee(tp)) 1934 return -EOPNOTSUPP; 1935 1936 ret = phy_ethtool_set_eee(tp->phydev, data); 1937 1938 if (!ret) 1939 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1940 MDIO_AN_EEE_ADV); 1941 return ret; 1942 } 1943 1944 static void rtl8169_get_ringparam(struct net_device *dev, 1945 struct ethtool_ringparam *data, 1946 struct kernel_ethtool_ringparam *kernel_data, 1947 struct netlink_ext_ack *extack) 1948 { 1949 data->rx_max_pending = NUM_RX_DESC; 1950 data->rx_pending = NUM_RX_DESC; 1951 data->tx_max_pending = NUM_TX_DESC; 1952 data->tx_pending = NUM_TX_DESC; 1953 } 1954 1955 static void rtl8169_get_pauseparam(struct net_device *dev, 1956 struct ethtool_pauseparam *data) 1957 { 1958 struct rtl8169_private *tp = netdev_priv(dev); 1959 bool tx_pause, rx_pause; 1960 1961 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1962 1963 data->autoneg = tp->phydev->autoneg; 1964 data->tx_pause = tx_pause ? 1 : 0; 1965 data->rx_pause = rx_pause ? 1 : 0; 1966 } 1967 1968 static int rtl8169_set_pauseparam(struct net_device *dev, 1969 struct ethtool_pauseparam *data) 1970 { 1971 struct rtl8169_private *tp = netdev_priv(dev); 1972 1973 if (dev->mtu > ETH_DATA_LEN) 1974 return -EOPNOTSUPP; 1975 1976 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1977 1978 return 0; 1979 } 1980 1981 static const struct ethtool_ops rtl8169_ethtool_ops = { 1982 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1983 ETHTOOL_COALESCE_MAX_FRAMES, 1984 .get_drvinfo = rtl8169_get_drvinfo, 1985 .get_regs_len = rtl8169_get_regs_len, 1986 .get_link = ethtool_op_get_link, 1987 .get_coalesce = rtl_get_coalesce, 1988 .set_coalesce = rtl_set_coalesce, 1989 .get_regs = rtl8169_get_regs, 1990 .get_wol = rtl8169_get_wol, 1991 .set_wol = rtl8169_set_wol, 1992 .get_strings = rtl8169_get_strings, 1993 .get_sset_count = rtl8169_get_sset_count, 1994 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1995 .get_ts_info = ethtool_op_get_ts_info, 1996 .nway_reset = phy_ethtool_nway_reset, 1997 .get_eee = rtl8169_get_eee, 1998 .set_eee = rtl8169_set_eee, 1999 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2000 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2001 .get_ringparam = rtl8169_get_ringparam, 2002 .get_pauseparam = rtl8169_get_pauseparam, 2003 .set_pauseparam = rtl8169_set_pauseparam, 2004 }; 2005 2006 static void rtl_enable_eee(struct rtl8169_private *tp) 2007 { 2008 struct phy_device *phydev = tp->phydev; 2009 int adv; 2010 2011 /* respect EEE advertisement the user may have set */ 2012 if (tp->eee_adv >= 0) 2013 adv = tp->eee_adv; 2014 else 2015 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2016 2017 if (adv >= 0) 2018 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2019 } 2020 2021 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2022 { 2023 /* 2024 * The driver currently handles the 8168Bf and the 8168Be identically 2025 * but they can be identified more specifically through the test below 2026 * if needed: 2027 * 2028 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2029 * 2030 * Same thing for the 8101Eb and the 8101Ec: 2031 * 2032 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2033 */ 2034 static const struct rtl_mac_info { 2035 u16 mask; 2036 u16 val; 2037 enum mac_version ver; 2038 } mac_info[] = { 2039 /* 8125B family. */ 2040 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2041 2042 /* 8125A family. */ 2043 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2044 /* It seems only XID 609 made it to the mass market. 2045 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2046 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2047 */ 2048 2049 /* RTL8117 */ 2050 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2051 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2052 2053 /* 8168EP family. */ 2054 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2055 /* It seems this chip version never made it to 2056 * the wild. Let's disable detection. 2057 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2058 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2059 */ 2060 2061 /* 8168H family. */ 2062 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2063 /* It seems this chip version never made it to 2064 * the wild. Let's disable detection. 2065 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2066 */ 2067 2068 /* 8168G family. */ 2069 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2070 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2071 /* It seems this chip version never made it to 2072 * the wild. Let's disable detection. 2073 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2074 */ 2075 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2076 2077 /* 8168F family. */ 2078 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2079 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2080 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2081 2082 /* 8168E family. */ 2083 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2084 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2085 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2086 2087 /* 8168D family. */ 2088 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2089 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2090 2091 /* 8168DP family. */ 2092 /* It seems this early RTL8168dp version never made it to 2093 * the wild. Support has been removed. 2094 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2095 */ 2096 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2097 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2098 2099 /* 8168C family. */ 2100 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2101 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2102 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2103 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2104 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2105 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2106 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2107 2108 /* 8168B family. */ 2109 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2110 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2111 2112 /* 8101 family. */ 2113 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2114 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2115 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2116 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2117 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2118 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2119 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2120 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2121 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2122 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2123 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2124 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2125 2126 /* 8110 family. */ 2127 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2128 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2129 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2130 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2131 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2132 2133 /* Catch-all */ 2134 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2135 }; 2136 const struct rtl_mac_info *p = mac_info; 2137 enum mac_version ver; 2138 2139 while ((xid & p->mask) != p->val) 2140 p++; 2141 ver = p->ver; 2142 2143 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2144 if (ver == RTL_GIGA_MAC_VER_42) 2145 ver = RTL_GIGA_MAC_VER_43; 2146 else if (ver == RTL_GIGA_MAC_VER_46) 2147 ver = RTL_GIGA_MAC_VER_48; 2148 } 2149 2150 return ver; 2151 } 2152 2153 static void rtl_release_firmware(struct rtl8169_private *tp) 2154 { 2155 if (tp->rtl_fw) { 2156 rtl_fw_release_firmware(tp->rtl_fw); 2157 kfree(tp->rtl_fw); 2158 tp->rtl_fw = NULL; 2159 } 2160 } 2161 2162 void r8169_apply_firmware(struct rtl8169_private *tp) 2163 { 2164 int val; 2165 2166 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2167 if (tp->rtl_fw) { 2168 rtl_fw_write_firmware(tp, tp->rtl_fw); 2169 /* At least one firmware doesn't reset tp->ocp_base. */ 2170 tp->ocp_base = OCP_STD_PHY_BASE; 2171 2172 /* PHY soft reset may still be in progress */ 2173 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2174 !(val & BMCR_RESET), 2175 50000, 600000, true); 2176 } 2177 } 2178 2179 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2180 { 2181 /* Adjust EEE LED frequency */ 2182 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2183 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2184 2185 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2186 } 2187 2188 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2189 { 2190 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2191 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2192 } 2193 2194 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2195 { 2196 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2197 } 2198 2199 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2200 { 2201 rtl8125_set_eee_txidle_timer(tp); 2202 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2203 } 2204 2205 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2206 { 2207 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2208 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2209 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2210 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2211 } 2212 2213 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2214 { 2215 u16 data1, data2, ioffset; 2216 2217 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2218 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2219 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2220 2221 ioffset = (data2 >> 1) & 0x7ff8; 2222 ioffset |= data2 & 0x0007; 2223 if (data1 & BIT(7)) 2224 ioffset |= BIT(15); 2225 2226 return ioffset; 2227 } 2228 2229 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2230 { 2231 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 2232 return; 2233 2234 set_bit(flag, tp->wk.flags); 2235 schedule_work(&tp->wk.work); 2236 } 2237 2238 static void rtl8169_init_phy(struct rtl8169_private *tp) 2239 { 2240 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2241 2242 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2243 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2244 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2245 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2246 RTL_W8(tp, 0x82, 0x01); 2247 } 2248 2249 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2250 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2251 tp->pci_dev->subsystem_device == 0xe000) 2252 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2253 2254 /* We may have called phy_speed_down before */ 2255 phy_speed_up(tp->phydev); 2256 2257 if (rtl_supports_eee(tp)) 2258 rtl_enable_eee(tp); 2259 2260 genphy_soft_reset(tp->phydev); 2261 } 2262 2263 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2264 { 2265 rtl_unlock_config_regs(tp); 2266 2267 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2268 rtl_pci_commit(tp); 2269 2270 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2271 rtl_pci_commit(tp); 2272 2273 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2274 rtl_rar_exgmac_set(tp, addr); 2275 2276 rtl_lock_config_regs(tp); 2277 } 2278 2279 static int rtl_set_mac_address(struct net_device *dev, void *p) 2280 { 2281 struct rtl8169_private *tp = netdev_priv(dev); 2282 int ret; 2283 2284 ret = eth_mac_addr(dev, p); 2285 if (ret) 2286 return ret; 2287 2288 rtl_rar_set(tp, dev->dev_addr); 2289 2290 return 0; 2291 } 2292 2293 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2294 { 2295 switch (tp->mac_version) { 2296 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2297 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2298 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2299 break; 2300 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2301 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2302 case RTL_GIGA_MAC_VER_38: 2303 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2304 break; 2305 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2306 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2307 break; 2308 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2309 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2310 break; 2311 default: 2312 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2313 break; 2314 } 2315 } 2316 2317 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2318 { 2319 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2320 } 2321 2322 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2323 { 2324 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2325 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2326 } 2327 2328 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2329 { 2330 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2331 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2332 } 2333 2334 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2335 { 2336 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2337 } 2338 2339 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2340 { 2341 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2342 } 2343 2344 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2345 { 2346 RTL_W8(tp, MaxTxPacketSize, 0x24); 2347 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2348 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2349 } 2350 2351 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2352 { 2353 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2354 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2355 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2356 } 2357 2358 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2359 { 2360 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2361 } 2362 2363 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2364 { 2365 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2366 } 2367 2368 static void rtl_jumbo_config(struct rtl8169_private *tp) 2369 { 2370 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2371 int readrq = 4096; 2372 2373 rtl_unlock_config_regs(tp); 2374 switch (tp->mac_version) { 2375 case RTL_GIGA_MAC_VER_17: 2376 if (jumbo) { 2377 readrq = 512; 2378 r8168b_1_hw_jumbo_enable(tp); 2379 } else { 2380 r8168b_1_hw_jumbo_disable(tp); 2381 } 2382 break; 2383 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2384 if (jumbo) { 2385 readrq = 512; 2386 r8168c_hw_jumbo_enable(tp); 2387 } else { 2388 r8168c_hw_jumbo_disable(tp); 2389 } 2390 break; 2391 case RTL_GIGA_MAC_VER_28: 2392 if (jumbo) 2393 r8168dp_hw_jumbo_enable(tp); 2394 else 2395 r8168dp_hw_jumbo_disable(tp); 2396 break; 2397 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2398 if (jumbo) 2399 r8168e_hw_jumbo_enable(tp); 2400 else 2401 r8168e_hw_jumbo_disable(tp); 2402 break; 2403 default: 2404 break; 2405 } 2406 rtl_lock_config_regs(tp); 2407 2408 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2409 pcie_set_readrq(tp->pci_dev, readrq); 2410 2411 /* Chip doesn't support pause in jumbo mode */ 2412 if (jumbo) { 2413 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2414 tp->phydev->advertising); 2415 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2416 tp->phydev->advertising); 2417 phy_start_aneg(tp->phydev); 2418 } 2419 } 2420 2421 DECLARE_RTL_COND(rtl_chipcmd_cond) 2422 { 2423 return RTL_R8(tp, ChipCmd) & CmdReset; 2424 } 2425 2426 static void rtl_hw_reset(struct rtl8169_private *tp) 2427 { 2428 RTL_W8(tp, ChipCmd, CmdReset); 2429 2430 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2431 } 2432 2433 static void rtl_request_firmware(struct rtl8169_private *tp) 2434 { 2435 struct rtl_fw *rtl_fw; 2436 2437 /* firmware loaded already or no firmware available */ 2438 if (tp->rtl_fw || !tp->fw_name) 2439 return; 2440 2441 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2442 if (!rtl_fw) 2443 return; 2444 2445 rtl_fw->phy_write = rtl_writephy; 2446 rtl_fw->phy_read = rtl_readphy; 2447 rtl_fw->mac_mcu_write = mac_mcu_write; 2448 rtl_fw->mac_mcu_read = mac_mcu_read; 2449 rtl_fw->fw_name = tp->fw_name; 2450 rtl_fw->dev = tp_to_dev(tp); 2451 2452 if (rtl_fw_request_firmware(rtl_fw)) 2453 kfree(rtl_fw); 2454 else 2455 tp->rtl_fw = rtl_fw; 2456 } 2457 2458 static void rtl_rx_close(struct rtl8169_private *tp) 2459 { 2460 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2461 } 2462 2463 DECLARE_RTL_COND(rtl_npq_cond) 2464 { 2465 return RTL_R8(tp, TxPoll) & NPQ; 2466 } 2467 2468 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2469 { 2470 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2471 } 2472 2473 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2474 { 2475 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2476 } 2477 2478 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2479 { 2480 /* IntrMitigate has new functionality on RTL8125 */ 2481 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2482 } 2483 2484 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2485 { 2486 switch (tp->mac_version) { 2487 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2488 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2489 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2490 break; 2491 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2492 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2493 break; 2494 case RTL_GIGA_MAC_VER_63: 2495 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2496 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2497 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2498 break; 2499 default: 2500 break; 2501 } 2502 } 2503 2504 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2505 { 2506 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2507 } 2508 2509 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2510 { 2511 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2512 fsleep(2000); 2513 rtl_wait_txrx_fifo_empty(tp); 2514 } 2515 2516 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2517 { 2518 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2519 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2520 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2521 2522 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2523 rtl_disable_rxdvgate(tp); 2524 } 2525 2526 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2527 { 2528 if (tp->dash_enabled) 2529 return; 2530 2531 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2532 tp->mac_version == RTL_GIGA_MAC_VER_33) 2533 rtl_ephy_write(tp, 0x19, 0xff64); 2534 2535 if (device_may_wakeup(tp_to_dev(tp))) { 2536 phy_speed_down(tp->phydev, false); 2537 rtl_wol_enable_rx(tp); 2538 } 2539 } 2540 2541 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2542 { 2543 u32 val = TX_DMA_BURST << TxDMAShift | 2544 InterFrameGap << TxInterFrameGapShift; 2545 2546 if (rtl_is_8168evl_up(tp)) 2547 val |= TXCFG_AUTO_FIFO; 2548 2549 RTL_W32(tp, TxConfig, val); 2550 } 2551 2552 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2553 { 2554 /* Low hurts. Let's disable the filtering. */ 2555 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2556 } 2557 2558 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2559 { 2560 /* 2561 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2562 * register to be written before TxDescAddrLow to work. 2563 * Switching from MMIO to I/O access fixes the issue as well. 2564 */ 2565 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2566 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2567 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2568 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2569 } 2570 2571 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2572 { 2573 u32 val; 2574 2575 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2576 val = 0x000fff00; 2577 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2578 val = 0x00ffff00; 2579 else 2580 return; 2581 2582 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2583 val |= 0xff; 2584 2585 RTL_W32(tp, 0x7c, val); 2586 } 2587 2588 static void rtl_set_rx_mode(struct net_device *dev) 2589 { 2590 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2591 /* Multicast hash filter */ 2592 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2593 struct rtl8169_private *tp = netdev_priv(dev); 2594 u32 tmp; 2595 2596 if (dev->flags & IFF_PROMISC) { 2597 rx_mode |= AcceptAllPhys; 2598 } else if (!(dev->flags & IFF_MULTICAST)) { 2599 rx_mode &= ~AcceptMulticast; 2600 } else if (dev->flags & IFF_ALLMULTI || 2601 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2602 /* accept all multicasts */ 2603 } else if (netdev_mc_empty(dev)) { 2604 rx_mode &= ~AcceptMulticast; 2605 } else { 2606 struct netdev_hw_addr *ha; 2607 2608 mc_filter[1] = mc_filter[0] = 0; 2609 netdev_for_each_mc_addr(ha, dev) { 2610 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2611 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2612 } 2613 2614 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2615 tmp = mc_filter[0]; 2616 mc_filter[0] = swab32(mc_filter[1]); 2617 mc_filter[1] = swab32(tmp); 2618 } 2619 } 2620 2621 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2622 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2623 2624 tmp = RTL_R32(tp, RxConfig); 2625 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2626 } 2627 2628 DECLARE_RTL_COND(rtl_csiar_cond) 2629 { 2630 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2631 } 2632 2633 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2634 { 2635 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2636 2637 RTL_W32(tp, CSIDR, value); 2638 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2639 CSIAR_BYTE_ENABLE | func << 16); 2640 2641 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2642 } 2643 2644 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2645 { 2646 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2647 2648 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2649 CSIAR_BYTE_ENABLE); 2650 2651 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2652 RTL_R32(tp, CSIDR) : ~0; 2653 } 2654 2655 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2656 { 2657 struct pci_dev *pdev = tp->pci_dev; 2658 u32 csi; 2659 2660 /* According to Realtek the value at config space address 0x070f 2661 * controls the L0s/L1 entrance latency. We try standard ECAM access 2662 * first and if it fails fall back to CSI. 2663 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2664 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2665 */ 2666 if (pdev->cfg_size > 0x070f && 2667 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2668 return; 2669 2670 netdev_notice_once(tp->dev, 2671 "No native access to PCI extended config space, falling back to CSI\n"); 2672 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2673 rtl_csi_write(tp, 0x070c, csi | val << 24); 2674 } 2675 2676 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2677 { 2678 /* L0 7us, L1 16us */ 2679 rtl_set_aspm_entry_latency(tp, 0x27); 2680 } 2681 2682 struct ephy_info { 2683 unsigned int offset; 2684 u16 mask; 2685 u16 bits; 2686 }; 2687 2688 static void __rtl_ephy_init(struct rtl8169_private *tp, 2689 const struct ephy_info *e, int len) 2690 { 2691 u16 w; 2692 2693 while (len-- > 0) { 2694 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2695 rtl_ephy_write(tp, e->offset, w); 2696 e++; 2697 } 2698 } 2699 2700 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2701 2702 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2703 { 2704 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2705 PCI_EXP_LNKCTL_CLKREQ_EN); 2706 } 2707 2708 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2709 { 2710 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2711 PCI_EXP_LNKCTL_CLKREQ_EN); 2712 } 2713 2714 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2715 { 2716 /* work around an issue when PCI reset occurs during L2/L3 state */ 2717 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2718 } 2719 2720 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2721 { 2722 /* Bits control which events trigger ASPM L1 exit: 2723 * Bit 12: rxdv 2724 * Bit 11: ltr_msg 2725 * Bit 10: txdma_poll 2726 * Bit 9: xadm 2727 * Bit 8: pktavi 2728 * Bit 7: txpla 2729 */ 2730 switch (tp->mac_version) { 2731 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2732 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2733 break; 2734 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2735 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2736 break; 2737 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2738 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2739 break; 2740 default: 2741 break; 2742 } 2743 } 2744 2745 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2746 { 2747 switch (tp->mac_version) { 2748 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2749 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2750 break; 2751 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2752 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2753 break; 2754 default: 2755 break; 2756 } 2757 } 2758 2759 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2760 { 2761 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2762 return; 2763 2764 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2765 if (enable && tp->aspm_manageable) { 2766 /* On these chip versions ASPM can even harm 2767 * bus communication of other PCI devices. 2768 */ 2769 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2770 tp->mac_version == RTL_GIGA_MAC_VER_43) 2771 return; 2772 2773 rtl_mod_config5(tp, 0, ASPM_en); 2774 rtl_mod_config2(tp, 0, ClkReqEn); 2775 2776 switch (tp->mac_version) { 2777 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2778 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2779 /* reset ephy tx/rx disable timer */ 2780 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2781 /* chip can trigger L1.2 */ 2782 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2783 break; 2784 default: 2785 break; 2786 } 2787 } else { 2788 switch (tp->mac_version) { 2789 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2790 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2791 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2792 break; 2793 default: 2794 break; 2795 } 2796 2797 rtl_mod_config2(tp, ClkReqEn, 0); 2798 rtl_mod_config5(tp, ASPM_en, 0); 2799 } 2800 } 2801 2802 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2803 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2804 { 2805 /* Usage of dynamic vs. static FIFO is controlled by bit 2806 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2807 */ 2808 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2809 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2810 } 2811 2812 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2813 u8 low, u8 high) 2814 { 2815 /* FIFO thresholds for pause flow control */ 2816 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2817 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2818 } 2819 2820 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2821 { 2822 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2823 } 2824 2825 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2826 { 2827 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2828 2829 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2830 2831 rtl_disable_clock_request(tp); 2832 } 2833 2834 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2835 { 2836 static const struct ephy_info e_info_8168cp[] = { 2837 { 0x01, 0, 0x0001 }, 2838 { 0x02, 0x0800, 0x1000 }, 2839 { 0x03, 0, 0x0042 }, 2840 { 0x06, 0x0080, 0x0000 }, 2841 { 0x07, 0, 0x2000 } 2842 }; 2843 2844 rtl_set_def_aspm_entry_latency(tp); 2845 2846 rtl_ephy_init(tp, e_info_8168cp); 2847 2848 __rtl_hw_start_8168cp(tp); 2849 } 2850 2851 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2852 { 2853 rtl_set_def_aspm_entry_latency(tp); 2854 2855 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2856 } 2857 2858 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2859 { 2860 rtl_set_def_aspm_entry_latency(tp); 2861 2862 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2863 2864 /* Magic. */ 2865 RTL_W8(tp, DBG_REG, 0x20); 2866 } 2867 2868 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2869 { 2870 static const struct ephy_info e_info_8168c_1[] = { 2871 { 0x02, 0x0800, 0x1000 }, 2872 { 0x03, 0, 0x0002 }, 2873 { 0x06, 0x0080, 0x0000 } 2874 }; 2875 2876 rtl_set_def_aspm_entry_latency(tp); 2877 2878 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2879 2880 rtl_ephy_init(tp, e_info_8168c_1); 2881 2882 __rtl_hw_start_8168cp(tp); 2883 } 2884 2885 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2886 { 2887 static const struct ephy_info e_info_8168c_2[] = { 2888 { 0x01, 0, 0x0001 }, 2889 { 0x03, 0x0400, 0x0020 } 2890 }; 2891 2892 rtl_set_def_aspm_entry_latency(tp); 2893 2894 rtl_ephy_init(tp, e_info_8168c_2); 2895 2896 __rtl_hw_start_8168cp(tp); 2897 } 2898 2899 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2900 { 2901 rtl_set_def_aspm_entry_latency(tp); 2902 2903 __rtl_hw_start_8168cp(tp); 2904 } 2905 2906 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2907 { 2908 rtl_set_def_aspm_entry_latency(tp); 2909 2910 rtl_disable_clock_request(tp); 2911 } 2912 2913 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2914 { 2915 static const struct ephy_info e_info_8168d_4[] = { 2916 { 0x0b, 0x0000, 0x0048 }, 2917 { 0x19, 0x0020, 0x0050 }, 2918 { 0x0c, 0x0100, 0x0020 }, 2919 { 0x10, 0x0004, 0x0000 }, 2920 }; 2921 2922 rtl_set_def_aspm_entry_latency(tp); 2923 2924 rtl_ephy_init(tp, e_info_8168d_4); 2925 2926 rtl_enable_clock_request(tp); 2927 } 2928 2929 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2930 { 2931 static const struct ephy_info e_info_8168e_1[] = { 2932 { 0x00, 0x0200, 0x0100 }, 2933 { 0x00, 0x0000, 0x0004 }, 2934 { 0x06, 0x0002, 0x0001 }, 2935 { 0x06, 0x0000, 0x0030 }, 2936 { 0x07, 0x0000, 0x2000 }, 2937 { 0x00, 0x0000, 0x0020 }, 2938 { 0x03, 0x5800, 0x2000 }, 2939 { 0x03, 0x0000, 0x0001 }, 2940 { 0x01, 0x0800, 0x1000 }, 2941 { 0x07, 0x0000, 0x4000 }, 2942 { 0x1e, 0x0000, 0x2000 }, 2943 { 0x19, 0xffff, 0xfe6c }, 2944 { 0x0a, 0x0000, 0x0040 } 2945 }; 2946 2947 rtl_set_def_aspm_entry_latency(tp); 2948 2949 rtl_ephy_init(tp, e_info_8168e_1); 2950 2951 rtl_disable_clock_request(tp); 2952 2953 /* Reset tx FIFO pointer */ 2954 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2955 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2956 2957 rtl_mod_config5(tp, Spi_en, 0); 2958 } 2959 2960 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2961 { 2962 static const struct ephy_info e_info_8168e_2[] = { 2963 { 0x09, 0x0000, 0x0080 }, 2964 { 0x19, 0x0000, 0x0224 }, 2965 { 0x00, 0x0000, 0x0004 }, 2966 { 0x0c, 0x3df0, 0x0200 }, 2967 }; 2968 2969 rtl_set_def_aspm_entry_latency(tp); 2970 2971 rtl_ephy_init(tp, e_info_8168e_2); 2972 2973 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2974 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2975 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2976 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2977 rtl_reset_packet_filter(tp); 2978 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2979 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2980 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2981 2982 rtl_disable_clock_request(tp); 2983 2984 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2985 2986 rtl8168_config_eee_mac(tp); 2987 2988 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2989 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2990 rtl_mod_config5(tp, Spi_en, 0); 2991 } 2992 2993 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2994 { 2995 rtl_set_def_aspm_entry_latency(tp); 2996 2997 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2998 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2999 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3000 rtl_reset_packet_filter(tp); 3001 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3002 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3003 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3004 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3005 3006 rtl_disable_clock_request(tp); 3007 3008 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3009 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3010 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3011 rtl_mod_config5(tp, Spi_en, 0); 3012 3013 rtl8168_config_eee_mac(tp); 3014 } 3015 3016 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3017 { 3018 static const struct ephy_info e_info_8168f_1[] = { 3019 { 0x06, 0x00c0, 0x0020 }, 3020 { 0x08, 0x0001, 0x0002 }, 3021 { 0x09, 0x0000, 0x0080 }, 3022 { 0x19, 0x0000, 0x0224 }, 3023 { 0x00, 0x0000, 0x0008 }, 3024 { 0x0c, 0x3df0, 0x0200 }, 3025 }; 3026 3027 rtl_hw_start_8168f(tp); 3028 3029 rtl_ephy_init(tp, e_info_8168f_1); 3030 } 3031 3032 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3033 { 3034 static const struct ephy_info e_info_8168f_1[] = { 3035 { 0x06, 0x00c0, 0x0020 }, 3036 { 0x0f, 0xffff, 0x5200 }, 3037 { 0x19, 0x0000, 0x0224 }, 3038 { 0x00, 0x0000, 0x0008 }, 3039 { 0x0c, 0x3df0, 0x0200 }, 3040 }; 3041 3042 rtl_hw_start_8168f(tp); 3043 rtl_pcie_state_l2l3_disable(tp); 3044 3045 rtl_ephy_init(tp, e_info_8168f_1); 3046 } 3047 3048 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3049 { 3050 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3051 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3052 3053 rtl_set_def_aspm_entry_latency(tp); 3054 3055 rtl_reset_packet_filter(tp); 3056 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3057 3058 rtl_disable_rxdvgate(tp); 3059 3060 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3061 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3062 3063 rtl8168_config_eee_mac(tp); 3064 3065 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3066 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3067 3068 rtl_pcie_state_l2l3_disable(tp); 3069 } 3070 3071 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3072 { 3073 static const struct ephy_info e_info_8168g_1[] = { 3074 { 0x00, 0x0008, 0x0000 }, 3075 { 0x0c, 0x3ff0, 0x0820 }, 3076 { 0x1e, 0x0000, 0x0001 }, 3077 { 0x19, 0x8000, 0x0000 } 3078 }; 3079 3080 rtl_hw_start_8168g(tp); 3081 rtl_ephy_init(tp, e_info_8168g_1); 3082 } 3083 3084 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3085 { 3086 static const struct ephy_info e_info_8168g_2[] = { 3087 { 0x00, 0x0008, 0x0000 }, 3088 { 0x0c, 0x3ff0, 0x0820 }, 3089 { 0x19, 0xffff, 0x7c00 }, 3090 { 0x1e, 0xffff, 0x20eb }, 3091 { 0x0d, 0xffff, 0x1666 }, 3092 { 0x00, 0xffff, 0x10a3 }, 3093 { 0x06, 0xffff, 0xf050 }, 3094 { 0x04, 0x0000, 0x0010 }, 3095 { 0x1d, 0x4000, 0x0000 }, 3096 }; 3097 3098 rtl_hw_start_8168g(tp); 3099 rtl_ephy_init(tp, e_info_8168g_2); 3100 } 3101 3102 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3103 { 3104 static const u16 fix_data[] = { 3105 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3106 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3107 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3108 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3109 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3110 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3111 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3112 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3113 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3114 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3115 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3116 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3117 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3118 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3119 }; 3120 unsigned long flags; 3121 int i; 3122 3123 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3124 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3125 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3126 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3127 } 3128 3129 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3130 { 3131 static const struct ephy_info e_info_8411_2[] = { 3132 { 0x00, 0x0008, 0x0000 }, 3133 { 0x0c, 0x37d0, 0x0820 }, 3134 { 0x1e, 0x0000, 0x0001 }, 3135 { 0x19, 0x8021, 0x0000 }, 3136 { 0x1e, 0x0000, 0x2000 }, 3137 { 0x0d, 0x0100, 0x0200 }, 3138 { 0x00, 0x0000, 0x0080 }, 3139 { 0x06, 0x0000, 0x0010 }, 3140 { 0x04, 0x0000, 0x0010 }, 3141 { 0x1d, 0x0000, 0x4000 }, 3142 }; 3143 3144 rtl_hw_start_8168g(tp); 3145 3146 rtl_ephy_init(tp, e_info_8411_2); 3147 3148 /* The following Realtek-provided magic fixes an issue with the RX unit 3149 * getting confused after the PHY having been powered-down. 3150 */ 3151 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3152 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3153 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3154 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3155 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3156 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3157 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3158 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3159 mdelay(3); 3160 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3161 3162 rtl8411b_fix_phy_down(tp); 3163 3164 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3165 3166 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3167 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3168 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3169 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3170 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3171 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3172 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3173 } 3174 3175 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3176 { 3177 static const struct ephy_info e_info_8168h_1[] = { 3178 { 0x1e, 0x0800, 0x0001 }, 3179 { 0x1d, 0x0000, 0x0800 }, 3180 { 0x05, 0xffff, 0x2089 }, 3181 { 0x06, 0xffff, 0x5881 }, 3182 { 0x04, 0xffff, 0x854a }, 3183 { 0x01, 0xffff, 0x068b } 3184 }; 3185 int rg_saw_cnt; 3186 3187 rtl_ephy_init(tp, e_info_8168h_1); 3188 3189 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3190 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3191 3192 rtl_set_def_aspm_entry_latency(tp); 3193 3194 rtl_reset_packet_filter(tp); 3195 3196 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3197 3198 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3199 3200 rtl_disable_rxdvgate(tp); 3201 3202 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3203 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3204 3205 rtl8168_config_eee_mac(tp); 3206 3207 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3208 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3209 3210 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3211 3212 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3213 3214 rtl_pcie_state_l2l3_disable(tp); 3215 3216 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3217 if (rg_saw_cnt > 0) { 3218 u16 sw_cnt_1ms_ini; 3219 3220 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3221 sw_cnt_1ms_ini &= 0x0fff; 3222 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3223 } 3224 3225 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3226 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3227 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3228 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3229 3230 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3231 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3232 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3233 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3234 } 3235 3236 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3237 { 3238 rtl8168ep_stop_cmac(tp); 3239 3240 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3241 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3242 3243 rtl_set_def_aspm_entry_latency(tp); 3244 3245 rtl_reset_packet_filter(tp); 3246 3247 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3248 3249 rtl_disable_rxdvgate(tp); 3250 3251 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3252 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3253 3254 rtl8168_config_eee_mac(tp); 3255 3256 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3257 3258 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3259 3260 rtl_pcie_state_l2l3_disable(tp); 3261 } 3262 3263 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3264 { 3265 static const struct ephy_info e_info_8168ep_3[] = { 3266 { 0x00, 0x0000, 0x0080 }, 3267 { 0x0d, 0x0100, 0x0200 }, 3268 { 0x19, 0x8021, 0x0000 }, 3269 { 0x1e, 0x0000, 0x2000 }, 3270 }; 3271 3272 rtl_ephy_init(tp, e_info_8168ep_3); 3273 3274 rtl_hw_start_8168ep(tp); 3275 3276 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3277 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3278 3279 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3280 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3281 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3282 } 3283 3284 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3285 { 3286 static const struct ephy_info e_info_8117[] = { 3287 { 0x19, 0x0040, 0x1100 }, 3288 { 0x59, 0x0040, 0x1100 }, 3289 }; 3290 int rg_saw_cnt; 3291 3292 rtl8168ep_stop_cmac(tp); 3293 rtl_ephy_init(tp, e_info_8117); 3294 3295 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3296 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3297 3298 rtl_set_def_aspm_entry_latency(tp); 3299 3300 rtl_reset_packet_filter(tp); 3301 3302 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3303 3304 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3305 3306 rtl_disable_rxdvgate(tp); 3307 3308 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3309 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3310 3311 rtl8168_config_eee_mac(tp); 3312 3313 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3314 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3315 3316 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3317 3318 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3319 3320 rtl_pcie_state_l2l3_disable(tp); 3321 3322 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3323 if (rg_saw_cnt > 0) { 3324 u16 sw_cnt_1ms_ini; 3325 3326 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3327 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3328 } 3329 3330 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3331 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3332 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3333 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3334 3335 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3336 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3337 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3338 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3339 3340 /* firmware is for MAC only */ 3341 r8169_apply_firmware(tp); 3342 } 3343 3344 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3345 { 3346 static const struct ephy_info e_info_8102e_1[] = { 3347 { 0x01, 0, 0x6e65 }, 3348 { 0x02, 0, 0x091f }, 3349 { 0x03, 0, 0xc2f9 }, 3350 { 0x06, 0, 0xafb5 }, 3351 { 0x07, 0, 0x0e00 }, 3352 { 0x19, 0, 0xec80 }, 3353 { 0x01, 0, 0x2e65 }, 3354 { 0x01, 0, 0x6e65 } 3355 }; 3356 u8 cfg1; 3357 3358 rtl_set_def_aspm_entry_latency(tp); 3359 3360 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3361 3362 RTL_W8(tp, Config1, 3363 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3364 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3365 3366 cfg1 = RTL_R8(tp, Config1); 3367 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3368 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3369 3370 rtl_ephy_init(tp, e_info_8102e_1); 3371 } 3372 3373 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3374 { 3375 rtl_set_def_aspm_entry_latency(tp); 3376 3377 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3378 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3379 } 3380 3381 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3382 { 3383 rtl_hw_start_8102e_2(tp); 3384 3385 rtl_ephy_write(tp, 0x03, 0xc2f9); 3386 } 3387 3388 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3389 { 3390 static const struct ephy_info e_info_8401[] = { 3391 { 0x01, 0xffff, 0x6fe5 }, 3392 { 0x03, 0xffff, 0x0599 }, 3393 { 0x06, 0xffff, 0xaf25 }, 3394 { 0x07, 0xffff, 0x8e68 }, 3395 }; 3396 3397 rtl_ephy_init(tp, e_info_8401); 3398 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3399 } 3400 3401 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3402 { 3403 static const struct ephy_info e_info_8105e_1[] = { 3404 { 0x07, 0, 0x4000 }, 3405 { 0x19, 0, 0x0200 }, 3406 { 0x19, 0, 0x0020 }, 3407 { 0x1e, 0, 0x2000 }, 3408 { 0x03, 0, 0x0001 }, 3409 { 0x19, 0, 0x0100 }, 3410 { 0x19, 0, 0x0004 }, 3411 { 0x0a, 0, 0x0020 } 3412 }; 3413 3414 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3415 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3416 3417 /* Disable Early Tally Counter */ 3418 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3419 3420 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3421 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3422 3423 rtl_ephy_init(tp, e_info_8105e_1); 3424 3425 rtl_pcie_state_l2l3_disable(tp); 3426 } 3427 3428 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3429 { 3430 rtl_hw_start_8105e_1(tp); 3431 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3432 } 3433 3434 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3435 { 3436 static const struct ephy_info e_info_8402[] = { 3437 { 0x19, 0xffff, 0xff64 }, 3438 { 0x1e, 0, 0x4000 } 3439 }; 3440 3441 rtl_set_def_aspm_entry_latency(tp); 3442 3443 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3444 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3445 3446 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3447 3448 rtl_ephy_init(tp, e_info_8402); 3449 3450 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3451 rtl_reset_packet_filter(tp); 3452 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3453 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3454 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3455 3456 /* disable EEE */ 3457 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3458 3459 rtl_pcie_state_l2l3_disable(tp); 3460 } 3461 3462 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3463 { 3464 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3465 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3466 3467 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3468 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3469 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3470 3471 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3472 rtl_set_aspm_entry_latency(tp, 0x2f); 3473 3474 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3475 3476 /* disable EEE */ 3477 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3478 3479 rtl_pcie_state_l2l3_disable(tp); 3480 } 3481 3482 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3483 { 3484 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3485 } 3486 3487 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3488 { 3489 rtl_pcie_state_l2l3_disable(tp); 3490 3491 RTL_W16(tp, 0x382, 0x221b); 3492 RTL_W8(tp, 0x4500, 0); 3493 RTL_W16(tp, 0x4800, 0); 3494 3495 /* disable UPS */ 3496 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3497 3498 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3499 3500 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3501 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3502 3503 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3504 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3505 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3506 3507 /* disable new tx descriptor format */ 3508 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3509 3510 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3511 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3512 else 3513 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3514 3515 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3516 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3517 else 3518 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3519 3520 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3521 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3522 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3523 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3524 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3525 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3526 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3527 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3528 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3529 3530 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3531 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3532 udelay(1); 3533 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3534 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3535 3536 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3537 3538 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3539 3540 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3541 rtl8125b_config_eee_mac(tp); 3542 else 3543 rtl8125a_config_eee_mac(tp); 3544 3545 rtl_disable_rxdvgate(tp); 3546 } 3547 3548 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3549 { 3550 static const struct ephy_info e_info_8125a_2[] = { 3551 { 0x04, 0xffff, 0xd000 }, 3552 { 0x0a, 0xffff, 0x8653 }, 3553 { 0x23, 0xffff, 0xab66 }, 3554 { 0x20, 0xffff, 0x9455 }, 3555 { 0x21, 0xffff, 0x99ff }, 3556 { 0x29, 0xffff, 0xfe04 }, 3557 3558 { 0x44, 0xffff, 0xd000 }, 3559 { 0x4a, 0xffff, 0x8653 }, 3560 { 0x63, 0xffff, 0xab66 }, 3561 { 0x60, 0xffff, 0x9455 }, 3562 { 0x61, 0xffff, 0x99ff }, 3563 { 0x69, 0xffff, 0xfe04 }, 3564 }; 3565 3566 rtl_set_def_aspm_entry_latency(tp); 3567 rtl_ephy_init(tp, e_info_8125a_2); 3568 rtl_hw_start_8125_common(tp); 3569 } 3570 3571 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3572 { 3573 static const struct ephy_info e_info_8125b[] = { 3574 { 0x0b, 0xffff, 0xa908 }, 3575 { 0x1e, 0xffff, 0x20eb }, 3576 { 0x4b, 0xffff, 0xa908 }, 3577 { 0x5e, 0xffff, 0x20eb }, 3578 { 0x22, 0x0030, 0x0020 }, 3579 { 0x62, 0x0030, 0x0020 }, 3580 }; 3581 3582 rtl_set_def_aspm_entry_latency(tp); 3583 rtl_ephy_init(tp, e_info_8125b); 3584 rtl_hw_start_8125_common(tp); 3585 } 3586 3587 static void rtl_hw_config(struct rtl8169_private *tp) 3588 { 3589 static const rtl_generic_fct hw_configs[] = { 3590 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3591 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3592 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3593 [RTL_GIGA_MAC_VER_10] = NULL, 3594 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3595 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3596 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3597 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3598 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3599 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3600 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3601 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3602 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3603 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3604 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3605 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3606 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3607 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3608 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3609 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3610 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3611 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3612 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3613 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3614 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3615 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3616 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3617 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3618 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3619 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3620 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3621 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3622 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3623 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3624 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3625 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3626 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3627 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3628 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3629 }; 3630 3631 if (hw_configs[tp->mac_version]) 3632 hw_configs[tp->mac_version](tp); 3633 } 3634 3635 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3636 { 3637 int i; 3638 3639 /* disable interrupt coalescing */ 3640 for (i = 0xa00; i < 0xb00; i += 4) 3641 RTL_W32(tp, i, 0); 3642 3643 rtl_hw_config(tp); 3644 } 3645 3646 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3647 { 3648 if (rtl_is_8168evl_up(tp)) 3649 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3650 else 3651 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3652 3653 rtl_hw_config(tp); 3654 3655 /* disable interrupt coalescing */ 3656 RTL_W16(tp, IntrMitigate, 0x0000); 3657 } 3658 3659 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3660 { 3661 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3662 3663 tp->cp_cmd |= PCIMulRW; 3664 3665 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3666 tp->mac_version == RTL_GIGA_MAC_VER_03) 3667 tp->cp_cmd |= EnAnaPLL; 3668 3669 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3670 3671 rtl8169_set_magic_reg(tp); 3672 3673 /* disable interrupt coalescing */ 3674 RTL_W16(tp, IntrMitigate, 0x0000); 3675 } 3676 3677 static void rtl_hw_start(struct rtl8169_private *tp) 3678 { 3679 rtl_unlock_config_regs(tp); 3680 /* disable aspm and clock request before ephy access */ 3681 rtl_hw_aspm_clkreq_enable(tp, false); 3682 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3683 3684 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3685 rtl_hw_start_8169(tp); 3686 else if (rtl_is_8125(tp)) 3687 rtl_hw_start_8125(tp); 3688 else 3689 rtl_hw_start_8168(tp); 3690 3691 rtl_enable_exit_l1(tp); 3692 rtl_hw_aspm_clkreq_enable(tp, true); 3693 rtl_set_rx_max_size(tp); 3694 rtl_set_rx_tx_desc_registers(tp); 3695 rtl_lock_config_regs(tp); 3696 3697 rtl_jumbo_config(tp); 3698 3699 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3700 rtl_pci_commit(tp); 3701 3702 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3703 rtl_init_rxcfg(tp); 3704 rtl_set_tx_config_registers(tp); 3705 rtl_set_rx_config_features(tp, tp->dev->features); 3706 rtl_set_rx_mode(tp->dev); 3707 rtl_irq_enable(tp); 3708 } 3709 3710 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3711 { 3712 struct rtl8169_private *tp = netdev_priv(dev); 3713 3714 dev->mtu = new_mtu; 3715 netdev_update_features(dev); 3716 rtl_jumbo_config(tp); 3717 3718 switch (tp->mac_version) { 3719 case RTL_GIGA_MAC_VER_61: 3720 case RTL_GIGA_MAC_VER_63: 3721 rtl8125_set_eee_txidle_timer(tp); 3722 break; 3723 default: 3724 break; 3725 } 3726 3727 return 0; 3728 } 3729 3730 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3731 { 3732 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3733 3734 desc->opts2 = 0; 3735 /* Force memory writes to complete before releasing descriptor */ 3736 dma_wmb(); 3737 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3738 } 3739 3740 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3741 struct RxDesc *desc) 3742 { 3743 struct device *d = tp_to_dev(tp); 3744 int node = dev_to_node(d); 3745 dma_addr_t mapping; 3746 struct page *data; 3747 3748 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3749 if (!data) 3750 return NULL; 3751 3752 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3753 if (unlikely(dma_mapping_error(d, mapping))) { 3754 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3755 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3756 return NULL; 3757 } 3758 3759 desc->addr = cpu_to_le64(mapping); 3760 rtl8169_mark_to_asic(desc); 3761 3762 return data; 3763 } 3764 3765 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3766 { 3767 int i; 3768 3769 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3770 dma_unmap_page(tp_to_dev(tp), 3771 le64_to_cpu(tp->RxDescArray[i].addr), 3772 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3773 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3774 tp->Rx_databuff[i] = NULL; 3775 tp->RxDescArray[i].addr = 0; 3776 tp->RxDescArray[i].opts1 = 0; 3777 } 3778 } 3779 3780 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3781 { 3782 int i; 3783 3784 for (i = 0; i < NUM_RX_DESC; i++) { 3785 struct page *data; 3786 3787 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3788 if (!data) { 3789 rtl8169_rx_clear(tp); 3790 return -ENOMEM; 3791 } 3792 tp->Rx_databuff[i] = data; 3793 } 3794 3795 /* mark as last descriptor in the ring */ 3796 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3797 3798 return 0; 3799 } 3800 3801 static int rtl8169_init_ring(struct rtl8169_private *tp) 3802 { 3803 rtl8169_init_ring_indexes(tp); 3804 3805 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3806 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3807 3808 return rtl8169_rx_fill(tp); 3809 } 3810 3811 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3812 { 3813 struct ring_info *tx_skb = tp->tx_skb + entry; 3814 struct TxDesc *desc = tp->TxDescArray + entry; 3815 3816 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3817 DMA_TO_DEVICE); 3818 memset(desc, 0, sizeof(*desc)); 3819 memset(tx_skb, 0, sizeof(*tx_skb)); 3820 } 3821 3822 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3823 unsigned int n) 3824 { 3825 unsigned int i; 3826 3827 for (i = 0; i < n; i++) { 3828 unsigned int entry = (start + i) % NUM_TX_DESC; 3829 struct ring_info *tx_skb = tp->tx_skb + entry; 3830 unsigned int len = tx_skb->len; 3831 3832 if (len) { 3833 struct sk_buff *skb = tx_skb->skb; 3834 3835 rtl8169_unmap_tx_skb(tp, entry); 3836 if (skb) 3837 dev_consume_skb_any(skb); 3838 } 3839 } 3840 } 3841 3842 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3843 { 3844 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3845 netdev_reset_queue(tp->dev); 3846 } 3847 3848 static void rtl8169_cleanup(struct rtl8169_private *tp) 3849 { 3850 napi_disable(&tp->napi); 3851 3852 /* Give a racing hard_start_xmit a few cycles to complete. */ 3853 synchronize_net(); 3854 3855 /* Disable interrupts */ 3856 rtl8169_irq_mask_and_ack(tp); 3857 3858 rtl_rx_close(tp); 3859 3860 switch (tp->mac_version) { 3861 case RTL_GIGA_MAC_VER_28: 3862 case RTL_GIGA_MAC_VER_31: 3863 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3864 break; 3865 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3866 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3867 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3868 break; 3869 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3870 rtl_enable_rxdvgate(tp); 3871 fsleep(2000); 3872 break; 3873 default: 3874 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3875 fsleep(100); 3876 break; 3877 } 3878 3879 rtl_hw_reset(tp); 3880 3881 rtl8169_tx_clear(tp); 3882 rtl8169_init_ring_indexes(tp); 3883 } 3884 3885 static void rtl_reset_work(struct rtl8169_private *tp) 3886 { 3887 int i; 3888 3889 netif_stop_queue(tp->dev); 3890 3891 rtl8169_cleanup(tp); 3892 3893 for (i = 0; i < NUM_RX_DESC; i++) 3894 rtl8169_mark_to_asic(tp->RxDescArray + i); 3895 3896 napi_enable(&tp->napi); 3897 rtl_hw_start(tp); 3898 } 3899 3900 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3901 { 3902 struct rtl8169_private *tp = netdev_priv(dev); 3903 3904 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 3905 } 3906 3907 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3908 void *addr, unsigned int entry, bool desc_own) 3909 { 3910 struct TxDesc *txd = tp->TxDescArray + entry; 3911 struct device *d = tp_to_dev(tp); 3912 dma_addr_t mapping; 3913 u32 opts1; 3914 int ret; 3915 3916 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3917 ret = dma_mapping_error(d, mapping); 3918 if (unlikely(ret)) { 3919 if (net_ratelimit()) 3920 netdev_err(tp->dev, "Failed to map TX data!\n"); 3921 return ret; 3922 } 3923 3924 txd->addr = cpu_to_le64(mapping); 3925 txd->opts2 = cpu_to_le32(opts[1]); 3926 3927 opts1 = opts[0] | len; 3928 if (entry == NUM_TX_DESC - 1) 3929 opts1 |= RingEnd; 3930 if (desc_own) 3931 opts1 |= DescOwn; 3932 txd->opts1 = cpu_to_le32(opts1); 3933 3934 tp->tx_skb[entry].len = len; 3935 3936 return 0; 3937 } 3938 3939 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3940 const u32 *opts, unsigned int entry) 3941 { 3942 struct skb_shared_info *info = skb_shinfo(skb); 3943 unsigned int cur_frag; 3944 3945 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 3946 const skb_frag_t *frag = info->frags + cur_frag; 3947 void *addr = skb_frag_address(frag); 3948 u32 len = skb_frag_size(frag); 3949 3950 entry = (entry + 1) % NUM_TX_DESC; 3951 3952 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 3953 goto err_out; 3954 } 3955 3956 return 0; 3957 3958 err_out: 3959 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 3960 return -EIO; 3961 } 3962 3963 static bool rtl_skb_is_udp(struct sk_buff *skb) 3964 { 3965 int no = skb_network_offset(skb); 3966 struct ipv6hdr *i6h, _i6h; 3967 struct iphdr *ih, _ih; 3968 3969 switch (vlan_get_protocol(skb)) { 3970 case htons(ETH_P_IP): 3971 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 3972 return ih && ih->protocol == IPPROTO_UDP; 3973 case htons(ETH_P_IPV6): 3974 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 3975 return i6h && i6h->nexthdr == IPPROTO_UDP; 3976 default: 3977 return false; 3978 } 3979 } 3980 3981 #define RTL_MIN_PATCH_LEN 47 3982 3983 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 3984 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 3985 struct sk_buff *skb) 3986 { 3987 unsigned int padto = 0, len = skb->len; 3988 3989 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 3990 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 3991 unsigned int trans_data_len = skb_tail_pointer(skb) - 3992 skb_transport_header(skb); 3993 3994 if (trans_data_len >= offsetof(struct udphdr, len) && 3995 trans_data_len < RTL_MIN_PATCH_LEN) { 3996 u16 dest = ntohs(udp_hdr(skb)->dest); 3997 3998 /* dest is a standard PTP port */ 3999 if (dest == 319 || dest == 320) 4000 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4001 } 4002 4003 if (trans_data_len < sizeof(struct udphdr)) 4004 padto = max_t(unsigned int, padto, 4005 len + sizeof(struct udphdr) - trans_data_len); 4006 } 4007 4008 return padto; 4009 } 4010 4011 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4012 struct sk_buff *skb) 4013 { 4014 unsigned int padto; 4015 4016 padto = rtl8125_quirk_udp_padto(tp, skb); 4017 4018 switch (tp->mac_version) { 4019 case RTL_GIGA_MAC_VER_34: 4020 case RTL_GIGA_MAC_VER_61: 4021 case RTL_GIGA_MAC_VER_63: 4022 padto = max_t(unsigned int, padto, ETH_ZLEN); 4023 break; 4024 default: 4025 break; 4026 } 4027 4028 return padto; 4029 } 4030 4031 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4032 { 4033 u32 mss = skb_shinfo(skb)->gso_size; 4034 4035 if (mss) { 4036 opts[0] |= TD_LSO; 4037 opts[0] |= mss << TD0_MSS_SHIFT; 4038 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4039 const struct iphdr *ip = ip_hdr(skb); 4040 4041 if (ip->protocol == IPPROTO_TCP) 4042 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4043 else if (ip->protocol == IPPROTO_UDP) 4044 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4045 else 4046 WARN_ON_ONCE(1); 4047 } 4048 } 4049 4050 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4051 struct sk_buff *skb, u32 *opts) 4052 { 4053 struct skb_shared_info *shinfo = skb_shinfo(skb); 4054 u32 mss = shinfo->gso_size; 4055 4056 if (mss) { 4057 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4058 opts[0] |= TD1_GTSENV4; 4059 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4060 if (skb_cow_head(skb, 0)) 4061 return false; 4062 4063 tcp_v6_gso_csum_prep(skb); 4064 opts[0] |= TD1_GTSENV6; 4065 } else { 4066 WARN_ON_ONCE(1); 4067 } 4068 4069 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4070 opts[1] |= mss << TD1_MSS_SHIFT; 4071 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4072 u8 ip_protocol; 4073 4074 switch (vlan_get_protocol(skb)) { 4075 case htons(ETH_P_IP): 4076 opts[1] |= TD1_IPv4_CS; 4077 ip_protocol = ip_hdr(skb)->protocol; 4078 break; 4079 4080 case htons(ETH_P_IPV6): 4081 opts[1] |= TD1_IPv6_CS; 4082 ip_protocol = ipv6_hdr(skb)->nexthdr; 4083 break; 4084 4085 default: 4086 ip_protocol = IPPROTO_RAW; 4087 break; 4088 } 4089 4090 if (ip_protocol == IPPROTO_TCP) 4091 opts[1] |= TD1_TCP_CS; 4092 else if (ip_protocol == IPPROTO_UDP) 4093 opts[1] |= TD1_UDP_CS; 4094 else 4095 WARN_ON_ONCE(1); 4096 4097 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4098 } else { 4099 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4100 4101 /* skb_padto would free the skb on error */ 4102 return !__skb_put_padto(skb, padto, false); 4103 } 4104 4105 return true; 4106 } 4107 4108 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4109 { 4110 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4111 } 4112 4113 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4114 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4115 { 4116 switch (tp->mac_version) { 4117 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4118 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4119 return false; 4120 default: 4121 return true; 4122 } 4123 } 4124 4125 static void rtl8169_doorbell(struct rtl8169_private *tp) 4126 { 4127 if (rtl_is_8125(tp)) 4128 RTL_W16(tp, TxPoll_8125, BIT(0)); 4129 else 4130 RTL_W8(tp, TxPoll, NPQ); 4131 } 4132 4133 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4134 struct net_device *dev) 4135 { 4136 unsigned int frags = skb_shinfo(skb)->nr_frags; 4137 struct rtl8169_private *tp = netdev_priv(dev); 4138 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4139 struct TxDesc *txd_first, *txd_last; 4140 bool stop_queue, door_bell; 4141 u32 opts[2]; 4142 4143 if (unlikely(!rtl_tx_slots_avail(tp))) { 4144 if (net_ratelimit()) 4145 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4146 goto err_stop_0; 4147 } 4148 4149 opts[1] = rtl8169_tx_vlan_tag(skb); 4150 opts[0] = 0; 4151 4152 if (!rtl_chip_supports_csum_v2(tp)) 4153 rtl8169_tso_csum_v1(skb, opts); 4154 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4155 goto err_dma_0; 4156 4157 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4158 entry, false))) 4159 goto err_dma_0; 4160 4161 txd_first = tp->TxDescArray + entry; 4162 4163 if (frags) { 4164 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4165 goto err_dma_1; 4166 entry = (entry + frags) % NUM_TX_DESC; 4167 } 4168 4169 txd_last = tp->TxDescArray + entry; 4170 txd_last->opts1 |= cpu_to_le32(LastFrag); 4171 tp->tx_skb[entry].skb = skb; 4172 4173 skb_tx_timestamp(skb); 4174 4175 /* Force memory writes to complete before releasing descriptor */ 4176 dma_wmb(); 4177 4178 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4179 4180 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4181 4182 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4183 smp_wmb(); 4184 4185 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4186 4187 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4188 R8169_TX_STOP_THRS, 4189 R8169_TX_START_THRS); 4190 if (door_bell || stop_queue) 4191 rtl8169_doorbell(tp); 4192 4193 return NETDEV_TX_OK; 4194 4195 err_dma_1: 4196 rtl8169_unmap_tx_skb(tp, entry); 4197 err_dma_0: 4198 dev_kfree_skb_any(skb); 4199 dev->stats.tx_dropped++; 4200 return NETDEV_TX_OK; 4201 4202 err_stop_0: 4203 netif_stop_queue(dev); 4204 dev->stats.tx_dropped++; 4205 return NETDEV_TX_BUSY; 4206 } 4207 4208 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4209 { 4210 struct skb_shared_info *info = skb_shinfo(skb); 4211 unsigned int nr_frags = info->nr_frags; 4212 4213 if (!nr_frags) 4214 return UINT_MAX; 4215 4216 return skb_frag_size(info->frags + nr_frags - 1); 4217 } 4218 4219 /* Workaround for hw issues with TSO on RTL8168evl */ 4220 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4221 netdev_features_t features) 4222 { 4223 /* IPv4 header has options field */ 4224 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4225 ip_hdrlen(skb) > sizeof(struct iphdr)) 4226 features &= ~NETIF_F_ALL_TSO; 4227 4228 /* IPv4 TCP header has options field */ 4229 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4230 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4231 features &= ~NETIF_F_ALL_TSO; 4232 4233 else if (rtl_last_frag_len(skb) <= 6) 4234 features &= ~NETIF_F_ALL_TSO; 4235 4236 return features; 4237 } 4238 4239 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4240 struct net_device *dev, 4241 netdev_features_t features) 4242 { 4243 struct rtl8169_private *tp = netdev_priv(dev); 4244 4245 if (skb_is_gso(skb)) { 4246 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4247 features = rtl8168evl_fix_tso(skb, features); 4248 4249 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4250 rtl_chip_supports_csum_v2(tp)) 4251 features &= ~NETIF_F_ALL_TSO; 4252 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4253 /* work around hw bug on some chip versions */ 4254 if (skb->len < ETH_ZLEN) 4255 features &= ~NETIF_F_CSUM_MASK; 4256 4257 if (rtl_quirk_packet_padto(tp, skb)) 4258 features &= ~NETIF_F_CSUM_MASK; 4259 4260 if (skb_transport_offset(skb) > TCPHO_MAX && 4261 rtl_chip_supports_csum_v2(tp)) 4262 features &= ~NETIF_F_CSUM_MASK; 4263 } 4264 4265 return vlan_features_check(skb, features); 4266 } 4267 4268 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4269 { 4270 struct rtl8169_private *tp = netdev_priv(dev); 4271 struct pci_dev *pdev = tp->pci_dev; 4272 int pci_status_errs; 4273 u16 pci_cmd; 4274 4275 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4276 4277 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4278 4279 if (net_ratelimit()) 4280 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4281 pci_cmd, pci_status_errs); 4282 4283 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4284 } 4285 4286 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4287 int budget) 4288 { 4289 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4290 struct sk_buff *skb; 4291 4292 dirty_tx = tp->dirty_tx; 4293 4294 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4295 unsigned int entry = dirty_tx % NUM_TX_DESC; 4296 u32 status; 4297 4298 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4299 if (status & DescOwn) 4300 break; 4301 4302 skb = tp->tx_skb[entry].skb; 4303 rtl8169_unmap_tx_skb(tp, entry); 4304 4305 if (skb) { 4306 pkts_compl++; 4307 bytes_compl += skb->len; 4308 napi_consume_skb(skb, budget); 4309 } 4310 dirty_tx++; 4311 } 4312 4313 if (tp->dirty_tx != dirty_tx) { 4314 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4315 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4316 4317 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4318 rtl_tx_slots_avail(tp), 4319 R8169_TX_START_THRS); 4320 /* 4321 * 8168 hack: TxPoll requests are lost when the Tx packets are 4322 * too close. Let's kick an extra TxPoll request when a burst 4323 * of start_xmit activity is detected (if it is not detected, 4324 * it is slow enough). -- FR 4325 * If skb is NULL then we come here again once a tx irq is 4326 * triggered after the last fragment is marked transmitted. 4327 */ 4328 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4329 rtl8169_doorbell(tp); 4330 } 4331 } 4332 4333 static inline int rtl8169_fragmented_frame(u32 status) 4334 { 4335 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4336 } 4337 4338 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4339 { 4340 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4341 4342 if (status == RxProtoTCP || status == RxProtoUDP) 4343 skb->ip_summed = CHECKSUM_UNNECESSARY; 4344 else 4345 skb_checksum_none_assert(skb); 4346 } 4347 4348 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4349 { 4350 struct device *d = tp_to_dev(tp); 4351 int count; 4352 4353 for (count = 0; count < budget; count++, tp->cur_rx++) { 4354 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4355 struct RxDesc *desc = tp->RxDescArray + entry; 4356 struct sk_buff *skb; 4357 const void *rx_buf; 4358 dma_addr_t addr; 4359 u32 status; 4360 4361 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4362 if (status & DescOwn) 4363 break; 4364 4365 /* This barrier is needed to keep us from reading 4366 * any other fields out of the Rx descriptor until 4367 * we know the status of DescOwn 4368 */ 4369 dma_rmb(); 4370 4371 if (unlikely(status & RxRES)) { 4372 if (net_ratelimit()) 4373 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4374 status); 4375 dev->stats.rx_errors++; 4376 if (status & (RxRWT | RxRUNT)) 4377 dev->stats.rx_length_errors++; 4378 if (status & RxCRC) 4379 dev->stats.rx_crc_errors++; 4380 4381 if (!(dev->features & NETIF_F_RXALL)) 4382 goto release_descriptor; 4383 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4384 goto release_descriptor; 4385 } 4386 4387 pkt_size = status & GENMASK(13, 0); 4388 if (likely(!(dev->features & NETIF_F_RXFCS))) 4389 pkt_size -= ETH_FCS_LEN; 4390 4391 /* The driver does not support incoming fragmented frames. 4392 * They are seen as a symptom of over-mtu sized frames. 4393 */ 4394 if (unlikely(rtl8169_fragmented_frame(status))) { 4395 dev->stats.rx_dropped++; 4396 dev->stats.rx_length_errors++; 4397 goto release_descriptor; 4398 } 4399 4400 skb = napi_alloc_skb(&tp->napi, pkt_size); 4401 if (unlikely(!skb)) { 4402 dev->stats.rx_dropped++; 4403 goto release_descriptor; 4404 } 4405 4406 addr = le64_to_cpu(desc->addr); 4407 rx_buf = page_address(tp->Rx_databuff[entry]); 4408 4409 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4410 prefetch(rx_buf); 4411 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4412 skb->tail += pkt_size; 4413 skb->len = pkt_size; 4414 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4415 4416 rtl8169_rx_csum(skb, status); 4417 skb->protocol = eth_type_trans(skb, dev); 4418 4419 rtl8169_rx_vlan_tag(desc, skb); 4420 4421 if (skb->pkt_type == PACKET_MULTICAST) 4422 dev->stats.multicast++; 4423 4424 napi_gro_receive(&tp->napi, skb); 4425 4426 dev_sw_netstats_rx_add(dev, pkt_size); 4427 release_descriptor: 4428 rtl8169_mark_to_asic(desc); 4429 } 4430 4431 return count; 4432 } 4433 4434 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4435 { 4436 struct rtl8169_private *tp = dev_instance; 4437 u32 status = rtl_get_events(tp); 4438 4439 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4440 return IRQ_NONE; 4441 4442 if (unlikely(status & SYSErr)) { 4443 rtl8169_pcierr_interrupt(tp->dev); 4444 goto out; 4445 } 4446 4447 if (status & LinkChg) 4448 phy_mac_interrupt(tp->phydev); 4449 4450 if (unlikely(status & RxFIFOOver && 4451 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4452 netif_stop_queue(tp->dev); 4453 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4454 } 4455 4456 if (napi_schedule_prep(&tp->napi)) { 4457 rtl_irq_disable(tp); 4458 __napi_schedule(&tp->napi); 4459 } 4460 out: 4461 rtl_ack_events(tp, status); 4462 4463 return IRQ_HANDLED; 4464 } 4465 4466 static void rtl_task(struct work_struct *work) 4467 { 4468 struct rtl8169_private *tp = 4469 container_of(work, struct rtl8169_private, wk.work); 4470 int ret; 4471 4472 rtnl_lock(); 4473 4474 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4475 goto out_unlock; 4476 4477 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4478 /* if chip isn't accessible, reset bus to revive it */ 4479 if (RTL_R32(tp, TxConfig) == ~0) { 4480 ret = pci_reset_bus(tp->pci_dev); 4481 if (ret < 0) { 4482 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4483 netif_device_detach(tp->dev); 4484 goto out_unlock; 4485 } 4486 } 4487 4488 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4489 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4490 PCIE_LINK_STATE_L0S); 4491 if (!ret) 4492 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4493 goto reset; 4494 } 4495 4496 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4497 reset: 4498 rtl_reset_work(tp); 4499 netif_wake_queue(tp->dev); 4500 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4501 rtl_reset_work(tp); 4502 } 4503 out_unlock: 4504 rtnl_unlock(); 4505 } 4506 4507 static int rtl8169_poll(struct napi_struct *napi, int budget) 4508 { 4509 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4510 struct net_device *dev = tp->dev; 4511 int work_done; 4512 4513 rtl_tx(dev, tp, budget); 4514 4515 work_done = rtl_rx(dev, tp, budget); 4516 4517 if (work_done < budget && napi_complete_done(napi, work_done)) 4518 rtl_irq_enable(tp); 4519 4520 return work_done; 4521 } 4522 4523 static void r8169_phylink_handler(struct net_device *ndev) 4524 { 4525 struct rtl8169_private *tp = netdev_priv(ndev); 4526 struct device *d = tp_to_dev(tp); 4527 4528 if (netif_carrier_ok(ndev)) { 4529 rtl_link_chg_patch(tp); 4530 pm_request_resume(d); 4531 netif_wake_queue(tp->dev); 4532 } else { 4533 /* In few cases rx is broken after link-down otherwise */ 4534 if (rtl_is_8125(tp)) 4535 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4536 pm_runtime_idle(d); 4537 } 4538 4539 phy_print_status(tp->phydev); 4540 } 4541 4542 static int r8169_phy_connect(struct rtl8169_private *tp) 4543 { 4544 struct phy_device *phydev = tp->phydev; 4545 phy_interface_t phy_mode; 4546 int ret; 4547 4548 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4549 PHY_INTERFACE_MODE_MII; 4550 4551 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4552 phy_mode); 4553 if (ret) 4554 return ret; 4555 4556 if (!tp->supports_gmii) 4557 phy_set_max_speed(phydev, SPEED_100); 4558 4559 phy_attached_info(phydev); 4560 4561 return 0; 4562 } 4563 4564 static void rtl8169_down(struct rtl8169_private *tp) 4565 { 4566 /* Clear all task flags */ 4567 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4568 4569 phy_stop(tp->phydev); 4570 4571 rtl8169_update_counters(tp); 4572 4573 pci_clear_master(tp->pci_dev); 4574 rtl_pci_commit(tp); 4575 4576 rtl8169_cleanup(tp); 4577 rtl_disable_exit_l1(tp); 4578 rtl_prepare_power_down(tp); 4579 4580 if (tp->dash_type != RTL_DASH_NONE) 4581 rtl8168_driver_stop(tp); 4582 } 4583 4584 static void rtl8169_up(struct rtl8169_private *tp) 4585 { 4586 if (tp->dash_type != RTL_DASH_NONE) 4587 rtl8168_driver_start(tp); 4588 4589 pci_set_master(tp->pci_dev); 4590 phy_init_hw(tp->phydev); 4591 phy_resume(tp->phydev); 4592 rtl8169_init_phy(tp); 4593 napi_enable(&tp->napi); 4594 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4595 rtl_reset_work(tp); 4596 4597 phy_start(tp->phydev); 4598 } 4599 4600 static int rtl8169_close(struct net_device *dev) 4601 { 4602 struct rtl8169_private *tp = netdev_priv(dev); 4603 struct pci_dev *pdev = tp->pci_dev; 4604 4605 pm_runtime_get_sync(&pdev->dev); 4606 4607 netif_stop_queue(dev); 4608 rtl8169_down(tp); 4609 rtl8169_rx_clear(tp); 4610 4611 cancel_work(&tp->wk.work); 4612 4613 free_irq(tp->irq, tp); 4614 4615 phy_disconnect(tp->phydev); 4616 4617 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4618 tp->RxPhyAddr); 4619 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4620 tp->TxPhyAddr); 4621 tp->TxDescArray = NULL; 4622 tp->RxDescArray = NULL; 4623 4624 pm_runtime_put_sync(&pdev->dev); 4625 4626 return 0; 4627 } 4628 4629 #ifdef CONFIG_NET_POLL_CONTROLLER 4630 static void rtl8169_netpoll(struct net_device *dev) 4631 { 4632 struct rtl8169_private *tp = netdev_priv(dev); 4633 4634 rtl8169_interrupt(tp->irq, tp); 4635 } 4636 #endif 4637 4638 static int rtl_open(struct net_device *dev) 4639 { 4640 struct rtl8169_private *tp = netdev_priv(dev); 4641 struct pci_dev *pdev = tp->pci_dev; 4642 unsigned long irqflags; 4643 int retval = -ENOMEM; 4644 4645 pm_runtime_get_sync(&pdev->dev); 4646 4647 /* 4648 * Rx and Tx descriptors needs 256 bytes alignment. 4649 * dma_alloc_coherent provides more. 4650 */ 4651 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4652 &tp->TxPhyAddr, GFP_KERNEL); 4653 if (!tp->TxDescArray) 4654 goto out; 4655 4656 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4657 &tp->RxPhyAddr, GFP_KERNEL); 4658 if (!tp->RxDescArray) 4659 goto err_free_tx_0; 4660 4661 retval = rtl8169_init_ring(tp); 4662 if (retval < 0) 4663 goto err_free_rx_1; 4664 4665 rtl_request_firmware(tp); 4666 4667 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4668 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4669 if (retval < 0) 4670 goto err_release_fw_2; 4671 4672 retval = r8169_phy_connect(tp); 4673 if (retval) 4674 goto err_free_irq; 4675 4676 rtl8169_up(tp); 4677 rtl8169_init_counter_offsets(tp); 4678 netif_start_queue(dev); 4679 out: 4680 pm_runtime_put_sync(&pdev->dev); 4681 4682 return retval; 4683 4684 err_free_irq: 4685 free_irq(tp->irq, tp); 4686 err_release_fw_2: 4687 rtl_release_firmware(tp); 4688 rtl8169_rx_clear(tp); 4689 err_free_rx_1: 4690 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4691 tp->RxPhyAddr); 4692 tp->RxDescArray = NULL; 4693 err_free_tx_0: 4694 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4695 tp->TxPhyAddr); 4696 tp->TxDescArray = NULL; 4697 goto out; 4698 } 4699 4700 static void 4701 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4702 { 4703 struct rtl8169_private *tp = netdev_priv(dev); 4704 struct pci_dev *pdev = tp->pci_dev; 4705 struct rtl8169_counters *counters = tp->counters; 4706 4707 pm_runtime_get_noresume(&pdev->dev); 4708 4709 netdev_stats_to_stats64(stats, &dev->stats); 4710 dev_fetch_sw_netstats(stats, dev->tstats); 4711 4712 /* 4713 * Fetch additional counter values missing in stats collected by driver 4714 * from tally counters. 4715 */ 4716 if (pm_runtime_active(&pdev->dev)) 4717 rtl8169_update_counters(tp); 4718 4719 /* 4720 * Subtract values fetched during initalization. 4721 * See rtl8169_init_counter_offsets for a description why we do that. 4722 */ 4723 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4724 le64_to_cpu(tp->tc_offset.tx_errors); 4725 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4726 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4727 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4728 le16_to_cpu(tp->tc_offset.tx_aborted); 4729 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4730 le16_to_cpu(tp->tc_offset.rx_missed); 4731 4732 pm_runtime_put_noidle(&pdev->dev); 4733 } 4734 4735 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4736 { 4737 netif_device_detach(tp->dev); 4738 4739 if (netif_running(tp->dev)) 4740 rtl8169_down(tp); 4741 } 4742 4743 static int rtl8169_runtime_resume(struct device *dev) 4744 { 4745 struct rtl8169_private *tp = dev_get_drvdata(dev); 4746 4747 rtl_rar_set(tp, tp->dev->dev_addr); 4748 __rtl8169_set_wol(tp, tp->saved_wolopts); 4749 4750 if (tp->TxDescArray) 4751 rtl8169_up(tp); 4752 4753 netif_device_attach(tp->dev); 4754 4755 return 0; 4756 } 4757 4758 static int rtl8169_suspend(struct device *device) 4759 { 4760 struct rtl8169_private *tp = dev_get_drvdata(device); 4761 4762 rtnl_lock(); 4763 rtl8169_net_suspend(tp); 4764 if (!device_may_wakeup(tp_to_dev(tp))) 4765 clk_disable_unprepare(tp->clk); 4766 rtnl_unlock(); 4767 4768 return 0; 4769 } 4770 4771 static int rtl8169_resume(struct device *device) 4772 { 4773 struct rtl8169_private *tp = dev_get_drvdata(device); 4774 4775 if (!device_may_wakeup(tp_to_dev(tp))) 4776 clk_prepare_enable(tp->clk); 4777 4778 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4779 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4780 rtl_init_rxcfg(tp); 4781 4782 return rtl8169_runtime_resume(device); 4783 } 4784 4785 static int rtl8169_runtime_suspend(struct device *device) 4786 { 4787 struct rtl8169_private *tp = dev_get_drvdata(device); 4788 4789 if (!tp->TxDescArray) { 4790 netif_device_detach(tp->dev); 4791 return 0; 4792 } 4793 4794 rtnl_lock(); 4795 __rtl8169_set_wol(tp, WAKE_PHY); 4796 rtl8169_net_suspend(tp); 4797 rtnl_unlock(); 4798 4799 return 0; 4800 } 4801 4802 static int rtl8169_runtime_idle(struct device *device) 4803 { 4804 struct rtl8169_private *tp = dev_get_drvdata(device); 4805 4806 if (tp->dash_enabled) 4807 return -EBUSY; 4808 4809 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4810 pm_schedule_suspend(device, 10000); 4811 4812 return -EBUSY; 4813 } 4814 4815 static const struct dev_pm_ops rtl8169_pm_ops = { 4816 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4817 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4818 rtl8169_runtime_idle) 4819 }; 4820 4821 static void rtl_shutdown(struct pci_dev *pdev) 4822 { 4823 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4824 4825 rtnl_lock(); 4826 rtl8169_net_suspend(tp); 4827 rtnl_unlock(); 4828 4829 /* Restore original MAC address */ 4830 rtl_rar_set(tp, tp->dev->perm_addr); 4831 4832 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 4833 pci_wake_from_d3(pdev, tp->saved_wolopts); 4834 pci_set_power_state(pdev, PCI_D3hot); 4835 } 4836 } 4837 4838 static void rtl_remove_one(struct pci_dev *pdev) 4839 { 4840 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4841 4842 if (pci_dev_run_wake(pdev)) 4843 pm_runtime_get_noresume(&pdev->dev); 4844 4845 cancel_work_sync(&tp->wk.work); 4846 4847 unregister_netdev(tp->dev); 4848 4849 if (tp->dash_type != RTL_DASH_NONE) 4850 rtl8168_driver_stop(tp); 4851 4852 rtl_release_firmware(tp); 4853 4854 /* restore original MAC address */ 4855 rtl_rar_set(tp, tp->dev->perm_addr); 4856 } 4857 4858 static const struct net_device_ops rtl_netdev_ops = { 4859 .ndo_open = rtl_open, 4860 .ndo_stop = rtl8169_close, 4861 .ndo_get_stats64 = rtl8169_get_stats64, 4862 .ndo_start_xmit = rtl8169_start_xmit, 4863 .ndo_features_check = rtl8169_features_check, 4864 .ndo_tx_timeout = rtl8169_tx_timeout, 4865 .ndo_validate_addr = eth_validate_addr, 4866 .ndo_change_mtu = rtl8169_change_mtu, 4867 .ndo_fix_features = rtl8169_fix_features, 4868 .ndo_set_features = rtl8169_set_features, 4869 .ndo_set_mac_address = rtl_set_mac_address, 4870 .ndo_eth_ioctl = phy_do_ioctl_running, 4871 .ndo_set_rx_mode = rtl_set_rx_mode, 4872 #ifdef CONFIG_NET_POLL_CONTROLLER 4873 .ndo_poll_controller = rtl8169_netpoll, 4874 #endif 4875 4876 }; 4877 4878 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4879 { 4880 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4881 4882 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4883 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4884 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4885 /* special workaround needed */ 4886 tp->irq_mask |= RxFIFOOver; 4887 else 4888 tp->irq_mask |= RxOverflow; 4889 } 4890 4891 static int rtl_alloc_irq(struct rtl8169_private *tp) 4892 { 4893 unsigned int flags; 4894 4895 switch (tp->mac_version) { 4896 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4897 rtl_unlock_config_regs(tp); 4898 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4899 rtl_lock_config_regs(tp); 4900 fallthrough; 4901 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4902 flags = PCI_IRQ_LEGACY; 4903 break; 4904 default: 4905 flags = PCI_IRQ_ALL_TYPES; 4906 break; 4907 } 4908 4909 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4910 } 4911 4912 static void rtl_read_mac_address(struct rtl8169_private *tp, 4913 u8 mac_addr[ETH_ALEN]) 4914 { 4915 /* Get MAC address */ 4916 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 4917 u32 value; 4918 4919 value = rtl_eri_read(tp, 0xe0); 4920 put_unaligned_le32(value, mac_addr); 4921 value = rtl_eri_read(tp, 0xe4); 4922 put_unaligned_le16(value, mac_addr + 4); 4923 } else if (rtl_is_8125(tp)) { 4924 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 4925 } 4926 } 4927 4928 DECLARE_RTL_COND(rtl_link_list_ready_cond) 4929 { 4930 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 4931 } 4932 4933 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 4934 { 4935 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 4936 } 4937 4938 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 4939 { 4940 struct rtl8169_private *tp = mii_bus->priv; 4941 4942 if (phyaddr > 0) 4943 return -ENODEV; 4944 4945 return rtl_readphy(tp, phyreg); 4946 } 4947 4948 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 4949 int phyreg, u16 val) 4950 { 4951 struct rtl8169_private *tp = mii_bus->priv; 4952 4953 if (phyaddr > 0) 4954 return -ENODEV; 4955 4956 rtl_writephy(tp, phyreg, val); 4957 4958 return 0; 4959 } 4960 4961 static int r8169_mdio_register(struct rtl8169_private *tp) 4962 { 4963 struct pci_dev *pdev = tp->pci_dev; 4964 struct mii_bus *new_bus; 4965 int ret; 4966 4967 new_bus = devm_mdiobus_alloc(&pdev->dev); 4968 if (!new_bus) 4969 return -ENOMEM; 4970 4971 new_bus->name = "r8169"; 4972 new_bus->priv = tp; 4973 new_bus->parent = &pdev->dev; 4974 new_bus->irq[0] = PHY_MAC_INTERRUPT; 4975 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 4976 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 4977 4978 new_bus->read = r8169_mdio_read_reg; 4979 new_bus->write = r8169_mdio_write_reg; 4980 4981 ret = devm_mdiobus_register(&pdev->dev, new_bus); 4982 if (ret) 4983 return ret; 4984 4985 tp->phydev = mdiobus_get_phy(new_bus, 0); 4986 if (!tp->phydev) { 4987 return -ENODEV; 4988 } else if (!tp->phydev->drv) { 4989 /* Most chip versions fail with the genphy driver. 4990 * Therefore ensure that the dedicated PHY driver is loaded. 4991 */ 4992 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 4993 tp->phydev->phy_id); 4994 return -EUNATCH; 4995 } 4996 4997 tp->phydev->mac_managed_pm = true; 4998 4999 phy_support_asym_pause(tp->phydev); 5000 5001 /* PHY will be woken up in rtl_open() */ 5002 phy_suspend(tp->phydev); 5003 5004 return 0; 5005 } 5006 5007 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5008 { 5009 rtl_enable_rxdvgate(tp); 5010 5011 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5012 msleep(1); 5013 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5014 5015 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5016 r8168g_wait_ll_share_fifo_ready(tp); 5017 5018 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5019 r8168g_wait_ll_share_fifo_ready(tp); 5020 } 5021 5022 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5023 { 5024 rtl_enable_rxdvgate(tp); 5025 5026 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5027 msleep(1); 5028 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5029 5030 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5031 r8168g_wait_ll_share_fifo_ready(tp); 5032 5033 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5034 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5035 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5036 r8168g_wait_ll_share_fifo_ready(tp); 5037 } 5038 5039 static void rtl_hw_initialize(struct rtl8169_private *tp) 5040 { 5041 switch (tp->mac_version) { 5042 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5043 rtl8168ep_stop_cmac(tp); 5044 fallthrough; 5045 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5046 rtl_hw_init_8168g(tp); 5047 break; 5048 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5049 rtl_hw_init_8125(tp); 5050 break; 5051 default: 5052 break; 5053 } 5054 } 5055 5056 static int rtl_jumbo_max(struct rtl8169_private *tp) 5057 { 5058 /* Non-GBit versions don't support jumbo frames */ 5059 if (!tp->supports_gmii) 5060 return 0; 5061 5062 switch (tp->mac_version) { 5063 /* RTL8169 */ 5064 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5065 return JUMBO_7K; 5066 /* RTL8168b */ 5067 case RTL_GIGA_MAC_VER_11: 5068 case RTL_GIGA_MAC_VER_17: 5069 return JUMBO_4K; 5070 /* RTL8168c */ 5071 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5072 return JUMBO_6K; 5073 default: 5074 return JUMBO_9K; 5075 } 5076 } 5077 5078 static void rtl_init_mac_address(struct rtl8169_private *tp) 5079 { 5080 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5081 struct net_device *dev = tp->dev; 5082 int rc; 5083 5084 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5085 if (!rc) 5086 goto done; 5087 5088 rtl_read_mac_address(tp, mac_addr); 5089 if (is_valid_ether_addr(mac_addr)) 5090 goto done; 5091 5092 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5093 if (is_valid_ether_addr(mac_addr)) 5094 goto done; 5095 5096 eth_random_addr(mac_addr); 5097 dev->addr_assign_type = NET_ADDR_RANDOM; 5098 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5099 done: 5100 eth_hw_addr_set(dev, mac_addr); 5101 rtl_rar_set(tp, mac_addr); 5102 } 5103 5104 /* register is set if system vendor successfully tested ASPM 1.2 */ 5105 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5106 { 5107 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5108 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5109 return true; 5110 5111 return false; 5112 } 5113 5114 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5115 { 5116 struct rtl8169_private *tp; 5117 int jumbo_max, region, rc; 5118 enum mac_version chipset; 5119 struct net_device *dev; 5120 u32 txconfig; 5121 u16 xid; 5122 5123 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5124 if (!dev) 5125 return -ENOMEM; 5126 5127 SET_NETDEV_DEV(dev, &pdev->dev); 5128 dev->netdev_ops = &rtl_netdev_ops; 5129 tp = netdev_priv(dev); 5130 tp->dev = dev; 5131 tp->pci_dev = pdev; 5132 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5133 tp->eee_adv = -1; 5134 tp->ocp_base = OCP_STD_PHY_BASE; 5135 5136 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5137 raw_spin_lock_init(&tp->config25_lock); 5138 raw_spin_lock_init(&tp->mac_ocp_lock); 5139 5140 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5141 struct pcpu_sw_netstats); 5142 if (!dev->tstats) 5143 return -ENOMEM; 5144 5145 /* Get the *optional* external "ether_clk" used on some boards */ 5146 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5147 if (IS_ERR(tp->clk)) 5148 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5149 5150 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5151 rc = pcim_enable_device(pdev); 5152 if (rc < 0) 5153 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5154 5155 if (pcim_set_mwi(pdev) < 0) 5156 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5157 5158 /* use first MMIO region */ 5159 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5160 if (region < 0) 5161 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5162 5163 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5164 if (rc < 0) 5165 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5166 5167 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5168 5169 txconfig = RTL_R32(tp, TxConfig); 5170 if (txconfig == ~0U) 5171 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5172 5173 xid = (txconfig >> 20) & 0xfcf; 5174 5175 /* Identify chip attached to board */ 5176 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5177 if (chipset == RTL_GIGA_MAC_NONE) 5178 return dev_err_probe(&pdev->dev, -ENODEV, 5179 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5180 xid); 5181 tp->mac_version = chipset; 5182 5183 /* Disable ASPM L1 as that cause random device stop working 5184 * problems as well as full system hangs for some PCIe devices users. 5185 */ 5186 if (rtl_aspm_is_safe(tp)) 5187 rc = 0; 5188 else 5189 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5190 tp->aspm_manageable = !rc; 5191 5192 tp->dash_type = rtl_get_dash_type(tp); 5193 tp->dash_enabled = rtl_dash_is_enabled(tp); 5194 5195 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5196 5197 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5198 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5199 dev->features |= NETIF_F_HIGHDMA; 5200 5201 rtl_init_rxcfg(tp); 5202 5203 rtl8169_irq_mask_and_ack(tp); 5204 5205 rtl_hw_initialize(tp); 5206 5207 rtl_hw_reset(tp); 5208 5209 rc = rtl_alloc_irq(tp); 5210 if (rc < 0) 5211 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5212 5213 tp->irq = pci_irq_vector(pdev, 0); 5214 5215 INIT_WORK(&tp->wk.work, rtl_task); 5216 5217 rtl_init_mac_address(tp); 5218 5219 dev->ethtool_ops = &rtl8169_ethtool_ops; 5220 5221 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5222 5223 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5224 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5225 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5226 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5227 5228 /* 5229 * Pretend we are using VLANs; This bypasses a nasty bug where 5230 * Interrupts stop flowing on high load on 8110SCd controllers. 5231 */ 5232 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5233 /* Disallow toggling */ 5234 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5235 5236 if (rtl_chip_supports_csum_v2(tp)) 5237 dev->hw_features |= NETIF_F_IPV6_CSUM; 5238 5239 dev->features |= dev->hw_features; 5240 5241 /* There has been a number of reports that using SG/TSO results in 5242 * tx timeouts. However for a lot of people SG/TSO works fine. 5243 * Therefore disable both features by default, but allow users to 5244 * enable them. Use at own risk! 5245 */ 5246 if (rtl_chip_supports_csum_v2(tp)) { 5247 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5248 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5249 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5250 } else { 5251 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5252 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5253 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5254 } 5255 5256 dev->hw_features |= NETIF_F_RXALL; 5257 dev->hw_features |= NETIF_F_RXFCS; 5258 5259 netdev_sw_irq_coalesce_default_on(dev); 5260 5261 /* configure chip for default features */ 5262 rtl8169_set_features(dev, dev->features); 5263 5264 if (!tp->dash_enabled) { 5265 rtl_set_d3_pll_down(tp, true); 5266 } else { 5267 rtl_set_d3_pll_down(tp, false); 5268 dev->wol_enabled = 1; 5269 } 5270 5271 jumbo_max = rtl_jumbo_max(tp); 5272 if (jumbo_max) 5273 dev->max_mtu = jumbo_max; 5274 5275 rtl_set_irq_mask(tp); 5276 5277 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5278 5279 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5280 &tp->counters_phys_addr, 5281 GFP_KERNEL); 5282 if (!tp->counters) 5283 return -ENOMEM; 5284 5285 pci_set_drvdata(pdev, tp); 5286 5287 rc = r8169_mdio_register(tp); 5288 if (rc) 5289 return rc; 5290 5291 rc = register_netdev(dev); 5292 if (rc) 5293 return rc; 5294 5295 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5296 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5297 5298 if (jumbo_max) 5299 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5300 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5301 "ok" : "ko"); 5302 5303 if (tp->dash_type != RTL_DASH_NONE) { 5304 netdev_info(dev, "DASH %s\n", 5305 tp->dash_enabled ? "enabled" : "disabled"); 5306 rtl8168_driver_start(tp); 5307 } 5308 5309 if (pci_dev_run_wake(pdev)) 5310 pm_runtime_put_sync(&pdev->dev); 5311 5312 return 0; 5313 } 5314 5315 static struct pci_driver rtl8169_pci_driver = { 5316 .name = KBUILD_MODNAME, 5317 .id_table = rtl8169_pci_tbl, 5318 .probe = rtl_init_one, 5319 .remove = rtl_remove_one, 5320 .shutdown = rtl_shutdown, 5321 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5322 }; 5323 5324 module_pci_driver(rtl8169_pci_driver); 5325