1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/hwmon.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/in.h> 23 #include <linux/io.h> 24 #include <linux/ip.h> 25 #include <linux/tcp.h> 26 #include <linux/interrupt.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/bitfield.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <linux/unaligned.h> 33 #include <net/ip6_checksum.h> 34 #include <net/netdev_queues.h> 35 36 #include "r8169.h" 37 #include "r8169_firmware.h" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 59 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" 60 #define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw" 61 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 62 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 63 64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 66 67 #define R8169_REGS_SIZE 256 68 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 69 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 70 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 73 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 74 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 75 76 #define OCP_STD_PHY_BASE 0xa400 77 78 #define RTL_CFG_NO_GBIT 1 79 80 /* write/read MMIO register */ 81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 87 88 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 92 93 static const struct { 94 const char *name; 95 const char *fw_name; 96 } rtl_chip_infos[] = { 97 /* PCI devices. */ 98 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 99 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 100 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 101 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 102 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 103 /* PCI-E devices. */ 104 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 106 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 107 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 108 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 109 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 111 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 117 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 118 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 119 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 122 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 124 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 125 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 126 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 127 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 128 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 129 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 130 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 131 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 132 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 133 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 134 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 135 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 136 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 137 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 138 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 139 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 140 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 141 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 142 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 143 [RTL_GIGA_MAC_VER_64] = {"RTL8125D", FIRMWARE_8125D_1}, 144 [RTL_GIGA_MAC_VER_65] = {"RTL8125D", FIRMWARE_8125D_2}, 145 [RTL_GIGA_MAC_VER_70] = {"RTL8126A", FIRMWARE_8126A_2}, 146 [RTL_GIGA_MAC_VER_71] = {"RTL8126A", FIRMWARE_8126A_3}, 147 }; 148 149 static const struct pci_device_id rtl8169_pci_tbl[] = { 150 { PCI_VDEVICE(REALTEK, 0x2502) }, 151 { PCI_VDEVICE(REALTEK, 0x2600) }, 152 { PCI_VDEVICE(REALTEK, 0x8129) }, 153 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 154 { PCI_VDEVICE(REALTEK, 0x8161) }, 155 { PCI_VDEVICE(REALTEK, 0x8162) }, 156 { PCI_VDEVICE(REALTEK, 0x8167) }, 157 { PCI_VDEVICE(REALTEK, 0x8168) }, 158 { PCI_VDEVICE(NCUBE, 0x8168) }, 159 { PCI_VDEVICE(REALTEK, 0x8169) }, 160 { PCI_VENDOR_ID_DLINK, 0x4300, 161 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 162 { PCI_VDEVICE(DLINK, 0x4300) }, 163 { PCI_VDEVICE(DLINK, 0x4302) }, 164 { PCI_VDEVICE(AT, 0xc107) }, 165 { PCI_VDEVICE(USR, 0x0116) }, 166 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 167 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 168 { PCI_VDEVICE(REALTEK, 0x8125) }, 169 { PCI_VDEVICE(REALTEK, 0x8126) }, 170 { PCI_VDEVICE(REALTEK, 0x3000) }, 171 {} 172 }; 173 174 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 175 176 enum rtl_registers { 177 MAC0 = 0, /* Ethernet hardware address. */ 178 MAC4 = 4, 179 MAR0 = 8, /* Multicast filter. */ 180 CounterAddrLow = 0x10, 181 CounterAddrHigh = 0x14, 182 TxDescStartAddrLow = 0x20, 183 TxDescStartAddrHigh = 0x24, 184 TxHDescStartAddrLow = 0x28, 185 TxHDescStartAddrHigh = 0x2c, 186 FLASH = 0x30, 187 ERSR = 0x36, 188 ChipCmd = 0x37, 189 TxPoll = 0x38, 190 IntrMask = 0x3c, 191 IntrStatus = 0x3e, 192 193 TxConfig = 0x40, 194 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 195 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 196 197 RxConfig = 0x44, 198 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 199 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 200 #define RXCFG_FIFO_SHIFT 13 201 /* No threshold before first PCI xfer */ 202 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 203 #define RX_EARLY_OFF (1 << 11) 204 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 205 #define RXCFG_DMA_SHIFT 8 206 /* Unlimited maximum PCI burst. */ 207 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 208 209 Cfg9346 = 0x50, 210 Config0 = 0x51, 211 Config1 = 0x52, 212 Config2 = 0x53, 213 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 214 215 Config3 = 0x54, 216 Config4 = 0x55, 217 Config5 = 0x56, 218 PHYAR = 0x60, 219 PHYstatus = 0x6c, 220 RxMaxSize = 0xda, 221 CPlusCmd = 0xe0, 222 IntrMitigate = 0xe2, 223 224 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 225 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 226 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 227 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 228 229 #define RTL_COALESCE_T_MAX 0x0fU 230 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 231 232 RxDescAddrLow = 0xe4, 233 RxDescAddrHigh = 0xe8, 234 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 235 236 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 237 238 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 239 240 #define TxPacketMax (8064 >> 7) 241 #define EarlySize 0x27 242 243 FuncEvent = 0xf0, 244 FuncEventMask = 0xf4, 245 FuncPresetState = 0xf8, 246 IBCR0 = 0xf8, 247 IBCR2 = 0xf9, 248 IBIMR0 = 0xfa, 249 IBISR0 = 0xfb, 250 FuncForceEvent = 0xfc, 251 }; 252 253 enum rtl8168_8101_registers { 254 CSIDR = 0x64, 255 CSIAR = 0x68, 256 #define CSIAR_FLAG 0x80000000 257 #define CSIAR_WRITE_CMD 0x80000000 258 #define CSIAR_BYTE_ENABLE 0x0000f000 259 #define CSIAR_ADDR_MASK 0x00000fff 260 PMCH = 0x6f, 261 #define D3COLD_NO_PLL_DOWN BIT(7) 262 #define D3HOT_NO_PLL_DOWN BIT(6) 263 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 264 EPHYAR = 0x80, 265 #define EPHYAR_FLAG 0x80000000 266 #define EPHYAR_WRITE_CMD 0x80000000 267 #define EPHYAR_REG_MASK 0x1f 268 #define EPHYAR_REG_SHIFT 16 269 #define EPHYAR_DATA_MASK 0xffff 270 DLLPR = 0xd0, 271 #define PFM_EN (1 << 6) 272 #define TX_10M_PS_EN (1 << 7) 273 DBG_REG = 0xd1, 274 #define FIX_NAK_1 (1 << 4) 275 #define FIX_NAK_2 (1 << 3) 276 TWSI = 0xd2, 277 MCU = 0xd3, 278 #define NOW_IS_OOB (1 << 7) 279 #define TX_EMPTY (1 << 5) 280 #define RX_EMPTY (1 << 4) 281 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 282 #define EN_NDP (1 << 3) 283 #define EN_OOB_RESET (1 << 2) 284 #define LINK_LIST_RDY (1 << 1) 285 EFUSEAR = 0xdc, 286 #define EFUSEAR_FLAG 0x80000000 287 #define EFUSEAR_WRITE_CMD 0x80000000 288 #define EFUSEAR_READ_CMD 0x00000000 289 #define EFUSEAR_REG_MASK 0x03ff 290 #define EFUSEAR_REG_SHIFT 8 291 #define EFUSEAR_DATA_MASK 0xff 292 MISC_1 = 0xf2, 293 #define PFM_D3COLD_EN (1 << 6) 294 }; 295 296 enum rtl8168_registers { 297 LED_CTRL = 0x18, 298 LED_FREQ = 0x1a, 299 EEE_LED = 0x1b, 300 ERIDR = 0x70, 301 ERIAR = 0x74, 302 #define ERIAR_FLAG 0x80000000 303 #define ERIAR_WRITE_CMD 0x80000000 304 #define ERIAR_READ_CMD 0x00000000 305 #define ERIAR_ADDR_BYTE_ALIGN 4 306 #define ERIAR_TYPE_SHIFT 16 307 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 310 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_MASK_SHIFT 12 312 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 315 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 317 EPHY_RXER_NUM = 0x7c, 318 OCPDR = 0xb0, /* OCP GPHY access */ 319 #define OCPDR_WRITE_CMD 0x80000000 320 #define OCPDR_READ_CMD 0x00000000 321 #define OCPDR_REG_MASK 0x7f 322 #define OCPDR_GPHY_REG_SHIFT 16 323 #define OCPDR_DATA_MASK 0xffff 324 OCPAR = 0xb4, 325 #define OCPAR_FLAG 0x80000000 326 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 327 #define OCPAR_GPHY_READ_CMD 0x0000f060 328 GPHY_OCP = 0xb8, 329 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 330 MISC = 0xf0, /* 8168e only. */ 331 #define TXPLA_RST (1 << 29) 332 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 333 #define PWM_EN (1 << 22) 334 #define RXDV_GATED_EN (1 << 19) 335 #define EARLY_TALLY_EN (1 << 16) 336 }; 337 338 enum rtl8125_registers { 339 LEDSEL0 = 0x18, 340 INT_CFG0_8125 = 0x34, 341 #define INT_CFG0_ENABLE_8125 BIT(0) 342 #define INT_CFG0_CLKREQEN BIT(3) 343 IntrMask_8125 = 0x38, 344 IntrStatus_8125 = 0x3c, 345 INT_CFG1_8125 = 0x7a, 346 LEDSEL2 = 0x84, 347 LEDSEL1 = 0x86, 348 TxPoll_8125 = 0x90, 349 LEDSEL3 = 0x96, 350 MAC0_BKP = 0x19e0, 351 RSS_CTRL_8125 = 0x4500, 352 Q_NUM_CTRL_8125 = 0x4800, 353 EEE_TXIDLE_TIMER_8125 = 0x6048, 354 }; 355 356 #define LEDSEL_MASK_8125 0x23f 357 358 #define RX_VLAN_INNER_8125 BIT(22) 359 #define RX_VLAN_OUTER_8125 BIT(23) 360 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 361 362 #define RX_FETCH_DFLT_8125 (8 << 27) 363 364 enum rtl_register_content { 365 /* InterruptStatusBits */ 366 SYSErr = 0x8000, 367 PCSTimeout = 0x4000, 368 SWInt = 0x0100, 369 TxDescUnavail = 0x0080, 370 RxFIFOOver = 0x0040, 371 LinkChg = 0x0020, 372 RxOverflow = 0x0010, 373 TxErr = 0x0008, 374 TxOK = 0x0004, 375 RxErr = 0x0002, 376 RxOK = 0x0001, 377 378 /* RxStatusDesc */ 379 RxRWT = (1 << 22), 380 RxRES = (1 << 21), 381 RxRUNT = (1 << 20), 382 RxCRC = (1 << 19), 383 384 /* ChipCmdBits */ 385 StopReq = 0x80, 386 CmdReset = 0x10, 387 CmdRxEnb = 0x08, 388 CmdTxEnb = 0x04, 389 RxBufEmpty = 0x01, 390 391 /* TXPoll register p.5 */ 392 HPQ = 0x80, /* Poll cmd on the high prio queue */ 393 NPQ = 0x40, /* Poll cmd on the low prio queue */ 394 FSWInt = 0x01, /* Forced software interrupt */ 395 396 /* Cfg9346Bits */ 397 Cfg9346_Lock = 0x00, 398 Cfg9346_Unlock = 0xc0, 399 400 /* rx_mode_bits */ 401 AcceptErr = 0x20, 402 AcceptRunt = 0x10, 403 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 404 AcceptBroadcast = 0x08, 405 AcceptMulticast = 0x04, 406 AcceptMyPhys = 0x02, 407 AcceptAllPhys = 0x01, 408 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 409 #define RX_CONFIG_ACCEPT_MASK 0x3f 410 411 /* TxConfigBits */ 412 TxInterFrameGapShift = 24, 413 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 414 415 /* Config1 register p.24 */ 416 LEDS1 = (1 << 7), 417 LEDS0 = (1 << 6), 418 Speed_down = (1 << 4), 419 MEMMAP = (1 << 3), 420 IOMAP = (1 << 2), 421 VPD = (1 << 1), 422 PMEnable = (1 << 0), /* Power Management Enable */ 423 424 /* Config2 register p. 25 */ 425 ClkReqEn = (1 << 7), /* Clock Request Enable */ 426 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 427 PCI_Clock_66MHz = 0x01, 428 PCI_Clock_33MHz = 0x00, 429 430 /* Config3 register p.25 */ 431 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 432 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 433 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 434 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 435 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 436 437 /* Config4 register */ 438 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 439 440 /* Config5 register p.27 */ 441 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 442 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 443 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 444 Spi_en = (1 << 3), 445 LanWake = (1 << 1), /* LanWake enable/disable */ 446 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 447 ASPM_en = (1 << 0), /* ASPM enable */ 448 449 /* CPlusCmd p.31 */ 450 EnableBist = (1 << 15), // 8168 8101 451 Mac_dbgo_oe = (1 << 14), // 8168 8101 452 EnAnaPLL = (1 << 14), // 8169 453 Normal_mode = (1 << 13), // unused 454 Force_half_dup = (1 << 12), // 8168 8101 455 Force_rxflow_en = (1 << 11), // 8168 8101 456 Force_txflow_en = (1 << 10), // 8168 8101 457 Cxpl_dbg_sel = (1 << 9), // 8168 8101 458 ASF = (1 << 8), // 8168 8101 459 PktCntrDisable = (1 << 7), // 8168 8101 460 Mac_dbgo_sel = 0x001c, // 8168 461 RxVlan = (1 << 6), 462 RxChkSum = (1 << 5), 463 PCIDAC = (1 << 4), 464 PCIMulRW = (1 << 3), 465 #define INTT_MASK GENMASK(1, 0) 466 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 467 468 /* rtl8169_PHYstatus */ 469 TBI_Enable = 0x80, 470 TxFlowCtrl = 0x40, 471 RxFlowCtrl = 0x20, 472 _1000bpsF = 0x10, 473 _100bps = 0x08, 474 _10bps = 0x04, 475 LinkStatus = 0x02, 476 FullDup = 0x01, 477 478 /* ResetCounterCommand */ 479 CounterReset = 0x1, 480 481 /* DumpCounterCommand */ 482 CounterDump = 0x8, 483 484 /* magic enable v2 */ 485 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 486 }; 487 488 enum rtl_desc_bit { 489 /* First doubleword. */ 490 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 491 RingEnd = (1 << 30), /* End of descriptor ring */ 492 FirstFrag = (1 << 29), /* First segment of a packet */ 493 LastFrag = (1 << 28), /* Final segment of a packet */ 494 }; 495 496 /* Generic case. */ 497 enum rtl_tx_desc_bit { 498 /* First doubleword. */ 499 TD_LSO = (1 << 27), /* Large Send Offload */ 500 #define TD_MSS_MAX 0x07ffu /* MSS value */ 501 502 /* Second doubleword. */ 503 TxVlanTag = (1 << 17), /* Add VLAN tag */ 504 }; 505 506 /* 8169, 8168b and 810x except 8102e. */ 507 enum rtl_tx_desc_bit_0 { 508 /* First doubleword. */ 509 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 510 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 511 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 512 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 513 }; 514 515 /* 8102e, 8168c and beyond. */ 516 enum rtl_tx_desc_bit_1 { 517 /* First doubleword. */ 518 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 519 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 520 #define GTTCPHO_SHIFT 18 521 #define GTTCPHO_MAX 0x7f 522 523 /* Second doubleword. */ 524 #define TCPHO_SHIFT 18 525 #define TCPHO_MAX 0x3ff 526 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 527 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 528 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 529 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 530 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 531 }; 532 533 enum rtl_rx_desc_bit { 534 /* Rx private */ 535 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 536 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 537 538 #define RxProtoUDP (PID1) 539 #define RxProtoTCP (PID0) 540 #define RxProtoIP (PID1 | PID0) 541 #define RxProtoMask RxProtoIP 542 543 IPFail = (1 << 16), /* IP checksum failed */ 544 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 545 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 546 547 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 548 549 RxVlanTag = (1 << 16), /* VLAN tag available */ 550 }; 551 552 #define RTL_GSO_MAX_SIZE_V1 32000 553 #define RTL_GSO_MAX_SEGS_V1 24 554 #define RTL_GSO_MAX_SIZE_V2 64000 555 #define RTL_GSO_MAX_SEGS_V2 64 556 557 struct TxDesc { 558 __le32 opts1; 559 __le32 opts2; 560 __le64 addr; 561 }; 562 563 struct RxDesc { 564 __le32 opts1; 565 __le32 opts2; 566 __le64 addr; 567 }; 568 569 struct ring_info { 570 struct sk_buff *skb; 571 u32 len; 572 }; 573 574 struct rtl8169_counters { 575 __le64 tx_packets; 576 __le64 rx_packets; 577 __le64 tx_errors; 578 __le32 rx_errors; 579 __le16 rx_missed; 580 __le16 align_errors; 581 __le32 tx_one_collision; 582 __le32 tx_multi_collision; 583 __le64 rx_unicast; 584 __le64 rx_broadcast; 585 __le32 rx_multicast; 586 __le16 tx_aborted; 587 __le16 tx_underrun; 588 /* new since RTL8125 */ 589 __le64 tx_octets; 590 __le64 rx_octets; 591 __le64 rx_multicast64; 592 __le64 tx_unicast64; 593 __le64 tx_broadcast64; 594 __le64 tx_multicast64; 595 __le32 tx_pause_on; 596 __le32 tx_pause_off; 597 __le32 tx_pause_all; 598 __le32 tx_deferred; 599 __le32 tx_late_collision; 600 __le32 tx_all_collision; 601 __le32 tx_aborted32; 602 __le32 align_errors32; 603 __le32 rx_frame_too_long; 604 __le32 rx_runt; 605 __le32 rx_pause_on; 606 __le32 rx_pause_off; 607 __le32 rx_pause_all; 608 __le32 rx_unknown_opcode; 609 __le32 rx_mac_error; 610 __le32 tx_underrun32; 611 __le32 rx_mac_missed; 612 __le32 rx_tcam_dropped; 613 __le32 tdu; 614 __le32 rdu; 615 }; 616 617 struct rtl8169_tc_offsets { 618 bool inited; 619 __le64 tx_errors; 620 __le32 tx_multi_collision; 621 __le16 tx_aborted; 622 __le16 rx_missed; 623 }; 624 625 enum rtl_flag { 626 RTL_FLAG_TASK_RESET_PENDING, 627 RTL_FLAG_TASK_TX_TIMEOUT, 628 RTL_FLAG_MAX 629 }; 630 631 enum rtl_dash_type { 632 RTL_DASH_NONE, 633 RTL_DASH_DP, 634 RTL_DASH_EP, 635 }; 636 637 struct rtl8169_private { 638 void __iomem *mmio_addr; /* memory map physical address */ 639 struct pci_dev *pci_dev; 640 struct net_device *dev; 641 struct phy_device *phydev; 642 struct napi_struct napi; 643 enum mac_version mac_version; 644 enum rtl_dash_type dash_type; 645 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 646 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 647 u32 dirty_tx; 648 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 649 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 650 dma_addr_t TxPhyAddr; 651 dma_addr_t RxPhyAddr; 652 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 653 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 654 u16 cp_cmd; 655 u16 tx_lpi_timer; 656 u32 irq_mask; 657 int irq; 658 struct clk *clk; 659 660 struct { 661 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 662 struct work_struct work; 663 } wk; 664 665 raw_spinlock_t mac_ocp_lock; 666 struct mutex led_lock; /* serialize LED ctrl RMW access */ 667 668 unsigned supports_gmii:1; 669 unsigned aspm_manageable:1; 670 unsigned dash_enabled:1; 671 dma_addr_t counters_phys_addr; 672 struct rtl8169_counters *counters; 673 struct rtl8169_tc_offsets tc_offset; 674 u32 saved_wolopts; 675 676 const char *fw_name; 677 struct rtl_fw *rtl_fw; 678 679 struct r8169_led_classdev *leds; 680 681 u32 ocp_base; 682 }; 683 684 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 685 686 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 687 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 688 MODULE_SOFTDEP("pre: realtek"); 689 MODULE_LICENSE("GPL"); 690 MODULE_FIRMWARE(FIRMWARE_8168D_1); 691 MODULE_FIRMWARE(FIRMWARE_8168D_2); 692 MODULE_FIRMWARE(FIRMWARE_8168E_1); 693 MODULE_FIRMWARE(FIRMWARE_8168E_2); 694 MODULE_FIRMWARE(FIRMWARE_8168E_3); 695 MODULE_FIRMWARE(FIRMWARE_8105E_1); 696 MODULE_FIRMWARE(FIRMWARE_8168F_1); 697 MODULE_FIRMWARE(FIRMWARE_8168F_2); 698 MODULE_FIRMWARE(FIRMWARE_8402_1); 699 MODULE_FIRMWARE(FIRMWARE_8411_1); 700 MODULE_FIRMWARE(FIRMWARE_8411_2); 701 MODULE_FIRMWARE(FIRMWARE_8106E_1); 702 MODULE_FIRMWARE(FIRMWARE_8106E_2); 703 MODULE_FIRMWARE(FIRMWARE_8168G_2); 704 MODULE_FIRMWARE(FIRMWARE_8168G_3); 705 MODULE_FIRMWARE(FIRMWARE_8168H_2); 706 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 707 MODULE_FIRMWARE(FIRMWARE_8107E_2); 708 MODULE_FIRMWARE(FIRMWARE_8125A_3); 709 MODULE_FIRMWARE(FIRMWARE_8125B_2); 710 MODULE_FIRMWARE(FIRMWARE_8125D_1); 711 MODULE_FIRMWARE(FIRMWARE_8125D_2); 712 MODULE_FIRMWARE(FIRMWARE_8126A_2); 713 MODULE_FIRMWARE(FIRMWARE_8126A_3); 714 715 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 716 { 717 return &tp->pci_dev->dev; 718 } 719 720 static void rtl_lock_config_regs(struct rtl8169_private *tp) 721 { 722 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 723 } 724 725 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 726 { 727 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 728 } 729 730 static void rtl_pci_commit(struct rtl8169_private *tp) 731 { 732 /* Read an arbitrary register to commit a preceding PCI write */ 733 RTL_R8(tp, ChipCmd); 734 } 735 736 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 737 { 738 u8 val; 739 740 val = RTL_R8(tp, Config2); 741 RTL_W8(tp, Config2, (val & ~clear) | set); 742 } 743 744 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 745 { 746 u8 val; 747 748 val = RTL_R8(tp, Config5); 749 RTL_W8(tp, Config5, (val & ~clear) | set); 750 } 751 752 static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg, 753 u8 bits, bool cond) 754 { 755 u8 val, old_val; 756 757 old_val = RTL_R8(tp, reg); 758 if (cond) 759 val = old_val | bits; 760 else 761 val = old_val & ~bits; 762 if (val != old_val) 763 RTL_W8(tp, reg, val); 764 } 765 766 static bool rtl_is_8125(struct rtl8169_private *tp) 767 { 768 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 769 } 770 771 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 772 { 773 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 774 tp->mac_version != RTL_GIGA_MAC_VER_39 && 775 tp->mac_version <= RTL_GIGA_MAC_VER_53; 776 } 777 778 static bool rtl_supports_eee(struct rtl8169_private *tp) 779 { 780 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 781 tp->mac_version != RTL_GIGA_MAC_VER_37 && 782 tp->mac_version != RTL_GIGA_MAC_VER_39; 783 } 784 785 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 786 { 787 int i; 788 789 for (i = 0; i < ETH_ALEN; i++) 790 mac[i] = RTL_R8(tp, reg + i); 791 } 792 793 struct rtl_cond { 794 bool (*check)(struct rtl8169_private *); 795 const char *msg; 796 }; 797 798 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 799 unsigned long usecs, int n, bool high) 800 { 801 int i; 802 803 for (i = 0; i < n; i++) { 804 if (c->check(tp) == high) 805 return true; 806 fsleep(usecs); 807 } 808 809 if (net_ratelimit()) 810 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 811 c->msg, !high, n, usecs); 812 return false; 813 } 814 815 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 816 const struct rtl_cond *c, 817 unsigned long d, int n) 818 { 819 return rtl_loop_wait(tp, c, d, n, true); 820 } 821 822 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 823 const struct rtl_cond *c, 824 unsigned long d, int n) 825 { 826 return rtl_loop_wait(tp, c, d, n, false); 827 } 828 829 #define DECLARE_RTL_COND(name) \ 830 static bool name ## _check(struct rtl8169_private *); \ 831 \ 832 static const struct rtl_cond name = { \ 833 .check = name ## _check, \ 834 .msg = #name \ 835 }; \ 836 \ 837 static bool name ## _check(struct rtl8169_private *tp) 838 839 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 840 { 841 struct device *dev = tp_to_dev(tp); 842 int ret; 843 844 ret = pm_runtime_resume_and_get(dev); 845 if (ret < 0) 846 return ret; 847 848 mutex_lock(&tp->led_lock); 849 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 850 mutex_unlock(&tp->led_lock); 851 852 pm_runtime_put_sync(dev); 853 854 return 0; 855 } 856 857 int rtl8168_get_led_mode(struct rtl8169_private *tp) 858 { 859 struct device *dev = tp_to_dev(tp); 860 int ret; 861 862 ret = pm_runtime_resume_and_get(dev); 863 if (ret < 0) 864 return ret; 865 866 ret = RTL_R16(tp, LED_CTRL); 867 868 pm_runtime_put_sync(dev); 869 870 return ret; 871 } 872 873 static int rtl8125_get_led_reg(int index) 874 { 875 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 876 877 return led_regs[index]; 878 } 879 880 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 881 { 882 int reg = rtl8125_get_led_reg(index); 883 struct device *dev = tp_to_dev(tp); 884 int ret; 885 u16 val; 886 887 ret = pm_runtime_resume_and_get(dev); 888 if (ret < 0) 889 return ret; 890 891 mutex_lock(&tp->led_lock); 892 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 893 RTL_W16(tp, reg, val | mode); 894 mutex_unlock(&tp->led_lock); 895 896 pm_runtime_put_sync(dev); 897 898 return 0; 899 } 900 901 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 902 { 903 int reg = rtl8125_get_led_reg(index); 904 struct device *dev = tp_to_dev(tp); 905 int ret; 906 907 ret = pm_runtime_resume_and_get(dev); 908 if (ret < 0) 909 return ret; 910 911 ret = RTL_R16(tp, reg); 912 913 pm_runtime_put_sync(dev); 914 915 return ret; 916 } 917 918 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 919 char *buf, int buf_len) 920 { 921 struct pci_dev *pdev = tp->pci_dev; 922 char pdom[8], pfun[8]; 923 int domain; 924 925 domain = pci_domain_nr(pdev->bus); 926 if (domain) 927 snprintf(pdom, sizeof(pdom), "P%d", domain); 928 else 929 pdom[0] = '\0'; 930 931 if (pdev->multifunction) 932 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 933 else 934 pfun[0] = '\0'; 935 936 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 937 PCI_SLOT(pdev->devfn), pfun, idx); 938 } 939 940 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 941 { 942 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 943 if (type == ERIAR_OOB && 944 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 945 tp->mac_version == RTL_GIGA_MAC_VER_53)) 946 *cmd |= 0xf70 << 18; 947 } 948 949 DECLARE_RTL_COND(rtl_eriar_cond) 950 { 951 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 952 } 953 954 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 955 u32 val, int type) 956 { 957 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 958 959 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 960 return; 961 962 RTL_W32(tp, ERIDR, val); 963 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 964 RTL_W32(tp, ERIAR, cmd); 965 966 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 967 } 968 969 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 970 u32 val) 971 { 972 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 973 } 974 975 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 976 { 977 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 978 979 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 980 RTL_W32(tp, ERIAR, cmd); 981 982 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 983 RTL_R32(tp, ERIDR) : ~0; 984 } 985 986 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 987 { 988 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 989 } 990 991 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 992 { 993 u32 val = rtl_eri_read(tp, addr); 994 995 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 996 } 997 998 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 999 { 1000 rtl_w0w1_eri(tp, addr, p, 0); 1001 } 1002 1003 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1004 { 1005 rtl_w0w1_eri(tp, addr, 0, m); 1006 } 1007 1008 static bool rtl_ocp_reg_failure(u32 reg) 1009 { 1010 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1011 } 1012 1013 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1014 { 1015 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1016 } 1017 1018 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1019 { 1020 if (rtl_ocp_reg_failure(reg)) 1021 return; 1022 1023 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1024 1025 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1026 } 1027 1028 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1029 { 1030 if (rtl_ocp_reg_failure(reg)) 1031 return 0; 1032 1033 RTL_W32(tp, GPHY_OCP, reg << 15); 1034 1035 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1036 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1037 } 1038 1039 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1040 { 1041 if (rtl_ocp_reg_failure(reg)) 1042 return; 1043 1044 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1045 } 1046 1047 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1048 { 1049 unsigned long flags; 1050 1051 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1052 __r8168_mac_ocp_write(tp, reg, data); 1053 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1054 } 1055 1056 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1057 { 1058 if (rtl_ocp_reg_failure(reg)) 1059 return 0; 1060 1061 RTL_W32(tp, OCPDR, reg << 15); 1062 1063 return RTL_R32(tp, OCPDR); 1064 } 1065 1066 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1067 { 1068 unsigned long flags; 1069 u16 val; 1070 1071 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1072 val = __r8168_mac_ocp_read(tp, reg); 1073 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1074 1075 return val; 1076 } 1077 1078 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1079 u16 set) 1080 { 1081 unsigned long flags; 1082 u16 data; 1083 1084 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1085 data = __r8168_mac_ocp_read(tp, reg); 1086 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1087 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1088 } 1089 1090 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1091 * PHY MCU interrupts before PHY power-down. 1092 */ 1093 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1094 { 1095 switch (tp->mac_version) { 1096 case RTL_GIGA_MAC_VER_40: 1097 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1098 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1099 else 1100 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1101 break; 1102 default: 1103 break; 1104 } 1105 }; 1106 1107 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1108 { 1109 if (reg == 0x1f) { 1110 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1111 return; 1112 } 1113 1114 if (tp->ocp_base != OCP_STD_PHY_BASE) 1115 reg -= 0x10; 1116 1117 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1118 rtl8168g_phy_suspend_quirk(tp, value); 1119 1120 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1121 } 1122 1123 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1124 { 1125 if (reg == 0x1f) 1126 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1127 1128 if (tp->ocp_base != OCP_STD_PHY_BASE) 1129 reg -= 0x10; 1130 1131 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1132 } 1133 1134 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1135 { 1136 if (reg == 0x1f) { 1137 tp->ocp_base = value << 4; 1138 return; 1139 } 1140 1141 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1142 } 1143 1144 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1145 { 1146 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1147 } 1148 1149 DECLARE_RTL_COND(rtl_phyar_cond) 1150 { 1151 return RTL_R32(tp, PHYAR) & 0x80000000; 1152 } 1153 1154 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1155 { 1156 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1157 1158 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1159 /* 1160 * According to hardware specs a 20us delay is required after write 1161 * complete indication, but before sending next command. 1162 */ 1163 udelay(20); 1164 } 1165 1166 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1167 { 1168 int value; 1169 1170 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1171 1172 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1173 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1174 1175 /* 1176 * According to hardware specs a 20us delay is required after read 1177 * complete indication, but before sending next command. 1178 */ 1179 udelay(20); 1180 1181 return value; 1182 } 1183 1184 DECLARE_RTL_COND(rtl_ocpar_cond) 1185 { 1186 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1187 } 1188 1189 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1190 1191 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1192 { 1193 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1194 } 1195 1196 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1197 { 1198 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1199 } 1200 1201 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1202 { 1203 r8168dp_2_mdio_start(tp); 1204 1205 r8169_mdio_write(tp, reg, value); 1206 1207 r8168dp_2_mdio_stop(tp); 1208 } 1209 1210 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1211 { 1212 int value; 1213 1214 /* Work around issue with chip reporting wrong PHY ID */ 1215 if (reg == MII_PHYSID2) 1216 return 0xc912; 1217 1218 r8168dp_2_mdio_start(tp); 1219 1220 value = r8169_mdio_read(tp, reg); 1221 1222 r8168dp_2_mdio_stop(tp); 1223 1224 return value; 1225 } 1226 1227 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1228 { 1229 switch (tp->mac_version) { 1230 case RTL_GIGA_MAC_VER_28: 1231 case RTL_GIGA_MAC_VER_31: 1232 r8168dp_2_mdio_write(tp, location, val); 1233 break; 1234 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 1235 r8168g_mdio_write(tp, location, val); 1236 break; 1237 default: 1238 r8169_mdio_write(tp, location, val); 1239 break; 1240 } 1241 } 1242 1243 static int rtl_readphy(struct rtl8169_private *tp, int location) 1244 { 1245 switch (tp->mac_version) { 1246 case RTL_GIGA_MAC_VER_28: 1247 case RTL_GIGA_MAC_VER_31: 1248 return r8168dp_2_mdio_read(tp, location); 1249 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 1250 return r8168g_mdio_read(tp, location); 1251 default: 1252 return r8169_mdio_read(tp, location); 1253 } 1254 } 1255 1256 DECLARE_RTL_COND(rtl_ephyar_cond) 1257 { 1258 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1259 } 1260 1261 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1262 { 1263 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1264 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1265 1266 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1267 1268 udelay(10); 1269 } 1270 1271 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1272 { 1273 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1274 1275 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1276 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1277 } 1278 1279 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1280 { 1281 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1282 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1283 RTL_R32(tp, OCPDR) : ~0; 1284 } 1285 1286 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1287 { 1288 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1289 } 1290 1291 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1292 u32 data) 1293 { 1294 RTL_W32(tp, OCPDR, data); 1295 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1296 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1297 } 1298 1299 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1300 u32 data) 1301 { 1302 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1303 data, ERIAR_OOB); 1304 } 1305 1306 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1307 { 1308 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1309 1310 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1311 } 1312 1313 #define OOB_CMD_RESET 0x00 1314 #define OOB_CMD_DRIVER_START 0x05 1315 #define OOB_CMD_DRIVER_STOP 0x06 1316 1317 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1318 { 1319 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1320 } 1321 1322 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1323 { 1324 u16 reg; 1325 1326 reg = rtl8168_get_ocp_reg(tp); 1327 1328 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1329 } 1330 1331 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1332 { 1333 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1334 } 1335 1336 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1337 { 1338 return RTL_R8(tp, IBISR0) & 0x20; 1339 } 1340 1341 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1342 { 1343 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1344 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1345 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1346 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1347 } 1348 1349 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1350 { 1351 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1352 if (tp->dash_enabled) 1353 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1354 } 1355 1356 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1357 { 1358 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1359 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1360 if (tp->dash_enabled) 1361 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1362 } 1363 1364 static void rtl8168_driver_start(struct rtl8169_private *tp) 1365 { 1366 if (tp->dash_type == RTL_DASH_DP) 1367 rtl8168dp_driver_start(tp); 1368 else 1369 rtl8168ep_driver_start(tp); 1370 } 1371 1372 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1373 { 1374 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1375 if (tp->dash_enabled) 1376 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1377 } 1378 1379 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1380 { 1381 rtl8168ep_stop_cmac(tp); 1382 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1383 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1384 if (tp->dash_enabled) 1385 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1386 } 1387 1388 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1389 { 1390 if (tp->dash_type == RTL_DASH_DP) 1391 rtl8168dp_driver_stop(tp); 1392 else 1393 rtl8168ep_driver_stop(tp); 1394 } 1395 1396 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1397 { 1398 u16 reg = rtl8168_get_ocp_reg(tp); 1399 1400 return r8168dp_ocp_read(tp, reg) & BIT(15); 1401 } 1402 1403 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1404 { 1405 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1406 } 1407 1408 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1409 { 1410 switch (tp->dash_type) { 1411 case RTL_DASH_DP: 1412 return r8168dp_check_dash(tp); 1413 case RTL_DASH_EP: 1414 return r8168ep_check_dash(tp); 1415 default: 1416 return false; 1417 } 1418 } 1419 1420 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1421 { 1422 switch (tp->mac_version) { 1423 case RTL_GIGA_MAC_VER_28: 1424 case RTL_GIGA_MAC_VER_31: 1425 return RTL_DASH_DP; 1426 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1427 return RTL_DASH_EP; 1428 default: 1429 return RTL_DASH_NONE; 1430 } 1431 } 1432 1433 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1434 { 1435 if (tp->mac_version >= RTL_GIGA_MAC_VER_25 && 1436 tp->mac_version != RTL_GIGA_MAC_VER_28 && 1437 tp->mac_version != RTL_GIGA_MAC_VER_31 && 1438 tp->mac_version != RTL_GIGA_MAC_VER_38) 1439 r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, !enable); 1440 } 1441 1442 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1443 { 1444 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1445 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1446 } 1447 1448 DECLARE_RTL_COND(rtl_efusear_cond) 1449 { 1450 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1451 } 1452 1453 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1454 { 1455 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1456 1457 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1458 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1459 } 1460 1461 static u32 rtl_get_events(struct rtl8169_private *tp) 1462 { 1463 if (rtl_is_8125(tp)) 1464 return RTL_R32(tp, IntrStatus_8125); 1465 else 1466 return RTL_R16(tp, IntrStatus); 1467 } 1468 1469 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1470 { 1471 if (rtl_is_8125(tp)) 1472 RTL_W32(tp, IntrStatus_8125, bits); 1473 else 1474 RTL_W16(tp, IntrStatus, bits); 1475 } 1476 1477 static void rtl_irq_disable(struct rtl8169_private *tp) 1478 { 1479 if (rtl_is_8125(tp)) 1480 RTL_W32(tp, IntrMask_8125, 0); 1481 else 1482 RTL_W16(tp, IntrMask, 0); 1483 } 1484 1485 static void rtl_irq_enable(struct rtl8169_private *tp) 1486 { 1487 if (rtl_is_8125(tp)) 1488 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1489 else 1490 RTL_W16(tp, IntrMask, tp->irq_mask); 1491 } 1492 1493 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1494 { 1495 rtl_irq_disable(tp); 1496 rtl_ack_events(tp, 0xffffffff); 1497 rtl_pci_commit(tp); 1498 } 1499 1500 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1501 { 1502 struct phy_device *phydev = tp->phydev; 1503 1504 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1505 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1506 if (phydev->speed == SPEED_1000) { 1507 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1508 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1509 } else if (phydev->speed == SPEED_100) { 1510 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1511 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1512 } else { 1513 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1514 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1515 } 1516 rtl_reset_packet_filter(tp); 1517 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1518 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1519 if (phydev->speed == SPEED_1000) { 1520 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1521 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1522 } else { 1523 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1524 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1525 } 1526 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1527 if (phydev->speed == SPEED_10) { 1528 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1529 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1530 } else { 1531 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1532 } 1533 } 1534 } 1535 1536 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1537 1538 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1539 { 1540 struct rtl8169_private *tp = netdev_priv(dev); 1541 1542 wol->supported = WAKE_ANY; 1543 wol->wolopts = tp->saved_wolopts; 1544 } 1545 1546 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1547 { 1548 rtl_unlock_config_regs(tp); 1549 1550 if (rtl_is_8168evl_up(tp)) { 1551 if (wolopts & WAKE_MAGIC) 1552 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1553 else 1554 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1555 } else if (rtl_is_8125(tp)) { 1556 if (wolopts & WAKE_MAGIC) 1557 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1558 else 1559 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1560 } else { 1561 r8169_mod_reg8_cond(tp, Config3, MagicPacket, 1562 wolopts & WAKE_MAGIC); 1563 } 1564 1565 r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY); 1566 if (rtl_is_8125(tp)) 1567 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, 1568 wolopts & WAKE_PHY ? 0x13 : 0); 1569 r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST); 1570 r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST); 1571 r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST); 1572 r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts); 1573 1574 switch (tp->mac_version) { 1575 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1576 r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts); 1577 break; 1578 case RTL_GIGA_MAC_VER_34: 1579 case RTL_GIGA_MAC_VER_37: 1580 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_71: 1581 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); 1582 break; 1583 default: 1584 break; 1585 } 1586 1587 rtl_lock_config_regs(tp); 1588 1589 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1590 1591 if (!tp->dash_enabled) { 1592 rtl_set_d3_pll_down(tp, !wolopts); 1593 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1594 } 1595 } 1596 1597 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1598 { 1599 struct rtl8169_private *tp = netdev_priv(dev); 1600 1601 if (wol->wolopts & ~WAKE_ANY) 1602 return -EINVAL; 1603 1604 tp->saved_wolopts = wol->wolopts; 1605 __rtl8169_set_wol(tp, tp->saved_wolopts); 1606 1607 return 0; 1608 } 1609 1610 static void rtl8169_get_drvinfo(struct net_device *dev, 1611 struct ethtool_drvinfo *info) 1612 { 1613 struct rtl8169_private *tp = netdev_priv(dev); 1614 struct rtl_fw *rtl_fw = tp->rtl_fw; 1615 1616 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1617 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1618 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1619 if (rtl_fw) 1620 strscpy(info->fw_version, rtl_fw->version, 1621 sizeof(info->fw_version)); 1622 } 1623 1624 static int rtl8169_get_regs_len(struct net_device *dev) 1625 { 1626 return R8169_REGS_SIZE; 1627 } 1628 1629 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1630 netdev_features_t features) 1631 { 1632 struct rtl8169_private *tp = netdev_priv(dev); 1633 1634 if (dev->mtu > TD_MSS_MAX) 1635 features &= ~NETIF_F_ALL_TSO; 1636 1637 if (dev->mtu > ETH_DATA_LEN && 1638 tp->mac_version > RTL_GIGA_MAC_VER_06) 1639 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1640 1641 return features; 1642 } 1643 1644 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1645 netdev_features_t features) 1646 { 1647 u32 rx_config = RTL_R32(tp, RxConfig); 1648 1649 if (features & NETIF_F_RXALL) 1650 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1651 else 1652 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1653 1654 if (rtl_is_8125(tp)) { 1655 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1656 rx_config |= RX_VLAN_8125; 1657 else 1658 rx_config &= ~RX_VLAN_8125; 1659 } 1660 1661 RTL_W32(tp, RxConfig, rx_config); 1662 } 1663 1664 static int rtl8169_set_features(struct net_device *dev, 1665 netdev_features_t features) 1666 { 1667 struct rtl8169_private *tp = netdev_priv(dev); 1668 1669 rtl_set_rx_config_features(tp, features); 1670 1671 if (features & NETIF_F_RXCSUM) 1672 tp->cp_cmd |= RxChkSum; 1673 else 1674 tp->cp_cmd &= ~RxChkSum; 1675 1676 if (!rtl_is_8125(tp)) { 1677 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1678 tp->cp_cmd |= RxVlan; 1679 else 1680 tp->cp_cmd &= ~RxVlan; 1681 } 1682 1683 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1684 rtl_pci_commit(tp); 1685 1686 return 0; 1687 } 1688 1689 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1690 { 1691 return (skb_vlan_tag_present(skb)) ? 1692 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1693 } 1694 1695 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1696 { 1697 u32 opts2 = le32_to_cpu(desc->opts2); 1698 1699 if (opts2 & RxVlanTag) 1700 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1701 } 1702 1703 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1704 void *p) 1705 { 1706 struct rtl8169_private *tp = netdev_priv(dev); 1707 u32 __iomem *data = tp->mmio_addr; 1708 u32 *dw = p; 1709 int i; 1710 1711 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1712 memcpy_fromio(dw++, data++, 4); 1713 } 1714 1715 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1716 "tx_packets", 1717 "rx_packets", 1718 "tx_errors", 1719 "rx_errors", 1720 "rx_missed", 1721 "align_errors", 1722 "tx_single_collisions", 1723 "tx_multi_collisions", 1724 "unicast", 1725 "broadcast", 1726 "multicast", 1727 "tx_aborted", 1728 "tx_underrun", 1729 }; 1730 1731 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1732 { 1733 switch (sset) { 1734 case ETH_SS_STATS: 1735 return ARRAY_SIZE(rtl8169_gstrings); 1736 default: 1737 return -EOPNOTSUPP; 1738 } 1739 } 1740 1741 DECLARE_RTL_COND(rtl_counters_cond) 1742 { 1743 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1744 } 1745 1746 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1747 { 1748 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1749 1750 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1751 rtl_pci_commit(tp); 1752 RTL_W32(tp, CounterAddrLow, cmd); 1753 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1754 1755 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1756 } 1757 1758 static void rtl8169_update_counters(struct rtl8169_private *tp) 1759 { 1760 u8 val = RTL_R8(tp, ChipCmd); 1761 1762 /* 1763 * Some chips are unable to dump tally counters when the receiver 1764 * is disabled. If 0xff chip may be in a PCI power-save state. 1765 */ 1766 if (val & CmdRxEnb && val != 0xff) 1767 rtl8169_do_counters(tp, CounterDump); 1768 } 1769 1770 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1771 { 1772 struct rtl8169_counters *counters = tp->counters; 1773 1774 /* 1775 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1776 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1777 * reset by a power cycle, while the counter values collected by the 1778 * driver are reset at every driver unload/load cycle. 1779 * 1780 * To make sure the HW values returned by @get_stats64 match the SW 1781 * values, we collect the initial values at first open(*) and use them 1782 * as offsets to normalize the values returned by @get_stats64. 1783 * 1784 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1785 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1786 * set at open time by rtl_hw_start. 1787 */ 1788 1789 if (tp->tc_offset.inited) 1790 return; 1791 1792 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1793 rtl8169_do_counters(tp, CounterReset); 1794 } else { 1795 rtl8169_update_counters(tp); 1796 tp->tc_offset.tx_errors = counters->tx_errors; 1797 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1798 tp->tc_offset.tx_aborted = counters->tx_aborted; 1799 tp->tc_offset.rx_missed = counters->rx_missed; 1800 } 1801 1802 tp->tc_offset.inited = true; 1803 } 1804 1805 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1806 struct ethtool_stats *stats, u64 *data) 1807 { 1808 struct rtl8169_private *tp = netdev_priv(dev); 1809 struct rtl8169_counters *counters; 1810 1811 counters = tp->counters; 1812 rtl8169_update_counters(tp); 1813 1814 data[0] = le64_to_cpu(counters->tx_packets); 1815 data[1] = le64_to_cpu(counters->rx_packets); 1816 data[2] = le64_to_cpu(counters->tx_errors); 1817 data[3] = le32_to_cpu(counters->rx_errors); 1818 data[4] = le16_to_cpu(counters->rx_missed); 1819 data[5] = le16_to_cpu(counters->align_errors); 1820 data[6] = le32_to_cpu(counters->tx_one_collision); 1821 data[7] = le32_to_cpu(counters->tx_multi_collision); 1822 data[8] = le64_to_cpu(counters->rx_unicast); 1823 data[9] = le64_to_cpu(counters->rx_broadcast); 1824 data[10] = le32_to_cpu(counters->rx_multicast); 1825 data[11] = le16_to_cpu(counters->tx_aborted); 1826 data[12] = le16_to_cpu(counters->tx_underrun); 1827 } 1828 1829 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1830 { 1831 switch(stringset) { 1832 case ETH_SS_STATS: 1833 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1834 break; 1835 } 1836 } 1837 1838 /* 1839 * Interrupt coalescing 1840 * 1841 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1842 * > 8169, 8168 and 810x line of chipsets 1843 * 1844 * 8169, 8168, and 8136(810x) serial chipsets support it. 1845 * 1846 * > 2 - the Tx timer unit at gigabit speed 1847 * 1848 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1849 * (0xe0) bit 1 and bit 0. 1850 * 1851 * For 8169 1852 * bit[1:0] \ speed 1000M 100M 10M 1853 * 0 0 320ns 2.56us 40.96us 1854 * 0 1 2.56us 20.48us 327.7us 1855 * 1 0 5.12us 40.96us 655.4us 1856 * 1 1 10.24us 81.92us 1.31ms 1857 * 1858 * For the other 1859 * bit[1:0] \ speed 1000M 100M 10M 1860 * 0 0 5us 2.56us 40.96us 1861 * 0 1 40us 20.48us 327.7us 1862 * 1 0 80us 40.96us 655.4us 1863 * 1 1 160us 81.92us 1.31ms 1864 */ 1865 1866 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1867 struct rtl_coalesce_info { 1868 u32 speed; 1869 u32 scale_nsecs[4]; 1870 }; 1871 1872 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1873 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1874 1875 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1876 { SPEED_1000, COALESCE_DELAY(320) }, 1877 { SPEED_100, COALESCE_DELAY(2560) }, 1878 { SPEED_10, COALESCE_DELAY(40960) }, 1879 { 0 }, 1880 }; 1881 1882 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1883 { SPEED_1000, COALESCE_DELAY(5000) }, 1884 { SPEED_100, COALESCE_DELAY(2560) }, 1885 { SPEED_10, COALESCE_DELAY(40960) }, 1886 { 0 }, 1887 }; 1888 #undef COALESCE_DELAY 1889 1890 /* get rx/tx scale vector corresponding to current speed */ 1891 static const struct rtl_coalesce_info * 1892 rtl_coalesce_info(struct rtl8169_private *tp) 1893 { 1894 const struct rtl_coalesce_info *ci; 1895 1896 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1897 ci = rtl_coalesce_info_8169; 1898 else 1899 ci = rtl_coalesce_info_8168_8136; 1900 1901 /* if speed is unknown assume highest one */ 1902 if (tp->phydev->speed == SPEED_UNKNOWN) 1903 return ci; 1904 1905 for (; ci->speed; ci++) { 1906 if (tp->phydev->speed == ci->speed) 1907 return ci; 1908 } 1909 1910 return ERR_PTR(-ELNRNG); 1911 } 1912 1913 static int rtl_get_coalesce(struct net_device *dev, 1914 struct ethtool_coalesce *ec, 1915 struct kernel_ethtool_coalesce *kernel_coal, 1916 struct netlink_ext_ack *extack) 1917 { 1918 struct rtl8169_private *tp = netdev_priv(dev); 1919 const struct rtl_coalesce_info *ci; 1920 u32 scale, c_us, c_fr; 1921 u16 intrmit; 1922 1923 if (rtl_is_8125(tp)) 1924 return -EOPNOTSUPP; 1925 1926 memset(ec, 0, sizeof(*ec)); 1927 1928 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1929 ci = rtl_coalesce_info(tp); 1930 if (IS_ERR(ci)) 1931 return PTR_ERR(ci); 1932 1933 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1934 1935 intrmit = RTL_R16(tp, IntrMitigate); 1936 1937 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1938 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1939 1940 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1941 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1942 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1943 1944 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1945 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1946 1947 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1948 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1949 1950 return 0; 1951 } 1952 1953 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1954 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1955 u16 *cp01) 1956 { 1957 const struct rtl_coalesce_info *ci; 1958 u16 i; 1959 1960 ci = rtl_coalesce_info(tp); 1961 if (IS_ERR(ci)) 1962 return PTR_ERR(ci); 1963 1964 for (i = 0; i < 4; i++) { 1965 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1966 *cp01 = i; 1967 return ci->scale_nsecs[i]; 1968 } 1969 } 1970 1971 return -ERANGE; 1972 } 1973 1974 static int rtl_set_coalesce(struct net_device *dev, 1975 struct ethtool_coalesce *ec, 1976 struct kernel_ethtool_coalesce *kernel_coal, 1977 struct netlink_ext_ack *extack) 1978 { 1979 struct rtl8169_private *tp = netdev_priv(dev); 1980 u32 tx_fr = ec->tx_max_coalesced_frames; 1981 u32 rx_fr = ec->rx_max_coalesced_frames; 1982 u32 coal_usec_max, units; 1983 u16 w = 0, cp01 = 0; 1984 int scale; 1985 1986 if (rtl_is_8125(tp)) 1987 return -EOPNOTSUPP; 1988 1989 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1990 return -ERANGE; 1991 1992 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1993 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1994 if (scale < 0) 1995 return scale; 1996 1997 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1998 * not only when usecs=0 because of e.g. the following scenario: 1999 * 2000 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2001 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2002 * - then user does `ethtool -C eth0 rx-usecs 100` 2003 * 2004 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2005 * if we want to ignore rx_frames then it has to be set to 0. 2006 */ 2007 if (rx_fr == 1) 2008 rx_fr = 0; 2009 if (tx_fr == 1) 2010 tx_fr = 0; 2011 2012 /* HW requires time limit to be set if frame limit is set */ 2013 if ((tx_fr && !ec->tx_coalesce_usecs) || 2014 (rx_fr && !ec->rx_coalesce_usecs)) 2015 return -EINVAL; 2016 2017 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2018 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2019 2020 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2021 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2022 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2023 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2024 2025 RTL_W16(tp, IntrMitigate, w); 2026 2027 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2028 if (rtl_is_8168evl_up(tp)) { 2029 if (!rx_fr && !tx_fr) 2030 /* disable packet counter */ 2031 tp->cp_cmd |= PktCntrDisable; 2032 else 2033 tp->cp_cmd &= ~PktCntrDisable; 2034 } 2035 2036 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2037 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2038 rtl_pci_commit(tp); 2039 2040 return 0; 2041 } 2042 2043 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2044 { 2045 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2046 2047 switch (tp->mac_version) { 2048 case RTL_GIGA_MAC_VER_46: 2049 case RTL_GIGA_MAC_VER_48: 2050 tp->tx_lpi_timer = timer_val; 2051 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2052 break; 2053 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 2054 tp->tx_lpi_timer = timer_val; 2055 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2056 break; 2057 default: 2058 break; 2059 } 2060 } 2061 2062 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2063 { 2064 unsigned int speed = tp->phydev->speed; 2065 unsigned int timer = tp->tx_lpi_timer; 2066 2067 if (!timer || speed == SPEED_UNKNOWN) 2068 return 0; 2069 2070 /* tx_lpi_timer value is in bytes */ 2071 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2072 } 2073 2074 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2075 { 2076 struct rtl8169_private *tp = netdev_priv(dev); 2077 int ret; 2078 2079 if (!rtl_supports_eee(tp)) 2080 return -EOPNOTSUPP; 2081 2082 ret = phy_ethtool_get_eee(tp->phydev, data); 2083 if (ret) 2084 return ret; 2085 2086 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2087 2088 return 0; 2089 } 2090 2091 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2092 { 2093 struct rtl8169_private *tp = netdev_priv(dev); 2094 2095 if (!rtl_supports_eee(tp)) 2096 return -EOPNOTSUPP; 2097 2098 return phy_ethtool_set_eee(tp->phydev, data); 2099 } 2100 2101 static void rtl8169_get_ringparam(struct net_device *dev, 2102 struct ethtool_ringparam *data, 2103 struct kernel_ethtool_ringparam *kernel_data, 2104 struct netlink_ext_ack *extack) 2105 { 2106 data->rx_max_pending = NUM_RX_DESC; 2107 data->rx_pending = NUM_RX_DESC; 2108 data->tx_max_pending = NUM_TX_DESC; 2109 data->tx_pending = NUM_TX_DESC; 2110 } 2111 2112 static void rtl8169_get_pause_stats(struct net_device *dev, 2113 struct ethtool_pause_stats *pause_stats) 2114 { 2115 struct rtl8169_private *tp = netdev_priv(dev); 2116 2117 if (!rtl_is_8125(tp)) 2118 return; 2119 2120 rtl8169_update_counters(tp); 2121 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on); 2122 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on); 2123 } 2124 2125 static void rtl8169_get_pauseparam(struct net_device *dev, 2126 struct ethtool_pauseparam *data) 2127 { 2128 struct rtl8169_private *tp = netdev_priv(dev); 2129 bool tx_pause, rx_pause; 2130 2131 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2132 2133 data->autoneg = tp->phydev->autoneg; 2134 data->tx_pause = tx_pause ? 1 : 0; 2135 data->rx_pause = rx_pause ? 1 : 0; 2136 } 2137 2138 static int rtl8169_set_pauseparam(struct net_device *dev, 2139 struct ethtool_pauseparam *data) 2140 { 2141 struct rtl8169_private *tp = netdev_priv(dev); 2142 2143 if (dev->mtu > ETH_DATA_LEN) 2144 return -EOPNOTSUPP; 2145 2146 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2147 2148 return 0; 2149 } 2150 2151 static void rtl8169_get_eth_mac_stats(struct net_device *dev, 2152 struct ethtool_eth_mac_stats *mac_stats) 2153 { 2154 struct rtl8169_private *tp = netdev_priv(dev); 2155 2156 rtl8169_update_counters(tp); 2157 2158 mac_stats->FramesTransmittedOK = 2159 le64_to_cpu(tp->counters->tx_packets); 2160 mac_stats->SingleCollisionFrames = 2161 le32_to_cpu(tp->counters->tx_one_collision); 2162 mac_stats->MultipleCollisionFrames = 2163 le32_to_cpu(tp->counters->tx_multi_collision); 2164 mac_stats->FramesReceivedOK = 2165 le64_to_cpu(tp->counters->rx_packets); 2166 mac_stats->AlignmentErrors = 2167 le16_to_cpu(tp->counters->align_errors); 2168 mac_stats->FramesLostDueToIntMACXmitError = 2169 le64_to_cpu(tp->counters->tx_errors); 2170 mac_stats->BroadcastFramesReceivedOK = 2171 le64_to_cpu(tp->counters->rx_broadcast); 2172 mac_stats->MulticastFramesReceivedOK = 2173 le32_to_cpu(tp->counters->rx_multicast); 2174 2175 if (!rtl_is_8125(tp)) 2176 return; 2177 2178 mac_stats->AlignmentErrors = 2179 le32_to_cpu(tp->counters->align_errors32); 2180 mac_stats->OctetsTransmittedOK = 2181 le64_to_cpu(tp->counters->tx_octets); 2182 mac_stats->LateCollisions = 2183 le32_to_cpu(tp->counters->tx_late_collision); 2184 mac_stats->FramesAbortedDueToXSColls = 2185 le32_to_cpu(tp->counters->tx_aborted32); 2186 mac_stats->OctetsReceivedOK = 2187 le64_to_cpu(tp->counters->rx_octets); 2188 mac_stats->FramesLostDueToIntMACRcvError = 2189 le32_to_cpu(tp->counters->rx_mac_error); 2190 mac_stats->MulticastFramesXmittedOK = 2191 le64_to_cpu(tp->counters->tx_multicast64); 2192 mac_stats->BroadcastFramesXmittedOK = 2193 le64_to_cpu(tp->counters->tx_broadcast64); 2194 mac_stats->MulticastFramesReceivedOK = 2195 le64_to_cpu(tp->counters->rx_multicast64); 2196 mac_stats->FrameTooLongErrors = 2197 le32_to_cpu(tp->counters->rx_frame_too_long); 2198 } 2199 2200 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, 2201 struct ethtool_eth_ctrl_stats *ctrl_stats) 2202 { 2203 struct rtl8169_private *tp = netdev_priv(dev); 2204 2205 if (!rtl_is_8125(tp)) 2206 return; 2207 2208 rtl8169_update_counters(tp); 2209 2210 ctrl_stats->UnsupportedOpcodesReceived = 2211 le32_to_cpu(tp->counters->rx_unknown_opcode); 2212 } 2213 2214 static const struct ethtool_ops rtl8169_ethtool_ops = { 2215 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2216 ETHTOOL_COALESCE_MAX_FRAMES, 2217 .get_drvinfo = rtl8169_get_drvinfo, 2218 .get_regs_len = rtl8169_get_regs_len, 2219 .get_link = ethtool_op_get_link, 2220 .get_coalesce = rtl_get_coalesce, 2221 .set_coalesce = rtl_set_coalesce, 2222 .get_regs = rtl8169_get_regs, 2223 .get_wol = rtl8169_get_wol, 2224 .set_wol = rtl8169_set_wol, 2225 .get_strings = rtl8169_get_strings, 2226 .get_sset_count = rtl8169_get_sset_count, 2227 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2228 .get_ts_info = ethtool_op_get_ts_info, 2229 .nway_reset = phy_ethtool_nway_reset, 2230 .get_eee = rtl8169_get_eee, 2231 .set_eee = rtl8169_set_eee, 2232 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2233 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2234 .get_ringparam = rtl8169_get_ringparam, 2235 .get_pause_stats = rtl8169_get_pause_stats, 2236 .get_pauseparam = rtl8169_get_pauseparam, 2237 .set_pauseparam = rtl8169_set_pauseparam, 2238 .get_eth_mac_stats = rtl8169_get_eth_mac_stats, 2239 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, 2240 }; 2241 2242 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2243 { 2244 /* 2245 * The driver currently handles the 8168Bf and the 8168Be identically 2246 * but they can be identified more specifically through the test below 2247 * if needed: 2248 * 2249 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2250 * 2251 * Same thing for the 8101Eb and the 8101Ec: 2252 * 2253 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2254 */ 2255 static const struct rtl_mac_info { 2256 u16 mask; 2257 u16 val; 2258 enum mac_version ver; 2259 } mac_info[] = { 2260 /* 8126A family. */ 2261 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_71 }, 2262 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70 }, 2263 2264 /* 8125D family. */ 2265 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_65 }, 2266 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, 2267 2268 /* 8125B family. */ 2269 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2270 2271 /* 8125A family. */ 2272 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2273 /* It seems only XID 609 made it to the mass market. 2274 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2275 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2276 */ 2277 2278 /* RTL8117 */ 2279 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2280 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2281 2282 /* 8168EP family. */ 2283 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2284 /* It seems this chip version never made it to 2285 * the wild. Let's disable detection. 2286 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2287 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2288 */ 2289 2290 /* 8168H family. */ 2291 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2292 /* It seems this chip version never made it to 2293 * the wild. Let's disable detection. 2294 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2295 */ 2296 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 2297 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, 2298 2299 /* 8168G family. */ 2300 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2301 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2302 /* It seems this chip version never made it to 2303 * the wild. Let's disable detection. 2304 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2305 */ 2306 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2307 2308 /* 8168F family. */ 2309 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2310 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2311 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2312 2313 /* 8168E family. */ 2314 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2315 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2316 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2317 2318 /* 8168D family. */ 2319 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2320 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2321 2322 /* 8168DP family. */ 2323 /* It seems this early RTL8168dp version never made it to 2324 * the wild. Support has been removed. 2325 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2326 */ 2327 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2328 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2329 2330 /* 8168C family. */ 2331 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2332 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2333 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2334 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2335 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2336 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2337 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2338 2339 /* 8168B family. */ 2340 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2341 /* This one is very old and rare, support has been removed. 2342 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2343 */ 2344 2345 /* 8101 family. */ 2346 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2347 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2348 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2349 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2350 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2351 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2352 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2353 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2354 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2355 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2356 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2357 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2358 2359 /* 8110 family. */ 2360 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2361 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2362 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2363 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2364 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2365 2366 /* Catch-all */ 2367 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2368 }; 2369 const struct rtl_mac_info *p = mac_info; 2370 enum mac_version ver; 2371 2372 while ((xid & p->mask) != p->val) 2373 p++; 2374 ver = p->ver; 2375 2376 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2377 if (ver == RTL_GIGA_MAC_VER_42) 2378 ver = RTL_GIGA_MAC_VER_43; 2379 else if (ver == RTL_GIGA_MAC_VER_46) 2380 ver = RTL_GIGA_MAC_VER_48; 2381 } 2382 2383 return ver; 2384 } 2385 2386 static void rtl_release_firmware(struct rtl8169_private *tp) 2387 { 2388 if (tp->rtl_fw) { 2389 rtl_fw_release_firmware(tp->rtl_fw); 2390 kfree(tp->rtl_fw); 2391 tp->rtl_fw = NULL; 2392 } 2393 } 2394 2395 void r8169_apply_firmware(struct rtl8169_private *tp) 2396 { 2397 int val; 2398 2399 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2400 if (tp->rtl_fw) { 2401 rtl_fw_write_firmware(tp, tp->rtl_fw); 2402 /* At least one firmware doesn't reset tp->ocp_base. */ 2403 tp->ocp_base = OCP_STD_PHY_BASE; 2404 2405 /* PHY soft reset may still be in progress */ 2406 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2407 !(val & BMCR_RESET), 2408 50000, 600000, true); 2409 } 2410 } 2411 2412 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2413 { 2414 /* Adjust EEE LED frequency */ 2415 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2416 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2417 2418 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2419 } 2420 2421 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2422 { 2423 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2424 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2425 } 2426 2427 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2428 { 2429 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2430 } 2431 2432 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2433 { 2434 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2435 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2436 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2437 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2438 } 2439 2440 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2441 { 2442 u16 data1, data2, ioffset; 2443 2444 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2445 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2446 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2447 2448 ioffset = (data2 >> 1) & 0x7ff8; 2449 ioffset |= data2 & 0x0007; 2450 if (data1 & BIT(7)) 2451 ioffset |= BIT(15); 2452 2453 return ioffset; 2454 } 2455 2456 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2457 { 2458 set_bit(flag, tp->wk.flags); 2459 if (!schedule_work(&tp->wk.work)) 2460 clear_bit(flag, tp->wk.flags); 2461 } 2462 2463 static void rtl8169_init_phy(struct rtl8169_private *tp) 2464 { 2465 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2466 2467 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2468 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2469 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2470 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2471 RTL_W8(tp, 0x82, 0x01); 2472 } 2473 2474 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2475 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2476 tp->pci_dev->subsystem_device == 0xe000) 2477 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2478 2479 /* We may have called phy_speed_down before */ 2480 phy_speed_up(tp->phydev); 2481 2482 genphy_soft_reset(tp->phydev); 2483 } 2484 2485 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2486 { 2487 rtl_unlock_config_regs(tp); 2488 2489 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2490 rtl_pci_commit(tp); 2491 2492 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2493 rtl_pci_commit(tp); 2494 2495 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2496 rtl_rar_exgmac_set(tp, addr); 2497 2498 rtl_lock_config_regs(tp); 2499 } 2500 2501 static int rtl_set_mac_address(struct net_device *dev, void *p) 2502 { 2503 struct rtl8169_private *tp = netdev_priv(dev); 2504 int ret; 2505 2506 ret = eth_mac_addr(dev, p); 2507 if (ret) 2508 return ret; 2509 2510 rtl_rar_set(tp, dev->dev_addr); 2511 2512 return 0; 2513 } 2514 2515 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2516 { 2517 switch (tp->mac_version) { 2518 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2519 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2520 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2521 break; 2522 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2523 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2524 case RTL_GIGA_MAC_VER_38: 2525 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2526 break; 2527 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2528 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2529 break; 2530 case RTL_GIGA_MAC_VER_61: 2531 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2532 break; 2533 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71: 2534 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2535 RX_PAUSE_SLOT_ON); 2536 break; 2537 default: 2538 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2539 break; 2540 } 2541 } 2542 2543 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2544 { 2545 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2546 } 2547 2548 static void rtl_jumbo_config(struct rtl8169_private *tp) 2549 { 2550 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2551 int readrq = 4096; 2552 2553 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 && 2554 tp->mac_version <= RTL_GIGA_MAC_VER_26) 2555 readrq = 512; 2556 2557 rtl_unlock_config_regs(tp); 2558 switch (tp->mac_version) { 2559 case RTL_GIGA_MAC_VER_17: 2560 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2561 break; 2562 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2563 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2564 r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo); 2565 break; 2566 case RTL_GIGA_MAC_VER_28: 2567 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2568 break; 2569 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2570 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); 2571 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2572 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2573 break; 2574 default: 2575 break; 2576 } 2577 rtl_lock_config_regs(tp); 2578 2579 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2580 pcie_set_readrq(tp->pci_dev, readrq); 2581 2582 /* Chip doesn't support pause in jumbo mode */ 2583 if (jumbo) { 2584 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2585 tp->phydev->advertising); 2586 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2587 tp->phydev->advertising); 2588 phy_start_aneg(tp->phydev); 2589 } 2590 } 2591 2592 DECLARE_RTL_COND(rtl_chipcmd_cond) 2593 { 2594 return RTL_R8(tp, ChipCmd) & CmdReset; 2595 } 2596 2597 static void rtl_hw_reset(struct rtl8169_private *tp) 2598 { 2599 RTL_W8(tp, ChipCmd, CmdReset); 2600 2601 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2602 } 2603 2604 static void rtl_request_firmware(struct rtl8169_private *tp) 2605 { 2606 struct rtl_fw *rtl_fw; 2607 2608 /* firmware loaded already or no firmware available */ 2609 if (tp->rtl_fw || !tp->fw_name) 2610 return; 2611 2612 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2613 if (!rtl_fw) 2614 return; 2615 2616 rtl_fw->phy_write = rtl_writephy; 2617 rtl_fw->phy_read = rtl_readphy; 2618 rtl_fw->mac_mcu_write = mac_mcu_write; 2619 rtl_fw->mac_mcu_read = mac_mcu_read; 2620 rtl_fw->fw_name = tp->fw_name; 2621 rtl_fw->dev = tp_to_dev(tp); 2622 2623 if (rtl_fw_request_firmware(rtl_fw)) 2624 kfree(rtl_fw); 2625 else 2626 tp->rtl_fw = rtl_fw; 2627 } 2628 2629 static void rtl_rx_close(struct rtl8169_private *tp) 2630 { 2631 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2632 } 2633 2634 DECLARE_RTL_COND(rtl_npq_cond) 2635 { 2636 return RTL_R8(tp, TxPoll) & NPQ; 2637 } 2638 2639 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2640 { 2641 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2642 } 2643 2644 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2645 { 2646 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2647 } 2648 2649 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2650 { 2651 /* IntrMitigate has new functionality on RTL8125 */ 2652 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2653 } 2654 2655 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2656 { 2657 switch (tp->mac_version) { 2658 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2659 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2660 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2661 break; 2662 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2663 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2664 break; 2665 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71: 2666 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2667 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2668 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2669 break; 2670 default: 2671 break; 2672 } 2673 } 2674 2675 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2676 { 2677 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2678 } 2679 2680 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2681 { 2682 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2683 fsleep(2000); 2684 rtl_wait_txrx_fifo_empty(tp); 2685 } 2686 2687 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2688 { 2689 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2690 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2691 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2692 2693 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2694 rtl_disable_rxdvgate(tp); 2695 } 2696 2697 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2698 { 2699 if (tp->dash_enabled) 2700 return; 2701 2702 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2703 tp->mac_version == RTL_GIGA_MAC_VER_33) 2704 rtl_ephy_write(tp, 0x19, 0xff64); 2705 2706 if (device_may_wakeup(tp_to_dev(tp))) { 2707 phy_speed_down(tp->phydev, false); 2708 rtl_wol_enable_rx(tp); 2709 } 2710 } 2711 2712 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2713 { 2714 u32 val = TX_DMA_BURST << TxDMAShift | 2715 InterFrameGap << TxInterFrameGapShift; 2716 2717 if (rtl_is_8168evl_up(tp)) 2718 val |= TXCFG_AUTO_FIFO; 2719 2720 RTL_W32(tp, TxConfig, val); 2721 } 2722 2723 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2724 { 2725 /* Low hurts. Let's disable the filtering. */ 2726 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2727 } 2728 2729 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2730 { 2731 /* 2732 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2733 * register to be written before TxDescAddrLow to work. 2734 * Switching from MMIO to I/O access fixes the issue as well. 2735 */ 2736 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2737 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2738 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2739 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2740 } 2741 2742 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2743 { 2744 u32 val; 2745 2746 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2747 val = 0x000fff00; 2748 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2749 val = 0x00ffff00; 2750 else 2751 return; 2752 2753 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2754 val |= 0xff; 2755 2756 RTL_W32(tp, 0x7c, val); 2757 } 2758 2759 static void rtl_set_rx_mode(struct net_device *dev) 2760 { 2761 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2762 /* Multicast hash filter */ 2763 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2764 struct rtl8169_private *tp = netdev_priv(dev); 2765 u32 tmp; 2766 2767 if (dev->flags & IFF_PROMISC) { 2768 rx_mode |= AcceptAllPhys; 2769 } else if (!(dev->flags & IFF_MULTICAST)) { 2770 rx_mode &= ~AcceptMulticast; 2771 } else if (dev->flags & IFF_ALLMULTI || 2772 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2773 /* accept all multicasts */ 2774 } else if (netdev_mc_empty(dev)) { 2775 rx_mode &= ~AcceptMulticast; 2776 } else { 2777 struct netdev_hw_addr *ha; 2778 2779 mc_filter[1] = mc_filter[0] = 0; 2780 netdev_for_each_mc_addr(ha, dev) { 2781 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2782 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2783 } 2784 2785 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2786 tmp = mc_filter[0]; 2787 mc_filter[0] = swab32(mc_filter[1]); 2788 mc_filter[1] = swab32(tmp); 2789 } 2790 } 2791 2792 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2793 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2794 2795 tmp = RTL_R32(tp, RxConfig); 2796 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2797 } 2798 2799 DECLARE_RTL_COND(rtl_csiar_cond) 2800 { 2801 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2802 } 2803 2804 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2805 { 2806 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2807 2808 RTL_W32(tp, CSIDR, value); 2809 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2810 CSIAR_BYTE_ENABLE | func << 16); 2811 2812 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2813 } 2814 2815 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2816 { 2817 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2818 2819 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2820 CSIAR_BYTE_ENABLE); 2821 2822 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2823 RTL_R32(tp, CSIDR) : ~0; 2824 } 2825 2826 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2827 { 2828 struct pci_dev *pdev = tp->pci_dev; 2829 u32 csi; 2830 2831 /* According to Realtek the value at config space address 0x070f 2832 * controls the L0s/L1 entrance latency. We try standard ECAM access 2833 * first and if it fails fall back to CSI. 2834 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2835 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2836 */ 2837 if (pdev->cfg_size > 0x070f && 2838 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2839 return; 2840 2841 netdev_notice_once(tp->dev, 2842 "No native access to PCI extended config space, falling back to CSI\n"); 2843 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2844 rtl_csi_write(tp, 0x070c, csi | val << 24); 2845 } 2846 2847 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2848 { 2849 /* L0 7us, L1 16us */ 2850 rtl_set_aspm_entry_latency(tp, 0x27); 2851 } 2852 2853 struct ephy_info { 2854 unsigned int offset; 2855 u16 mask; 2856 u16 bits; 2857 }; 2858 2859 static void __rtl_ephy_init(struct rtl8169_private *tp, 2860 const struct ephy_info *e, int len) 2861 { 2862 u16 w; 2863 2864 while (len-- > 0) { 2865 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2866 rtl_ephy_write(tp, e->offset, w); 2867 e++; 2868 } 2869 } 2870 2871 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2872 2873 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2874 { 2875 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2876 PCI_EXP_LNKCTL_CLKREQ_EN); 2877 } 2878 2879 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2880 { 2881 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2882 PCI_EXP_LNKCTL_CLKREQ_EN); 2883 } 2884 2885 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2886 { 2887 /* work around an issue when PCI reset occurs during L2/L3 state */ 2888 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2889 } 2890 2891 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2892 { 2893 /* Bits control which events trigger ASPM L1 exit: 2894 * Bit 12: rxdv 2895 * Bit 11: ltr_msg 2896 * Bit 10: txdma_poll 2897 * Bit 9: xadm 2898 * Bit 8: pktavi 2899 * Bit 7: txpla 2900 */ 2901 switch (tp->mac_version) { 2902 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2903 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2904 break; 2905 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2906 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2907 break; 2908 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 2909 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2910 break; 2911 default: 2912 break; 2913 } 2914 } 2915 2916 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2917 { 2918 switch (tp->mac_version) { 2919 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2920 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2921 break; 2922 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 2923 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2924 break; 2925 default: 2926 break; 2927 } 2928 } 2929 2930 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2931 { 2932 u8 val8; 2933 2934 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2935 return; 2936 2937 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2938 if (enable && tp->aspm_manageable) { 2939 /* On these chip versions ASPM can even harm 2940 * bus communication of other PCI devices. 2941 */ 2942 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2943 tp->mac_version == RTL_GIGA_MAC_VER_43) 2944 return; 2945 2946 rtl_mod_config5(tp, 0, ASPM_en); 2947 switch (tp->mac_version) { 2948 case RTL_GIGA_MAC_VER_70: 2949 case RTL_GIGA_MAC_VER_71: 2950 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2951 RTL_W8(tp, INT_CFG0_8125, val8); 2952 break; 2953 default: 2954 rtl_mod_config2(tp, 0, ClkReqEn); 2955 break; 2956 } 2957 2958 switch (tp->mac_version) { 2959 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2960 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 2961 /* reset ephy tx/rx disable timer */ 2962 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2963 /* chip can trigger L1.2 */ 2964 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2965 break; 2966 default: 2967 break; 2968 } 2969 } else { 2970 switch (tp->mac_version) { 2971 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2972 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 2973 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2974 break; 2975 default: 2976 break; 2977 } 2978 2979 switch (tp->mac_version) { 2980 case RTL_GIGA_MAC_VER_70: 2981 case RTL_GIGA_MAC_VER_71: 2982 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2983 RTL_W8(tp, INT_CFG0_8125, val8); 2984 break; 2985 default: 2986 rtl_mod_config2(tp, ClkReqEn, 0); 2987 break; 2988 } 2989 rtl_mod_config5(tp, ASPM_en, 0); 2990 } 2991 } 2992 2993 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2994 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2995 { 2996 /* Usage of dynamic vs. static FIFO is controlled by bit 2997 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2998 */ 2999 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 3000 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 3001 } 3002 3003 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3004 u8 low, u8 high) 3005 { 3006 /* FIFO thresholds for pause flow control */ 3007 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3008 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3009 } 3010 3011 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3012 { 3013 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3014 } 3015 3016 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3017 { 3018 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3019 3020 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3021 3022 rtl_disable_clock_request(tp); 3023 } 3024 3025 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3026 { 3027 static const struct ephy_info e_info_8168cp[] = { 3028 { 0x01, 0, 0x0001 }, 3029 { 0x02, 0x0800, 0x1000 }, 3030 { 0x03, 0, 0x0042 }, 3031 { 0x06, 0x0080, 0x0000 }, 3032 { 0x07, 0, 0x2000 } 3033 }; 3034 3035 rtl_set_def_aspm_entry_latency(tp); 3036 3037 rtl_ephy_init(tp, e_info_8168cp); 3038 3039 __rtl_hw_start_8168cp(tp); 3040 } 3041 3042 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3043 { 3044 rtl_set_def_aspm_entry_latency(tp); 3045 3046 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3047 } 3048 3049 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3050 { 3051 rtl_set_def_aspm_entry_latency(tp); 3052 3053 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3054 3055 /* Magic. */ 3056 RTL_W8(tp, DBG_REG, 0x20); 3057 } 3058 3059 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3060 { 3061 static const struct ephy_info e_info_8168c_1[] = { 3062 { 0x02, 0x0800, 0x1000 }, 3063 { 0x03, 0, 0x0002 }, 3064 { 0x06, 0x0080, 0x0000 } 3065 }; 3066 3067 rtl_set_def_aspm_entry_latency(tp); 3068 3069 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3070 3071 rtl_ephy_init(tp, e_info_8168c_1); 3072 3073 __rtl_hw_start_8168cp(tp); 3074 } 3075 3076 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3077 { 3078 static const struct ephy_info e_info_8168c_2[] = { 3079 { 0x01, 0, 0x0001 }, 3080 { 0x03, 0x0400, 0x0020 } 3081 }; 3082 3083 rtl_set_def_aspm_entry_latency(tp); 3084 3085 rtl_ephy_init(tp, e_info_8168c_2); 3086 3087 __rtl_hw_start_8168cp(tp); 3088 } 3089 3090 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3091 { 3092 rtl_set_def_aspm_entry_latency(tp); 3093 3094 __rtl_hw_start_8168cp(tp); 3095 } 3096 3097 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3098 { 3099 rtl_set_def_aspm_entry_latency(tp); 3100 3101 rtl_disable_clock_request(tp); 3102 } 3103 3104 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3105 { 3106 static const struct ephy_info e_info_8168d_4[] = { 3107 { 0x0b, 0x0000, 0x0048 }, 3108 { 0x19, 0x0020, 0x0050 }, 3109 { 0x0c, 0x0100, 0x0020 }, 3110 { 0x10, 0x0004, 0x0000 }, 3111 }; 3112 3113 rtl_set_def_aspm_entry_latency(tp); 3114 3115 rtl_ephy_init(tp, e_info_8168d_4); 3116 3117 rtl_enable_clock_request(tp); 3118 } 3119 3120 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3121 { 3122 static const struct ephy_info e_info_8168e_1[] = { 3123 { 0x00, 0x0200, 0x0100 }, 3124 { 0x00, 0x0000, 0x0004 }, 3125 { 0x06, 0x0002, 0x0001 }, 3126 { 0x06, 0x0000, 0x0030 }, 3127 { 0x07, 0x0000, 0x2000 }, 3128 { 0x00, 0x0000, 0x0020 }, 3129 { 0x03, 0x5800, 0x2000 }, 3130 { 0x03, 0x0000, 0x0001 }, 3131 { 0x01, 0x0800, 0x1000 }, 3132 { 0x07, 0x0000, 0x4000 }, 3133 { 0x1e, 0x0000, 0x2000 }, 3134 { 0x19, 0xffff, 0xfe6c }, 3135 { 0x0a, 0x0000, 0x0040 } 3136 }; 3137 3138 rtl_set_def_aspm_entry_latency(tp); 3139 3140 rtl_ephy_init(tp, e_info_8168e_1); 3141 3142 rtl_disable_clock_request(tp); 3143 3144 /* Reset tx FIFO pointer */ 3145 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3146 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3147 3148 rtl_mod_config5(tp, Spi_en, 0); 3149 } 3150 3151 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3152 { 3153 static const struct ephy_info e_info_8168e_2[] = { 3154 { 0x09, 0x0000, 0x0080 }, 3155 { 0x19, 0x0000, 0x0224 }, 3156 { 0x00, 0x0000, 0x0004 }, 3157 { 0x0c, 0x3df0, 0x0200 }, 3158 }; 3159 3160 rtl_set_def_aspm_entry_latency(tp); 3161 3162 rtl_ephy_init(tp, e_info_8168e_2); 3163 3164 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3165 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3166 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3167 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3168 rtl_reset_packet_filter(tp); 3169 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3170 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3171 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3172 3173 rtl_disable_clock_request(tp); 3174 3175 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3176 3177 rtl8168_config_eee_mac(tp); 3178 3179 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3180 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3181 rtl_mod_config5(tp, Spi_en, 0); 3182 } 3183 3184 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3185 { 3186 rtl_set_def_aspm_entry_latency(tp); 3187 3188 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3189 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3190 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3191 rtl_reset_packet_filter(tp); 3192 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3193 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3194 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3195 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3196 3197 rtl_disable_clock_request(tp); 3198 3199 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3200 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3201 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3202 rtl_mod_config5(tp, Spi_en, 0); 3203 3204 rtl8168_config_eee_mac(tp); 3205 } 3206 3207 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3208 { 3209 static const struct ephy_info e_info_8168f_1[] = { 3210 { 0x06, 0x00c0, 0x0020 }, 3211 { 0x08, 0x0001, 0x0002 }, 3212 { 0x09, 0x0000, 0x0080 }, 3213 { 0x19, 0x0000, 0x0224 }, 3214 { 0x00, 0x0000, 0x0008 }, 3215 { 0x0c, 0x3df0, 0x0200 }, 3216 }; 3217 3218 rtl_hw_start_8168f(tp); 3219 3220 rtl_ephy_init(tp, e_info_8168f_1); 3221 } 3222 3223 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3224 { 3225 static const struct ephy_info e_info_8168f_1[] = { 3226 { 0x06, 0x00c0, 0x0020 }, 3227 { 0x0f, 0xffff, 0x5200 }, 3228 { 0x19, 0x0000, 0x0224 }, 3229 { 0x00, 0x0000, 0x0008 }, 3230 { 0x0c, 0x3df0, 0x0200 }, 3231 }; 3232 3233 rtl_hw_start_8168f(tp); 3234 rtl_pcie_state_l2l3_disable(tp); 3235 3236 rtl_ephy_init(tp, e_info_8168f_1); 3237 } 3238 3239 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3240 { 3241 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3242 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3243 3244 rtl_set_def_aspm_entry_latency(tp); 3245 3246 rtl_reset_packet_filter(tp); 3247 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3248 3249 rtl_disable_rxdvgate(tp); 3250 3251 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3252 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3253 3254 rtl8168_config_eee_mac(tp); 3255 3256 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3257 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3258 3259 rtl_pcie_state_l2l3_disable(tp); 3260 } 3261 3262 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3263 { 3264 static const struct ephy_info e_info_8168g_1[] = { 3265 { 0x00, 0x0008, 0x0000 }, 3266 { 0x0c, 0x3ff0, 0x0820 }, 3267 { 0x1e, 0x0000, 0x0001 }, 3268 { 0x19, 0x8000, 0x0000 } 3269 }; 3270 3271 rtl_hw_start_8168g(tp); 3272 rtl_ephy_init(tp, e_info_8168g_1); 3273 } 3274 3275 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3276 { 3277 static const struct ephy_info e_info_8168g_2[] = { 3278 { 0x00, 0x0008, 0x0000 }, 3279 { 0x0c, 0x3ff0, 0x0820 }, 3280 { 0x19, 0xffff, 0x7c00 }, 3281 { 0x1e, 0xffff, 0x20eb }, 3282 { 0x0d, 0xffff, 0x1666 }, 3283 { 0x00, 0xffff, 0x10a3 }, 3284 { 0x06, 0xffff, 0xf050 }, 3285 { 0x04, 0x0000, 0x0010 }, 3286 { 0x1d, 0x4000, 0x0000 }, 3287 }; 3288 3289 rtl_hw_start_8168g(tp); 3290 rtl_ephy_init(tp, e_info_8168g_2); 3291 } 3292 3293 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3294 { 3295 static const u16 fix_data[] = { 3296 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3297 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3298 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3299 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3300 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3301 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3302 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3303 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3304 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3305 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3306 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3307 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3308 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3309 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3310 }; 3311 unsigned long flags; 3312 int i; 3313 3314 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3315 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3316 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3317 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3318 } 3319 3320 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3321 { 3322 static const struct ephy_info e_info_8411_2[] = { 3323 { 0x00, 0x0008, 0x0000 }, 3324 { 0x0c, 0x37d0, 0x0820 }, 3325 { 0x1e, 0x0000, 0x0001 }, 3326 { 0x19, 0x8021, 0x0000 }, 3327 { 0x1e, 0x0000, 0x2000 }, 3328 { 0x0d, 0x0100, 0x0200 }, 3329 { 0x00, 0x0000, 0x0080 }, 3330 { 0x06, 0x0000, 0x0010 }, 3331 { 0x04, 0x0000, 0x0010 }, 3332 { 0x1d, 0x0000, 0x4000 }, 3333 }; 3334 3335 rtl_hw_start_8168g(tp); 3336 3337 rtl_ephy_init(tp, e_info_8411_2); 3338 3339 /* The following Realtek-provided magic fixes an issue with the RX unit 3340 * getting confused after the PHY having been powered-down. 3341 */ 3342 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3343 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3344 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3345 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3346 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3347 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3348 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3349 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3350 mdelay(3); 3351 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3352 3353 rtl8411b_fix_phy_down(tp); 3354 3355 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3356 3357 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3358 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3359 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3360 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3361 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3362 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3363 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3364 } 3365 3366 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3367 { 3368 static const struct ephy_info e_info_8168h_1[] = { 3369 { 0x1e, 0x0800, 0x0001 }, 3370 { 0x1d, 0x0000, 0x0800 }, 3371 { 0x05, 0xffff, 0x2089 }, 3372 { 0x06, 0xffff, 0x5881 }, 3373 { 0x04, 0xffff, 0x854a }, 3374 { 0x01, 0xffff, 0x068b } 3375 }; 3376 int rg_saw_cnt; 3377 3378 rtl_ephy_init(tp, e_info_8168h_1); 3379 3380 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3381 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3382 3383 rtl_set_def_aspm_entry_latency(tp); 3384 3385 rtl_reset_packet_filter(tp); 3386 3387 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3388 3389 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3390 3391 rtl_disable_rxdvgate(tp); 3392 3393 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3394 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3395 3396 rtl8168_config_eee_mac(tp); 3397 3398 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3399 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3400 3401 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3402 3403 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3404 3405 rtl_pcie_state_l2l3_disable(tp); 3406 3407 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3408 if (rg_saw_cnt > 0) { 3409 u16 sw_cnt_1ms_ini; 3410 3411 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3412 sw_cnt_1ms_ini &= 0x0fff; 3413 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3414 } 3415 3416 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3417 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3418 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3419 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3420 3421 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3422 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3423 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3424 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3425 } 3426 3427 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3428 { 3429 rtl8168ep_stop_cmac(tp); 3430 3431 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3432 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3433 3434 rtl_set_def_aspm_entry_latency(tp); 3435 3436 rtl_reset_packet_filter(tp); 3437 3438 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3439 3440 rtl_disable_rxdvgate(tp); 3441 3442 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3443 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3444 3445 rtl8168_config_eee_mac(tp); 3446 3447 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3448 3449 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3450 3451 rtl_pcie_state_l2l3_disable(tp); 3452 } 3453 3454 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3455 { 3456 static const struct ephy_info e_info_8168ep_3[] = { 3457 { 0x00, 0x0000, 0x0080 }, 3458 { 0x0d, 0x0100, 0x0200 }, 3459 { 0x19, 0x8021, 0x0000 }, 3460 { 0x1e, 0x0000, 0x2000 }, 3461 }; 3462 3463 rtl_ephy_init(tp, e_info_8168ep_3); 3464 3465 rtl_hw_start_8168ep(tp); 3466 3467 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3468 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3469 3470 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3471 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3472 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3473 } 3474 3475 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3476 { 3477 static const struct ephy_info e_info_8117[] = { 3478 { 0x19, 0x0040, 0x1100 }, 3479 { 0x59, 0x0040, 0x1100 }, 3480 }; 3481 int rg_saw_cnt; 3482 3483 rtl8168ep_stop_cmac(tp); 3484 rtl_ephy_init(tp, e_info_8117); 3485 3486 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3487 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3488 3489 rtl_set_def_aspm_entry_latency(tp); 3490 3491 rtl_reset_packet_filter(tp); 3492 3493 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3494 3495 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3496 3497 rtl_disable_rxdvgate(tp); 3498 3499 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3500 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3501 3502 rtl8168_config_eee_mac(tp); 3503 3504 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3505 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3506 3507 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3508 3509 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3510 3511 rtl_pcie_state_l2l3_disable(tp); 3512 3513 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3514 if (rg_saw_cnt > 0) { 3515 u16 sw_cnt_1ms_ini; 3516 3517 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3518 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3519 } 3520 3521 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3522 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3523 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3524 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3525 3526 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3527 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3528 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3529 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3530 3531 /* firmware is for MAC only */ 3532 r8169_apply_firmware(tp); 3533 } 3534 3535 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3536 { 3537 static const struct ephy_info e_info_8102e_1[] = { 3538 { 0x01, 0, 0x6e65 }, 3539 { 0x02, 0, 0x091f }, 3540 { 0x03, 0, 0xc2f9 }, 3541 { 0x06, 0, 0xafb5 }, 3542 { 0x07, 0, 0x0e00 }, 3543 { 0x19, 0, 0xec80 }, 3544 { 0x01, 0, 0x2e65 }, 3545 { 0x01, 0, 0x6e65 } 3546 }; 3547 u8 cfg1; 3548 3549 rtl_set_def_aspm_entry_latency(tp); 3550 3551 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3552 3553 RTL_W8(tp, Config1, 3554 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3555 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3556 3557 cfg1 = RTL_R8(tp, Config1); 3558 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3559 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3560 3561 rtl_ephy_init(tp, e_info_8102e_1); 3562 } 3563 3564 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3565 { 3566 rtl_set_def_aspm_entry_latency(tp); 3567 3568 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3569 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3570 } 3571 3572 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3573 { 3574 rtl_hw_start_8102e_2(tp); 3575 3576 rtl_ephy_write(tp, 0x03, 0xc2f9); 3577 } 3578 3579 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3580 { 3581 static const struct ephy_info e_info_8401[] = { 3582 { 0x01, 0xffff, 0x6fe5 }, 3583 { 0x03, 0xffff, 0x0599 }, 3584 { 0x06, 0xffff, 0xaf25 }, 3585 { 0x07, 0xffff, 0x8e68 }, 3586 }; 3587 3588 rtl_ephy_init(tp, e_info_8401); 3589 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3590 } 3591 3592 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3593 { 3594 static const struct ephy_info e_info_8105e_1[] = { 3595 { 0x07, 0, 0x4000 }, 3596 { 0x19, 0, 0x0200 }, 3597 { 0x19, 0, 0x0020 }, 3598 { 0x1e, 0, 0x2000 }, 3599 { 0x03, 0, 0x0001 }, 3600 { 0x19, 0, 0x0100 }, 3601 { 0x19, 0, 0x0004 }, 3602 { 0x0a, 0, 0x0020 } 3603 }; 3604 3605 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3606 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3607 3608 /* Disable Early Tally Counter */ 3609 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3610 3611 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3612 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3613 3614 rtl_ephy_init(tp, e_info_8105e_1); 3615 3616 rtl_pcie_state_l2l3_disable(tp); 3617 } 3618 3619 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3620 { 3621 rtl_hw_start_8105e_1(tp); 3622 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3623 } 3624 3625 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3626 { 3627 static const struct ephy_info e_info_8402[] = { 3628 { 0x19, 0xffff, 0xff64 }, 3629 { 0x1e, 0, 0x4000 } 3630 }; 3631 3632 rtl_set_def_aspm_entry_latency(tp); 3633 3634 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3635 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3636 3637 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3638 3639 rtl_ephy_init(tp, e_info_8402); 3640 3641 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3642 rtl_reset_packet_filter(tp); 3643 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3644 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3645 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3646 3647 /* disable EEE */ 3648 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3649 3650 rtl_pcie_state_l2l3_disable(tp); 3651 } 3652 3653 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3654 { 3655 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3656 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3657 3658 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3659 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3660 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3661 3662 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3663 rtl_set_aspm_entry_latency(tp, 0x2f); 3664 3665 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3666 3667 /* disable EEE */ 3668 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3669 3670 rtl_pcie_state_l2l3_disable(tp); 3671 } 3672 3673 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3674 { 3675 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3676 } 3677 3678 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3679 { 3680 rtl_pcie_state_l2l3_disable(tp); 3681 3682 RTL_W16(tp, 0x382, 0x221b); 3683 RTL_W32(tp, RSS_CTRL_8125, 0); 3684 RTL_W16(tp, Q_NUM_CTRL_8125, 0); 3685 3686 /* disable UPS */ 3687 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3688 3689 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3690 3691 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3692 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3693 3694 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3695 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3696 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3697 3698 /* disable new tx descriptor format */ 3699 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3700 3701 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3702 tp->mac_version == RTL_GIGA_MAC_VER_71) 3703 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3704 3705 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3706 tp->mac_version == RTL_GIGA_MAC_VER_71) 3707 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3708 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3709 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3710 else 3711 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3712 3713 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3714 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3715 else 3716 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3717 3718 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3719 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3720 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3721 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3722 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3723 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3724 if (tp->mac_version == RTL_GIGA_MAC_VER_70 || 3725 tp->mac_version == RTL_GIGA_MAC_VER_71) 3726 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3727 else 3728 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3729 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3730 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3731 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3732 3733 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3734 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3735 udelay(1); 3736 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3737 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3738 3739 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3740 3741 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3742 3743 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3744 rtl8125a_config_eee_mac(tp); 3745 else 3746 rtl8125b_config_eee_mac(tp); 3747 3748 rtl_disable_rxdvgate(tp); 3749 } 3750 3751 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3752 { 3753 static const struct ephy_info e_info_8125a_2[] = { 3754 { 0x04, 0xffff, 0xd000 }, 3755 { 0x0a, 0xffff, 0x8653 }, 3756 { 0x23, 0xffff, 0xab66 }, 3757 { 0x20, 0xffff, 0x9455 }, 3758 { 0x21, 0xffff, 0x99ff }, 3759 { 0x29, 0xffff, 0xfe04 }, 3760 3761 { 0x44, 0xffff, 0xd000 }, 3762 { 0x4a, 0xffff, 0x8653 }, 3763 { 0x63, 0xffff, 0xab66 }, 3764 { 0x60, 0xffff, 0x9455 }, 3765 { 0x61, 0xffff, 0x99ff }, 3766 { 0x69, 0xffff, 0xfe04 }, 3767 }; 3768 3769 rtl_set_def_aspm_entry_latency(tp); 3770 rtl_ephy_init(tp, e_info_8125a_2); 3771 rtl_hw_start_8125_common(tp); 3772 } 3773 3774 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3775 { 3776 static const struct ephy_info e_info_8125b[] = { 3777 { 0x0b, 0xffff, 0xa908 }, 3778 { 0x1e, 0xffff, 0x20eb }, 3779 { 0x4b, 0xffff, 0xa908 }, 3780 { 0x5e, 0xffff, 0x20eb }, 3781 { 0x22, 0x0030, 0x0020 }, 3782 { 0x62, 0x0030, 0x0020 }, 3783 }; 3784 3785 rtl_set_def_aspm_entry_latency(tp); 3786 rtl_ephy_init(tp, e_info_8125b); 3787 rtl_hw_start_8125_common(tp); 3788 } 3789 3790 static void rtl_hw_start_8125d(struct rtl8169_private *tp) 3791 { 3792 rtl_set_def_aspm_entry_latency(tp); 3793 rtl_hw_start_8125_common(tp); 3794 } 3795 3796 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3797 { 3798 rtl_set_def_aspm_entry_latency(tp); 3799 rtl_hw_start_8125_common(tp); 3800 } 3801 3802 static void rtl_hw_config(struct rtl8169_private *tp) 3803 { 3804 static const rtl_generic_fct hw_configs[] = { 3805 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3806 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3807 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3808 [RTL_GIGA_MAC_VER_10] = NULL, 3809 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3810 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3811 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3812 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3813 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3814 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3815 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3816 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3817 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3818 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3819 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3820 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3821 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3822 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3823 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3824 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3825 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3826 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3827 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3828 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3829 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3830 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3831 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3832 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3833 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3834 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3835 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3836 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3837 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3838 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3839 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3840 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3841 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3842 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3843 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, 3844 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d, 3845 [RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a, 3846 [RTL_GIGA_MAC_VER_71] = rtl_hw_start_8126a, 3847 }; 3848 3849 if (hw_configs[tp->mac_version]) 3850 hw_configs[tp->mac_version](tp); 3851 } 3852 3853 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3854 { 3855 int i; 3856 3857 RTL_W8(tp, INT_CFG0_8125, 0x00); 3858 3859 /* disable interrupt coalescing */ 3860 switch (tp->mac_version) { 3861 case RTL_GIGA_MAC_VER_61: 3862 case RTL_GIGA_MAC_VER_64: 3863 case RTL_GIGA_MAC_VER_65: 3864 for (i = 0xa00; i < 0xb00; i += 4) 3865 RTL_W32(tp, i, 0); 3866 break; 3867 case RTL_GIGA_MAC_VER_63: 3868 case RTL_GIGA_MAC_VER_70: 3869 case RTL_GIGA_MAC_VER_71: 3870 for (i = 0xa00; i < 0xa80; i += 4) 3871 RTL_W32(tp, i, 0); 3872 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3873 break; 3874 default: 3875 break; 3876 } 3877 3878 /* enable extended tally counter */ 3879 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); 3880 3881 rtl_hw_config(tp); 3882 } 3883 3884 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3885 { 3886 if (rtl_is_8168evl_up(tp)) 3887 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3888 else 3889 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3890 3891 rtl_hw_config(tp); 3892 3893 /* disable interrupt coalescing */ 3894 RTL_W16(tp, IntrMitigate, 0x0000); 3895 } 3896 3897 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3898 { 3899 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3900 3901 tp->cp_cmd |= PCIMulRW; 3902 3903 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3904 tp->mac_version == RTL_GIGA_MAC_VER_03) 3905 tp->cp_cmd |= EnAnaPLL; 3906 3907 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3908 3909 rtl8169_set_magic_reg(tp); 3910 3911 /* disable interrupt coalescing */ 3912 RTL_W16(tp, IntrMitigate, 0x0000); 3913 } 3914 3915 static void rtl_hw_start(struct rtl8169_private *tp) 3916 { 3917 rtl_unlock_config_regs(tp); 3918 /* disable aspm and clock request before ephy access */ 3919 rtl_hw_aspm_clkreq_enable(tp, false); 3920 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3921 3922 rtl_set_eee_txidle_timer(tp); 3923 3924 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3925 rtl_hw_start_8169(tp); 3926 else if (rtl_is_8125(tp)) 3927 rtl_hw_start_8125(tp); 3928 else 3929 rtl_hw_start_8168(tp); 3930 3931 rtl_enable_exit_l1(tp); 3932 rtl_hw_aspm_clkreq_enable(tp, true); 3933 rtl_set_rx_max_size(tp); 3934 rtl_set_rx_tx_desc_registers(tp); 3935 rtl_lock_config_regs(tp); 3936 3937 rtl_jumbo_config(tp); 3938 3939 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3940 rtl_pci_commit(tp); 3941 3942 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3943 rtl_init_rxcfg(tp); 3944 rtl_set_tx_config_registers(tp); 3945 rtl_set_rx_config_features(tp, tp->dev->features); 3946 rtl_set_rx_mode(tp->dev); 3947 rtl_irq_enable(tp); 3948 } 3949 3950 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3951 { 3952 struct rtl8169_private *tp = netdev_priv(dev); 3953 3954 WRITE_ONCE(dev->mtu, new_mtu); 3955 netdev_update_features(dev); 3956 rtl_jumbo_config(tp); 3957 rtl_set_eee_txidle_timer(tp); 3958 3959 return 0; 3960 } 3961 3962 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3963 { 3964 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3965 3966 desc->opts2 = 0; 3967 /* Force memory writes to complete before releasing descriptor */ 3968 dma_wmb(); 3969 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3970 } 3971 3972 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3973 struct RxDesc *desc) 3974 { 3975 struct device *d = tp_to_dev(tp); 3976 int node = dev_to_node(d); 3977 dma_addr_t mapping; 3978 struct page *data; 3979 3980 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3981 if (!data) 3982 return NULL; 3983 3984 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3985 if (unlikely(dma_mapping_error(d, mapping))) { 3986 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3987 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3988 return NULL; 3989 } 3990 3991 desc->addr = cpu_to_le64(mapping); 3992 rtl8169_mark_to_asic(desc); 3993 3994 return data; 3995 } 3996 3997 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3998 { 3999 int i; 4000 4001 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 4002 dma_unmap_page(tp_to_dev(tp), 4003 le64_to_cpu(tp->RxDescArray[i].addr), 4004 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4005 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4006 tp->Rx_databuff[i] = NULL; 4007 tp->RxDescArray[i].addr = 0; 4008 tp->RxDescArray[i].opts1 = 0; 4009 } 4010 } 4011 4012 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4013 { 4014 int i; 4015 4016 for (i = 0; i < NUM_RX_DESC; i++) { 4017 struct page *data; 4018 4019 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4020 if (!data) { 4021 rtl8169_rx_clear(tp); 4022 return -ENOMEM; 4023 } 4024 tp->Rx_databuff[i] = data; 4025 } 4026 4027 /* mark as last descriptor in the ring */ 4028 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4029 4030 return 0; 4031 } 4032 4033 static int rtl8169_init_ring(struct rtl8169_private *tp) 4034 { 4035 rtl8169_init_ring_indexes(tp); 4036 4037 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4038 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4039 4040 return rtl8169_rx_fill(tp); 4041 } 4042 4043 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4044 { 4045 struct ring_info *tx_skb = tp->tx_skb + entry; 4046 struct TxDesc *desc = tp->TxDescArray + entry; 4047 4048 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4049 DMA_TO_DEVICE); 4050 memset(desc, 0, sizeof(*desc)); 4051 memset(tx_skb, 0, sizeof(*tx_skb)); 4052 } 4053 4054 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4055 unsigned int n) 4056 { 4057 unsigned int i; 4058 4059 for (i = 0; i < n; i++) { 4060 unsigned int entry = (start + i) % NUM_TX_DESC; 4061 struct ring_info *tx_skb = tp->tx_skb + entry; 4062 unsigned int len = tx_skb->len; 4063 4064 if (len) { 4065 struct sk_buff *skb = tx_skb->skb; 4066 4067 rtl8169_unmap_tx_skb(tp, entry); 4068 if (skb) 4069 dev_consume_skb_any(skb); 4070 } 4071 } 4072 } 4073 4074 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4075 { 4076 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4077 netdev_reset_queue(tp->dev); 4078 } 4079 4080 static void rtl8169_cleanup(struct rtl8169_private *tp) 4081 { 4082 napi_disable(&tp->napi); 4083 4084 /* Give a racing hard_start_xmit a few cycles to complete. */ 4085 synchronize_net(); 4086 4087 /* Disable interrupts */ 4088 rtl8169_irq_mask_and_ack(tp); 4089 4090 rtl_rx_close(tp); 4091 4092 switch (tp->mac_version) { 4093 case RTL_GIGA_MAC_VER_28: 4094 case RTL_GIGA_MAC_VER_31: 4095 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4096 break; 4097 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4098 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4099 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4100 break; 4101 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71: 4102 rtl_enable_rxdvgate(tp); 4103 fsleep(2000); 4104 break; 4105 default: 4106 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4107 fsleep(100); 4108 break; 4109 } 4110 4111 rtl_hw_reset(tp); 4112 4113 rtl8169_tx_clear(tp); 4114 rtl8169_init_ring_indexes(tp); 4115 } 4116 4117 static void rtl_reset_work(struct rtl8169_private *tp) 4118 { 4119 int i; 4120 4121 netif_stop_queue(tp->dev); 4122 4123 rtl8169_cleanup(tp); 4124 4125 for (i = 0; i < NUM_RX_DESC; i++) 4126 rtl8169_mark_to_asic(tp->RxDescArray + i); 4127 4128 napi_enable(&tp->napi); 4129 rtl_hw_start(tp); 4130 } 4131 4132 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4133 { 4134 struct rtl8169_private *tp = netdev_priv(dev); 4135 4136 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4137 } 4138 4139 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4140 void *addr, unsigned int entry, bool desc_own) 4141 { 4142 struct TxDesc *txd = tp->TxDescArray + entry; 4143 struct device *d = tp_to_dev(tp); 4144 dma_addr_t mapping; 4145 u32 opts1; 4146 int ret; 4147 4148 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4149 ret = dma_mapping_error(d, mapping); 4150 if (unlikely(ret)) { 4151 if (net_ratelimit()) 4152 netdev_err(tp->dev, "Failed to map TX data!\n"); 4153 return ret; 4154 } 4155 4156 txd->addr = cpu_to_le64(mapping); 4157 txd->opts2 = cpu_to_le32(opts[1]); 4158 4159 opts1 = opts[0] | len; 4160 if (entry == NUM_TX_DESC - 1) 4161 opts1 |= RingEnd; 4162 if (desc_own) 4163 opts1 |= DescOwn; 4164 txd->opts1 = cpu_to_le32(opts1); 4165 4166 tp->tx_skb[entry].len = len; 4167 4168 return 0; 4169 } 4170 4171 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4172 const u32 *opts, unsigned int entry) 4173 { 4174 struct skb_shared_info *info = skb_shinfo(skb); 4175 unsigned int cur_frag; 4176 4177 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4178 const skb_frag_t *frag = info->frags + cur_frag; 4179 void *addr = skb_frag_address(frag); 4180 u32 len = skb_frag_size(frag); 4181 4182 entry = (entry + 1) % NUM_TX_DESC; 4183 4184 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4185 goto err_out; 4186 } 4187 4188 return 0; 4189 4190 err_out: 4191 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4192 return -EIO; 4193 } 4194 4195 static bool rtl_skb_is_udp(struct sk_buff *skb) 4196 { 4197 int no = skb_network_offset(skb); 4198 struct ipv6hdr *i6h, _i6h; 4199 struct iphdr *ih, _ih; 4200 4201 switch (vlan_get_protocol(skb)) { 4202 case htons(ETH_P_IP): 4203 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4204 return ih && ih->protocol == IPPROTO_UDP; 4205 case htons(ETH_P_IPV6): 4206 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4207 return i6h && i6h->nexthdr == IPPROTO_UDP; 4208 default: 4209 return false; 4210 } 4211 } 4212 4213 #define RTL_MIN_PATCH_LEN 47 4214 4215 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4216 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4217 struct sk_buff *skb) 4218 { 4219 unsigned int padto = 0, len = skb->len; 4220 4221 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) && 4222 skb_transport_header_was_set(skb)) { 4223 unsigned int trans_data_len = skb_tail_pointer(skb) - 4224 skb_transport_header(skb); 4225 4226 if (trans_data_len >= offsetof(struct udphdr, len) && 4227 trans_data_len < RTL_MIN_PATCH_LEN) { 4228 u16 dest = ntohs(udp_hdr(skb)->dest); 4229 4230 /* dest is a standard PTP port */ 4231 if (dest == 319 || dest == 320) 4232 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4233 } 4234 4235 if (trans_data_len < sizeof(struct udphdr)) 4236 padto = max_t(unsigned int, padto, 4237 len + sizeof(struct udphdr) - trans_data_len); 4238 } 4239 4240 return padto; 4241 } 4242 4243 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4244 struct sk_buff *skb) 4245 { 4246 unsigned int padto = 0; 4247 4248 switch (tp->mac_version) { 4249 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 4250 padto = rtl8125_quirk_udp_padto(tp, skb); 4251 break; 4252 default: 4253 break; 4254 } 4255 4256 switch (tp->mac_version) { 4257 case RTL_GIGA_MAC_VER_34: 4258 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 4259 padto = max_t(unsigned int, padto, ETH_ZLEN); 4260 break; 4261 default: 4262 break; 4263 } 4264 4265 return padto; 4266 } 4267 4268 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4269 { 4270 u32 mss = skb_shinfo(skb)->gso_size; 4271 4272 if (mss) { 4273 opts[0] |= TD_LSO; 4274 opts[0] |= mss << TD0_MSS_SHIFT; 4275 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4276 const struct iphdr *ip = ip_hdr(skb); 4277 4278 if (ip->protocol == IPPROTO_TCP) 4279 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4280 else if (ip->protocol == IPPROTO_UDP) 4281 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4282 else 4283 WARN_ON_ONCE(1); 4284 } 4285 } 4286 4287 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4288 struct sk_buff *skb, u32 *opts) 4289 { 4290 struct skb_shared_info *shinfo = skb_shinfo(skb); 4291 u32 mss = shinfo->gso_size; 4292 4293 if (mss) { 4294 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4295 opts[0] |= TD1_GTSENV4; 4296 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4297 if (skb_cow_head(skb, 0)) 4298 return false; 4299 4300 tcp_v6_gso_csum_prep(skb); 4301 opts[0] |= TD1_GTSENV6; 4302 } else { 4303 WARN_ON_ONCE(1); 4304 } 4305 4306 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4307 opts[1] |= mss << TD1_MSS_SHIFT; 4308 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4309 u8 ip_protocol; 4310 4311 switch (vlan_get_protocol(skb)) { 4312 case htons(ETH_P_IP): 4313 opts[1] |= TD1_IPv4_CS; 4314 ip_protocol = ip_hdr(skb)->protocol; 4315 break; 4316 4317 case htons(ETH_P_IPV6): 4318 opts[1] |= TD1_IPv6_CS; 4319 ip_protocol = ipv6_hdr(skb)->nexthdr; 4320 break; 4321 4322 default: 4323 ip_protocol = IPPROTO_RAW; 4324 break; 4325 } 4326 4327 if (ip_protocol == IPPROTO_TCP) 4328 opts[1] |= TD1_TCP_CS; 4329 else if (ip_protocol == IPPROTO_UDP) 4330 opts[1] |= TD1_UDP_CS; 4331 else 4332 WARN_ON_ONCE(1); 4333 4334 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4335 } else { 4336 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4337 4338 /* skb_padto would free the skb on error */ 4339 return !__skb_put_padto(skb, padto, false); 4340 } 4341 4342 return true; 4343 } 4344 4345 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4346 { 4347 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4348 } 4349 4350 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4351 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4352 { 4353 switch (tp->mac_version) { 4354 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4355 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4356 return false; 4357 default: 4358 return true; 4359 } 4360 } 4361 4362 static void rtl8169_doorbell(struct rtl8169_private *tp) 4363 { 4364 if (rtl_is_8125(tp)) 4365 RTL_W16(tp, TxPoll_8125, BIT(0)); 4366 else 4367 RTL_W8(tp, TxPoll, NPQ); 4368 } 4369 4370 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4371 struct net_device *dev) 4372 { 4373 struct rtl8169_private *tp = netdev_priv(dev); 4374 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4375 struct TxDesc *txd_first, *txd_last; 4376 bool stop_queue, door_bell; 4377 unsigned int frags; 4378 u32 opts[2]; 4379 4380 if (unlikely(!rtl_tx_slots_avail(tp))) { 4381 if (net_ratelimit()) 4382 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4383 netif_stop_queue(dev); 4384 return NETDEV_TX_BUSY; 4385 } 4386 4387 opts[1] = rtl8169_tx_vlan_tag(skb); 4388 opts[0] = 0; 4389 4390 if (!rtl_chip_supports_csum_v2(tp)) 4391 rtl8169_tso_csum_v1(skb, opts); 4392 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4393 goto err_dma_0; 4394 4395 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4396 entry, false))) 4397 goto err_dma_0; 4398 4399 txd_first = tp->TxDescArray + entry; 4400 4401 frags = skb_shinfo(skb)->nr_frags; 4402 if (frags) { 4403 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4404 goto err_dma_1; 4405 entry = (entry + frags) % NUM_TX_DESC; 4406 } 4407 4408 txd_last = tp->TxDescArray + entry; 4409 txd_last->opts1 |= cpu_to_le32(LastFrag); 4410 tp->tx_skb[entry].skb = skb; 4411 4412 skb_tx_timestamp(skb); 4413 4414 /* Force memory writes to complete before releasing descriptor */ 4415 dma_wmb(); 4416 4417 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4418 4419 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4420 4421 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4422 smp_wmb(); 4423 4424 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4425 4426 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4427 R8169_TX_STOP_THRS, 4428 R8169_TX_START_THRS); 4429 if (door_bell || stop_queue) 4430 rtl8169_doorbell(tp); 4431 4432 return NETDEV_TX_OK; 4433 4434 err_dma_1: 4435 rtl8169_unmap_tx_skb(tp, entry); 4436 err_dma_0: 4437 dev_kfree_skb_any(skb); 4438 dev->stats.tx_dropped++; 4439 return NETDEV_TX_OK; 4440 } 4441 4442 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4443 { 4444 struct skb_shared_info *info = skb_shinfo(skb); 4445 unsigned int nr_frags = info->nr_frags; 4446 4447 if (!nr_frags) 4448 return UINT_MAX; 4449 4450 return skb_frag_size(info->frags + nr_frags - 1); 4451 } 4452 4453 /* Workaround for hw issues with TSO on RTL8168evl */ 4454 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4455 netdev_features_t features) 4456 { 4457 /* IPv4 header has options field */ 4458 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4459 ip_hdrlen(skb) > sizeof(struct iphdr)) 4460 features &= ~NETIF_F_ALL_TSO; 4461 4462 /* IPv4 TCP header has options field */ 4463 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4464 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4465 features &= ~NETIF_F_ALL_TSO; 4466 4467 else if (rtl_last_frag_len(skb) <= 6) 4468 features &= ~NETIF_F_ALL_TSO; 4469 4470 return features; 4471 } 4472 4473 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4474 struct net_device *dev, 4475 netdev_features_t features) 4476 { 4477 struct rtl8169_private *tp = netdev_priv(dev); 4478 4479 if (skb_is_gso(skb)) { 4480 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4481 features = rtl8168evl_fix_tso(skb, features); 4482 4483 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4484 rtl_chip_supports_csum_v2(tp)) 4485 features &= ~NETIF_F_ALL_TSO; 4486 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4487 /* work around hw bug on some chip versions */ 4488 if (skb->len < ETH_ZLEN) 4489 features &= ~NETIF_F_CSUM_MASK; 4490 4491 if (rtl_quirk_packet_padto(tp, skb)) 4492 features &= ~NETIF_F_CSUM_MASK; 4493 4494 if (skb_transport_offset(skb) > TCPHO_MAX && 4495 rtl_chip_supports_csum_v2(tp)) 4496 features &= ~NETIF_F_CSUM_MASK; 4497 } 4498 4499 return vlan_features_check(skb, features); 4500 } 4501 4502 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4503 { 4504 struct rtl8169_private *tp = netdev_priv(dev); 4505 struct pci_dev *pdev = tp->pci_dev; 4506 int pci_status_errs; 4507 u16 pci_cmd; 4508 4509 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4510 4511 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4512 4513 if (net_ratelimit()) 4514 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4515 pci_cmd, pci_status_errs); 4516 4517 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4518 } 4519 4520 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4521 int budget) 4522 { 4523 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4524 struct sk_buff *skb; 4525 4526 dirty_tx = tp->dirty_tx; 4527 4528 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4529 unsigned int entry = dirty_tx % NUM_TX_DESC; 4530 u32 status; 4531 4532 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4533 if (status & DescOwn) 4534 break; 4535 4536 skb = tp->tx_skb[entry].skb; 4537 rtl8169_unmap_tx_skb(tp, entry); 4538 4539 if (skb) { 4540 pkts_compl++; 4541 bytes_compl += skb->len; 4542 napi_consume_skb(skb, budget); 4543 } 4544 dirty_tx++; 4545 } 4546 4547 if (tp->dirty_tx != dirty_tx) { 4548 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4549 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4550 4551 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4552 rtl_tx_slots_avail(tp), 4553 R8169_TX_START_THRS); 4554 /* 4555 * 8168 hack: TxPoll requests are lost when the Tx packets are 4556 * too close. Let's kick an extra TxPoll request when a burst 4557 * of start_xmit activity is detected (if it is not detected, 4558 * it is slow enough). -- FR 4559 * If skb is NULL then we come here again once a tx irq is 4560 * triggered after the last fragment is marked transmitted. 4561 */ 4562 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4563 rtl8169_doorbell(tp); 4564 } 4565 } 4566 4567 static inline int rtl8169_fragmented_frame(u32 status) 4568 { 4569 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4570 } 4571 4572 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4573 { 4574 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4575 4576 if (status == RxProtoTCP || status == RxProtoUDP) 4577 skb->ip_summed = CHECKSUM_UNNECESSARY; 4578 else 4579 skb_checksum_none_assert(skb); 4580 } 4581 4582 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4583 { 4584 struct device *d = tp_to_dev(tp); 4585 int count; 4586 4587 for (count = 0; count < budget; count++, tp->cur_rx++) { 4588 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4589 struct RxDesc *desc = tp->RxDescArray + entry; 4590 struct sk_buff *skb; 4591 const void *rx_buf; 4592 dma_addr_t addr; 4593 u32 status; 4594 4595 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4596 if (status & DescOwn) 4597 break; 4598 4599 /* This barrier is needed to keep us from reading 4600 * any other fields out of the Rx descriptor until 4601 * we know the status of DescOwn 4602 */ 4603 dma_rmb(); 4604 4605 if (unlikely(status & RxRES)) { 4606 if (net_ratelimit()) 4607 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4608 status); 4609 dev->stats.rx_errors++; 4610 if (status & (RxRWT | RxRUNT)) 4611 dev->stats.rx_length_errors++; 4612 if (status & RxCRC) 4613 dev->stats.rx_crc_errors++; 4614 4615 if (!(dev->features & NETIF_F_RXALL)) 4616 goto release_descriptor; 4617 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4618 goto release_descriptor; 4619 } 4620 4621 pkt_size = status & GENMASK(13, 0); 4622 if (likely(!(dev->features & NETIF_F_RXFCS))) 4623 pkt_size -= ETH_FCS_LEN; 4624 4625 /* The driver does not support incoming fragmented frames. 4626 * They are seen as a symptom of over-mtu sized frames. 4627 */ 4628 if (unlikely(rtl8169_fragmented_frame(status))) { 4629 dev->stats.rx_dropped++; 4630 dev->stats.rx_length_errors++; 4631 goto release_descriptor; 4632 } 4633 4634 skb = napi_alloc_skb(&tp->napi, pkt_size); 4635 if (unlikely(!skb)) { 4636 dev->stats.rx_dropped++; 4637 goto release_descriptor; 4638 } 4639 4640 addr = le64_to_cpu(desc->addr); 4641 rx_buf = page_address(tp->Rx_databuff[entry]); 4642 4643 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4644 prefetch(rx_buf); 4645 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4646 skb->tail += pkt_size; 4647 skb->len = pkt_size; 4648 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4649 4650 rtl8169_rx_csum(skb, status); 4651 skb->protocol = eth_type_trans(skb, dev); 4652 4653 rtl8169_rx_vlan_tag(desc, skb); 4654 4655 if (skb->pkt_type == PACKET_MULTICAST) 4656 dev->stats.multicast++; 4657 4658 napi_gro_receive(&tp->napi, skb); 4659 4660 dev_sw_netstats_rx_add(dev, pkt_size); 4661 release_descriptor: 4662 rtl8169_mark_to_asic(desc); 4663 } 4664 4665 return count; 4666 } 4667 4668 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4669 { 4670 struct rtl8169_private *tp = dev_instance; 4671 u32 status = rtl_get_events(tp); 4672 4673 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4674 return IRQ_NONE; 4675 4676 /* At least RTL8168fp may unexpectedly set the SYSErr bit */ 4677 if (unlikely(status & SYSErr && 4678 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { 4679 rtl8169_pcierr_interrupt(tp->dev); 4680 goto out; 4681 } 4682 4683 if (status & LinkChg) 4684 phy_mac_interrupt(tp->phydev); 4685 4686 rtl_irq_disable(tp); 4687 napi_schedule(&tp->napi); 4688 out: 4689 rtl_ack_events(tp, status); 4690 4691 return IRQ_HANDLED; 4692 } 4693 4694 static void rtl_task(struct work_struct *work) 4695 { 4696 struct rtl8169_private *tp = 4697 container_of(work, struct rtl8169_private, wk.work); 4698 int ret; 4699 4700 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4701 /* if chip isn't accessible, reset bus to revive it */ 4702 if (RTL_R32(tp, TxConfig) == ~0) { 4703 ret = pci_reset_bus(tp->pci_dev); 4704 if (ret < 0) { 4705 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4706 netif_device_detach(tp->dev); 4707 return; 4708 } 4709 } 4710 4711 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4712 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4713 PCIE_LINK_STATE_L0S); 4714 if (!ret) 4715 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4716 goto reset; 4717 } 4718 4719 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4720 reset: 4721 rtl_reset_work(tp); 4722 netif_wake_queue(tp->dev); 4723 } 4724 } 4725 4726 static int rtl8169_poll(struct napi_struct *napi, int budget) 4727 { 4728 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4729 struct net_device *dev = tp->dev; 4730 int work_done; 4731 4732 rtl_tx(dev, tp, budget); 4733 4734 work_done = rtl_rx(dev, tp, budget); 4735 4736 if (work_done < budget && napi_complete_done(napi, work_done)) 4737 rtl_irq_enable(tp); 4738 4739 return work_done; 4740 } 4741 4742 static void r8169_phylink_handler(struct net_device *ndev) 4743 { 4744 struct rtl8169_private *tp = netdev_priv(ndev); 4745 struct device *d = tp_to_dev(tp); 4746 4747 if (netif_carrier_ok(ndev)) { 4748 rtl_link_chg_patch(tp); 4749 pm_request_resume(d); 4750 } else { 4751 pm_runtime_idle(d); 4752 } 4753 4754 phy_print_status(tp->phydev); 4755 } 4756 4757 static int r8169_phy_connect(struct rtl8169_private *tp) 4758 { 4759 struct phy_device *phydev = tp->phydev; 4760 phy_interface_t phy_mode; 4761 int ret; 4762 4763 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4764 PHY_INTERFACE_MODE_MII; 4765 4766 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4767 phy_mode); 4768 if (ret) 4769 return ret; 4770 4771 if (!tp->supports_gmii) 4772 phy_set_max_speed(phydev, SPEED_100); 4773 4774 phy_attached_info(phydev); 4775 4776 return 0; 4777 } 4778 4779 static void rtl8169_down(struct rtl8169_private *tp) 4780 { 4781 disable_work_sync(&tp->wk.work); 4782 /* Clear all task flags */ 4783 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4784 4785 phy_stop(tp->phydev); 4786 4787 rtl8169_update_counters(tp); 4788 4789 pci_clear_master(tp->pci_dev); 4790 rtl_pci_commit(tp); 4791 4792 rtl8169_cleanup(tp); 4793 rtl_disable_exit_l1(tp); 4794 rtl_prepare_power_down(tp); 4795 4796 if (tp->dash_type != RTL_DASH_NONE) 4797 rtl8168_driver_stop(tp); 4798 } 4799 4800 static void rtl8169_up(struct rtl8169_private *tp) 4801 { 4802 if (tp->dash_type != RTL_DASH_NONE) 4803 rtl8168_driver_start(tp); 4804 4805 pci_set_master(tp->pci_dev); 4806 phy_init_hw(tp->phydev); 4807 phy_resume(tp->phydev); 4808 rtl8169_init_phy(tp); 4809 napi_enable(&tp->napi); 4810 enable_work(&tp->wk.work); 4811 rtl_reset_work(tp); 4812 4813 phy_start(tp->phydev); 4814 } 4815 4816 static int rtl8169_close(struct net_device *dev) 4817 { 4818 struct rtl8169_private *tp = netdev_priv(dev); 4819 struct pci_dev *pdev = tp->pci_dev; 4820 4821 pm_runtime_get_sync(&pdev->dev); 4822 4823 netif_stop_queue(dev); 4824 rtl8169_down(tp); 4825 rtl8169_rx_clear(tp); 4826 4827 free_irq(tp->irq, tp); 4828 4829 phy_disconnect(tp->phydev); 4830 4831 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4832 tp->RxPhyAddr); 4833 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4834 tp->TxPhyAddr); 4835 tp->TxDescArray = NULL; 4836 tp->RxDescArray = NULL; 4837 4838 pm_runtime_put_sync(&pdev->dev); 4839 4840 return 0; 4841 } 4842 4843 #ifdef CONFIG_NET_POLL_CONTROLLER 4844 static void rtl8169_netpoll(struct net_device *dev) 4845 { 4846 struct rtl8169_private *tp = netdev_priv(dev); 4847 4848 rtl8169_interrupt(tp->irq, tp); 4849 } 4850 #endif 4851 4852 static int rtl_open(struct net_device *dev) 4853 { 4854 struct rtl8169_private *tp = netdev_priv(dev); 4855 struct pci_dev *pdev = tp->pci_dev; 4856 unsigned long irqflags; 4857 int retval = -ENOMEM; 4858 4859 pm_runtime_get_sync(&pdev->dev); 4860 4861 /* 4862 * Rx and Tx descriptors needs 256 bytes alignment. 4863 * dma_alloc_coherent provides more. 4864 */ 4865 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4866 &tp->TxPhyAddr, GFP_KERNEL); 4867 if (!tp->TxDescArray) 4868 goto out; 4869 4870 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4871 &tp->RxPhyAddr, GFP_KERNEL); 4872 if (!tp->RxDescArray) 4873 goto err_free_tx_0; 4874 4875 retval = rtl8169_init_ring(tp); 4876 if (retval < 0) 4877 goto err_free_rx_1; 4878 4879 rtl_request_firmware(tp); 4880 4881 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4882 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4883 if (retval < 0) 4884 goto err_release_fw_2; 4885 4886 retval = r8169_phy_connect(tp); 4887 if (retval) 4888 goto err_free_irq; 4889 4890 rtl8169_up(tp); 4891 rtl8169_init_counter_offsets(tp); 4892 netif_start_queue(dev); 4893 out: 4894 pm_runtime_put_sync(&pdev->dev); 4895 4896 return retval; 4897 4898 err_free_irq: 4899 free_irq(tp->irq, tp); 4900 err_release_fw_2: 4901 rtl_release_firmware(tp); 4902 rtl8169_rx_clear(tp); 4903 err_free_rx_1: 4904 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4905 tp->RxPhyAddr); 4906 tp->RxDescArray = NULL; 4907 err_free_tx_0: 4908 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4909 tp->TxPhyAddr); 4910 tp->TxDescArray = NULL; 4911 goto out; 4912 } 4913 4914 static void 4915 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4916 { 4917 struct rtl8169_private *tp = netdev_priv(dev); 4918 struct pci_dev *pdev = tp->pci_dev; 4919 struct rtl8169_counters *counters = tp->counters; 4920 4921 pm_runtime_get_noresume(&pdev->dev); 4922 4923 netdev_stats_to_stats64(stats, &dev->stats); 4924 dev_fetch_sw_netstats(stats, dev->tstats); 4925 4926 /* 4927 * Fetch additional counter values missing in stats collected by driver 4928 * from tally counters. 4929 */ 4930 if (pm_runtime_active(&pdev->dev)) 4931 rtl8169_update_counters(tp); 4932 4933 /* 4934 * Subtract values fetched during initalization. 4935 * See rtl8169_init_counter_offsets for a description why we do that. 4936 */ 4937 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4938 le64_to_cpu(tp->tc_offset.tx_errors); 4939 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4940 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4941 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4942 le16_to_cpu(tp->tc_offset.tx_aborted); 4943 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4944 le16_to_cpu(tp->tc_offset.rx_missed); 4945 4946 pm_runtime_put_noidle(&pdev->dev); 4947 } 4948 4949 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4950 { 4951 netif_device_detach(tp->dev); 4952 4953 if (netif_running(tp->dev)) 4954 rtl8169_down(tp); 4955 } 4956 4957 static int rtl8169_runtime_resume(struct device *dev) 4958 { 4959 struct rtl8169_private *tp = dev_get_drvdata(dev); 4960 4961 rtl_rar_set(tp, tp->dev->dev_addr); 4962 __rtl8169_set_wol(tp, tp->saved_wolopts); 4963 4964 if (tp->TxDescArray) 4965 rtl8169_up(tp); 4966 4967 netif_device_attach(tp->dev); 4968 4969 return 0; 4970 } 4971 4972 static int rtl8169_suspend(struct device *device) 4973 { 4974 struct rtl8169_private *tp = dev_get_drvdata(device); 4975 4976 rtnl_lock(); 4977 rtl8169_net_suspend(tp); 4978 if (!device_may_wakeup(tp_to_dev(tp))) 4979 clk_disable_unprepare(tp->clk); 4980 rtnl_unlock(); 4981 4982 return 0; 4983 } 4984 4985 static int rtl8169_resume(struct device *device) 4986 { 4987 struct rtl8169_private *tp = dev_get_drvdata(device); 4988 4989 if (!device_may_wakeup(tp_to_dev(tp))) 4990 clk_prepare_enable(tp->clk); 4991 4992 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4993 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4994 rtl_init_rxcfg(tp); 4995 4996 return rtl8169_runtime_resume(device); 4997 } 4998 4999 static int rtl8169_runtime_suspend(struct device *device) 5000 { 5001 struct rtl8169_private *tp = dev_get_drvdata(device); 5002 5003 if (!tp->TxDescArray) { 5004 netif_device_detach(tp->dev); 5005 return 0; 5006 } 5007 5008 rtnl_lock(); 5009 __rtl8169_set_wol(tp, WAKE_PHY); 5010 rtl8169_net_suspend(tp); 5011 rtnl_unlock(); 5012 5013 return 0; 5014 } 5015 5016 static int rtl8169_runtime_idle(struct device *device) 5017 { 5018 struct rtl8169_private *tp = dev_get_drvdata(device); 5019 5020 if (tp->dash_enabled) 5021 return -EBUSY; 5022 5023 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5024 pm_schedule_suspend(device, 10000); 5025 5026 return -EBUSY; 5027 } 5028 5029 static const struct dev_pm_ops rtl8169_pm_ops = { 5030 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5031 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5032 rtl8169_runtime_idle) 5033 }; 5034 5035 static void rtl_shutdown(struct pci_dev *pdev) 5036 { 5037 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5038 5039 rtnl_lock(); 5040 rtl8169_net_suspend(tp); 5041 rtnl_unlock(); 5042 5043 /* Restore original MAC address */ 5044 rtl_rar_set(tp, tp->dev->perm_addr); 5045 5046 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5047 pci_wake_from_d3(pdev, tp->saved_wolopts); 5048 pci_set_power_state(pdev, PCI_D3hot); 5049 } 5050 } 5051 5052 static void rtl_remove_one(struct pci_dev *pdev) 5053 { 5054 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5055 5056 if (pci_dev_run_wake(pdev)) 5057 pm_runtime_get_noresume(&pdev->dev); 5058 5059 disable_work_sync(&tp->wk.work); 5060 5061 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5062 r8169_remove_leds(tp->leds); 5063 5064 unregister_netdev(tp->dev); 5065 5066 if (tp->dash_type != RTL_DASH_NONE) 5067 rtl8168_driver_stop(tp); 5068 5069 rtl_release_firmware(tp); 5070 5071 /* restore original MAC address */ 5072 rtl_rar_set(tp, tp->dev->perm_addr); 5073 } 5074 5075 static const struct net_device_ops rtl_netdev_ops = { 5076 .ndo_open = rtl_open, 5077 .ndo_stop = rtl8169_close, 5078 .ndo_get_stats64 = rtl8169_get_stats64, 5079 .ndo_start_xmit = rtl8169_start_xmit, 5080 .ndo_features_check = rtl8169_features_check, 5081 .ndo_tx_timeout = rtl8169_tx_timeout, 5082 .ndo_validate_addr = eth_validate_addr, 5083 .ndo_change_mtu = rtl8169_change_mtu, 5084 .ndo_fix_features = rtl8169_fix_features, 5085 .ndo_set_features = rtl8169_set_features, 5086 .ndo_set_mac_address = rtl_set_mac_address, 5087 .ndo_eth_ioctl = phy_do_ioctl_running, 5088 .ndo_set_rx_mode = rtl_set_rx_mode, 5089 #ifdef CONFIG_NET_POLL_CONTROLLER 5090 .ndo_poll_controller = rtl8169_netpoll, 5091 #endif 5092 5093 }; 5094 5095 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5096 { 5097 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5098 5099 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5100 tp->irq_mask |= SYSErr | RxFIFOOver; 5101 } 5102 5103 static int rtl_alloc_irq(struct rtl8169_private *tp) 5104 { 5105 unsigned int flags; 5106 5107 switch (tp->mac_version) { 5108 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5109 rtl_unlock_config_regs(tp); 5110 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5111 rtl_lock_config_regs(tp); 5112 fallthrough; 5113 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5114 flags = PCI_IRQ_INTX; 5115 break; 5116 default: 5117 flags = PCI_IRQ_ALL_TYPES; 5118 break; 5119 } 5120 5121 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5122 } 5123 5124 static void rtl_read_mac_address(struct rtl8169_private *tp, 5125 u8 mac_addr[ETH_ALEN]) 5126 { 5127 /* Get MAC address */ 5128 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5129 u32 value; 5130 5131 value = rtl_eri_read(tp, 0xe0); 5132 put_unaligned_le32(value, mac_addr); 5133 value = rtl_eri_read(tp, 0xe4); 5134 put_unaligned_le16(value, mac_addr + 4); 5135 } else if (rtl_is_8125(tp)) { 5136 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5137 } 5138 } 5139 5140 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5141 { 5142 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5143 } 5144 5145 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5146 { 5147 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5148 } 5149 5150 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5151 { 5152 struct rtl8169_private *tp = mii_bus->priv; 5153 5154 if (phyaddr > 0) 5155 return -ENODEV; 5156 5157 return rtl_readphy(tp, phyreg); 5158 } 5159 5160 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5161 int phyreg, u16 val) 5162 { 5163 struct rtl8169_private *tp = mii_bus->priv; 5164 5165 if (phyaddr > 0) 5166 return -ENODEV; 5167 5168 rtl_writephy(tp, phyreg, val); 5169 5170 return 0; 5171 } 5172 5173 static int r8169_mdio_register(struct rtl8169_private *tp) 5174 { 5175 struct pci_dev *pdev = tp->pci_dev; 5176 struct mii_bus *new_bus; 5177 int ret; 5178 5179 /* On some boards with this chip version the BIOS is buggy and misses 5180 * to reset the PHY page selector. This results in the PHY ID read 5181 * accessing registers on a different page, returning a more or 5182 * less random value. Fix this by resetting the page selector first. 5183 */ 5184 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5185 tp->mac_version == RTL_GIGA_MAC_VER_26) 5186 r8169_mdio_write(tp, 0x1f, 0); 5187 5188 new_bus = devm_mdiobus_alloc(&pdev->dev); 5189 if (!new_bus) 5190 return -ENOMEM; 5191 5192 new_bus->name = "r8169"; 5193 new_bus->priv = tp; 5194 new_bus->parent = &pdev->dev; 5195 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5196 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5197 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5198 5199 new_bus->read = r8169_mdio_read_reg; 5200 new_bus->write = r8169_mdio_write_reg; 5201 5202 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5203 if (ret) 5204 return ret; 5205 5206 tp->phydev = mdiobus_get_phy(new_bus, 0); 5207 if (!tp->phydev) { 5208 return -ENODEV; 5209 } else if (!tp->phydev->drv) { 5210 /* Most chip versions fail with the genphy driver. 5211 * Therefore ensure that the dedicated PHY driver is loaded. 5212 */ 5213 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5214 tp->phydev->phy_id); 5215 return -EUNATCH; 5216 } 5217 5218 tp->phydev->mac_managed_pm = true; 5219 if (rtl_supports_eee(tp)) 5220 phy_support_eee(tp->phydev); 5221 phy_support_asym_pause(tp->phydev); 5222 5223 /* mimic behavior of r8125/r8126 vendor drivers */ 5224 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 5225 phy_set_eee_broken(tp->phydev, 5226 ETHTOOL_LINK_MODE_2500baseT_Full_BIT); 5227 phy_set_eee_broken(tp->phydev, ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 5228 5229 /* PHY will be woken up in rtl_open() */ 5230 phy_suspend(tp->phydev); 5231 5232 return 0; 5233 } 5234 5235 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5236 { 5237 rtl_enable_rxdvgate(tp); 5238 5239 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5240 msleep(1); 5241 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5242 5243 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5244 r8168g_wait_ll_share_fifo_ready(tp); 5245 5246 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5247 r8168g_wait_ll_share_fifo_ready(tp); 5248 } 5249 5250 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5251 { 5252 rtl_enable_rxdvgate(tp); 5253 5254 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5255 msleep(1); 5256 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5257 5258 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5259 r8168g_wait_ll_share_fifo_ready(tp); 5260 5261 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5262 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5263 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5264 r8168g_wait_ll_share_fifo_ready(tp); 5265 } 5266 5267 static void rtl_hw_initialize(struct rtl8169_private *tp) 5268 { 5269 switch (tp->mac_version) { 5270 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5271 rtl8168ep_stop_cmac(tp); 5272 fallthrough; 5273 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5274 rtl_hw_init_8168g(tp); 5275 break; 5276 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71: 5277 rtl_hw_init_8125(tp); 5278 break; 5279 default: 5280 break; 5281 } 5282 } 5283 5284 static int rtl_jumbo_max(struct rtl8169_private *tp) 5285 { 5286 /* Non-GBit versions don't support jumbo frames */ 5287 if (!tp->supports_gmii) 5288 return 0; 5289 5290 switch (tp->mac_version) { 5291 /* RTL8169 */ 5292 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5293 return JUMBO_7K; 5294 /* RTL8168b */ 5295 case RTL_GIGA_MAC_VER_17: 5296 return JUMBO_4K; 5297 /* RTL8168c */ 5298 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5299 return JUMBO_6K; 5300 default: 5301 return JUMBO_9K; 5302 } 5303 } 5304 5305 static void rtl_init_mac_address(struct rtl8169_private *tp) 5306 { 5307 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5308 struct net_device *dev = tp->dev; 5309 int rc; 5310 5311 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5312 if (!rc) 5313 goto done; 5314 5315 rtl_read_mac_address(tp, mac_addr); 5316 if (is_valid_ether_addr(mac_addr)) 5317 goto done; 5318 5319 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5320 if (is_valid_ether_addr(mac_addr)) 5321 goto done; 5322 5323 eth_random_addr(mac_addr); 5324 dev->addr_assign_type = NET_ADDR_RANDOM; 5325 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5326 done: 5327 eth_hw_addr_set(dev, mac_addr); 5328 rtl_rar_set(tp, mac_addr); 5329 } 5330 5331 /* register is set if system vendor successfully tested ASPM 1.2 */ 5332 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5333 { 5334 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5335 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5336 return true; 5337 5338 return false; 5339 } 5340 5341 static int r8169_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 5342 u32 attr, int channel, long *val) 5343 { 5344 struct rtl8169_private *tp = dev_get_drvdata(dev); 5345 int val_raw; 5346 5347 val_raw = phy_read_paged(tp->phydev, 0xbd8, 0x12) & 0x3ff; 5348 if (val_raw >= 512) 5349 val_raw -= 1024; 5350 5351 *val = 1000 * val_raw / 2; 5352 5353 return 0; 5354 } 5355 5356 static const struct hwmon_ops r8169_hwmon_ops = { 5357 .visible = 0444, 5358 .read = r8169_hwmon_read, 5359 }; 5360 5361 static const struct hwmon_channel_info * const r8169_hwmon_info[] = { 5362 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 5363 NULL 5364 }; 5365 5366 static const struct hwmon_chip_info r8169_hwmon_chip_info = { 5367 .ops = &r8169_hwmon_ops, 5368 .info = r8169_hwmon_info, 5369 }; 5370 5371 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5372 { 5373 struct rtl8169_private *tp; 5374 int jumbo_max, region, rc; 5375 enum mac_version chipset; 5376 struct net_device *dev; 5377 u32 txconfig; 5378 u16 xid; 5379 5380 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5381 if (!dev) 5382 return -ENOMEM; 5383 5384 SET_NETDEV_DEV(dev, &pdev->dev); 5385 dev->netdev_ops = &rtl_netdev_ops; 5386 tp = netdev_priv(dev); 5387 tp->dev = dev; 5388 tp->pci_dev = pdev; 5389 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5390 tp->ocp_base = OCP_STD_PHY_BASE; 5391 5392 raw_spin_lock_init(&tp->mac_ocp_lock); 5393 mutex_init(&tp->led_lock); 5394 5395 /* Get the *optional* external "ether_clk" used on some boards */ 5396 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5397 if (IS_ERR(tp->clk)) 5398 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5399 5400 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5401 rc = pcim_enable_device(pdev); 5402 if (rc < 0) 5403 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5404 5405 if (pcim_set_mwi(pdev) < 0) 5406 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5407 5408 /* use first MMIO region */ 5409 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5410 if (region < 0) 5411 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5412 5413 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5414 if (rc < 0) 5415 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5416 5417 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5418 5419 txconfig = RTL_R32(tp, TxConfig); 5420 if (txconfig == ~0U) 5421 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5422 5423 xid = (txconfig >> 20) & 0xfcf; 5424 5425 /* Identify chip attached to board */ 5426 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5427 if (chipset == RTL_GIGA_MAC_NONE) 5428 return dev_err_probe(&pdev->dev, -ENODEV, 5429 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5430 xid); 5431 tp->mac_version = chipset; 5432 5433 /* Disable ASPM L1 as that cause random device stop working 5434 * problems as well as full system hangs for some PCIe devices users. 5435 */ 5436 if (rtl_aspm_is_safe(tp)) 5437 rc = 0; 5438 else 5439 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5440 tp->aspm_manageable = !rc; 5441 5442 tp->dash_type = rtl_get_dash_type(tp); 5443 tp->dash_enabled = rtl_dash_is_enabled(tp); 5444 5445 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5446 5447 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5448 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5449 dev->features |= NETIF_F_HIGHDMA; 5450 5451 rtl_init_rxcfg(tp); 5452 5453 rtl8169_irq_mask_and_ack(tp); 5454 5455 rtl_hw_initialize(tp); 5456 5457 rtl_hw_reset(tp); 5458 5459 rc = rtl_alloc_irq(tp); 5460 if (rc < 0) 5461 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5462 5463 tp->irq = pci_irq_vector(pdev, 0); 5464 5465 INIT_WORK(&tp->wk.work, rtl_task); 5466 disable_work(&tp->wk.work); 5467 5468 rtl_init_mac_address(tp); 5469 5470 dev->ethtool_ops = &rtl8169_ethtool_ops; 5471 5472 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5473 5474 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5475 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5476 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5477 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5478 5479 /* 5480 * Pretend we are using VLANs; This bypasses a nasty bug where 5481 * Interrupts stop flowing on high load on 8110SCd controllers. 5482 */ 5483 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5484 /* Disallow toggling */ 5485 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5486 5487 if (rtl_chip_supports_csum_v2(tp)) 5488 dev->hw_features |= NETIF_F_IPV6_CSUM; 5489 5490 dev->features |= dev->hw_features; 5491 5492 if (rtl_chip_supports_csum_v2(tp)) { 5493 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5494 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5495 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5496 } else { 5497 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5498 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5499 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5500 } 5501 5502 /* There has been a number of reports that using SG/TSO results in 5503 * tx timeouts. However for a lot of people SG/TSO works fine. 5504 * It's not fully clear which chip versions are affected. Vendor 5505 * drivers enable SG/TSO for certain chip versions per default, 5506 * let's mimic this here. On other chip versions users can 5507 * use ethtool to enable SG/TSO, use at own risk! 5508 */ 5509 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5510 tp->mac_version != RTL_GIGA_MAC_VER_61) 5511 dev->features |= dev->hw_features; 5512 5513 dev->hw_features |= NETIF_F_RXALL; 5514 dev->hw_features |= NETIF_F_RXFCS; 5515 5516 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5517 5518 netdev_sw_irq_coalesce_default_on(dev); 5519 5520 /* configure chip for default features */ 5521 rtl8169_set_features(dev, dev->features); 5522 5523 if (!tp->dash_enabled) { 5524 rtl_set_d3_pll_down(tp, true); 5525 } else { 5526 rtl_set_d3_pll_down(tp, false); 5527 dev->ethtool->wol_enabled = 1; 5528 } 5529 5530 jumbo_max = rtl_jumbo_max(tp); 5531 if (jumbo_max) 5532 dev->max_mtu = jumbo_max; 5533 5534 rtl_set_irq_mask(tp); 5535 5536 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5537 5538 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5539 &tp->counters_phys_addr, 5540 GFP_KERNEL); 5541 if (!tp->counters) 5542 return -ENOMEM; 5543 5544 pci_set_drvdata(pdev, tp); 5545 5546 rc = r8169_mdio_register(tp); 5547 if (rc) 5548 return rc; 5549 5550 /* The temperature sensor is available from RTl8125B */ 5551 if (IS_REACHABLE(CONFIG_HWMON) && tp->mac_version >= RTL_GIGA_MAC_VER_63) 5552 /* ignore errors */ 5553 devm_hwmon_device_register_with_info(&pdev->dev, "nic_temp", tp, 5554 &r8169_hwmon_chip_info, 5555 NULL); 5556 rc = register_netdev(dev); 5557 if (rc) 5558 return rc; 5559 5560 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5561 if (rtl_is_8125(tp)) 5562 tp->leds = rtl8125_init_leds(dev); 5563 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5564 tp->leds = rtl8168_init_leds(dev); 5565 } 5566 5567 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5568 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5569 5570 if (jumbo_max) 5571 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5572 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5573 "ok" : "ko"); 5574 5575 if (tp->dash_type != RTL_DASH_NONE) { 5576 netdev_info(dev, "DASH %s\n", 5577 tp->dash_enabled ? "enabled" : "disabled"); 5578 rtl8168_driver_start(tp); 5579 } 5580 5581 if (pci_dev_run_wake(pdev)) 5582 pm_runtime_put_sync(&pdev->dev); 5583 5584 return 0; 5585 } 5586 5587 static struct pci_driver rtl8169_pci_driver = { 5588 .name = KBUILD_MODNAME, 5589 .id_table = rtl8169_pci_tbl, 5590 .probe = rtl_init_one, 5591 .remove = rtl_remove_one, 5592 .shutdown = rtl_shutdown, 5593 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5594 }; 5595 5596 module_pci_driver(rtl8169_pci_driver); 5597