1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/bitfield.h> 31 #include <linux/prefetch.h> 32 #include <linux/ipv6.h> 33 #include <net/ip6_checksum.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define MODULENAME "r8169" 39 40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 57 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 58 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 59 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 60 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 61 62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 64 #define MC_FILTER_LIMIT 32 65 66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 68 69 #define R8169_REGS_SIZE 256 70 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 75 76 #define OCP_STD_PHY_BASE 0xa400 77 78 #define RTL_CFG_NO_GBIT 1 79 80 /* write/read MMIO register */ 81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 87 88 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 92 93 static const struct { 94 const char *name; 95 const char *fw_name; 96 } rtl_chip_infos[] = { 97 /* PCI devices. */ 98 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 99 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 100 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 101 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 102 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 103 /* PCI-E devices. */ 104 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 106 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 107 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 108 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 111 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 112 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 113 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 114 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 115 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 119 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 120 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 121 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 122 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 123 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 124 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 125 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 126 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 127 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 128 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 129 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 130 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 131 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 132 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 133 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 134 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 135 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 136 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 137 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 138 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 139 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 140 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 141 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 142 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 143 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 144 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 145 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 146 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 148 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 149 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 150 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 151 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 152 }; 153 154 static const struct pci_device_id rtl8169_pci_tbl[] = { 155 { PCI_VDEVICE(REALTEK, 0x2502) }, 156 { PCI_VDEVICE(REALTEK, 0x2600) }, 157 { PCI_VDEVICE(REALTEK, 0x8129) }, 158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 159 { PCI_VDEVICE(REALTEK, 0x8161) }, 160 { PCI_VDEVICE(REALTEK, 0x8167) }, 161 { PCI_VDEVICE(REALTEK, 0x8168) }, 162 { PCI_VDEVICE(NCUBE, 0x8168) }, 163 { PCI_VDEVICE(REALTEK, 0x8169) }, 164 { PCI_VENDOR_ID_DLINK, 0x4300, 165 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 166 { PCI_VDEVICE(DLINK, 0x4300) }, 167 { PCI_VDEVICE(DLINK, 0x4302) }, 168 { PCI_VDEVICE(AT, 0xc107) }, 169 { PCI_VDEVICE(USR, 0x0116) }, 170 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 171 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 172 { PCI_VDEVICE(REALTEK, 0x8125) }, 173 { PCI_VDEVICE(REALTEK, 0x3000) }, 174 {} 175 }; 176 177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 178 179 enum rtl_registers { 180 MAC0 = 0, /* Ethernet hardware address. */ 181 MAC4 = 4, 182 MAR0 = 8, /* Multicast filter. */ 183 CounterAddrLow = 0x10, 184 CounterAddrHigh = 0x14, 185 TxDescStartAddrLow = 0x20, 186 TxDescStartAddrHigh = 0x24, 187 TxHDescStartAddrLow = 0x28, 188 TxHDescStartAddrHigh = 0x2c, 189 FLASH = 0x30, 190 ERSR = 0x36, 191 ChipCmd = 0x37, 192 TxPoll = 0x38, 193 IntrMask = 0x3c, 194 IntrStatus = 0x3e, 195 196 TxConfig = 0x40, 197 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 198 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 199 200 RxConfig = 0x44, 201 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 202 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 203 #define RXCFG_FIFO_SHIFT 13 204 /* No threshold before first PCI xfer */ 205 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 206 #define RX_EARLY_OFF (1 << 11) 207 #define RXCFG_DMA_SHIFT 8 208 /* Unlimited maximum PCI burst. */ 209 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 210 211 Cfg9346 = 0x50, 212 Config0 = 0x51, 213 Config1 = 0x52, 214 Config2 = 0x53, 215 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 216 217 Config3 = 0x54, 218 Config4 = 0x55, 219 Config5 = 0x56, 220 PHYAR = 0x60, 221 PHYstatus = 0x6c, 222 RxMaxSize = 0xda, 223 CPlusCmd = 0xe0, 224 IntrMitigate = 0xe2, 225 226 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 227 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 228 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 229 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 230 231 #define RTL_COALESCE_T_MAX 0x0fU 232 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 233 234 RxDescAddrLow = 0xe4, 235 RxDescAddrHigh = 0xe8, 236 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 237 238 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 239 240 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 241 242 #define TxPacketMax (8064 >> 7) 243 #define EarlySize 0x27 244 245 FuncEvent = 0xf0, 246 FuncEventMask = 0xf4, 247 FuncPresetState = 0xf8, 248 IBCR0 = 0xf8, 249 IBCR2 = 0xf9, 250 IBIMR0 = 0xfa, 251 IBISR0 = 0xfb, 252 FuncForceEvent = 0xfc, 253 }; 254 255 enum rtl8168_8101_registers { 256 CSIDR = 0x64, 257 CSIAR = 0x68, 258 #define CSIAR_FLAG 0x80000000 259 #define CSIAR_WRITE_CMD 0x80000000 260 #define CSIAR_BYTE_ENABLE 0x0000f000 261 #define CSIAR_ADDR_MASK 0x00000fff 262 PMCH = 0x6f, 263 EPHYAR = 0x80, 264 #define EPHYAR_FLAG 0x80000000 265 #define EPHYAR_WRITE_CMD 0x80000000 266 #define EPHYAR_REG_MASK 0x1f 267 #define EPHYAR_REG_SHIFT 16 268 #define EPHYAR_DATA_MASK 0xffff 269 DLLPR = 0xd0, 270 #define PFM_EN (1 << 6) 271 #define TX_10M_PS_EN (1 << 7) 272 DBG_REG = 0xd1, 273 #define FIX_NAK_1 (1 << 4) 274 #define FIX_NAK_2 (1 << 3) 275 TWSI = 0xd2, 276 MCU = 0xd3, 277 #define NOW_IS_OOB (1 << 7) 278 #define TX_EMPTY (1 << 5) 279 #define RX_EMPTY (1 << 4) 280 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 281 #define EN_NDP (1 << 3) 282 #define EN_OOB_RESET (1 << 2) 283 #define LINK_LIST_RDY (1 << 1) 284 EFUSEAR = 0xdc, 285 #define EFUSEAR_FLAG 0x80000000 286 #define EFUSEAR_WRITE_CMD 0x80000000 287 #define EFUSEAR_READ_CMD 0x00000000 288 #define EFUSEAR_REG_MASK 0x03ff 289 #define EFUSEAR_REG_SHIFT 8 290 #define EFUSEAR_DATA_MASK 0xff 291 MISC_1 = 0xf2, 292 #define PFM_D3COLD_EN (1 << 6) 293 }; 294 295 enum rtl8168_registers { 296 LED_FREQ = 0x1a, 297 EEE_LED = 0x1b, 298 ERIDR = 0x70, 299 ERIAR = 0x74, 300 #define ERIAR_FLAG 0x80000000 301 #define ERIAR_WRITE_CMD 0x80000000 302 #define ERIAR_READ_CMD 0x00000000 303 #define ERIAR_ADDR_BYTE_ALIGN 4 304 #define ERIAR_TYPE_SHIFT 16 305 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 306 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_MASK_SHIFT 12 310 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 311 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 315 EPHY_RXER_NUM = 0x7c, 316 OCPDR = 0xb0, /* OCP GPHY access */ 317 #define OCPDR_WRITE_CMD 0x80000000 318 #define OCPDR_READ_CMD 0x00000000 319 #define OCPDR_REG_MASK 0x7f 320 #define OCPDR_GPHY_REG_SHIFT 16 321 #define OCPDR_DATA_MASK 0xffff 322 OCPAR = 0xb4, 323 #define OCPAR_FLAG 0x80000000 324 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 325 #define OCPAR_GPHY_READ_CMD 0x0000f060 326 GPHY_OCP = 0xb8, 327 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 328 MISC = 0xf0, /* 8168e only. */ 329 #define TXPLA_RST (1 << 29) 330 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 331 #define PWM_EN (1 << 22) 332 #define RXDV_GATED_EN (1 << 19) 333 #define EARLY_TALLY_EN (1 << 16) 334 }; 335 336 enum rtl8125_registers { 337 IntrMask_8125 = 0x38, 338 IntrStatus_8125 = 0x3c, 339 TxPoll_8125 = 0x90, 340 MAC0_BKP = 0x19e0, 341 }; 342 343 #define RX_VLAN_INNER_8125 BIT(22) 344 #define RX_VLAN_OUTER_8125 BIT(23) 345 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 346 347 #define RX_FETCH_DFLT_8125 (8 << 27) 348 349 enum rtl_register_content { 350 /* InterruptStatusBits */ 351 SYSErr = 0x8000, 352 PCSTimeout = 0x4000, 353 SWInt = 0x0100, 354 TxDescUnavail = 0x0080, 355 RxFIFOOver = 0x0040, 356 LinkChg = 0x0020, 357 RxOverflow = 0x0010, 358 TxErr = 0x0008, 359 TxOK = 0x0004, 360 RxErr = 0x0002, 361 RxOK = 0x0001, 362 363 /* RxStatusDesc */ 364 RxRWT = (1 << 22), 365 RxRES = (1 << 21), 366 RxRUNT = (1 << 20), 367 RxCRC = (1 << 19), 368 369 /* ChipCmdBits */ 370 StopReq = 0x80, 371 CmdReset = 0x10, 372 CmdRxEnb = 0x08, 373 CmdTxEnb = 0x04, 374 RxBufEmpty = 0x01, 375 376 /* TXPoll register p.5 */ 377 HPQ = 0x80, /* Poll cmd on the high prio queue */ 378 NPQ = 0x40, /* Poll cmd on the low prio queue */ 379 FSWInt = 0x01, /* Forced software interrupt */ 380 381 /* Cfg9346Bits */ 382 Cfg9346_Lock = 0x00, 383 Cfg9346_Unlock = 0xc0, 384 385 /* rx_mode_bits */ 386 AcceptErr = 0x20, 387 AcceptRunt = 0x10, 388 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 389 AcceptBroadcast = 0x08, 390 AcceptMulticast = 0x04, 391 AcceptMyPhys = 0x02, 392 AcceptAllPhys = 0x01, 393 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 394 #define RX_CONFIG_ACCEPT_MASK 0x3f 395 396 /* TxConfigBits */ 397 TxInterFrameGapShift = 24, 398 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 399 400 /* Config1 register p.24 */ 401 LEDS1 = (1 << 7), 402 LEDS0 = (1 << 6), 403 Speed_down = (1 << 4), 404 MEMMAP = (1 << 3), 405 IOMAP = (1 << 2), 406 VPD = (1 << 1), 407 PMEnable = (1 << 0), /* Power Management Enable */ 408 409 /* Config2 register p. 25 */ 410 ClkReqEn = (1 << 7), /* Clock Request Enable */ 411 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 412 PCI_Clock_66MHz = 0x01, 413 PCI_Clock_33MHz = 0x00, 414 415 /* Config3 register p.25 */ 416 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 417 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 418 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 419 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 420 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 421 422 /* Config4 register */ 423 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 424 425 /* Config5 register p.27 */ 426 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 427 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 428 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 429 Spi_en = (1 << 3), 430 LanWake = (1 << 1), /* LanWake enable/disable */ 431 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 432 ASPM_en = (1 << 0), /* ASPM enable */ 433 434 /* CPlusCmd p.31 */ 435 EnableBist = (1 << 15), // 8168 8101 436 Mac_dbgo_oe = (1 << 14), // 8168 8101 437 EnAnaPLL = (1 << 14), // 8169 438 Normal_mode = (1 << 13), // unused 439 Force_half_dup = (1 << 12), // 8168 8101 440 Force_rxflow_en = (1 << 11), // 8168 8101 441 Force_txflow_en = (1 << 10), // 8168 8101 442 Cxpl_dbg_sel = (1 << 9), // 8168 8101 443 ASF = (1 << 8), // 8168 8101 444 PktCntrDisable = (1 << 7), // 8168 8101 445 Mac_dbgo_sel = 0x001c, // 8168 446 RxVlan = (1 << 6), 447 RxChkSum = (1 << 5), 448 PCIDAC = (1 << 4), 449 PCIMulRW = (1 << 3), 450 #define INTT_MASK GENMASK(1, 0) 451 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 452 453 /* rtl8169_PHYstatus */ 454 TBI_Enable = 0x80, 455 TxFlowCtrl = 0x40, 456 RxFlowCtrl = 0x20, 457 _1000bpsF = 0x10, 458 _100bps = 0x08, 459 _10bps = 0x04, 460 LinkStatus = 0x02, 461 FullDup = 0x01, 462 463 /* ResetCounterCommand */ 464 CounterReset = 0x1, 465 466 /* DumpCounterCommand */ 467 CounterDump = 0x8, 468 469 /* magic enable v2 */ 470 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 471 }; 472 473 enum rtl_desc_bit { 474 /* First doubleword. */ 475 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 476 RingEnd = (1 << 30), /* End of descriptor ring */ 477 FirstFrag = (1 << 29), /* First segment of a packet */ 478 LastFrag = (1 << 28), /* Final segment of a packet */ 479 }; 480 481 /* Generic case. */ 482 enum rtl_tx_desc_bit { 483 /* First doubleword. */ 484 TD_LSO = (1 << 27), /* Large Send Offload */ 485 #define TD_MSS_MAX 0x07ffu /* MSS value */ 486 487 /* Second doubleword. */ 488 TxVlanTag = (1 << 17), /* Add VLAN tag */ 489 }; 490 491 /* 8169, 8168b and 810x except 8102e. */ 492 enum rtl_tx_desc_bit_0 { 493 /* First doubleword. */ 494 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 495 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 496 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 497 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 498 }; 499 500 /* 8102e, 8168c and beyond. */ 501 enum rtl_tx_desc_bit_1 { 502 /* First doubleword. */ 503 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 504 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 505 #define GTTCPHO_SHIFT 18 506 #define GTTCPHO_MAX 0x7f 507 508 /* Second doubleword. */ 509 #define TCPHO_SHIFT 18 510 #define TCPHO_MAX 0x3ff 511 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 512 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 513 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 514 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 515 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 516 }; 517 518 enum rtl_rx_desc_bit { 519 /* Rx private */ 520 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 521 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 522 523 #define RxProtoUDP (PID1) 524 #define RxProtoTCP (PID0) 525 #define RxProtoIP (PID1 | PID0) 526 #define RxProtoMask RxProtoIP 527 528 IPFail = (1 << 16), /* IP checksum failed */ 529 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 530 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 531 RxVlanTag = (1 << 16), /* VLAN tag available */ 532 }; 533 534 #define RsvdMask 0x3fffc000 535 536 #define RTL_GSO_MAX_SIZE_V1 32000 537 #define RTL_GSO_MAX_SEGS_V1 24 538 #define RTL_GSO_MAX_SIZE_V2 64000 539 #define RTL_GSO_MAX_SEGS_V2 64 540 541 struct TxDesc { 542 __le32 opts1; 543 __le32 opts2; 544 __le64 addr; 545 }; 546 547 struct RxDesc { 548 __le32 opts1; 549 __le32 opts2; 550 __le64 addr; 551 }; 552 553 struct ring_info { 554 struct sk_buff *skb; 555 u32 len; 556 }; 557 558 struct rtl8169_counters { 559 __le64 tx_packets; 560 __le64 rx_packets; 561 __le64 tx_errors; 562 __le32 rx_errors; 563 __le16 rx_missed; 564 __le16 align_errors; 565 __le32 tx_one_collision; 566 __le32 tx_multi_collision; 567 __le64 rx_unicast; 568 __le64 rx_broadcast; 569 __le32 rx_multicast; 570 __le16 tx_aborted; 571 __le16 tx_underun; 572 }; 573 574 struct rtl8169_tc_offsets { 575 bool inited; 576 __le64 tx_errors; 577 __le32 tx_multi_collision; 578 __le16 tx_aborted; 579 __le16 rx_missed; 580 }; 581 582 enum rtl_flag { 583 RTL_FLAG_TASK_ENABLED = 0, 584 RTL_FLAG_TASK_RESET_PENDING, 585 RTL_FLAG_MAX 586 }; 587 588 struct rtl8169_stats { 589 u64 packets; 590 u64 bytes; 591 struct u64_stats_sync syncp; 592 }; 593 594 struct rtl8169_private { 595 void __iomem *mmio_addr; /* memory map physical address */ 596 struct pci_dev *pci_dev; 597 struct net_device *dev; 598 struct phy_device *phydev; 599 struct napi_struct napi; 600 enum mac_version mac_version; 601 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 602 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 603 u32 dirty_tx; 604 struct rtl8169_stats rx_stats; 605 struct rtl8169_stats tx_stats; 606 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 607 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 608 dma_addr_t TxPhyAddr; 609 dma_addr_t RxPhyAddr; 610 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 611 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 612 u16 cp_cmd; 613 u32 irq_mask; 614 struct clk *clk; 615 616 struct { 617 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 618 struct mutex mutex; 619 struct work_struct work; 620 } wk; 621 622 unsigned irq_enabled:1; 623 unsigned supports_gmii:1; 624 unsigned aspm_manageable:1; 625 dma_addr_t counters_phys_addr; 626 struct rtl8169_counters *counters; 627 struct rtl8169_tc_offsets tc_offset; 628 u32 saved_wolopts; 629 int eee_adv; 630 631 const char *fw_name; 632 struct rtl_fw *rtl_fw; 633 634 u32 ocp_base; 635 }; 636 637 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 638 639 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 640 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 641 MODULE_SOFTDEP("pre: realtek"); 642 MODULE_LICENSE("GPL"); 643 MODULE_FIRMWARE(FIRMWARE_8168D_1); 644 MODULE_FIRMWARE(FIRMWARE_8168D_2); 645 MODULE_FIRMWARE(FIRMWARE_8168E_1); 646 MODULE_FIRMWARE(FIRMWARE_8168E_2); 647 MODULE_FIRMWARE(FIRMWARE_8168E_3); 648 MODULE_FIRMWARE(FIRMWARE_8105E_1); 649 MODULE_FIRMWARE(FIRMWARE_8168F_1); 650 MODULE_FIRMWARE(FIRMWARE_8168F_2); 651 MODULE_FIRMWARE(FIRMWARE_8402_1); 652 MODULE_FIRMWARE(FIRMWARE_8411_1); 653 MODULE_FIRMWARE(FIRMWARE_8411_2); 654 MODULE_FIRMWARE(FIRMWARE_8106E_1); 655 MODULE_FIRMWARE(FIRMWARE_8106E_2); 656 MODULE_FIRMWARE(FIRMWARE_8168G_2); 657 MODULE_FIRMWARE(FIRMWARE_8168G_3); 658 MODULE_FIRMWARE(FIRMWARE_8168H_1); 659 MODULE_FIRMWARE(FIRMWARE_8168H_2); 660 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 661 MODULE_FIRMWARE(FIRMWARE_8107E_1); 662 MODULE_FIRMWARE(FIRMWARE_8107E_2); 663 MODULE_FIRMWARE(FIRMWARE_8125A_3); 664 665 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 666 { 667 return &tp->pci_dev->dev; 668 } 669 670 static void rtl_lock_work(struct rtl8169_private *tp) 671 { 672 mutex_lock(&tp->wk.mutex); 673 } 674 675 static void rtl_unlock_work(struct rtl8169_private *tp) 676 { 677 mutex_unlock(&tp->wk.mutex); 678 } 679 680 static void rtl_lock_config_regs(struct rtl8169_private *tp) 681 { 682 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 683 } 684 685 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 686 { 687 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 688 } 689 690 static void rtl_pci_commit(struct rtl8169_private *tp) 691 { 692 /* Read an arbitrary register to commit a preceding PCI write */ 693 RTL_R8(tp, ChipCmd); 694 } 695 696 static bool rtl_is_8125(struct rtl8169_private *tp) 697 { 698 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 699 } 700 701 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 702 { 703 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 704 tp->mac_version != RTL_GIGA_MAC_VER_39 && 705 tp->mac_version <= RTL_GIGA_MAC_VER_52; 706 } 707 708 static bool rtl_supports_eee(struct rtl8169_private *tp) 709 { 710 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 711 tp->mac_version != RTL_GIGA_MAC_VER_37 && 712 tp->mac_version != RTL_GIGA_MAC_VER_39; 713 } 714 715 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 716 { 717 int i; 718 719 for (i = 0; i < ETH_ALEN; i++) 720 mac[i] = RTL_R8(tp, reg + i); 721 } 722 723 struct rtl_cond { 724 bool (*check)(struct rtl8169_private *); 725 const char *msg; 726 }; 727 728 static void rtl_udelay(unsigned int d) 729 { 730 udelay(d); 731 } 732 733 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 734 void (*delay)(unsigned int), unsigned int d, int n, 735 bool high) 736 { 737 int i; 738 739 for (i = 0; i < n; i++) { 740 if (c->check(tp) == high) 741 return true; 742 delay(d); 743 } 744 745 if (net_ratelimit()) 746 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %d).\n", 747 c->msg, !high, n, d); 748 return false; 749 } 750 751 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 752 const struct rtl_cond *c, 753 unsigned int d, int n) 754 { 755 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 756 } 757 758 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 759 const struct rtl_cond *c, 760 unsigned int d, int n) 761 { 762 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 763 } 764 765 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 766 const struct rtl_cond *c, 767 unsigned int d, int n) 768 { 769 return rtl_loop_wait(tp, c, msleep, d, n, true); 770 } 771 772 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 773 const struct rtl_cond *c, 774 unsigned int d, int n) 775 { 776 return rtl_loop_wait(tp, c, msleep, d, n, false); 777 } 778 779 #define DECLARE_RTL_COND(name) \ 780 static bool name ## _check(struct rtl8169_private *); \ 781 \ 782 static const struct rtl_cond name = { \ 783 .check = name ## _check, \ 784 .msg = #name \ 785 }; \ 786 \ 787 static bool name ## _check(struct rtl8169_private *tp) 788 789 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 790 { 791 if (reg & 0xffff0001) { 792 if (net_ratelimit()) 793 netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg); 794 return true; 795 } 796 return false; 797 } 798 799 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 800 { 801 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 802 } 803 804 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 805 { 806 if (rtl_ocp_reg_failure(tp, reg)) 807 return; 808 809 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 810 811 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 812 } 813 814 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 815 { 816 if (rtl_ocp_reg_failure(tp, reg)) 817 return 0; 818 819 RTL_W32(tp, GPHY_OCP, reg << 15); 820 821 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 822 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 823 } 824 825 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 826 { 827 if (rtl_ocp_reg_failure(tp, reg)) 828 return; 829 830 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 831 } 832 833 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 834 { 835 if (rtl_ocp_reg_failure(tp, reg)) 836 return 0; 837 838 RTL_W32(tp, OCPDR, reg << 15); 839 840 return RTL_R32(tp, OCPDR); 841 } 842 843 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 844 u16 set) 845 { 846 u16 data = r8168_mac_ocp_read(tp, reg); 847 848 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 849 } 850 851 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 852 { 853 if (reg == 0x1f) { 854 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 855 return; 856 } 857 858 if (tp->ocp_base != OCP_STD_PHY_BASE) 859 reg -= 0x10; 860 861 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 862 } 863 864 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 865 { 866 if (reg == 0x1f) 867 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 868 869 if (tp->ocp_base != OCP_STD_PHY_BASE) 870 reg -= 0x10; 871 872 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 873 } 874 875 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 876 { 877 if (reg == 0x1f) { 878 tp->ocp_base = value << 4; 879 return; 880 } 881 882 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 883 } 884 885 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 886 { 887 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 888 } 889 890 DECLARE_RTL_COND(rtl_phyar_cond) 891 { 892 return RTL_R32(tp, PHYAR) & 0x80000000; 893 } 894 895 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 896 { 897 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 898 899 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 900 /* 901 * According to hardware specs a 20us delay is required after write 902 * complete indication, but before sending next command. 903 */ 904 udelay(20); 905 } 906 907 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 908 { 909 int value; 910 911 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 912 913 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 914 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 915 916 /* 917 * According to hardware specs a 20us delay is required after read 918 * complete indication, but before sending next command. 919 */ 920 udelay(20); 921 922 return value; 923 } 924 925 DECLARE_RTL_COND(rtl_ocpar_cond) 926 { 927 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 928 } 929 930 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 931 { 932 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 933 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 934 RTL_W32(tp, EPHY_RXER_NUM, 0); 935 936 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 937 } 938 939 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 940 { 941 r8168dp_1_mdio_access(tp, reg, 942 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 943 } 944 945 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 946 { 947 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 948 949 mdelay(1); 950 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 951 RTL_W32(tp, EPHY_RXER_NUM, 0); 952 953 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 954 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 955 } 956 957 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 958 959 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 960 { 961 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 962 } 963 964 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 965 { 966 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 967 } 968 969 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 970 { 971 r8168dp_2_mdio_start(tp); 972 973 r8169_mdio_write(tp, reg, value); 974 975 r8168dp_2_mdio_stop(tp); 976 } 977 978 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 979 { 980 int value; 981 982 /* Work around issue with chip reporting wrong PHY ID */ 983 if (reg == MII_PHYSID2) 984 return 0xc912; 985 986 r8168dp_2_mdio_start(tp); 987 988 value = r8169_mdio_read(tp, reg); 989 990 r8168dp_2_mdio_stop(tp); 991 992 return value; 993 } 994 995 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 996 { 997 switch (tp->mac_version) { 998 case RTL_GIGA_MAC_VER_27: 999 r8168dp_1_mdio_write(tp, location, val); 1000 break; 1001 case RTL_GIGA_MAC_VER_28: 1002 case RTL_GIGA_MAC_VER_31: 1003 r8168dp_2_mdio_write(tp, location, val); 1004 break; 1005 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1006 r8168g_mdio_write(tp, location, val); 1007 break; 1008 default: 1009 r8169_mdio_write(tp, location, val); 1010 break; 1011 } 1012 } 1013 1014 static int rtl_readphy(struct rtl8169_private *tp, int location) 1015 { 1016 switch (tp->mac_version) { 1017 case RTL_GIGA_MAC_VER_27: 1018 return r8168dp_1_mdio_read(tp, location); 1019 case RTL_GIGA_MAC_VER_28: 1020 case RTL_GIGA_MAC_VER_31: 1021 return r8168dp_2_mdio_read(tp, location); 1022 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1023 return r8168g_mdio_read(tp, location); 1024 default: 1025 return r8169_mdio_read(tp, location); 1026 } 1027 } 1028 1029 DECLARE_RTL_COND(rtl_ephyar_cond) 1030 { 1031 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1032 } 1033 1034 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1035 { 1036 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1037 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1038 1039 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1040 1041 udelay(10); 1042 } 1043 1044 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1045 { 1046 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1047 1048 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1049 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1050 } 1051 1052 DECLARE_RTL_COND(rtl_eriar_cond) 1053 { 1054 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1055 } 1056 1057 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1058 u32 val, int type) 1059 { 1060 BUG_ON((addr & 3) || (mask == 0)); 1061 RTL_W32(tp, ERIDR, val); 1062 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1063 1064 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1065 } 1066 1067 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1068 u32 val) 1069 { 1070 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1071 } 1072 1073 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1074 { 1075 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1076 1077 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1078 RTL_R32(tp, ERIDR) : ~0; 1079 } 1080 1081 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1082 { 1083 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1084 } 1085 1086 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1087 u32 m) 1088 { 1089 u32 val; 1090 1091 val = rtl_eri_read(tp, addr); 1092 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1093 } 1094 1095 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1096 u32 p) 1097 { 1098 rtl_w0w1_eri(tp, addr, mask, p, 0); 1099 } 1100 1101 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1102 u32 m) 1103 { 1104 rtl_w0w1_eri(tp, addr, mask, 0, m); 1105 } 1106 1107 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1108 { 1109 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1110 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1111 RTL_R32(tp, OCPDR) : ~0; 1112 } 1113 1114 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1115 { 1116 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1117 } 1118 1119 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1120 u32 data) 1121 { 1122 RTL_W32(tp, OCPDR, data); 1123 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1124 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1125 } 1126 1127 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1128 u32 data) 1129 { 1130 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1131 data, ERIAR_OOB); 1132 } 1133 1134 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1135 { 1136 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1137 1138 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1139 } 1140 1141 #define OOB_CMD_RESET 0x00 1142 #define OOB_CMD_DRIVER_START 0x05 1143 #define OOB_CMD_DRIVER_STOP 0x06 1144 1145 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1146 { 1147 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1148 } 1149 1150 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1151 { 1152 u16 reg; 1153 1154 reg = rtl8168_get_ocp_reg(tp); 1155 1156 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1157 } 1158 1159 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1160 { 1161 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1162 } 1163 1164 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1165 { 1166 return RTL_R8(tp, IBISR0) & 0x20; 1167 } 1168 1169 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1170 { 1171 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1172 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1173 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1174 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1175 } 1176 1177 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1178 { 1179 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1180 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1181 } 1182 1183 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1184 { 1185 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1186 r8168ep_ocp_write(tp, 0x01, 0x30, 1187 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1188 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1189 } 1190 1191 static void rtl8168_driver_start(struct rtl8169_private *tp) 1192 { 1193 switch (tp->mac_version) { 1194 case RTL_GIGA_MAC_VER_27: 1195 case RTL_GIGA_MAC_VER_28: 1196 case RTL_GIGA_MAC_VER_31: 1197 rtl8168dp_driver_start(tp); 1198 break; 1199 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1200 rtl8168ep_driver_start(tp); 1201 break; 1202 default: 1203 BUG(); 1204 break; 1205 } 1206 } 1207 1208 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1209 { 1210 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1211 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1212 } 1213 1214 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1215 { 1216 rtl8168ep_stop_cmac(tp); 1217 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1218 r8168ep_ocp_write(tp, 0x01, 0x30, 1219 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1220 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1221 } 1222 1223 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1224 { 1225 switch (tp->mac_version) { 1226 case RTL_GIGA_MAC_VER_27: 1227 case RTL_GIGA_MAC_VER_28: 1228 case RTL_GIGA_MAC_VER_31: 1229 rtl8168dp_driver_stop(tp); 1230 break; 1231 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1232 rtl8168ep_driver_stop(tp); 1233 break; 1234 default: 1235 BUG(); 1236 break; 1237 } 1238 } 1239 1240 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1241 { 1242 u16 reg = rtl8168_get_ocp_reg(tp); 1243 1244 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1245 } 1246 1247 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1248 { 1249 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1250 } 1251 1252 static bool r8168_check_dash(struct rtl8169_private *tp) 1253 { 1254 switch (tp->mac_version) { 1255 case RTL_GIGA_MAC_VER_27: 1256 case RTL_GIGA_MAC_VER_28: 1257 case RTL_GIGA_MAC_VER_31: 1258 return r8168dp_check_dash(tp); 1259 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1260 return r8168ep_check_dash(tp); 1261 default: 1262 return false; 1263 } 1264 } 1265 1266 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1267 { 1268 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1269 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1270 } 1271 1272 DECLARE_RTL_COND(rtl_efusear_cond) 1273 { 1274 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1275 } 1276 1277 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1278 { 1279 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1280 1281 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1282 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1283 } 1284 1285 static u32 rtl_get_events(struct rtl8169_private *tp) 1286 { 1287 if (rtl_is_8125(tp)) 1288 return RTL_R32(tp, IntrStatus_8125); 1289 else 1290 return RTL_R16(tp, IntrStatus); 1291 } 1292 1293 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1294 { 1295 if (rtl_is_8125(tp)) 1296 RTL_W32(tp, IntrStatus_8125, bits); 1297 else 1298 RTL_W16(tp, IntrStatus, bits); 1299 } 1300 1301 static void rtl_irq_disable(struct rtl8169_private *tp) 1302 { 1303 if (rtl_is_8125(tp)) 1304 RTL_W32(tp, IntrMask_8125, 0); 1305 else 1306 RTL_W16(tp, IntrMask, 0); 1307 tp->irq_enabled = 0; 1308 } 1309 1310 static void rtl_irq_enable(struct rtl8169_private *tp) 1311 { 1312 tp->irq_enabled = 1; 1313 if (rtl_is_8125(tp)) 1314 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1315 else 1316 RTL_W16(tp, IntrMask, tp->irq_mask); 1317 } 1318 1319 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1320 { 1321 rtl_irq_disable(tp); 1322 rtl_ack_events(tp, 0xffffffff); 1323 rtl_pci_commit(tp); 1324 } 1325 1326 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1327 { 1328 struct phy_device *phydev = tp->phydev; 1329 1330 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1331 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1332 if (phydev->speed == SPEED_1000) { 1333 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1334 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1335 } else if (phydev->speed == SPEED_100) { 1336 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1337 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1338 } else { 1339 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1340 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1341 } 1342 rtl_reset_packet_filter(tp); 1343 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1344 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1345 if (phydev->speed == SPEED_1000) { 1346 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1347 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1348 } else { 1349 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1350 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1351 } 1352 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1353 if (phydev->speed == SPEED_10) { 1354 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1355 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1356 } else { 1357 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1358 } 1359 } 1360 } 1361 1362 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1363 1364 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1365 { 1366 struct rtl8169_private *tp = netdev_priv(dev); 1367 1368 rtl_lock_work(tp); 1369 wol->supported = WAKE_ANY; 1370 wol->wolopts = tp->saved_wolopts; 1371 rtl_unlock_work(tp); 1372 } 1373 1374 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1375 { 1376 static const struct { 1377 u32 opt; 1378 u16 reg; 1379 u8 mask; 1380 } cfg[] = { 1381 { WAKE_PHY, Config3, LinkUp }, 1382 { WAKE_UCAST, Config5, UWF }, 1383 { WAKE_BCAST, Config5, BWF }, 1384 { WAKE_MCAST, Config5, MWF }, 1385 { WAKE_ANY, Config5, LanWake }, 1386 { WAKE_MAGIC, Config3, MagicPacket } 1387 }; 1388 unsigned int i, tmp = ARRAY_SIZE(cfg); 1389 u8 options; 1390 1391 rtl_unlock_config_regs(tp); 1392 1393 if (rtl_is_8168evl_up(tp)) { 1394 tmp--; 1395 if (wolopts & WAKE_MAGIC) 1396 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1397 MagicPacket_v2); 1398 else 1399 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1400 MagicPacket_v2); 1401 } else if (rtl_is_8125(tp)) { 1402 tmp--; 1403 if (wolopts & WAKE_MAGIC) 1404 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1405 else 1406 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1407 } 1408 1409 for (i = 0; i < tmp; i++) { 1410 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1411 if (wolopts & cfg[i].opt) 1412 options |= cfg[i].mask; 1413 RTL_W8(tp, cfg[i].reg, options); 1414 } 1415 1416 switch (tp->mac_version) { 1417 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1418 options = RTL_R8(tp, Config1) & ~PMEnable; 1419 if (wolopts) 1420 options |= PMEnable; 1421 RTL_W8(tp, Config1, options); 1422 break; 1423 case RTL_GIGA_MAC_VER_34: 1424 case RTL_GIGA_MAC_VER_37: 1425 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_61: 1426 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1427 if (wolopts) 1428 options |= PME_SIGNAL; 1429 RTL_W8(tp, Config2, options); 1430 break; 1431 default: 1432 break; 1433 } 1434 1435 rtl_lock_config_regs(tp); 1436 1437 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1438 tp->dev->wol_enabled = wolopts ? 1 : 0; 1439 } 1440 1441 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1442 { 1443 struct rtl8169_private *tp = netdev_priv(dev); 1444 struct device *d = tp_to_dev(tp); 1445 1446 if (wol->wolopts & ~WAKE_ANY) 1447 return -EINVAL; 1448 1449 pm_runtime_get_noresume(d); 1450 1451 rtl_lock_work(tp); 1452 1453 tp->saved_wolopts = wol->wolopts; 1454 1455 if (pm_runtime_active(d)) 1456 __rtl8169_set_wol(tp, tp->saved_wolopts); 1457 1458 rtl_unlock_work(tp); 1459 1460 pm_runtime_put_noidle(d); 1461 1462 return 0; 1463 } 1464 1465 static void rtl8169_get_drvinfo(struct net_device *dev, 1466 struct ethtool_drvinfo *info) 1467 { 1468 struct rtl8169_private *tp = netdev_priv(dev); 1469 struct rtl_fw *rtl_fw = tp->rtl_fw; 1470 1471 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1472 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1473 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1474 if (rtl_fw) 1475 strlcpy(info->fw_version, rtl_fw->version, 1476 sizeof(info->fw_version)); 1477 } 1478 1479 static int rtl8169_get_regs_len(struct net_device *dev) 1480 { 1481 return R8169_REGS_SIZE; 1482 } 1483 1484 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1485 netdev_features_t features) 1486 { 1487 struct rtl8169_private *tp = netdev_priv(dev); 1488 1489 if (dev->mtu > TD_MSS_MAX) 1490 features &= ~NETIF_F_ALL_TSO; 1491 1492 if (dev->mtu > ETH_DATA_LEN && 1493 tp->mac_version > RTL_GIGA_MAC_VER_06) 1494 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1495 1496 return features; 1497 } 1498 1499 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1500 netdev_features_t features) 1501 { 1502 u32 rx_config = RTL_R32(tp, RxConfig); 1503 1504 if (features & NETIF_F_RXALL) 1505 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1506 else 1507 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1508 1509 if (rtl_is_8125(tp)) { 1510 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1511 rx_config |= RX_VLAN_8125; 1512 else 1513 rx_config &= ~RX_VLAN_8125; 1514 } 1515 1516 RTL_W32(tp, RxConfig, rx_config); 1517 } 1518 1519 static int rtl8169_set_features(struct net_device *dev, 1520 netdev_features_t features) 1521 { 1522 struct rtl8169_private *tp = netdev_priv(dev); 1523 1524 rtl_lock_work(tp); 1525 1526 rtl_set_rx_config_features(tp, features); 1527 1528 if (features & NETIF_F_RXCSUM) 1529 tp->cp_cmd |= RxChkSum; 1530 else 1531 tp->cp_cmd &= ~RxChkSum; 1532 1533 if (!rtl_is_8125(tp)) { 1534 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1535 tp->cp_cmd |= RxVlan; 1536 else 1537 tp->cp_cmd &= ~RxVlan; 1538 } 1539 1540 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1541 rtl_pci_commit(tp); 1542 1543 rtl_unlock_work(tp); 1544 1545 return 0; 1546 } 1547 1548 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1549 { 1550 return (skb_vlan_tag_present(skb)) ? 1551 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1552 } 1553 1554 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1555 { 1556 u32 opts2 = le32_to_cpu(desc->opts2); 1557 1558 if (opts2 & RxVlanTag) 1559 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1560 } 1561 1562 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1563 void *p) 1564 { 1565 struct rtl8169_private *tp = netdev_priv(dev); 1566 u32 __iomem *data = tp->mmio_addr; 1567 u32 *dw = p; 1568 int i; 1569 1570 rtl_lock_work(tp); 1571 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1572 memcpy_fromio(dw++, data++, 4); 1573 rtl_unlock_work(tp); 1574 } 1575 1576 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1577 "tx_packets", 1578 "rx_packets", 1579 "tx_errors", 1580 "rx_errors", 1581 "rx_missed", 1582 "align_errors", 1583 "tx_single_collisions", 1584 "tx_multi_collisions", 1585 "unicast", 1586 "broadcast", 1587 "multicast", 1588 "tx_aborted", 1589 "tx_underrun", 1590 }; 1591 1592 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1593 { 1594 switch (sset) { 1595 case ETH_SS_STATS: 1596 return ARRAY_SIZE(rtl8169_gstrings); 1597 default: 1598 return -EOPNOTSUPP; 1599 } 1600 } 1601 1602 DECLARE_RTL_COND(rtl_counters_cond) 1603 { 1604 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1605 } 1606 1607 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1608 { 1609 dma_addr_t paddr = tp->counters_phys_addr; 1610 u32 cmd; 1611 1612 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1613 rtl_pci_commit(tp); 1614 cmd = (u64)paddr & DMA_BIT_MASK(32); 1615 RTL_W32(tp, CounterAddrLow, cmd); 1616 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1617 1618 rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1619 } 1620 1621 static void rtl8169_reset_counters(struct rtl8169_private *tp) 1622 { 1623 /* 1624 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1625 * tally counters. 1626 */ 1627 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) 1628 rtl8169_do_counters(tp, CounterReset); 1629 } 1630 1631 static void rtl8169_update_counters(struct rtl8169_private *tp) 1632 { 1633 u8 val = RTL_R8(tp, ChipCmd); 1634 1635 /* 1636 * Some chips are unable to dump tally counters when the receiver 1637 * is disabled. If 0xff chip may be in a PCI power-save state. 1638 */ 1639 if (val & CmdRxEnb && val != 0xff) 1640 rtl8169_do_counters(tp, CounterDump); 1641 } 1642 1643 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1644 { 1645 struct rtl8169_counters *counters = tp->counters; 1646 1647 /* 1648 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1649 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1650 * reset by a power cycle, while the counter values collected by the 1651 * driver are reset at every driver unload/load cycle. 1652 * 1653 * To make sure the HW values returned by @get_stats64 match the SW 1654 * values, we collect the initial values at first open(*) and use them 1655 * as offsets to normalize the values returned by @get_stats64. 1656 * 1657 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1658 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1659 * set at open time by rtl_hw_start. 1660 */ 1661 1662 if (tp->tc_offset.inited) 1663 return; 1664 1665 rtl8169_reset_counters(tp); 1666 rtl8169_update_counters(tp); 1667 1668 tp->tc_offset.tx_errors = counters->tx_errors; 1669 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1670 tp->tc_offset.tx_aborted = counters->tx_aborted; 1671 tp->tc_offset.rx_missed = counters->rx_missed; 1672 tp->tc_offset.inited = true; 1673 } 1674 1675 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1676 struct ethtool_stats *stats, u64 *data) 1677 { 1678 struct rtl8169_private *tp = netdev_priv(dev); 1679 struct device *d = tp_to_dev(tp); 1680 struct rtl8169_counters *counters = tp->counters; 1681 1682 ASSERT_RTNL(); 1683 1684 pm_runtime_get_noresume(d); 1685 1686 if (pm_runtime_active(d)) 1687 rtl8169_update_counters(tp); 1688 1689 pm_runtime_put_noidle(d); 1690 1691 data[0] = le64_to_cpu(counters->tx_packets); 1692 data[1] = le64_to_cpu(counters->rx_packets); 1693 data[2] = le64_to_cpu(counters->tx_errors); 1694 data[3] = le32_to_cpu(counters->rx_errors); 1695 data[4] = le16_to_cpu(counters->rx_missed); 1696 data[5] = le16_to_cpu(counters->align_errors); 1697 data[6] = le32_to_cpu(counters->tx_one_collision); 1698 data[7] = le32_to_cpu(counters->tx_multi_collision); 1699 data[8] = le64_to_cpu(counters->rx_unicast); 1700 data[9] = le64_to_cpu(counters->rx_broadcast); 1701 data[10] = le32_to_cpu(counters->rx_multicast); 1702 data[11] = le16_to_cpu(counters->tx_aborted); 1703 data[12] = le16_to_cpu(counters->tx_underun); 1704 } 1705 1706 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1707 { 1708 switch(stringset) { 1709 case ETH_SS_STATS: 1710 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1711 break; 1712 } 1713 } 1714 1715 /* 1716 * Interrupt coalescing 1717 * 1718 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1719 * > 8169, 8168 and 810x line of chipsets 1720 * 1721 * 8169, 8168, and 8136(810x) serial chipsets support it. 1722 * 1723 * > 2 - the Tx timer unit at gigabit speed 1724 * 1725 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1726 * (0xe0) bit 1 and bit 0. 1727 * 1728 * For 8169 1729 * bit[1:0] \ speed 1000M 100M 10M 1730 * 0 0 320ns 2.56us 40.96us 1731 * 0 1 2.56us 20.48us 327.7us 1732 * 1 0 5.12us 40.96us 655.4us 1733 * 1 1 10.24us 81.92us 1.31ms 1734 * 1735 * For the other 1736 * bit[1:0] \ speed 1000M 100M 10M 1737 * 0 0 5us 2.56us 40.96us 1738 * 0 1 40us 20.48us 327.7us 1739 * 1 0 80us 40.96us 655.4us 1740 * 1 1 160us 81.92us 1.31ms 1741 */ 1742 1743 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1744 struct rtl_coalesce_info { 1745 u32 speed; 1746 u32 scale_nsecs[4]; 1747 }; 1748 1749 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1750 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1751 1752 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1753 { SPEED_10, COALESCE_DELAY(40960) }, 1754 { SPEED_100, COALESCE_DELAY(2560) }, 1755 { SPEED_1000, COALESCE_DELAY(320) }, 1756 { 0 }, 1757 }; 1758 1759 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1760 { SPEED_10, COALESCE_DELAY(40960) }, 1761 { SPEED_100, COALESCE_DELAY(2560) }, 1762 { SPEED_1000, COALESCE_DELAY(5000) }, 1763 { 0 }, 1764 }; 1765 #undef COALESCE_DELAY 1766 1767 /* get rx/tx scale vector corresponding to current speed */ 1768 static const struct rtl_coalesce_info * 1769 rtl_coalesce_info(struct rtl8169_private *tp) 1770 { 1771 const struct rtl_coalesce_info *ci; 1772 1773 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1774 ci = rtl_coalesce_info_8169; 1775 else 1776 ci = rtl_coalesce_info_8168_8136; 1777 1778 for (; ci->speed; ci++) { 1779 if (tp->phydev->speed == ci->speed) 1780 return ci; 1781 } 1782 1783 return ERR_PTR(-ELNRNG); 1784 } 1785 1786 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1787 { 1788 struct rtl8169_private *tp = netdev_priv(dev); 1789 const struct rtl_coalesce_info *ci; 1790 u32 scale, c_us, c_fr; 1791 u16 intrmit; 1792 1793 if (rtl_is_8125(tp)) 1794 return -EOPNOTSUPP; 1795 1796 memset(ec, 0, sizeof(*ec)); 1797 1798 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1799 ci = rtl_coalesce_info(tp); 1800 if (IS_ERR(ci)) 1801 return PTR_ERR(ci); 1802 1803 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1804 1805 intrmit = RTL_R16(tp, IntrMitigate); 1806 1807 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1808 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1809 1810 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1811 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1812 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1813 1814 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1815 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1816 1817 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1818 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1819 1820 return 0; 1821 } 1822 1823 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1824 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1825 u16 *cp01) 1826 { 1827 const struct rtl_coalesce_info *ci; 1828 u16 i; 1829 1830 ci = rtl_coalesce_info(tp); 1831 if (IS_ERR(ci)) 1832 return PTR_ERR(ci); 1833 1834 for (i = 0; i < 4; i++) { 1835 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1836 *cp01 = i; 1837 return ci->scale_nsecs[i]; 1838 } 1839 } 1840 1841 return -ERANGE; 1842 } 1843 1844 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1845 { 1846 struct rtl8169_private *tp = netdev_priv(dev); 1847 u32 tx_fr = ec->tx_max_coalesced_frames; 1848 u32 rx_fr = ec->rx_max_coalesced_frames; 1849 u32 coal_usec_max, units; 1850 u16 w = 0, cp01 = 0; 1851 int scale; 1852 1853 if (rtl_is_8125(tp)) 1854 return -EOPNOTSUPP; 1855 1856 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1857 return -ERANGE; 1858 1859 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1860 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1861 if (scale < 0) 1862 return scale; 1863 1864 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1865 * not only when usecs=0 because of e.g. the following scenario: 1866 * 1867 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1868 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1869 * - then user does `ethtool -C eth0 rx-usecs 100` 1870 * 1871 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1872 * if we want to ignore rx_frames then it has to be set to 0. 1873 */ 1874 if (rx_fr == 1) 1875 rx_fr = 0; 1876 if (tx_fr == 1) 1877 tx_fr = 0; 1878 1879 /* HW requires time limit to be set if frame limit is set */ 1880 if ((tx_fr && !ec->tx_coalesce_usecs) || 1881 (rx_fr && !ec->rx_coalesce_usecs)) 1882 return -EINVAL; 1883 1884 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1885 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1886 1887 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1888 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1889 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1890 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1891 1892 rtl_lock_work(tp); 1893 1894 RTL_W16(tp, IntrMitigate, w); 1895 1896 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1897 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1898 rtl_pci_commit(tp); 1899 1900 rtl_unlock_work(tp); 1901 1902 return 0; 1903 } 1904 1905 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1906 { 1907 struct rtl8169_private *tp = netdev_priv(dev); 1908 struct device *d = tp_to_dev(tp); 1909 int ret; 1910 1911 if (!rtl_supports_eee(tp)) 1912 return -EOPNOTSUPP; 1913 1914 pm_runtime_get_noresume(d); 1915 1916 if (!pm_runtime_active(d)) { 1917 ret = -EOPNOTSUPP; 1918 } else { 1919 ret = phy_ethtool_get_eee(tp->phydev, data); 1920 } 1921 1922 pm_runtime_put_noidle(d); 1923 1924 return ret; 1925 } 1926 1927 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1928 { 1929 struct rtl8169_private *tp = netdev_priv(dev); 1930 struct device *d = tp_to_dev(tp); 1931 int ret; 1932 1933 if (!rtl_supports_eee(tp)) 1934 return -EOPNOTSUPP; 1935 1936 pm_runtime_get_noresume(d); 1937 1938 if (!pm_runtime_active(d)) { 1939 ret = -EOPNOTSUPP; 1940 goto out; 1941 } 1942 1943 if (dev->phydev->autoneg == AUTONEG_DISABLE || 1944 dev->phydev->duplex != DUPLEX_FULL) { 1945 ret = -EPROTONOSUPPORT; 1946 goto out; 1947 } 1948 1949 ret = phy_ethtool_set_eee(tp->phydev, data); 1950 1951 if (!ret) 1952 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1953 MDIO_AN_EEE_ADV); 1954 out: 1955 pm_runtime_put_noidle(d); 1956 return ret; 1957 } 1958 1959 static const struct ethtool_ops rtl8169_ethtool_ops = { 1960 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1961 ETHTOOL_COALESCE_MAX_FRAMES, 1962 .get_drvinfo = rtl8169_get_drvinfo, 1963 .get_regs_len = rtl8169_get_regs_len, 1964 .get_link = ethtool_op_get_link, 1965 .get_coalesce = rtl_get_coalesce, 1966 .set_coalesce = rtl_set_coalesce, 1967 .get_regs = rtl8169_get_regs, 1968 .get_wol = rtl8169_get_wol, 1969 .set_wol = rtl8169_set_wol, 1970 .get_strings = rtl8169_get_strings, 1971 .get_sset_count = rtl8169_get_sset_count, 1972 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1973 .get_ts_info = ethtool_op_get_ts_info, 1974 .nway_reset = phy_ethtool_nway_reset, 1975 .get_eee = rtl8169_get_eee, 1976 .set_eee = rtl8169_set_eee, 1977 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1978 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1979 }; 1980 1981 static void rtl_enable_eee(struct rtl8169_private *tp) 1982 { 1983 struct phy_device *phydev = tp->phydev; 1984 int adv; 1985 1986 /* respect EEE advertisement the user may have set */ 1987 if (tp->eee_adv >= 0) 1988 adv = tp->eee_adv; 1989 else 1990 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1991 1992 if (adv >= 0) 1993 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1994 } 1995 1996 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1997 { 1998 /* 1999 * The driver currently handles the 8168Bf and the 8168Be identically 2000 * but they can be identified more specifically through the test below 2001 * if needed: 2002 * 2003 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2004 * 2005 * Same thing for the 8101Eb and the 8101Ec: 2006 * 2007 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2008 */ 2009 static const struct rtl_mac_info { 2010 u16 mask; 2011 u16 val; 2012 enum mac_version ver; 2013 } mac_info[] = { 2014 /* 8125 family. */ 2015 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2016 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2017 2018 /* RTL8117 */ 2019 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2020 2021 /* 8168EP family. */ 2022 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2023 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2024 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2025 2026 /* 8168H family. */ 2027 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2028 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2029 2030 /* 8168G family. */ 2031 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2032 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2033 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2034 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2035 2036 /* 8168F family. */ 2037 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2038 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2039 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2040 2041 /* 8168E family. */ 2042 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2043 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2044 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2045 2046 /* 8168D family. */ 2047 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2048 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2049 2050 /* 8168DP family. */ 2051 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2052 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2053 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2054 2055 /* 8168C family. */ 2056 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2057 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2058 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2059 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2060 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2061 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2062 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2063 2064 /* 8168B family. */ 2065 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2066 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2067 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2068 2069 /* 8101 family. */ 2070 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2071 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2072 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2073 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2074 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2075 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2076 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2077 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2078 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2079 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2080 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2081 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2082 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2083 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2084 /* FIXME: where did these entries come from ? -- FR */ 2085 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2086 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2087 2088 /* 8110 family. */ 2089 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2090 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2091 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2092 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2093 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2094 2095 /* Catch-all */ 2096 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2097 }; 2098 const struct rtl_mac_info *p = mac_info; 2099 enum mac_version ver; 2100 2101 while ((xid & p->mask) != p->val) 2102 p++; 2103 ver = p->ver; 2104 2105 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2106 if (ver == RTL_GIGA_MAC_VER_42) 2107 ver = RTL_GIGA_MAC_VER_43; 2108 else if (ver == RTL_GIGA_MAC_VER_45) 2109 ver = RTL_GIGA_MAC_VER_47; 2110 else if (ver == RTL_GIGA_MAC_VER_46) 2111 ver = RTL_GIGA_MAC_VER_48; 2112 } 2113 2114 return ver; 2115 } 2116 2117 static void rtl_release_firmware(struct rtl8169_private *tp) 2118 { 2119 if (tp->rtl_fw) { 2120 rtl_fw_release_firmware(tp->rtl_fw); 2121 kfree(tp->rtl_fw); 2122 tp->rtl_fw = NULL; 2123 } 2124 } 2125 2126 void r8169_apply_firmware(struct rtl8169_private *tp) 2127 { 2128 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2129 if (tp->rtl_fw) 2130 rtl_fw_write_firmware(tp, tp->rtl_fw); 2131 } 2132 2133 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2134 { 2135 /* Adjust EEE LED frequency */ 2136 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2137 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2138 2139 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2140 } 2141 2142 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2143 { 2144 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2145 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2146 } 2147 2148 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2149 { 2150 const u16 w[] = { 2151 addr[0] | (addr[1] << 8), 2152 addr[2] | (addr[3] << 8), 2153 addr[4] | (addr[5] << 8) 2154 }; 2155 2156 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2157 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2158 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2159 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2160 } 2161 2162 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2163 { 2164 u16 data1, data2, ioffset; 2165 2166 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2167 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2168 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2169 2170 ioffset = (data2 >> 1) & 0x7ff8; 2171 ioffset |= data2 & 0x0007; 2172 if (data1 & BIT(7)) 2173 ioffset |= BIT(15); 2174 2175 return ioffset; 2176 } 2177 2178 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2179 { 2180 set_bit(flag, tp->wk.flags); 2181 schedule_work(&tp->wk.work); 2182 } 2183 2184 static void rtl8169_init_phy(struct rtl8169_private *tp) 2185 { 2186 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2187 2188 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2189 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2190 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2191 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2192 RTL_W8(tp, 0x82, 0x01); 2193 } 2194 2195 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2196 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2197 tp->pci_dev->subsystem_device == 0xe000) 2198 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2199 2200 /* We may have called phy_speed_down before */ 2201 phy_speed_up(tp->phydev); 2202 2203 if (rtl_supports_eee(tp)) 2204 rtl_enable_eee(tp); 2205 2206 genphy_soft_reset(tp->phydev); 2207 } 2208 2209 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 2210 { 2211 rtl_lock_work(tp); 2212 2213 rtl_unlock_config_regs(tp); 2214 2215 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 2216 rtl_pci_commit(tp); 2217 2218 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2219 rtl_pci_commit(tp); 2220 2221 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2222 rtl_rar_exgmac_set(tp, addr); 2223 2224 rtl_lock_config_regs(tp); 2225 2226 rtl_unlock_work(tp); 2227 } 2228 2229 static int rtl_set_mac_address(struct net_device *dev, void *p) 2230 { 2231 struct rtl8169_private *tp = netdev_priv(dev); 2232 struct device *d = tp_to_dev(tp); 2233 int ret; 2234 2235 ret = eth_mac_addr(dev, p); 2236 if (ret) 2237 return ret; 2238 2239 pm_runtime_get_noresume(d); 2240 2241 if (pm_runtime_active(d)) 2242 rtl_rar_set(tp, dev->dev_addr); 2243 2244 pm_runtime_put_noidle(d); 2245 2246 return 0; 2247 } 2248 2249 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 2250 { 2251 switch (tp->mac_version) { 2252 case RTL_GIGA_MAC_VER_25: 2253 case RTL_GIGA_MAC_VER_26: 2254 case RTL_GIGA_MAC_VER_29: 2255 case RTL_GIGA_MAC_VER_30: 2256 case RTL_GIGA_MAC_VER_32: 2257 case RTL_GIGA_MAC_VER_33: 2258 case RTL_GIGA_MAC_VER_34: 2259 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61: 2260 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2261 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2262 break; 2263 default: 2264 break; 2265 } 2266 } 2267 2268 static void rtl_pll_power_down(struct rtl8169_private *tp) 2269 { 2270 if (r8168_check_dash(tp)) 2271 return; 2272 2273 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2274 tp->mac_version == RTL_GIGA_MAC_VER_33) 2275 rtl_ephy_write(tp, 0x19, 0xff64); 2276 2277 if (device_may_wakeup(tp_to_dev(tp))) { 2278 phy_speed_down(tp->phydev, false); 2279 rtl_wol_suspend_quirk(tp); 2280 return; 2281 } 2282 2283 switch (tp->mac_version) { 2284 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2285 case RTL_GIGA_MAC_VER_37: 2286 case RTL_GIGA_MAC_VER_39: 2287 case RTL_GIGA_MAC_VER_43: 2288 case RTL_GIGA_MAC_VER_44: 2289 case RTL_GIGA_MAC_VER_45: 2290 case RTL_GIGA_MAC_VER_46: 2291 case RTL_GIGA_MAC_VER_47: 2292 case RTL_GIGA_MAC_VER_48: 2293 case RTL_GIGA_MAC_VER_50: 2294 case RTL_GIGA_MAC_VER_51: 2295 case RTL_GIGA_MAC_VER_52: 2296 case RTL_GIGA_MAC_VER_60: 2297 case RTL_GIGA_MAC_VER_61: 2298 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2299 break; 2300 case RTL_GIGA_MAC_VER_40: 2301 case RTL_GIGA_MAC_VER_41: 2302 case RTL_GIGA_MAC_VER_49: 2303 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 2304 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2305 break; 2306 default: 2307 break; 2308 } 2309 } 2310 2311 static void rtl_pll_power_up(struct rtl8169_private *tp) 2312 { 2313 switch (tp->mac_version) { 2314 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2315 case RTL_GIGA_MAC_VER_37: 2316 case RTL_GIGA_MAC_VER_39: 2317 case RTL_GIGA_MAC_VER_43: 2318 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 2319 break; 2320 case RTL_GIGA_MAC_VER_44: 2321 case RTL_GIGA_MAC_VER_45: 2322 case RTL_GIGA_MAC_VER_46: 2323 case RTL_GIGA_MAC_VER_47: 2324 case RTL_GIGA_MAC_VER_48: 2325 case RTL_GIGA_MAC_VER_50: 2326 case RTL_GIGA_MAC_VER_51: 2327 case RTL_GIGA_MAC_VER_52: 2328 case RTL_GIGA_MAC_VER_60: 2329 case RTL_GIGA_MAC_VER_61: 2330 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2331 break; 2332 case RTL_GIGA_MAC_VER_40: 2333 case RTL_GIGA_MAC_VER_41: 2334 case RTL_GIGA_MAC_VER_49: 2335 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2336 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 2337 break; 2338 default: 2339 break; 2340 } 2341 2342 phy_resume(tp->phydev); 2343 } 2344 2345 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2346 { 2347 switch (tp->mac_version) { 2348 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2349 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2350 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2351 break; 2352 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2353 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2354 case RTL_GIGA_MAC_VER_38: 2355 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2356 break; 2357 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2358 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2359 break; 2360 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2361 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2362 break; 2363 default: 2364 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2365 break; 2366 } 2367 } 2368 2369 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2370 { 2371 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2372 } 2373 2374 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2375 { 2376 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2377 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2378 } 2379 2380 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2381 { 2382 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2383 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2384 } 2385 2386 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2387 { 2388 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2389 } 2390 2391 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2392 { 2393 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2394 } 2395 2396 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2397 { 2398 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2399 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2400 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2401 } 2402 2403 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2404 { 2405 RTL_W8(tp, MaxTxPacketSize, 0x0c); 2406 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2407 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2408 } 2409 2410 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2411 { 2412 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2413 } 2414 2415 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2416 { 2417 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2418 } 2419 2420 static void rtl_jumbo_config(struct rtl8169_private *tp) 2421 { 2422 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2423 2424 rtl_unlock_config_regs(tp); 2425 switch (tp->mac_version) { 2426 case RTL_GIGA_MAC_VER_12: 2427 case RTL_GIGA_MAC_VER_17: 2428 if (jumbo) { 2429 pcie_set_readrq(tp->pci_dev, 512); 2430 r8168b_1_hw_jumbo_enable(tp); 2431 } else { 2432 r8168b_1_hw_jumbo_disable(tp); 2433 } 2434 break; 2435 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2436 if (jumbo) { 2437 pcie_set_readrq(tp->pci_dev, 512); 2438 r8168c_hw_jumbo_enable(tp); 2439 } else { 2440 r8168c_hw_jumbo_disable(tp); 2441 } 2442 break; 2443 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2444 if (jumbo) 2445 r8168dp_hw_jumbo_enable(tp); 2446 else 2447 r8168dp_hw_jumbo_disable(tp); 2448 break; 2449 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2450 if (jumbo) { 2451 pcie_set_readrq(tp->pci_dev, 512); 2452 r8168e_hw_jumbo_enable(tp); 2453 } else { 2454 r8168e_hw_jumbo_disable(tp); 2455 } 2456 break; 2457 default: 2458 break; 2459 } 2460 rtl_lock_config_regs(tp); 2461 2462 if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2463 pcie_set_readrq(tp->pci_dev, 4096); 2464 } 2465 2466 DECLARE_RTL_COND(rtl_chipcmd_cond) 2467 { 2468 return RTL_R8(tp, ChipCmd) & CmdReset; 2469 } 2470 2471 static void rtl_hw_reset(struct rtl8169_private *tp) 2472 { 2473 RTL_W8(tp, ChipCmd, CmdReset); 2474 2475 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2476 } 2477 2478 static void rtl_request_firmware(struct rtl8169_private *tp) 2479 { 2480 struct rtl_fw *rtl_fw; 2481 2482 /* firmware loaded already or no firmware available */ 2483 if (tp->rtl_fw || !tp->fw_name) 2484 return; 2485 2486 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2487 if (!rtl_fw) 2488 return; 2489 2490 rtl_fw->phy_write = rtl_writephy; 2491 rtl_fw->phy_read = rtl_readphy; 2492 rtl_fw->mac_mcu_write = mac_mcu_write; 2493 rtl_fw->mac_mcu_read = mac_mcu_read; 2494 rtl_fw->fw_name = tp->fw_name; 2495 rtl_fw->dev = tp_to_dev(tp); 2496 2497 if (rtl_fw_request_firmware(rtl_fw)) 2498 kfree(rtl_fw); 2499 else 2500 tp->rtl_fw = rtl_fw; 2501 } 2502 2503 static void rtl_rx_close(struct rtl8169_private *tp) 2504 { 2505 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2506 } 2507 2508 DECLARE_RTL_COND(rtl_npq_cond) 2509 { 2510 return RTL_R8(tp, TxPoll) & NPQ; 2511 } 2512 2513 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2514 { 2515 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2516 } 2517 2518 static void rtl8169_hw_reset(struct rtl8169_private *tp) 2519 { 2520 /* Disable interrupts */ 2521 rtl8169_irq_mask_and_ack(tp); 2522 2523 rtl_rx_close(tp); 2524 2525 switch (tp->mac_version) { 2526 case RTL_GIGA_MAC_VER_27: 2527 case RTL_GIGA_MAC_VER_28: 2528 case RTL_GIGA_MAC_VER_31: 2529 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 2530 break; 2531 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2532 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2533 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2534 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 2535 break; 2536 default: 2537 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2538 udelay(100); 2539 break; 2540 } 2541 2542 rtl_hw_reset(tp); 2543 } 2544 2545 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2546 { 2547 u32 val = TX_DMA_BURST << TxDMAShift | 2548 InterFrameGap << TxInterFrameGapShift; 2549 2550 if (rtl_is_8168evl_up(tp)) 2551 val |= TXCFG_AUTO_FIFO; 2552 2553 RTL_W32(tp, TxConfig, val); 2554 } 2555 2556 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2557 { 2558 /* Low hurts. Let's disable the filtering. */ 2559 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2560 } 2561 2562 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2563 { 2564 /* 2565 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2566 * register to be written before TxDescAddrLow to work. 2567 * Switching from MMIO to I/O access fixes the issue as well. 2568 */ 2569 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2570 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2571 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2572 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2573 } 2574 2575 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2576 { 2577 u32 val; 2578 2579 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2580 val = 0x000fff00; 2581 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2582 val = 0x00ffff00; 2583 else 2584 return; 2585 2586 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2587 val |= 0xff; 2588 2589 RTL_W32(tp, 0x7c, val); 2590 } 2591 2592 static void rtl_set_rx_mode(struct net_device *dev) 2593 { 2594 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2595 /* Multicast hash filter */ 2596 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2597 struct rtl8169_private *tp = netdev_priv(dev); 2598 u32 tmp; 2599 2600 if (dev->flags & IFF_PROMISC) { 2601 rx_mode |= AcceptAllPhys; 2602 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2603 dev->flags & IFF_ALLMULTI || 2604 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2605 /* accept all multicasts */ 2606 } else if (netdev_mc_empty(dev)) { 2607 rx_mode &= ~AcceptMulticast; 2608 } else { 2609 struct netdev_hw_addr *ha; 2610 2611 mc_filter[1] = mc_filter[0] = 0; 2612 netdev_for_each_mc_addr(ha, dev) { 2613 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2614 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2615 } 2616 2617 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2618 tmp = mc_filter[0]; 2619 mc_filter[0] = swab32(mc_filter[1]); 2620 mc_filter[1] = swab32(tmp); 2621 } 2622 } 2623 2624 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2625 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2626 2627 tmp = RTL_R32(tp, RxConfig); 2628 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2629 } 2630 2631 DECLARE_RTL_COND(rtl_csiar_cond) 2632 { 2633 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2634 } 2635 2636 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2637 { 2638 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2639 2640 RTL_W32(tp, CSIDR, value); 2641 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2642 CSIAR_BYTE_ENABLE | func << 16); 2643 2644 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2645 } 2646 2647 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2648 { 2649 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2650 2651 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2652 CSIAR_BYTE_ENABLE); 2653 2654 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2655 RTL_R32(tp, CSIDR) : ~0; 2656 } 2657 2658 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2659 { 2660 struct pci_dev *pdev = tp->pci_dev; 2661 u32 csi; 2662 2663 /* According to Realtek the value at config space address 0x070f 2664 * controls the L0s/L1 entrance latency. We try standard ECAM access 2665 * first and if it fails fall back to CSI. 2666 */ 2667 if (pdev->cfg_size > 0x070f && 2668 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2669 return; 2670 2671 netdev_notice_once(tp->dev, 2672 "No native access to PCI extended config space, falling back to CSI\n"); 2673 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2674 rtl_csi_write(tp, 0x070c, csi | val << 24); 2675 } 2676 2677 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2678 { 2679 rtl_csi_access_enable(tp, 0x27); 2680 } 2681 2682 struct ephy_info { 2683 unsigned int offset; 2684 u16 mask; 2685 u16 bits; 2686 }; 2687 2688 static void __rtl_ephy_init(struct rtl8169_private *tp, 2689 const struct ephy_info *e, int len) 2690 { 2691 u16 w; 2692 2693 while (len-- > 0) { 2694 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2695 rtl_ephy_write(tp, e->offset, w); 2696 e++; 2697 } 2698 } 2699 2700 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2701 2702 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2703 { 2704 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2705 PCI_EXP_LNKCTL_CLKREQ_EN); 2706 } 2707 2708 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2709 { 2710 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2711 PCI_EXP_LNKCTL_CLKREQ_EN); 2712 } 2713 2714 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2715 { 2716 /* work around an issue when PCI reset occurs during L2/L3 state */ 2717 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2718 } 2719 2720 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2721 { 2722 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2723 if (enable && tp->aspm_manageable) { 2724 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2725 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2726 } else { 2727 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2728 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2729 } 2730 2731 udelay(10); 2732 } 2733 2734 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2735 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2736 { 2737 /* Usage of dynamic vs. static FIFO is controlled by bit 2738 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2739 */ 2740 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2741 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2742 } 2743 2744 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2745 u8 low, u8 high) 2746 { 2747 /* FIFO thresholds for pause flow control */ 2748 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2749 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2750 } 2751 2752 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2753 { 2754 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2755 } 2756 2757 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2758 { 2759 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2760 2761 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2762 2763 rtl_disable_clock_request(tp); 2764 } 2765 2766 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2767 { 2768 static const struct ephy_info e_info_8168cp[] = { 2769 { 0x01, 0, 0x0001 }, 2770 { 0x02, 0x0800, 0x1000 }, 2771 { 0x03, 0, 0x0042 }, 2772 { 0x06, 0x0080, 0x0000 }, 2773 { 0x07, 0, 0x2000 } 2774 }; 2775 2776 rtl_set_def_aspm_entry_latency(tp); 2777 2778 rtl_ephy_init(tp, e_info_8168cp); 2779 2780 __rtl_hw_start_8168cp(tp); 2781 } 2782 2783 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2784 { 2785 rtl_set_def_aspm_entry_latency(tp); 2786 2787 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2788 } 2789 2790 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2791 { 2792 rtl_set_def_aspm_entry_latency(tp); 2793 2794 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2795 2796 /* Magic. */ 2797 RTL_W8(tp, DBG_REG, 0x20); 2798 } 2799 2800 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2801 { 2802 static const struct ephy_info e_info_8168c_1[] = { 2803 { 0x02, 0x0800, 0x1000 }, 2804 { 0x03, 0, 0x0002 }, 2805 { 0x06, 0x0080, 0x0000 } 2806 }; 2807 2808 rtl_set_def_aspm_entry_latency(tp); 2809 2810 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2811 2812 rtl_ephy_init(tp, e_info_8168c_1); 2813 2814 __rtl_hw_start_8168cp(tp); 2815 } 2816 2817 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2818 { 2819 static const struct ephy_info e_info_8168c_2[] = { 2820 { 0x01, 0, 0x0001 }, 2821 { 0x03, 0x0400, 0x0020 } 2822 }; 2823 2824 rtl_set_def_aspm_entry_latency(tp); 2825 2826 rtl_ephy_init(tp, e_info_8168c_2); 2827 2828 __rtl_hw_start_8168cp(tp); 2829 } 2830 2831 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2832 { 2833 rtl_hw_start_8168c_2(tp); 2834 } 2835 2836 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2837 { 2838 rtl_set_def_aspm_entry_latency(tp); 2839 2840 __rtl_hw_start_8168cp(tp); 2841 } 2842 2843 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2844 { 2845 rtl_set_def_aspm_entry_latency(tp); 2846 2847 rtl_disable_clock_request(tp); 2848 } 2849 2850 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2851 { 2852 static const struct ephy_info e_info_8168d_4[] = { 2853 { 0x0b, 0x0000, 0x0048 }, 2854 { 0x19, 0x0020, 0x0050 }, 2855 { 0x0c, 0x0100, 0x0020 }, 2856 { 0x10, 0x0004, 0x0000 }, 2857 }; 2858 2859 rtl_set_def_aspm_entry_latency(tp); 2860 2861 rtl_ephy_init(tp, e_info_8168d_4); 2862 2863 rtl_enable_clock_request(tp); 2864 } 2865 2866 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2867 { 2868 static const struct ephy_info e_info_8168e_1[] = { 2869 { 0x00, 0x0200, 0x0100 }, 2870 { 0x00, 0x0000, 0x0004 }, 2871 { 0x06, 0x0002, 0x0001 }, 2872 { 0x06, 0x0000, 0x0030 }, 2873 { 0x07, 0x0000, 0x2000 }, 2874 { 0x00, 0x0000, 0x0020 }, 2875 { 0x03, 0x5800, 0x2000 }, 2876 { 0x03, 0x0000, 0x0001 }, 2877 { 0x01, 0x0800, 0x1000 }, 2878 { 0x07, 0x0000, 0x4000 }, 2879 { 0x1e, 0x0000, 0x2000 }, 2880 { 0x19, 0xffff, 0xfe6c }, 2881 { 0x0a, 0x0000, 0x0040 } 2882 }; 2883 2884 rtl_set_def_aspm_entry_latency(tp); 2885 2886 rtl_ephy_init(tp, e_info_8168e_1); 2887 2888 rtl_disable_clock_request(tp); 2889 2890 /* Reset tx FIFO pointer */ 2891 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2892 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2893 2894 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2895 } 2896 2897 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2898 { 2899 static const struct ephy_info e_info_8168e_2[] = { 2900 { 0x09, 0x0000, 0x0080 }, 2901 { 0x19, 0x0000, 0x0224 }, 2902 { 0x00, 0x0000, 0x0004 }, 2903 { 0x0c, 0x3df0, 0x0200 }, 2904 }; 2905 2906 rtl_set_def_aspm_entry_latency(tp); 2907 2908 rtl_ephy_init(tp, e_info_8168e_2); 2909 2910 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2911 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2912 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2913 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2914 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2915 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 2916 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 2917 2918 rtl_disable_clock_request(tp); 2919 2920 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2921 2922 rtl8168_config_eee_mac(tp); 2923 2924 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2925 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2926 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2927 2928 rtl_hw_aspm_clkreq_enable(tp, true); 2929 } 2930 2931 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2932 { 2933 rtl_set_def_aspm_entry_latency(tp); 2934 2935 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2936 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2937 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2938 rtl_reset_packet_filter(tp); 2939 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 2940 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 2941 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2942 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2943 2944 rtl_disable_clock_request(tp); 2945 2946 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2947 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2948 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2949 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2950 2951 rtl8168_config_eee_mac(tp); 2952 } 2953 2954 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2955 { 2956 static const struct ephy_info e_info_8168f_1[] = { 2957 { 0x06, 0x00c0, 0x0020 }, 2958 { 0x08, 0x0001, 0x0002 }, 2959 { 0x09, 0x0000, 0x0080 }, 2960 { 0x19, 0x0000, 0x0224 }, 2961 { 0x00, 0x0000, 0x0004 }, 2962 { 0x0c, 0x3df0, 0x0200 }, 2963 }; 2964 2965 rtl_hw_start_8168f(tp); 2966 2967 rtl_ephy_init(tp, e_info_8168f_1); 2968 2969 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 2970 } 2971 2972 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2973 { 2974 static const struct ephy_info e_info_8168f_1[] = { 2975 { 0x06, 0x00c0, 0x0020 }, 2976 { 0x0f, 0xffff, 0x5200 }, 2977 { 0x19, 0x0000, 0x0224 }, 2978 { 0x00, 0x0000, 0x0004 }, 2979 { 0x0c, 0x3df0, 0x0200 }, 2980 }; 2981 2982 rtl_hw_start_8168f(tp); 2983 rtl_pcie_state_l2l3_disable(tp); 2984 2985 rtl_ephy_init(tp, e_info_8168f_1); 2986 2987 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 2988 } 2989 2990 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2991 { 2992 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2993 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2994 2995 rtl_set_def_aspm_entry_latency(tp); 2996 2997 rtl_reset_packet_filter(tp); 2998 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2999 3000 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3001 3002 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3003 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3004 3005 rtl8168_config_eee_mac(tp); 3006 3007 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 3008 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3009 3010 rtl_pcie_state_l2l3_disable(tp); 3011 } 3012 3013 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3014 { 3015 static const struct ephy_info e_info_8168g_1[] = { 3016 { 0x00, 0x0008, 0x0000 }, 3017 { 0x0c, 0x3ff0, 0x0820 }, 3018 { 0x1e, 0x0000, 0x0001 }, 3019 { 0x19, 0x8000, 0x0000 } 3020 }; 3021 3022 rtl_hw_start_8168g(tp); 3023 3024 /* disable aspm and clock request before access ephy */ 3025 rtl_hw_aspm_clkreq_enable(tp, false); 3026 rtl_ephy_init(tp, e_info_8168g_1); 3027 rtl_hw_aspm_clkreq_enable(tp, true); 3028 } 3029 3030 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3031 { 3032 static const struct ephy_info e_info_8168g_2[] = { 3033 { 0x00, 0x0008, 0x0000 }, 3034 { 0x0c, 0x3ff0, 0x0820 }, 3035 { 0x19, 0xffff, 0x7c00 }, 3036 { 0x1e, 0xffff, 0x20eb }, 3037 { 0x0d, 0xffff, 0x1666 }, 3038 { 0x00, 0xffff, 0x10a3 }, 3039 { 0x06, 0xffff, 0xf050 }, 3040 { 0x04, 0x0000, 0x0010 }, 3041 { 0x1d, 0x4000, 0x0000 }, 3042 }; 3043 3044 rtl_hw_start_8168g(tp); 3045 3046 /* disable aspm and clock request before access ephy */ 3047 rtl_hw_aspm_clkreq_enable(tp, false); 3048 rtl_ephy_init(tp, e_info_8168g_2); 3049 } 3050 3051 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3052 { 3053 static const struct ephy_info e_info_8411_2[] = { 3054 { 0x00, 0x0008, 0x0000 }, 3055 { 0x0c, 0x37d0, 0x0820 }, 3056 { 0x1e, 0x0000, 0x0001 }, 3057 { 0x19, 0x8021, 0x0000 }, 3058 { 0x1e, 0x0000, 0x2000 }, 3059 { 0x0d, 0x0100, 0x0200 }, 3060 { 0x00, 0x0000, 0x0080 }, 3061 { 0x06, 0x0000, 0x0010 }, 3062 { 0x04, 0x0000, 0x0010 }, 3063 { 0x1d, 0x0000, 0x4000 }, 3064 }; 3065 3066 rtl_hw_start_8168g(tp); 3067 3068 /* disable aspm and clock request before access ephy */ 3069 rtl_hw_aspm_clkreq_enable(tp, false); 3070 rtl_ephy_init(tp, e_info_8411_2); 3071 3072 /* The following Realtek-provided magic fixes an issue with the RX unit 3073 * getting confused after the PHY having been powered-down. 3074 */ 3075 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3076 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3077 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3078 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3079 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3080 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3081 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3082 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3083 mdelay(3); 3084 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3085 3086 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3087 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3088 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3089 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3090 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3091 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3092 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3093 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3094 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3095 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3096 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3097 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3098 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3099 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3100 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3101 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3102 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3103 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3104 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3105 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3106 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3107 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3108 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3109 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3110 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3111 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3112 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3113 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3114 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3115 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3116 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3117 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3118 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3119 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3120 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3121 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3122 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3123 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3124 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3125 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3126 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3127 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3128 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3129 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3130 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3131 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3132 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3133 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3134 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3135 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3136 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3137 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3138 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3139 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3140 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3141 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3142 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3143 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3144 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3145 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3146 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3147 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3148 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3149 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3150 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3151 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3152 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3153 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3154 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3155 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3156 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3157 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3158 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3159 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3160 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3161 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3162 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3163 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3164 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3165 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3166 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3167 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3168 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3169 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3170 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3171 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3172 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3173 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3174 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3175 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3176 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3177 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3178 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3179 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3180 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3181 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3182 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3183 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3184 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3185 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3186 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3187 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3188 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3189 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3190 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3191 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3192 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3193 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3194 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3195 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3196 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3197 3198 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3199 3200 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3201 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3202 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3203 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3204 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3205 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3206 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3207 3208 rtl_hw_aspm_clkreq_enable(tp, true); 3209 } 3210 3211 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3212 { 3213 static const struct ephy_info e_info_8168h_1[] = { 3214 { 0x1e, 0x0800, 0x0001 }, 3215 { 0x1d, 0x0000, 0x0800 }, 3216 { 0x05, 0xffff, 0x2089 }, 3217 { 0x06, 0xffff, 0x5881 }, 3218 { 0x04, 0xffff, 0x854a }, 3219 { 0x01, 0xffff, 0x068b } 3220 }; 3221 int rg_saw_cnt; 3222 3223 /* disable aspm and clock request before access ephy */ 3224 rtl_hw_aspm_clkreq_enable(tp, false); 3225 rtl_ephy_init(tp, e_info_8168h_1); 3226 3227 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3228 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3229 3230 rtl_set_def_aspm_entry_latency(tp); 3231 3232 rtl_reset_packet_filter(tp); 3233 3234 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 3235 3236 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 3237 3238 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3239 3240 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3241 3242 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3243 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3244 3245 rtl8168_config_eee_mac(tp); 3246 3247 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3248 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3249 3250 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3251 3252 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3253 3254 rtl_pcie_state_l2l3_disable(tp); 3255 3256 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3257 if (rg_saw_cnt > 0) { 3258 u16 sw_cnt_1ms_ini; 3259 3260 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3261 sw_cnt_1ms_ini &= 0x0fff; 3262 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3263 } 3264 3265 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3266 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3267 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3268 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3269 3270 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3271 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3272 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3273 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3274 3275 rtl_hw_aspm_clkreq_enable(tp, true); 3276 } 3277 3278 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3279 { 3280 rtl8168ep_stop_cmac(tp); 3281 3282 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3283 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3284 3285 rtl_set_def_aspm_entry_latency(tp); 3286 3287 rtl_reset_packet_filter(tp); 3288 3289 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 3290 3291 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3292 3293 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3294 3295 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3296 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3297 3298 rtl8168_config_eee_mac(tp); 3299 3300 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 3301 3302 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3303 3304 rtl_pcie_state_l2l3_disable(tp); 3305 } 3306 3307 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3308 { 3309 static const struct ephy_info e_info_8168ep_1[] = { 3310 { 0x00, 0xffff, 0x10ab }, 3311 { 0x06, 0xffff, 0xf030 }, 3312 { 0x08, 0xffff, 0x2006 }, 3313 { 0x0d, 0xffff, 0x1666 }, 3314 { 0x0c, 0x3ff0, 0x0000 } 3315 }; 3316 3317 /* disable aspm and clock request before access ephy */ 3318 rtl_hw_aspm_clkreq_enable(tp, false); 3319 rtl_ephy_init(tp, e_info_8168ep_1); 3320 3321 rtl_hw_start_8168ep(tp); 3322 3323 rtl_hw_aspm_clkreq_enable(tp, true); 3324 } 3325 3326 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3327 { 3328 static const struct ephy_info e_info_8168ep_2[] = { 3329 { 0x00, 0xffff, 0x10a3 }, 3330 { 0x19, 0xffff, 0xfc00 }, 3331 { 0x1e, 0xffff, 0x20ea } 3332 }; 3333 3334 /* disable aspm and clock request before access ephy */ 3335 rtl_hw_aspm_clkreq_enable(tp, false); 3336 rtl_ephy_init(tp, e_info_8168ep_2); 3337 3338 rtl_hw_start_8168ep(tp); 3339 3340 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3341 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3342 3343 rtl_hw_aspm_clkreq_enable(tp, true); 3344 } 3345 3346 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3347 { 3348 static const struct ephy_info e_info_8168ep_3[] = { 3349 { 0x00, 0x0000, 0x0080 }, 3350 { 0x0d, 0x0100, 0x0200 }, 3351 { 0x19, 0x8021, 0x0000 }, 3352 { 0x1e, 0x0000, 0x2000 }, 3353 }; 3354 3355 /* disable aspm and clock request before access ephy */ 3356 rtl_hw_aspm_clkreq_enable(tp, false); 3357 rtl_ephy_init(tp, e_info_8168ep_3); 3358 3359 rtl_hw_start_8168ep(tp); 3360 3361 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3362 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3363 3364 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3365 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3366 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3367 3368 rtl_hw_aspm_clkreq_enable(tp, true); 3369 } 3370 3371 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3372 { 3373 static const struct ephy_info e_info_8117[] = { 3374 { 0x19, 0x0040, 0x1100 }, 3375 { 0x59, 0x0040, 0x1100 }, 3376 }; 3377 int rg_saw_cnt; 3378 3379 rtl8168ep_stop_cmac(tp); 3380 3381 /* disable aspm and clock request before access ephy */ 3382 rtl_hw_aspm_clkreq_enable(tp, false); 3383 rtl_ephy_init(tp, e_info_8117); 3384 3385 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3386 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3387 3388 rtl_set_def_aspm_entry_latency(tp); 3389 3390 rtl_reset_packet_filter(tp); 3391 3392 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90); 3393 3394 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3395 3396 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3397 3398 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3399 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3400 3401 rtl8168_config_eee_mac(tp); 3402 3403 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3404 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3405 3406 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3407 3408 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3409 3410 rtl_pcie_state_l2l3_disable(tp); 3411 3412 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3413 if (rg_saw_cnt > 0) { 3414 u16 sw_cnt_1ms_ini; 3415 3416 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3417 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3418 } 3419 3420 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3421 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3422 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3423 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3424 3425 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3426 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3427 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3428 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3429 3430 /* firmware is for MAC only */ 3431 r8169_apply_firmware(tp); 3432 3433 rtl_hw_aspm_clkreq_enable(tp, true); 3434 } 3435 3436 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3437 { 3438 static const struct ephy_info e_info_8102e_1[] = { 3439 { 0x01, 0, 0x6e65 }, 3440 { 0x02, 0, 0x091f }, 3441 { 0x03, 0, 0xc2f9 }, 3442 { 0x06, 0, 0xafb5 }, 3443 { 0x07, 0, 0x0e00 }, 3444 { 0x19, 0, 0xec80 }, 3445 { 0x01, 0, 0x2e65 }, 3446 { 0x01, 0, 0x6e65 } 3447 }; 3448 u8 cfg1; 3449 3450 rtl_set_def_aspm_entry_latency(tp); 3451 3452 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3453 3454 RTL_W8(tp, Config1, 3455 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3456 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3457 3458 cfg1 = RTL_R8(tp, Config1); 3459 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3460 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3461 3462 rtl_ephy_init(tp, e_info_8102e_1); 3463 } 3464 3465 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3466 { 3467 rtl_set_def_aspm_entry_latency(tp); 3468 3469 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3470 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3471 } 3472 3473 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3474 { 3475 rtl_hw_start_8102e_2(tp); 3476 3477 rtl_ephy_write(tp, 0x03, 0xc2f9); 3478 } 3479 3480 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3481 { 3482 static const struct ephy_info e_info_8105e_1[] = { 3483 { 0x07, 0, 0x4000 }, 3484 { 0x19, 0, 0x0200 }, 3485 { 0x19, 0, 0x0020 }, 3486 { 0x1e, 0, 0x2000 }, 3487 { 0x03, 0, 0x0001 }, 3488 { 0x19, 0, 0x0100 }, 3489 { 0x19, 0, 0x0004 }, 3490 { 0x0a, 0, 0x0020 } 3491 }; 3492 3493 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3494 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3495 3496 /* Disable Early Tally Counter */ 3497 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3498 3499 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3500 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3501 3502 rtl_ephy_init(tp, e_info_8105e_1); 3503 3504 rtl_pcie_state_l2l3_disable(tp); 3505 } 3506 3507 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3508 { 3509 rtl_hw_start_8105e_1(tp); 3510 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3511 } 3512 3513 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3514 { 3515 static const struct ephy_info e_info_8402[] = { 3516 { 0x19, 0xffff, 0xff64 }, 3517 { 0x1e, 0, 0x4000 } 3518 }; 3519 3520 rtl_set_def_aspm_entry_latency(tp); 3521 3522 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3523 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3524 3525 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3526 3527 rtl_ephy_init(tp, e_info_8402); 3528 3529 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3530 rtl_reset_packet_filter(tp); 3531 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3532 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3533 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 3534 3535 /* disable EEE */ 3536 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3537 3538 rtl_pcie_state_l2l3_disable(tp); 3539 } 3540 3541 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3542 { 3543 rtl_hw_aspm_clkreq_enable(tp, false); 3544 3545 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3546 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3547 3548 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3549 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3550 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3551 3552 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3553 3554 /* disable EEE */ 3555 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3556 3557 rtl_pcie_state_l2l3_disable(tp); 3558 rtl_hw_aspm_clkreq_enable(tp, true); 3559 } 3560 3561 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3562 { 3563 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3564 } 3565 3566 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3567 { 3568 rtl_pcie_state_l2l3_disable(tp); 3569 3570 RTL_W16(tp, 0x382, 0x221b); 3571 RTL_W8(tp, 0x4500, 0); 3572 RTL_W16(tp, 0x4800, 0); 3573 3574 /* disable UPS */ 3575 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3576 3577 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3578 3579 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3580 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3581 3582 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3583 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3584 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3585 3586 /* disable new tx descriptor format */ 3587 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3588 3589 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3590 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3591 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3592 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3593 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3594 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3595 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3596 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3597 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 3598 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3599 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3600 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 3601 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3602 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3603 udelay(1); 3604 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3605 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3606 3607 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3608 3609 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3610 3611 rtl8125_config_eee_mac(tp); 3612 3613 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3614 udelay(10); 3615 } 3616 3617 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 3618 { 3619 static const struct ephy_info e_info_8125_1[] = { 3620 { 0x01, 0xffff, 0xa812 }, 3621 { 0x09, 0xffff, 0x520c }, 3622 { 0x04, 0xffff, 0xd000 }, 3623 { 0x0d, 0xffff, 0xf702 }, 3624 { 0x0a, 0xffff, 0x8653 }, 3625 { 0x06, 0xffff, 0x001e }, 3626 { 0x08, 0xffff, 0x3595 }, 3627 { 0x20, 0xffff, 0x9455 }, 3628 { 0x21, 0xffff, 0x99ff }, 3629 { 0x02, 0xffff, 0x6046 }, 3630 { 0x29, 0xffff, 0xfe00 }, 3631 { 0x23, 0xffff, 0xab62 }, 3632 3633 { 0x41, 0xffff, 0xa80c }, 3634 { 0x49, 0xffff, 0x520c }, 3635 { 0x44, 0xffff, 0xd000 }, 3636 { 0x4d, 0xffff, 0xf702 }, 3637 { 0x4a, 0xffff, 0x8653 }, 3638 { 0x46, 0xffff, 0x001e }, 3639 { 0x48, 0xffff, 0x3595 }, 3640 { 0x60, 0xffff, 0x9455 }, 3641 { 0x61, 0xffff, 0x99ff }, 3642 { 0x42, 0xffff, 0x6046 }, 3643 { 0x69, 0xffff, 0xfe00 }, 3644 { 0x63, 0xffff, 0xab62 }, 3645 }; 3646 3647 rtl_set_def_aspm_entry_latency(tp); 3648 3649 /* disable aspm and clock request before access ephy */ 3650 rtl_hw_aspm_clkreq_enable(tp, false); 3651 rtl_ephy_init(tp, e_info_8125_1); 3652 3653 rtl_hw_start_8125_common(tp); 3654 } 3655 3656 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 3657 { 3658 static const struct ephy_info e_info_8125_2[] = { 3659 { 0x04, 0xffff, 0xd000 }, 3660 { 0x0a, 0xffff, 0x8653 }, 3661 { 0x23, 0xffff, 0xab66 }, 3662 { 0x20, 0xffff, 0x9455 }, 3663 { 0x21, 0xffff, 0x99ff }, 3664 { 0x29, 0xffff, 0xfe04 }, 3665 3666 { 0x44, 0xffff, 0xd000 }, 3667 { 0x4a, 0xffff, 0x8653 }, 3668 { 0x63, 0xffff, 0xab66 }, 3669 { 0x60, 0xffff, 0x9455 }, 3670 { 0x61, 0xffff, 0x99ff }, 3671 { 0x69, 0xffff, 0xfe04 }, 3672 }; 3673 3674 rtl_set_def_aspm_entry_latency(tp); 3675 3676 /* disable aspm and clock request before access ephy */ 3677 rtl_hw_aspm_clkreq_enable(tp, false); 3678 rtl_ephy_init(tp, e_info_8125_2); 3679 3680 rtl_hw_start_8125_common(tp); 3681 } 3682 3683 static void rtl_hw_config(struct rtl8169_private *tp) 3684 { 3685 static const rtl_generic_fct hw_configs[] = { 3686 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3687 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3688 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3689 [RTL_GIGA_MAC_VER_10] = NULL, 3690 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3691 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3692 [RTL_GIGA_MAC_VER_13] = NULL, 3693 [RTL_GIGA_MAC_VER_14] = NULL, 3694 [RTL_GIGA_MAC_VER_15] = NULL, 3695 [RTL_GIGA_MAC_VER_16] = NULL, 3696 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3697 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3698 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3699 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3700 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3701 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3702 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3703 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3704 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3705 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3706 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3707 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3708 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3709 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3710 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3711 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3712 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3713 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3714 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3715 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3716 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3717 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3718 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3719 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3720 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3721 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3722 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3723 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3724 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3725 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3726 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3727 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3728 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3729 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3730 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3731 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3732 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 3733 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 3734 }; 3735 3736 if (hw_configs[tp->mac_version]) 3737 hw_configs[tp->mac_version](tp); 3738 } 3739 3740 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3741 { 3742 int i; 3743 3744 /* disable interrupt coalescing */ 3745 for (i = 0xa00; i < 0xb00; i += 4) 3746 RTL_W32(tp, i, 0); 3747 3748 rtl_hw_config(tp); 3749 } 3750 3751 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3752 { 3753 if (rtl_is_8168evl_up(tp)) 3754 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3755 else 3756 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3757 3758 rtl_hw_config(tp); 3759 3760 /* disable interrupt coalescing */ 3761 RTL_W16(tp, IntrMitigate, 0x0000); 3762 } 3763 3764 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3765 { 3766 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3767 3768 tp->cp_cmd |= PCIMulRW; 3769 3770 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3771 tp->mac_version == RTL_GIGA_MAC_VER_03) 3772 tp->cp_cmd |= EnAnaPLL; 3773 3774 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3775 3776 rtl8169_set_magic_reg(tp); 3777 3778 /* disable interrupt coalescing */ 3779 RTL_W16(tp, IntrMitigate, 0x0000); 3780 } 3781 3782 static void rtl_hw_start(struct rtl8169_private *tp) 3783 { 3784 rtl_unlock_config_regs(tp); 3785 3786 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3787 3788 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3789 rtl_hw_start_8169(tp); 3790 else if (rtl_is_8125(tp)) 3791 rtl_hw_start_8125(tp); 3792 else 3793 rtl_hw_start_8168(tp); 3794 3795 rtl_set_rx_max_size(tp); 3796 rtl_set_rx_tx_desc_registers(tp); 3797 rtl_lock_config_regs(tp); 3798 3799 rtl_jumbo_config(tp); 3800 3801 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3802 rtl_pci_commit(tp); 3803 3804 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3805 rtl_init_rxcfg(tp); 3806 rtl_set_tx_config_registers(tp); 3807 rtl_set_rx_config_features(tp, tp->dev->features); 3808 rtl_set_rx_mode(tp->dev); 3809 rtl_irq_enable(tp); 3810 } 3811 3812 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3813 { 3814 struct rtl8169_private *tp = netdev_priv(dev); 3815 3816 dev->mtu = new_mtu; 3817 netdev_update_features(dev); 3818 rtl_jumbo_config(tp); 3819 3820 return 0; 3821 } 3822 3823 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 3824 { 3825 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3826 3827 desc->opts2 = 0; 3828 /* Force memory writes to complete before releasing descriptor */ 3829 dma_wmb(); 3830 3831 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 3832 } 3833 3834 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3835 struct RxDesc *desc) 3836 { 3837 struct device *d = tp_to_dev(tp); 3838 int node = dev_to_node(d); 3839 dma_addr_t mapping; 3840 struct page *data; 3841 3842 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3843 if (!data) 3844 return NULL; 3845 3846 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3847 if (unlikely(dma_mapping_error(d, mapping))) { 3848 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3849 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3850 return NULL; 3851 } 3852 3853 desc->addr = cpu_to_le64(mapping); 3854 rtl8169_mark_to_asic(desc); 3855 3856 return data; 3857 } 3858 3859 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3860 { 3861 unsigned int i; 3862 3863 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3864 dma_unmap_page(tp_to_dev(tp), 3865 le64_to_cpu(tp->RxDescArray[i].addr), 3866 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3867 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3868 tp->Rx_databuff[i] = NULL; 3869 tp->RxDescArray[i].addr = 0; 3870 tp->RxDescArray[i].opts1 = 0; 3871 } 3872 } 3873 3874 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3875 { 3876 unsigned int i; 3877 3878 for (i = 0; i < NUM_RX_DESC; i++) { 3879 struct page *data; 3880 3881 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3882 if (!data) { 3883 rtl8169_rx_clear(tp); 3884 return -ENOMEM; 3885 } 3886 tp->Rx_databuff[i] = data; 3887 } 3888 3889 /* mark as last descriptor in the ring */ 3890 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3891 3892 return 0; 3893 } 3894 3895 static int rtl8169_init_ring(struct rtl8169_private *tp) 3896 { 3897 rtl8169_init_ring_indexes(tp); 3898 3899 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3900 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3901 3902 return rtl8169_rx_fill(tp); 3903 } 3904 3905 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3906 { 3907 struct ring_info *tx_skb = tp->tx_skb + entry; 3908 struct TxDesc *desc = tp->TxDescArray + entry; 3909 3910 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3911 DMA_TO_DEVICE); 3912 memset(desc, 0, sizeof(*desc)); 3913 memset(tx_skb, 0, sizeof(*tx_skb)); 3914 } 3915 3916 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3917 unsigned int n) 3918 { 3919 unsigned int i; 3920 3921 for (i = 0; i < n; i++) { 3922 unsigned int entry = (start + i) % NUM_TX_DESC; 3923 struct ring_info *tx_skb = tp->tx_skb + entry; 3924 unsigned int len = tx_skb->len; 3925 3926 if (len) { 3927 struct sk_buff *skb = tx_skb->skb; 3928 3929 rtl8169_unmap_tx_skb(tp, entry); 3930 if (skb) 3931 dev_consume_skb_any(skb); 3932 } 3933 } 3934 } 3935 3936 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3937 { 3938 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3939 tp->cur_tx = tp->dirty_tx = 0; 3940 netdev_reset_queue(tp->dev); 3941 } 3942 3943 static void rtl_reset_work(struct rtl8169_private *tp) 3944 { 3945 struct net_device *dev = tp->dev; 3946 int i; 3947 3948 napi_disable(&tp->napi); 3949 netif_stop_queue(dev); 3950 synchronize_rcu(); 3951 3952 rtl8169_hw_reset(tp); 3953 3954 for (i = 0; i < NUM_RX_DESC; i++) 3955 rtl8169_mark_to_asic(tp->RxDescArray + i); 3956 3957 rtl8169_tx_clear(tp); 3958 rtl8169_init_ring_indexes(tp); 3959 3960 napi_enable(&tp->napi); 3961 rtl_hw_start(tp); 3962 netif_wake_queue(dev); 3963 } 3964 3965 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3966 { 3967 struct rtl8169_private *tp = netdev_priv(dev); 3968 3969 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3970 } 3971 3972 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3973 void *addr, unsigned int entry, bool desc_own) 3974 { 3975 struct TxDesc *txd = tp->TxDescArray + entry; 3976 struct device *d = tp_to_dev(tp); 3977 dma_addr_t mapping; 3978 u32 opts1; 3979 int ret; 3980 3981 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3982 ret = dma_mapping_error(d, mapping); 3983 if (unlikely(ret)) { 3984 if (net_ratelimit()) 3985 netdev_err(tp->dev, "Failed to map TX data!\n"); 3986 return ret; 3987 } 3988 3989 txd->addr = cpu_to_le64(mapping); 3990 txd->opts2 = cpu_to_le32(opts[1]); 3991 3992 opts1 = opts[0] | len; 3993 if (entry == NUM_TX_DESC - 1) 3994 opts1 |= RingEnd; 3995 if (desc_own) 3996 opts1 |= DescOwn; 3997 txd->opts1 = cpu_to_le32(opts1); 3998 3999 tp->tx_skb[entry].len = len; 4000 4001 return 0; 4002 } 4003 4004 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4005 const u32 *opts, unsigned int entry) 4006 { 4007 struct skb_shared_info *info = skb_shinfo(skb); 4008 unsigned int cur_frag; 4009 4010 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4011 const skb_frag_t *frag = info->frags + cur_frag; 4012 void *addr = skb_frag_address(frag); 4013 u32 len = skb_frag_size(frag); 4014 4015 entry = (entry + 1) % NUM_TX_DESC; 4016 4017 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4018 goto err_out; 4019 } 4020 4021 return 0; 4022 4023 err_out: 4024 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4025 return -EIO; 4026 } 4027 4028 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 4029 { 4030 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 4031 } 4032 4033 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4034 { 4035 u32 mss = skb_shinfo(skb)->gso_size; 4036 4037 if (mss) { 4038 opts[0] |= TD_LSO; 4039 opts[0] |= mss << TD0_MSS_SHIFT; 4040 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4041 const struct iphdr *ip = ip_hdr(skb); 4042 4043 if (ip->protocol == IPPROTO_TCP) 4044 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4045 else if (ip->protocol == IPPROTO_UDP) 4046 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4047 else 4048 WARN_ON_ONCE(1); 4049 } 4050 } 4051 4052 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4053 struct sk_buff *skb, u32 *opts) 4054 { 4055 u32 transport_offset = (u32)skb_transport_offset(skb); 4056 struct skb_shared_info *shinfo = skb_shinfo(skb); 4057 u32 mss = shinfo->gso_size; 4058 4059 if (mss) { 4060 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4061 opts[0] |= TD1_GTSENV4; 4062 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4063 if (skb_cow_head(skb, 0)) 4064 return false; 4065 4066 tcp_v6_gso_csum_prep(skb); 4067 opts[0] |= TD1_GTSENV6; 4068 } else { 4069 WARN_ON_ONCE(1); 4070 } 4071 4072 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4073 opts[1] |= mss << TD1_MSS_SHIFT; 4074 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4075 u8 ip_protocol; 4076 4077 switch (vlan_get_protocol(skb)) { 4078 case htons(ETH_P_IP): 4079 opts[1] |= TD1_IPv4_CS; 4080 ip_protocol = ip_hdr(skb)->protocol; 4081 break; 4082 4083 case htons(ETH_P_IPV6): 4084 opts[1] |= TD1_IPv6_CS; 4085 ip_protocol = ipv6_hdr(skb)->nexthdr; 4086 break; 4087 4088 default: 4089 ip_protocol = IPPROTO_RAW; 4090 break; 4091 } 4092 4093 if (ip_protocol == IPPROTO_TCP) 4094 opts[1] |= TD1_TCP_CS; 4095 else if (ip_protocol == IPPROTO_UDP) 4096 opts[1] |= TD1_UDP_CS; 4097 else 4098 WARN_ON_ONCE(1); 4099 4100 opts[1] |= transport_offset << TCPHO_SHIFT; 4101 } else { 4102 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 4103 return !eth_skb_pad(skb); 4104 } 4105 4106 return true; 4107 } 4108 4109 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 4110 unsigned int nr_frags) 4111 { 4112 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 4113 4114 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4115 return slots_avail > nr_frags; 4116 } 4117 4118 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4119 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4120 { 4121 switch (tp->mac_version) { 4122 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4123 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4124 return false; 4125 default: 4126 return true; 4127 } 4128 } 4129 4130 static void rtl8169_doorbell(struct rtl8169_private *tp) 4131 { 4132 if (rtl_is_8125(tp)) 4133 RTL_W16(tp, TxPoll_8125, BIT(0)); 4134 else 4135 RTL_W8(tp, TxPoll, NPQ); 4136 } 4137 4138 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4139 struct net_device *dev) 4140 { 4141 unsigned int frags = skb_shinfo(skb)->nr_frags; 4142 struct rtl8169_private *tp = netdev_priv(dev); 4143 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4144 struct TxDesc *txd_first, *txd_last; 4145 bool stop_queue, door_bell; 4146 u32 opts[2]; 4147 4148 txd_first = tp->TxDescArray + entry; 4149 4150 if (unlikely(!rtl_tx_slots_avail(tp, frags))) { 4151 if (net_ratelimit()) 4152 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4153 goto err_stop_0; 4154 } 4155 4156 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn)) 4157 goto err_stop_0; 4158 4159 opts[1] = rtl8169_tx_vlan_tag(skb); 4160 opts[0] = 0; 4161 4162 if (!rtl_chip_supports_csum_v2(tp)) 4163 rtl8169_tso_csum_v1(skb, opts); 4164 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4165 goto err_dma_0; 4166 4167 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4168 entry, false))) 4169 goto err_dma_0; 4170 4171 if (frags) { 4172 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4173 goto err_dma_1; 4174 entry = (entry + frags) % NUM_TX_DESC; 4175 } 4176 4177 txd_last = tp->TxDescArray + entry; 4178 txd_last->opts1 |= cpu_to_le32(LastFrag); 4179 tp->tx_skb[entry].skb = skb; 4180 4181 skb_tx_timestamp(skb); 4182 4183 /* Force memory writes to complete before releasing descriptor */ 4184 dma_wmb(); 4185 4186 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4187 4188 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4189 4190 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4191 smp_wmb(); 4192 4193 tp->cur_tx += frags + 1; 4194 4195 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 4196 if (unlikely(stop_queue)) { 4197 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4198 * not miss a ring update when it notices a stopped queue. 4199 */ 4200 smp_wmb(); 4201 netif_stop_queue(dev); 4202 door_bell = true; 4203 } 4204 4205 if (door_bell) 4206 rtl8169_doorbell(tp); 4207 4208 if (unlikely(stop_queue)) { 4209 /* Sync with rtl_tx: 4210 * - publish queue status and cur_tx ring index (write barrier) 4211 * - refresh dirty_tx ring index (read barrier). 4212 * May the current thread have a pessimistic view of the ring 4213 * status and forget to wake up queue, a racing rtl_tx thread 4214 * can't. 4215 */ 4216 smp_mb(); 4217 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 4218 netif_start_queue(dev); 4219 } 4220 4221 return NETDEV_TX_OK; 4222 4223 err_dma_1: 4224 rtl8169_unmap_tx_skb(tp, entry); 4225 err_dma_0: 4226 dev_kfree_skb_any(skb); 4227 dev->stats.tx_dropped++; 4228 return NETDEV_TX_OK; 4229 4230 err_stop_0: 4231 netif_stop_queue(dev); 4232 dev->stats.tx_dropped++; 4233 return NETDEV_TX_BUSY; 4234 } 4235 4236 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4237 { 4238 struct skb_shared_info *info = skb_shinfo(skb); 4239 unsigned int nr_frags = info->nr_frags; 4240 4241 if (!nr_frags) 4242 return UINT_MAX; 4243 4244 return skb_frag_size(info->frags + nr_frags - 1); 4245 } 4246 4247 /* Workaround for hw issues with TSO on RTL8168evl */ 4248 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4249 netdev_features_t features) 4250 { 4251 /* IPv4 header has options field */ 4252 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4253 ip_hdrlen(skb) > sizeof(struct iphdr)) 4254 features &= ~NETIF_F_ALL_TSO; 4255 4256 /* IPv4 TCP header has options field */ 4257 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4258 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4259 features &= ~NETIF_F_ALL_TSO; 4260 4261 else if (rtl_last_frag_len(skb) <= 6) 4262 features &= ~NETIF_F_ALL_TSO; 4263 4264 return features; 4265 } 4266 4267 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4268 struct net_device *dev, 4269 netdev_features_t features) 4270 { 4271 int transport_offset = skb_transport_offset(skb); 4272 struct rtl8169_private *tp = netdev_priv(dev); 4273 4274 if (skb_is_gso(skb)) { 4275 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4276 features = rtl8168evl_fix_tso(skb, features); 4277 4278 if (transport_offset > GTTCPHO_MAX && 4279 rtl_chip_supports_csum_v2(tp)) 4280 features &= ~NETIF_F_ALL_TSO; 4281 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4282 if (skb->len < ETH_ZLEN) { 4283 switch (tp->mac_version) { 4284 case RTL_GIGA_MAC_VER_11: 4285 case RTL_GIGA_MAC_VER_12: 4286 case RTL_GIGA_MAC_VER_17: 4287 case RTL_GIGA_MAC_VER_34: 4288 features &= ~NETIF_F_CSUM_MASK; 4289 break; 4290 default: 4291 break; 4292 } 4293 } 4294 4295 if (transport_offset > TCPHO_MAX && 4296 rtl_chip_supports_csum_v2(tp)) 4297 features &= ~NETIF_F_CSUM_MASK; 4298 } 4299 4300 return vlan_features_check(skb, features); 4301 } 4302 4303 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4304 { 4305 struct rtl8169_private *tp = netdev_priv(dev); 4306 struct pci_dev *pdev = tp->pci_dev; 4307 int pci_status_errs; 4308 u16 pci_cmd; 4309 4310 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4311 4312 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4313 4314 if (net_ratelimit()) 4315 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4316 pci_cmd, pci_status_errs); 4317 /* 4318 * The recovery sequence below admits a very elaborated explanation: 4319 * - it seems to work; 4320 * - I did not see what else could be done; 4321 * - it makes iop3xx happy. 4322 * 4323 * Feel free to adjust to your needs. 4324 */ 4325 if (pdev->broken_parity_status) 4326 pci_cmd &= ~PCI_COMMAND_PARITY; 4327 else 4328 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4329 4330 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4331 4332 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4333 } 4334 4335 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4336 int budget) 4337 { 4338 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 4339 4340 dirty_tx = tp->dirty_tx; 4341 smp_rmb(); 4342 4343 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) { 4344 unsigned int entry = dirty_tx % NUM_TX_DESC; 4345 struct sk_buff *skb = tp->tx_skb[entry].skb; 4346 u32 status; 4347 4348 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4349 if (status & DescOwn) 4350 break; 4351 4352 rtl8169_unmap_tx_skb(tp, entry); 4353 4354 if (skb) { 4355 pkts_compl++; 4356 bytes_compl += skb->len; 4357 napi_consume_skb(skb, budget); 4358 } 4359 dirty_tx++; 4360 } 4361 4362 if (tp->dirty_tx != dirty_tx) { 4363 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4364 4365 u64_stats_update_begin(&tp->tx_stats.syncp); 4366 tp->tx_stats.packets += pkts_compl; 4367 tp->tx_stats.bytes += bytes_compl; 4368 u64_stats_update_end(&tp->tx_stats.syncp); 4369 4370 tp->dirty_tx = dirty_tx; 4371 /* Sync with rtl8169_start_xmit: 4372 * - publish dirty_tx ring index (write barrier) 4373 * - refresh cur_tx ring index and queue status (read barrier) 4374 * May the current thread miss the stopped queue condition, 4375 * a racing xmit thread can only have a right view of the 4376 * ring status. 4377 */ 4378 smp_mb(); 4379 if (netif_queue_stopped(dev) && 4380 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 4381 netif_wake_queue(dev); 4382 } 4383 /* 4384 * 8168 hack: TxPoll requests are lost when the Tx packets are 4385 * too close. Let's kick an extra TxPoll request when a burst 4386 * of start_xmit activity is detected (if it is not detected, 4387 * it is slow enough). -- FR 4388 */ 4389 if (tp->cur_tx != dirty_tx) 4390 rtl8169_doorbell(tp); 4391 } 4392 } 4393 4394 static inline int rtl8169_fragmented_frame(u32 status) 4395 { 4396 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4397 } 4398 4399 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4400 { 4401 u32 status = opts1 & RxProtoMask; 4402 4403 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4404 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 4405 skb->ip_summed = CHECKSUM_UNNECESSARY; 4406 else 4407 skb_checksum_none_assert(skb); 4408 } 4409 4410 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 4411 { 4412 unsigned int cur_rx, rx_left; 4413 unsigned int count; 4414 4415 cur_rx = tp->cur_rx; 4416 4417 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 4418 unsigned int entry = cur_rx % NUM_RX_DESC; 4419 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 4420 struct RxDesc *desc = tp->RxDescArray + entry; 4421 u32 status; 4422 4423 status = le32_to_cpu(desc->opts1); 4424 if (status & DescOwn) 4425 break; 4426 4427 /* This barrier is needed to keep us from reading 4428 * any other fields out of the Rx descriptor until 4429 * we know the status of DescOwn 4430 */ 4431 dma_rmb(); 4432 4433 if (unlikely(status & RxRES)) { 4434 if (net_ratelimit()) 4435 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4436 status); 4437 dev->stats.rx_errors++; 4438 if (status & (RxRWT | RxRUNT)) 4439 dev->stats.rx_length_errors++; 4440 if (status & RxCRC) 4441 dev->stats.rx_crc_errors++; 4442 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 4443 dev->features & NETIF_F_RXALL) { 4444 goto process_pkt; 4445 } 4446 } else { 4447 unsigned int pkt_size; 4448 struct sk_buff *skb; 4449 4450 process_pkt: 4451 pkt_size = status & GENMASK(13, 0); 4452 if (likely(!(dev->features & NETIF_F_RXFCS))) 4453 pkt_size -= ETH_FCS_LEN; 4454 /* 4455 * The driver does not support incoming fragmented 4456 * frames. They are seen as a symptom of over-mtu 4457 * sized frames. 4458 */ 4459 if (unlikely(rtl8169_fragmented_frame(status))) { 4460 dev->stats.rx_dropped++; 4461 dev->stats.rx_length_errors++; 4462 goto release_descriptor; 4463 } 4464 4465 skb = napi_alloc_skb(&tp->napi, pkt_size); 4466 if (unlikely(!skb)) { 4467 dev->stats.rx_dropped++; 4468 goto release_descriptor; 4469 } 4470 4471 dma_sync_single_for_cpu(tp_to_dev(tp), 4472 le64_to_cpu(desc->addr), 4473 pkt_size, DMA_FROM_DEVICE); 4474 prefetch(rx_buf); 4475 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4476 skb->tail += pkt_size; 4477 skb->len = pkt_size; 4478 4479 dma_sync_single_for_device(tp_to_dev(tp), 4480 le64_to_cpu(desc->addr), 4481 pkt_size, DMA_FROM_DEVICE); 4482 4483 rtl8169_rx_csum(skb, status); 4484 skb->protocol = eth_type_trans(skb, dev); 4485 4486 rtl8169_rx_vlan_tag(desc, skb); 4487 4488 if (skb->pkt_type == PACKET_MULTICAST) 4489 dev->stats.multicast++; 4490 4491 napi_gro_receive(&tp->napi, skb); 4492 4493 u64_stats_update_begin(&tp->rx_stats.syncp); 4494 tp->rx_stats.packets++; 4495 tp->rx_stats.bytes += pkt_size; 4496 u64_stats_update_end(&tp->rx_stats.syncp); 4497 } 4498 release_descriptor: 4499 rtl8169_mark_to_asic(desc); 4500 } 4501 4502 count = cur_rx - tp->cur_rx; 4503 tp->cur_rx = cur_rx; 4504 4505 return count; 4506 } 4507 4508 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4509 { 4510 struct rtl8169_private *tp = dev_instance; 4511 u32 status = rtl_get_events(tp); 4512 4513 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 4514 !(status & tp->irq_mask)) 4515 return IRQ_NONE; 4516 4517 if (unlikely(status & SYSErr)) { 4518 rtl8169_pcierr_interrupt(tp->dev); 4519 goto out; 4520 } 4521 4522 if (status & LinkChg) 4523 phy_mac_interrupt(tp->phydev); 4524 4525 if (unlikely(status & RxFIFOOver && 4526 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4527 netif_stop_queue(tp->dev); 4528 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4529 } 4530 4531 rtl_irq_disable(tp); 4532 napi_schedule_irqoff(&tp->napi); 4533 out: 4534 rtl_ack_events(tp, status); 4535 4536 return IRQ_HANDLED; 4537 } 4538 4539 static void rtl_task(struct work_struct *work) 4540 { 4541 struct rtl8169_private *tp = 4542 container_of(work, struct rtl8169_private, wk.work); 4543 4544 rtl_lock_work(tp); 4545 4546 if (!netif_running(tp->dev) || 4547 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4548 goto out_unlock; 4549 4550 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) 4551 rtl_reset_work(tp); 4552 out_unlock: 4553 rtl_unlock_work(tp); 4554 } 4555 4556 static int rtl8169_poll(struct napi_struct *napi, int budget) 4557 { 4558 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4559 struct net_device *dev = tp->dev; 4560 int work_done; 4561 4562 work_done = rtl_rx(dev, tp, (u32) budget); 4563 4564 rtl_tx(dev, tp, budget); 4565 4566 if (work_done < budget) { 4567 napi_complete_done(napi, work_done); 4568 rtl_irq_enable(tp); 4569 } 4570 4571 return work_done; 4572 } 4573 4574 static void r8169_phylink_handler(struct net_device *ndev) 4575 { 4576 struct rtl8169_private *tp = netdev_priv(ndev); 4577 4578 if (netif_carrier_ok(ndev)) { 4579 rtl_link_chg_patch(tp); 4580 pm_request_resume(&tp->pci_dev->dev); 4581 } else { 4582 pm_runtime_idle(&tp->pci_dev->dev); 4583 } 4584 4585 if (net_ratelimit()) 4586 phy_print_status(tp->phydev); 4587 } 4588 4589 static int r8169_phy_connect(struct rtl8169_private *tp) 4590 { 4591 struct phy_device *phydev = tp->phydev; 4592 phy_interface_t phy_mode; 4593 int ret; 4594 4595 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4596 PHY_INTERFACE_MODE_MII; 4597 4598 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4599 phy_mode); 4600 if (ret) 4601 return ret; 4602 4603 if (!tp->supports_gmii) 4604 phy_set_max_speed(phydev, SPEED_100); 4605 4606 phy_support_asym_pause(phydev); 4607 4608 phy_attached_info(phydev); 4609 4610 return 0; 4611 } 4612 4613 static void rtl8169_down(struct net_device *dev) 4614 { 4615 struct rtl8169_private *tp = netdev_priv(dev); 4616 4617 phy_stop(tp->phydev); 4618 4619 napi_disable(&tp->napi); 4620 netif_stop_queue(dev); 4621 4622 rtl8169_hw_reset(tp); 4623 4624 /* Give a racing hard_start_xmit a few cycles to complete. */ 4625 synchronize_rcu(); 4626 4627 rtl8169_tx_clear(tp); 4628 4629 rtl8169_rx_clear(tp); 4630 4631 rtl_pll_power_down(tp); 4632 } 4633 4634 static int rtl8169_close(struct net_device *dev) 4635 { 4636 struct rtl8169_private *tp = netdev_priv(dev); 4637 struct pci_dev *pdev = tp->pci_dev; 4638 4639 pm_runtime_get_sync(&pdev->dev); 4640 4641 /* Update counters before going down */ 4642 rtl8169_update_counters(tp); 4643 4644 rtl_lock_work(tp); 4645 /* Clear all task flags */ 4646 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4647 4648 rtl8169_down(dev); 4649 rtl_unlock_work(tp); 4650 4651 cancel_work_sync(&tp->wk.work); 4652 4653 phy_disconnect(tp->phydev); 4654 4655 pci_free_irq(pdev, 0, tp); 4656 4657 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4658 tp->RxPhyAddr); 4659 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4660 tp->TxPhyAddr); 4661 tp->TxDescArray = NULL; 4662 tp->RxDescArray = NULL; 4663 4664 pm_runtime_put_sync(&pdev->dev); 4665 4666 return 0; 4667 } 4668 4669 #ifdef CONFIG_NET_POLL_CONTROLLER 4670 static void rtl8169_netpoll(struct net_device *dev) 4671 { 4672 struct rtl8169_private *tp = netdev_priv(dev); 4673 4674 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4675 } 4676 #endif 4677 4678 static int rtl_open(struct net_device *dev) 4679 { 4680 struct rtl8169_private *tp = netdev_priv(dev); 4681 struct pci_dev *pdev = tp->pci_dev; 4682 int retval = -ENOMEM; 4683 4684 pm_runtime_get_sync(&pdev->dev); 4685 4686 /* 4687 * Rx and Tx descriptors needs 256 bytes alignment. 4688 * dma_alloc_coherent provides more. 4689 */ 4690 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4691 &tp->TxPhyAddr, GFP_KERNEL); 4692 if (!tp->TxDescArray) 4693 goto err_pm_runtime_put; 4694 4695 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4696 &tp->RxPhyAddr, GFP_KERNEL); 4697 if (!tp->RxDescArray) 4698 goto err_free_tx_0; 4699 4700 retval = rtl8169_init_ring(tp); 4701 if (retval < 0) 4702 goto err_free_rx_1; 4703 4704 rtl_request_firmware(tp); 4705 4706 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 4707 dev->name); 4708 if (retval < 0) 4709 goto err_release_fw_2; 4710 4711 retval = r8169_phy_connect(tp); 4712 if (retval) 4713 goto err_free_irq; 4714 4715 rtl_lock_work(tp); 4716 4717 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4718 4719 napi_enable(&tp->napi); 4720 4721 rtl8169_init_phy(tp); 4722 4723 rtl_pll_power_up(tp); 4724 4725 rtl_hw_start(tp); 4726 4727 rtl8169_init_counter_offsets(tp); 4728 4729 phy_start(tp->phydev); 4730 netif_start_queue(dev); 4731 4732 rtl_unlock_work(tp); 4733 4734 pm_runtime_put_sync(&pdev->dev); 4735 out: 4736 return retval; 4737 4738 err_free_irq: 4739 pci_free_irq(pdev, 0, tp); 4740 err_release_fw_2: 4741 rtl_release_firmware(tp); 4742 rtl8169_rx_clear(tp); 4743 err_free_rx_1: 4744 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4745 tp->RxPhyAddr); 4746 tp->RxDescArray = NULL; 4747 err_free_tx_0: 4748 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4749 tp->TxPhyAddr); 4750 tp->TxDescArray = NULL; 4751 err_pm_runtime_put: 4752 pm_runtime_put_noidle(&pdev->dev); 4753 goto out; 4754 } 4755 4756 static void 4757 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4758 { 4759 struct rtl8169_private *tp = netdev_priv(dev); 4760 struct pci_dev *pdev = tp->pci_dev; 4761 struct rtl8169_counters *counters = tp->counters; 4762 unsigned int start; 4763 4764 pm_runtime_get_noresume(&pdev->dev); 4765 4766 netdev_stats_to_stats64(stats, &dev->stats); 4767 4768 do { 4769 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 4770 stats->rx_packets = tp->rx_stats.packets; 4771 stats->rx_bytes = tp->rx_stats.bytes; 4772 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 4773 4774 do { 4775 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 4776 stats->tx_packets = tp->tx_stats.packets; 4777 stats->tx_bytes = tp->tx_stats.bytes; 4778 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 4779 4780 /* 4781 * Fetch additional counter values missing in stats collected by driver 4782 * from tally counters. 4783 */ 4784 if (pm_runtime_active(&pdev->dev)) 4785 rtl8169_update_counters(tp); 4786 4787 /* 4788 * Subtract values fetched during initalization. 4789 * See rtl8169_init_counter_offsets for a description why we do that. 4790 */ 4791 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4792 le64_to_cpu(tp->tc_offset.tx_errors); 4793 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4794 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4795 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4796 le16_to_cpu(tp->tc_offset.tx_aborted); 4797 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4798 le16_to_cpu(tp->tc_offset.rx_missed); 4799 4800 pm_runtime_put_noidle(&pdev->dev); 4801 } 4802 4803 static void rtl8169_net_suspend(struct net_device *dev) 4804 { 4805 struct rtl8169_private *tp = netdev_priv(dev); 4806 4807 if (!netif_running(dev)) 4808 return; 4809 4810 phy_stop(tp->phydev); 4811 netif_device_detach(dev); 4812 4813 rtl_lock_work(tp); 4814 napi_disable(&tp->napi); 4815 /* Clear all task flags */ 4816 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4817 4818 rtl_unlock_work(tp); 4819 4820 rtl_pll_power_down(tp); 4821 } 4822 4823 #ifdef CONFIG_PM 4824 4825 static int rtl8169_suspend(struct device *device) 4826 { 4827 struct net_device *dev = dev_get_drvdata(device); 4828 struct rtl8169_private *tp = netdev_priv(dev); 4829 4830 rtl8169_net_suspend(dev); 4831 clk_disable_unprepare(tp->clk); 4832 4833 return 0; 4834 } 4835 4836 static void __rtl8169_resume(struct net_device *dev) 4837 { 4838 struct rtl8169_private *tp = netdev_priv(dev); 4839 4840 netif_device_attach(dev); 4841 4842 rtl_pll_power_up(tp); 4843 rtl8169_init_phy(tp); 4844 4845 phy_start(tp->phydev); 4846 4847 rtl_lock_work(tp); 4848 napi_enable(&tp->napi); 4849 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4850 rtl_reset_work(tp); 4851 rtl_unlock_work(tp); 4852 } 4853 4854 static int rtl8169_resume(struct device *device) 4855 { 4856 struct net_device *dev = dev_get_drvdata(device); 4857 struct rtl8169_private *tp = netdev_priv(dev); 4858 4859 rtl_rar_set(tp, dev->dev_addr); 4860 4861 clk_prepare_enable(tp->clk); 4862 4863 if (netif_running(dev)) 4864 __rtl8169_resume(dev); 4865 4866 return 0; 4867 } 4868 4869 static int rtl8169_runtime_suspend(struct device *device) 4870 { 4871 struct net_device *dev = dev_get_drvdata(device); 4872 struct rtl8169_private *tp = netdev_priv(dev); 4873 4874 if (!tp->TxDescArray) 4875 return 0; 4876 4877 rtl_lock_work(tp); 4878 __rtl8169_set_wol(tp, WAKE_ANY); 4879 rtl_unlock_work(tp); 4880 4881 rtl8169_net_suspend(dev); 4882 4883 /* Update counters before going runtime suspend */ 4884 rtl8169_update_counters(tp); 4885 4886 return 0; 4887 } 4888 4889 static int rtl8169_runtime_resume(struct device *device) 4890 { 4891 struct net_device *dev = dev_get_drvdata(device); 4892 struct rtl8169_private *tp = netdev_priv(dev); 4893 4894 rtl_rar_set(tp, dev->dev_addr); 4895 4896 if (!tp->TxDescArray) 4897 return 0; 4898 4899 rtl_lock_work(tp); 4900 __rtl8169_set_wol(tp, tp->saved_wolopts); 4901 rtl_unlock_work(tp); 4902 4903 __rtl8169_resume(dev); 4904 4905 return 0; 4906 } 4907 4908 static int rtl8169_runtime_idle(struct device *device) 4909 { 4910 struct net_device *dev = dev_get_drvdata(device); 4911 4912 if (!netif_running(dev) || !netif_carrier_ok(dev)) 4913 pm_schedule_suspend(device, 10000); 4914 4915 return -EBUSY; 4916 } 4917 4918 static const struct dev_pm_ops rtl8169_pm_ops = { 4919 .suspend = rtl8169_suspend, 4920 .resume = rtl8169_resume, 4921 .freeze = rtl8169_suspend, 4922 .thaw = rtl8169_resume, 4923 .poweroff = rtl8169_suspend, 4924 .restore = rtl8169_resume, 4925 .runtime_suspend = rtl8169_runtime_suspend, 4926 .runtime_resume = rtl8169_runtime_resume, 4927 .runtime_idle = rtl8169_runtime_idle, 4928 }; 4929 4930 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 4931 4932 #else /* !CONFIG_PM */ 4933 4934 #define RTL8169_PM_OPS NULL 4935 4936 #endif /* !CONFIG_PM */ 4937 4938 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4939 { 4940 /* WoL fails with 8168b when the receiver is disabled. */ 4941 switch (tp->mac_version) { 4942 case RTL_GIGA_MAC_VER_11: 4943 case RTL_GIGA_MAC_VER_12: 4944 case RTL_GIGA_MAC_VER_17: 4945 pci_clear_master(tp->pci_dev); 4946 4947 RTL_W8(tp, ChipCmd, CmdRxEnb); 4948 rtl_pci_commit(tp); 4949 break; 4950 default: 4951 break; 4952 } 4953 } 4954 4955 static void rtl_shutdown(struct pci_dev *pdev) 4956 { 4957 struct net_device *dev = pci_get_drvdata(pdev); 4958 struct rtl8169_private *tp = netdev_priv(dev); 4959 4960 rtl8169_net_suspend(dev); 4961 4962 /* Restore original MAC address */ 4963 rtl_rar_set(tp, dev->perm_addr); 4964 4965 rtl8169_hw_reset(tp); 4966 4967 if (system_state == SYSTEM_POWER_OFF) { 4968 if (tp->saved_wolopts) { 4969 rtl_wol_suspend_quirk(tp); 4970 rtl_wol_shutdown_quirk(tp); 4971 } 4972 4973 pci_wake_from_d3(pdev, true); 4974 pci_set_power_state(pdev, PCI_D3hot); 4975 } 4976 } 4977 4978 static void rtl_remove_one(struct pci_dev *pdev) 4979 { 4980 struct net_device *dev = pci_get_drvdata(pdev); 4981 struct rtl8169_private *tp = netdev_priv(dev); 4982 4983 if (r8168_check_dash(tp)) 4984 rtl8168_driver_stop(tp); 4985 4986 netif_napi_del(&tp->napi); 4987 4988 unregister_netdev(dev); 4989 mdiobus_unregister(tp->phydev->mdio.bus); 4990 4991 rtl_release_firmware(tp); 4992 4993 if (pci_dev_run_wake(pdev)) 4994 pm_runtime_get_noresume(&pdev->dev); 4995 4996 /* restore original MAC address */ 4997 rtl_rar_set(tp, dev->perm_addr); 4998 } 4999 5000 static const struct net_device_ops rtl_netdev_ops = { 5001 .ndo_open = rtl_open, 5002 .ndo_stop = rtl8169_close, 5003 .ndo_get_stats64 = rtl8169_get_stats64, 5004 .ndo_start_xmit = rtl8169_start_xmit, 5005 .ndo_features_check = rtl8169_features_check, 5006 .ndo_tx_timeout = rtl8169_tx_timeout, 5007 .ndo_validate_addr = eth_validate_addr, 5008 .ndo_change_mtu = rtl8169_change_mtu, 5009 .ndo_fix_features = rtl8169_fix_features, 5010 .ndo_set_features = rtl8169_set_features, 5011 .ndo_set_mac_address = rtl_set_mac_address, 5012 .ndo_do_ioctl = phy_do_ioctl_running, 5013 .ndo_set_rx_mode = rtl_set_rx_mode, 5014 #ifdef CONFIG_NET_POLL_CONTROLLER 5015 .ndo_poll_controller = rtl8169_netpoll, 5016 #endif 5017 5018 }; 5019 5020 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5021 { 5022 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5023 5024 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5025 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5026 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5027 /* special workaround needed */ 5028 tp->irq_mask |= RxFIFOOver; 5029 else 5030 tp->irq_mask |= RxOverflow; 5031 } 5032 5033 static int rtl_alloc_irq(struct rtl8169_private *tp) 5034 { 5035 unsigned int flags; 5036 5037 switch (tp->mac_version) { 5038 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5039 rtl_unlock_config_regs(tp); 5040 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5041 rtl_lock_config_regs(tp); 5042 /* fall through */ 5043 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5044 flags = PCI_IRQ_LEGACY; 5045 break; 5046 default: 5047 flags = PCI_IRQ_ALL_TYPES; 5048 break; 5049 } 5050 5051 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5052 } 5053 5054 static void rtl_read_mac_address(struct rtl8169_private *tp, 5055 u8 mac_addr[ETH_ALEN]) 5056 { 5057 /* Get MAC address */ 5058 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5059 u32 value = rtl_eri_read(tp, 0xe0); 5060 5061 mac_addr[0] = (value >> 0) & 0xff; 5062 mac_addr[1] = (value >> 8) & 0xff; 5063 mac_addr[2] = (value >> 16) & 0xff; 5064 mac_addr[3] = (value >> 24) & 0xff; 5065 5066 value = rtl_eri_read(tp, 0xe4); 5067 mac_addr[4] = (value >> 0) & 0xff; 5068 mac_addr[5] = (value >> 8) & 0xff; 5069 } else if (rtl_is_8125(tp)) { 5070 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5071 } 5072 } 5073 5074 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5075 { 5076 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5077 } 5078 5079 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 5080 { 5081 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 5082 } 5083 5084 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5085 { 5086 struct rtl8169_private *tp = mii_bus->priv; 5087 5088 if (phyaddr > 0) 5089 return -ENODEV; 5090 5091 return rtl_readphy(tp, phyreg); 5092 } 5093 5094 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5095 int phyreg, u16 val) 5096 { 5097 struct rtl8169_private *tp = mii_bus->priv; 5098 5099 if (phyaddr > 0) 5100 return -ENODEV; 5101 5102 rtl_writephy(tp, phyreg, val); 5103 5104 return 0; 5105 } 5106 5107 static int r8169_mdio_register(struct rtl8169_private *tp) 5108 { 5109 struct pci_dev *pdev = tp->pci_dev; 5110 struct mii_bus *new_bus; 5111 int ret; 5112 5113 new_bus = devm_mdiobus_alloc(&pdev->dev); 5114 if (!new_bus) 5115 return -ENOMEM; 5116 5117 new_bus->name = "r8169"; 5118 new_bus->priv = tp; 5119 new_bus->parent = &pdev->dev; 5120 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5121 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5122 5123 new_bus->read = r8169_mdio_read_reg; 5124 new_bus->write = r8169_mdio_write_reg; 5125 5126 ret = devm_mdiobus_register(new_bus); 5127 if (ret) 5128 return ret; 5129 5130 tp->phydev = mdiobus_get_phy(new_bus, 0); 5131 if (!tp->phydev) { 5132 return -ENODEV; 5133 } else if (!tp->phydev->drv) { 5134 /* Most chip versions fail with the genphy driver. 5135 * Therefore ensure that the dedicated PHY driver is loaded. 5136 */ 5137 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5138 tp->phydev->phy_id); 5139 return -EUNATCH; 5140 } 5141 5142 /* PHY will be woken up in rtl_open() */ 5143 phy_suspend(tp->phydev); 5144 5145 return 0; 5146 } 5147 5148 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5149 { 5150 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 5151 5152 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 5153 return; 5154 5155 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 5156 return; 5157 5158 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5159 msleep(1); 5160 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5161 5162 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5163 5164 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 5165 return; 5166 5167 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5168 5169 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5170 } 5171 5172 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5173 { 5174 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 5175 5176 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 5177 return; 5178 5179 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5180 msleep(1); 5181 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5182 5183 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5184 5185 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 5186 return; 5187 5188 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5189 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5190 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5191 5192 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5193 } 5194 5195 static void rtl_hw_initialize(struct rtl8169_private *tp) 5196 { 5197 switch (tp->mac_version) { 5198 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 5199 rtl8168ep_stop_cmac(tp); 5200 /* fall through */ 5201 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5202 rtl_hw_init_8168g(tp); 5203 break; 5204 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 5205 rtl_hw_init_8125(tp); 5206 break; 5207 default: 5208 break; 5209 } 5210 } 5211 5212 static int rtl_jumbo_max(struct rtl8169_private *tp) 5213 { 5214 /* Non-GBit versions don't support jumbo frames */ 5215 if (!tp->supports_gmii) 5216 return 0; 5217 5218 switch (tp->mac_version) { 5219 /* RTL8169 */ 5220 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5221 return JUMBO_7K; 5222 /* RTL8168b */ 5223 case RTL_GIGA_MAC_VER_11: 5224 case RTL_GIGA_MAC_VER_12: 5225 case RTL_GIGA_MAC_VER_17: 5226 return JUMBO_4K; 5227 /* RTL8168c */ 5228 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5229 return JUMBO_6K; 5230 default: 5231 return JUMBO_9K; 5232 } 5233 } 5234 5235 static void rtl_disable_clk(void *data) 5236 { 5237 clk_disable_unprepare(data); 5238 } 5239 5240 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5241 { 5242 struct device *d = tp_to_dev(tp); 5243 struct clk *clk; 5244 int rc; 5245 5246 clk = devm_clk_get(d, "ether_clk"); 5247 if (IS_ERR(clk)) { 5248 rc = PTR_ERR(clk); 5249 if (rc == -ENOENT) 5250 /* clk-core allows NULL (for suspend / resume) */ 5251 rc = 0; 5252 else if (rc != -EPROBE_DEFER) 5253 dev_err(d, "failed to get clk: %d\n", rc); 5254 } else { 5255 tp->clk = clk; 5256 rc = clk_prepare_enable(clk); 5257 if (rc) 5258 dev_err(d, "failed to enable clk: %d\n", rc); 5259 else 5260 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5261 } 5262 5263 return rc; 5264 } 5265 5266 static void rtl_init_mac_address(struct rtl8169_private *tp) 5267 { 5268 struct net_device *dev = tp->dev; 5269 u8 *mac_addr = dev->dev_addr; 5270 int rc; 5271 5272 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5273 if (!rc) 5274 goto done; 5275 5276 rtl_read_mac_address(tp, mac_addr); 5277 if (is_valid_ether_addr(mac_addr)) 5278 goto done; 5279 5280 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5281 if (is_valid_ether_addr(mac_addr)) 5282 goto done; 5283 5284 eth_hw_addr_random(dev); 5285 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5286 done: 5287 rtl_rar_set(tp, mac_addr); 5288 } 5289 5290 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5291 { 5292 struct rtl8169_private *tp; 5293 int jumbo_max, region, rc; 5294 enum mac_version chipset; 5295 struct net_device *dev; 5296 u16 xid; 5297 5298 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5299 if (!dev) 5300 return -ENOMEM; 5301 5302 SET_NETDEV_DEV(dev, &pdev->dev); 5303 dev->netdev_ops = &rtl_netdev_ops; 5304 tp = netdev_priv(dev); 5305 tp->dev = dev; 5306 tp->pci_dev = pdev; 5307 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5308 tp->eee_adv = -1; 5309 tp->ocp_base = OCP_STD_PHY_BASE; 5310 5311 /* Get the *optional* external "ether_clk" used on some boards */ 5312 rc = rtl_get_ether_clk(tp); 5313 if (rc) 5314 return rc; 5315 5316 /* Disable ASPM completely as that cause random device stop working 5317 * problems as well as full system hangs for some PCIe devices users. 5318 */ 5319 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5320 PCIE_LINK_STATE_L1); 5321 tp->aspm_manageable = !rc; 5322 5323 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5324 rc = pcim_enable_device(pdev); 5325 if (rc < 0) { 5326 dev_err(&pdev->dev, "enable failure\n"); 5327 return rc; 5328 } 5329 5330 if (pcim_set_mwi(pdev) < 0) 5331 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5332 5333 /* use first MMIO region */ 5334 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5335 if (region < 0) { 5336 dev_err(&pdev->dev, "no MMIO resource found\n"); 5337 return -ENODEV; 5338 } 5339 5340 /* check for weird/broken PCI region reporting */ 5341 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5342 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5343 return -ENODEV; 5344 } 5345 5346 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5347 if (rc < 0) { 5348 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5349 return rc; 5350 } 5351 5352 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5353 5354 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5355 5356 /* Identify chip attached to board */ 5357 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5358 if (chipset == RTL_GIGA_MAC_NONE) { 5359 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid); 5360 return -ENODEV; 5361 } 5362 5363 tp->mac_version = chipset; 5364 5365 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5366 5367 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5368 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5369 dev->features |= NETIF_F_HIGHDMA; 5370 5371 rtl_init_rxcfg(tp); 5372 5373 rtl8169_irq_mask_and_ack(tp); 5374 5375 rtl_hw_initialize(tp); 5376 5377 rtl_hw_reset(tp); 5378 5379 pci_set_master(pdev); 5380 5381 rc = rtl_alloc_irq(tp); 5382 if (rc < 0) { 5383 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5384 return rc; 5385 } 5386 5387 mutex_init(&tp->wk.mutex); 5388 INIT_WORK(&tp->wk.work, rtl_task); 5389 u64_stats_init(&tp->rx_stats.syncp); 5390 u64_stats_init(&tp->tx_stats.syncp); 5391 5392 rtl_init_mac_address(tp); 5393 5394 dev->ethtool_ops = &rtl8169_ethtool_ops; 5395 5396 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5397 5398 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5399 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5400 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5401 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5402 5403 /* 5404 * Pretend we are using VLANs; This bypasses a nasty bug where 5405 * Interrupts stop flowing on high load on 8110SCd controllers. 5406 */ 5407 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5408 /* Disallow toggling */ 5409 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5410 5411 if (rtl_chip_supports_csum_v2(tp)) 5412 dev->hw_features |= NETIF_F_IPV6_CSUM; 5413 5414 dev->features |= dev->hw_features; 5415 5416 /* There has been a number of reports that using SG/TSO results in 5417 * tx timeouts. However for a lot of people SG/TSO works fine. 5418 * Therefore disable both features by default, but allow users to 5419 * enable them. Use at own risk! 5420 */ 5421 if (rtl_chip_supports_csum_v2(tp)) { 5422 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5423 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5424 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5425 } else { 5426 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5427 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5428 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5429 } 5430 5431 dev->hw_features |= NETIF_F_RXALL; 5432 dev->hw_features |= NETIF_F_RXFCS; 5433 5434 /* configure chip for default features */ 5435 rtl8169_set_features(dev, dev->features); 5436 5437 jumbo_max = rtl_jumbo_max(tp); 5438 if (jumbo_max) 5439 dev->max_mtu = jumbo_max; 5440 5441 rtl_set_irq_mask(tp); 5442 5443 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5444 5445 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5446 &tp->counters_phys_addr, 5447 GFP_KERNEL); 5448 if (!tp->counters) 5449 return -ENOMEM; 5450 5451 pci_set_drvdata(pdev, dev); 5452 5453 rc = r8169_mdio_register(tp); 5454 if (rc) 5455 return rc; 5456 5457 /* chip gets powered up in rtl_open() */ 5458 rtl_pll_power_down(tp); 5459 5460 rc = register_netdev(dev); 5461 if (rc) 5462 return rc; 5463 5464 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5465 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5466 pci_irq_vector(pdev, 0)); 5467 5468 if (jumbo_max) 5469 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5470 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5471 "ok" : "ko"); 5472 5473 if (r8168_check_dash(tp)) 5474 rtl8168_driver_start(tp); 5475 5476 if (pci_dev_run_wake(pdev)) 5477 pm_runtime_put_sync(&pdev->dev); 5478 5479 return 0; 5480 } 5481 5482 static struct pci_driver rtl8169_pci_driver = { 5483 .name = MODULENAME, 5484 .id_table = rtl8169_pci_tbl, 5485 .probe = rtl_init_one, 5486 .remove = rtl_remove_one, 5487 .shutdown = rtl_shutdown, 5488 .driver.pm = RTL8169_PM_OPS, 5489 }; 5490 5491 module_pci_driver(rtl8169_pci_driver); 5492