1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 59 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 60 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 61 62 #define R8169_REGS_SIZE 256 63 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 64 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 65 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 66 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 67 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 68 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 69 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 70 71 #define OCP_STD_PHY_BASE 0xa400 72 73 #define RTL_CFG_NO_GBIT 1 74 75 /* write/read MMIO register */ 76 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 79 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 80 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 81 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 82 83 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 84 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 88 static const struct { 89 const char *name; 90 const char *fw_name; 91 } rtl_chip_infos[] = { 92 /* PCI devices. */ 93 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 94 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 95 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 96 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 97 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 98 /* PCI-E devices. */ 99 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 100 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 102 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 103 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 104 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 105 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 106 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 107 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 108 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 109 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 112 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 114 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 115 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 116 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 117 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 118 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 119 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 120 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 121 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 122 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 123 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 124 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 125 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 126 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 127 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 128 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 129 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 130 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 131 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 132 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 133 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 134 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 135 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 136 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 137 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 138 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 139 }; 140 141 static const struct pci_device_id rtl8169_pci_tbl[] = { 142 { PCI_VDEVICE(REALTEK, 0x2502) }, 143 { PCI_VDEVICE(REALTEK, 0x2600) }, 144 { PCI_VDEVICE(REALTEK, 0x8129) }, 145 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 146 { PCI_VDEVICE(REALTEK, 0x8161) }, 147 { PCI_VDEVICE(REALTEK, 0x8162) }, 148 { PCI_VDEVICE(REALTEK, 0x8167) }, 149 { PCI_VDEVICE(REALTEK, 0x8168) }, 150 { PCI_VDEVICE(NCUBE, 0x8168) }, 151 { PCI_VDEVICE(REALTEK, 0x8169) }, 152 { PCI_VENDOR_ID_DLINK, 0x4300, 153 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 154 { PCI_VDEVICE(DLINK, 0x4300) }, 155 { PCI_VDEVICE(DLINK, 0x4302) }, 156 { PCI_VDEVICE(AT, 0xc107) }, 157 { PCI_VDEVICE(USR, 0x0116) }, 158 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 159 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 160 { PCI_VDEVICE(REALTEK, 0x8125) }, 161 { PCI_VDEVICE(REALTEK, 0x3000) }, 162 {} 163 }; 164 165 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 166 167 enum rtl_registers { 168 MAC0 = 0, /* Ethernet hardware address. */ 169 MAC4 = 4, 170 MAR0 = 8, /* Multicast filter. */ 171 CounterAddrLow = 0x10, 172 CounterAddrHigh = 0x14, 173 TxDescStartAddrLow = 0x20, 174 TxDescStartAddrHigh = 0x24, 175 TxHDescStartAddrLow = 0x28, 176 TxHDescStartAddrHigh = 0x2c, 177 FLASH = 0x30, 178 ERSR = 0x36, 179 ChipCmd = 0x37, 180 TxPoll = 0x38, 181 IntrMask = 0x3c, 182 IntrStatus = 0x3e, 183 184 TxConfig = 0x40, 185 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 186 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 187 188 RxConfig = 0x44, 189 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 190 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 191 #define RXCFG_FIFO_SHIFT 13 192 /* No threshold before first PCI xfer */ 193 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 194 #define RX_EARLY_OFF (1 << 11) 195 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 196 #define RXCFG_DMA_SHIFT 8 197 /* Unlimited maximum PCI burst. */ 198 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 199 200 Cfg9346 = 0x50, 201 Config0 = 0x51, 202 Config1 = 0x52, 203 Config2 = 0x53, 204 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 205 206 Config3 = 0x54, 207 Config4 = 0x55, 208 Config5 = 0x56, 209 PHYAR = 0x60, 210 PHYstatus = 0x6c, 211 RxMaxSize = 0xda, 212 CPlusCmd = 0xe0, 213 IntrMitigate = 0xe2, 214 215 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 216 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 217 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 218 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 219 220 #define RTL_COALESCE_T_MAX 0x0fU 221 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 222 223 RxDescAddrLow = 0xe4, 224 RxDescAddrHigh = 0xe8, 225 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 226 227 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 228 229 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 230 231 #define TxPacketMax (8064 >> 7) 232 #define EarlySize 0x27 233 234 FuncEvent = 0xf0, 235 FuncEventMask = 0xf4, 236 FuncPresetState = 0xf8, 237 IBCR0 = 0xf8, 238 IBCR2 = 0xf9, 239 IBIMR0 = 0xfa, 240 IBISR0 = 0xfb, 241 FuncForceEvent = 0xfc, 242 }; 243 244 enum rtl8168_8101_registers { 245 CSIDR = 0x64, 246 CSIAR = 0x68, 247 #define CSIAR_FLAG 0x80000000 248 #define CSIAR_WRITE_CMD 0x80000000 249 #define CSIAR_BYTE_ENABLE 0x0000f000 250 #define CSIAR_ADDR_MASK 0x00000fff 251 PMCH = 0x6f, 252 #define D3COLD_NO_PLL_DOWN BIT(7) 253 #define D3HOT_NO_PLL_DOWN BIT(6) 254 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 255 EPHYAR = 0x80, 256 #define EPHYAR_FLAG 0x80000000 257 #define EPHYAR_WRITE_CMD 0x80000000 258 #define EPHYAR_REG_MASK 0x1f 259 #define EPHYAR_REG_SHIFT 16 260 #define EPHYAR_DATA_MASK 0xffff 261 DLLPR = 0xd0, 262 #define PFM_EN (1 << 6) 263 #define TX_10M_PS_EN (1 << 7) 264 DBG_REG = 0xd1, 265 #define FIX_NAK_1 (1 << 4) 266 #define FIX_NAK_2 (1 << 3) 267 TWSI = 0xd2, 268 MCU = 0xd3, 269 #define NOW_IS_OOB (1 << 7) 270 #define TX_EMPTY (1 << 5) 271 #define RX_EMPTY (1 << 4) 272 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 273 #define EN_NDP (1 << 3) 274 #define EN_OOB_RESET (1 << 2) 275 #define LINK_LIST_RDY (1 << 1) 276 EFUSEAR = 0xdc, 277 #define EFUSEAR_FLAG 0x80000000 278 #define EFUSEAR_WRITE_CMD 0x80000000 279 #define EFUSEAR_READ_CMD 0x00000000 280 #define EFUSEAR_REG_MASK 0x03ff 281 #define EFUSEAR_REG_SHIFT 8 282 #define EFUSEAR_DATA_MASK 0xff 283 MISC_1 = 0xf2, 284 #define PFM_D3COLD_EN (1 << 6) 285 }; 286 287 enum rtl8168_registers { 288 LED_CTRL = 0x18, 289 LED_FREQ = 0x1a, 290 EEE_LED = 0x1b, 291 ERIDR = 0x70, 292 ERIAR = 0x74, 293 #define ERIAR_FLAG 0x80000000 294 #define ERIAR_WRITE_CMD 0x80000000 295 #define ERIAR_READ_CMD 0x00000000 296 #define ERIAR_ADDR_BYTE_ALIGN 4 297 #define ERIAR_TYPE_SHIFT 16 298 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 299 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 300 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 301 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_MASK_SHIFT 12 303 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 304 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 305 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 306 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 308 EPHY_RXER_NUM = 0x7c, 309 OCPDR = 0xb0, /* OCP GPHY access */ 310 #define OCPDR_WRITE_CMD 0x80000000 311 #define OCPDR_READ_CMD 0x00000000 312 #define OCPDR_REG_MASK 0x7f 313 #define OCPDR_GPHY_REG_SHIFT 16 314 #define OCPDR_DATA_MASK 0xffff 315 OCPAR = 0xb4, 316 #define OCPAR_FLAG 0x80000000 317 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 318 #define OCPAR_GPHY_READ_CMD 0x0000f060 319 GPHY_OCP = 0xb8, 320 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 321 MISC = 0xf0, /* 8168e only. */ 322 #define TXPLA_RST (1 << 29) 323 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 324 #define PWM_EN (1 << 22) 325 #define RXDV_GATED_EN (1 << 19) 326 #define EARLY_TALLY_EN (1 << 16) 327 }; 328 329 enum rtl8125_registers { 330 IntrMask_8125 = 0x38, 331 IntrStatus_8125 = 0x3c, 332 TxPoll_8125 = 0x90, 333 MAC0_BKP = 0x19e0, 334 EEE_TXIDLE_TIMER_8125 = 0x6048, 335 }; 336 337 #define RX_VLAN_INNER_8125 BIT(22) 338 #define RX_VLAN_OUTER_8125 BIT(23) 339 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 340 341 #define RX_FETCH_DFLT_8125 (8 << 27) 342 343 enum rtl_register_content { 344 /* InterruptStatusBits */ 345 SYSErr = 0x8000, 346 PCSTimeout = 0x4000, 347 SWInt = 0x0100, 348 TxDescUnavail = 0x0080, 349 RxFIFOOver = 0x0040, 350 LinkChg = 0x0020, 351 RxOverflow = 0x0010, 352 TxErr = 0x0008, 353 TxOK = 0x0004, 354 RxErr = 0x0002, 355 RxOK = 0x0001, 356 357 /* RxStatusDesc */ 358 RxRWT = (1 << 22), 359 RxRES = (1 << 21), 360 RxRUNT = (1 << 20), 361 RxCRC = (1 << 19), 362 363 /* ChipCmdBits */ 364 StopReq = 0x80, 365 CmdReset = 0x10, 366 CmdRxEnb = 0x08, 367 CmdTxEnb = 0x04, 368 RxBufEmpty = 0x01, 369 370 /* TXPoll register p.5 */ 371 HPQ = 0x80, /* Poll cmd on the high prio queue */ 372 NPQ = 0x40, /* Poll cmd on the low prio queue */ 373 FSWInt = 0x01, /* Forced software interrupt */ 374 375 /* Cfg9346Bits */ 376 Cfg9346_Lock = 0x00, 377 Cfg9346_Unlock = 0xc0, 378 379 /* rx_mode_bits */ 380 AcceptErr = 0x20, 381 AcceptRunt = 0x10, 382 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 383 AcceptBroadcast = 0x08, 384 AcceptMulticast = 0x04, 385 AcceptMyPhys = 0x02, 386 AcceptAllPhys = 0x01, 387 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 388 #define RX_CONFIG_ACCEPT_MASK 0x3f 389 390 /* TxConfigBits */ 391 TxInterFrameGapShift = 24, 392 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 393 394 /* Config1 register p.24 */ 395 LEDS1 = (1 << 7), 396 LEDS0 = (1 << 6), 397 Speed_down = (1 << 4), 398 MEMMAP = (1 << 3), 399 IOMAP = (1 << 2), 400 VPD = (1 << 1), 401 PMEnable = (1 << 0), /* Power Management Enable */ 402 403 /* Config2 register p. 25 */ 404 ClkReqEn = (1 << 7), /* Clock Request Enable */ 405 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 406 PCI_Clock_66MHz = 0x01, 407 PCI_Clock_33MHz = 0x00, 408 409 /* Config3 register p.25 */ 410 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 411 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 412 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 413 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 414 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 415 416 /* Config4 register */ 417 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 418 419 /* Config5 register p.27 */ 420 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 421 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 422 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 423 Spi_en = (1 << 3), 424 LanWake = (1 << 1), /* LanWake enable/disable */ 425 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 426 ASPM_en = (1 << 0), /* ASPM enable */ 427 428 /* CPlusCmd p.31 */ 429 EnableBist = (1 << 15), // 8168 8101 430 Mac_dbgo_oe = (1 << 14), // 8168 8101 431 EnAnaPLL = (1 << 14), // 8169 432 Normal_mode = (1 << 13), // unused 433 Force_half_dup = (1 << 12), // 8168 8101 434 Force_rxflow_en = (1 << 11), // 8168 8101 435 Force_txflow_en = (1 << 10), // 8168 8101 436 Cxpl_dbg_sel = (1 << 9), // 8168 8101 437 ASF = (1 << 8), // 8168 8101 438 PktCntrDisable = (1 << 7), // 8168 8101 439 Mac_dbgo_sel = 0x001c, // 8168 440 RxVlan = (1 << 6), 441 RxChkSum = (1 << 5), 442 PCIDAC = (1 << 4), 443 PCIMulRW = (1 << 3), 444 #define INTT_MASK GENMASK(1, 0) 445 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 446 447 /* rtl8169_PHYstatus */ 448 TBI_Enable = 0x80, 449 TxFlowCtrl = 0x40, 450 RxFlowCtrl = 0x20, 451 _1000bpsF = 0x10, 452 _100bps = 0x08, 453 _10bps = 0x04, 454 LinkStatus = 0x02, 455 FullDup = 0x01, 456 457 /* ResetCounterCommand */ 458 CounterReset = 0x1, 459 460 /* DumpCounterCommand */ 461 CounterDump = 0x8, 462 463 /* magic enable v2 */ 464 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 465 }; 466 467 enum rtl_desc_bit { 468 /* First doubleword. */ 469 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 470 RingEnd = (1 << 30), /* End of descriptor ring */ 471 FirstFrag = (1 << 29), /* First segment of a packet */ 472 LastFrag = (1 << 28), /* Final segment of a packet */ 473 }; 474 475 /* Generic case. */ 476 enum rtl_tx_desc_bit { 477 /* First doubleword. */ 478 TD_LSO = (1 << 27), /* Large Send Offload */ 479 #define TD_MSS_MAX 0x07ffu /* MSS value */ 480 481 /* Second doubleword. */ 482 TxVlanTag = (1 << 17), /* Add VLAN tag */ 483 }; 484 485 /* 8169, 8168b and 810x except 8102e. */ 486 enum rtl_tx_desc_bit_0 { 487 /* First doubleword. */ 488 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 489 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 490 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 491 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 492 }; 493 494 /* 8102e, 8168c and beyond. */ 495 enum rtl_tx_desc_bit_1 { 496 /* First doubleword. */ 497 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 498 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 499 #define GTTCPHO_SHIFT 18 500 #define GTTCPHO_MAX 0x7f 501 502 /* Second doubleword. */ 503 #define TCPHO_SHIFT 18 504 #define TCPHO_MAX 0x3ff 505 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 506 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 507 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 508 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 509 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 510 }; 511 512 enum rtl_rx_desc_bit { 513 /* Rx private */ 514 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 515 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 516 517 #define RxProtoUDP (PID1) 518 #define RxProtoTCP (PID0) 519 #define RxProtoIP (PID1 | PID0) 520 #define RxProtoMask RxProtoIP 521 522 IPFail = (1 << 16), /* IP checksum failed */ 523 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 524 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 525 526 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 527 528 RxVlanTag = (1 << 16), /* VLAN tag available */ 529 }; 530 531 #define RTL_GSO_MAX_SIZE_V1 32000 532 #define RTL_GSO_MAX_SEGS_V1 24 533 #define RTL_GSO_MAX_SIZE_V2 64000 534 #define RTL_GSO_MAX_SEGS_V2 64 535 536 struct TxDesc { 537 __le32 opts1; 538 __le32 opts2; 539 __le64 addr; 540 }; 541 542 struct RxDesc { 543 __le32 opts1; 544 __le32 opts2; 545 __le64 addr; 546 }; 547 548 struct ring_info { 549 struct sk_buff *skb; 550 u32 len; 551 }; 552 553 struct rtl8169_counters { 554 __le64 tx_packets; 555 __le64 rx_packets; 556 __le64 tx_errors; 557 __le32 rx_errors; 558 __le16 rx_missed; 559 __le16 align_errors; 560 __le32 tx_one_collision; 561 __le32 tx_multi_collision; 562 __le64 rx_unicast; 563 __le64 rx_broadcast; 564 __le32 rx_multicast; 565 __le16 tx_aborted; 566 __le16 tx_underun; 567 }; 568 569 struct rtl8169_tc_offsets { 570 bool inited; 571 __le64 tx_errors; 572 __le32 tx_multi_collision; 573 __le16 tx_aborted; 574 __le16 rx_missed; 575 }; 576 577 enum rtl_flag { 578 RTL_FLAG_TASK_ENABLED = 0, 579 RTL_FLAG_TASK_RESET_PENDING, 580 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 581 RTL_FLAG_TASK_TX_TIMEOUT, 582 RTL_FLAG_MAX 583 }; 584 585 enum rtl_dash_type { 586 RTL_DASH_NONE, 587 RTL_DASH_DP, 588 RTL_DASH_EP, 589 }; 590 591 struct rtl8169_private { 592 void __iomem *mmio_addr; /* memory map physical address */ 593 struct pci_dev *pci_dev; 594 struct net_device *dev; 595 struct phy_device *phydev; 596 struct napi_struct napi; 597 enum mac_version mac_version; 598 enum rtl_dash_type dash_type; 599 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 600 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 601 u32 dirty_tx; 602 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 603 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 604 dma_addr_t TxPhyAddr; 605 dma_addr_t RxPhyAddr; 606 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 607 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 608 u16 cp_cmd; 609 u32 irq_mask; 610 int irq; 611 struct clk *clk; 612 613 struct { 614 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 615 struct work_struct work; 616 } wk; 617 618 raw_spinlock_t config25_lock; 619 raw_spinlock_t mac_ocp_lock; 620 struct mutex led_lock; /* serialize LED ctrl RMW access */ 621 622 raw_spinlock_t cfg9346_usage_lock; 623 int cfg9346_usage_count; 624 625 unsigned supports_gmii:1; 626 unsigned aspm_manageable:1; 627 unsigned dash_enabled:1; 628 dma_addr_t counters_phys_addr; 629 struct rtl8169_counters *counters; 630 struct rtl8169_tc_offsets tc_offset; 631 u32 saved_wolopts; 632 633 const char *fw_name; 634 struct rtl_fw *rtl_fw; 635 636 u32 ocp_base; 637 }; 638 639 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 640 641 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 642 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 643 MODULE_SOFTDEP("pre: realtek"); 644 MODULE_LICENSE("GPL"); 645 MODULE_FIRMWARE(FIRMWARE_8168D_1); 646 MODULE_FIRMWARE(FIRMWARE_8168D_2); 647 MODULE_FIRMWARE(FIRMWARE_8168E_1); 648 MODULE_FIRMWARE(FIRMWARE_8168E_2); 649 MODULE_FIRMWARE(FIRMWARE_8168E_3); 650 MODULE_FIRMWARE(FIRMWARE_8105E_1); 651 MODULE_FIRMWARE(FIRMWARE_8168F_1); 652 MODULE_FIRMWARE(FIRMWARE_8168F_2); 653 MODULE_FIRMWARE(FIRMWARE_8402_1); 654 MODULE_FIRMWARE(FIRMWARE_8411_1); 655 MODULE_FIRMWARE(FIRMWARE_8411_2); 656 MODULE_FIRMWARE(FIRMWARE_8106E_1); 657 MODULE_FIRMWARE(FIRMWARE_8106E_2); 658 MODULE_FIRMWARE(FIRMWARE_8168G_2); 659 MODULE_FIRMWARE(FIRMWARE_8168G_3); 660 MODULE_FIRMWARE(FIRMWARE_8168H_2); 661 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 662 MODULE_FIRMWARE(FIRMWARE_8107E_2); 663 MODULE_FIRMWARE(FIRMWARE_8125A_3); 664 MODULE_FIRMWARE(FIRMWARE_8125B_2); 665 666 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 667 { 668 return &tp->pci_dev->dev; 669 } 670 671 static void rtl_lock_config_regs(struct rtl8169_private *tp) 672 { 673 unsigned long flags; 674 675 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 676 if (!--tp->cfg9346_usage_count) 677 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 678 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 679 } 680 681 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 682 { 683 unsigned long flags; 684 685 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 686 if (!tp->cfg9346_usage_count++) 687 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 688 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 689 } 690 691 static void rtl_pci_commit(struct rtl8169_private *tp) 692 { 693 /* Read an arbitrary register to commit a preceding PCI write */ 694 RTL_R8(tp, ChipCmd); 695 } 696 697 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 698 { 699 unsigned long flags; 700 u8 val; 701 702 raw_spin_lock_irqsave(&tp->config25_lock, flags); 703 val = RTL_R8(tp, Config2); 704 RTL_W8(tp, Config2, (val & ~clear) | set); 705 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 706 } 707 708 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 709 { 710 unsigned long flags; 711 u8 val; 712 713 raw_spin_lock_irqsave(&tp->config25_lock, flags); 714 val = RTL_R8(tp, Config5); 715 RTL_W8(tp, Config5, (val & ~clear) | set); 716 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 717 } 718 719 static bool rtl_is_8125(struct rtl8169_private *tp) 720 { 721 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 722 } 723 724 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 725 { 726 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 727 tp->mac_version != RTL_GIGA_MAC_VER_39 && 728 tp->mac_version <= RTL_GIGA_MAC_VER_53; 729 } 730 731 static bool rtl_supports_eee(struct rtl8169_private *tp) 732 { 733 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 734 tp->mac_version != RTL_GIGA_MAC_VER_37 && 735 tp->mac_version != RTL_GIGA_MAC_VER_39; 736 } 737 738 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 739 { 740 int i; 741 742 for (i = 0; i < ETH_ALEN; i++) 743 mac[i] = RTL_R8(tp, reg + i); 744 } 745 746 struct rtl_cond { 747 bool (*check)(struct rtl8169_private *); 748 const char *msg; 749 }; 750 751 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 752 unsigned long usecs, int n, bool high) 753 { 754 int i; 755 756 for (i = 0; i < n; i++) { 757 if (c->check(tp) == high) 758 return true; 759 fsleep(usecs); 760 } 761 762 if (net_ratelimit()) 763 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 764 c->msg, !high, n, usecs); 765 return false; 766 } 767 768 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 769 const struct rtl_cond *c, 770 unsigned long d, int n) 771 { 772 return rtl_loop_wait(tp, c, d, n, true); 773 } 774 775 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 776 const struct rtl_cond *c, 777 unsigned long d, int n) 778 { 779 return rtl_loop_wait(tp, c, d, n, false); 780 } 781 782 #define DECLARE_RTL_COND(name) \ 783 static bool name ## _check(struct rtl8169_private *); \ 784 \ 785 static const struct rtl_cond name = { \ 786 .check = name ## _check, \ 787 .msg = #name \ 788 }; \ 789 \ 790 static bool name ## _check(struct rtl8169_private *tp) 791 792 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 793 { 794 struct device *dev = tp_to_dev(tp); 795 int ret; 796 797 ret = pm_runtime_resume_and_get(dev); 798 if (ret < 0) 799 return ret; 800 801 mutex_lock(&tp->led_lock); 802 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 803 mutex_unlock(&tp->led_lock); 804 805 pm_runtime_put_sync(dev); 806 807 return 0; 808 } 809 810 int rtl8168_get_led_mode(struct rtl8169_private *tp) 811 { 812 struct device *dev = tp_to_dev(tp); 813 int ret; 814 815 ret = pm_runtime_resume_and_get(dev); 816 if (ret < 0) 817 return ret; 818 819 ret = RTL_R16(tp, LED_CTRL); 820 821 pm_runtime_put_sync(dev); 822 823 return ret; 824 } 825 826 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 827 char *buf, int buf_len) 828 { 829 struct pci_dev *pdev = tp->pci_dev; 830 char pdom[8], pfun[8]; 831 int domain; 832 833 domain = pci_domain_nr(pdev->bus); 834 if (domain) 835 snprintf(pdom, sizeof(pdom), "P%d", domain); 836 else 837 pdom[0] = '\0'; 838 839 if (pdev->multifunction) 840 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 841 else 842 pfun[0] = '\0'; 843 844 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 845 PCI_SLOT(pdev->devfn), pfun, idx); 846 } 847 848 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 849 { 850 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 851 if (type == ERIAR_OOB && 852 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 853 tp->mac_version == RTL_GIGA_MAC_VER_53)) 854 *cmd |= 0xf70 << 18; 855 } 856 857 DECLARE_RTL_COND(rtl_eriar_cond) 858 { 859 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 860 } 861 862 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 863 u32 val, int type) 864 { 865 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 866 867 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 868 return; 869 870 RTL_W32(tp, ERIDR, val); 871 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 872 RTL_W32(tp, ERIAR, cmd); 873 874 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 875 } 876 877 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 878 u32 val) 879 { 880 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 881 } 882 883 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 884 { 885 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 886 887 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 888 RTL_W32(tp, ERIAR, cmd); 889 890 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 891 RTL_R32(tp, ERIDR) : ~0; 892 } 893 894 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 895 { 896 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 897 } 898 899 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 900 { 901 u32 val = rtl_eri_read(tp, addr); 902 903 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 904 } 905 906 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 907 { 908 rtl_w0w1_eri(tp, addr, p, 0); 909 } 910 911 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 912 { 913 rtl_w0w1_eri(tp, addr, 0, m); 914 } 915 916 static bool rtl_ocp_reg_failure(u32 reg) 917 { 918 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 919 } 920 921 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 922 { 923 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 924 } 925 926 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 927 { 928 if (rtl_ocp_reg_failure(reg)) 929 return; 930 931 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 932 933 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 934 } 935 936 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 937 { 938 if (rtl_ocp_reg_failure(reg)) 939 return 0; 940 941 RTL_W32(tp, GPHY_OCP, reg << 15); 942 943 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 944 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 945 } 946 947 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 948 { 949 if (rtl_ocp_reg_failure(reg)) 950 return; 951 952 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 953 } 954 955 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 956 { 957 unsigned long flags; 958 959 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 960 __r8168_mac_ocp_write(tp, reg, data); 961 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 962 } 963 964 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 965 { 966 if (rtl_ocp_reg_failure(reg)) 967 return 0; 968 969 RTL_W32(tp, OCPDR, reg << 15); 970 971 return RTL_R32(tp, OCPDR); 972 } 973 974 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 975 { 976 unsigned long flags; 977 u16 val; 978 979 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 980 val = __r8168_mac_ocp_read(tp, reg); 981 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 982 983 return val; 984 } 985 986 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 987 u16 set) 988 { 989 unsigned long flags; 990 u16 data; 991 992 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 993 data = __r8168_mac_ocp_read(tp, reg); 994 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 995 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 996 } 997 998 /* Work around a hw issue with RTL8168g PHY, the quirk disables 999 * PHY MCU interrupts before PHY power-down. 1000 */ 1001 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1002 { 1003 switch (tp->mac_version) { 1004 case RTL_GIGA_MAC_VER_40: 1005 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1006 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1007 else 1008 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1009 break; 1010 default: 1011 break; 1012 } 1013 }; 1014 1015 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1016 { 1017 if (reg == 0x1f) { 1018 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1019 return; 1020 } 1021 1022 if (tp->ocp_base != OCP_STD_PHY_BASE) 1023 reg -= 0x10; 1024 1025 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1026 rtl8168g_phy_suspend_quirk(tp, value); 1027 1028 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1029 } 1030 1031 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1032 { 1033 if (reg == 0x1f) 1034 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1035 1036 if (tp->ocp_base != OCP_STD_PHY_BASE) 1037 reg -= 0x10; 1038 1039 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1040 } 1041 1042 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1043 { 1044 if (reg == 0x1f) { 1045 tp->ocp_base = value << 4; 1046 return; 1047 } 1048 1049 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1050 } 1051 1052 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1053 { 1054 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1055 } 1056 1057 DECLARE_RTL_COND(rtl_phyar_cond) 1058 { 1059 return RTL_R32(tp, PHYAR) & 0x80000000; 1060 } 1061 1062 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1063 { 1064 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1065 1066 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1067 /* 1068 * According to hardware specs a 20us delay is required after write 1069 * complete indication, but before sending next command. 1070 */ 1071 udelay(20); 1072 } 1073 1074 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1075 { 1076 int value; 1077 1078 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1079 1080 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1081 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1082 1083 /* 1084 * According to hardware specs a 20us delay is required after read 1085 * complete indication, but before sending next command. 1086 */ 1087 udelay(20); 1088 1089 return value; 1090 } 1091 1092 DECLARE_RTL_COND(rtl_ocpar_cond) 1093 { 1094 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1095 } 1096 1097 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1098 1099 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1100 { 1101 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1102 } 1103 1104 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1105 { 1106 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1107 } 1108 1109 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1110 { 1111 r8168dp_2_mdio_start(tp); 1112 1113 r8169_mdio_write(tp, reg, value); 1114 1115 r8168dp_2_mdio_stop(tp); 1116 } 1117 1118 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1119 { 1120 int value; 1121 1122 /* Work around issue with chip reporting wrong PHY ID */ 1123 if (reg == MII_PHYSID2) 1124 return 0xc912; 1125 1126 r8168dp_2_mdio_start(tp); 1127 1128 value = r8169_mdio_read(tp, reg); 1129 1130 r8168dp_2_mdio_stop(tp); 1131 1132 return value; 1133 } 1134 1135 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1136 { 1137 switch (tp->mac_version) { 1138 case RTL_GIGA_MAC_VER_28: 1139 case RTL_GIGA_MAC_VER_31: 1140 r8168dp_2_mdio_write(tp, location, val); 1141 break; 1142 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1143 r8168g_mdio_write(tp, location, val); 1144 break; 1145 default: 1146 r8169_mdio_write(tp, location, val); 1147 break; 1148 } 1149 } 1150 1151 static int rtl_readphy(struct rtl8169_private *tp, int location) 1152 { 1153 switch (tp->mac_version) { 1154 case RTL_GIGA_MAC_VER_28: 1155 case RTL_GIGA_MAC_VER_31: 1156 return r8168dp_2_mdio_read(tp, location); 1157 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1158 return r8168g_mdio_read(tp, location); 1159 default: 1160 return r8169_mdio_read(tp, location); 1161 } 1162 } 1163 1164 DECLARE_RTL_COND(rtl_ephyar_cond) 1165 { 1166 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1167 } 1168 1169 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1170 { 1171 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1172 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1173 1174 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1175 1176 udelay(10); 1177 } 1178 1179 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1180 { 1181 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1182 1183 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1184 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1185 } 1186 1187 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1188 { 1189 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1190 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1191 RTL_R32(tp, OCPDR) : ~0; 1192 } 1193 1194 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1195 { 1196 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1197 } 1198 1199 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1200 u32 data) 1201 { 1202 RTL_W32(tp, OCPDR, data); 1203 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1204 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1205 } 1206 1207 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1208 u32 data) 1209 { 1210 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1211 data, ERIAR_OOB); 1212 } 1213 1214 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1215 { 1216 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1217 1218 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1219 } 1220 1221 #define OOB_CMD_RESET 0x00 1222 #define OOB_CMD_DRIVER_START 0x05 1223 #define OOB_CMD_DRIVER_STOP 0x06 1224 1225 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1226 { 1227 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1228 } 1229 1230 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1231 { 1232 u16 reg; 1233 1234 reg = rtl8168_get_ocp_reg(tp); 1235 1236 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1237 } 1238 1239 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1240 { 1241 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1242 } 1243 1244 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1245 { 1246 return RTL_R8(tp, IBISR0) & 0x20; 1247 } 1248 1249 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1250 { 1251 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1252 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1253 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1254 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1255 } 1256 1257 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1258 { 1259 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1260 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1261 } 1262 1263 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1264 { 1265 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1266 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1267 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1268 } 1269 1270 static void rtl8168_driver_start(struct rtl8169_private *tp) 1271 { 1272 if (tp->dash_type == RTL_DASH_DP) 1273 rtl8168dp_driver_start(tp); 1274 else 1275 rtl8168ep_driver_start(tp); 1276 } 1277 1278 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1279 { 1280 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1281 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1282 } 1283 1284 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1285 { 1286 rtl8168ep_stop_cmac(tp); 1287 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1288 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1289 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1290 } 1291 1292 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1293 { 1294 if (tp->dash_type == RTL_DASH_DP) 1295 rtl8168dp_driver_stop(tp); 1296 else 1297 rtl8168ep_driver_stop(tp); 1298 } 1299 1300 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1301 { 1302 u16 reg = rtl8168_get_ocp_reg(tp); 1303 1304 return r8168dp_ocp_read(tp, reg) & BIT(15); 1305 } 1306 1307 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1308 { 1309 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1310 } 1311 1312 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1313 { 1314 switch (tp->dash_type) { 1315 case RTL_DASH_DP: 1316 return r8168dp_check_dash(tp); 1317 case RTL_DASH_EP: 1318 return r8168ep_check_dash(tp); 1319 default: 1320 return false; 1321 } 1322 } 1323 1324 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1325 { 1326 switch (tp->mac_version) { 1327 case RTL_GIGA_MAC_VER_28: 1328 case RTL_GIGA_MAC_VER_31: 1329 return RTL_DASH_DP; 1330 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1331 return RTL_DASH_EP; 1332 default: 1333 return RTL_DASH_NONE; 1334 } 1335 } 1336 1337 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1338 { 1339 switch (tp->mac_version) { 1340 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1341 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1342 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1343 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1344 if (enable) 1345 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1346 else 1347 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1348 break; 1349 default: 1350 break; 1351 } 1352 } 1353 1354 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1355 { 1356 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1357 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1358 } 1359 1360 DECLARE_RTL_COND(rtl_efusear_cond) 1361 { 1362 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1363 } 1364 1365 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1366 { 1367 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1368 1369 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1370 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1371 } 1372 1373 static u32 rtl_get_events(struct rtl8169_private *tp) 1374 { 1375 if (rtl_is_8125(tp)) 1376 return RTL_R32(tp, IntrStatus_8125); 1377 else 1378 return RTL_R16(tp, IntrStatus); 1379 } 1380 1381 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1382 { 1383 if (rtl_is_8125(tp)) 1384 RTL_W32(tp, IntrStatus_8125, bits); 1385 else 1386 RTL_W16(tp, IntrStatus, bits); 1387 } 1388 1389 static void rtl_irq_disable(struct rtl8169_private *tp) 1390 { 1391 if (rtl_is_8125(tp)) 1392 RTL_W32(tp, IntrMask_8125, 0); 1393 else 1394 RTL_W16(tp, IntrMask, 0); 1395 } 1396 1397 static void rtl_irq_enable(struct rtl8169_private *tp) 1398 { 1399 if (rtl_is_8125(tp)) 1400 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1401 else 1402 RTL_W16(tp, IntrMask, tp->irq_mask); 1403 } 1404 1405 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1406 { 1407 rtl_irq_disable(tp); 1408 rtl_ack_events(tp, 0xffffffff); 1409 rtl_pci_commit(tp); 1410 } 1411 1412 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1413 { 1414 struct phy_device *phydev = tp->phydev; 1415 1416 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1417 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1418 if (phydev->speed == SPEED_1000) { 1419 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1420 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1421 } else if (phydev->speed == SPEED_100) { 1422 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1423 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1424 } else { 1425 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1426 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1427 } 1428 rtl_reset_packet_filter(tp); 1429 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1430 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1431 if (phydev->speed == SPEED_1000) { 1432 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1433 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1434 } else { 1435 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1436 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1437 } 1438 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1439 if (phydev->speed == SPEED_10) { 1440 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1441 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1442 } else { 1443 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1444 } 1445 } 1446 } 1447 1448 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1449 1450 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1451 { 1452 struct rtl8169_private *tp = netdev_priv(dev); 1453 1454 wol->supported = WAKE_ANY; 1455 wol->wolopts = tp->saved_wolopts; 1456 } 1457 1458 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1459 { 1460 static const struct { 1461 u32 opt; 1462 u16 reg; 1463 u8 mask; 1464 } cfg[] = { 1465 { WAKE_PHY, Config3, LinkUp }, 1466 { WAKE_UCAST, Config5, UWF }, 1467 { WAKE_BCAST, Config5, BWF }, 1468 { WAKE_MCAST, Config5, MWF }, 1469 { WAKE_ANY, Config5, LanWake }, 1470 { WAKE_MAGIC, Config3, MagicPacket } 1471 }; 1472 unsigned int i, tmp = ARRAY_SIZE(cfg); 1473 unsigned long flags; 1474 u8 options; 1475 1476 rtl_unlock_config_regs(tp); 1477 1478 if (rtl_is_8168evl_up(tp)) { 1479 tmp--; 1480 if (wolopts & WAKE_MAGIC) 1481 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1482 else 1483 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1484 } else if (rtl_is_8125(tp)) { 1485 tmp--; 1486 if (wolopts & WAKE_MAGIC) 1487 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1488 else 1489 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1490 } 1491 1492 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1493 for (i = 0; i < tmp; i++) { 1494 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1495 if (wolopts & cfg[i].opt) 1496 options |= cfg[i].mask; 1497 RTL_W8(tp, cfg[i].reg, options); 1498 } 1499 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1500 1501 switch (tp->mac_version) { 1502 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1503 options = RTL_R8(tp, Config1) & ~PMEnable; 1504 if (wolopts) 1505 options |= PMEnable; 1506 RTL_W8(tp, Config1, options); 1507 break; 1508 case RTL_GIGA_MAC_VER_34: 1509 case RTL_GIGA_MAC_VER_37: 1510 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1511 if (wolopts) 1512 rtl_mod_config2(tp, 0, PME_SIGNAL); 1513 else 1514 rtl_mod_config2(tp, PME_SIGNAL, 0); 1515 break; 1516 default: 1517 break; 1518 } 1519 1520 rtl_lock_config_regs(tp); 1521 1522 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1523 1524 if (!tp->dash_enabled) { 1525 rtl_set_d3_pll_down(tp, !wolopts); 1526 tp->dev->wol_enabled = wolopts ? 1 : 0; 1527 } 1528 } 1529 1530 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1531 { 1532 struct rtl8169_private *tp = netdev_priv(dev); 1533 1534 if (wol->wolopts & ~WAKE_ANY) 1535 return -EINVAL; 1536 1537 tp->saved_wolopts = wol->wolopts; 1538 __rtl8169_set_wol(tp, tp->saved_wolopts); 1539 1540 return 0; 1541 } 1542 1543 static void rtl8169_get_drvinfo(struct net_device *dev, 1544 struct ethtool_drvinfo *info) 1545 { 1546 struct rtl8169_private *tp = netdev_priv(dev); 1547 struct rtl_fw *rtl_fw = tp->rtl_fw; 1548 1549 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1550 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1551 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1552 if (rtl_fw) 1553 strscpy(info->fw_version, rtl_fw->version, 1554 sizeof(info->fw_version)); 1555 } 1556 1557 static int rtl8169_get_regs_len(struct net_device *dev) 1558 { 1559 return R8169_REGS_SIZE; 1560 } 1561 1562 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1563 netdev_features_t features) 1564 { 1565 struct rtl8169_private *tp = netdev_priv(dev); 1566 1567 if (dev->mtu > TD_MSS_MAX) 1568 features &= ~NETIF_F_ALL_TSO; 1569 1570 if (dev->mtu > ETH_DATA_LEN && 1571 tp->mac_version > RTL_GIGA_MAC_VER_06) 1572 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1573 1574 return features; 1575 } 1576 1577 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1578 netdev_features_t features) 1579 { 1580 u32 rx_config = RTL_R32(tp, RxConfig); 1581 1582 if (features & NETIF_F_RXALL) 1583 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1584 else 1585 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1586 1587 if (rtl_is_8125(tp)) { 1588 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1589 rx_config |= RX_VLAN_8125; 1590 else 1591 rx_config &= ~RX_VLAN_8125; 1592 } 1593 1594 RTL_W32(tp, RxConfig, rx_config); 1595 } 1596 1597 static int rtl8169_set_features(struct net_device *dev, 1598 netdev_features_t features) 1599 { 1600 struct rtl8169_private *tp = netdev_priv(dev); 1601 1602 rtl_set_rx_config_features(tp, features); 1603 1604 if (features & NETIF_F_RXCSUM) 1605 tp->cp_cmd |= RxChkSum; 1606 else 1607 tp->cp_cmd &= ~RxChkSum; 1608 1609 if (!rtl_is_8125(tp)) { 1610 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1611 tp->cp_cmd |= RxVlan; 1612 else 1613 tp->cp_cmd &= ~RxVlan; 1614 } 1615 1616 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1617 rtl_pci_commit(tp); 1618 1619 return 0; 1620 } 1621 1622 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1623 { 1624 return (skb_vlan_tag_present(skb)) ? 1625 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1626 } 1627 1628 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1629 { 1630 u32 opts2 = le32_to_cpu(desc->opts2); 1631 1632 if (opts2 & RxVlanTag) 1633 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1634 } 1635 1636 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1637 void *p) 1638 { 1639 struct rtl8169_private *tp = netdev_priv(dev); 1640 u32 __iomem *data = tp->mmio_addr; 1641 u32 *dw = p; 1642 int i; 1643 1644 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1645 memcpy_fromio(dw++, data++, 4); 1646 } 1647 1648 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1649 "tx_packets", 1650 "rx_packets", 1651 "tx_errors", 1652 "rx_errors", 1653 "rx_missed", 1654 "align_errors", 1655 "tx_single_collisions", 1656 "tx_multi_collisions", 1657 "unicast", 1658 "broadcast", 1659 "multicast", 1660 "tx_aborted", 1661 "tx_underrun", 1662 }; 1663 1664 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1665 { 1666 switch (sset) { 1667 case ETH_SS_STATS: 1668 return ARRAY_SIZE(rtl8169_gstrings); 1669 default: 1670 return -EOPNOTSUPP; 1671 } 1672 } 1673 1674 DECLARE_RTL_COND(rtl_counters_cond) 1675 { 1676 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1677 } 1678 1679 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1680 { 1681 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1682 1683 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1684 rtl_pci_commit(tp); 1685 RTL_W32(tp, CounterAddrLow, cmd); 1686 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1687 1688 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1689 } 1690 1691 static void rtl8169_update_counters(struct rtl8169_private *tp) 1692 { 1693 u8 val = RTL_R8(tp, ChipCmd); 1694 1695 /* 1696 * Some chips are unable to dump tally counters when the receiver 1697 * is disabled. If 0xff chip may be in a PCI power-save state. 1698 */ 1699 if (val & CmdRxEnb && val != 0xff) 1700 rtl8169_do_counters(tp, CounterDump); 1701 } 1702 1703 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1704 { 1705 struct rtl8169_counters *counters = tp->counters; 1706 1707 /* 1708 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1709 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1710 * reset by a power cycle, while the counter values collected by the 1711 * driver are reset at every driver unload/load cycle. 1712 * 1713 * To make sure the HW values returned by @get_stats64 match the SW 1714 * values, we collect the initial values at first open(*) and use them 1715 * as offsets to normalize the values returned by @get_stats64. 1716 * 1717 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1718 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1719 * set at open time by rtl_hw_start. 1720 */ 1721 1722 if (tp->tc_offset.inited) 1723 return; 1724 1725 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1726 rtl8169_do_counters(tp, CounterReset); 1727 } else { 1728 rtl8169_update_counters(tp); 1729 tp->tc_offset.tx_errors = counters->tx_errors; 1730 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1731 tp->tc_offset.tx_aborted = counters->tx_aborted; 1732 tp->tc_offset.rx_missed = counters->rx_missed; 1733 } 1734 1735 tp->tc_offset.inited = true; 1736 } 1737 1738 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1739 struct ethtool_stats *stats, u64 *data) 1740 { 1741 struct rtl8169_private *tp = netdev_priv(dev); 1742 struct rtl8169_counters *counters; 1743 1744 counters = tp->counters; 1745 rtl8169_update_counters(tp); 1746 1747 data[0] = le64_to_cpu(counters->tx_packets); 1748 data[1] = le64_to_cpu(counters->rx_packets); 1749 data[2] = le64_to_cpu(counters->tx_errors); 1750 data[3] = le32_to_cpu(counters->rx_errors); 1751 data[4] = le16_to_cpu(counters->rx_missed); 1752 data[5] = le16_to_cpu(counters->align_errors); 1753 data[6] = le32_to_cpu(counters->tx_one_collision); 1754 data[7] = le32_to_cpu(counters->tx_multi_collision); 1755 data[8] = le64_to_cpu(counters->rx_unicast); 1756 data[9] = le64_to_cpu(counters->rx_broadcast); 1757 data[10] = le32_to_cpu(counters->rx_multicast); 1758 data[11] = le16_to_cpu(counters->tx_aborted); 1759 data[12] = le16_to_cpu(counters->tx_underun); 1760 } 1761 1762 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1763 { 1764 switch(stringset) { 1765 case ETH_SS_STATS: 1766 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1767 break; 1768 } 1769 } 1770 1771 /* 1772 * Interrupt coalescing 1773 * 1774 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1775 * > 8169, 8168 and 810x line of chipsets 1776 * 1777 * 8169, 8168, and 8136(810x) serial chipsets support it. 1778 * 1779 * > 2 - the Tx timer unit at gigabit speed 1780 * 1781 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1782 * (0xe0) bit 1 and bit 0. 1783 * 1784 * For 8169 1785 * bit[1:0] \ speed 1000M 100M 10M 1786 * 0 0 320ns 2.56us 40.96us 1787 * 0 1 2.56us 20.48us 327.7us 1788 * 1 0 5.12us 40.96us 655.4us 1789 * 1 1 10.24us 81.92us 1.31ms 1790 * 1791 * For the other 1792 * bit[1:0] \ speed 1000M 100M 10M 1793 * 0 0 5us 2.56us 40.96us 1794 * 0 1 40us 20.48us 327.7us 1795 * 1 0 80us 40.96us 655.4us 1796 * 1 1 160us 81.92us 1.31ms 1797 */ 1798 1799 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1800 struct rtl_coalesce_info { 1801 u32 speed; 1802 u32 scale_nsecs[4]; 1803 }; 1804 1805 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1806 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1807 1808 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1809 { SPEED_1000, COALESCE_DELAY(320) }, 1810 { SPEED_100, COALESCE_DELAY(2560) }, 1811 { SPEED_10, COALESCE_DELAY(40960) }, 1812 { 0 }, 1813 }; 1814 1815 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1816 { SPEED_1000, COALESCE_DELAY(5000) }, 1817 { SPEED_100, COALESCE_DELAY(2560) }, 1818 { SPEED_10, COALESCE_DELAY(40960) }, 1819 { 0 }, 1820 }; 1821 #undef COALESCE_DELAY 1822 1823 /* get rx/tx scale vector corresponding to current speed */ 1824 static const struct rtl_coalesce_info * 1825 rtl_coalesce_info(struct rtl8169_private *tp) 1826 { 1827 const struct rtl_coalesce_info *ci; 1828 1829 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1830 ci = rtl_coalesce_info_8169; 1831 else 1832 ci = rtl_coalesce_info_8168_8136; 1833 1834 /* if speed is unknown assume highest one */ 1835 if (tp->phydev->speed == SPEED_UNKNOWN) 1836 return ci; 1837 1838 for (; ci->speed; ci++) { 1839 if (tp->phydev->speed == ci->speed) 1840 return ci; 1841 } 1842 1843 return ERR_PTR(-ELNRNG); 1844 } 1845 1846 static int rtl_get_coalesce(struct net_device *dev, 1847 struct ethtool_coalesce *ec, 1848 struct kernel_ethtool_coalesce *kernel_coal, 1849 struct netlink_ext_ack *extack) 1850 { 1851 struct rtl8169_private *tp = netdev_priv(dev); 1852 const struct rtl_coalesce_info *ci; 1853 u32 scale, c_us, c_fr; 1854 u16 intrmit; 1855 1856 if (rtl_is_8125(tp)) 1857 return -EOPNOTSUPP; 1858 1859 memset(ec, 0, sizeof(*ec)); 1860 1861 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1862 ci = rtl_coalesce_info(tp); 1863 if (IS_ERR(ci)) 1864 return PTR_ERR(ci); 1865 1866 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1867 1868 intrmit = RTL_R16(tp, IntrMitigate); 1869 1870 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1871 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1872 1873 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1874 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1875 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1876 1877 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1878 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1879 1880 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1881 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1882 1883 return 0; 1884 } 1885 1886 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1887 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1888 u16 *cp01) 1889 { 1890 const struct rtl_coalesce_info *ci; 1891 u16 i; 1892 1893 ci = rtl_coalesce_info(tp); 1894 if (IS_ERR(ci)) 1895 return PTR_ERR(ci); 1896 1897 for (i = 0; i < 4; i++) { 1898 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1899 *cp01 = i; 1900 return ci->scale_nsecs[i]; 1901 } 1902 } 1903 1904 return -ERANGE; 1905 } 1906 1907 static int rtl_set_coalesce(struct net_device *dev, 1908 struct ethtool_coalesce *ec, 1909 struct kernel_ethtool_coalesce *kernel_coal, 1910 struct netlink_ext_ack *extack) 1911 { 1912 struct rtl8169_private *tp = netdev_priv(dev); 1913 u32 tx_fr = ec->tx_max_coalesced_frames; 1914 u32 rx_fr = ec->rx_max_coalesced_frames; 1915 u32 coal_usec_max, units; 1916 u16 w = 0, cp01 = 0; 1917 int scale; 1918 1919 if (rtl_is_8125(tp)) 1920 return -EOPNOTSUPP; 1921 1922 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1923 return -ERANGE; 1924 1925 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1926 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1927 if (scale < 0) 1928 return scale; 1929 1930 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1931 * not only when usecs=0 because of e.g. the following scenario: 1932 * 1933 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1934 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1935 * - then user does `ethtool -C eth0 rx-usecs 100` 1936 * 1937 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1938 * if we want to ignore rx_frames then it has to be set to 0. 1939 */ 1940 if (rx_fr == 1) 1941 rx_fr = 0; 1942 if (tx_fr == 1) 1943 tx_fr = 0; 1944 1945 /* HW requires time limit to be set if frame limit is set */ 1946 if ((tx_fr && !ec->tx_coalesce_usecs) || 1947 (rx_fr && !ec->rx_coalesce_usecs)) 1948 return -EINVAL; 1949 1950 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1951 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1952 1953 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1954 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1955 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1956 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1957 1958 RTL_W16(tp, IntrMitigate, w); 1959 1960 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1961 if (rtl_is_8168evl_up(tp)) { 1962 if (!rx_fr && !tx_fr) 1963 /* disable packet counter */ 1964 tp->cp_cmd |= PktCntrDisable; 1965 else 1966 tp->cp_cmd &= ~PktCntrDisable; 1967 } 1968 1969 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1970 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1971 rtl_pci_commit(tp); 1972 1973 return 0; 1974 } 1975 1976 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 1977 { 1978 struct rtl8169_private *tp = netdev_priv(dev); 1979 1980 if (!rtl_supports_eee(tp)) 1981 return -EOPNOTSUPP; 1982 1983 return phy_ethtool_get_eee(tp->phydev, data); 1984 } 1985 1986 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 1987 { 1988 struct rtl8169_private *tp = netdev_priv(dev); 1989 1990 if (!rtl_supports_eee(tp)) 1991 return -EOPNOTSUPP; 1992 1993 return phy_ethtool_set_eee(tp->phydev, data); 1994 } 1995 1996 static void rtl8169_get_ringparam(struct net_device *dev, 1997 struct ethtool_ringparam *data, 1998 struct kernel_ethtool_ringparam *kernel_data, 1999 struct netlink_ext_ack *extack) 2000 { 2001 data->rx_max_pending = NUM_RX_DESC; 2002 data->rx_pending = NUM_RX_DESC; 2003 data->tx_max_pending = NUM_TX_DESC; 2004 data->tx_pending = NUM_TX_DESC; 2005 } 2006 2007 static void rtl8169_get_pauseparam(struct net_device *dev, 2008 struct ethtool_pauseparam *data) 2009 { 2010 struct rtl8169_private *tp = netdev_priv(dev); 2011 bool tx_pause, rx_pause; 2012 2013 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2014 2015 data->autoneg = tp->phydev->autoneg; 2016 data->tx_pause = tx_pause ? 1 : 0; 2017 data->rx_pause = rx_pause ? 1 : 0; 2018 } 2019 2020 static int rtl8169_set_pauseparam(struct net_device *dev, 2021 struct ethtool_pauseparam *data) 2022 { 2023 struct rtl8169_private *tp = netdev_priv(dev); 2024 2025 if (dev->mtu > ETH_DATA_LEN) 2026 return -EOPNOTSUPP; 2027 2028 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2029 2030 return 0; 2031 } 2032 2033 static const struct ethtool_ops rtl8169_ethtool_ops = { 2034 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2035 ETHTOOL_COALESCE_MAX_FRAMES, 2036 .get_drvinfo = rtl8169_get_drvinfo, 2037 .get_regs_len = rtl8169_get_regs_len, 2038 .get_link = ethtool_op_get_link, 2039 .get_coalesce = rtl_get_coalesce, 2040 .set_coalesce = rtl_set_coalesce, 2041 .get_regs = rtl8169_get_regs, 2042 .get_wol = rtl8169_get_wol, 2043 .set_wol = rtl8169_set_wol, 2044 .get_strings = rtl8169_get_strings, 2045 .get_sset_count = rtl8169_get_sset_count, 2046 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2047 .get_ts_info = ethtool_op_get_ts_info, 2048 .nway_reset = phy_ethtool_nway_reset, 2049 .get_eee = rtl8169_get_eee, 2050 .set_eee = rtl8169_set_eee, 2051 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2052 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2053 .get_ringparam = rtl8169_get_ringparam, 2054 .get_pauseparam = rtl8169_get_pauseparam, 2055 .set_pauseparam = rtl8169_set_pauseparam, 2056 }; 2057 2058 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2059 { 2060 /* 2061 * The driver currently handles the 8168Bf and the 8168Be identically 2062 * but they can be identified more specifically through the test below 2063 * if needed: 2064 * 2065 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2066 * 2067 * Same thing for the 8101Eb and the 8101Ec: 2068 * 2069 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2070 */ 2071 static const struct rtl_mac_info { 2072 u16 mask; 2073 u16 val; 2074 enum mac_version ver; 2075 } mac_info[] = { 2076 /* 8125B family. */ 2077 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2078 2079 /* 8125A family. */ 2080 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2081 /* It seems only XID 609 made it to the mass market. 2082 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2083 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2084 */ 2085 2086 /* RTL8117 */ 2087 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2088 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2089 2090 /* 8168EP family. */ 2091 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2092 /* It seems this chip version never made it to 2093 * the wild. Let's disable detection. 2094 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2095 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2096 */ 2097 2098 /* 8168H family. */ 2099 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2100 /* It seems this chip version never made it to 2101 * the wild. Let's disable detection. 2102 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2103 */ 2104 2105 /* 8168G family. */ 2106 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2107 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2108 /* It seems this chip version never made it to 2109 * the wild. Let's disable detection. 2110 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2111 */ 2112 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2113 2114 /* 8168F family. */ 2115 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2116 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2117 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2118 2119 /* 8168E family. */ 2120 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2121 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2122 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2123 2124 /* 8168D family. */ 2125 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2126 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2127 2128 /* 8168DP family. */ 2129 /* It seems this early RTL8168dp version never made it to 2130 * the wild. Support has been removed. 2131 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2132 */ 2133 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2134 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2135 2136 /* 8168C family. */ 2137 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2138 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2139 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2140 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2141 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2142 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2143 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2144 2145 /* 8168B family. */ 2146 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2147 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2148 2149 /* 8101 family. */ 2150 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2151 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2152 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2153 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2154 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2155 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2156 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2157 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2158 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2159 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2160 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2161 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2162 2163 /* 8110 family. */ 2164 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2165 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2166 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2167 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2168 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2169 2170 /* Catch-all */ 2171 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2172 }; 2173 const struct rtl_mac_info *p = mac_info; 2174 enum mac_version ver; 2175 2176 while ((xid & p->mask) != p->val) 2177 p++; 2178 ver = p->ver; 2179 2180 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2181 if (ver == RTL_GIGA_MAC_VER_42) 2182 ver = RTL_GIGA_MAC_VER_43; 2183 else if (ver == RTL_GIGA_MAC_VER_46) 2184 ver = RTL_GIGA_MAC_VER_48; 2185 } 2186 2187 return ver; 2188 } 2189 2190 static void rtl_release_firmware(struct rtl8169_private *tp) 2191 { 2192 if (tp->rtl_fw) { 2193 rtl_fw_release_firmware(tp->rtl_fw); 2194 kfree(tp->rtl_fw); 2195 tp->rtl_fw = NULL; 2196 } 2197 } 2198 2199 void r8169_apply_firmware(struct rtl8169_private *tp) 2200 { 2201 int val; 2202 2203 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2204 if (tp->rtl_fw) { 2205 rtl_fw_write_firmware(tp, tp->rtl_fw); 2206 /* At least one firmware doesn't reset tp->ocp_base. */ 2207 tp->ocp_base = OCP_STD_PHY_BASE; 2208 2209 /* PHY soft reset may still be in progress */ 2210 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2211 !(val & BMCR_RESET), 2212 50000, 600000, true); 2213 } 2214 } 2215 2216 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2217 { 2218 /* Adjust EEE LED frequency */ 2219 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2220 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2221 2222 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2223 } 2224 2225 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2226 { 2227 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2228 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2229 } 2230 2231 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2232 { 2233 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2234 } 2235 2236 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2237 { 2238 rtl8125_set_eee_txidle_timer(tp); 2239 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2240 } 2241 2242 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2243 { 2244 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2245 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2246 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2247 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2248 } 2249 2250 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2251 { 2252 u16 data1, data2, ioffset; 2253 2254 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2255 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2256 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2257 2258 ioffset = (data2 >> 1) & 0x7ff8; 2259 ioffset |= data2 & 0x0007; 2260 if (data1 & BIT(7)) 2261 ioffset |= BIT(15); 2262 2263 return ioffset; 2264 } 2265 2266 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2267 { 2268 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 2269 return; 2270 2271 set_bit(flag, tp->wk.flags); 2272 schedule_work(&tp->wk.work); 2273 } 2274 2275 static void rtl8169_init_phy(struct rtl8169_private *tp) 2276 { 2277 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2278 2279 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2280 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2281 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2282 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2283 RTL_W8(tp, 0x82, 0x01); 2284 } 2285 2286 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2287 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2288 tp->pci_dev->subsystem_device == 0xe000) 2289 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2290 2291 /* We may have called phy_speed_down before */ 2292 phy_speed_up(tp->phydev); 2293 2294 genphy_soft_reset(tp->phydev); 2295 } 2296 2297 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2298 { 2299 rtl_unlock_config_regs(tp); 2300 2301 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2302 rtl_pci_commit(tp); 2303 2304 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2305 rtl_pci_commit(tp); 2306 2307 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2308 rtl_rar_exgmac_set(tp, addr); 2309 2310 rtl_lock_config_regs(tp); 2311 } 2312 2313 static int rtl_set_mac_address(struct net_device *dev, void *p) 2314 { 2315 struct rtl8169_private *tp = netdev_priv(dev); 2316 int ret; 2317 2318 ret = eth_mac_addr(dev, p); 2319 if (ret) 2320 return ret; 2321 2322 rtl_rar_set(tp, dev->dev_addr); 2323 2324 return 0; 2325 } 2326 2327 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2328 { 2329 switch (tp->mac_version) { 2330 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2331 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2332 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2333 break; 2334 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2335 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2336 case RTL_GIGA_MAC_VER_38: 2337 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2338 break; 2339 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2340 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2341 break; 2342 case RTL_GIGA_MAC_VER_61: 2343 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2344 break; 2345 case RTL_GIGA_MAC_VER_63: 2346 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2347 RX_PAUSE_SLOT_ON); 2348 break; 2349 default: 2350 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2351 break; 2352 } 2353 } 2354 2355 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2356 { 2357 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2358 } 2359 2360 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2361 { 2362 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2363 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2364 } 2365 2366 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2367 { 2368 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2369 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2370 } 2371 2372 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2373 { 2374 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2375 } 2376 2377 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2378 { 2379 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2380 } 2381 2382 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2383 { 2384 RTL_W8(tp, MaxTxPacketSize, 0x24); 2385 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2386 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2387 } 2388 2389 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2390 { 2391 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2392 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2393 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2394 } 2395 2396 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2397 { 2398 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2399 } 2400 2401 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2402 { 2403 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2404 } 2405 2406 static void rtl_jumbo_config(struct rtl8169_private *tp) 2407 { 2408 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2409 int readrq = 4096; 2410 2411 rtl_unlock_config_regs(tp); 2412 switch (tp->mac_version) { 2413 case RTL_GIGA_MAC_VER_17: 2414 if (jumbo) { 2415 readrq = 512; 2416 r8168b_1_hw_jumbo_enable(tp); 2417 } else { 2418 r8168b_1_hw_jumbo_disable(tp); 2419 } 2420 break; 2421 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2422 if (jumbo) { 2423 readrq = 512; 2424 r8168c_hw_jumbo_enable(tp); 2425 } else { 2426 r8168c_hw_jumbo_disable(tp); 2427 } 2428 break; 2429 case RTL_GIGA_MAC_VER_28: 2430 if (jumbo) 2431 r8168dp_hw_jumbo_enable(tp); 2432 else 2433 r8168dp_hw_jumbo_disable(tp); 2434 break; 2435 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2436 if (jumbo) 2437 r8168e_hw_jumbo_enable(tp); 2438 else 2439 r8168e_hw_jumbo_disable(tp); 2440 break; 2441 default: 2442 break; 2443 } 2444 rtl_lock_config_regs(tp); 2445 2446 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2447 pcie_set_readrq(tp->pci_dev, readrq); 2448 2449 /* Chip doesn't support pause in jumbo mode */ 2450 if (jumbo) { 2451 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2452 tp->phydev->advertising); 2453 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2454 tp->phydev->advertising); 2455 phy_start_aneg(tp->phydev); 2456 } 2457 } 2458 2459 DECLARE_RTL_COND(rtl_chipcmd_cond) 2460 { 2461 return RTL_R8(tp, ChipCmd) & CmdReset; 2462 } 2463 2464 static void rtl_hw_reset(struct rtl8169_private *tp) 2465 { 2466 RTL_W8(tp, ChipCmd, CmdReset); 2467 2468 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2469 } 2470 2471 static void rtl_request_firmware(struct rtl8169_private *tp) 2472 { 2473 struct rtl_fw *rtl_fw; 2474 2475 /* firmware loaded already or no firmware available */ 2476 if (tp->rtl_fw || !tp->fw_name) 2477 return; 2478 2479 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2480 if (!rtl_fw) 2481 return; 2482 2483 rtl_fw->phy_write = rtl_writephy; 2484 rtl_fw->phy_read = rtl_readphy; 2485 rtl_fw->mac_mcu_write = mac_mcu_write; 2486 rtl_fw->mac_mcu_read = mac_mcu_read; 2487 rtl_fw->fw_name = tp->fw_name; 2488 rtl_fw->dev = tp_to_dev(tp); 2489 2490 if (rtl_fw_request_firmware(rtl_fw)) 2491 kfree(rtl_fw); 2492 else 2493 tp->rtl_fw = rtl_fw; 2494 } 2495 2496 static void rtl_rx_close(struct rtl8169_private *tp) 2497 { 2498 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2499 } 2500 2501 DECLARE_RTL_COND(rtl_npq_cond) 2502 { 2503 return RTL_R8(tp, TxPoll) & NPQ; 2504 } 2505 2506 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2507 { 2508 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2509 } 2510 2511 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2512 { 2513 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2514 } 2515 2516 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2517 { 2518 /* IntrMitigate has new functionality on RTL8125 */ 2519 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2520 } 2521 2522 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2523 { 2524 switch (tp->mac_version) { 2525 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2526 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2527 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2528 break; 2529 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2530 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2531 break; 2532 case RTL_GIGA_MAC_VER_63: 2533 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2534 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2535 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2536 break; 2537 default: 2538 break; 2539 } 2540 } 2541 2542 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2543 { 2544 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2545 } 2546 2547 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2548 { 2549 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2550 fsleep(2000); 2551 rtl_wait_txrx_fifo_empty(tp); 2552 } 2553 2554 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2555 { 2556 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2557 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2558 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2559 2560 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2561 rtl_disable_rxdvgate(tp); 2562 } 2563 2564 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2565 { 2566 if (tp->dash_enabled) 2567 return; 2568 2569 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2570 tp->mac_version == RTL_GIGA_MAC_VER_33) 2571 rtl_ephy_write(tp, 0x19, 0xff64); 2572 2573 if (device_may_wakeup(tp_to_dev(tp))) { 2574 phy_speed_down(tp->phydev, false); 2575 rtl_wol_enable_rx(tp); 2576 } 2577 } 2578 2579 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2580 { 2581 u32 val = TX_DMA_BURST << TxDMAShift | 2582 InterFrameGap << TxInterFrameGapShift; 2583 2584 if (rtl_is_8168evl_up(tp)) 2585 val |= TXCFG_AUTO_FIFO; 2586 2587 RTL_W32(tp, TxConfig, val); 2588 } 2589 2590 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2591 { 2592 /* Low hurts. Let's disable the filtering. */ 2593 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2594 } 2595 2596 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2597 { 2598 /* 2599 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2600 * register to be written before TxDescAddrLow to work. 2601 * Switching from MMIO to I/O access fixes the issue as well. 2602 */ 2603 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2604 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2605 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2606 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2607 } 2608 2609 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2610 { 2611 u32 val; 2612 2613 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2614 val = 0x000fff00; 2615 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2616 val = 0x00ffff00; 2617 else 2618 return; 2619 2620 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2621 val |= 0xff; 2622 2623 RTL_W32(tp, 0x7c, val); 2624 } 2625 2626 static void rtl_set_rx_mode(struct net_device *dev) 2627 { 2628 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2629 /* Multicast hash filter */ 2630 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2631 struct rtl8169_private *tp = netdev_priv(dev); 2632 u32 tmp; 2633 2634 if (dev->flags & IFF_PROMISC) { 2635 rx_mode |= AcceptAllPhys; 2636 } else if (!(dev->flags & IFF_MULTICAST)) { 2637 rx_mode &= ~AcceptMulticast; 2638 } else if (dev->flags & IFF_ALLMULTI || 2639 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2640 /* accept all multicasts */ 2641 } else if (netdev_mc_empty(dev)) { 2642 rx_mode &= ~AcceptMulticast; 2643 } else { 2644 struct netdev_hw_addr *ha; 2645 2646 mc_filter[1] = mc_filter[0] = 0; 2647 netdev_for_each_mc_addr(ha, dev) { 2648 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2649 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2650 } 2651 2652 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2653 tmp = mc_filter[0]; 2654 mc_filter[0] = swab32(mc_filter[1]); 2655 mc_filter[1] = swab32(tmp); 2656 } 2657 } 2658 2659 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2660 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2661 2662 tmp = RTL_R32(tp, RxConfig); 2663 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2664 } 2665 2666 DECLARE_RTL_COND(rtl_csiar_cond) 2667 { 2668 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2669 } 2670 2671 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2672 { 2673 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2674 2675 RTL_W32(tp, CSIDR, value); 2676 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2677 CSIAR_BYTE_ENABLE | func << 16); 2678 2679 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2680 } 2681 2682 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2683 { 2684 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2685 2686 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2687 CSIAR_BYTE_ENABLE); 2688 2689 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2690 RTL_R32(tp, CSIDR) : ~0; 2691 } 2692 2693 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2694 { 2695 struct pci_dev *pdev = tp->pci_dev; 2696 u32 csi; 2697 2698 /* According to Realtek the value at config space address 0x070f 2699 * controls the L0s/L1 entrance latency. We try standard ECAM access 2700 * first and if it fails fall back to CSI. 2701 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2702 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2703 */ 2704 if (pdev->cfg_size > 0x070f && 2705 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2706 return; 2707 2708 netdev_notice_once(tp->dev, 2709 "No native access to PCI extended config space, falling back to CSI\n"); 2710 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2711 rtl_csi_write(tp, 0x070c, csi | val << 24); 2712 } 2713 2714 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2715 { 2716 /* L0 7us, L1 16us */ 2717 rtl_set_aspm_entry_latency(tp, 0x27); 2718 } 2719 2720 struct ephy_info { 2721 unsigned int offset; 2722 u16 mask; 2723 u16 bits; 2724 }; 2725 2726 static void __rtl_ephy_init(struct rtl8169_private *tp, 2727 const struct ephy_info *e, int len) 2728 { 2729 u16 w; 2730 2731 while (len-- > 0) { 2732 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2733 rtl_ephy_write(tp, e->offset, w); 2734 e++; 2735 } 2736 } 2737 2738 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2739 2740 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2741 { 2742 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2743 PCI_EXP_LNKCTL_CLKREQ_EN); 2744 } 2745 2746 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2747 { 2748 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2749 PCI_EXP_LNKCTL_CLKREQ_EN); 2750 } 2751 2752 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2753 { 2754 /* work around an issue when PCI reset occurs during L2/L3 state */ 2755 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2756 } 2757 2758 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2759 { 2760 /* Bits control which events trigger ASPM L1 exit: 2761 * Bit 12: rxdv 2762 * Bit 11: ltr_msg 2763 * Bit 10: txdma_poll 2764 * Bit 9: xadm 2765 * Bit 8: pktavi 2766 * Bit 7: txpla 2767 */ 2768 switch (tp->mac_version) { 2769 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2770 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2771 break; 2772 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2773 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2774 break; 2775 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2776 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2777 break; 2778 default: 2779 break; 2780 } 2781 } 2782 2783 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2784 { 2785 switch (tp->mac_version) { 2786 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2787 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2788 break; 2789 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2790 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2791 break; 2792 default: 2793 break; 2794 } 2795 } 2796 2797 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2798 { 2799 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2800 return; 2801 2802 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2803 if (enable && tp->aspm_manageable) { 2804 /* On these chip versions ASPM can even harm 2805 * bus communication of other PCI devices. 2806 */ 2807 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2808 tp->mac_version == RTL_GIGA_MAC_VER_43) 2809 return; 2810 2811 rtl_mod_config5(tp, 0, ASPM_en); 2812 rtl_mod_config2(tp, 0, ClkReqEn); 2813 2814 switch (tp->mac_version) { 2815 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2816 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2817 /* reset ephy tx/rx disable timer */ 2818 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2819 /* chip can trigger L1.2 */ 2820 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2821 break; 2822 default: 2823 break; 2824 } 2825 } else { 2826 switch (tp->mac_version) { 2827 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2828 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2829 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2830 break; 2831 default: 2832 break; 2833 } 2834 2835 rtl_mod_config2(tp, ClkReqEn, 0); 2836 rtl_mod_config5(tp, ASPM_en, 0); 2837 } 2838 } 2839 2840 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2841 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2842 { 2843 /* Usage of dynamic vs. static FIFO is controlled by bit 2844 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2845 */ 2846 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2847 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2848 } 2849 2850 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2851 u8 low, u8 high) 2852 { 2853 /* FIFO thresholds for pause flow control */ 2854 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2855 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2856 } 2857 2858 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2859 { 2860 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2861 } 2862 2863 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2864 { 2865 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2866 2867 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2868 2869 rtl_disable_clock_request(tp); 2870 } 2871 2872 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2873 { 2874 static const struct ephy_info e_info_8168cp[] = { 2875 { 0x01, 0, 0x0001 }, 2876 { 0x02, 0x0800, 0x1000 }, 2877 { 0x03, 0, 0x0042 }, 2878 { 0x06, 0x0080, 0x0000 }, 2879 { 0x07, 0, 0x2000 } 2880 }; 2881 2882 rtl_set_def_aspm_entry_latency(tp); 2883 2884 rtl_ephy_init(tp, e_info_8168cp); 2885 2886 __rtl_hw_start_8168cp(tp); 2887 } 2888 2889 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2890 { 2891 rtl_set_def_aspm_entry_latency(tp); 2892 2893 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2894 } 2895 2896 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2897 { 2898 rtl_set_def_aspm_entry_latency(tp); 2899 2900 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2901 2902 /* Magic. */ 2903 RTL_W8(tp, DBG_REG, 0x20); 2904 } 2905 2906 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2907 { 2908 static const struct ephy_info e_info_8168c_1[] = { 2909 { 0x02, 0x0800, 0x1000 }, 2910 { 0x03, 0, 0x0002 }, 2911 { 0x06, 0x0080, 0x0000 } 2912 }; 2913 2914 rtl_set_def_aspm_entry_latency(tp); 2915 2916 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2917 2918 rtl_ephy_init(tp, e_info_8168c_1); 2919 2920 __rtl_hw_start_8168cp(tp); 2921 } 2922 2923 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2924 { 2925 static const struct ephy_info e_info_8168c_2[] = { 2926 { 0x01, 0, 0x0001 }, 2927 { 0x03, 0x0400, 0x0020 } 2928 }; 2929 2930 rtl_set_def_aspm_entry_latency(tp); 2931 2932 rtl_ephy_init(tp, e_info_8168c_2); 2933 2934 __rtl_hw_start_8168cp(tp); 2935 } 2936 2937 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2938 { 2939 rtl_set_def_aspm_entry_latency(tp); 2940 2941 __rtl_hw_start_8168cp(tp); 2942 } 2943 2944 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2945 { 2946 rtl_set_def_aspm_entry_latency(tp); 2947 2948 rtl_disable_clock_request(tp); 2949 } 2950 2951 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2952 { 2953 static const struct ephy_info e_info_8168d_4[] = { 2954 { 0x0b, 0x0000, 0x0048 }, 2955 { 0x19, 0x0020, 0x0050 }, 2956 { 0x0c, 0x0100, 0x0020 }, 2957 { 0x10, 0x0004, 0x0000 }, 2958 }; 2959 2960 rtl_set_def_aspm_entry_latency(tp); 2961 2962 rtl_ephy_init(tp, e_info_8168d_4); 2963 2964 rtl_enable_clock_request(tp); 2965 } 2966 2967 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2968 { 2969 static const struct ephy_info e_info_8168e_1[] = { 2970 { 0x00, 0x0200, 0x0100 }, 2971 { 0x00, 0x0000, 0x0004 }, 2972 { 0x06, 0x0002, 0x0001 }, 2973 { 0x06, 0x0000, 0x0030 }, 2974 { 0x07, 0x0000, 0x2000 }, 2975 { 0x00, 0x0000, 0x0020 }, 2976 { 0x03, 0x5800, 0x2000 }, 2977 { 0x03, 0x0000, 0x0001 }, 2978 { 0x01, 0x0800, 0x1000 }, 2979 { 0x07, 0x0000, 0x4000 }, 2980 { 0x1e, 0x0000, 0x2000 }, 2981 { 0x19, 0xffff, 0xfe6c }, 2982 { 0x0a, 0x0000, 0x0040 } 2983 }; 2984 2985 rtl_set_def_aspm_entry_latency(tp); 2986 2987 rtl_ephy_init(tp, e_info_8168e_1); 2988 2989 rtl_disable_clock_request(tp); 2990 2991 /* Reset tx FIFO pointer */ 2992 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2993 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2994 2995 rtl_mod_config5(tp, Spi_en, 0); 2996 } 2997 2998 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2999 { 3000 static const struct ephy_info e_info_8168e_2[] = { 3001 { 0x09, 0x0000, 0x0080 }, 3002 { 0x19, 0x0000, 0x0224 }, 3003 { 0x00, 0x0000, 0x0004 }, 3004 { 0x0c, 0x3df0, 0x0200 }, 3005 }; 3006 3007 rtl_set_def_aspm_entry_latency(tp); 3008 3009 rtl_ephy_init(tp, e_info_8168e_2); 3010 3011 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3012 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3013 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3014 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3015 rtl_reset_packet_filter(tp); 3016 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3017 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3018 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3019 3020 rtl_disable_clock_request(tp); 3021 3022 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3023 3024 rtl8168_config_eee_mac(tp); 3025 3026 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3027 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3028 rtl_mod_config5(tp, Spi_en, 0); 3029 } 3030 3031 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3032 { 3033 rtl_set_def_aspm_entry_latency(tp); 3034 3035 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3036 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3037 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3038 rtl_reset_packet_filter(tp); 3039 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3040 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3041 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3042 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3043 3044 rtl_disable_clock_request(tp); 3045 3046 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3047 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3048 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3049 rtl_mod_config5(tp, Spi_en, 0); 3050 3051 rtl8168_config_eee_mac(tp); 3052 } 3053 3054 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3055 { 3056 static const struct ephy_info e_info_8168f_1[] = { 3057 { 0x06, 0x00c0, 0x0020 }, 3058 { 0x08, 0x0001, 0x0002 }, 3059 { 0x09, 0x0000, 0x0080 }, 3060 { 0x19, 0x0000, 0x0224 }, 3061 { 0x00, 0x0000, 0x0008 }, 3062 { 0x0c, 0x3df0, 0x0200 }, 3063 }; 3064 3065 rtl_hw_start_8168f(tp); 3066 3067 rtl_ephy_init(tp, e_info_8168f_1); 3068 } 3069 3070 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3071 { 3072 static const struct ephy_info e_info_8168f_1[] = { 3073 { 0x06, 0x00c0, 0x0020 }, 3074 { 0x0f, 0xffff, 0x5200 }, 3075 { 0x19, 0x0000, 0x0224 }, 3076 { 0x00, 0x0000, 0x0008 }, 3077 { 0x0c, 0x3df0, 0x0200 }, 3078 }; 3079 3080 rtl_hw_start_8168f(tp); 3081 rtl_pcie_state_l2l3_disable(tp); 3082 3083 rtl_ephy_init(tp, e_info_8168f_1); 3084 } 3085 3086 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3087 { 3088 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3089 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3090 3091 rtl_set_def_aspm_entry_latency(tp); 3092 3093 rtl_reset_packet_filter(tp); 3094 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3095 3096 rtl_disable_rxdvgate(tp); 3097 3098 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3099 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3100 3101 rtl8168_config_eee_mac(tp); 3102 3103 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3104 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3105 3106 rtl_pcie_state_l2l3_disable(tp); 3107 } 3108 3109 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3110 { 3111 static const struct ephy_info e_info_8168g_1[] = { 3112 { 0x00, 0x0008, 0x0000 }, 3113 { 0x0c, 0x3ff0, 0x0820 }, 3114 { 0x1e, 0x0000, 0x0001 }, 3115 { 0x19, 0x8000, 0x0000 } 3116 }; 3117 3118 rtl_hw_start_8168g(tp); 3119 rtl_ephy_init(tp, e_info_8168g_1); 3120 } 3121 3122 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3123 { 3124 static const struct ephy_info e_info_8168g_2[] = { 3125 { 0x00, 0x0008, 0x0000 }, 3126 { 0x0c, 0x3ff0, 0x0820 }, 3127 { 0x19, 0xffff, 0x7c00 }, 3128 { 0x1e, 0xffff, 0x20eb }, 3129 { 0x0d, 0xffff, 0x1666 }, 3130 { 0x00, 0xffff, 0x10a3 }, 3131 { 0x06, 0xffff, 0xf050 }, 3132 { 0x04, 0x0000, 0x0010 }, 3133 { 0x1d, 0x4000, 0x0000 }, 3134 }; 3135 3136 rtl_hw_start_8168g(tp); 3137 rtl_ephy_init(tp, e_info_8168g_2); 3138 } 3139 3140 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3141 { 3142 static const u16 fix_data[] = { 3143 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3144 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3145 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3146 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3147 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3148 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3149 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3150 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3151 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3152 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3153 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3154 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3155 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3156 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3157 }; 3158 unsigned long flags; 3159 int i; 3160 3161 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3162 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3163 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3164 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3165 } 3166 3167 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3168 { 3169 static const struct ephy_info e_info_8411_2[] = { 3170 { 0x00, 0x0008, 0x0000 }, 3171 { 0x0c, 0x37d0, 0x0820 }, 3172 { 0x1e, 0x0000, 0x0001 }, 3173 { 0x19, 0x8021, 0x0000 }, 3174 { 0x1e, 0x0000, 0x2000 }, 3175 { 0x0d, 0x0100, 0x0200 }, 3176 { 0x00, 0x0000, 0x0080 }, 3177 { 0x06, 0x0000, 0x0010 }, 3178 { 0x04, 0x0000, 0x0010 }, 3179 { 0x1d, 0x0000, 0x4000 }, 3180 }; 3181 3182 rtl_hw_start_8168g(tp); 3183 3184 rtl_ephy_init(tp, e_info_8411_2); 3185 3186 /* The following Realtek-provided magic fixes an issue with the RX unit 3187 * getting confused after the PHY having been powered-down. 3188 */ 3189 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3190 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3191 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3192 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3193 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3194 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3195 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3196 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3197 mdelay(3); 3198 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3199 3200 rtl8411b_fix_phy_down(tp); 3201 3202 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3203 3204 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3205 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3206 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3207 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3208 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3209 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3210 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3211 } 3212 3213 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3214 { 3215 static const struct ephy_info e_info_8168h_1[] = { 3216 { 0x1e, 0x0800, 0x0001 }, 3217 { 0x1d, 0x0000, 0x0800 }, 3218 { 0x05, 0xffff, 0x2089 }, 3219 { 0x06, 0xffff, 0x5881 }, 3220 { 0x04, 0xffff, 0x854a }, 3221 { 0x01, 0xffff, 0x068b } 3222 }; 3223 int rg_saw_cnt; 3224 3225 rtl_ephy_init(tp, e_info_8168h_1); 3226 3227 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3228 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3229 3230 rtl_set_def_aspm_entry_latency(tp); 3231 3232 rtl_reset_packet_filter(tp); 3233 3234 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3235 3236 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3237 3238 rtl_disable_rxdvgate(tp); 3239 3240 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3241 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3242 3243 rtl8168_config_eee_mac(tp); 3244 3245 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3246 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3247 3248 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3249 3250 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3251 3252 rtl_pcie_state_l2l3_disable(tp); 3253 3254 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3255 if (rg_saw_cnt > 0) { 3256 u16 sw_cnt_1ms_ini; 3257 3258 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3259 sw_cnt_1ms_ini &= 0x0fff; 3260 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3261 } 3262 3263 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3264 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3265 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3266 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3267 3268 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3269 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3270 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3271 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3272 } 3273 3274 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3275 { 3276 rtl8168ep_stop_cmac(tp); 3277 3278 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3279 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3280 3281 rtl_set_def_aspm_entry_latency(tp); 3282 3283 rtl_reset_packet_filter(tp); 3284 3285 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3286 3287 rtl_disable_rxdvgate(tp); 3288 3289 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3290 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3291 3292 rtl8168_config_eee_mac(tp); 3293 3294 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3295 3296 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3297 3298 rtl_pcie_state_l2l3_disable(tp); 3299 } 3300 3301 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3302 { 3303 static const struct ephy_info e_info_8168ep_3[] = { 3304 { 0x00, 0x0000, 0x0080 }, 3305 { 0x0d, 0x0100, 0x0200 }, 3306 { 0x19, 0x8021, 0x0000 }, 3307 { 0x1e, 0x0000, 0x2000 }, 3308 }; 3309 3310 rtl_ephy_init(tp, e_info_8168ep_3); 3311 3312 rtl_hw_start_8168ep(tp); 3313 3314 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3315 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3316 3317 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3318 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3319 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3320 } 3321 3322 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3323 { 3324 static const struct ephy_info e_info_8117[] = { 3325 { 0x19, 0x0040, 0x1100 }, 3326 { 0x59, 0x0040, 0x1100 }, 3327 }; 3328 int rg_saw_cnt; 3329 3330 rtl8168ep_stop_cmac(tp); 3331 rtl_ephy_init(tp, e_info_8117); 3332 3333 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3334 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3335 3336 rtl_set_def_aspm_entry_latency(tp); 3337 3338 rtl_reset_packet_filter(tp); 3339 3340 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3341 3342 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3343 3344 rtl_disable_rxdvgate(tp); 3345 3346 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3347 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3348 3349 rtl8168_config_eee_mac(tp); 3350 3351 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3352 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3353 3354 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3355 3356 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3357 3358 rtl_pcie_state_l2l3_disable(tp); 3359 3360 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3361 if (rg_saw_cnt > 0) { 3362 u16 sw_cnt_1ms_ini; 3363 3364 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3365 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3366 } 3367 3368 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3369 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3370 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3371 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3372 3373 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3374 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3375 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3376 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3377 3378 /* firmware is for MAC only */ 3379 r8169_apply_firmware(tp); 3380 } 3381 3382 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3383 { 3384 static const struct ephy_info e_info_8102e_1[] = { 3385 { 0x01, 0, 0x6e65 }, 3386 { 0x02, 0, 0x091f }, 3387 { 0x03, 0, 0xc2f9 }, 3388 { 0x06, 0, 0xafb5 }, 3389 { 0x07, 0, 0x0e00 }, 3390 { 0x19, 0, 0xec80 }, 3391 { 0x01, 0, 0x2e65 }, 3392 { 0x01, 0, 0x6e65 } 3393 }; 3394 u8 cfg1; 3395 3396 rtl_set_def_aspm_entry_latency(tp); 3397 3398 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3399 3400 RTL_W8(tp, Config1, 3401 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3402 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3403 3404 cfg1 = RTL_R8(tp, Config1); 3405 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3406 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3407 3408 rtl_ephy_init(tp, e_info_8102e_1); 3409 } 3410 3411 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3412 { 3413 rtl_set_def_aspm_entry_latency(tp); 3414 3415 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3416 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3417 } 3418 3419 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3420 { 3421 rtl_hw_start_8102e_2(tp); 3422 3423 rtl_ephy_write(tp, 0x03, 0xc2f9); 3424 } 3425 3426 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3427 { 3428 static const struct ephy_info e_info_8401[] = { 3429 { 0x01, 0xffff, 0x6fe5 }, 3430 { 0x03, 0xffff, 0x0599 }, 3431 { 0x06, 0xffff, 0xaf25 }, 3432 { 0x07, 0xffff, 0x8e68 }, 3433 }; 3434 3435 rtl_ephy_init(tp, e_info_8401); 3436 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3437 } 3438 3439 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3440 { 3441 static const struct ephy_info e_info_8105e_1[] = { 3442 { 0x07, 0, 0x4000 }, 3443 { 0x19, 0, 0x0200 }, 3444 { 0x19, 0, 0x0020 }, 3445 { 0x1e, 0, 0x2000 }, 3446 { 0x03, 0, 0x0001 }, 3447 { 0x19, 0, 0x0100 }, 3448 { 0x19, 0, 0x0004 }, 3449 { 0x0a, 0, 0x0020 } 3450 }; 3451 3452 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3453 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3454 3455 /* Disable Early Tally Counter */ 3456 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3457 3458 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3459 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3460 3461 rtl_ephy_init(tp, e_info_8105e_1); 3462 3463 rtl_pcie_state_l2l3_disable(tp); 3464 } 3465 3466 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3467 { 3468 rtl_hw_start_8105e_1(tp); 3469 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3470 } 3471 3472 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3473 { 3474 static const struct ephy_info e_info_8402[] = { 3475 { 0x19, 0xffff, 0xff64 }, 3476 { 0x1e, 0, 0x4000 } 3477 }; 3478 3479 rtl_set_def_aspm_entry_latency(tp); 3480 3481 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3482 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3483 3484 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3485 3486 rtl_ephy_init(tp, e_info_8402); 3487 3488 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3489 rtl_reset_packet_filter(tp); 3490 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3491 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3492 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3493 3494 /* disable EEE */ 3495 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3496 3497 rtl_pcie_state_l2l3_disable(tp); 3498 } 3499 3500 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3501 { 3502 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3503 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3504 3505 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3506 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3507 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3508 3509 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3510 rtl_set_aspm_entry_latency(tp, 0x2f); 3511 3512 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3513 3514 /* disable EEE */ 3515 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3516 3517 rtl_pcie_state_l2l3_disable(tp); 3518 } 3519 3520 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3521 { 3522 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3523 } 3524 3525 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3526 { 3527 rtl_pcie_state_l2l3_disable(tp); 3528 3529 RTL_W16(tp, 0x382, 0x221b); 3530 RTL_W8(tp, 0x4500, 0); 3531 RTL_W16(tp, 0x4800, 0); 3532 3533 /* disable UPS */ 3534 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3535 3536 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3537 3538 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3539 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3540 3541 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3542 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3543 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3544 3545 /* disable new tx descriptor format */ 3546 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3547 3548 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3549 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3550 else 3551 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3552 3553 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3554 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3555 else 3556 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3557 3558 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3559 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3560 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3561 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3562 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3563 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3564 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3565 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3566 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3567 3568 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3569 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3570 udelay(1); 3571 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3572 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3573 3574 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3575 3576 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3577 3578 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3579 rtl8125b_config_eee_mac(tp); 3580 else 3581 rtl8125a_config_eee_mac(tp); 3582 3583 rtl_disable_rxdvgate(tp); 3584 } 3585 3586 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3587 { 3588 static const struct ephy_info e_info_8125a_2[] = { 3589 { 0x04, 0xffff, 0xd000 }, 3590 { 0x0a, 0xffff, 0x8653 }, 3591 { 0x23, 0xffff, 0xab66 }, 3592 { 0x20, 0xffff, 0x9455 }, 3593 { 0x21, 0xffff, 0x99ff }, 3594 { 0x29, 0xffff, 0xfe04 }, 3595 3596 { 0x44, 0xffff, 0xd000 }, 3597 { 0x4a, 0xffff, 0x8653 }, 3598 { 0x63, 0xffff, 0xab66 }, 3599 { 0x60, 0xffff, 0x9455 }, 3600 { 0x61, 0xffff, 0x99ff }, 3601 { 0x69, 0xffff, 0xfe04 }, 3602 }; 3603 3604 rtl_set_def_aspm_entry_latency(tp); 3605 rtl_ephy_init(tp, e_info_8125a_2); 3606 rtl_hw_start_8125_common(tp); 3607 } 3608 3609 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3610 { 3611 static const struct ephy_info e_info_8125b[] = { 3612 { 0x0b, 0xffff, 0xa908 }, 3613 { 0x1e, 0xffff, 0x20eb }, 3614 { 0x4b, 0xffff, 0xa908 }, 3615 { 0x5e, 0xffff, 0x20eb }, 3616 { 0x22, 0x0030, 0x0020 }, 3617 { 0x62, 0x0030, 0x0020 }, 3618 }; 3619 3620 rtl_set_def_aspm_entry_latency(tp); 3621 rtl_ephy_init(tp, e_info_8125b); 3622 rtl_hw_start_8125_common(tp); 3623 } 3624 3625 static void rtl_hw_config(struct rtl8169_private *tp) 3626 { 3627 static const rtl_generic_fct hw_configs[] = { 3628 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3629 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3630 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3631 [RTL_GIGA_MAC_VER_10] = NULL, 3632 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3633 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3634 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3635 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3636 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3637 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3638 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3639 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3640 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3641 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3642 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3643 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3644 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3645 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3646 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3647 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3648 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3649 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3650 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3651 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3652 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3653 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3654 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3655 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3656 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3657 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3658 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3659 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3660 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3661 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3662 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3663 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3664 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3665 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3666 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3667 }; 3668 3669 if (hw_configs[tp->mac_version]) 3670 hw_configs[tp->mac_version](tp); 3671 } 3672 3673 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3674 { 3675 int i; 3676 3677 /* disable interrupt coalescing */ 3678 for (i = 0xa00; i < 0xb00; i += 4) 3679 RTL_W32(tp, i, 0); 3680 3681 rtl_hw_config(tp); 3682 } 3683 3684 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3685 { 3686 if (rtl_is_8168evl_up(tp)) 3687 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3688 else 3689 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3690 3691 rtl_hw_config(tp); 3692 3693 /* disable interrupt coalescing */ 3694 RTL_W16(tp, IntrMitigate, 0x0000); 3695 } 3696 3697 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3698 { 3699 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3700 3701 tp->cp_cmd |= PCIMulRW; 3702 3703 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3704 tp->mac_version == RTL_GIGA_MAC_VER_03) 3705 tp->cp_cmd |= EnAnaPLL; 3706 3707 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3708 3709 rtl8169_set_magic_reg(tp); 3710 3711 /* disable interrupt coalescing */ 3712 RTL_W16(tp, IntrMitigate, 0x0000); 3713 } 3714 3715 static void rtl_hw_start(struct rtl8169_private *tp) 3716 { 3717 rtl_unlock_config_regs(tp); 3718 /* disable aspm and clock request before ephy access */ 3719 rtl_hw_aspm_clkreq_enable(tp, false); 3720 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3721 3722 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3723 rtl_hw_start_8169(tp); 3724 else if (rtl_is_8125(tp)) 3725 rtl_hw_start_8125(tp); 3726 else 3727 rtl_hw_start_8168(tp); 3728 3729 rtl_enable_exit_l1(tp); 3730 rtl_hw_aspm_clkreq_enable(tp, true); 3731 rtl_set_rx_max_size(tp); 3732 rtl_set_rx_tx_desc_registers(tp); 3733 rtl_lock_config_regs(tp); 3734 3735 rtl_jumbo_config(tp); 3736 3737 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3738 rtl_pci_commit(tp); 3739 3740 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3741 rtl_init_rxcfg(tp); 3742 rtl_set_tx_config_registers(tp); 3743 rtl_set_rx_config_features(tp, tp->dev->features); 3744 rtl_set_rx_mode(tp->dev); 3745 rtl_irq_enable(tp); 3746 } 3747 3748 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3749 { 3750 struct rtl8169_private *tp = netdev_priv(dev); 3751 3752 dev->mtu = new_mtu; 3753 netdev_update_features(dev); 3754 rtl_jumbo_config(tp); 3755 3756 switch (tp->mac_version) { 3757 case RTL_GIGA_MAC_VER_61: 3758 case RTL_GIGA_MAC_VER_63: 3759 rtl8125_set_eee_txidle_timer(tp); 3760 break; 3761 default: 3762 break; 3763 } 3764 3765 return 0; 3766 } 3767 3768 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3769 { 3770 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3771 3772 desc->opts2 = 0; 3773 /* Force memory writes to complete before releasing descriptor */ 3774 dma_wmb(); 3775 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3776 } 3777 3778 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3779 struct RxDesc *desc) 3780 { 3781 struct device *d = tp_to_dev(tp); 3782 int node = dev_to_node(d); 3783 dma_addr_t mapping; 3784 struct page *data; 3785 3786 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3787 if (!data) 3788 return NULL; 3789 3790 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3791 if (unlikely(dma_mapping_error(d, mapping))) { 3792 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3793 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3794 return NULL; 3795 } 3796 3797 desc->addr = cpu_to_le64(mapping); 3798 rtl8169_mark_to_asic(desc); 3799 3800 return data; 3801 } 3802 3803 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3804 { 3805 int i; 3806 3807 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3808 dma_unmap_page(tp_to_dev(tp), 3809 le64_to_cpu(tp->RxDescArray[i].addr), 3810 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3811 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3812 tp->Rx_databuff[i] = NULL; 3813 tp->RxDescArray[i].addr = 0; 3814 tp->RxDescArray[i].opts1 = 0; 3815 } 3816 } 3817 3818 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3819 { 3820 int i; 3821 3822 for (i = 0; i < NUM_RX_DESC; i++) { 3823 struct page *data; 3824 3825 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3826 if (!data) { 3827 rtl8169_rx_clear(tp); 3828 return -ENOMEM; 3829 } 3830 tp->Rx_databuff[i] = data; 3831 } 3832 3833 /* mark as last descriptor in the ring */ 3834 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3835 3836 return 0; 3837 } 3838 3839 static int rtl8169_init_ring(struct rtl8169_private *tp) 3840 { 3841 rtl8169_init_ring_indexes(tp); 3842 3843 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3844 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3845 3846 return rtl8169_rx_fill(tp); 3847 } 3848 3849 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3850 { 3851 struct ring_info *tx_skb = tp->tx_skb + entry; 3852 struct TxDesc *desc = tp->TxDescArray + entry; 3853 3854 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3855 DMA_TO_DEVICE); 3856 memset(desc, 0, sizeof(*desc)); 3857 memset(tx_skb, 0, sizeof(*tx_skb)); 3858 } 3859 3860 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3861 unsigned int n) 3862 { 3863 unsigned int i; 3864 3865 for (i = 0; i < n; i++) { 3866 unsigned int entry = (start + i) % NUM_TX_DESC; 3867 struct ring_info *tx_skb = tp->tx_skb + entry; 3868 unsigned int len = tx_skb->len; 3869 3870 if (len) { 3871 struct sk_buff *skb = tx_skb->skb; 3872 3873 rtl8169_unmap_tx_skb(tp, entry); 3874 if (skb) 3875 dev_consume_skb_any(skb); 3876 } 3877 } 3878 } 3879 3880 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3881 { 3882 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3883 netdev_reset_queue(tp->dev); 3884 } 3885 3886 static void rtl8169_cleanup(struct rtl8169_private *tp) 3887 { 3888 napi_disable(&tp->napi); 3889 3890 /* Give a racing hard_start_xmit a few cycles to complete. */ 3891 synchronize_net(); 3892 3893 /* Disable interrupts */ 3894 rtl8169_irq_mask_and_ack(tp); 3895 3896 rtl_rx_close(tp); 3897 3898 switch (tp->mac_version) { 3899 case RTL_GIGA_MAC_VER_28: 3900 case RTL_GIGA_MAC_VER_31: 3901 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3902 break; 3903 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3904 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3905 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3906 break; 3907 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3908 rtl_enable_rxdvgate(tp); 3909 fsleep(2000); 3910 break; 3911 default: 3912 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3913 fsleep(100); 3914 break; 3915 } 3916 3917 rtl_hw_reset(tp); 3918 3919 rtl8169_tx_clear(tp); 3920 rtl8169_init_ring_indexes(tp); 3921 } 3922 3923 static void rtl_reset_work(struct rtl8169_private *tp) 3924 { 3925 int i; 3926 3927 netif_stop_queue(tp->dev); 3928 3929 rtl8169_cleanup(tp); 3930 3931 for (i = 0; i < NUM_RX_DESC; i++) 3932 rtl8169_mark_to_asic(tp->RxDescArray + i); 3933 3934 napi_enable(&tp->napi); 3935 rtl_hw_start(tp); 3936 } 3937 3938 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3939 { 3940 struct rtl8169_private *tp = netdev_priv(dev); 3941 3942 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 3943 } 3944 3945 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3946 void *addr, unsigned int entry, bool desc_own) 3947 { 3948 struct TxDesc *txd = tp->TxDescArray + entry; 3949 struct device *d = tp_to_dev(tp); 3950 dma_addr_t mapping; 3951 u32 opts1; 3952 int ret; 3953 3954 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3955 ret = dma_mapping_error(d, mapping); 3956 if (unlikely(ret)) { 3957 if (net_ratelimit()) 3958 netdev_err(tp->dev, "Failed to map TX data!\n"); 3959 return ret; 3960 } 3961 3962 txd->addr = cpu_to_le64(mapping); 3963 txd->opts2 = cpu_to_le32(opts[1]); 3964 3965 opts1 = opts[0] | len; 3966 if (entry == NUM_TX_DESC - 1) 3967 opts1 |= RingEnd; 3968 if (desc_own) 3969 opts1 |= DescOwn; 3970 txd->opts1 = cpu_to_le32(opts1); 3971 3972 tp->tx_skb[entry].len = len; 3973 3974 return 0; 3975 } 3976 3977 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3978 const u32 *opts, unsigned int entry) 3979 { 3980 struct skb_shared_info *info = skb_shinfo(skb); 3981 unsigned int cur_frag; 3982 3983 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 3984 const skb_frag_t *frag = info->frags + cur_frag; 3985 void *addr = skb_frag_address(frag); 3986 u32 len = skb_frag_size(frag); 3987 3988 entry = (entry + 1) % NUM_TX_DESC; 3989 3990 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 3991 goto err_out; 3992 } 3993 3994 return 0; 3995 3996 err_out: 3997 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 3998 return -EIO; 3999 } 4000 4001 static bool rtl_skb_is_udp(struct sk_buff *skb) 4002 { 4003 int no = skb_network_offset(skb); 4004 struct ipv6hdr *i6h, _i6h; 4005 struct iphdr *ih, _ih; 4006 4007 switch (vlan_get_protocol(skb)) { 4008 case htons(ETH_P_IP): 4009 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4010 return ih && ih->protocol == IPPROTO_UDP; 4011 case htons(ETH_P_IPV6): 4012 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4013 return i6h && i6h->nexthdr == IPPROTO_UDP; 4014 default: 4015 return false; 4016 } 4017 } 4018 4019 #define RTL_MIN_PATCH_LEN 47 4020 4021 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4022 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4023 struct sk_buff *skb) 4024 { 4025 unsigned int padto = 0, len = skb->len; 4026 4027 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4028 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4029 unsigned int trans_data_len = skb_tail_pointer(skb) - 4030 skb_transport_header(skb); 4031 4032 if (trans_data_len >= offsetof(struct udphdr, len) && 4033 trans_data_len < RTL_MIN_PATCH_LEN) { 4034 u16 dest = ntohs(udp_hdr(skb)->dest); 4035 4036 /* dest is a standard PTP port */ 4037 if (dest == 319 || dest == 320) 4038 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4039 } 4040 4041 if (trans_data_len < sizeof(struct udphdr)) 4042 padto = max_t(unsigned int, padto, 4043 len + sizeof(struct udphdr) - trans_data_len); 4044 } 4045 4046 return padto; 4047 } 4048 4049 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4050 struct sk_buff *skb) 4051 { 4052 unsigned int padto; 4053 4054 padto = rtl8125_quirk_udp_padto(tp, skb); 4055 4056 switch (tp->mac_version) { 4057 case RTL_GIGA_MAC_VER_34: 4058 case RTL_GIGA_MAC_VER_61: 4059 case RTL_GIGA_MAC_VER_63: 4060 padto = max_t(unsigned int, padto, ETH_ZLEN); 4061 break; 4062 default: 4063 break; 4064 } 4065 4066 return padto; 4067 } 4068 4069 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4070 { 4071 u32 mss = skb_shinfo(skb)->gso_size; 4072 4073 if (mss) { 4074 opts[0] |= TD_LSO; 4075 opts[0] |= mss << TD0_MSS_SHIFT; 4076 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4077 const struct iphdr *ip = ip_hdr(skb); 4078 4079 if (ip->protocol == IPPROTO_TCP) 4080 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4081 else if (ip->protocol == IPPROTO_UDP) 4082 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4083 else 4084 WARN_ON_ONCE(1); 4085 } 4086 } 4087 4088 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4089 struct sk_buff *skb, u32 *opts) 4090 { 4091 struct skb_shared_info *shinfo = skb_shinfo(skb); 4092 u32 mss = shinfo->gso_size; 4093 4094 if (mss) { 4095 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4096 opts[0] |= TD1_GTSENV4; 4097 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4098 if (skb_cow_head(skb, 0)) 4099 return false; 4100 4101 tcp_v6_gso_csum_prep(skb); 4102 opts[0] |= TD1_GTSENV6; 4103 } else { 4104 WARN_ON_ONCE(1); 4105 } 4106 4107 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4108 opts[1] |= mss << TD1_MSS_SHIFT; 4109 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4110 u8 ip_protocol; 4111 4112 switch (vlan_get_protocol(skb)) { 4113 case htons(ETH_P_IP): 4114 opts[1] |= TD1_IPv4_CS; 4115 ip_protocol = ip_hdr(skb)->protocol; 4116 break; 4117 4118 case htons(ETH_P_IPV6): 4119 opts[1] |= TD1_IPv6_CS; 4120 ip_protocol = ipv6_hdr(skb)->nexthdr; 4121 break; 4122 4123 default: 4124 ip_protocol = IPPROTO_RAW; 4125 break; 4126 } 4127 4128 if (ip_protocol == IPPROTO_TCP) 4129 opts[1] |= TD1_TCP_CS; 4130 else if (ip_protocol == IPPROTO_UDP) 4131 opts[1] |= TD1_UDP_CS; 4132 else 4133 WARN_ON_ONCE(1); 4134 4135 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4136 } else { 4137 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4138 4139 /* skb_padto would free the skb on error */ 4140 return !__skb_put_padto(skb, padto, false); 4141 } 4142 4143 return true; 4144 } 4145 4146 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4147 { 4148 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4149 } 4150 4151 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4152 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4153 { 4154 switch (tp->mac_version) { 4155 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4156 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4157 return false; 4158 default: 4159 return true; 4160 } 4161 } 4162 4163 static void rtl8169_doorbell(struct rtl8169_private *tp) 4164 { 4165 if (rtl_is_8125(tp)) 4166 RTL_W16(tp, TxPoll_8125, BIT(0)); 4167 else 4168 RTL_W8(tp, TxPoll, NPQ); 4169 } 4170 4171 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4172 struct net_device *dev) 4173 { 4174 unsigned int frags = skb_shinfo(skb)->nr_frags; 4175 struct rtl8169_private *tp = netdev_priv(dev); 4176 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4177 struct TxDesc *txd_first, *txd_last; 4178 bool stop_queue, door_bell; 4179 u32 opts[2]; 4180 4181 if (unlikely(!rtl_tx_slots_avail(tp))) { 4182 if (net_ratelimit()) 4183 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4184 goto err_stop_0; 4185 } 4186 4187 opts[1] = rtl8169_tx_vlan_tag(skb); 4188 opts[0] = 0; 4189 4190 if (!rtl_chip_supports_csum_v2(tp)) 4191 rtl8169_tso_csum_v1(skb, opts); 4192 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4193 goto err_dma_0; 4194 4195 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4196 entry, false))) 4197 goto err_dma_0; 4198 4199 txd_first = tp->TxDescArray + entry; 4200 4201 if (frags) { 4202 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4203 goto err_dma_1; 4204 entry = (entry + frags) % NUM_TX_DESC; 4205 } 4206 4207 txd_last = tp->TxDescArray + entry; 4208 txd_last->opts1 |= cpu_to_le32(LastFrag); 4209 tp->tx_skb[entry].skb = skb; 4210 4211 skb_tx_timestamp(skb); 4212 4213 /* Force memory writes to complete before releasing descriptor */ 4214 dma_wmb(); 4215 4216 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4217 4218 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4219 4220 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4221 smp_wmb(); 4222 4223 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4224 4225 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4226 R8169_TX_STOP_THRS, 4227 R8169_TX_START_THRS); 4228 if (door_bell || stop_queue) 4229 rtl8169_doorbell(tp); 4230 4231 return NETDEV_TX_OK; 4232 4233 err_dma_1: 4234 rtl8169_unmap_tx_skb(tp, entry); 4235 err_dma_0: 4236 dev_kfree_skb_any(skb); 4237 dev->stats.tx_dropped++; 4238 return NETDEV_TX_OK; 4239 4240 err_stop_0: 4241 netif_stop_queue(dev); 4242 dev->stats.tx_dropped++; 4243 return NETDEV_TX_BUSY; 4244 } 4245 4246 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4247 { 4248 struct skb_shared_info *info = skb_shinfo(skb); 4249 unsigned int nr_frags = info->nr_frags; 4250 4251 if (!nr_frags) 4252 return UINT_MAX; 4253 4254 return skb_frag_size(info->frags + nr_frags - 1); 4255 } 4256 4257 /* Workaround for hw issues with TSO on RTL8168evl */ 4258 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4259 netdev_features_t features) 4260 { 4261 /* IPv4 header has options field */ 4262 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4263 ip_hdrlen(skb) > sizeof(struct iphdr)) 4264 features &= ~NETIF_F_ALL_TSO; 4265 4266 /* IPv4 TCP header has options field */ 4267 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4268 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4269 features &= ~NETIF_F_ALL_TSO; 4270 4271 else if (rtl_last_frag_len(skb) <= 6) 4272 features &= ~NETIF_F_ALL_TSO; 4273 4274 return features; 4275 } 4276 4277 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4278 struct net_device *dev, 4279 netdev_features_t features) 4280 { 4281 struct rtl8169_private *tp = netdev_priv(dev); 4282 4283 if (skb_is_gso(skb)) { 4284 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4285 features = rtl8168evl_fix_tso(skb, features); 4286 4287 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4288 rtl_chip_supports_csum_v2(tp)) 4289 features &= ~NETIF_F_ALL_TSO; 4290 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4291 /* work around hw bug on some chip versions */ 4292 if (skb->len < ETH_ZLEN) 4293 features &= ~NETIF_F_CSUM_MASK; 4294 4295 if (rtl_quirk_packet_padto(tp, skb)) 4296 features &= ~NETIF_F_CSUM_MASK; 4297 4298 if (skb_transport_offset(skb) > TCPHO_MAX && 4299 rtl_chip_supports_csum_v2(tp)) 4300 features &= ~NETIF_F_CSUM_MASK; 4301 } 4302 4303 return vlan_features_check(skb, features); 4304 } 4305 4306 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4307 { 4308 struct rtl8169_private *tp = netdev_priv(dev); 4309 struct pci_dev *pdev = tp->pci_dev; 4310 int pci_status_errs; 4311 u16 pci_cmd; 4312 4313 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4314 4315 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4316 4317 if (net_ratelimit()) 4318 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4319 pci_cmd, pci_status_errs); 4320 4321 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4322 } 4323 4324 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4325 int budget) 4326 { 4327 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4328 struct sk_buff *skb; 4329 4330 dirty_tx = tp->dirty_tx; 4331 4332 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4333 unsigned int entry = dirty_tx % NUM_TX_DESC; 4334 u32 status; 4335 4336 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4337 if (status & DescOwn) 4338 break; 4339 4340 skb = tp->tx_skb[entry].skb; 4341 rtl8169_unmap_tx_skb(tp, entry); 4342 4343 if (skb) { 4344 pkts_compl++; 4345 bytes_compl += skb->len; 4346 napi_consume_skb(skb, budget); 4347 } 4348 dirty_tx++; 4349 } 4350 4351 if (tp->dirty_tx != dirty_tx) { 4352 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4353 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4354 4355 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4356 rtl_tx_slots_avail(tp), 4357 R8169_TX_START_THRS); 4358 /* 4359 * 8168 hack: TxPoll requests are lost when the Tx packets are 4360 * too close. Let's kick an extra TxPoll request when a burst 4361 * of start_xmit activity is detected (if it is not detected, 4362 * it is slow enough). -- FR 4363 * If skb is NULL then we come here again once a tx irq is 4364 * triggered after the last fragment is marked transmitted. 4365 */ 4366 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4367 rtl8169_doorbell(tp); 4368 } 4369 } 4370 4371 static inline int rtl8169_fragmented_frame(u32 status) 4372 { 4373 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4374 } 4375 4376 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4377 { 4378 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4379 4380 if (status == RxProtoTCP || status == RxProtoUDP) 4381 skb->ip_summed = CHECKSUM_UNNECESSARY; 4382 else 4383 skb_checksum_none_assert(skb); 4384 } 4385 4386 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4387 { 4388 struct device *d = tp_to_dev(tp); 4389 int count; 4390 4391 for (count = 0; count < budget; count++, tp->cur_rx++) { 4392 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4393 struct RxDesc *desc = tp->RxDescArray + entry; 4394 struct sk_buff *skb; 4395 const void *rx_buf; 4396 dma_addr_t addr; 4397 u32 status; 4398 4399 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4400 if (status & DescOwn) 4401 break; 4402 4403 /* This barrier is needed to keep us from reading 4404 * any other fields out of the Rx descriptor until 4405 * we know the status of DescOwn 4406 */ 4407 dma_rmb(); 4408 4409 if (unlikely(status & RxRES)) { 4410 if (net_ratelimit()) 4411 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4412 status); 4413 dev->stats.rx_errors++; 4414 if (status & (RxRWT | RxRUNT)) 4415 dev->stats.rx_length_errors++; 4416 if (status & RxCRC) 4417 dev->stats.rx_crc_errors++; 4418 4419 if (!(dev->features & NETIF_F_RXALL)) 4420 goto release_descriptor; 4421 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4422 goto release_descriptor; 4423 } 4424 4425 pkt_size = status & GENMASK(13, 0); 4426 if (likely(!(dev->features & NETIF_F_RXFCS))) 4427 pkt_size -= ETH_FCS_LEN; 4428 4429 /* The driver does not support incoming fragmented frames. 4430 * They are seen as a symptom of over-mtu sized frames. 4431 */ 4432 if (unlikely(rtl8169_fragmented_frame(status))) { 4433 dev->stats.rx_dropped++; 4434 dev->stats.rx_length_errors++; 4435 goto release_descriptor; 4436 } 4437 4438 skb = napi_alloc_skb(&tp->napi, pkt_size); 4439 if (unlikely(!skb)) { 4440 dev->stats.rx_dropped++; 4441 goto release_descriptor; 4442 } 4443 4444 addr = le64_to_cpu(desc->addr); 4445 rx_buf = page_address(tp->Rx_databuff[entry]); 4446 4447 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4448 prefetch(rx_buf); 4449 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4450 skb->tail += pkt_size; 4451 skb->len = pkt_size; 4452 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4453 4454 rtl8169_rx_csum(skb, status); 4455 skb->protocol = eth_type_trans(skb, dev); 4456 4457 rtl8169_rx_vlan_tag(desc, skb); 4458 4459 if (skb->pkt_type == PACKET_MULTICAST) 4460 dev->stats.multicast++; 4461 4462 napi_gro_receive(&tp->napi, skb); 4463 4464 dev_sw_netstats_rx_add(dev, pkt_size); 4465 release_descriptor: 4466 rtl8169_mark_to_asic(desc); 4467 } 4468 4469 return count; 4470 } 4471 4472 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4473 { 4474 struct rtl8169_private *tp = dev_instance; 4475 u32 status = rtl_get_events(tp); 4476 4477 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4478 return IRQ_NONE; 4479 4480 if (unlikely(status & SYSErr)) { 4481 rtl8169_pcierr_interrupt(tp->dev); 4482 goto out; 4483 } 4484 4485 if (status & LinkChg) 4486 phy_mac_interrupt(tp->phydev); 4487 4488 if (unlikely(status & RxFIFOOver && 4489 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4490 netif_stop_queue(tp->dev); 4491 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4492 } 4493 4494 if (napi_schedule_prep(&tp->napi)) { 4495 rtl_irq_disable(tp); 4496 __napi_schedule(&tp->napi); 4497 } 4498 out: 4499 rtl_ack_events(tp, status); 4500 4501 return IRQ_HANDLED; 4502 } 4503 4504 static void rtl_task(struct work_struct *work) 4505 { 4506 struct rtl8169_private *tp = 4507 container_of(work, struct rtl8169_private, wk.work); 4508 int ret; 4509 4510 rtnl_lock(); 4511 4512 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4513 goto out_unlock; 4514 4515 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4516 /* if chip isn't accessible, reset bus to revive it */ 4517 if (RTL_R32(tp, TxConfig) == ~0) { 4518 ret = pci_reset_bus(tp->pci_dev); 4519 if (ret < 0) { 4520 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4521 netif_device_detach(tp->dev); 4522 goto out_unlock; 4523 } 4524 } 4525 4526 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4527 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4528 PCIE_LINK_STATE_L0S); 4529 if (!ret) 4530 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4531 goto reset; 4532 } 4533 4534 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4535 reset: 4536 rtl_reset_work(tp); 4537 netif_wake_queue(tp->dev); 4538 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4539 rtl_reset_work(tp); 4540 } 4541 out_unlock: 4542 rtnl_unlock(); 4543 } 4544 4545 static int rtl8169_poll(struct napi_struct *napi, int budget) 4546 { 4547 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4548 struct net_device *dev = tp->dev; 4549 int work_done; 4550 4551 rtl_tx(dev, tp, budget); 4552 4553 work_done = rtl_rx(dev, tp, budget); 4554 4555 if (work_done < budget && napi_complete_done(napi, work_done)) 4556 rtl_irq_enable(tp); 4557 4558 return work_done; 4559 } 4560 4561 static void r8169_phylink_handler(struct net_device *ndev) 4562 { 4563 struct rtl8169_private *tp = netdev_priv(ndev); 4564 struct device *d = tp_to_dev(tp); 4565 4566 if (netif_carrier_ok(ndev)) { 4567 rtl_link_chg_patch(tp); 4568 pm_request_resume(d); 4569 netif_wake_queue(tp->dev); 4570 } else { 4571 /* In few cases rx is broken after link-down otherwise */ 4572 if (rtl_is_8125(tp)) 4573 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4574 pm_runtime_idle(d); 4575 } 4576 4577 phy_print_status(tp->phydev); 4578 } 4579 4580 static int r8169_phy_connect(struct rtl8169_private *tp) 4581 { 4582 struct phy_device *phydev = tp->phydev; 4583 phy_interface_t phy_mode; 4584 int ret; 4585 4586 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4587 PHY_INTERFACE_MODE_MII; 4588 4589 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4590 phy_mode); 4591 if (ret) 4592 return ret; 4593 4594 if (!tp->supports_gmii) 4595 phy_set_max_speed(phydev, SPEED_100); 4596 4597 phy_attached_info(phydev); 4598 4599 return 0; 4600 } 4601 4602 static void rtl8169_down(struct rtl8169_private *tp) 4603 { 4604 /* Clear all task flags */ 4605 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4606 4607 phy_stop(tp->phydev); 4608 4609 rtl8169_update_counters(tp); 4610 4611 pci_clear_master(tp->pci_dev); 4612 rtl_pci_commit(tp); 4613 4614 rtl8169_cleanup(tp); 4615 rtl_disable_exit_l1(tp); 4616 rtl_prepare_power_down(tp); 4617 4618 if (tp->dash_type != RTL_DASH_NONE) 4619 rtl8168_driver_stop(tp); 4620 } 4621 4622 static void rtl8169_up(struct rtl8169_private *tp) 4623 { 4624 if (tp->dash_type != RTL_DASH_NONE) 4625 rtl8168_driver_start(tp); 4626 4627 pci_set_master(tp->pci_dev); 4628 phy_init_hw(tp->phydev); 4629 phy_resume(tp->phydev); 4630 rtl8169_init_phy(tp); 4631 napi_enable(&tp->napi); 4632 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4633 rtl_reset_work(tp); 4634 4635 phy_start(tp->phydev); 4636 } 4637 4638 static int rtl8169_close(struct net_device *dev) 4639 { 4640 struct rtl8169_private *tp = netdev_priv(dev); 4641 struct pci_dev *pdev = tp->pci_dev; 4642 4643 pm_runtime_get_sync(&pdev->dev); 4644 4645 netif_stop_queue(dev); 4646 rtl8169_down(tp); 4647 rtl8169_rx_clear(tp); 4648 4649 cancel_work(&tp->wk.work); 4650 4651 free_irq(tp->irq, tp); 4652 4653 phy_disconnect(tp->phydev); 4654 4655 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4656 tp->RxPhyAddr); 4657 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4658 tp->TxPhyAddr); 4659 tp->TxDescArray = NULL; 4660 tp->RxDescArray = NULL; 4661 4662 pm_runtime_put_sync(&pdev->dev); 4663 4664 return 0; 4665 } 4666 4667 #ifdef CONFIG_NET_POLL_CONTROLLER 4668 static void rtl8169_netpoll(struct net_device *dev) 4669 { 4670 struct rtl8169_private *tp = netdev_priv(dev); 4671 4672 rtl8169_interrupt(tp->irq, tp); 4673 } 4674 #endif 4675 4676 static int rtl_open(struct net_device *dev) 4677 { 4678 struct rtl8169_private *tp = netdev_priv(dev); 4679 struct pci_dev *pdev = tp->pci_dev; 4680 unsigned long irqflags; 4681 int retval = -ENOMEM; 4682 4683 pm_runtime_get_sync(&pdev->dev); 4684 4685 /* 4686 * Rx and Tx descriptors needs 256 bytes alignment. 4687 * dma_alloc_coherent provides more. 4688 */ 4689 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4690 &tp->TxPhyAddr, GFP_KERNEL); 4691 if (!tp->TxDescArray) 4692 goto out; 4693 4694 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4695 &tp->RxPhyAddr, GFP_KERNEL); 4696 if (!tp->RxDescArray) 4697 goto err_free_tx_0; 4698 4699 retval = rtl8169_init_ring(tp); 4700 if (retval < 0) 4701 goto err_free_rx_1; 4702 4703 rtl_request_firmware(tp); 4704 4705 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4706 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4707 if (retval < 0) 4708 goto err_release_fw_2; 4709 4710 retval = r8169_phy_connect(tp); 4711 if (retval) 4712 goto err_free_irq; 4713 4714 rtl8169_up(tp); 4715 rtl8169_init_counter_offsets(tp); 4716 netif_start_queue(dev); 4717 out: 4718 pm_runtime_put_sync(&pdev->dev); 4719 4720 return retval; 4721 4722 err_free_irq: 4723 free_irq(tp->irq, tp); 4724 err_release_fw_2: 4725 rtl_release_firmware(tp); 4726 rtl8169_rx_clear(tp); 4727 err_free_rx_1: 4728 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4729 tp->RxPhyAddr); 4730 tp->RxDescArray = NULL; 4731 err_free_tx_0: 4732 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4733 tp->TxPhyAddr); 4734 tp->TxDescArray = NULL; 4735 goto out; 4736 } 4737 4738 static void 4739 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4740 { 4741 struct rtl8169_private *tp = netdev_priv(dev); 4742 struct pci_dev *pdev = tp->pci_dev; 4743 struct rtl8169_counters *counters = tp->counters; 4744 4745 pm_runtime_get_noresume(&pdev->dev); 4746 4747 netdev_stats_to_stats64(stats, &dev->stats); 4748 dev_fetch_sw_netstats(stats, dev->tstats); 4749 4750 /* 4751 * Fetch additional counter values missing in stats collected by driver 4752 * from tally counters. 4753 */ 4754 if (pm_runtime_active(&pdev->dev)) 4755 rtl8169_update_counters(tp); 4756 4757 /* 4758 * Subtract values fetched during initalization. 4759 * See rtl8169_init_counter_offsets for a description why we do that. 4760 */ 4761 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4762 le64_to_cpu(tp->tc_offset.tx_errors); 4763 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4764 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4765 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4766 le16_to_cpu(tp->tc_offset.tx_aborted); 4767 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4768 le16_to_cpu(tp->tc_offset.rx_missed); 4769 4770 pm_runtime_put_noidle(&pdev->dev); 4771 } 4772 4773 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4774 { 4775 netif_device_detach(tp->dev); 4776 4777 if (netif_running(tp->dev)) 4778 rtl8169_down(tp); 4779 } 4780 4781 static int rtl8169_runtime_resume(struct device *dev) 4782 { 4783 struct rtl8169_private *tp = dev_get_drvdata(dev); 4784 4785 rtl_rar_set(tp, tp->dev->dev_addr); 4786 __rtl8169_set_wol(tp, tp->saved_wolopts); 4787 4788 if (tp->TxDescArray) 4789 rtl8169_up(tp); 4790 4791 netif_device_attach(tp->dev); 4792 4793 return 0; 4794 } 4795 4796 static int rtl8169_suspend(struct device *device) 4797 { 4798 struct rtl8169_private *tp = dev_get_drvdata(device); 4799 4800 rtnl_lock(); 4801 rtl8169_net_suspend(tp); 4802 if (!device_may_wakeup(tp_to_dev(tp))) 4803 clk_disable_unprepare(tp->clk); 4804 rtnl_unlock(); 4805 4806 return 0; 4807 } 4808 4809 static int rtl8169_resume(struct device *device) 4810 { 4811 struct rtl8169_private *tp = dev_get_drvdata(device); 4812 4813 if (!device_may_wakeup(tp_to_dev(tp))) 4814 clk_prepare_enable(tp->clk); 4815 4816 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4817 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4818 rtl_init_rxcfg(tp); 4819 4820 return rtl8169_runtime_resume(device); 4821 } 4822 4823 static int rtl8169_runtime_suspend(struct device *device) 4824 { 4825 struct rtl8169_private *tp = dev_get_drvdata(device); 4826 4827 if (!tp->TxDescArray) { 4828 netif_device_detach(tp->dev); 4829 return 0; 4830 } 4831 4832 rtnl_lock(); 4833 __rtl8169_set_wol(tp, WAKE_PHY); 4834 rtl8169_net_suspend(tp); 4835 rtnl_unlock(); 4836 4837 return 0; 4838 } 4839 4840 static int rtl8169_runtime_idle(struct device *device) 4841 { 4842 struct rtl8169_private *tp = dev_get_drvdata(device); 4843 4844 if (tp->dash_enabled) 4845 return -EBUSY; 4846 4847 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4848 pm_schedule_suspend(device, 10000); 4849 4850 return -EBUSY; 4851 } 4852 4853 static const struct dev_pm_ops rtl8169_pm_ops = { 4854 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4855 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4856 rtl8169_runtime_idle) 4857 }; 4858 4859 static void rtl_shutdown(struct pci_dev *pdev) 4860 { 4861 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4862 4863 rtnl_lock(); 4864 rtl8169_net_suspend(tp); 4865 rtnl_unlock(); 4866 4867 /* Restore original MAC address */ 4868 rtl_rar_set(tp, tp->dev->perm_addr); 4869 4870 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 4871 pci_wake_from_d3(pdev, tp->saved_wolopts); 4872 pci_set_power_state(pdev, PCI_D3hot); 4873 } 4874 } 4875 4876 static void rtl_remove_one(struct pci_dev *pdev) 4877 { 4878 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4879 4880 if (pci_dev_run_wake(pdev)) 4881 pm_runtime_get_noresume(&pdev->dev); 4882 4883 cancel_work_sync(&tp->wk.work); 4884 4885 unregister_netdev(tp->dev); 4886 4887 if (tp->dash_type != RTL_DASH_NONE) 4888 rtl8168_driver_stop(tp); 4889 4890 rtl_release_firmware(tp); 4891 4892 /* restore original MAC address */ 4893 rtl_rar_set(tp, tp->dev->perm_addr); 4894 } 4895 4896 static const struct net_device_ops rtl_netdev_ops = { 4897 .ndo_open = rtl_open, 4898 .ndo_stop = rtl8169_close, 4899 .ndo_get_stats64 = rtl8169_get_stats64, 4900 .ndo_start_xmit = rtl8169_start_xmit, 4901 .ndo_features_check = rtl8169_features_check, 4902 .ndo_tx_timeout = rtl8169_tx_timeout, 4903 .ndo_validate_addr = eth_validate_addr, 4904 .ndo_change_mtu = rtl8169_change_mtu, 4905 .ndo_fix_features = rtl8169_fix_features, 4906 .ndo_set_features = rtl8169_set_features, 4907 .ndo_set_mac_address = rtl_set_mac_address, 4908 .ndo_eth_ioctl = phy_do_ioctl_running, 4909 .ndo_set_rx_mode = rtl_set_rx_mode, 4910 #ifdef CONFIG_NET_POLL_CONTROLLER 4911 .ndo_poll_controller = rtl8169_netpoll, 4912 #endif 4913 4914 }; 4915 4916 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4917 { 4918 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4919 4920 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4921 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4922 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4923 /* special workaround needed */ 4924 tp->irq_mask |= RxFIFOOver; 4925 else 4926 tp->irq_mask |= RxOverflow; 4927 } 4928 4929 static int rtl_alloc_irq(struct rtl8169_private *tp) 4930 { 4931 unsigned int flags; 4932 4933 switch (tp->mac_version) { 4934 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4935 rtl_unlock_config_regs(tp); 4936 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4937 rtl_lock_config_regs(tp); 4938 fallthrough; 4939 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4940 flags = PCI_IRQ_LEGACY; 4941 break; 4942 default: 4943 flags = PCI_IRQ_ALL_TYPES; 4944 break; 4945 } 4946 4947 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4948 } 4949 4950 static void rtl_read_mac_address(struct rtl8169_private *tp, 4951 u8 mac_addr[ETH_ALEN]) 4952 { 4953 /* Get MAC address */ 4954 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 4955 u32 value; 4956 4957 value = rtl_eri_read(tp, 0xe0); 4958 put_unaligned_le32(value, mac_addr); 4959 value = rtl_eri_read(tp, 0xe4); 4960 put_unaligned_le16(value, mac_addr + 4); 4961 } else if (rtl_is_8125(tp)) { 4962 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 4963 } 4964 } 4965 4966 DECLARE_RTL_COND(rtl_link_list_ready_cond) 4967 { 4968 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 4969 } 4970 4971 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 4972 { 4973 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 4974 } 4975 4976 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 4977 { 4978 struct rtl8169_private *tp = mii_bus->priv; 4979 4980 if (phyaddr > 0) 4981 return -ENODEV; 4982 4983 return rtl_readphy(tp, phyreg); 4984 } 4985 4986 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 4987 int phyreg, u16 val) 4988 { 4989 struct rtl8169_private *tp = mii_bus->priv; 4990 4991 if (phyaddr > 0) 4992 return -ENODEV; 4993 4994 rtl_writephy(tp, phyreg, val); 4995 4996 return 0; 4997 } 4998 4999 static int r8169_mdio_register(struct rtl8169_private *tp) 5000 { 5001 struct pci_dev *pdev = tp->pci_dev; 5002 struct mii_bus *new_bus; 5003 int ret; 5004 5005 new_bus = devm_mdiobus_alloc(&pdev->dev); 5006 if (!new_bus) 5007 return -ENOMEM; 5008 5009 new_bus->name = "r8169"; 5010 new_bus->priv = tp; 5011 new_bus->parent = &pdev->dev; 5012 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5013 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5014 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5015 5016 new_bus->read = r8169_mdio_read_reg; 5017 new_bus->write = r8169_mdio_write_reg; 5018 5019 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5020 if (ret) 5021 return ret; 5022 5023 tp->phydev = mdiobus_get_phy(new_bus, 0); 5024 if (!tp->phydev) { 5025 return -ENODEV; 5026 } else if (!tp->phydev->drv) { 5027 /* Most chip versions fail with the genphy driver. 5028 * Therefore ensure that the dedicated PHY driver is loaded. 5029 */ 5030 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5031 tp->phydev->phy_id); 5032 return -EUNATCH; 5033 } 5034 5035 tp->phydev->mac_managed_pm = true; 5036 if (rtl_supports_eee(tp)) 5037 linkmode_copy(tp->phydev->advertising_eee, 5038 tp->phydev->supported_eee); 5039 phy_support_asym_pause(tp->phydev); 5040 5041 /* PHY will be woken up in rtl_open() */ 5042 phy_suspend(tp->phydev); 5043 5044 return 0; 5045 } 5046 5047 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5048 { 5049 rtl_enable_rxdvgate(tp); 5050 5051 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5052 msleep(1); 5053 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5054 5055 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5056 r8168g_wait_ll_share_fifo_ready(tp); 5057 5058 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5059 r8168g_wait_ll_share_fifo_ready(tp); 5060 } 5061 5062 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5063 { 5064 rtl_enable_rxdvgate(tp); 5065 5066 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5067 msleep(1); 5068 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5069 5070 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5071 r8168g_wait_ll_share_fifo_ready(tp); 5072 5073 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5074 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5075 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5076 r8168g_wait_ll_share_fifo_ready(tp); 5077 } 5078 5079 static void rtl_hw_initialize(struct rtl8169_private *tp) 5080 { 5081 switch (tp->mac_version) { 5082 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5083 rtl8168ep_stop_cmac(tp); 5084 fallthrough; 5085 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5086 rtl_hw_init_8168g(tp); 5087 break; 5088 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5089 rtl_hw_init_8125(tp); 5090 break; 5091 default: 5092 break; 5093 } 5094 } 5095 5096 static int rtl_jumbo_max(struct rtl8169_private *tp) 5097 { 5098 /* Non-GBit versions don't support jumbo frames */ 5099 if (!tp->supports_gmii) 5100 return 0; 5101 5102 switch (tp->mac_version) { 5103 /* RTL8169 */ 5104 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5105 return JUMBO_7K; 5106 /* RTL8168b */ 5107 case RTL_GIGA_MAC_VER_11: 5108 case RTL_GIGA_MAC_VER_17: 5109 return JUMBO_4K; 5110 /* RTL8168c */ 5111 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5112 return JUMBO_6K; 5113 default: 5114 return JUMBO_9K; 5115 } 5116 } 5117 5118 static void rtl_init_mac_address(struct rtl8169_private *tp) 5119 { 5120 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5121 struct net_device *dev = tp->dev; 5122 int rc; 5123 5124 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5125 if (!rc) 5126 goto done; 5127 5128 rtl_read_mac_address(tp, mac_addr); 5129 if (is_valid_ether_addr(mac_addr)) 5130 goto done; 5131 5132 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5133 if (is_valid_ether_addr(mac_addr)) 5134 goto done; 5135 5136 eth_random_addr(mac_addr); 5137 dev->addr_assign_type = NET_ADDR_RANDOM; 5138 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5139 done: 5140 eth_hw_addr_set(dev, mac_addr); 5141 rtl_rar_set(tp, mac_addr); 5142 } 5143 5144 /* register is set if system vendor successfully tested ASPM 1.2 */ 5145 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5146 { 5147 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5148 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5149 return true; 5150 5151 return false; 5152 } 5153 5154 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5155 { 5156 struct rtl8169_private *tp; 5157 int jumbo_max, region, rc; 5158 enum mac_version chipset; 5159 struct net_device *dev; 5160 u32 txconfig; 5161 u16 xid; 5162 5163 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5164 if (!dev) 5165 return -ENOMEM; 5166 5167 SET_NETDEV_DEV(dev, &pdev->dev); 5168 dev->netdev_ops = &rtl_netdev_ops; 5169 tp = netdev_priv(dev); 5170 tp->dev = dev; 5171 tp->pci_dev = pdev; 5172 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5173 tp->ocp_base = OCP_STD_PHY_BASE; 5174 5175 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5176 raw_spin_lock_init(&tp->config25_lock); 5177 raw_spin_lock_init(&tp->mac_ocp_lock); 5178 mutex_init(&tp->led_lock); 5179 5180 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5181 struct pcpu_sw_netstats); 5182 if (!dev->tstats) 5183 return -ENOMEM; 5184 5185 /* Get the *optional* external "ether_clk" used on some boards */ 5186 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5187 if (IS_ERR(tp->clk)) 5188 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5189 5190 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5191 rc = pcim_enable_device(pdev); 5192 if (rc < 0) 5193 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5194 5195 if (pcim_set_mwi(pdev) < 0) 5196 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5197 5198 /* use first MMIO region */ 5199 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5200 if (region < 0) 5201 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5202 5203 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5204 if (rc < 0) 5205 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5206 5207 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5208 5209 txconfig = RTL_R32(tp, TxConfig); 5210 if (txconfig == ~0U) 5211 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5212 5213 xid = (txconfig >> 20) & 0xfcf; 5214 5215 /* Identify chip attached to board */ 5216 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5217 if (chipset == RTL_GIGA_MAC_NONE) 5218 return dev_err_probe(&pdev->dev, -ENODEV, 5219 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5220 xid); 5221 tp->mac_version = chipset; 5222 5223 /* Disable ASPM L1 as that cause random device stop working 5224 * problems as well as full system hangs for some PCIe devices users. 5225 */ 5226 if (rtl_aspm_is_safe(tp)) 5227 rc = 0; 5228 else 5229 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5230 tp->aspm_manageable = !rc; 5231 5232 tp->dash_type = rtl_get_dash_type(tp); 5233 tp->dash_enabled = rtl_dash_is_enabled(tp); 5234 5235 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5236 5237 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5238 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5239 dev->features |= NETIF_F_HIGHDMA; 5240 5241 rtl_init_rxcfg(tp); 5242 5243 rtl8169_irq_mask_and_ack(tp); 5244 5245 rtl_hw_initialize(tp); 5246 5247 rtl_hw_reset(tp); 5248 5249 rc = rtl_alloc_irq(tp); 5250 if (rc < 0) 5251 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5252 5253 tp->irq = pci_irq_vector(pdev, 0); 5254 5255 INIT_WORK(&tp->wk.work, rtl_task); 5256 5257 rtl_init_mac_address(tp); 5258 5259 dev->ethtool_ops = &rtl8169_ethtool_ops; 5260 5261 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5262 5263 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5264 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5265 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5266 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5267 5268 /* 5269 * Pretend we are using VLANs; This bypasses a nasty bug where 5270 * Interrupts stop flowing on high load on 8110SCd controllers. 5271 */ 5272 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5273 /* Disallow toggling */ 5274 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5275 5276 if (rtl_chip_supports_csum_v2(tp)) 5277 dev->hw_features |= NETIF_F_IPV6_CSUM; 5278 5279 dev->features |= dev->hw_features; 5280 5281 /* There has been a number of reports that using SG/TSO results in 5282 * tx timeouts. However for a lot of people SG/TSO works fine. 5283 * Therefore disable both features by default, but allow users to 5284 * enable them. Use at own risk! 5285 */ 5286 if (rtl_chip_supports_csum_v2(tp)) { 5287 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5288 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5289 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5290 } else { 5291 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5292 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5293 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5294 } 5295 5296 dev->hw_features |= NETIF_F_RXALL; 5297 dev->hw_features |= NETIF_F_RXFCS; 5298 5299 netdev_sw_irq_coalesce_default_on(dev); 5300 5301 /* configure chip for default features */ 5302 rtl8169_set_features(dev, dev->features); 5303 5304 if (!tp->dash_enabled) { 5305 rtl_set_d3_pll_down(tp, true); 5306 } else { 5307 rtl_set_d3_pll_down(tp, false); 5308 dev->wol_enabled = 1; 5309 } 5310 5311 jumbo_max = rtl_jumbo_max(tp); 5312 if (jumbo_max) 5313 dev->max_mtu = jumbo_max; 5314 5315 rtl_set_irq_mask(tp); 5316 5317 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5318 5319 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5320 &tp->counters_phys_addr, 5321 GFP_KERNEL); 5322 if (!tp->counters) 5323 return -ENOMEM; 5324 5325 pci_set_drvdata(pdev, tp); 5326 5327 rc = r8169_mdio_register(tp); 5328 if (rc) 5329 return rc; 5330 5331 rc = register_netdev(dev); 5332 if (rc) 5333 return rc; 5334 5335 if (IS_ENABLED(CONFIG_R8169_LEDS) && 5336 tp->mac_version > RTL_GIGA_MAC_VER_06 && 5337 tp->mac_version < RTL_GIGA_MAC_VER_61) 5338 rtl8168_init_leds(dev); 5339 5340 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5341 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5342 5343 if (jumbo_max) 5344 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5345 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5346 "ok" : "ko"); 5347 5348 if (tp->dash_type != RTL_DASH_NONE) { 5349 netdev_info(dev, "DASH %s\n", 5350 tp->dash_enabled ? "enabled" : "disabled"); 5351 rtl8168_driver_start(tp); 5352 } 5353 5354 if (pci_dev_run_wake(pdev)) 5355 pm_runtime_put_sync(&pdev->dev); 5356 5357 return 0; 5358 } 5359 5360 static struct pci_driver rtl8169_pci_driver = { 5361 .name = KBUILD_MODNAME, 5362 .id_table = rtl8169_pci_tbl, 5363 .probe = rtl_init_one, 5364 .remove = rtl_remove_one, 5365 .shutdown = rtl_shutdown, 5366 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5367 }; 5368 5369 module_pci_driver(rtl8169_pci_driver); 5370