1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 59 60 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 61 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 62 63 #define R8169_REGS_SIZE 256 64 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 65 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 66 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 67 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 68 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 69 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 70 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 71 72 #define OCP_STD_PHY_BASE 0xa400 73 74 #define RTL_CFG_NO_GBIT 1 75 76 /* write/read MMIO register */ 77 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 81 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 82 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 83 84 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 89 static const struct { 90 const char *name; 91 const char *fw_name; 92 } rtl_chip_infos[] = { 93 /* PCI devices. */ 94 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 95 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 96 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 97 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 98 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 99 /* PCI-E devices. */ 100 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 102 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 103 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 104 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 105 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 106 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 108 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 109 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 115 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 116 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 117 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 118 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 119 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 121 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 122 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 123 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 124 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 125 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 126 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 127 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 128 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 129 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 130 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 131 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 132 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 133 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 134 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 135 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 136 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 137 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 138 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 139 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 140 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 141 }; 142 143 static const struct pci_device_id rtl8169_pci_tbl[] = { 144 { PCI_VDEVICE(REALTEK, 0x2502) }, 145 { PCI_VDEVICE(REALTEK, 0x2600) }, 146 { PCI_VDEVICE(REALTEK, 0x8129) }, 147 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 148 { PCI_VDEVICE(REALTEK, 0x8161) }, 149 { PCI_VDEVICE(REALTEK, 0x8162) }, 150 { PCI_VDEVICE(REALTEK, 0x8167) }, 151 { PCI_VDEVICE(REALTEK, 0x8168) }, 152 { PCI_VDEVICE(NCUBE, 0x8168) }, 153 { PCI_VDEVICE(REALTEK, 0x8169) }, 154 { PCI_VENDOR_ID_DLINK, 0x4300, 155 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 156 { PCI_VDEVICE(DLINK, 0x4300) }, 157 { PCI_VDEVICE(DLINK, 0x4302) }, 158 { PCI_VDEVICE(AT, 0xc107) }, 159 { PCI_VDEVICE(USR, 0x0116) }, 160 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 161 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 162 { PCI_VDEVICE(REALTEK, 0x8125) }, 163 { PCI_VDEVICE(REALTEK, 0x8126) }, 164 { PCI_VDEVICE(REALTEK, 0x3000) }, 165 {} 166 }; 167 168 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 169 170 enum rtl_registers { 171 MAC0 = 0, /* Ethernet hardware address. */ 172 MAC4 = 4, 173 MAR0 = 8, /* Multicast filter. */ 174 CounterAddrLow = 0x10, 175 CounterAddrHigh = 0x14, 176 TxDescStartAddrLow = 0x20, 177 TxDescStartAddrHigh = 0x24, 178 TxHDescStartAddrLow = 0x28, 179 TxHDescStartAddrHigh = 0x2c, 180 FLASH = 0x30, 181 ERSR = 0x36, 182 ChipCmd = 0x37, 183 TxPoll = 0x38, 184 IntrMask = 0x3c, 185 IntrStatus = 0x3e, 186 187 TxConfig = 0x40, 188 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 189 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 190 191 RxConfig = 0x44, 192 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 193 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 194 #define RXCFG_FIFO_SHIFT 13 195 /* No threshold before first PCI xfer */ 196 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 197 #define RX_EARLY_OFF (1 << 11) 198 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 199 #define RXCFG_DMA_SHIFT 8 200 /* Unlimited maximum PCI burst. */ 201 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 202 203 Cfg9346 = 0x50, 204 Config0 = 0x51, 205 Config1 = 0x52, 206 Config2 = 0x53, 207 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 208 209 Config3 = 0x54, 210 Config4 = 0x55, 211 Config5 = 0x56, 212 PHYAR = 0x60, 213 PHYstatus = 0x6c, 214 RxMaxSize = 0xda, 215 CPlusCmd = 0xe0, 216 IntrMitigate = 0xe2, 217 218 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 219 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 220 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 221 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 222 223 #define RTL_COALESCE_T_MAX 0x0fU 224 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 225 226 RxDescAddrLow = 0xe4, 227 RxDescAddrHigh = 0xe8, 228 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 229 230 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 231 232 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 233 234 #define TxPacketMax (8064 >> 7) 235 #define EarlySize 0x27 236 237 FuncEvent = 0xf0, 238 FuncEventMask = 0xf4, 239 FuncPresetState = 0xf8, 240 IBCR0 = 0xf8, 241 IBCR2 = 0xf9, 242 IBIMR0 = 0xfa, 243 IBISR0 = 0xfb, 244 FuncForceEvent = 0xfc, 245 }; 246 247 enum rtl8168_8101_registers { 248 CSIDR = 0x64, 249 CSIAR = 0x68, 250 #define CSIAR_FLAG 0x80000000 251 #define CSIAR_WRITE_CMD 0x80000000 252 #define CSIAR_BYTE_ENABLE 0x0000f000 253 #define CSIAR_ADDR_MASK 0x00000fff 254 PMCH = 0x6f, 255 #define D3COLD_NO_PLL_DOWN BIT(7) 256 #define D3HOT_NO_PLL_DOWN BIT(6) 257 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 258 EPHYAR = 0x80, 259 #define EPHYAR_FLAG 0x80000000 260 #define EPHYAR_WRITE_CMD 0x80000000 261 #define EPHYAR_REG_MASK 0x1f 262 #define EPHYAR_REG_SHIFT 16 263 #define EPHYAR_DATA_MASK 0xffff 264 DLLPR = 0xd0, 265 #define PFM_EN (1 << 6) 266 #define TX_10M_PS_EN (1 << 7) 267 DBG_REG = 0xd1, 268 #define FIX_NAK_1 (1 << 4) 269 #define FIX_NAK_2 (1 << 3) 270 TWSI = 0xd2, 271 MCU = 0xd3, 272 #define NOW_IS_OOB (1 << 7) 273 #define TX_EMPTY (1 << 5) 274 #define RX_EMPTY (1 << 4) 275 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 276 #define EN_NDP (1 << 3) 277 #define EN_OOB_RESET (1 << 2) 278 #define LINK_LIST_RDY (1 << 1) 279 EFUSEAR = 0xdc, 280 #define EFUSEAR_FLAG 0x80000000 281 #define EFUSEAR_WRITE_CMD 0x80000000 282 #define EFUSEAR_READ_CMD 0x00000000 283 #define EFUSEAR_REG_MASK 0x03ff 284 #define EFUSEAR_REG_SHIFT 8 285 #define EFUSEAR_DATA_MASK 0xff 286 MISC_1 = 0xf2, 287 #define PFM_D3COLD_EN (1 << 6) 288 }; 289 290 enum rtl8168_registers { 291 LED_CTRL = 0x18, 292 LED_FREQ = 0x1a, 293 EEE_LED = 0x1b, 294 ERIDR = 0x70, 295 ERIAR = 0x74, 296 #define ERIAR_FLAG 0x80000000 297 #define ERIAR_WRITE_CMD 0x80000000 298 #define ERIAR_READ_CMD 0x00000000 299 #define ERIAR_ADDR_BYTE_ALIGN 4 300 #define ERIAR_TYPE_SHIFT 16 301 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 303 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_MASK_SHIFT 12 306 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 308 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 311 EPHY_RXER_NUM = 0x7c, 312 OCPDR = 0xb0, /* OCP GPHY access */ 313 #define OCPDR_WRITE_CMD 0x80000000 314 #define OCPDR_READ_CMD 0x00000000 315 #define OCPDR_REG_MASK 0x7f 316 #define OCPDR_GPHY_REG_SHIFT 16 317 #define OCPDR_DATA_MASK 0xffff 318 OCPAR = 0xb4, 319 #define OCPAR_FLAG 0x80000000 320 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 321 #define OCPAR_GPHY_READ_CMD 0x0000f060 322 GPHY_OCP = 0xb8, 323 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 324 MISC = 0xf0, /* 8168e only. */ 325 #define TXPLA_RST (1 << 29) 326 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 327 #define PWM_EN (1 << 22) 328 #define RXDV_GATED_EN (1 << 19) 329 #define EARLY_TALLY_EN (1 << 16) 330 }; 331 332 enum rtl8125_registers { 333 LEDSEL0 = 0x18, 334 INT_CFG0_8125 = 0x34, 335 #define INT_CFG0_ENABLE_8125 BIT(0) 336 #define INT_CFG0_CLKREQEN BIT(3) 337 IntrMask_8125 = 0x38, 338 IntrStatus_8125 = 0x3c, 339 INT_CFG1_8125 = 0x7a, 340 LEDSEL2 = 0x84, 341 LEDSEL1 = 0x86, 342 TxPoll_8125 = 0x90, 343 LEDSEL3 = 0x96, 344 MAC0_BKP = 0x19e0, 345 EEE_TXIDLE_TIMER_8125 = 0x6048, 346 }; 347 348 #define LEDSEL_MASK_8125 0x23f 349 350 #define RX_VLAN_INNER_8125 BIT(22) 351 #define RX_VLAN_OUTER_8125 BIT(23) 352 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 353 354 #define RX_FETCH_DFLT_8125 (8 << 27) 355 356 enum rtl_register_content { 357 /* InterruptStatusBits */ 358 SYSErr = 0x8000, 359 PCSTimeout = 0x4000, 360 SWInt = 0x0100, 361 TxDescUnavail = 0x0080, 362 RxFIFOOver = 0x0040, 363 LinkChg = 0x0020, 364 RxOverflow = 0x0010, 365 TxErr = 0x0008, 366 TxOK = 0x0004, 367 RxErr = 0x0002, 368 RxOK = 0x0001, 369 370 /* RxStatusDesc */ 371 RxRWT = (1 << 22), 372 RxRES = (1 << 21), 373 RxRUNT = (1 << 20), 374 RxCRC = (1 << 19), 375 376 /* ChipCmdBits */ 377 StopReq = 0x80, 378 CmdReset = 0x10, 379 CmdRxEnb = 0x08, 380 CmdTxEnb = 0x04, 381 RxBufEmpty = 0x01, 382 383 /* TXPoll register p.5 */ 384 HPQ = 0x80, /* Poll cmd on the high prio queue */ 385 NPQ = 0x40, /* Poll cmd on the low prio queue */ 386 FSWInt = 0x01, /* Forced software interrupt */ 387 388 /* Cfg9346Bits */ 389 Cfg9346_Lock = 0x00, 390 Cfg9346_Unlock = 0xc0, 391 392 /* rx_mode_bits */ 393 AcceptErr = 0x20, 394 AcceptRunt = 0x10, 395 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 396 AcceptBroadcast = 0x08, 397 AcceptMulticast = 0x04, 398 AcceptMyPhys = 0x02, 399 AcceptAllPhys = 0x01, 400 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 401 #define RX_CONFIG_ACCEPT_MASK 0x3f 402 403 /* TxConfigBits */ 404 TxInterFrameGapShift = 24, 405 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 406 407 /* Config1 register p.24 */ 408 LEDS1 = (1 << 7), 409 LEDS0 = (1 << 6), 410 Speed_down = (1 << 4), 411 MEMMAP = (1 << 3), 412 IOMAP = (1 << 2), 413 VPD = (1 << 1), 414 PMEnable = (1 << 0), /* Power Management Enable */ 415 416 /* Config2 register p. 25 */ 417 ClkReqEn = (1 << 7), /* Clock Request Enable */ 418 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 419 PCI_Clock_66MHz = 0x01, 420 PCI_Clock_33MHz = 0x00, 421 422 /* Config3 register p.25 */ 423 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 424 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 425 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 426 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 427 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 428 429 /* Config4 register */ 430 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 431 432 /* Config5 register p.27 */ 433 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 434 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 435 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 436 Spi_en = (1 << 3), 437 LanWake = (1 << 1), /* LanWake enable/disable */ 438 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 439 ASPM_en = (1 << 0), /* ASPM enable */ 440 441 /* CPlusCmd p.31 */ 442 EnableBist = (1 << 15), // 8168 8101 443 Mac_dbgo_oe = (1 << 14), // 8168 8101 444 EnAnaPLL = (1 << 14), // 8169 445 Normal_mode = (1 << 13), // unused 446 Force_half_dup = (1 << 12), // 8168 8101 447 Force_rxflow_en = (1 << 11), // 8168 8101 448 Force_txflow_en = (1 << 10), // 8168 8101 449 Cxpl_dbg_sel = (1 << 9), // 8168 8101 450 ASF = (1 << 8), // 8168 8101 451 PktCntrDisable = (1 << 7), // 8168 8101 452 Mac_dbgo_sel = 0x001c, // 8168 453 RxVlan = (1 << 6), 454 RxChkSum = (1 << 5), 455 PCIDAC = (1 << 4), 456 PCIMulRW = (1 << 3), 457 #define INTT_MASK GENMASK(1, 0) 458 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 459 460 /* rtl8169_PHYstatus */ 461 TBI_Enable = 0x80, 462 TxFlowCtrl = 0x40, 463 RxFlowCtrl = 0x20, 464 _1000bpsF = 0x10, 465 _100bps = 0x08, 466 _10bps = 0x04, 467 LinkStatus = 0x02, 468 FullDup = 0x01, 469 470 /* ResetCounterCommand */ 471 CounterReset = 0x1, 472 473 /* DumpCounterCommand */ 474 CounterDump = 0x8, 475 476 /* magic enable v2 */ 477 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 478 }; 479 480 enum rtl_desc_bit { 481 /* First doubleword. */ 482 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 483 RingEnd = (1 << 30), /* End of descriptor ring */ 484 FirstFrag = (1 << 29), /* First segment of a packet */ 485 LastFrag = (1 << 28), /* Final segment of a packet */ 486 }; 487 488 /* Generic case. */ 489 enum rtl_tx_desc_bit { 490 /* First doubleword. */ 491 TD_LSO = (1 << 27), /* Large Send Offload */ 492 #define TD_MSS_MAX 0x07ffu /* MSS value */ 493 494 /* Second doubleword. */ 495 TxVlanTag = (1 << 17), /* Add VLAN tag */ 496 }; 497 498 /* 8169, 8168b and 810x except 8102e. */ 499 enum rtl_tx_desc_bit_0 { 500 /* First doubleword. */ 501 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 502 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 503 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 504 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 505 }; 506 507 /* 8102e, 8168c and beyond. */ 508 enum rtl_tx_desc_bit_1 { 509 /* First doubleword. */ 510 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 511 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 512 #define GTTCPHO_SHIFT 18 513 #define GTTCPHO_MAX 0x7f 514 515 /* Second doubleword. */ 516 #define TCPHO_SHIFT 18 517 #define TCPHO_MAX 0x3ff 518 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 519 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 520 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 521 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 522 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 523 }; 524 525 enum rtl_rx_desc_bit { 526 /* Rx private */ 527 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 528 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 529 530 #define RxProtoUDP (PID1) 531 #define RxProtoTCP (PID0) 532 #define RxProtoIP (PID1 | PID0) 533 #define RxProtoMask RxProtoIP 534 535 IPFail = (1 << 16), /* IP checksum failed */ 536 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 537 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 538 539 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 540 541 RxVlanTag = (1 << 16), /* VLAN tag available */ 542 }; 543 544 #define RTL_GSO_MAX_SIZE_V1 32000 545 #define RTL_GSO_MAX_SEGS_V1 24 546 #define RTL_GSO_MAX_SIZE_V2 64000 547 #define RTL_GSO_MAX_SEGS_V2 64 548 549 struct TxDesc { 550 __le32 opts1; 551 __le32 opts2; 552 __le64 addr; 553 }; 554 555 struct RxDesc { 556 __le32 opts1; 557 __le32 opts2; 558 __le64 addr; 559 }; 560 561 struct ring_info { 562 struct sk_buff *skb; 563 u32 len; 564 }; 565 566 struct rtl8169_counters { 567 __le64 tx_packets; 568 __le64 rx_packets; 569 __le64 tx_errors; 570 __le32 rx_errors; 571 __le16 rx_missed; 572 __le16 align_errors; 573 __le32 tx_one_collision; 574 __le32 tx_multi_collision; 575 __le64 rx_unicast; 576 __le64 rx_broadcast; 577 __le32 rx_multicast; 578 __le16 tx_aborted; 579 __le16 tx_underun; 580 }; 581 582 struct rtl8169_tc_offsets { 583 bool inited; 584 __le64 tx_errors; 585 __le32 tx_multi_collision; 586 __le16 tx_aborted; 587 __le16 rx_missed; 588 }; 589 590 enum rtl_flag { 591 RTL_FLAG_TASK_ENABLED = 0, 592 RTL_FLAG_TASK_RESET_PENDING, 593 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 594 RTL_FLAG_TASK_TX_TIMEOUT, 595 RTL_FLAG_MAX 596 }; 597 598 enum rtl_dash_type { 599 RTL_DASH_NONE, 600 RTL_DASH_DP, 601 RTL_DASH_EP, 602 }; 603 604 struct rtl8169_private { 605 void __iomem *mmio_addr; /* memory map physical address */ 606 struct pci_dev *pci_dev; 607 struct net_device *dev; 608 struct phy_device *phydev; 609 struct napi_struct napi; 610 enum mac_version mac_version; 611 enum rtl_dash_type dash_type; 612 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 613 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 614 u32 dirty_tx; 615 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 616 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 617 dma_addr_t TxPhyAddr; 618 dma_addr_t RxPhyAddr; 619 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 620 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 621 u16 cp_cmd; 622 u16 tx_lpi_timer; 623 u32 irq_mask; 624 int irq; 625 struct clk *clk; 626 627 struct { 628 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 629 struct work_struct work; 630 } wk; 631 632 raw_spinlock_t config25_lock; 633 raw_spinlock_t mac_ocp_lock; 634 struct mutex led_lock; /* serialize LED ctrl RMW access */ 635 636 raw_spinlock_t cfg9346_usage_lock; 637 int cfg9346_usage_count; 638 639 unsigned supports_gmii:1; 640 unsigned aspm_manageable:1; 641 unsigned dash_enabled:1; 642 dma_addr_t counters_phys_addr; 643 struct rtl8169_counters *counters; 644 struct rtl8169_tc_offsets tc_offset; 645 u32 saved_wolopts; 646 647 const char *fw_name; 648 struct rtl_fw *rtl_fw; 649 650 struct r8169_led_classdev *leds; 651 652 u32 ocp_base; 653 }; 654 655 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 656 657 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 658 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 659 MODULE_SOFTDEP("pre: realtek"); 660 MODULE_LICENSE("GPL"); 661 MODULE_FIRMWARE(FIRMWARE_8168D_1); 662 MODULE_FIRMWARE(FIRMWARE_8168D_2); 663 MODULE_FIRMWARE(FIRMWARE_8168E_1); 664 MODULE_FIRMWARE(FIRMWARE_8168E_2); 665 MODULE_FIRMWARE(FIRMWARE_8168E_3); 666 MODULE_FIRMWARE(FIRMWARE_8105E_1); 667 MODULE_FIRMWARE(FIRMWARE_8168F_1); 668 MODULE_FIRMWARE(FIRMWARE_8168F_2); 669 MODULE_FIRMWARE(FIRMWARE_8402_1); 670 MODULE_FIRMWARE(FIRMWARE_8411_1); 671 MODULE_FIRMWARE(FIRMWARE_8411_2); 672 MODULE_FIRMWARE(FIRMWARE_8106E_1); 673 MODULE_FIRMWARE(FIRMWARE_8106E_2); 674 MODULE_FIRMWARE(FIRMWARE_8168G_2); 675 MODULE_FIRMWARE(FIRMWARE_8168G_3); 676 MODULE_FIRMWARE(FIRMWARE_8168H_2); 677 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 678 MODULE_FIRMWARE(FIRMWARE_8107E_2); 679 MODULE_FIRMWARE(FIRMWARE_8125A_3); 680 MODULE_FIRMWARE(FIRMWARE_8125B_2); 681 MODULE_FIRMWARE(FIRMWARE_8126A_2); 682 683 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 684 { 685 return &tp->pci_dev->dev; 686 } 687 688 static void rtl_lock_config_regs(struct rtl8169_private *tp) 689 { 690 unsigned long flags; 691 692 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 693 if (!--tp->cfg9346_usage_count) 694 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 695 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 696 } 697 698 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 699 { 700 unsigned long flags; 701 702 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 703 if (!tp->cfg9346_usage_count++) 704 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 705 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 706 } 707 708 static void rtl_pci_commit(struct rtl8169_private *tp) 709 { 710 /* Read an arbitrary register to commit a preceding PCI write */ 711 RTL_R8(tp, ChipCmd); 712 } 713 714 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 715 { 716 unsigned long flags; 717 u8 val; 718 719 raw_spin_lock_irqsave(&tp->config25_lock, flags); 720 val = RTL_R8(tp, Config2); 721 RTL_W8(tp, Config2, (val & ~clear) | set); 722 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 723 } 724 725 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 726 { 727 unsigned long flags; 728 u8 val; 729 730 raw_spin_lock_irqsave(&tp->config25_lock, flags); 731 val = RTL_R8(tp, Config5); 732 RTL_W8(tp, Config5, (val & ~clear) | set); 733 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 734 } 735 736 static bool rtl_is_8125(struct rtl8169_private *tp) 737 { 738 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 739 } 740 741 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 742 { 743 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 744 tp->mac_version != RTL_GIGA_MAC_VER_39 && 745 tp->mac_version <= RTL_GIGA_MAC_VER_53; 746 } 747 748 static bool rtl_supports_eee(struct rtl8169_private *tp) 749 { 750 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 751 tp->mac_version != RTL_GIGA_MAC_VER_37 && 752 tp->mac_version != RTL_GIGA_MAC_VER_39; 753 } 754 755 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 756 { 757 int i; 758 759 for (i = 0; i < ETH_ALEN; i++) 760 mac[i] = RTL_R8(tp, reg + i); 761 } 762 763 struct rtl_cond { 764 bool (*check)(struct rtl8169_private *); 765 const char *msg; 766 }; 767 768 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 769 unsigned long usecs, int n, bool high) 770 { 771 int i; 772 773 for (i = 0; i < n; i++) { 774 if (c->check(tp) == high) 775 return true; 776 fsleep(usecs); 777 } 778 779 if (net_ratelimit()) 780 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 781 c->msg, !high, n, usecs); 782 return false; 783 } 784 785 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 786 const struct rtl_cond *c, 787 unsigned long d, int n) 788 { 789 return rtl_loop_wait(tp, c, d, n, true); 790 } 791 792 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 793 const struct rtl_cond *c, 794 unsigned long d, int n) 795 { 796 return rtl_loop_wait(tp, c, d, n, false); 797 } 798 799 #define DECLARE_RTL_COND(name) \ 800 static bool name ## _check(struct rtl8169_private *); \ 801 \ 802 static const struct rtl_cond name = { \ 803 .check = name ## _check, \ 804 .msg = #name \ 805 }; \ 806 \ 807 static bool name ## _check(struct rtl8169_private *tp) 808 809 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 810 { 811 struct device *dev = tp_to_dev(tp); 812 int ret; 813 814 ret = pm_runtime_resume_and_get(dev); 815 if (ret < 0) 816 return ret; 817 818 mutex_lock(&tp->led_lock); 819 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 820 mutex_unlock(&tp->led_lock); 821 822 pm_runtime_put_sync(dev); 823 824 return 0; 825 } 826 827 int rtl8168_get_led_mode(struct rtl8169_private *tp) 828 { 829 struct device *dev = tp_to_dev(tp); 830 int ret; 831 832 ret = pm_runtime_resume_and_get(dev); 833 if (ret < 0) 834 return ret; 835 836 ret = RTL_R16(tp, LED_CTRL); 837 838 pm_runtime_put_sync(dev); 839 840 return ret; 841 } 842 843 static int rtl8125_get_led_reg(int index) 844 { 845 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 846 847 return led_regs[index]; 848 } 849 850 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 851 { 852 int reg = rtl8125_get_led_reg(index); 853 struct device *dev = tp_to_dev(tp); 854 int ret; 855 u16 val; 856 857 ret = pm_runtime_resume_and_get(dev); 858 if (ret < 0) 859 return ret; 860 861 mutex_lock(&tp->led_lock); 862 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 863 RTL_W16(tp, reg, val | mode); 864 mutex_unlock(&tp->led_lock); 865 866 pm_runtime_put_sync(dev); 867 868 return 0; 869 } 870 871 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 872 { 873 int reg = rtl8125_get_led_reg(index); 874 struct device *dev = tp_to_dev(tp); 875 int ret; 876 877 ret = pm_runtime_resume_and_get(dev); 878 if (ret < 0) 879 return ret; 880 881 ret = RTL_R16(tp, reg); 882 883 pm_runtime_put_sync(dev); 884 885 return ret; 886 } 887 888 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 889 char *buf, int buf_len) 890 { 891 struct pci_dev *pdev = tp->pci_dev; 892 char pdom[8], pfun[8]; 893 int domain; 894 895 domain = pci_domain_nr(pdev->bus); 896 if (domain) 897 snprintf(pdom, sizeof(pdom), "P%d", domain); 898 else 899 pdom[0] = '\0'; 900 901 if (pdev->multifunction) 902 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 903 else 904 pfun[0] = '\0'; 905 906 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 907 PCI_SLOT(pdev->devfn), pfun, idx); 908 } 909 910 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 911 { 912 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 913 if (type == ERIAR_OOB && 914 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 915 tp->mac_version == RTL_GIGA_MAC_VER_53)) 916 *cmd |= 0xf70 << 18; 917 } 918 919 DECLARE_RTL_COND(rtl_eriar_cond) 920 { 921 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 922 } 923 924 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 925 u32 val, int type) 926 { 927 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 928 929 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 930 return; 931 932 RTL_W32(tp, ERIDR, val); 933 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 934 RTL_W32(tp, ERIAR, cmd); 935 936 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 937 } 938 939 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 940 u32 val) 941 { 942 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 943 } 944 945 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 946 { 947 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 948 949 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 950 RTL_W32(tp, ERIAR, cmd); 951 952 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 953 RTL_R32(tp, ERIDR) : ~0; 954 } 955 956 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 957 { 958 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 959 } 960 961 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 962 { 963 u32 val = rtl_eri_read(tp, addr); 964 965 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 966 } 967 968 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 969 { 970 rtl_w0w1_eri(tp, addr, p, 0); 971 } 972 973 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 974 { 975 rtl_w0w1_eri(tp, addr, 0, m); 976 } 977 978 static bool rtl_ocp_reg_failure(u32 reg) 979 { 980 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 981 } 982 983 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 984 { 985 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 986 } 987 988 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 989 { 990 if (rtl_ocp_reg_failure(reg)) 991 return; 992 993 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 994 995 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 996 } 997 998 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 999 { 1000 if (rtl_ocp_reg_failure(reg)) 1001 return 0; 1002 1003 RTL_W32(tp, GPHY_OCP, reg << 15); 1004 1005 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1006 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1007 } 1008 1009 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1010 { 1011 if (rtl_ocp_reg_failure(reg)) 1012 return; 1013 1014 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1015 } 1016 1017 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1018 { 1019 unsigned long flags; 1020 1021 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1022 __r8168_mac_ocp_write(tp, reg, data); 1023 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1024 } 1025 1026 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1027 { 1028 if (rtl_ocp_reg_failure(reg)) 1029 return 0; 1030 1031 RTL_W32(tp, OCPDR, reg << 15); 1032 1033 return RTL_R32(tp, OCPDR); 1034 } 1035 1036 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1037 { 1038 unsigned long flags; 1039 u16 val; 1040 1041 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1042 val = __r8168_mac_ocp_read(tp, reg); 1043 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1044 1045 return val; 1046 } 1047 1048 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1049 u16 set) 1050 { 1051 unsigned long flags; 1052 u16 data; 1053 1054 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1055 data = __r8168_mac_ocp_read(tp, reg); 1056 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1057 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1058 } 1059 1060 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1061 * PHY MCU interrupts before PHY power-down. 1062 */ 1063 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1064 { 1065 switch (tp->mac_version) { 1066 case RTL_GIGA_MAC_VER_40: 1067 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1068 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1069 else 1070 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1071 break; 1072 default: 1073 break; 1074 } 1075 }; 1076 1077 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1078 { 1079 if (reg == 0x1f) { 1080 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1081 return; 1082 } 1083 1084 if (tp->ocp_base != OCP_STD_PHY_BASE) 1085 reg -= 0x10; 1086 1087 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1088 rtl8168g_phy_suspend_quirk(tp, value); 1089 1090 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1091 } 1092 1093 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1094 { 1095 if (reg == 0x1f) 1096 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1097 1098 if (tp->ocp_base != OCP_STD_PHY_BASE) 1099 reg -= 0x10; 1100 1101 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1102 } 1103 1104 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1105 { 1106 if (reg == 0x1f) { 1107 tp->ocp_base = value << 4; 1108 return; 1109 } 1110 1111 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1112 } 1113 1114 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1115 { 1116 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1117 } 1118 1119 DECLARE_RTL_COND(rtl_phyar_cond) 1120 { 1121 return RTL_R32(tp, PHYAR) & 0x80000000; 1122 } 1123 1124 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1125 { 1126 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1127 1128 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1129 /* 1130 * According to hardware specs a 20us delay is required after write 1131 * complete indication, but before sending next command. 1132 */ 1133 udelay(20); 1134 } 1135 1136 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1137 { 1138 int value; 1139 1140 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1141 1142 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1143 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1144 1145 /* 1146 * According to hardware specs a 20us delay is required after read 1147 * complete indication, but before sending next command. 1148 */ 1149 udelay(20); 1150 1151 return value; 1152 } 1153 1154 DECLARE_RTL_COND(rtl_ocpar_cond) 1155 { 1156 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1157 } 1158 1159 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1160 1161 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1162 { 1163 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1164 } 1165 1166 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1167 { 1168 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1169 } 1170 1171 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1172 { 1173 r8168dp_2_mdio_start(tp); 1174 1175 r8169_mdio_write(tp, reg, value); 1176 1177 r8168dp_2_mdio_stop(tp); 1178 } 1179 1180 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1181 { 1182 int value; 1183 1184 /* Work around issue with chip reporting wrong PHY ID */ 1185 if (reg == MII_PHYSID2) 1186 return 0xc912; 1187 1188 r8168dp_2_mdio_start(tp); 1189 1190 value = r8169_mdio_read(tp, reg); 1191 1192 r8168dp_2_mdio_stop(tp); 1193 1194 return value; 1195 } 1196 1197 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1198 { 1199 switch (tp->mac_version) { 1200 case RTL_GIGA_MAC_VER_28: 1201 case RTL_GIGA_MAC_VER_31: 1202 r8168dp_2_mdio_write(tp, location, val); 1203 break; 1204 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 1205 r8168g_mdio_write(tp, location, val); 1206 break; 1207 default: 1208 r8169_mdio_write(tp, location, val); 1209 break; 1210 } 1211 } 1212 1213 static int rtl_readphy(struct rtl8169_private *tp, int location) 1214 { 1215 switch (tp->mac_version) { 1216 case RTL_GIGA_MAC_VER_28: 1217 case RTL_GIGA_MAC_VER_31: 1218 return r8168dp_2_mdio_read(tp, location); 1219 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 1220 return r8168g_mdio_read(tp, location); 1221 default: 1222 return r8169_mdio_read(tp, location); 1223 } 1224 } 1225 1226 DECLARE_RTL_COND(rtl_ephyar_cond) 1227 { 1228 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1229 } 1230 1231 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1232 { 1233 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1234 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1235 1236 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1237 1238 udelay(10); 1239 } 1240 1241 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1242 { 1243 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1244 1245 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1246 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1247 } 1248 1249 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1250 { 1251 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1252 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1253 RTL_R32(tp, OCPDR) : ~0; 1254 } 1255 1256 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1257 { 1258 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1259 } 1260 1261 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1262 u32 data) 1263 { 1264 RTL_W32(tp, OCPDR, data); 1265 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1266 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1267 } 1268 1269 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1270 u32 data) 1271 { 1272 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1273 data, ERIAR_OOB); 1274 } 1275 1276 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1277 { 1278 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1279 1280 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1281 } 1282 1283 #define OOB_CMD_RESET 0x00 1284 #define OOB_CMD_DRIVER_START 0x05 1285 #define OOB_CMD_DRIVER_STOP 0x06 1286 1287 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1288 { 1289 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1290 } 1291 1292 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1293 { 1294 u16 reg; 1295 1296 reg = rtl8168_get_ocp_reg(tp); 1297 1298 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1299 } 1300 1301 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1302 { 1303 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1304 } 1305 1306 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1307 { 1308 return RTL_R8(tp, IBISR0) & 0x20; 1309 } 1310 1311 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1312 { 1313 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1314 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1315 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1316 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1317 } 1318 1319 static void rtl_dash_loop_wait(struct rtl8169_private *tp, 1320 const struct rtl_cond *c, 1321 unsigned long usecs, int n, bool high) 1322 { 1323 if (!tp->dash_enabled) 1324 return; 1325 rtl_loop_wait(tp, c, usecs, n, high); 1326 } 1327 1328 static void rtl_dash_loop_wait_high(struct rtl8169_private *tp, 1329 const struct rtl_cond *c, 1330 unsigned long d, int n) 1331 { 1332 rtl_dash_loop_wait(tp, c, d, n, true); 1333 } 1334 1335 static void rtl_dash_loop_wait_low(struct rtl8169_private *tp, 1336 const struct rtl_cond *c, 1337 unsigned long d, int n) 1338 { 1339 rtl_dash_loop_wait(tp, c, d, n, false); 1340 } 1341 1342 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1343 { 1344 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1345 rtl_dash_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1346 } 1347 1348 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1349 { 1350 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1351 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1352 rtl_dash_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1353 } 1354 1355 static void rtl8168_driver_start(struct rtl8169_private *tp) 1356 { 1357 if (tp->dash_type == RTL_DASH_DP) 1358 rtl8168dp_driver_start(tp); 1359 else 1360 rtl8168ep_driver_start(tp); 1361 } 1362 1363 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1364 { 1365 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1366 rtl_dash_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1367 } 1368 1369 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1370 { 1371 rtl8168ep_stop_cmac(tp); 1372 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1373 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1374 rtl_dash_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1375 } 1376 1377 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1378 { 1379 if (tp->dash_type == RTL_DASH_DP) 1380 rtl8168dp_driver_stop(tp); 1381 else 1382 rtl8168ep_driver_stop(tp); 1383 } 1384 1385 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1386 { 1387 u16 reg = rtl8168_get_ocp_reg(tp); 1388 1389 return r8168dp_ocp_read(tp, reg) & BIT(15); 1390 } 1391 1392 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1393 { 1394 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1395 } 1396 1397 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1398 { 1399 switch (tp->dash_type) { 1400 case RTL_DASH_DP: 1401 return r8168dp_check_dash(tp); 1402 case RTL_DASH_EP: 1403 return r8168ep_check_dash(tp); 1404 default: 1405 return false; 1406 } 1407 } 1408 1409 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1410 { 1411 switch (tp->mac_version) { 1412 case RTL_GIGA_MAC_VER_28: 1413 case RTL_GIGA_MAC_VER_31: 1414 return RTL_DASH_DP; 1415 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1416 return RTL_DASH_EP; 1417 default: 1418 return RTL_DASH_NONE; 1419 } 1420 } 1421 1422 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1423 { 1424 switch (tp->mac_version) { 1425 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1426 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1427 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1428 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65: 1429 if (enable) 1430 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1431 else 1432 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1433 break; 1434 default: 1435 break; 1436 } 1437 } 1438 1439 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1440 { 1441 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1442 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1443 } 1444 1445 DECLARE_RTL_COND(rtl_efusear_cond) 1446 { 1447 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1448 } 1449 1450 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1451 { 1452 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1453 1454 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1455 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1456 } 1457 1458 static u32 rtl_get_events(struct rtl8169_private *tp) 1459 { 1460 if (rtl_is_8125(tp)) 1461 return RTL_R32(tp, IntrStatus_8125); 1462 else 1463 return RTL_R16(tp, IntrStatus); 1464 } 1465 1466 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1467 { 1468 if (rtl_is_8125(tp)) 1469 RTL_W32(tp, IntrStatus_8125, bits); 1470 else 1471 RTL_W16(tp, IntrStatus, bits); 1472 } 1473 1474 static void rtl_irq_disable(struct rtl8169_private *tp) 1475 { 1476 if (rtl_is_8125(tp)) 1477 RTL_W32(tp, IntrMask_8125, 0); 1478 else 1479 RTL_W16(tp, IntrMask, 0); 1480 } 1481 1482 static void rtl_irq_enable(struct rtl8169_private *tp) 1483 { 1484 if (rtl_is_8125(tp)) 1485 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1486 else 1487 RTL_W16(tp, IntrMask, tp->irq_mask); 1488 } 1489 1490 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1491 { 1492 rtl_irq_disable(tp); 1493 rtl_ack_events(tp, 0xffffffff); 1494 rtl_pci_commit(tp); 1495 } 1496 1497 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1498 { 1499 struct phy_device *phydev = tp->phydev; 1500 1501 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1502 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1503 if (phydev->speed == SPEED_1000) { 1504 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1505 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1506 } else if (phydev->speed == SPEED_100) { 1507 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1508 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1509 } else { 1510 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1511 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1512 } 1513 rtl_reset_packet_filter(tp); 1514 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1515 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1516 if (phydev->speed == SPEED_1000) { 1517 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1518 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1519 } else { 1520 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1521 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1522 } 1523 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1524 if (phydev->speed == SPEED_10) { 1525 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1526 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1527 } else { 1528 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1529 } 1530 } 1531 } 1532 1533 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1534 1535 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1536 { 1537 struct rtl8169_private *tp = netdev_priv(dev); 1538 1539 wol->supported = WAKE_ANY; 1540 wol->wolopts = tp->saved_wolopts; 1541 } 1542 1543 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1544 { 1545 static const struct { 1546 u32 opt; 1547 u16 reg; 1548 u8 mask; 1549 } cfg[] = { 1550 { WAKE_PHY, Config3, LinkUp }, 1551 { WAKE_UCAST, Config5, UWF }, 1552 { WAKE_BCAST, Config5, BWF }, 1553 { WAKE_MCAST, Config5, MWF }, 1554 { WAKE_ANY, Config5, LanWake }, 1555 { WAKE_MAGIC, Config3, MagicPacket } 1556 }; 1557 unsigned int i, tmp = ARRAY_SIZE(cfg); 1558 unsigned long flags; 1559 u8 options; 1560 1561 rtl_unlock_config_regs(tp); 1562 1563 if (rtl_is_8168evl_up(tp)) { 1564 tmp--; 1565 if (wolopts & WAKE_MAGIC) 1566 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1567 else 1568 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1569 } else if (rtl_is_8125(tp)) { 1570 tmp--; 1571 if (wolopts & WAKE_MAGIC) 1572 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1573 else 1574 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1575 } 1576 1577 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1578 for (i = 0; i < tmp; i++) { 1579 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1580 if (wolopts & cfg[i].opt) 1581 options |= cfg[i].mask; 1582 RTL_W8(tp, cfg[i].reg, options); 1583 } 1584 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1585 1586 switch (tp->mac_version) { 1587 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1588 options = RTL_R8(tp, Config1) & ~PMEnable; 1589 if (wolopts) 1590 options |= PMEnable; 1591 RTL_W8(tp, Config1, options); 1592 break; 1593 case RTL_GIGA_MAC_VER_34: 1594 case RTL_GIGA_MAC_VER_37: 1595 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65: 1596 if (wolopts) 1597 rtl_mod_config2(tp, 0, PME_SIGNAL); 1598 else 1599 rtl_mod_config2(tp, PME_SIGNAL, 0); 1600 break; 1601 default: 1602 break; 1603 } 1604 1605 rtl_lock_config_regs(tp); 1606 1607 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1608 1609 if (!tp->dash_enabled) { 1610 rtl_set_d3_pll_down(tp, !wolopts); 1611 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1612 } 1613 } 1614 1615 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1616 { 1617 struct rtl8169_private *tp = netdev_priv(dev); 1618 1619 if (wol->wolopts & ~WAKE_ANY) 1620 return -EINVAL; 1621 1622 tp->saved_wolopts = wol->wolopts; 1623 __rtl8169_set_wol(tp, tp->saved_wolopts); 1624 1625 return 0; 1626 } 1627 1628 static void rtl8169_get_drvinfo(struct net_device *dev, 1629 struct ethtool_drvinfo *info) 1630 { 1631 struct rtl8169_private *tp = netdev_priv(dev); 1632 struct rtl_fw *rtl_fw = tp->rtl_fw; 1633 1634 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1635 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1636 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1637 if (rtl_fw) 1638 strscpy(info->fw_version, rtl_fw->version, 1639 sizeof(info->fw_version)); 1640 } 1641 1642 static int rtl8169_get_regs_len(struct net_device *dev) 1643 { 1644 return R8169_REGS_SIZE; 1645 } 1646 1647 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1648 netdev_features_t features) 1649 { 1650 struct rtl8169_private *tp = netdev_priv(dev); 1651 1652 if (dev->mtu > TD_MSS_MAX) 1653 features &= ~NETIF_F_ALL_TSO; 1654 1655 if (dev->mtu > ETH_DATA_LEN && 1656 tp->mac_version > RTL_GIGA_MAC_VER_06) 1657 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1658 1659 return features; 1660 } 1661 1662 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1663 netdev_features_t features) 1664 { 1665 u32 rx_config = RTL_R32(tp, RxConfig); 1666 1667 if (features & NETIF_F_RXALL) 1668 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1669 else 1670 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1671 1672 if (rtl_is_8125(tp)) { 1673 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1674 rx_config |= RX_VLAN_8125; 1675 else 1676 rx_config &= ~RX_VLAN_8125; 1677 } 1678 1679 RTL_W32(tp, RxConfig, rx_config); 1680 } 1681 1682 static int rtl8169_set_features(struct net_device *dev, 1683 netdev_features_t features) 1684 { 1685 struct rtl8169_private *tp = netdev_priv(dev); 1686 1687 rtl_set_rx_config_features(tp, features); 1688 1689 if (features & NETIF_F_RXCSUM) 1690 tp->cp_cmd |= RxChkSum; 1691 else 1692 tp->cp_cmd &= ~RxChkSum; 1693 1694 if (!rtl_is_8125(tp)) { 1695 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1696 tp->cp_cmd |= RxVlan; 1697 else 1698 tp->cp_cmd &= ~RxVlan; 1699 } 1700 1701 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1702 rtl_pci_commit(tp); 1703 1704 return 0; 1705 } 1706 1707 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1708 { 1709 return (skb_vlan_tag_present(skb)) ? 1710 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1711 } 1712 1713 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1714 { 1715 u32 opts2 = le32_to_cpu(desc->opts2); 1716 1717 if (opts2 & RxVlanTag) 1718 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1719 } 1720 1721 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1722 void *p) 1723 { 1724 struct rtl8169_private *tp = netdev_priv(dev); 1725 u32 __iomem *data = tp->mmio_addr; 1726 u32 *dw = p; 1727 int i; 1728 1729 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1730 memcpy_fromio(dw++, data++, 4); 1731 } 1732 1733 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1734 "tx_packets", 1735 "rx_packets", 1736 "tx_errors", 1737 "rx_errors", 1738 "rx_missed", 1739 "align_errors", 1740 "tx_single_collisions", 1741 "tx_multi_collisions", 1742 "unicast", 1743 "broadcast", 1744 "multicast", 1745 "tx_aborted", 1746 "tx_underrun", 1747 }; 1748 1749 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1750 { 1751 switch (sset) { 1752 case ETH_SS_STATS: 1753 return ARRAY_SIZE(rtl8169_gstrings); 1754 default: 1755 return -EOPNOTSUPP; 1756 } 1757 } 1758 1759 DECLARE_RTL_COND(rtl_counters_cond) 1760 { 1761 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1762 } 1763 1764 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1765 { 1766 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1767 1768 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1769 rtl_pci_commit(tp); 1770 RTL_W32(tp, CounterAddrLow, cmd); 1771 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1772 1773 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1774 } 1775 1776 static void rtl8169_update_counters(struct rtl8169_private *tp) 1777 { 1778 u8 val = RTL_R8(tp, ChipCmd); 1779 1780 /* 1781 * Some chips are unable to dump tally counters when the receiver 1782 * is disabled. If 0xff chip may be in a PCI power-save state. 1783 */ 1784 if (val & CmdRxEnb && val != 0xff) 1785 rtl8169_do_counters(tp, CounterDump); 1786 } 1787 1788 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1789 { 1790 struct rtl8169_counters *counters = tp->counters; 1791 1792 /* 1793 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1794 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1795 * reset by a power cycle, while the counter values collected by the 1796 * driver are reset at every driver unload/load cycle. 1797 * 1798 * To make sure the HW values returned by @get_stats64 match the SW 1799 * values, we collect the initial values at first open(*) and use them 1800 * as offsets to normalize the values returned by @get_stats64. 1801 * 1802 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1803 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1804 * set at open time by rtl_hw_start. 1805 */ 1806 1807 if (tp->tc_offset.inited) 1808 return; 1809 1810 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1811 rtl8169_do_counters(tp, CounterReset); 1812 } else { 1813 rtl8169_update_counters(tp); 1814 tp->tc_offset.tx_errors = counters->tx_errors; 1815 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1816 tp->tc_offset.tx_aborted = counters->tx_aborted; 1817 tp->tc_offset.rx_missed = counters->rx_missed; 1818 } 1819 1820 tp->tc_offset.inited = true; 1821 } 1822 1823 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1824 struct ethtool_stats *stats, u64 *data) 1825 { 1826 struct rtl8169_private *tp = netdev_priv(dev); 1827 struct rtl8169_counters *counters; 1828 1829 counters = tp->counters; 1830 rtl8169_update_counters(tp); 1831 1832 data[0] = le64_to_cpu(counters->tx_packets); 1833 data[1] = le64_to_cpu(counters->rx_packets); 1834 data[2] = le64_to_cpu(counters->tx_errors); 1835 data[3] = le32_to_cpu(counters->rx_errors); 1836 data[4] = le16_to_cpu(counters->rx_missed); 1837 data[5] = le16_to_cpu(counters->align_errors); 1838 data[6] = le32_to_cpu(counters->tx_one_collision); 1839 data[7] = le32_to_cpu(counters->tx_multi_collision); 1840 data[8] = le64_to_cpu(counters->rx_unicast); 1841 data[9] = le64_to_cpu(counters->rx_broadcast); 1842 data[10] = le32_to_cpu(counters->rx_multicast); 1843 data[11] = le16_to_cpu(counters->tx_aborted); 1844 data[12] = le16_to_cpu(counters->tx_underun); 1845 } 1846 1847 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1848 { 1849 switch(stringset) { 1850 case ETH_SS_STATS: 1851 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1852 break; 1853 } 1854 } 1855 1856 /* 1857 * Interrupt coalescing 1858 * 1859 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1860 * > 8169, 8168 and 810x line of chipsets 1861 * 1862 * 8169, 8168, and 8136(810x) serial chipsets support it. 1863 * 1864 * > 2 - the Tx timer unit at gigabit speed 1865 * 1866 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1867 * (0xe0) bit 1 and bit 0. 1868 * 1869 * For 8169 1870 * bit[1:0] \ speed 1000M 100M 10M 1871 * 0 0 320ns 2.56us 40.96us 1872 * 0 1 2.56us 20.48us 327.7us 1873 * 1 0 5.12us 40.96us 655.4us 1874 * 1 1 10.24us 81.92us 1.31ms 1875 * 1876 * For the other 1877 * bit[1:0] \ speed 1000M 100M 10M 1878 * 0 0 5us 2.56us 40.96us 1879 * 0 1 40us 20.48us 327.7us 1880 * 1 0 80us 40.96us 655.4us 1881 * 1 1 160us 81.92us 1.31ms 1882 */ 1883 1884 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1885 struct rtl_coalesce_info { 1886 u32 speed; 1887 u32 scale_nsecs[4]; 1888 }; 1889 1890 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1891 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1892 1893 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1894 { SPEED_1000, COALESCE_DELAY(320) }, 1895 { SPEED_100, COALESCE_DELAY(2560) }, 1896 { SPEED_10, COALESCE_DELAY(40960) }, 1897 { 0 }, 1898 }; 1899 1900 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1901 { SPEED_1000, COALESCE_DELAY(5000) }, 1902 { SPEED_100, COALESCE_DELAY(2560) }, 1903 { SPEED_10, COALESCE_DELAY(40960) }, 1904 { 0 }, 1905 }; 1906 #undef COALESCE_DELAY 1907 1908 /* get rx/tx scale vector corresponding to current speed */ 1909 static const struct rtl_coalesce_info * 1910 rtl_coalesce_info(struct rtl8169_private *tp) 1911 { 1912 const struct rtl_coalesce_info *ci; 1913 1914 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1915 ci = rtl_coalesce_info_8169; 1916 else 1917 ci = rtl_coalesce_info_8168_8136; 1918 1919 /* if speed is unknown assume highest one */ 1920 if (tp->phydev->speed == SPEED_UNKNOWN) 1921 return ci; 1922 1923 for (; ci->speed; ci++) { 1924 if (tp->phydev->speed == ci->speed) 1925 return ci; 1926 } 1927 1928 return ERR_PTR(-ELNRNG); 1929 } 1930 1931 static int rtl_get_coalesce(struct net_device *dev, 1932 struct ethtool_coalesce *ec, 1933 struct kernel_ethtool_coalesce *kernel_coal, 1934 struct netlink_ext_ack *extack) 1935 { 1936 struct rtl8169_private *tp = netdev_priv(dev); 1937 const struct rtl_coalesce_info *ci; 1938 u32 scale, c_us, c_fr; 1939 u16 intrmit; 1940 1941 if (rtl_is_8125(tp)) 1942 return -EOPNOTSUPP; 1943 1944 memset(ec, 0, sizeof(*ec)); 1945 1946 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1947 ci = rtl_coalesce_info(tp); 1948 if (IS_ERR(ci)) 1949 return PTR_ERR(ci); 1950 1951 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1952 1953 intrmit = RTL_R16(tp, IntrMitigate); 1954 1955 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1956 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1957 1958 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1959 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1960 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1961 1962 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1963 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1964 1965 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1966 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1967 1968 return 0; 1969 } 1970 1971 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1972 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1973 u16 *cp01) 1974 { 1975 const struct rtl_coalesce_info *ci; 1976 u16 i; 1977 1978 ci = rtl_coalesce_info(tp); 1979 if (IS_ERR(ci)) 1980 return PTR_ERR(ci); 1981 1982 for (i = 0; i < 4; i++) { 1983 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1984 *cp01 = i; 1985 return ci->scale_nsecs[i]; 1986 } 1987 } 1988 1989 return -ERANGE; 1990 } 1991 1992 static int rtl_set_coalesce(struct net_device *dev, 1993 struct ethtool_coalesce *ec, 1994 struct kernel_ethtool_coalesce *kernel_coal, 1995 struct netlink_ext_ack *extack) 1996 { 1997 struct rtl8169_private *tp = netdev_priv(dev); 1998 u32 tx_fr = ec->tx_max_coalesced_frames; 1999 u32 rx_fr = ec->rx_max_coalesced_frames; 2000 u32 coal_usec_max, units; 2001 u16 w = 0, cp01 = 0; 2002 int scale; 2003 2004 if (rtl_is_8125(tp)) 2005 return -EOPNOTSUPP; 2006 2007 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 2008 return -ERANGE; 2009 2010 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 2011 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 2012 if (scale < 0) 2013 return scale; 2014 2015 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 2016 * not only when usecs=0 because of e.g. the following scenario: 2017 * 2018 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2019 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2020 * - then user does `ethtool -C eth0 rx-usecs 100` 2021 * 2022 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2023 * if we want to ignore rx_frames then it has to be set to 0. 2024 */ 2025 if (rx_fr == 1) 2026 rx_fr = 0; 2027 if (tx_fr == 1) 2028 tx_fr = 0; 2029 2030 /* HW requires time limit to be set if frame limit is set */ 2031 if ((tx_fr && !ec->tx_coalesce_usecs) || 2032 (rx_fr && !ec->rx_coalesce_usecs)) 2033 return -EINVAL; 2034 2035 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2036 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2037 2038 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2039 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2040 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2041 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2042 2043 RTL_W16(tp, IntrMitigate, w); 2044 2045 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2046 if (rtl_is_8168evl_up(tp)) { 2047 if (!rx_fr && !tx_fr) 2048 /* disable packet counter */ 2049 tp->cp_cmd |= PktCntrDisable; 2050 else 2051 tp->cp_cmd &= ~PktCntrDisable; 2052 } 2053 2054 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2055 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2056 rtl_pci_commit(tp); 2057 2058 return 0; 2059 } 2060 2061 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2062 { 2063 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2064 2065 switch (tp->mac_version) { 2066 case RTL_GIGA_MAC_VER_46: 2067 case RTL_GIGA_MAC_VER_48: 2068 tp->tx_lpi_timer = timer_val; 2069 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2070 break; 2071 case RTL_GIGA_MAC_VER_61: 2072 case RTL_GIGA_MAC_VER_63: 2073 case RTL_GIGA_MAC_VER_65: 2074 tp->tx_lpi_timer = timer_val; 2075 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2076 break; 2077 default: 2078 break; 2079 } 2080 } 2081 2082 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2083 { 2084 unsigned int speed = tp->phydev->speed; 2085 unsigned int timer = tp->tx_lpi_timer; 2086 2087 if (!timer || speed == SPEED_UNKNOWN) 2088 return 0; 2089 2090 /* tx_lpi_timer value is in bytes */ 2091 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2092 } 2093 2094 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2095 { 2096 struct rtl8169_private *tp = netdev_priv(dev); 2097 int ret; 2098 2099 if (!rtl_supports_eee(tp)) 2100 return -EOPNOTSUPP; 2101 2102 ret = phy_ethtool_get_eee(tp->phydev, data); 2103 if (ret) 2104 return ret; 2105 2106 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2107 2108 return 0; 2109 } 2110 2111 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2112 { 2113 struct rtl8169_private *tp = netdev_priv(dev); 2114 2115 if (!rtl_supports_eee(tp)) 2116 return -EOPNOTSUPP; 2117 2118 return phy_ethtool_set_eee(tp->phydev, data); 2119 } 2120 2121 static void rtl8169_get_ringparam(struct net_device *dev, 2122 struct ethtool_ringparam *data, 2123 struct kernel_ethtool_ringparam *kernel_data, 2124 struct netlink_ext_ack *extack) 2125 { 2126 data->rx_max_pending = NUM_RX_DESC; 2127 data->rx_pending = NUM_RX_DESC; 2128 data->tx_max_pending = NUM_TX_DESC; 2129 data->tx_pending = NUM_TX_DESC; 2130 } 2131 2132 static void rtl8169_get_pauseparam(struct net_device *dev, 2133 struct ethtool_pauseparam *data) 2134 { 2135 struct rtl8169_private *tp = netdev_priv(dev); 2136 bool tx_pause, rx_pause; 2137 2138 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2139 2140 data->autoneg = tp->phydev->autoneg; 2141 data->tx_pause = tx_pause ? 1 : 0; 2142 data->rx_pause = rx_pause ? 1 : 0; 2143 } 2144 2145 static int rtl8169_set_pauseparam(struct net_device *dev, 2146 struct ethtool_pauseparam *data) 2147 { 2148 struct rtl8169_private *tp = netdev_priv(dev); 2149 2150 if (dev->mtu > ETH_DATA_LEN) 2151 return -EOPNOTSUPP; 2152 2153 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2154 2155 return 0; 2156 } 2157 2158 static const struct ethtool_ops rtl8169_ethtool_ops = { 2159 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2160 ETHTOOL_COALESCE_MAX_FRAMES, 2161 .get_drvinfo = rtl8169_get_drvinfo, 2162 .get_regs_len = rtl8169_get_regs_len, 2163 .get_link = ethtool_op_get_link, 2164 .get_coalesce = rtl_get_coalesce, 2165 .set_coalesce = rtl_set_coalesce, 2166 .get_regs = rtl8169_get_regs, 2167 .get_wol = rtl8169_get_wol, 2168 .set_wol = rtl8169_set_wol, 2169 .get_strings = rtl8169_get_strings, 2170 .get_sset_count = rtl8169_get_sset_count, 2171 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2172 .get_ts_info = ethtool_op_get_ts_info, 2173 .nway_reset = phy_ethtool_nway_reset, 2174 .get_eee = rtl8169_get_eee, 2175 .set_eee = rtl8169_set_eee, 2176 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2177 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2178 .get_ringparam = rtl8169_get_ringparam, 2179 .get_pauseparam = rtl8169_get_pauseparam, 2180 .set_pauseparam = rtl8169_set_pauseparam, 2181 }; 2182 2183 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2184 { 2185 /* 2186 * The driver currently handles the 8168Bf and the 8168Be identically 2187 * but they can be identified more specifically through the test below 2188 * if needed: 2189 * 2190 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2191 * 2192 * Same thing for the 8101Eb and the 8101Ec: 2193 * 2194 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2195 */ 2196 static const struct rtl_mac_info { 2197 u16 mask; 2198 u16 val; 2199 enum mac_version ver; 2200 } mac_info[] = { 2201 /* 8126A family. */ 2202 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2203 2204 /* 8125B family. */ 2205 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2206 2207 /* 8125A family. */ 2208 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2209 /* It seems only XID 609 made it to the mass market. 2210 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2211 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2212 */ 2213 2214 /* RTL8117 */ 2215 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2216 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2217 2218 /* 8168EP family. */ 2219 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2220 /* It seems this chip version never made it to 2221 * the wild. Let's disable detection. 2222 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2223 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2224 */ 2225 2226 /* 8168H family. */ 2227 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2228 /* It seems this chip version never made it to 2229 * the wild. Let's disable detection. 2230 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2231 */ 2232 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 2233 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, 2234 2235 /* 8168G family. */ 2236 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2237 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2238 /* It seems this chip version never made it to 2239 * the wild. Let's disable detection. 2240 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2241 */ 2242 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2243 2244 /* 8168F family. */ 2245 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2246 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2247 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2248 2249 /* 8168E family. */ 2250 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2251 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2252 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2253 2254 /* 8168D family. */ 2255 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2256 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2257 2258 /* 8168DP family. */ 2259 /* It seems this early RTL8168dp version never made it to 2260 * the wild. Support has been removed. 2261 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2262 */ 2263 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2264 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2265 2266 /* 8168C family. */ 2267 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2268 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2269 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2270 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2271 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2272 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2273 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2274 2275 /* 8168B family. */ 2276 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2277 /* This one is very old and rare, let's see if anybody complains. 2278 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2279 */ 2280 2281 /* 8101 family. */ 2282 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2283 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2284 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2285 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2286 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2287 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2288 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2289 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2290 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2291 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2292 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2293 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2294 2295 /* 8110 family. */ 2296 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2297 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2298 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2299 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2300 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2301 2302 /* Catch-all */ 2303 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2304 }; 2305 const struct rtl_mac_info *p = mac_info; 2306 enum mac_version ver; 2307 2308 while ((xid & p->mask) != p->val) 2309 p++; 2310 ver = p->ver; 2311 2312 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2313 if (ver == RTL_GIGA_MAC_VER_42) 2314 ver = RTL_GIGA_MAC_VER_43; 2315 else if (ver == RTL_GIGA_MAC_VER_46) 2316 ver = RTL_GIGA_MAC_VER_48; 2317 } 2318 2319 return ver; 2320 } 2321 2322 static void rtl_release_firmware(struct rtl8169_private *tp) 2323 { 2324 if (tp->rtl_fw) { 2325 rtl_fw_release_firmware(tp->rtl_fw); 2326 kfree(tp->rtl_fw); 2327 tp->rtl_fw = NULL; 2328 } 2329 } 2330 2331 void r8169_apply_firmware(struct rtl8169_private *tp) 2332 { 2333 int val; 2334 2335 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2336 if (tp->rtl_fw) { 2337 rtl_fw_write_firmware(tp, tp->rtl_fw); 2338 /* At least one firmware doesn't reset tp->ocp_base. */ 2339 tp->ocp_base = OCP_STD_PHY_BASE; 2340 2341 /* PHY soft reset may still be in progress */ 2342 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2343 !(val & BMCR_RESET), 2344 50000, 600000, true); 2345 } 2346 } 2347 2348 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2349 { 2350 /* Adjust EEE LED frequency */ 2351 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2352 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2353 2354 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2355 } 2356 2357 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2358 { 2359 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2360 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2361 } 2362 2363 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2364 { 2365 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2366 } 2367 2368 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2369 { 2370 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2371 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2372 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2373 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2374 } 2375 2376 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2377 { 2378 u16 data1, data2, ioffset; 2379 2380 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2381 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2382 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2383 2384 ioffset = (data2 >> 1) & 0x7ff8; 2385 ioffset |= data2 & 0x0007; 2386 if (data1 & BIT(7)) 2387 ioffset |= BIT(15); 2388 2389 return ioffset; 2390 } 2391 2392 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2393 { 2394 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 2395 return; 2396 2397 set_bit(flag, tp->wk.flags); 2398 schedule_work(&tp->wk.work); 2399 } 2400 2401 static void rtl8169_init_phy(struct rtl8169_private *tp) 2402 { 2403 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2404 2405 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2406 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2407 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2408 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2409 RTL_W8(tp, 0x82, 0x01); 2410 } 2411 2412 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2413 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2414 tp->pci_dev->subsystem_device == 0xe000) 2415 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2416 2417 /* We may have called phy_speed_down before */ 2418 phy_speed_up(tp->phydev); 2419 2420 genphy_soft_reset(tp->phydev); 2421 } 2422 2423 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2424 { 2425 rtl_unlock_config_regs(tp); 2426 2427 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2428 rtl_pci_commit(tp); 2429 2430 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2431 rtl_pci_commit(tp); 2432 2433 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2434 rtl_rar_exgmac_set(tp, addr); 2435 2436 rtl_lock_config_regs(tp); 2437 } 2438 2439 static int rtl_set_mac_address(struct net_device *dev, void *p) 2440 { 2441 struct rtl8169_private *tp = netdev_priv(dev); 2442 int ret; 2443 2444 ret = eth_mac_addr(dev, p); 2445 if (ret) 2446 return ret; 2447 2448 rtl_rar_set(tp, dev->dev_addr); 2449 2450 return 0; 2451 } 2452 2453 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2454 { 2455 switch (tp->mac_version) { 2456 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2457 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2458 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2459 break; 2460 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2461 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2462 case RTL_GIGA_MAC_VER_38: 2463 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2464 break; 2465 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2466 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2467 break; 2468 case RTL_GIGA_MAC_VER_61: 2469 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2470 break; 2471 case RTL_GIGA_MAC_VER_63: 2472 case RTL_GIGA_MAC_VER_65: 2473 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2474 RX_PAUSE_SLOT_ON); 2475 break; 2476 default: 2477 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2478 break; 2479 } 2480 } 2481 2482 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2483 { 2484 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2485 } 2486 2487 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2488 { 2489 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2490 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2491 } 2492 2493 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2494 { 2495 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2496 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2497 } 2498 2499 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2500 { 2501 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2502 } 2503 2504 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2505 { 2506 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2507 } 2508 2509 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2510 { 2511 RTL_W8(tp, MaxTxPacketSize, 0x24); 2512 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2513 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2514 } 2515 2516 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2517 { 2518 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2519 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2520 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2521 } 2522 2523 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2524 { 2525 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2526 } 2527 2528 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2529 { 2530 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2531 } 2532 2533 static void rtl_jumbo_config(struct rtl8169_private *tp) 2534 { 2535 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2536 int readrq = 4096; 2537 2538 rtl_unlock_config_regs(tp); 2539 switch (tp->mac_version) { 2540 case RTL_GIGA_MAC_VER_17: 2541 if (jumbo) { 2542 readrq = 512; 2543 r8168b_1_hw_jumbo_enable(tp); 2544 } else { 2545 r8168b_1_hw_jumbo_disable(tp); 2546 } 2547 break; 2548 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2549 if (jumbo) { 2550 readrq = 512; 2551 r8168c_hw_jumbo_enable(tp); 2552 } else { 2553 r8168c_hw_jumbo_disable(tp); 2554 } 2555 break; 2556 case RTL_GIGA_MAC_VER_28: 2557 if (jumbo) 2558 r8168dp_hw_jumbo_enable(tp); 2559 else 2560 r8168dp_hw_jumbo_disable(tp); 2561 break; 2562 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2563 if (jumbo) 2564 r8168e_hw_jumbo_enable(tp); 2565 else 2566 r8168e_hw_jumbo_disable(tp); 2567 break; 2568 default: 2569 break; 2570 } 2571 rtl_lock_config_regs(tp); 2572 2573 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2574 pcie_set_readrq(tp->pci_dev, readrq); 2575 2576 /* Chip doesn't support pause in jumbo mode */ 2577 if (jumbo) { 2578 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2579 tp->phydev->advertising); 2580 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2581 tp->phydev->advertising); 2582 phy_start_aneg(tp->phydev); 2583 } 2584 } 2585 2586 DECLARE_RTL_COND(rtl_chipcmd_cond) 2587 { 2588 return RTL_R8(tp, ChipCmd) & CmdReset; 2589 } 2590 2591 static void rtl_hw_reset(struct rtl8169_private *tp) 2592 { 2593 RTL_W8(tp, ChipCmd, CmdReset); 2594 2595 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2596 } 2597 2598 static void rtl_request_firmware(struct rtl8169_private *tp) 2599 { 2600 struct rtl_fw *rtl_fw; 2601 2602 /* firmware loaded already or no firmware available */ 2603 if (tp->rtl_fw || !tp->fw_name) 2604 return; 2605 2606 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2607 if (!rtl_fw) 2608 return; 2609 2610 rtl_fw->phy_write = rtl_writephy; 2611 rtl_fw->phy_read = rtl_readphy; 2612 rtl_fw->mac_mcu_write = mac_mcu_write; 2613 rtl_fw->mac_mcu_read = mac_mcu_read; 2614 rtl_fw->fw_name = tp->fw_name; 2615 rtl_fw->dev = tp_to_dev(tp); 2616 2617 if (rtl_fw_request_firmware(rtl_fw)) 2618 kfree(rtl_fw); 2619 else 2620 tp->rtl_fw = rtl_fw; 2621 } 2622 2623 static void rtl_rx_close(struct rtl8169_private *tp) 2624 { 2625 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2626 } 2627 2628 DECLARE_RTL_COND(rtl_npq_cond) 2629 { 2630 return RTL_R8(tp, TxPoll) & NPQ; 2631 } 2632 2633 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2634 { 2635 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2636 } 2637 2638 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2639 { 2640 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2641 } 2642 2643 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2644 { 2645 /* IntrMitigate has new functionality on RTL8125 */ 2646 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2647 } 2648 2649 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2650 { 2651 switch (tp->mac_version) { 2652 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2653 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2654 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2655 break; 2656 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2657 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2658 break; 2659 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65: 2660 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2661 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2662 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2663 break; 2664 default: 2665 break; 2666 } 2667 } 2668 2669 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2670 { 2671 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2672 } 2673 2674 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2675 { 2676 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2677 fsleep(2000); 2678 rtl_wait_txrx_fifo_empty(tp); 2679 } 2680 2681 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2682 { 2683 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2684 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2685 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2686 2687 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2688 rtl_disable_rxdvgate(tp); 2689 } 2690 2691 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2692 { 2693 if (tp->dash_enabled) 2694 return; 2695 2696 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2697 tp->mac_version == RTL_GIGA_MAC_VER_33) 2698 rtl_ephy_write(tp, 0x19, 0xff64); 2699 2700 if (device_may_wakeup(tp_to_dev(tp))) { 2701 phy_speed_down(tp->phydev, false); 2702 rtl_wol_enable_rx(tp); 2703 } 2704 } 2705 2706 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2707 { 2708 u32 val = TX_DMA_BURST << TxDMAShift | 2709 InterFrameGap << TxInterFrameGapShift; 2710 2711 if (rtl_is_8168evl_up(tp)) 2712 val |= TXCFG_AUTO_FIFO; 2713 2714 RTL_W32(tp, TxConfig, val); 2715 } 2716 2717 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2718 { 2719 /* Low hurts. Let's disable the filtering. */ 2720 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2721 } 2722 2723 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2724 { 2725 /* 2726 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2727 * register to be written before TxDescAddrLow to work. 2728 * Switching from MMIO to I/O access fixes the issue as well. 2729 */ 2730 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2731 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2732 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2733 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2734 } 2735 2736 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2737 { 2738 u32 val; 2739 2740 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2741 val = 0x000fff00; 2742 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2743 val = 0x00ffff00; 2744 else 2745 return; 2746 2747 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2748 val |= 0xff; 2749 2750 RTL_W32(tp, 0x7c, val); 2751 } 2752 2753 static void rtl_set_rx_mode(struct net_device *dev) 2754 { 2755 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2756 /* Multicast hash filter */ 2757 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2758 struct rtl8169_private *tp = netdev_priv(dev); 2759 u32 tmp; 2760 2761 if (dev->flags & IFF_PROMISC) { 2762 rx_mode |= AcceptAllPhys; 2763 } else if (!(dev->flags & IFF_MULTICAST)) { 2764 rx_mode &= ~AcceptMulticast; 2765 } else if (dev->flags & IFF_ALLMULTI || 2766 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2767 /* accept all multicasts */ 2768 } else if (netdev_mc_empty(dev)) { 2769 rx_mode &= ~AcceptMulticast; 2770 } else { 2771 struct netdev_hw_addr *ha; 2772 2773 mc_filter[1] = mc_filter[0] = 0; 2774 netdev_for_each_mc_addr(ha, dev) { 2775 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2776 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2777 } 2778 2779 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2780 tmp = mc_filter[0]; 2781 mc_filter[0] = swab32(mc_filter[1]); 2782 mc_filter[1] = swab32(tmp); 2783 } 2784 } 2785 2786 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2787 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2788 2789 tmp = RTL_R32(tp, RxConfig); 2790 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2791 } 2792 2793 DECLARE_RTL_COND(rtl_csiar_cond) 2794 { 2795 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2796 } 2797 2798 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2799 { 2800 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2801 2802 RTL_W32(tp, CSIDR, value); 2803 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2804 CSIAR_BYTE_ENABLE | func << 16); 2805 2806 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2807 } 2808 2809 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2810 { 2811 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2812 2813 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2814 CSIAR_BYTE_ENABLE); 2815 2816 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2817 RTL_R32(tp, CSIDR) : ~0; 2818 } 2819 2820 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2821 { 2822 struct pci_dev *pdev = tp->pci_dev; 2823 u32 csi; 2824 2825 /* According to Realtek the value at config space address 0x070f 2826 * controls the L0s/L1 entrance latency. We try standard ECAM access 2827 * first and if it fails fall back to CSI. 2828 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2829 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2830 */ 2831 if (pdev->cfg_size > 0x070f && 2832 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2833 return; 2834 2835 netdev_notice_once(tp->dev, 2836 "No native access to PCI extended config space, falling back to CSI\n"); 2837 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2838 rtl_csi_write(tp, 0x070c, csi | val << 24); 2839 } 2840 2841 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2842 { 2843 /* L0 7us, L1 16us */ 2844 rtl_set_aspm_entry_latency(tp, 0x27); 2845 } 2846 2847 struct ephy_info { 2848 unsigned int offset; 2849 u16 mask; 2850 u16 bits; 2851 }; 2852 2853 static void __rtl_ephy_init(struct rtl8169_private *tp, 2854 const struct ephy_info *e, int len) 2855 { 2856 u16 w; 2857 2858 while (len-- > 0) { 2859 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2860 rtl_ephy_write(tp, e->offset, w); 2861 e++; 2862 } 2863 } 2864 2865 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2866 2867 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2868 { 2869 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2870 PCI_EXP_LNKCTL_CLKREQ_EN); 2871 } 2872 2873 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2874 { 2875 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2876 PCI_EXP_LNKCTL_CLKREQ_EN); 2877 } 2878 2879 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2880 { 2881 /* work around an issue when PCI reset occurs during L2/L3 state */ 2882 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2883 } 2884 2885 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2886 { 2887 /* Bits control which events trigger ASPM L1 exit: 2888 * Bit 12: rxdv 2889 * Bit 11: ltr_msg 2890 * Bit 10: txdma_poll 2891 * Bit 9: xadm 2892 * Bit 8: pktavi 2893 * Bit 7: txpla 2894 */ 2895 switch (tp->mac_version) { 2896 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2897 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2898 break; 2899 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2900 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2901 break; 2902 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 2903 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2904 break; 2905 default: 2906 break; 2907 } 2908 } 2909 2910 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2911 { 2912 switch (tp->mac_version) { 2913 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2914 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2915 break; 2916 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 2917 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2918 break; 2919 default: 2920 break; 2921 } 2922 } 2923 2924 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2925 { 2926 u8 val8; 2927 2928 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2929 return; 2930 2931 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2932 if (enable && tp->aspm_manageable) { 2933 /* On these chip versions ASPM can even harm 2934 * bus communication of other PCI devices. 2935 */ 2936 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2937 tp->mac_version == RTL_GIGA_MAC_VER_43) 2938 return; 2939 2940 rtl_mod_config5(tp, 0, ASPM_en); 2941 switch (tp->mac_version) { 2942 case RTL_GIGA_MAC_VER_65: 2943 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2944 RTL_W8(tp, INT_CFG0_8125, val8); 2945 break; 2946 default: 2947 rtl_mod_config2(tp, 0, ClkReqEn); 2948 break; 2949 } 2950 2951 switch (tp->mac_version) { 2952 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2953 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 2954 /* reset ephy tx/rx disable timer */ 2955 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2956 /* chip can trigger L1.2 */ 2957 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2958 break; 2959 default: 2960 break; 2961 } 2962 } else { 2963 switch (tp->mac_version) { 2964 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2965 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 2966 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2967 break; 2968 default: 2969 break; 2970 } 2971 2972 switch (tp->mac_version) { 2973 case RTL_GIGA_MAC_VER_65: 2974 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2975 RTL_W8(tp, INT_CFG0_8125, val8); 2976 break; 2977 default: 2978 rtl_mod_config2(tp, ClkReqEn, 0); 2979 break; 2980 } 2981 rtl_mod_config5(tp, ASPM_en, 0); 2982 } 2983 } 2984 2985 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2986 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2987 { 2988 /* Usage of dynamic vs. static FIFO is controlled by bit 2989 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2990 */ 2991 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2992 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2993 } 2994 2995 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2996 u8 low, u8 high) 2997 { 2998 /* FIFO thresholds for pause flow control */ 2999 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3000 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3001 } 3002 3003 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3004 { 3005 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3006 } 3007 3008 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3009 { 3010 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3011 3012 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3013 3014 rtl_disable_clock_request(tp); 3015 } 3016 3017 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3018 { 3019 static const struct ephy_info e_info_8168cp[] = { 3020 { 0x01, 0, 0x0001 }, 3021 { 0x02, 0x0800, 0x1000 }, 3022 { 0x03, 0, 0x0042 }, 3023 { 0x06, 0x0080, 0x0000 }, 3024 { 0x07, 0, 0x2000 } 3025 }; 3026 3027 rtl_set_def_aspm_entry_latency(tp); 3028 3029 rtl_ephy_init(tp, e_info_8168cp); 3030 3031 __rtl_hw_start_8168cp(tp); 3032 } 3033 3034 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3035 { 3036 rtl_set_def_aspm_entry_latency(tp); 3037 3038 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3039 } 3040 3041 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3042 { 3043 rtl_set_def_aspm_entry_latency(tp); 3044 3045 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3046 3047 /* Magic. */ 3048 RTL_W8(tp, DBG_REG, 0x20); 3049 } 3050 3051 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3052 { 3053 static const struct ephy_info e_info_8168c_1[] = { 3054 { 0x02, 0x0800, 0x1000 }, 3055 { 0x03, 0, 0x0002 }, 3056 { 0x06, 0x0080, 0x0000 } 3057 }; 3058 3059 rtl_set_def_aspm_entry_latency(tp); 3060 3061 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3062 3063 rtl_ephy_init(tp, e_info_8168c_1); 3064 3065 __rtl_hw_start_8168cp(tp); 3066 } 3067 3068 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3069 { 3070 static const struct ephy_info e_info_8168c_2[] = { 3071 { 0x01, 0, 0x0001 }, 3072 { 0x03, 0x0400, 0x0020 } 3073 }; 3074 3075 rtl_set_def_aspm_entry_latency(tp); 3076 3077 rtl_ephy_init(tp, e_info_8168c_2); 3078 3079 __rtl_hw_start_8168cp(tp); 3080 } 3081 3082 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3083 { 3084 rtl_set_def_aspm_entry_latency(tp); 3085 3086 __rtl_hw_start_8168cp(tp); 3087 } 3088 3089 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3090 { 3091 rtl_set_def_aspm_entry_latency(tp); 3092 3093 rtl_disable_clock_request(tp); 3094 } 3095 3096 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3097 { 3098 static const struct ephy_info e_info_8168d_4[] = { 3099 { 0x0b, 0x0000, 0x0048 }, 3100 { 0x19, 0x0020, 0x0050 }, 3101 { 0x0c, 0x0100, 0x0020 }, 3102 { 0x10, 0x0004, 0x0000 }, 3103 }; 3104 3105 rtl_set_def_aspm_entry_latency(tp); 3106 3107 rtl_ephy_init(tp, e_info_8168d_4); 3108 3109 rtl_enable_clock_request(tp); 3110 } 3111 3112 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3113 { 3114 static const struct ephy_info e_info_8168e_1[] = { 3115 { 0x00, 0x0200, 0x0100 }, 3116 { 0x00, 0x0000, 0x0004 }, 3117 { 0x06, 0x0002, 0x0001 }, 3118 { 0x06, 0x0000, 0x0030 }, 3119 { 0x07, 0x0000, 0x2000 }, 3120 { 0x00, 0x0000, 0x0020 }, 3121 { 0x03, 0x5800, 0x2000 }, 3122 { 0x03, 0x0000, 0x0001 }, 3123 { 0x01, 0x0800, 0x1000 }, 3124 { 0x07, 0x0000, 0x4000 }, 3125 { 0x1e, 0x0000, 0x2000 }, 3126 { 0x19, 0xffff, 0xfe6c }, 3127 { 0x0a, 0x0000, 0x0040 } 3128 }; 3129 3130 rtl_set_def_aspm_entry_latency(tp); 3131 3132 rtl_ephy_init(tp, e_info_8168e_1); 3133 3134 rtl_disable_clock_request(tp); 3135 3136 /* Reset tx FIFO pointer */ 3137 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3138 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3139 3140 rtl_mod_config5(tp, Spi_en, 0); 3141 } 3142 3143 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3144 { 3145 static const struct ephy_info e_info_8168e_2[] = { 3146 { 0x09, 0x0000, 0x0080 }, 3147 { 0x19, 0x0000, 0x0224 }, 3148 { 0x00, 0x0000, 0x0004 }, 3149 { 0x0c, 0x3df0, 0x0200 }, 3150 }; 3151 3152 rtl_set_def_aspm_entry_latency(tp); 3153 3154 rtl_ephy_init(tp, e_info_8168e_2); 3155 3156 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3157 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3158 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3159 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3160 rtl_reset_packet_filter(tp); 3161 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3162 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3163 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3164 3165 rtl_disable_clock_request(tp); 3166 3167 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3168 3169 rtl8168_config_eee_mac(tp); 3170 3171 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3172 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3173 rtl_mod_config5(tp, Spi_en, 0); 3174 } 3175 3176 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3177 { 3178 rtl_set_def_aspm_entry_latency(tp); 3179 3180 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3181 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3182 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3183 rtl_reset_packet_filter(tp); 3184 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3185 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3186 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3187 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3188 3189 rtl_disable_clock_request(tp); 3190 3191 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3192 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3193 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3194 rtl_mod_config5(tp, Spi_en, 0); 3195 3196 rtl8168_config_eee_mac(tp); 3197 } 3198 3199 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3200 { 3201 static const struct ephy_info e_info_8168f_1[] = { 3202 { 0x06, 0x00c0, 0x0020 }, 3203 { 0x08, 0x0001, 0x0002 }, 3204 { 0x09, 0x0000, 0x0080 }, 3205 { 0x19, 0x0000, 0x0224 }, 3206 { 0x00, 0x0000, 0x0008 }, 3207 { 0x0c, 0x3df0, 0x0200 }, 3208 }; 3209 3210 rtl_hw_start_8168f(tp); 3211 3212 rtl_ephy_init(tp, e_info_8168f_1); 3213 } 3214 3215 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3216 { 3217 static const struct ephy_info e_info_8168f_1[] = { 3218 { 0x06, 0x00c0, 0x0020 }, 3219 { 0x0f, 0xffff, 0x5200 }, 3220 { 0x19, 0x0000, 0x0224 }, 3221 { 0x00, 0x0000, 0x0008 }, 3222 { 0x0c, 0x3df0, 0x0200 }, 3223 }; 3224 3225 rtl_hw_start_8168f(tp); 3226 rtl_pcie_state_l2l3_disable(tp); 3227 3228 rtl_ephy_init(tp, e_info_8168f_1); 3229 } 3230 3231 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3232 { 3233 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3234 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3235 3236 rtl_set_def_aspm_entry_latency(tp); 3237 3238 rtl_reset_packet_filter(tp); 3239 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3240 3241 rtl_disable_rxdvgate(tp); 3242 3243 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3244 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3245 3246 rtl8168_config_eee_mac(tp); 3247 3248 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3249 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3250 3251 rtl_pcie_state_l2l3_disable(tp); 3252 } 3253 3254 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3255 { 3256 static const struct ephy_info e_info_8168g_1[] = { 3257 { 0x00, 0x0008, 0x0000 }, 3258 { 0x0c, 0x3ff0, 0x0820 }, 3259 { 0x1e, 0x0000, 0x0001 }, 3260 { 0x19, 0x8000, 0x0000 } 3261 }; 3262 3263 rtl_hw_start_8168g(tp); 3264 rtl_ephy_init(tp, e_info_8168g_1); 3265 } 3266 3267 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3268 { 3269 static const struct ephy_info e_info_8168g_2[] = { 3270 { 0x00, 0x0008, 0x0000 }, 3271 { 0x0c, 0x3ff0, 0x0820 }, 3272 { 0x19, 0xffff, 0x7c00 }, 3273 { 0x1e, 0xffff, 0x20eb }, 3274 { 0x0d, 0xffff, 0x1666 }, 3275 { 0x00, 0xffff, 0x10a3 }, 3276 { 0x06, 0xffff, 0xf050 }, 3277 { 0x04, 0x0000, 0x0010 }, 3278 { 0x1d, 0x4000, 0x0000 }, 3279 }; 3280 3281 rtl_hw_start_8168g(tp); 3282 rtl_ephy_init(tp, e_info_8168g_2); 3283 } 3284 3285 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3286 { 3287 static const u16 fix_data[] = { 3288 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3289 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3290 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3291 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3292 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3293 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3294 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3295 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3296 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3297 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3298 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3299 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3300 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3301 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3302 }; 3303 unsigned long flags; 3304 int i; 3305 3306 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3307 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3308 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3309 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3310 } 3311 3312 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3313 { 3314 static const struct ephy_info e_info_8411_2[] = { 3315 { 0x00, 0x0008, 0x0000 }, 3316 { 0x0c, 0x37d0, 0x0820 }, 3317 { 0x1e, 0x0000, 0x0001 }, 3318 { 0x19, 0x8021, 0x0000 }, 3319 { 0x1e, 0x0000, 0x2000 }, 3320 { 0x0d, 0x0100, 0x0200 }, 3321 { 0x00, 0x0000, 0x0080 }, 3322 { 0x06, 0x0000, 0x0010 }, 3323 { 0x04, 0x0000, 0x0010 }, 3324 { 0x1d, 0x0000, 0x4000 }, 3325 }; 3326 3327 rtl_hw_start_8168g(tp); 3328 3329 rtl_ephy_init(tp, e_info_8411_2); 3330 3331 /* The following Realtek-provided magic fixes an issue with the RX unit 3332 * getting confused after the PHY having been powered-down. 3333 */ 3334 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3335 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3336 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3337 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3338 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3339 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3340 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3341 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3342 mdelay(3); 3343 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3344 3345 rtl8411b_fix_phy_down(tp); 3346 3347 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3348 3349 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3350 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3351 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3352 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3353 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3354 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3355 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3356 } 3357 3358 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3359 { 3360 static const struct ephy_info e_info_8168h_1[] = { 3361 { 0x1e, 0x0800, 0x0001 }, 3362 { 0x1d, 0x0000, 0x0800 }, 3363 { 0x05, 0xffff, 0x2089 }, 3364 { 0x06, 0xffff, 0x5881 }, 3365 { 0x04, 0xffff, 0x854a }, 3366 { 0x01, 0xffff, 0x068b } 3367 }; 3368 int rg_saw_cnt; 3369 3370 rtl_ephy_init(tp, e_info_8168h_1); 3371 3372 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3373 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3374 3375 rtl_set_def_aspm_entry_latency(tp); 3376 3377 rtl_reset_packet_filter(tp); 3378 3379 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3380 3381 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3382 3383 rtl_disable_rxdvgate(tp); 3384 3385 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3386 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3387 3388 rtl8168_config_eee_mac(tp); 3389 3390 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3391 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3392 3393 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3394 3395 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3396 3397 rtl_pcie_state_l2l3_disable(tp); 3398 3399 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3400 if (rg_saw_cnt > 0) { 3401 u16 sw_cnt_1ms_ini; 3402 3403 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3404 sw_cnt_1ms_ini &= 0x0fff; 3405 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3406 } 3407 3408 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3409 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3410 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3411 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3412 3413 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3414 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3415 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3416 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3417 } 3418 3419 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3420 { 3421 rtl8168ep_stop_cmac(tp); 3422 3423 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3424 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3425 3426 rtl_set_def_aspm_entry_latency(tp); 3427 3428 rtl_reset_packet_filter(tp); 3429 3430 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3431 3432 rtl_disable_rxdvgate(tp); 3433 3434 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3435 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3436 3437 rtl8168_config_eee_mac(tp); 3438 3439 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3440 3441 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3442 3443 rtl_pcie_state_l2l3_disable(tp); 3444 } 3445 3446 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3447 { 3448 static const struct ephy_info e_info_8168ep_3[] = { 3449 { 0x00, 0x0000, 0x0080 }, 3450 { 0x0d, 0x0100, 0x0200 }, 3451 { 0x19, 0x8021, 0x0000 }, 3452 { 0x1e, 0x0000, 0x2000 }, 3453 }; 3454 3455 rtl_ephy_init(tp, e_info_8168ep_3); 3456 3457 rtl_hw_start_8168ep(tp); 3458 3459 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3460 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3461 3462 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3463 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3464 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3465 } 3466 3467 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3468 { 3469 static const struct ephy_info e_info_8117[] = { 3470 { 0x19, 0x0040, 0x1100 }, 3471 { 0x59, 0x0040, 0x1100 }, 3472 }; 3473 int rg_saw_cnt; 3474 3475 rtl8168ep_stop_cmac(tp); 3476 rtl_ephy_init(tp, e_info_8117); 3477 3478 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3479 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3480 3481 rtl_set_def_aspm_entry_latency(tp); 3482 3483 rtl_reset_packet_filter(tp); 3484 3485 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3486 3487 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3488 3489 rtl_disable_rxdvgate(tp); 3490 3491 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3492 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3493 3494 rtl8168_config_eee_mac(tp); 3495 3496 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3497 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3498 3499 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3500 3501 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3502 3503 rtl_pcie_state_l2l3_disable(tp); 3504 3505 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3506 if (rg_saw_cnt > 0) { 3507 u16 sw_cnt_1ms_ini; 3508 3509 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3510 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3511 } 3512 3513 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3514 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3515 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3516 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3517 3518 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3519 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3520 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3521 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3522 3523 /* firmware is for MAC only */ 3524 r8169_apply_firmware(tp); 3525 } 3526 3527 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3528 { 3529 static const struct ephy_info e_info_8102e_1[] = { 3530 { 0x01, 0, 0x6e65 }, 3531 { 0x02, 0, 0x091f }, 3532 { 0x03, 0, 0xc2f9 }, 3533 { 0x06, 0, 0xafb5 }, 3534 { 0x07, 0, 0x0e00 }, 3535 { 0x19, 0, 0xec80 }, 3536 { 0x01, 0, 0x2e65 }, 3537 { 0x01, 0, 0x6e65 } 3538 }; 3539 u8 cfg1; 3540 3541 rtl_set_def_aspm_entry_latency(tp); 3542 3543 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3544 3545 RTL_W8(tp, Config1, 3546 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3547 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3548 3549 cfg1 = RTL_R8(tp, Config1); 3550 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3551 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3552 3553 rtl_ephy_init(tp, e_info_8102e_1); 3554 } 3555 3556 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3557 { 3558 rtl_set_def_aspm_entry_latency(tp); 3559 3560 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3561 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3562 } 3563 3564 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3565 { 3566 rtl_hw_start_8102e_2(tp); 3567 3568 rtl_ephy_write(tp, 0x03, 0xc2f9); 3569 } 3570 3571 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3572 { 3573 static const struct ephy_info e_info_8401[] = { 3574 { 0x01, 0xffff, 0x6fe5 }, 3575 { 0x03, 0xffff, 0x0599 }, 3576 { 0x06, 0xffff, 0xaf25 }, 3577 { 0x07, 0xffff, 0x8e68 }, 3578 }; 3579 3580 rtl_ephy_init(tp, e_info_8401); 3581 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3582 } 3583 3584 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3585 { 3586 static const struct ephy_info e_info_8105e_1[] = { 3587 { 0x07, 0, 0x4000 }, 3588 { 0x19, 0, 0x0200 }, 3589 { 0x19, 0, 0x0020 }, 3590 { 0x1e, 0, 0x2000 }, 3591 { 0x03, 0, 0x0001 }, 3592 { 0x19, 0, 0x0100 }, 3593 { 0x19, 0, 0x0004 }, 3594 { 0x0a, 0, 0x0020 } 3595 }; 3596 3597 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3598 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3599 3600 /* Disable Early Tally Counter */ 3601 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3602 3603 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3604 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3605 3606 rtl_ephy_init(tp, e_info_8105e_1); 3607 3608 rtl_pcie_state_l2l3_disable(tp); 3609 } 3610 3611 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3612 { 3613 rtl_hw_start_8105e_1(tp); 3614 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3615 } 3616 3617 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3618 { 3619 static const struct ephy_info e_info_8402[] = { 3620 { 0x19, 0xffff, 0xff64 }, 3621 { 0x1e, 0, 0x4000 } 3622 }; 3623 3624 rtl_set_def_aspm_entry_latency(tp); 3625 3626 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3627 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3628 3629 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3630 3631 rtl_ephy_init(tp, e_info_8402); 3632 3633 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3634 rtl_reset_packet_filter(tp); 3635 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3636 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3637 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3638 3639 /* disable EEE */ 3640 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3641 3642 rtl_pcie_state_l2l3_disable(tp); 3643 } 3644 3645 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3646 { 3647 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3648 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3649 3650 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3651 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3652 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3653 3654 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3655 rtl_set_aspm_entry_latency(tp, 0x2f); 3656 3657 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3658 3659 /* disable EEE */ 3660 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3661 3662 rtl_pcie_state_l2l3_disable(tp); 3663 } 3664 3665 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3666 { 3667 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3668 } 3669 3670 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3671 { 3672 rtl_pcie_state_l2l3_disable(tp); 3673 3674 RTL_W16(tp, 0x382, 0x221b); 3675 RTL_W8(tp, 0x4500, 0); 3676 RTL_W16(tp, 0x4800, 0); 3677 3678 /* disable UPS */ 3679 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3680 3681 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3682 3683 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3684 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3685 3686 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3687 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3688 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3689 3690 /* disable new tx descriptor format */ 3691 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3692 3693 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3694 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3695 3696 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3697 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3698 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3699 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3700 else 3701 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3702 3703 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3704 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3705 else 3706 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3707 3708 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3709 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3710 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3711 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3712 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3713 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3714 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3715 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3716 else 3717 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3718 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3719 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3720 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3721 3722 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3723 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3724 udelay(1); 3725 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3726 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3727 3728 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3729 3730 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3731 3732 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3733 rtl8125a_config_eee_mac(tp); 3734 else 3735 rtl8125b_config_eee_mac(tp); 3736 3737 rtl_disable_rxdvgate(tp); 3738 } 3739 3740 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3741 { 3742 static const struct ephy_info e_info_8125a_2[] = { 3743 { 0x04, 0xffff, 0xd000 }, 3744 { 0x0a, 0xffff, 0x8653 }, 3745 { 0x23, 0xffff, 0xab66 }, 3746 { 0x20, 0xffff, 0x9455 }, 3747 { 0x21, 0xffff, 0x99ff }, 3748 { 0x29, 0xffff, 0xfe04 }, 3749 3750 { 0x44, 0xffff, 0xd000 }, 3751 { 0x4a, 0xffff, 0x8653 }, 3752 { 0x63, 0xffff, 0xab66 }, 3753 { 0x60, 0xffff, 0x9455 }, 3754 { 0x61, 0xffff, 0x99ff }, 3755 { 0x69, 0xffff, 0xfe04 }, 3756 }; 3757 3758 rtl_set_def_aspm_entry_latency(tp); 3759 rtl_ephy_init(tp, e_info_8125a_2); 3760 rtl_hw_start_8125_common(tp); 3761 } 3762 3763 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3764 { 3765 static const struct ephy_info e_info_8125b[] = { 3766 { 0x0b, 0xffff, 0xa908 }, 3767 { 0x1e, 0xffff, 0x20eb }, 3768 { 0x4b, 0xffff, 0xa908 }, 3769 { 0x5e, 0xffff, 0x20eb }, 3770 { 0x22, 0x0030, 0x0020 }, 3771 { 0x62, 0x0030, 0x0020 }, 3772 }; 3773 3774 rtl_set_def_aspm_entry_latency(tp); 3775 rtl_ephy_init(tp, e_info_8125b); 3776 rtl_hw_start_8125_common(tp); 3777 } 3778 3779 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3780 { 3781 rtl_set_def_aspm_entry_latency(tp); 3782 rtl_hw_start_8125_common(tp); 3783 } 3784 3785 static void rtl_hw_config(struct rtl8169_private *tp) 3786 { 3787 static const rtl_generic_fct hw_configs[] = { 3788 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3789 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3790 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3791 [RTL_GIGA_MAC_VER_10] = NULL, 3792 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3793 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3794 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3795 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3796 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3797 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3798 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3799 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3800 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3801 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3802 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3803 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3804 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3805 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3806 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3807 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3808 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3809 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3810 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3811 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3812 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3813 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3814 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3815 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3816 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3817 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3818 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3819 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3820 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3821 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3822 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3823 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3824 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3825 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3826 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3827 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3828 }; 3829 3830 if (hw_configs[tp->mac_version]) 3831 hw_configs[tp->mac_version](tp); 3832 } 3833 3834 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3835 { 3836 int i; 3837 3838 RTL_W8(tp, INT_CFG0_8125, 0x00); 3839 3840 /* disable interrupt coalescing */ 3841 switch (tp->mac_version) { 3842 case RTL_GIGA_MAC_VER_61: 3843 for (i = 0xa00; i < 0xb00; i += 4) 3844 RTL_W32(tp, i, 0); 3845 break; 3846 case RTL_GIGA_MAC_VER_63: 3847 case RTL_GIGA_MAC_VER_65: 3848 for (i = 0xa00; i < 0xa80; i += 4) 3849 RTL_W32(tp, i, 0); 3850 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3851 break; 3852 default: 3853 break; 3854 } 3855 3856 rtl_hw_config(tp); 3857 } 3858 3859 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3860 { 3861 if (rtl_is_8168evl_up(tp)) 3862 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3863 else 3864 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3865 3866 rtl_hw_config(tp); 3867 3868 /* disable interrupt coalescing */ 3869 RTL_W16(tp, IntrMitigate, 0x0000); 3870 } 3871 3872 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3873 { 3874 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3875 3876 tp->cp_cmd |= PCIMulRW; 3877 3878 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3879 tp->mac_version == RTL_GIGA_MAC_VER_03) 3880 tp->cp_cmd |= EnAnaPLL; 3881 3882 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3883 3884 rtl8169_set_magic_reg(tp); 3885 3886 /* disable interrupt coalescing */ 3887 RTL_W16(tp, IntrMitigate, 0x0000); 3888 } 3889 3890 static void rtl_hw_start(struct rtl8169_private *tp) 3891 { 3892 rtl_unlock_config_regs(tp); 3893 /* disable aspm and clock request before ephy access */ 3894 rtl_hw_aspm_clkreq_enable(tp, false); 3895 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3896 3897 rtl_set_eee_txidle_timer(tp); 3898 3899 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3900 rtl_hw_start_8169(tp); 3901 else if (rtl_is_8125(tp)) 3902 rtl_hw_start_8125(tp); 3903 else 3904 rtl_hw_start_8168(tp); 3905 3906 rtl_enable_exit_l1(tp); 3907 rtl_hw_aspm_clkreq_enable(tp, true); 3908 rtl_set_rx_max_size(tp); 3909 rtl_set_rx_tx_desc_registers(tp); 3910 rtl_lock_config_regs(tp); 3911 3912 rtl_jumbo_config(tp); 3913 3914 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3915 rtl_pci_commit(tp); 3916 3917 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3918 rtl_init_rxcfg(tp); 3919 rtl_set_tx_config_registers(tp); 3920 rtl_set_rx_config_features(tp, tp->dev->features); 3921 rtl_set_rx_mode(tp->dev); 3922 rtl_irq_enable(tp); 3923 } 3924 3925 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3926 { 3927 struct rtl8169_private *tp = netdev_priv(dev); 3928 3929 WRITE_ONCE(dev->mtu, new_mtu); 3930 netdev_update_features(dev); 3931 rtl_jumbo_config(tp); 3932 rtl_set_eee_txidle_timer(tp); 3933 3934 return 0; 3935 } 3936 3937 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3938 { 3939 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3940 3941 desc->opts2 = 0; 3942 /* Force memory writes to complete before releasing descriptor */ 3943 dma_wmb(); 3944 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3945 } 3946 3947 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3948 struct RxDesc *desc) 3949 { 3950 struct device *d = tp_to_dev(tp); 3951 int node = dev_to_node(d); 3952 dma_addr_t mapping; 3953 struct page *data; 3954 3955 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3956 if (!data) 3957 return NULL; 3958 3959 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3960 if (unlikely(dma_mapping_error(d, mapping))) { 3961 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3962 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3963 return NULL; 3964 } 3965 3966 desc->addr = cpu_to_le64(mapping); 3967 rtl8169_mark_to_asic(desc); 3968 3969 return data; 3970 } 3971 3972 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3973 { 3974 int i; 3975 3976 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3977 dma_unmap_page(tp_to_dev(tp), 3978 le64_to_cpu(tp->RxDescArray[i].addr), 3979 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3980 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3981 tp->Rx_databuff[i] = NULL; 3982 tp->RxDescArray[i].addr = 0; 3983 tp->RxDescArray[i].opts1 = 0; 3984 } 3985 } 3986 3987 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3988 { 3989 int i; 3990 3991 for (i = 0; i < NUM_RX_DESC; i++) { 3992 struct page *data; 3993 3994 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3995 if (!data) { 3996 rtl8169_rx_clear(tp); 3997 return -ENOMEM; 3998 } 3999 tp->Rx_databuff[i] = data; 4000 } 4001 4002 /* mark as last descriptor in the ring */ 4003 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4004 4005 return 0; 4006 } 4007 4008 static int rtl8169_init_ring(struct rtl8169_private *tp) 4009 { 4010 rtl8169_init_ring_indexes(tp); 4011 4012 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4013 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4014 4015 return rtl8169_rx_fill(tp); 4016 } 4017 4018 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4019 { 4020 struct ring_info *tx_skb = tp->tx_skb + entry; 4021 struct TxDesc *desc = tp->TxDescArray + entry; 4022 4023 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4024 DMA_TO_DEVICE); 4025 memset(desc, 0, sizeof(*desc)); 4026 memset(tx_skb, 0, sizeof(*tx_skb)); 4027 } 4028 4029 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4030 unsigned int n) 4031 { 4032 unsigned int i; 4033 4034 for (i = 0; i < n; i++) { 4035 unsigned int entry = (start + i) % NUM_TX_DESC; 4036 struct ring_info *tx_skb = tp->tx_skb + entry; 4037 unsigned int len = tx_skb->len; 4038 4039 if (len) { 4040 struct sk_buff *skb = tx_skb->skb; 4041 4042 rtl8169_unmap_tx_skb(tp, entry); 4043 if (skb) 4044 dev_consume_skb_any(skb); 4045 } 4046 } 4047 } 4048 4049 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4050 { 4051 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4052 netdev_reset_queue(tp->dev); 4053 } 4054 4055 static void rtl8169_cleanup(struct rtl8169_private *tp) 4056 { 4057 napi_disable(&tp->napi); 4058 4059 /* Give a racing hard_start_xmit a few cycles to complete. */ 4060 synchronize_net(); 4061 4062 /* Disable interrupts */ 4063 rtl8169_irq_mask_and_ack(tp); 4064 4065 rtl_rx_close(tp); 4066 4067 switch (tp->mac_version) { 4068 case RTL_GIGA_MAC_VER_28: 4069 case RTL_GIGA_MAC_VER_31: 4070 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4071 break; 4072 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4073 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4074 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4075 break; 4076 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 4077 rtl_enable_rxdvgate(tp); 4078 fsleep(2000); 4079 break; 4080 default: 4081 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4082 fsleep(100); 4083 break; 4084 } 4085 4086 rtl_hw_reset(tp); 4087 4088 rtl8169_tx_clear(tp); 4089 rtl8169_init_ring_indexes(tp); 4090 } 4091 4092 static void rtl_reset_work(struct rtl8169_private *tp) 4093 { 4094 int i; 4095 4096 netif_stop_queue(tp->dev); 4097 4098 rtl8169_cleanup(tp); 4099 4100 for (i = 0; i < NUM_RX_DESC; i++) 4101 rtl8169_mark_to_asic(tp->RxDescArray + i); 4102 4103 napi_enable(&tp->napi); 4104 rtl_hw_start(tp); 4105 } 4106 4107 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4108 { 4109 struct rtl8169_private *tp = netdev_priv(dev); 4110 4111 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4112 } 4113 4114 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4115 void *addr, unsigned int entry, bool desc_own) 4116 { 4117 struct TxDesc *txd = tp->TxDescArray + entry; 4118 struct device *d = tp_to_dev(tp); 4119 dma_addr_t mapping; 4120 u32 opts1; 4121 int ret; 4122 4123 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4124 ret = dma_mapping_error(d, mapping); 4125 if (unlikely(ret)) { 4126 if (net_ratelimit()) 4127 netdev_err(tp->dev, "Failed to map TX data!\n"); 4128 return ret; 4129 } 4130 4131 txd->addr = cpu_to_le64(mapping); 4132 txd->opts2 = cpu_to_le32(opts[1]); 4133 4134 opts1 = opts[0] | len; 4135 if (entry == NUM_TX_DESC - 1) 4136 opts1 |= RingEnd; 4137 if (desc_own) 4138 opts1 |= DescOwn; 4139 txd->opts1 = cpu_to_le32(opts1); 4140 4141 tp->tx_skb[entry].len = len; 4142 4143 return 0; 4144 } 4145 4146 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4147 const u32 *opts, unsigned int entry) 4148 { 4149 struct skb_shared_info *info = skb_shinfo(skb); 4150 unsigned int cur_frag; 4151 4152 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4153 const skb_frag_t *frag = info->frags + cur_frag; 4154 void *addr = skb_frag_address(frag); 4155 u32 len = skb_frag_size(frag); 4156 4157 entry = (entry + 1) % NUM_TX_DESC; 4158 4159 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4160 goto err_out; 4161 } 4162 4163 return 0; 4164 4165 err_out: 4166 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4167 return -EIO; 4168 } 4169 4170 static bool rtl_skb_is_udp(struct sk_buff *skb) 4171 { 4172 int no = skb_network_offset(skb); 4173 struct ipv6hdr *i6h, _i6h; 4174 struct iphdr *ih, _ih; 4175 4176 switch (vlan_get_protocol(skb)) { 4177 case htons(ETH_P_IP): 4178 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4179 return ih && ih->protocol == IPPROTO_UDP; 4180 case htons(ETH_P_IPV6): 4181 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4182 return i6h && i6h->nexthdr == IPPROTO_UDP; 4183 default: 4184 return false; 4185 } 4186 } 4187 4188 #define RTL_MIN_PATCH_LEN 47 4189 4190 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4191 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4192 struct sk_buff *skb) 4193 { 4194 unsigned int padto = 0, len = skb->len; 4195 4196 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4197 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4198 unsigned int trans_data_len = skb_tail_pointer(skb) - 4199 skb_transport_header(skb); 4200 4201 if (trans_data_len >= offsetof(struct udphdr, len) && 4202 trans_data_len < RTL_MIN_PATCH_LEN) { 4203 u16 dest = ntohs(udp_hdr(skb)->dest); 4204 4205 /* dest is a standard PTP port */ 4206 if (dest == 319 || dest == 320) 4207 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4208 } 4209 4210 if (trans_data_len < sizeof(struct udphdr)) 4211 padto = max_t(unsigned int, padto, 4212 len + sizeof(struct udphdr) - trans_data_len); 4213 } 4214 4215 return padto; 4216 } 4217 4218 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4219 struct sk_buff *skb) 4220 { 4221 unsigned int padto; 4222 4223 padto = rtl8125_quirk_udp_padto(tp, skb); 4224 4225 switch (tp->mac_version) { 4226 case RTL_GIGA_MAC_VER_34: 4227 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 4228 padto = max_t(unsigned int, padto, ETH_ZLEN); 4229 break; 4230 default: 4231 break; 4232 } 4233 4234 return padto; 4235 } 4236 4237 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4238 { 4239 u32 mss = skb_shinfo(skb)->gso_size; 4240 4241 if (mss) { 4242 opts[0] |= TD_LSO; 4243 opts[0] |= mss << TD0_MSS_SHIFT; 4244 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4245 const struct iphdr *ip = ip_hdr(skb); 4246 4247 if (ip->protocol == IPPROTO_TCP) 4248 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4249 else if (ip->protocol == IPPROTO_UDP) 4250 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4251 else 4252 WARN_ON_ONCE(1); 4253 } 4254 } 4255 4256 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4257 struct sk_buff *skb, u32 *opts) 4258 { 4259 struct skb_shared_info *shinfo = skb_shinfo(skb); 4260 u32 mss = shinfo->gso_size; 4261 4262 if (mss) { 4263 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4264 opts[0] |= TD1_GTSENV4; 4265 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4266 if (skb_cow_head(skb, 0)) 4267 return false; 4268 4269 tcp_v6_gso_csum_prep(skb); 4270 opts[0] |= TD1_GTSENV6; 4271 } else { 4272 WARN_ON_ONCE(1); 4273 } 4274 4275 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4276 opts[1] |= mss << TD1_MSS_SHIFT; 4277 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4278 u8 ip_protocol; 4279 4280 switch (vlan_get_protocol(skb)) { 4281 case htons(ETH_P_IP): 4282 opts[1] |= TD1_IPv4_CS; 4283 ip_protocol = ip_hdr(skb)->protocol; 4284 break; 4285 4286 case htons(ETH_P_IPV6): 4287 opts[1] |= TD1_IPv6_CS; 4288 ip_protocol = ipv6_hdr(skb)->nexthdr; 4289 break; 4290 4291 default: 4292 ip_protocol = IPPROTO_RAW; 4293 break; 4294 } 4295 4296 if (ip_protocol == IPPROTO_TCP) 4297 opts[1] |= TD1_TCP_CS; 4298 else if (ip_protocol == IPPROTO_UDP) 4299 opts[1] |= TD1_UDP_CS; 4300 else 4301 WARN_ON_ONCE(1); 4302 4303 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4304 } else { 4305 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4306 4307 /* skb_padto would free the skb on error */ 4308 return !__skb_put_padto(skb, padto, false); 4309 } 4310 4311 return true; 4312 } 4313 4314 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4315 { 4316 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4317 } 4318 4319 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4320 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4321 { 4322 switch (tp->mac_version) { 4323 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4324 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4325 return false; 4326 default: 4327 return true; 4328 } 4329 } 4330 4331 static void rtl8169_doorbell(struct rtl8169_private *tp) 4332 { 4333 if (rtl_is_8125(tp)) 4334 RTL_W16(tp, TxPoll_8125, BIT(0)); 4335 else 4336 RTL_W8(tp, TxPoll, NPQ); 4337 } 4338 4339 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4340 struct net_device *dev) 4341 { 4342 struct rtl8169_private *tp = netdev_priv(dev); 4343 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4344 struct TxDesc *txd_first, *txd_last; 4345 bool stop_queue, door_bell; 4346 unsigned int frags; 4347 u32 opts[2]; 4348 4349 if (unlikely(!rtl_tx_slots_avail(tp))) { 4350 if (net_ratelimit()) 4351 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4352 goto err_stop_0; 4353 } 4354 4355 opts[1] = rtl8169_tx_vlan_tag(skb); 4356 opts[0] = 0; 4357 4358 if (!rtl_chip_supports_csum_v2(tp)) 4359 rtl8169_tso_csum_v1(skb, opts); 4360 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4361 goto err_dma_0; 4362 4363 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4364 entry, false))) 4365 goto err_dma_0; 4366 4367 txd_first = tp->TxDescArray + entry; 4368 4369 frags = skb_shinfo(skb)->nr_frags; 4370 if (frags) { 4371 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4372 goto err_dma_1; 4373 entry = (entry + frags) % NUM_TX_DESC; 4374 } 4375 4376 txd_last = tp->TxDescArray + entry; 4377 txd_last->opts1 |= cpu_to_le32(LastFrag); 4378 tp->tx_skb[entry].skb = skb; 4379 4380 skb_tx_timestamp(skb); 4381 4382 /* Force memory writes to complete before releasing descriptor */ 4383 dma_wmb(); 4384 4385 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4386 4387 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4388 4389 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4390 smp_wmb(); 4391 4392 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4393 4394 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4395 R8169_TX_STOP_THRS, 4396 R8169_TX_START_THRS); 4397 if (door_bell || stop_queue) 4398 rtl8169_doorbell(tp); 4399 4400 return NETDEV_TX_OK; 4401 4402 err_dma_1: 4403 rtl8169_unmap_tx_skb(tp, entry); 4404 err_dma_0: 4405 dev_kfree_skb_any(skb); 4406 dev->stats.tx_dropped++; 4407 return NETDEV_TX_OK; 4408 4409 err_stop_0: 4410 netif_stop_queue(dev); 4411 dev->stats.tx_dropped++; 4412 return NETDEV_TX_BUSY; 4413 } 4414 4415 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4416 { 4417 struct skb_shared_info *info = skb_shinfo(skb); 4418 unsigned int nr_frags = info->nr_frags; 4419 4420 if (!nr_frags) 4421 return UINT_MAX; 4422 4423 return skb_frag_size(info->frags + nr_frags - 1); 4424 } 4425 4426 /* Workaround for hw issues with TSO on RTL8168evl */ 4427 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4428 netdev_features_t features) 4429 { 4430 /* IPv4 header has options field */ 4431 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4432 ip_hdrlen(skb) > sizeof(struct iphdr)) 4433 features &= ~NETIF_F_ALL_TSO; 4434 4435 /* IPv4 TCP header has options field */ 4436 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4437 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4438 features &= ~NETIF_F_ALL_TSO; 4439 4440 else if (rtl_last_frag_len(skb) <= 6) 4441 features &= ~NETIF_F_ALL_TSO; 4442 4443 return features; 4444 } 4445 4446 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4447 struct net_device *dev, 4448 netdev_features_t features) 4449 { 4450 struct rtl8169_private *tp = netdev_priv(dev); 4451 4452 if (skb_is_gso(skb)) { 4453 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4454 features = rtl8168evl_fix_tso(skb, features); 4455 4456 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4457 rtl_chip_supports_csum_v2(tp)) 4458 features &= ~NETIF_F_ALL_TSO; 4459 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4460 /* work around hw bug on some chip versions */ 4461 if (skb->len < ETH_ZLEN) 4462 features &= ~NETIF_F_CSUM_MASK; 4463 4464 if (rtl_quirk_packet_padto(tp, skb)) 4465 features &= ~NETIF_F_CSUM_MASK; 4466 4467 if (skb_transport_offset(skb) > TCPHO_MAX && 4468 rtl_chip_supports_csum_v2(tp)) 4469 features &= ~NETIF_F_CSUM_MASK; 4470 } 4471 4472 return vlan_features_check(skb, features); 4473 } 4474 4475 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4476 { 4477 struct rtl8169_private *tp = netdev_priv(dev); 4478 struct pci_dev *pdev = tp->pci_dev; 4479 int pci_status_errs; 4480 u16 pci_cmd; 4481 4482 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4483 4484 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4485 4486 if (net_ratelimit()) 4487 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4488 pci_cmd, pci_status_errs); 4489 4490 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4491 } 4492 4493 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4494 int budget) 4495 { 4496 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4497 struct sk_buff *skb; 4498 4499 dirty_tx = tp->dirty_tx; 4500 4501 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4502 unsigned int entry = dirty_tx % NUM_TX_DESC; 4503 u32 status; 4504 4505 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4506 if (status & DescOwn) 4507 break; 4508 4509 skb = tp->tx_skb[entry].skb; 4510 rtl8169_unmap_tx_skb(tp, entry); 4511 4512 if (skb) { 4513 pkts_compl++; 4514 bytes_compl += skb->len; 4515 napi_consume_skb(skb, budget); 4516 } 4517 dirty_tx++; 4518 } 4519 4520 if (tp->dirty_tx != dirty_tx) { 4521 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4522 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4523 4524 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4525 rtl_tx_slots_avail(tp), 4526 R8169_TX_START_THRS); 4527 /* 4528 * 8168 hack: TxPoll requests are lost when the Tx packets are 4529 * too close. Let's kick an extra TxPoll request when a burst 4530 * of start_xmit activity is detected (if it is not detected, 4531 * it is slow enough). -- FR 4532 * If skb is NULL then we come here again once a tx irq is 4533 * triggered after the last fragment is marked transmitted. 4534 */ 4535 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4536 rtl8169_doorbell(tp); 4537 } 4538 } 4539 4540 static inline int rtl8169_fragmented_frame(u32 status) 4541 { 4542 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4543 } 4544 4545 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4546 { 4547 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4548 4549 if (status == RxProtoTCP || status == RxProtoUDP) 4550 skb->ip_summed = CHECKSUM_UNNECESSARY; 4551 else 4552 skb_checksum_none_assert(skb); 4553 } 4554 4555 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4556 { 4557 struct device *d = tp_to_dev(tp); 4558 int count; 4559 4560 for (count = 0; count < budget; count++, tp->cur_rx++) { 4561 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4562 struct RxDesc *desc = tp->RxDescArray + entry; 4563 struct sk_buff *skb; 4564 const void *rx_buf; 4565 dma_addr_t addr; 4566 u32 status; 4567 4568 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4569 if (status & DescOwn) 4570 break; 4571 4572 /* This barrier is needed to keep us from reading 4573 * any other fields out of the Rx descriptor until 4574 * we know the status of DescOwn 4575 */ 4576 dma_rmb(); 4577 4578 if (unlikely(status & RxRES)) { 4579 if (net_ratelimit()) 4580 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4581 status); 4582 dev->stats.rx_errors++; 4583 if (status & (RxRWT | RxRUNT)) 4584 dev->stats.rx_length_errors++; 4585 if (status & RxCRC) 4586 dev->stats.rx_crc_errors++; 4587 4588 if (!(dev->features & NETIF_F_RXALL)) 4589 goto release_descriptor; 4590 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4591 goto release_descriptor; 4592 } 4593 4594 pkt_size = status & GENMASK(13, 0); 4595 if (likely(!(dev->features & NETIF_F_RXFCS))) 4596 pkt_size -= ETH_FCS_LEN; 4597 4598 /* The driver does not support incoming fragmented frames. 4599 * They are seen as a symptom of over-mtu sized frames. 4600 */ 4601 if (unlikely(rtl8169_fragmented_frame(status))) { 4602 dev->stats.rx_dropped++; 4603 dev->stats.rx_length_errors++; 4604 goto release_descriptor; 4605 } 4606 4607 skb = napi_alloc_skb(&tp->napi, pkt_size); 4608 if (unlikely(!skb)) { 4609 dev->stats.rx_dropped++; 4610 goto release_descriptor; 4611 } 4612 4613 addr = le64_to_cpu(desc->addr); 4614 rx_buf = page_address(tp->Rx_databuff[entry]); 4615 4616 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4617 prefetch(rx_buf); 4618 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4619 skb->tail += pkt_size; 4620 skb->len = pkt_size; 4621 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4622 4623 rtl8169_rx_csum(skb, status); 4624 skb->protocol = eth_type_trans(skb, dev); 4625 4626 rtl8169_rx_vlan_tag(desc, skb); 4627 4628 if (skb->pkt_type == PACKET_MULTICAST) 4629 dev->stats.multicast++; 4630 4631 napi_gro_receive(&tp->napi, skb); 4632 4633 dev_sw_netstats_rx_add(dev, pkt_size); 4634 release_descriptor: 4635 rtl8169_mark_to_asic(desc); 4636 } 4637 4638 return count; 4639 } 4640 4641 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4642 { 4643 struct rtl8169_private *tp = dev_instance; 4644 u32 status = rtl_get_events(tp); 4645 4646 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4647 return IRQ_NONE; 4648 4649 if (unlikely(status & SYSErr)) { 4650 rtl8169_pcierr_interrupt(tp->dev); 4651 goto out; 4652 } 4653 4654 if (status & LinkChg) 4655 phy_mac_interrupt(tp->phydev); 4656 4657 if (unlikely(status & RxFIFOOver && 4658 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4659 netif_stop_queue(tp->dev); 4660 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4661 } 4662 4663 rtl_irq_disable(tp); 4664 napi_schedule(&tp->napi); 4665 out: 4666 rtl_ack_events(tp, status); 4667 4668 return IRQ_HANDLED; 4669 } 4670 4671 static void rtl_task(struct work_struct *work) 4672 { 4673 struct rtl8169_private *tp = 4674 container_of(work, struct rtl8169_private, wk.work); 4675 int ret; 4676 4677 rtnl_lock(); 4678 4679 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4680 goto out_unlock; 4681 4682 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4683 /* if chip isn't accessible, reset bus to revive it */ 4684 if (RTL_R32(tp, TxConfig) == ~0) { 4685 ret = pci_reset_bus(tp->pci_dev); 4686 if (ret < 0) { 4687 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4688 netif_device_detach(tp->dev); 4689 goto out_unlock; 4690 } 4691 } 4692 4693 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4694 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4695 PCIE_LINK_STATE_L0S); 4696 if (!ret) 4697 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4698 goto reset; 4699 } 4700 4701 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4702 reset: 4703 rtl_reset_work(tp); 4704 netif_wake_queue(tp->dev); 4705 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4706 rtl_reset_work(tp); 4707 } 4708 out_unlock: 4709 rtnl_unlock(); 4710 } 4711 4712 static int rtl8169_poll(struct napi_struct *napi, int budget) 4713 { 4714 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4715 struct net_device *dev = tp->dev; 4716 int work_done; 4717 4718 rtl_tx(dev, tp, budget); 4719 4720 work_done = rtl_rx(dev, tp, budget); 4721 4722 if (work_done < budget && napi_complete_done(napi, work_done)) 4723 rtl_irq_enable(tp); 4724 4725 return work_done; 4726 } 4727 4728 static void r8169_phylink_handler(struct net_device *ndev) 4729 { 4730 struct rtl8169_private *tp = netdev_priv(ndev); 4731 struct device *d = tp_to_dev(tp); 4732 4733 if (netif_carrier_ok(ndev)) { 4734 rtl_link_chg_patch(tp); 4735 pm_request_resume(d); 4736 netif_wake_queue(tp->dev); 4737 } else { 4738 /* In few cases rx is broken after link-down otherwise */ 4739 if (rtl_is_8125(tp)) 4740 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4741 pm_runtime_idle(d); 4742 } 4743 4744 phy_print_status(tp->phydev); 4745 } 4746 4747 static int r8169_phy_connect(struct rtl8169_private *tp) 4748 { 4749 struct phy_device *phydev = tp->phydev; 4750 phy_interface_t phy_mode; 4751 int ret; 4752 4753 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4754 PHY_INTERFACE_MODE_MII; 4755 4756 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4757 phy_mode); 4758 if (ret) 4759 return ret; 4760 4761 if (!tp->supports_gmii) 4762 phy_set_max_speed(phydev, SPEED_100); 4763 4764 phy_attached_info(phydev); 4765 4766 return 0; 4767 } 4768 4769 static void rtl8169_down(struct rtl8169_private *tp) 4770 { 4771 /* Clear all task flags */ 4772 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4773 4774 phy_stop(tp->phydev); 4775 4776 rtl8169_update_counters(tp); 4777 4778 pci_clear_master(tp->pci_dev); 4779 rtl_pci_commit(tp); 4780 4781 rtl8169_cleanup(tp); 4782 rtl_disable_exit_l1(tp); 4783 rtl_prepare_power_down(tp); 4784 4785 if (tp->dash_type != RTL_DASH_NONE) 4786 rtl8168_driver_stop(tp); 4787 } 4788 4789 static void rtl8169_up(struct rtl8169_private *tp) 4790 { 4791 if (tp->dash_type != RTL_DASH_NONE) 4792 rtl8168_driver_start(tp); 4793 4794 pci_set_master(tp->pci_dev); 4795 phy_init_hw(tp->phydev); 4796 phy_resume(tp->phydev); 4797 rtl8169_init_phy(tp); 4798 napi_enable(&tp->napi); 4799 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4800 rtl_reset_work(tp); 4801 4802 phy_start(tp->phydev); 4803 } 4804 4805 static int rtl8169_close(struct net_device *dev) 4806 { 4807 struct rtl8169_private *tp = netdev_priv(dev); 4808 struct pci_dev *pdev = tp->pci_dev; 4809 4810 pm_runtime_get_sync(&pdev->dev); 4811 4812 netif_stop_queue(dev); 4813 rtl8169_down(tp); 4814 rtl8169_rx_clear(tp); 4815 4816 cancel_work(&tp->wk.work); 4817 4818 free_irq(tp->irq, tp); 4819 4820 phy_disconnect(tp->phydev); 4821 4822 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4823 tp->RxPhyAddr); 4824 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4825 tp->TxPhyAddr); 4826 tp->TxDescArray = NULL; 4827 tp->RxDescArray = NULL; 4828 4829 pm_runtime_put_sync(&pdev->dev); 4830 4831 return 0; 4832 } 4833 4834 #ifdef CONFIG_NET_POLL_CONTROLLER 4835 static void rtl8169_netpoll(struct net_device *dev) 4836 { 4837 struct rtl8169_private *tp = netdev_priv(dev); 4838 4839 rtl8169_interrupt(tp->irq, tp); 4840 } 4841 #endif 4842 4843 static int rtl_open(struct net_device *dev) 4844 { 4845 struct rtl8169_private *tp = netdev_priv(dev); 4846 struct pci_dev *pdev = tp->pci_dev; 4847 unsigned long irqflags; 4848 int retval = -ENOMEM; 4849 4850 pm_runtime_get_sync(&pdev->dev); 4851 4852 /* 4853 * Rx and Tx descriptors needs 256 bytes alignment. 4854 * dma_alloc_coherent provides more. 4855 */ 4856 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4857 &tp->TxPhyAddr, GFP_KERNEL); 4858 if (!tp->TxDescArray) 4859 goto out; 4860 4861 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4862 &tp->RxPhyAddr, GFP_KERNEL); 4863 if (!tp->RxDescArray) 4864 goto err_free_tx_0; 4865 4866 retval = rtl8169_init_ring(tp); 4867 if (retval < 0) 4868 goto err_free_rx_1; 4869 4870 rtl_request_firmware(tp); 4871 4872 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4873 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4874 if (retval < 0) 4875 goto err_release_fw_2; 4876 4877 retval = r8169_phy_connect(tp); 4878 if (retval) 4879 goto err_free_irq; 4880 4881 rtl8169_up(tp); 4882 rtl8169_init_counter_offsets(tp); 4883 netif_start_queue(dev); 4884 out: 4885 pm_runtime_put_sync(&pdev->dev); 4886 4887 return retval; 4888 4889 err_free_irq: 4890 free_irq(tp->irq, tp); 4891 err_release_fw_2: 4892 rtl_release_firmware(tp); 4893 rtl8169_rx_clear(tp); 4894 err_free_rx_1: 4895 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4896 tp->RxPhyAddr); 4897 tp->RxDescArray = NULL; 4898 err_free_tx_0: 4899 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4900 tp->TxPhyAddr); 4901 tp->TxDescArray = NULL; 4902 goto out; 4903 } 4904 4905 static void 4906 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4907 { 4908 struct rtl8169_private *tp = netdev_priv(dev); 4909 struct pci_dev *pdev = tp->pci_dev; 4910 struct rtl8169_counters *counters = tp->counters; 4911 4912 pm_runtime_get_noresume(&pdev->dev); 4913 4914 netdev_stats_to_stats64(stats, &dev->stats); 4915 dev_fetch_sw_netstats(stats, dev->tstats); 4916 4917 /* 4918 * Fetch additional counter values missing in stats collected by driver 4919 * from tally counters. 4920 */ 4921 if (pm_runtime_active(&pdev->dev)) 4922 rtl8169_update_counters(tp); 4923 4924 /* 4925 * Subtract values fetched during initalization. 4926 * See rtl8169_init_counter_offsets for a description why we do that. 4927 */ 4928 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4929 le64_to_cpu(tp->tc_offset.tx_errors); 4930 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4931 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4932 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4933 le16_to_cpu(tp->tc_offset.tx_aborted); 4934 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4935 le16_to_cpu(tp->tc_offset.rx_missed); 4936 4937 pm_runtime_put_noidle(&pdev->dev); 4938 } 4939 4940 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4941 { 4942 netif_device_detach(tp->dev); 4943 4944 if (netif_running(tp->dev)) 4945 rtl8169_down(tp); 4946 } 4947 4948 static int rtl8169_runtime_resume(struct device *dev) 4949 { 4950 struct rtl8169_private *tp = dev_get_drvdata(dev); 4951 4952 rtl_rar_set(tp, tp->dev->dev_addr); 4953 __rtl8169_set_wol(tp, tp->saved_wolopts); 4954 4955 if (tp->TxDescArray) 4956 rtl8169_up(tp); 4957 4958 netif_device_attach(tp->dev); 4959 4960 return 0; 4961 } 4962 4963 static int rtl8169_suspend(struct device *device) 4964 { 4965 struct rtl8169_private *tp = dev_get_drvdata(device); 4966 4967 rtnl_lock(); 4968 rtl8169_net_suspend(tp); 4969 if (!device_may_wakeup(tp_to_dev(tp))) 4970 clk_disable_unprepare(tp->clk); 4971 rtnl_unlock(); 4972 4973 return 0; 4974 } 4975 4976 static int rtl8169_resume(struct device *device) 4977 { 4978 struct rtl8169_private *tp = dev_get_drvdata(device); 4979 4980 if (!device_may_wakeup(tp_to_dev(tp))) 4981 clk_prepare_enable(tp->clk); 4982 4983 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4984 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4985 rtl_init_rxcfg(tp); 4986 4987 return rtl8169_runtime_resume(device); 4988 } 4989 4990 static int rtl8169_runtime_suspend(struct device *device) 4991 { 4992 struct rtl8169_private *tp = dev_get_drvdata(device); 4993 4994 if (!tp->TxDescArray) { 4995 netif_device_detach(tp->dev); 4996 return 0; 4997 } 4998 4999 rtnl_lock(); 5000 __rtl8169_set_wol(tp, WAKE_PHY); 5001 rtl8169_net_suspend(tp); 5002 rtnl_unlock(); 5003 5004 return 0; 5005 } 5006 5007 static int rtl8169_runtime_idle(struct device *device) 5008 { 5009 struct rtl8169_private *tp = dev_get_drvdata(device); 5010 5011 if (tp->dash_enabled) 5012 return -EBUSY; 5013 5014 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5015 pm_schedule_suspend(device, 10000); 5016 5017 return -EBUSY; 5018 } 5019 5020 static const struct dev_pm_ops rtl8169_pm_ops = { 5021 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5022 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5023 rtl8169_runtime_idle) 5024 }; 5025 5026 static void rtl_shutdown(struct pci_dev *pdev) 5027 { 5028 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5029 5030 rtnl_lock(); 5031 rtl8169_net_suspend(tp); 5032 rtnl_unlock(); 5033 5034 /* Restore original MAC address */ 5035 rtl_rar_set(tp, tp->dev->perm_addr); 5036 5037 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5038 pci_wake_from_d3(pdev, tp->saved_wolopts); 5039 pci_set_power_state(pdev, PCI_D3hot); 5040 } 5041 } 5042 5043 static void rtl_remove_one(struct pci_dev *pdev) 5044 { 5045 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5046 5047 if (pci_dev_run_wake(pdev)) 5048 pm_runtime_get_noresume(&pdev->dev); 5049 5050 cancel_work_sync(&tp->wk.work); 5051 5052 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5053 r8169_remove_leds(tp->leds); 5054 5055 unregister_netdev(tp->dev); 5056 5057 if (tp->dash_type != RTL_DASH_NONE) 5058 rtl8168_driver_stop(tp); 5059 5060 rtl_release_firmware(tp); 5061 5062 /* restore original MAC address */ 5063 rtl_rar_set(tp, tp->dev->perm_addr); 5064 } 5065 5066 static const struct net_device_ops rtl_netdev_ops = { 5067 .ndo_open = rtl_open, 5068 .ndo_stop = rtl8169_close, 5069 .ndo_get_stats64 = rtl8169_get_stats64, 5070 .ndo_start_xmit = rtl8169_start_xmit, 5071 .ndo_features_check = rtl8169_features_check, 5072 .ndo_tx_timeout = rtl8169_tx_timeout, 5073 .ndo_validate_addr = eth_validate_addr, 5074 .ndo_change_mtu = rtl8169_change_mtu, 5075 .ndo_fix_features = rtl8169_fix_features, 5076 .ndo_set_features = rtl8169_set_features, 5077 .ndo_set_mac_address = rtl_set_mac_address, 5078 .ndo_eth_ioctl = phy_do_ioctl_running, 5079 .ndo_set_rx_mode = rtl_set_rx_mode, 5080 #ifdef CONFIG_NET_POLL_CONTROLLER 5081 .ndo_poll_controller = rtl8169_netpoll, 5082 #endif 5083 5084 }; 5085 5086 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5087 { 5088 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5089 5090 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5091 tp->irq_mask |= SYSErr | RxFIFOOver; 5092 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5093 /* special workaround needed */ 5094 tp->irq_mask |= RxFIFOOver; 5095 } 5096 5097 static int rtl_alloc_irq(struct rtl8169_private *tp) 5098 { 5099 unsigned int flags; 5100 5101 switch (tp->mac_version) { 5102 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5103 rtl_unlock_config_regs(tp); 5104 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5105 rtl_lock_config_regs(tp); 5106 fallthrough; 5107 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5108 flags = PCI_IRQ_INTX; 5109 break; 5110 default: 5111 flags = PCI_IRQ_ALL_TYPES; 5112 break; 5113 } 5114 5115 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5116 } 5117 5118 static void rtl_read_mac_address(struct rtl8169_private *tp, 5119 u8 mac_addr[ETH_ALEN]) 5120 { 5121 /* Get MAC address */ 5122 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5123 u32 value; 5124 5125 value = rtl_eri_read(tp, 0xe0); 5126 put_unaligned_le32(value, mac_addr); 5127 value = rtl_eri_read(tp, 0xe4); 5128 put_unaligned_le16(value, mac_addr + 4); 5129 } else if (rtl_is_8125(tp)) { 5130 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5131 } 5132 } 5133 5134 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5135 { 5136 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5137 } 5138 5139 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5140 { 5141 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5142 } 5143 5144 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5145 { 5146 struct rtl8169_private *tp = mii_bus->priv; 5147 5148 if (phyaddr > 0) 5149 return -ENODEV; 5150 5151 return rtl_readphy(tp, phyreg); 5152 } 5153 5154 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5155 int phyreg, u16 val) 5156 { 5157 struct rtl8169_private *tp = mii_bus->priv; 5158 5159 if (phyaddr > 0) 5160 return -ENODEV; 5161 5162 rtl_writephy(tp, phyreg, val); 5163 5164 return 0; 5165 } 5166 5167 static int r8169_mdio_register(struct rtl8169_private *tp) 5168 { 5169 struct pci_dev *pdev = tp->pci_dev; 5170 struct mii_bus *new_bus; 5171 int ret; 5172 5173 /* On some boards with this chip version the BIOS is buggy and misses 5174 * to reset the PHY page selector. This results in the PHY ID read 5175 * accessing registers on a different page, returning a more or 5176 * less random value. Fix this by resetting the page selector first. 5177 */ 5178 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5179 tp->mac_version == RTL_GIGA_MAC_VER_26) 5180 r8169_mdio_write(tp, 0x1f, 0); 5181 5182 new_bus = devm_mdiobus_alloc(&pdev->dev); 5183 if (!new_bus) 5184 return -ENOMEM; 5185 5186 new_bus->name = "r8169"; 5187 new_bus->priv = tp; 5188 new_bus->parent = &pdev->dev; 5189 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5190 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5191 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5192 5193 new_bus->read = r8169_mdio_read_reg; 5194 new_bus->write = r8169_mdio_write_reg; 5195 5196 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5197 if (ret) 5198 return ret; 5199 5200 tp->phydev = mdiobus_get_phy(new_bus, 0); 5201 if (!tp->phydev) { 5202 return -ENODEV; 5203 } else if (!tp->phydev->drv) { 5204 /* Most chip versions fail with the genphy driver. 5205 * Therefore ensure that the dedicated PHY driver is loaded. 5206 */ 5207 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5208 tp->phydev->phy_id); 5209 return -EUNATCH; 5210 } 5211 5212 tp->phydev->mac_managed_pm = true; 5213 if (rtl_supports_eee(tp)) 5214 phy_support_eee(tp->phydev); 5215 phy_support_asym_pause(tp->phydev); 5216 5217 /* PHY will be woken up in rtl_open() */ 5218 phy_suspend(tp->phydev); 5219 5220 return 0; 5221 } 5222 5223 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5224 { 5225 rtl_enable_rxdvgate(tp); 5226 5227 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5228 msleep(1); 5229 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5230 5231 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5232 r8168g_wait_ll_share_fifo_ready(tp); 5233 5234 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5235 r8168g_wait_ll_share_fifo_ready(tp); 5236 } 5237 5238 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5239 { 5240 rtl_enable_rxdvgate(tp); 5241 5242 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5243 msleep(1); 5244 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5245 5246 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5247 r8168g_wait_ll_share_fifo_ready(tp); 5248 5249 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5250 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5251 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5252 r8168g_wait_ll_share_fifo_ready(tp); 5253 } 5254 5255 static void rtl_hw_initialize(struct rtl8169_private *tp) 5256 { 5257 switch (tp->mac_version) { 5258 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5259 rtl8168ep_stop_cmac(tp); 5260 fallthrough; 5261 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5262 rtl_hw_init_8168g(tp); 5263 break; 5264 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 5265 rtl_hw_init_8125(tp); 5266 break; 5267 default: 5268 break; 5269 } 5270 } 5271 5272 static int rtl_jumbo_max(struct rtl8169_private *tp) 5273 { 5274 /* Non-GBit versions don't support jumbo frames */ 5275 if (!tp->supports_gmii) 5276 return 0; 5277 5278 switch (tp->mac_version) { 5279 /* RTL8169 */ 5280 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5281 return JUMBO_7K; 5282 /* RTL8168b */ 5283 case RTL_GIGA_MAC_VER_11: 5284 case RTL_GIGA_MAC_VER_17: 5285 return JUMBO_4K; 5286 /* RTL8168c */ 5287 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5288 return JUMBO_6K; 5289 default: 5290 return JUMBO_9K; 5291 } 5292 } 5293 5294 static void rtl_init_mac_address(struct rtl8169_private *tp) 5295 { 5296 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5297 struct net_device *dev = tp->dev; 5298 int rc; 5299 5300 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5301 if (!rc) 5302 goto done; 5303 5304 rtl_read_mac_address(tp, mac_addr); 5305 if (is_valid_ether_addr(mac_addr)) 5306 goto done; 5307 5308 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5309 if (is_valid_ether_addr(mac_addr)) 5310 goto done; 5311 5312 eth_random_addr(mac_addr); 5313 dev->addr_assign_type = NET_ADDR_RANDOM; 5314 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5315 done: 5316 eth_hw_addr_set(dev, mac_addr); 5317 rtl_rar_set(tp, mac_addr); 5318 } 5319 5320 /* register is set if system vendor successfully tested ASPM 1.2 */ 5321 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5322 { 5323 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5324 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5325 return true; 5326 5327 return false; 5328 } 5329 5330 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5331 { 5332 struct rtl8169_private *tp; 5333 int jumbo_max, region, rc; 5334 enum mac_version chipset; 5335 struct net_device *dev; 5336 u32 txconfig; 5337 u16 xid; 5338 5339 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5340 if (!dev) 5341 return -ENOMEM; 5342 5343 SET_NETDEV_DEV(dev, &pdev->dev); 5344 dev->netdev_ops = &rtl_netdev_ops; 5345 tp = netdev_priv(dev); 5346 tp->dev = dev; 5347 tp->pci_dev = pdev; 5348 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5349 tp->ocp_base = OCP_STD_PHY_BASE; 5350 5351 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5352 raw_spin_lock_init(&tp->config25_lock); 5353 raw_spin_lock_init(&tp->mac_ocp_lock); 5354 mutex_init(&tp->led_lock); 5355 5356 /* Get the *optional* external "ether_clk" used on some boards */ 5357 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5358 if (IS_ERR(tp->clk)) 5359 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5360 5361 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5362 rc = pcim_enable_device(pdev); 5363 if (rc < 0) 5364 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5365 5366 if (pcim_set_mwi(pdev) < 0) 5367 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5368 5369 /* use first MMIO region */ 5370 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5371 if (region < 0) 5372 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5373 5374 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5375 if (rc < 0) 5376 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5377 5378 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5379 5380 txconfig = RTL_R32(tp, TxConfig); 5381 if (txconfig == ~0U) 5382 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5383 5384 xid = (txconfig >> 20) & 0xfcf; 5385 5386 /* Identify chip attached to board */ 5387 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5388 if (chipset == RTL_GIGA_MAC_NONE) 5389 return dev_err_probe(&pdev->dev, -ENODEV, 5390 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5391 xid); 5392 tp->mac_version = chipset; 5393 5394 /* Disable ASPM L1 as that cause random device stop working 5395 * problems as well as full system hangs for some PCIe devices users. 5396 */ 5397 if (rtl_aspm_is_safe(tp)) 5398 rc = 0; 5399 else 5400 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5401 tp->aspm_manageable = !rc; 5402 5403 tp->dash_type = rtl_get_dash_type(tp); 5404 tp->dash_enabled = rtl_dash_is_enabled(tp); 5405 5406 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5407 5408 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5409 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5410 dev->features |= NETIF_F_HIGHDMA; 5411 5412 rtl_init_rxcfg(tp); 5413 5414 rtl8169_irq_mask_and_ack(tp); 5415 5416 rtl_hw_initialize(tp); 5417 5418 rtl_hw_reset(tp); 5419 5420 rc = rtl_alloc_irq(tp); 5421 if (rc < 0) 5422 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5423 5424 tp->irq = pci_irq_vector(pdev, 0); 5425 5426 INIT_WORK(&tp->wk.work, rtl_task); 5427 5428 rtl_init_mac_address(tp); 5429 5430 dev->ethtool_ops = &rtl8169_ethtool_ops; 5431 5432 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5433 5434 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5435 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5436 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5437 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5438 5439 /* 5440 * Pretend we are using VLANs; This bypasses a nasty bug where 5441 * Interrupts stop flowing on high load on 8110SCd controllers. 5442 */ 5443 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5444 /* Disallow toggling */ 5445 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5446 5447 if (rtl_chip_supports_csum_v2(tp)) 5448 dev->hw_features |= NETIF_F_IPV6_CSUM; 5449 5450 dev->features |= dev->hw_features; 5451 5452 /* There has been a number of reports that using SG/TSO results in 5453 * tx timeouts. However for a lot of people SG/TSO works fine. 5454 * Therefore disable both features by default, but allow users to 5455 * enable them. Use at own risk! 5456 */ 5457 if (rtl_chip_supports_csum_v2(tp)) { 5458 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5459 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5460 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5461 } else { 5462 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5463 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5464 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5465 } 5466 5467 dev->hw_features |= NETIF_F_RXALL; 5468 dev->hw_features |= NETIF_F_RXFCS; 5469 5470 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5471 5472 netdev_sw_irq_coalesce_default_on(dev); 5473 5474 /* configure chip for default features */ 5475 rtl8169_set_features(dev, dev->features); 5476 5477 if (!tp->dash_enabled) { 5478 rtl_set_d3_pll_down(tp, true); 5479 } else { 5480 rtl_set_d3_pll_down(tp, false); 5481 dev->ethtool->wol_enabled = 1; 5482 } 5483 5484 jumbo_max = rtl_jumbo_max(tp); 5485 if (jumbo_max) 5486 dev->max_mtu = jumbo_max; 5487 5488 rtl_set_irq_mask(tp); 5489 5490 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5491 5492 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5493 &tp->counters_phys_addr, 5494 GFP_KERNEL); 5495 if (!tp->counters) 5496 return -ENOMEM; 5497 5498 pci_set_drvdata(pdev, tp); 5499 5500 rc = r8169_mdio_register(tp); 5501 if (rc) 5502 return rc; 5503 5504 rc = register_netdev(dev); 5505 if (rc) 5506 return rc; 5507 5508 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5509 if (rtl_is_8125(tp)) 5510 tp->leds = rtl8125_init_leds(dev); 5511 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5512 tp->leds = rtl8168_init_leds(dev); 5513 } 5514 5515 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5516 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5517 5518 if (jumbo_max) 5519 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5520 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5521 "ok" : "ko"); 5522 5523 if (tp->dash_type != RTL_DASH_NONE) { 5524 netdev_info(dev, "DASH %s\n", 5525 tp->dash_enabled ? "enabled" : "disabled"); 5526 rtl8168_driver_start(tp); 5527 } 5528 5529 if (pci_dev_run_wake(pdev)) 5530 pm_runtime_put_sync(&pdev->dev); 5531 5532 return 0; 5533 } 5534 5535 static struct pci_driver rtl8169_pci_driver = { 5536 .name = KBUILD_MODNAME, 5537 .id_table = rtl8169_pci_tbl, 5538 .probe = rtl_init_one, 5539 .remove = rtl_remove_one, 5540 .shutdown = rtl_shutdown, 5541 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5542 }; 5543 5544 module_pci_driver(rtl8169_pci_driver); 5545