1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 52 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 59 60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 62 #define MC_FILTER_LIMIT 32 63 64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 66 67 #define R8169_REGS_SIZE 256 68 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 69 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 70 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 73 74 #define OCP_STD_PHY_BASE 0xa400 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 91 static const struct { 92 const char *name; 93 const char *fw_name; 94 } rtl_chip_infos[] = { 95 /* PCI devices. */ 96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 101 /* PCI-E devices. */ 102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 109 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 110 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 111 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 112 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 118 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 119 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 120 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 121 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 122 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 123 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 124 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 125 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 126 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 127 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 128 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 129 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 130 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 131 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 132 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 133 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 134 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 135 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 136 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 137 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 138 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 139 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 140 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 141 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 142 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 143 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 144 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 145 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 146 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 147 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, 148 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 149 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 150 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 151 }; 152 153 static const struct pci_device_id rtl8169_pci_tbl[] = { 154 { PCI_VDEVICE(REALTEK, 0x2502) }, 155 { PCI_VDEVICE(REALTEK, 0x2600) }, 156 { PCI_VDEVICE(REALTEK, 0x8129) }, 157 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 158 { PCI_VDEVICE(REALTEK, 0x8161) }, 159 { PCI_VDEVICE(REALTEK, 0x8162) }, 160 { PCI_VDEVICE(REALTEK, 0x8167) }, 161 { PCI_VDEVICE(REALTEK, 0x8168) }, 162 { PCI_VDEVICE(NCUBE, 0x8168) }, 163 { PCI_VDEVICE(REALTEK, 0x8169) }, 164 { PCI_VENDOR_ID_DLINK, 0x4300, 165 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 166 { PCI_VDEVICE(DLINK, 0x4300) }, 167 { PCI_VDEVICE(DLINK, 0x4302) }, 168 { PCI_VDEVICE(AT, 0xc107) }, 169 { PCI_VDEVICE(USR, 0x0116) }, 170 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 171 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 172 { PCI_VDEVICE(REALTEK, 0x8125) }, 173 { PCI_VDEVICE(REALTEK, 0x3000) }, 174 {} 175 }; 176 177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 178 179 enum rtl_registers { 180 MAC0 = 0, /* Ethernet hardware address. */ 181 MAC4 = 4, 182 MAR0 = 8, /* Multicast filter. */ 183 CounterAddrLow = 0x10, 184 CounterAddrHigh = 0x14, 185 TxDescStartAddrLow = 0x20, 186 TxDescStartAddrHigh = 0x24, 187 TxHDescStartAddrLow = 0x28, 188 TxHDescStartAddrHigh = 0x2c, 189 FLASH = 0x30, 190 ERSR = 0x36, 191 ChipCmd = 0x37, 192 TxPoll = 0x38, 193 IntrMask = 0x3c, 194 IntrStatus = 0x3e, 195 196 TxConfig = 0x40, 197 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 198 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 199 200 RxConfig = 0x44, 201 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 202 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 203 #define RXCFG_FIFO_SHIFT 13 204 /* No threshold before first PCI xfer */ 205 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 206 #define RX_EARLY_OFF (1 << 11) 207 #define RXCFG_DMA_SHIFT 8 208 /* Unlimited maximum PCI burst. */ 209 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 210 211 Cfg9346 = 0x50, 212 Config0 = 0x51, 213 Config1 = 0x52, 214 Config2 = 0x53, 215 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 216 217 Config3 = 0x54, 218 Config4 = 0x55, 219 Config5 = 0x56, 220 PHYAR = 0x60, 221 PHYstatus = 0x6c, 222 RxMaxSize = 0xda, 223 CPlusCmd = 0xe0, 224 IntrMitigate = 0xe2, 225 226 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 227 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 228 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 229 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 230 231 #define RTL_COALESCE_T_MAX 0x0fU 232 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 233 234 RxDescAddrLow = 0xe4, 235 RxDescAddrHigh = 0xe8, 236 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 237 238 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 239 240 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 241 242 #define TxPacketMax (8064 >> 7) 243 #define EarlySize 0x27 244 245 FuncEvent = 0xf0, 246 FuncEventMask = 0xf4, 247 FuncPresetState = 0xf8, 248 IBCR0 = 0xf8, 249 IBCR2 = 0xf9, 250 IBIMR0 = 0xfa, 251 IBISR0 = 0xfb, 252 FuncForceEvent = 0xfc, 253 }; 254 255 enum rtl8168_8101_registers { 256 CSIDR = 0x64, 257 CSIAR = 0x68, 258 #define CSIAR_FLAG 0x80000000 259 #define CSIAR_WRITE_CMD 0x80000000 260 #define CSIAR_BYTE_ENABLE 0x0000f000 261 #define CSIAR_ADDR_MASK 0x00000fff 262 PMCH = 0x6f, 263 #define D3COLD_NO_PLL_DOWN BIT(7) 264 #define D3HOT_NO_PLL_DOWN BIT(6) 265 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 266 EPHYAR = 0x80, 267 #define EPHYAR_FLAG 0x80000000 268 #define EPHYAR_WRITE_CMD 0x80000000 269 #define EPHYAR_REG_MASK 0x1f 270 #define EPHYAR_REG_SHIFT 16 271 #define EPHYAR_DATA_MASK 0xffff 272 DLLPR = 0xd0, 273 #define PFM_EN (1 << 6) 274 #define TX_10M_PS_EN (1 << 7) 275 DBG_REG = 0xd1, 276 #define FIX_NAK_1 (1 << 4) 277 #define FIX_NAK_2 (1 << 3) 278 TWSI = 0xd2, 279 MCU = 0xd3, 280 #define NOW_IS_OOB (1 << 7) 281 #define TX_EMPTY (1 << 5) 282 #define RX_EMPTY (1 << 4) 283 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 284 #define EN_NDP (1 << 3) 285 #define EN_OOB_RESET (1 << 2) 286 #define LINK_LIST_RDY (1 << 1) 287 EFUSEAR = 0xdc, 288 #define EFUSEAR_FLAG 0x80000000 289 #define EFUSEAR_WRITE_CMD 0x80000000 290 #define EFUSEAR_READ_CMD 0x00000000 291 #define EFUSEAR_REG_MASK 0x03ff 292 #define EFUSEAR_REG_SHIFT 8 293 #define EFUSEAR_DATA_MASK 0xff 294 MISC_1 = 0xf2, 295 #define PFM_D3COLD_EN (1 << 6) 296 }; 297 298 enum rtl8168_registers { 299 LED_FREQ = 0x1a, 300 EEE_LED = 0x1b, 301 ERIDR = 0x70, 302 ERIAR = 0x74, 303 #define ERIAR_FLAG 0x80000000 304 #define ERIAR_WRITE_CMD 0x80000000 305 #define ERIAR_READ_CMD 0x00000000 306 #define ERIAR_ADDR_BYTE_ALIGN 4 307 #define ERIAR_TYPE_SHIFT 16 308 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 310 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 312 #define ERIAR_MASK_SHIFT 12 313 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 315 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 317 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 318 EPHY_RXER_NUM = 0x7c, 319 OCPDR = 0xb0, /* OCP GPHY access */ 320 #define OCPDR_WRITE_CMD 0x80000000 321 #define OCPDR_READ_CMD 0x00000000 322 #define OCPDR_REG_MASK 0x7f 323 #define OCPDR_GPHY_REG_SHIFT 16 324 #define OCPDR_DATA_MASK 0xffff 325 OCPAR = 0xb4, 326 #define OCPAR_FLAG 0x80000000 327 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 328 #define OCPAR_GPHY_READ_CMD 0x0000f060 329 GPHY_OCP = 0xb8, 330 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 331 MISC = 0xf0, /* 8168e only. */ 332 #define TXPLA_RST (1 << 29) 333 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 334 #define PWM_EN (1 << 22) 335 #define RXDV_GATED_EN (1 << 19) 336 #define EARLY_TALLY_EN (1 << 16) 337 }; 338 339 enum rtl8125_registers { 340 IntrMask_8125 = 0x38, 341 IntrStatus_8125 = 0x3c, 342 TxPoll_8125 = 0x90, 343 MAC0_BKP = 0x19e0, 344 EEE_TXIDLE_TIMER_8125 = 0x6048, 345 }; 346 347 #define RX_VLAN_INNER_8125 BIT(22) 348 #define RX_VLAN_OUTER_8125 BIT(23) 349 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 350 351 #define RX_FETCH_DFLT_8125 (8 << 27) 352 353 enum rtl_register_content { 354 /* InterruptStatusBits */ 355 SYSErr = 0x8000, 356 PCSTimeout = 0x4000, 357 SWInt = 0x0100, 358 TxDescUnavail = 0x0080, 359 RxFIFOOver = 0x0040, 360 LinkChg = 0x0020, 361 RxOverflow = 0x0010, 362 TxErr = 0x0008, 363 TxOK = 0x0004, 364 RxErr = 0x0002, 365 RxOK = 0x0001, 366 367 /* RxStatusDesc */ 368 RxRWT = (1 << 22), 369 RxRES = (1 << 21), 370 RxRUNT = (1 << 20), 371 RxCRC = (1 << 19), 372 373 /* ChipCmdBits */ 374 StopReq = 0x80, 375 CmdReset = 0x10, 376 CmdRxEnb = 0x08, 377 CmdTxEnb = 0x04, 378 RxBufEmpty = 0x01, 379 380 /* TXPoll register p.5 */ 381 HPQ = 0x80, /* Poll cmd on the high prio queue */ 382 NPQ = 0x40, /* Poll cmd on the low prio queue */ 383 FSWInt = 0x01, /* Forced software interrupt */ 384 385 /* Cfg9346Bits */ 386 Cfg9346_Lock = 0x00, 387 Cfg9346_Unlock = 0xc0, 388 389 /* rx_mode_bits */ 390 AcceptErr = 0x20, 391 AcceptRunt = 0x10, 392 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 393 AcceptBroadcast = 0x08, 394 AcceptMulticast = 0x04, 395 AcceptMyPhys = 0x02, 396 AcceptAllPhys = 0x01, 397 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 398 #define RX_CONFIG_ACCEPT_MASK 0x3f 399 400 /* TxConfigBits */ 401 TxInterFrameGapShift = 24, 402 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 403 404 /* Config1 register p.24 */ 405 LEDS1 = (1 << 7), 406 LEDS0 = (1 << 6), 407 Speed_down = (1 << 4), 408 MEMMAP = (1 << 3), 409 IOMAP = (1 << 2), 410 VPD = (1 << 1), 411 PMEnable = (1 << 0), /* Power Management Enable */ 412 413 /* Config2 register p. 25 */ 414 ClkReqEn = (1 << 7), /* Clock Request Enable */ 415 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 416 PCI_Clock_66MHz = 0x01, 417 PCI_Clock_33MHz = 0x00, 418 419 /* Config3 register p.25 */ 420 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 421 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 422 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 423 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 424 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 425 426 /* Config4 register */ 427 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 428 429 /* Config5 register p.27 */ 430 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 431 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 432 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 433 Spi_en = (1 << 3), 434 LanWake = (1 << 1), /* LanWake enable/disable */ 435 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 436 ASPM_en = (1 << 0), /* ASPM enable */ 437 438 /* CPlusCmd p.31 */ 439 EnableBist = (1 << 15), // 8168 8101 440 Mac_dbgo_oe = (1 << 14), // 8168 8101 441 EnAnaPLL = (1 << 14), // 8169 442 Normal_mode = (1 << 13), // unused 443 Force_half_dup = (1 << 12), // 8168 8101 444 Force_rxflow_en = (1 << 11), // 8168 8101 445 Force_txflow_en = (1 << 10), // 8168 8101 446 Cxpl_dbg_sel = (1 << 9), // 8168 8101 447 ASF = (1 << 8), // 8168 8101 448 PktCntrDisable = (1 << 7), // 8168 8101 449 Mac_dbgo_sel = 0x001c, // 8168 450 RxVlan = (1 << 6), 451 RxChkSum = (1 << 5), 452 PCIDAC = (1 << 4), 453 PCIMulRW = (1 << 3), 454 #define INTT_MASK GENMASK(1, 0) 455 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 456 457 /* rtl8169_PHYstatus */ 458 TBI_Enable = 0x80, 459 TxFlowCtrl = 0x40, 460 RxFlowCtrl = 0x20, 461 _1000bpsF = 0x10, 462 _100bps = 0x08, 463 _10bps = 0x04, 464 LinkStatus = 0x02, 465 FullDup = 0x01, 466 467 /* ResetCounterCommand */ 468 CounterReset = 0x1, 469 470 /* DumpCounterCommand */ 471 CounterDump = 0x8, 472 473 /* magic enable v2 */ 474 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 475 }; 476 477 enum rtl_desc_bit { 478 /* First doubleword. */ 479 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 480 RingEnd = (1 << 30), /* End of descriptor ring */ 481 FirstFrag = (1 << 29), /* First segment of a packet */ 482 LastFrag = (1 << 28), /* Final segment of a packet */ 483 }; 484 485 /* Generic case. */ 486 enum rtl_tx_desc_bit { 487 /* First doubleword. */ 488 TD_LSO = (1 << 27), /* Large Send Offload */ 489 #define TD_MSS_MAX 0x07ffu /* MSS value */ 490 491 /* Second doubleword. */ 492 TxVlanTag = (1 << 17), /* Add VLAN tag */ 493 }; 494 495 /* 8169, 8168b and 810x except 8102e. */ 496 enum rtl_tx_desc_bit_0 { 497 /* First doubleword. */ 498 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 499 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 500 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 501 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 502 }; 503 504 /* 8102e, 8168c and beyond. */ 505 enum rtl_tx_desc_bit_1 { 506 /* First doubleword. */ 507 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 508 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 509 #define GTTCPHO_SHIFT 18 510 #define GTTCPHO_MAX 0x7f 511 512 /* Second doubleword. */ 513 #define TCPHO_SHIFT 18 514 #define TCPHO_MAX 0x3ff 515 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 516 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 517 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 518 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 519 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 520 }; 521 522 enum rtl_rx_desc_bit { 523 /* Rx private */ 524 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 525 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 526 527 #define RxProtoUDP (PID1) 528 #define RxProtoTCP (PID0) 529 #define RxProtoIP (PID1 | PID0) 530 #define RxProtoMask RxProtoIP 531 532 IPFail = (1 << 16), /* IP checksum failed */ 533 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 534 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 535 536 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 537 538 RxVlanTag = (1 << 16), /* VLAN tag available */ 539 }; 540 541 #define RTL_GSO_MAX_SIZE_V1 32000 542 #define RTL_GSO_MAX_SEGS_V1 24 543 #define RTL_GSO_MAX_SIZE_V2 64000 544 #define RTL_GSO_MAX_SEGS_V2 64 545 546 struct TxDesc { 547 __le32 opts1; 548 __le32 opts2; 549 __le64 addr; 550 }; 551 552 struct RxDesc { 553 __le32 opts1; 554 __le32 opts2; 555 __le64 addr; 556 }; 557 558 struct ring_info { 559 struct sk_buff *skb; 560 u32 len; 561 }; 562 563 struct rtl8169_counters { 564 __le64 tx_packets; 565 __le64 rx_packets; 566 __le64 tx_errors; 567 __le32 rx_errors; 568 __le16 rx_missed; 569 __le16 align_errors; 570 __le32 tx_one_collision; 571 __le32 tx_multi_collision; 572 __le64 rx_unicast; 573 __le64 rx_broadcast; 574 __le32 rx_multicast; 575 __le16 tx_aborted; 576 __le16 tx_underun; 577 }; 578 579 struct rtl8169_tc_offsets { 580 bool inited; 581 __le64 tx_errors; 582 __le32 tx_multi_collision; 583 __le16 tx_aborted; 584 __le16 rx_missed; 585 }; 586 587 enum rtl_flag { 588 RTL_FLAG_TASK_ENABLED = 0, 589 RTL_FLAG_TASK_RESET_PENDING, 590 RTL_FLAG_MAX 591 }; 592 593 enum rtl_dash_type { 594 RTL_DASH_NONE, 595 RTL_DASH_DP, 596 RTL_DASH_EP, 597 }; 598 599 struct rtl8169_private { 600 void __iomem *mmio_addr; /* memory map physical address */ 601 struct pci_dev *pci_dev; 602 struct net_device *dev; 603 struct phy_device *phydev; 604 struct napi_struct napi; 605 enum mac_version mac_version; 606 enum rtl_dash_type dash_type; 607 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 608 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 609 u32 dirty_tx; 610 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 611 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 612 dma_addr_t TxPhyAddr; 613 dma_addr_t RxPhyAddr; 614 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 615 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 616 u16 cp_cmd; 617 u32 irq_mask; 618 int irq; 619 struct clk *clk; 620 621 struct { 622 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 623 struct work_struct work; 624 } wk; 625 626 unsigned supports_gmii:1; 627 unsigned aspm_manageable:1; 628 dma_addr_t counters_phys_addr; 629 struct rtl8169_counters *counters; 630 struct rtl8169_tc_offsets tc_offset; 631 u32 saved_wolopts; 632 int eee_adv; 633 634 const char *fw_name; 635 struct rtl_fw *rtl_fw; 636 637 u32 ocp_base; 638 }; 639 640 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 641 642 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 643 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 644 MODULE_SOFTDEP("pre: realtek"); 645 MODULE_LICENSE("GPL"); 646 MODULE_FIRMWARE(FIRMWARE_8168D_1); 647 MODULE_FIRMWARE(FIRMWARE_8168D_2); 648 MODULE_FIRMWARE(FIRMWARE_8168E_1); 649 MODULE_FIRMWARE(FIRMWARE_8168E_2); 650 MODULE_FIRMWARE(FIRMWARE_8168E_3); 651 MODULE_FIRMWARE(FIRMWARE_8105E_1); 652 MODULE_FIRMWARE(FIRMWARE_8168F_1); 653 MODULE_FIRMWARE(FIRMWARE_8168F_2); 654 MODULE_FIRMWARE(FIRMWARE_8402_1); 655 MODULE_FIRMWARE(FIRMWARE_8411_1); 656 MODULE_FIRMWARE(FIRMWARE_8411_2); 657 MODULE_FIRMWARE(FIRMWARE_8106E_1); 658 MODULE_FIRMWARE(FIRMWARE_8106E_2); 659 MODULE_FIRMWARE(FIRMWARE_8168G_2); 660 MODULE_FIRMWARE(FIRMWARE_8168G_3); 661 MODULE_FIRMWARE(FIRMWARE_8168H_1); 662 MODULE_FIRMWARE(FIRMWARE_8168H_2); 663 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 664 MODULE_FIRMWARE(FIRMWARE_8107E_1); 665 MODULE_FIRMWARE(FIRMWARE_8107E_2); 666 MODULE_FIRMWARE(FIRMWARE_8125A_3); 667 MODULE_FIRMWARE(FIRMWARE_8125B_2); 668 669 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 670 { 671 return &tp->pci_dev->dev; 672 } 673 674 static void rtl_lock_config_regs(struct rtl8169_private *tp) 675 { 676 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 677 } 678 679 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 680 { 681 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 682 } 683 684 static void rtl_pci_commit(struct rtl8169_private *tp) 685 { 686 /* Read an arbitrary register to commit a preceding PCI write */ 687 RTL_R8(tp, ChipCmd); 688 } 689 690 static bool rtl_is_8125(struct rtl8169_private *tp) 691 { 692 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 693 } 694 695 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 696 { 697 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 698 tp->mac_version != RTL_GIGA_MAC_VER_39 && 699 tp->mac_version <= RTL_GIGA_MAC_VER_53; 700 } 701 702 static bool rtl_supports_eee(struct rtl8169_private *tp) 703 { 704 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 705 tp->mac_version != RTL_GIGA_MAC_VER_37 && 706 tp->mac_version != RTL_GIGA_MAC_VER_39; 707 } 708 709 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 710 { 711 int i; 712 713 for (i = 0; i < ETH_ALEN; i++) 714 mac[i] = RTL_R8(tp, reg + i); 715 } 716 717 struct rtl_cond { 718 bool (*check)(struct rtl8169_private *); 719 const char *msg; 720 }; 721 722 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 723 unsigned long usecs, int n, bool high) 724 { 725 int i; 726 727 for (i = 0; i < n; i++) { 728 if (c->check(tp) == high) 729 return true; 730 fsleep(usecs); 731 } 732 733 if (net_ratelimit()) 734 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 735 c->msg, !high, n, usecs); 736 return false; 737 } 738 739 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 740 const struct rtl_cond *c, 741 unsigned long d, int n) 742 { 743 return rtl_loop_wait(tp, c, d, n, true); 744 } 745 746 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 747 const struct rtl_cond *c, 748 unsigned long d, int n) 749 { 750 return rtl_loop_wait(tp, c, d, n, false); 751 } 752 753 #define DECLARE_RTL_COND(name) \ 754 static bool name ## _check(struct rtl8169_private *); \ 755 \ 756 static const struct rtl_cond name = { \ 757 .check = name ## _check, \ 758 .msg = #name \ 759 }; \ 760 \ 761 static bool name ## _check(struct rtl8169_private *tp) 762 763 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 764 { 765 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 766 if (type == ERIAR_OOB && 767 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 768 tp->mac_version == RTL_GIGA_MAC_VER_53)) 769 *cmd |= 0xf70 << 18; 770 } 771 772 DECLARE_RTL_COND(rtl_eriar_cond) 773 { 774 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 775 } 776 777 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 778 u32 val, int type) 779 { 780 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 781 782 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 783 return; 784 785 RTL_W32(tp, ERIDR, val); 786 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 787 RTL_W32(tp, ERIAR, cmd); 788 789 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 790 } 791 792 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 793 u32 val) 794 { 795 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 796 } 797 798 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 799 { 800 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 801 802 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 803 RTL_W32(tp, ERIAR, cmd); 804 805 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 806 RTL_R32(tp, ERIDR) : ~0; 807 } 808 809 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 810 { 811 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 812 } 813 814 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 815 { 816 u32 val = rtl_eri_read(tp, addr); 817 818 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 819 } 820 821 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 822 { 823 rtl_w0w1_eri(tp, addr, p, 0); 824 } 825 826 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 827 { 828 rtl_w0w1_eri(tp, addr, 0, m); 829 } 830 831 static bool rtl_ocp_reg_failure(u32 reg) 832 { 833 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 834 } 835 836 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 837 { 838 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 839 } 840 841 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 842 { 843 if (rtl_ocp_reg_failure(reg)) 844 return; 845 846 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 847 848 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 849 } 850 851 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 852 { 853 if (rtl_ocp_reg_failure(reg)) 854 return 0; 855 856 RTL_W32(tp, GPHY_OCP, reg << 15); 857 858 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 859 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 860 } 861 862 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 863 { 864 if (rtl_ocp_reg_failure(reg)) 865 return; 866 867 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 868 } 869 870 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 871 { 872 if (rtl_ocp_reg_failure(reg)) 873 return 0; 874 875 RTL_W32(tp, OCPDR, reg << 15); 876 877 return RTL_R32(tp, OCPDR); 878 } 879 880 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 881 u16 set) 882 { 883 u16 data = r8168_mac_ocp_read(tp, reg); 884 885 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 886 } 887 888 /* Work around a hw issue with RTL8168g PHY, the quirk disables 889 * PHY MCU interrupts before PHY power-down. 890 */ 891 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 892 { 893 switch (tp->mac_version) { 894 case RTL_GIGA_MAC_VER_40: 895 case RTL_GIGA_MAC_VER_41: 896 case RTL_GIGA_MAC_VER_49: 897 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 898 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 899 else 900 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 901 break; 902 default: 903 break; 904 } 905 }; 906 907 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 908 { 909 if (reg == 0x1f) { 910 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 911 return; 912 } 913 914 if (tp->ocp_base != OCP_STD_PHY_BASE) 915 reg -= 0x10; 916 917 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 918 rtl8168g_phy_suspend_quirk(tp, value); 919 920 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 921 } 922 923 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 924 { 925 if (reg == 0x1f) 926 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 927 928 if (tp->ocp_base != OCP_STD_PHY_BASE) 929 reg -= 0x10; 930 931 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 932 } 933 934 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 935 { 936 if (reg == 0x1f) { 937 tp->ocp_base = value << 4; 938 return; 939 } 940 941 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 942 } 943 944 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 945 { 946 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 947 } 948 949 DECLARE_RTL_COND(rtl_phyar_cond) 950 { 951 return RTL_R32(tp, PHYAR) & 0x80000000; 952 } 953 954 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 955 { 956 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 957 958 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 959 /* 960 * According to hardware specs a 20us delay is required after write 961 * complete indication, but before sending next command. 962 */ 963 udelay(20); 964 } 965 966 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 967 { 968 int value; 969 970 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 971 972 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 973 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 974 975 /* 976 * According to hardware specs a 20us delay is required after read 977 * complete indication, but before sending next command. 978 */ 979 udelay(20); 980 981 return value; 982 } 983 984 DECLARE_RTL_COND(rtl_ocpar_cond) 985 { 986 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 987 } 988 989 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 990 991 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 992 { 993 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 994 } 995 996 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 997 { 998 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 999 } 1000 1001 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1002 { 1003 r8168dp_2_mdio_start(tp); 1004 1005 r8169_mdio_write(tp, reg, value); 1006 1007 r8168dp_2_mdio_stop(tp); 1008 } 1009 1010 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1011 { 1012 int value; 1013 1014 /* Work around issue with chip reporting wrong PHY ID */ 1015 if (reg == MII_PHYSID2) 1016 return 0xc912; 1017 1018 r8168dp_2_mdio_start(tp); 1019 1020 value = r8169_mdio_read(tp, reg); 1021 1022 r8168dp_2_mdio_stop(tp); 1023 1024 return value; 1025 } 1026 1027 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1028 { 1029 switch (tp->mac_version) { 1030 case RTL_GIGA_MAC_VER_28: 1031 case RTL_GIGA_MAC_VER_31: 1032 r8168dp_2_mdio_write(tp, location, val); 1033 break; 1034 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1035 r8168g_mdio_write(tp, location, val); 1036 break; 1037 default: 1038 r8169_mdio_write(tp, location, val); 1039 break; 1040 } 1041 } 1042 1043 static int rtl_readphy(struct rtl8169_private *tp, int location) 1044 { 1045 switch (tp->mac_version) { 1046 case RTL_GIGA_MAC_VER_28: 1047 case RTL_GIGA_MAC_VER_31: 1048 return r8168dp_2_mdio_read(tp, location); 1049 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1050 return r8168g_mdio_read(tp, location); 1051 default: 1052 return r8169_mdio_read(tp, location); 1053 } 1054 } 1055 1056 DECLARE_RTL_COND(rtl_ephyar_cond) 1057 { 1058 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1059 } 1060 1061 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1062 { 1063 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1064 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1065 1066 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1067 1068 udelay(10); 1069 } 1070 1071 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1072 { 1073 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1074 1075 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1076 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1077 } 1078 1079 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1080 { 1081 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1082 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1083 RTL_R32(tp, OCPDR) : ~0; 1084 } 1085 1086 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1087 { 1088 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1089 } 1090 1091 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1092 u32 data) 1093 { 1094 RTL_W32(tp, OCPDR, data); 1095 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1096 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1097 } 1098 1099 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1100 u32 data) 1101 { 1102 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1103 data, ERIAR_OOB); 1104 } 1105 1106 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1107 { 1108 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1109 1110 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1111 } 1112 1113 #define OOB_CMD_RESET 0x00 1114 #define OOB_CMD_DRIVER_START 0x05 1115 #define OOB_CMD_DRIVER_STOP 0x06 1116 1117 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1118 { 1119 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1120 } 1121 1122 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1123 { 1124 u16 reg; 1125 1126 reg = rtl8168_get_ocp_reg(tp); 1127 1128 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1129 } 1130 1131 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1132 { 1133 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1134 } 1135 1136 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1137 { 1138 return RTL_R8(tp, IBISR0) & 0x20; 1139 } 1140 1141 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1142 { 1143 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1144 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1145 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1146 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1147 } 1148 1149 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1150 { 1151 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1152 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1153 } 1154 1155 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1156 { 1157 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1158 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1159 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1160 } 1161 1162 static void rtl8168_driver_start(struct rtl8169_private *tp) 1163 { 1164 if (tp->dash_type == RTL_DASH_DP) 1165 rtl8168dp_driver_start(tp); 1166 else 1167 rtl8168ep_driver_start(tp); 1168 } 1169 1170 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1171 { 1172 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1173 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1174 } 1175 1176 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1177 { 1178 rtl8168ep_stop_cmac(tp); 1179 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1180 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1181 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1182 } 1183 1184 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1185 { 1186 if (tp->dash_type == RTL_DASH_DP) 1187 rtl8168dp_driver_stop(tp); 1188 else 1189 rtl8168ep_driver_stop(tp); 1190 } 1191 1192 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1193 { 1194 u16 reg = rtl8168_get_ocp_reg(tp); 1195 1196 return r8168dp_ocp_read(tp, reg) & BIT(15); 1197 } 1198 1199 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1200 { 1201 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1202 } 1203 1204 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1205 { 1206 switch (tp->mac_version) { 1207 case RTL_GIGA_MAC_VER_28: 1208 case RTL_GIGA_MAC_VER_31: 1209 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1210 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 1211 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1212 default: 1213 return RTL_DASH_NONE; 1214 } 1215 } 1216 1217 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1218 { 1219 switch (tp->mac_version) { 1220 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1221 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1222 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1223 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1224 if (enable) 1225 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1226 else 1227 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1228 break; 1229 default: 1230 break; 1231 } 1232 } 1233 1234 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1235 { 1236 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1237 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1238 } 1239 1240 DECLARE_RTL_COND(rtl_efusear_cond) 1241 { 1242 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1243 } 1244 1245 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1246 { 1247 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1248 1249 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1250 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1251 } 1252 1253 static u32 rtl_get_events(struct rtl8169_private *tp) 1254 { 1255 if (rtl_is_8125(tp)) 1256 return RTL_R32(tp, IntrStatus_8125); 1257 else 1258 return RTL_R16(tp, IntrStatus); 1259 } 1260 1261 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1262 { 1263 if (rtl_is_8125(tp)) 1264 RTL_W32(tp, IntrStatus_8125, bits); 1265 else 1266 RTL_W16(tp, IntrStatus, bits); 1267 } 1268 1269 static void rtl_irq_disable(struct rtl8169_private *tp) 1270 { 1271 if (rtl_is_8125(tp)) 1272 RTL_W32(tp, IntrMask_8125, 0); 1273 else 1274 RTL_W16(tp, IntrMask, 0); 1275 } 1276 1277 static void rtl_irq_enable(struct rtl8169_private *tp) 1278 { 1279 if (rtl_is_8125(tp)) 1280 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1281 else 1282 RTL_W16(tp, IntrMask, tp->irq_mask); 1283 } 1284 1285 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1286 { 1287 rtl_irq_disable(tp); 1288 rtl_ack_events(tp, 0xffffffff); 1289 rtl_pci_commit(tp); 1290 } 1291 1292 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1293 { 1294 struct phy_device *phydev = tp->phydev; 1295 1296 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1297 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1298 if (phydev->speed == SPEED_1000) { 1299 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1300 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1301 } else if (phydev->speed == SPEED_100) { 1302 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1303 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1304 } else { 1305 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1306 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1307 } 1308 rtl_reset_packet_filter(tp); 1309 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1310 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1311 if (phydev->speed == SPEED_1000) { 1312 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1313 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1314 } else { 1315 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1316 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1317 } 1318 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1319 if (phydev->speed == SPEED_10) { 1320 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1321 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1322 } else { 1323 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1324 } 1325 } 1326 } 1327 1328 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1329 1330 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1331 { 1332 struct rtl8169_private *tp = netdev_priv(dev); 1333 1334 wol->supported = WAKE_ANY; 1335 wol->wolopts = tp->saved_wolopts; 1336 } 1337 1338 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1339 { 1340 static const struct { 1341 u32 opt; 1342 u16 reg; 1343 u8 mask; 1344 } cfg[] = { 1345 { WAKE_PHY, Config3, LinkUp }, 1346 { WAKE_UCAST, Config5, UWF }, 1347 { WAKE_BCAST, Config5, BWF }, 1348 { WAKE_MCAST, Config5, MWF }, 1349 { WAKE_ANY, Config5, LanWake }, 1350 { WAKE_MAGIC, Config3, MagicPacket } 1351 }; 1352 unsigned int i, tmp = ARRAY_SIZE(cfg); 1353 u8 options; 1354 1355 rtl_unlock_config_regs(tp); 1356 1357 if (rtl_is_8168evl_up(tp)) { 1358 tmp--; 1359 if (wolopts & WAKE_MAGIC) 1360 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1361 else 1362 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1363 } else if (rtl_is_8125(tp)) { 1364 tmp--; 1365 if (wolopts & WAKE_MAGIC) 1366 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1367 else 1368 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1369 } 1370 1371 for (i = 0; i < tmp; i++) { 1372 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1373 if (wolopts & cfg[i].opt) 1374 options |= cfg[i].mask; 1375 RTL_W8(tp, cfg[i].reg, options); 1376 } 1377 1378 switch (tp->mac_version) { 1379 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1380 options = RTL_R8(tp, Config1) & ~PMEnable; 1381 if (wolopts) 1382 options |= PMEnable; 1383 RTL_W8(tp, Config1, options); 1384 break; 1385 case RTL_GIGA_MAC_VER_34: 1386 case RTL_GIGA_MAC_VER_37: 1387 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1388 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1389 if (wolopts) 1390 options |= PME_SIGNAL; 1391 RTL_W8(tp, Config2, options); 1392 break; 1393 default: 1394 break; 1395 } 1396 1397 rtl_lock_config_regs(tp); 1398 1399 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1400 rtl_set_d3_pll_down(tp, !wolopts); 1401 tp->dev->wol_enabled = wolopts ? 1 : 0; 1402 } 1403 1404 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1405 { 1406 struct rtl8169_private *tp = netdev_priv(dev); 1407 1408 if (wol->wolopts & ~WAKE_ANY) 1409 return -EINVAL; 1410 1411 tp->saved_wolopts = wol->wolopts; 1412 __rtl8169_set_wol(tp, tp->saved_wolopts); 1413 1414 return 0; 1415 } 1416 1417 static void rtl8169_get_drvinfo(struct net_device *dev, 1418 struct ethtool_drvinfo *info) 1419 { 1420 struct rtl8169_private *tp = netdev_priv(dev); 1421 struct rtl_fw *rtl_fw = tp->rtl_fw; 1422 1423 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1424 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1425 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1426 if (rtl_fw) 1427 strlcpy(info->fw_version, rtl_fw->version, 1428 sizeof(info->fw_version)); 1429 } 1430 1431 static int rtl8169_get_regs_len(struct net_device *dev) 1432 { 1433 return R8169_REGS_SIZE; 1434 } 1435 1436 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1437 netdev_features_t features) 1438 { 1439 struct rtl8169_private *tp = netdev_priv(dev); 1440 1441 if (dev->mtu > TD_MSS_MAX) 1442 features &= ~NETIF_F_ALL_TSO; 1443 1444 if (dev->mtu > ETH_DATA_LEN && 1445 tp->mac_version > RTL_GIGA_MAC_VER_06) 1446 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1447 1448 return features; 1449 } 1450 1451 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1452 netdev_features_t features) 1453 { 1454 u32 rx_config = RTL_R32(tp, RxConfig); 1455 1456 if (features & NETIF_F_RXALL) 1457 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1458 else 1459 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1460 1461 if (rtl_is_8125(tp)) { 1462 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1463 rx_config |= RX_VLAN_8125; 1464 else 1465 rx_config &= ~RX_VLAN_8125; 1466 } 1467 1468 RTL_W32(tp, RxConfig, rx_config); 1469 } 1470 1471 static int rtl8169_set_features(struct net_device *dev, 1472 netdev_features_t features) 1473 { 1474 struct rtl8169_private *tp = netdev_priv(dev); 1475 1476 rtl_set_rx_config_features(tp, features); 1477 1478 if (features & NETIF_F_RXCSUM) 1479 tp->cp_cmd |= RxChkSum; 1480 else 1481 tp->cp_cmd &= ~RxChkSum; 1482 1483 if (!rtl_is_8125(tp)) { 1484 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1485 tp->cp_cmd |= RxVlan; 1486 else 1487 tp->cp_cmd &= ~RxVlan; 1488 } 1489 1490 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1491 rtl_pci_commit(tp); 1492 1493 return 0; 1494 } 1495 1496 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1497 { 1498 return (skb_vlan_tag_present(skb)) ? 1499 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1500 } 1501 1502 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1503 { 1504 u32 opts2 = le32_to_cpu(desc->opts2); 1505 1506 if (opts2 & RxVlanTag) 1507 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1508 } 1509 1510 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1511 void *p) 1512 { 1513 struct rtl8169_private *tp = netdev_priv(dev); 1514 u32 __iomem *data = tp->mmio_addr; 1515 u32 *dw = p; 1516 int i; 1517 1518 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1519 memcpy_fromio(dw++, data++, 4); 1520 } 1521 1522 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1523 "tx_packets", 1524 "rx_packets", 1525 "tx_errors", 1526 "rx_errors", 1527 "rx_missed", 1528 "align_errors", 1529 "tx_single_collisions", 1530 "tx_multi_collisions", 1531 "unicast", 1532 "broadcast", 1533 "multicast", 1534 "tx_aborted", 1535 "tx_underrun", 1536 }; 1537 1538 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1539 { 1540 switch (sset) { 1541 case ETH_SS_STATS: 1542 return ARRAY_SIZE(rtl8169_gstrings); 1543 default: 1544 return -EOPNOTSUPP; 1545 } 1546 } 1547 1548 DECLARE_RTL_COND(rtl_counters_cond) 1549 { 1550 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1551 } 1552 1553 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1554 { 1555 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1556 1557 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1558 rtl_pci_commit(tp); 1559 RTL_W32(tp, CounterAddrLow, cmd); 1560 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1561 1562 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1563 } 1564 1565 static void rtl8169_update_counters(struct rtl8169_private *tp) 1566 { 1567 u8 val = RTL_R8(tp, ChipCmd); 1568 1569 /* 1570 * Some chips are unable to dump tally counters when the receiver 1571 * is disabled. If 0xff chip may be in a PCI power-save state. 1572 */ 1573 if (val & CmdRxEnb && val != 0xff) 1574 rtl8169_do_counters(tp, CounterDump); 1575 } 1576 1577 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1578 { 1579 struct rtl8169_counters *counters = tp->counters; 1580 1581 /* 1582 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1583 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1584 * reset by a power cycle, while the counter values collected by the 1585 * driver are reset at every driver unload/load cycle. 1586 * 1587 * To make sure the HW values returned by @get_stats64 match the SW 1588 * values, we collect the initial values at first open(*) and use them 1589 * as offsets to normalize the values returned by @get_stats64. 1590 * 1591 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1592 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1593 * set at open time by rtl_hw_start. 1594 */ 1595 1596 if (tp->tc_offset.inited) 1597 return; 1598 1599 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1600 rtl8169_do_counters(tp, CounterReset); 1601 } else { 1602 rtl8169_update_counters(tp); 1603 tp->tc_offset.tx_errors = counters->tx_errors; 1604 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1605 tp->tc_offset.tx_aborted = counters->tx_aborted; 1606 tp->tc_offset.rx_missed = counters->rx_missed; 1607 } 1608 1609 tp->tc_offset.inited = true; 1610 } 1611 1612 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1613 struct ethtool_stats *stats, u64 *data) 1614 { 1615 struct rtl8169_private *tp = netdev_priv(dev); 1616 struct rtl8169_counters *counters; 1617 1618 counters = tp->counters; 1619 rtl8169_update_counters(tp); 1620 1621 data[0] = le64_to_cpu(counters->tx_packets); 1622 data[1] = le64_to_cpu(counters->rx_packets); 1623 data[2] = le64_to_cpu(counters->tx_errors); 1624 data[3] = le32_to_cpu(counters->rx_errors); 1625 data[4] = le16_to_cpu(counters->rx_missed); 1626 data[5] = le16_to_cpu(counters->align_errors); 1627 data[6] = le32_to_cpu(counters->tx_one_collision); 1628 data[7] = le32_to_cpu(counters->tx_multi_collision); 1629 data[8] = le64_to_cpu(counters->rx_unicast); 1630 data[9] = le64_to_cpu(counters->rx_broadcast); 1631 data[10] = le32_to_cpu(counters->rx_multicast); 1632 data[11] = le16_to_cpu(counters->tx_aborted); 1633 data[12] = le16_to_cpu(counters->tx_underun); 1634 } 1635 1636 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1637 { 1638 switch(stringset) { 1639 case ETH_SS_STATS: 1640 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1641 break; 1642 } 1643 } 1644 1645 /* 1646 * Interrupt coalescing 1647 * 1648 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1649 * > 8169, 8168 and 810x line of chipsets 1650 * 1651 * 8169, 8168, and 8136(810x) serial chipsets support it. 1652 * 1653 * > 2 - the Tx timer unit at gigabit speed 1654 * 1655 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1656 * (0xe0) bit 1 and bit 0. 1657 * 1658 * For 8169 1659 * bit[1:0] \ speed 1000M 100M 10M 1660 * 0 0 320ns 2.56us 40.96us 1661 * 0 1 2.56us 20.48us 327.7us 1662 * 1 0 5.12us 40.96us 655.4us 1663 * 1 1 10.24us 81.92us 1.31ms 1664 * 1665 * For the other 1666 * bit[1:0] \ speed 1000M 100M 10M 1667 * 0 0 5us 2.56us 40.96us 1668 * 0 1 40us 20.48us 327.7us 1669 * 1 0 80us 40.96us 655.4us 1670 * 1 1 160us 81.92us 1.31ms 1671 */ 1672 1673 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1674 struct rtl_coalesce_info { 1675 u32 speed; 1676 u32 scale_nsecs[4]; 1677 }; 1678 1679 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1680 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1681 1682 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1683 { SPEED_1000, COALESCE_DELAY(320) }, 1684 { SPEED_100, COALESCE_DELAY(2560) }, 1685 { SPEED_10, COALESCE_DELAY(40960) }, 1686 { 0 }, 1687 }; 1688 1689 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1690 { SPEED_1000, COALESCE_DELAY(5000) }, 1691 { SPEED_100, COALESCE_DELAY(2560) }, 1692 { SPEED_10, COALESCE_DELAY(40960) }, 1693 { 0 }, 1694 }; 1695 #undef COALESCE_DELAY 1696 1697 /* get rx/tx scale vector corresponding to current speed */ 1698 static const struct rtl_coalesce_info * 1699 rtl_coalesce_info(struct rtl8169_private *tp) 1700 { 1701 const struct rtl_coalesce_info *ci; 1702 1703 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1704 ci = rtl_coalesce_info_8169; 1705 else 1706 ci = rtl_coalesce_info_8168_8136; 1707 1708 /* if speed is unknown assume highest one */ 1709 if (tp->phydev->speed == SPEED_UNKNOWN) 1710 return ci; 1711 1712 for (; ci->speed; ci++) { 1713 if (tp->phydev->speed == ci->speed) 1714 return ci; 1715 } 1716 1717 return ERR_PTR(-ELNRNG); 1718 } 1719 1720 static int rtl_get_coalesce(struct net_device *dev, 1721 struct ethtool_coalesce *ec, 1722 struct kernel_ethtool_coalesce *kernel_coal, 1723 struct netlink_ext_ack *extack) 1724 { 1725 struct rtl8169_private *tp = netdev_priv(dev); 1726 const struct rtl_coalesce_info *ci; 1727 u32 scale, c_us, c_fr; 1728 u16 intrmit; 1729 1730 if (rtl_is_8125(tp)) 1731 return -EOPNOTSUPP; 1732 1733 memset(ec, 0, sizeof(*ec)); 1734 1735 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1736 ci = rtl_coalesce_info(tp); 1737 if (IS_ERR(ci)) 1738 return PTR_ERR(ci); 1739 1740 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1741 1742 intrmit = RTL_R16(tp, IntrMitigate); 1743 1744 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1745 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1746 1747 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1748 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1749 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1750 1751 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1752 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1753 1754 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1755 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1756 1757 return 0; 1758 } 1759 1760 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1761 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1762 u16 *cp01) 1763 { 1764 const struct rtl_coalesce_info *ci; 1765 u16 i; 1766 1767 ci = rtl_coalesce_info(tp); 1768 if (IS_ERR(ci)) 1769 return PTR_ERR(ci); 1770 1771 for (i = 0; i < 4; i++) { 1772 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1773 *cp01 = i; 1774 return ci->scale_nsecs[i]; 1775 } 1776 } 1777 1778 return -ERANGE; 1779 } 1780 1781 static int rtl_set_coalesce(struct net_device *dev, 1782 struct ethtool_coalesce *ec, 1783 struct kernel_ethtool_coalesce *kernel_coal, 1784 struct netlink_ext_ack *extack) 1785 { 1786 struct rtl8169_private *tp = netdev_priv(dev); 1787 u32 tx_fr = ec->tx_max_coalesced_frames; 1788 u32 rx_fr = ec->rx_max_coalesced_frames; 1789 u32 coal_usec_max, units; 1790 u16 w = 0, cp01 = 0; 1791 int scale; 1792 1793 if (rtl_is_8125(tp)) 1794 return -EOPNOTSUPP; 1795 1796 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1797 return -ERANGE; 1798 1799 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1800 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1801 if (scale < 0) 1802 return scale; 1803 1804 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1805 * not only when usecs=0 because of e.g. the following scenario: 1806 * 1807 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1808 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1809 * - then user does `ethtool -C eth0 rx-usecs 100` 1810 * 1811 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1812 * if we want to ignore rx_frames then it has to be set to 0. 1813 */ 1814 if (rx_fr == 1) 1815 rx_fr = 0; 1816 if (tx_fr == 1) 1817 tx_fr = 0; 1818 1819 /* HW requires time limit to be set if frame limit is set */ 1820 if ((tx_fr && !ec->tx_coalesce_usecs) || 1821 (rx_fr && !ec->rx_coalesce_usecs)) 1822 return -EINVAL; 1823 1824 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1825 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1826 1827 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1828 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1829 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1830 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1831 1832 RTL_W16(tp, IntrMitigate, w); 1833 1834 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1835 if (rtl_is_8168evl_up(tp)) { 1836 if (!rx_fr && !tx_fr) 1837 /* disable packet counter */ 1838 tp->cp_cmd |= PktCntrDisable; 1839 else 1840 tp->cp_cmd &= ~PktCntrDisable; 1841 } 1842 1843 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1844 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1845 rtl_pci_commit(tp); 1846 1847 return 0; 1848 } 1849 1850 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1851 { 1852 struct rtl8169_private *tp = netdev_priv(dev); 1853 1854 if (!rtl_supports_eee(tp)) 1855 return -EOPNOTSUPP; 1856 1857 return phy_ethtool_get_eee(tp->phydev, data); 1858 } 1859 1860 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1861 { 1862 struct rtl8169_private *tp = netdev_priv(dev); 1863 int ret; 1864 1865 if (!rtl_supports_eee(tp)) 1866 return -EOPNOTSUPP; 1867 1868 ret = phy_ethtool_set_eee(tp->phydev, data); 1869 1870 if (!ret) 1871 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1872 MDIO_AN_EEE_ADV); 1873 return ret; 1874 } 1875 1876 static void rtl8169_get_ringparam(struct net_device *dev, 1877 struct ethtool_ringparam *data, 1878 struct kernel_ethtool_ringparam *kernel_data, 1879 struct netlink_ext_ack *extack) 1880 { 1881 data->rx_max_pending = NUM_RX_DESC; 1882 data->rx_pending = NUM_RX_DESC; 1883 data->tx_max_pending = NUM_TX_DESC; 1884 data->tx_pending = NUM_TX_DESC; 1885 } 1886 1887 static void rtl8169_get_pauseparam(struct net_device *dev, 1888 struct ethtool_pauseparam *data) 1889 { 1890 struct rtl8169_private *tp = netdev_priv(dev); 1891 bool tx_pause, rx_pause; 1892 1893 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1894 1895 data->autoneg = tp->phydev->autoneg; 1896 data->tx_pause = tx_pause ? 1 : 0; 1897 data->rx_pause = rx_pause ? 1 : 0; 1898 } 1899 1900 static int rtl8169_set_pauseparam(struct net_device *dev, 1901 struct ethtool_pauseparam *data) 1902 { 1903 struct rtl8169_private *tp = netdev_priv(dev); 1904 1905 if (dev->mtu > ETH_DATA_LEN) 1906 return -EOPNOTSUPP; 1907 1908 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1909 1910 return 0; 1911 } 1912 1913 static const struct ethtool_ops rtl8169_ethtool_ops = { 1914 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1915 ETHTOOL_COALESCE_MAX_FRAMES, 1916 .get_drvinfo = rtl8169_get_drvinfo, 1917 .get_regs_len = rtl8169_get_regs_len, 1918 .get_link = ethtool_op_get_link, 1919 .get_coalesce = rtl_get_coalesce, 1920 .set_coalesce = rtl_set_coalesce, 1921 .get_regs = rtl8169_get_regs, 1922 .get_wol = rtl8169_get_wol, 1923 .set_wol = rtl8169_set_wol, 1924 .get_strings = rtl8169_get_strings, 1925 .get_sset_count = rtl8169_get_sset_count, 1926 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1927 .get_ts_info = ethtool_op_get_ts_info, 1928 .nway_reset = phy_ethtool_nway_reset, 1929 .get_eee = rtl8169_get_eee, 1930 .set_eee = rtl8169_set_eee, 1931 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1932 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1933 .get_ringparam = rtl8169_get_ringparam, 1934 .get_pauseparam = rtl8169_get_pauseparam, 1935 .set_pauseparam = rtl8169_set_pauseparam, 1936 }; 1937 1938 static void rtl_enable_eee(struct rtl8169_private *tp) 1939 { 1940 struct phy_device *phydev = tp->phydev; 1941 int adv; 1942 1943 /* respect EEE advertisement the user may have set */ 1944 if (tp->eee_adv >= 0) 1945 adv = tp->eee_adv; 1946 else 1947 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1948 1949 if (adv >= 0) 1950 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1951 } 1952 1953 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1954 { 1955 /* 1956 * The driver currently handles the 8168Bf and the 8168Be identically 1957 * but they can be identified more specifically through the test below 1958 * if needed: 1959 * 1960 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1961 * 1962 * Same thing for the 8101Eb and the 8101Ec: 1963 * 1964 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1965 */ 1966 static const struct rtl_mac_info { 1967 u16 mask; 1968 u16 val; 1969 enum mac_version ver; 1970 } mac_info[] = { 1971 /* 8125B family. */ 1972 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1973 1974 /* 8125A family. */ 1975 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 1976 /* It seems only XID 609 made it to the mass market. 1977 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1978 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1979 */ 1980 1981 /* RTL8117 */ 1982 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 1983 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1984 1985 /* 8168EP family. */ 1986 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1987 /* It seems this chip version never made it to 1988 * the wild. Let's disable detection. 1989 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1990 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1991 */ 1992 1993 /* 8168H family. */ 1994 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1995 /* It seems this chip version never made it to 1996 * the wild. Let's disable detection. 1997 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1998 */ 1999 2000 /* 8168G family. */ 2001 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2002 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2003 /* It seems this chip version never made it to 2004 * the wild. Let's disable detection. 2005 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2006 */ 2007 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2008 2009 /* 8168F family. */ 2010 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2011 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2012 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2013 2014 /* 8168E family. */ 2015 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2016 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2017 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2018 2019 /* 8168D family. */ 2020 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2021 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2022 2023 /* 8168DP family. */ 2024 /* It seems this early RTL8168dp version never made it to 2025 * the wild. Support has been removed. 2026 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2027 */ 2028 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2029 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2030 2031 /* 8168C family. */ 2032 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2033 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2034 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2035 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2036 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2037 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2038 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2039 2040 /* 8168B family. */ 2041 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2042 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2043 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2044 2045 /* 8101 family. */ 2046 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2047 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2048 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2049 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2050 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2051 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2052 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2053 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2054 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2055 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2056 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2057 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2058 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2059 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2060 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2061 /* FIXME: where did these entries come from ? -- FR 2062 * Not even r8101 vendor driver knows these id's, 2063 * so let's disable detection for now. -- HK 2064 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2065 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2066 */ 2067 2068 /* 8110 family. */ 2069 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2070 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2071 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2072 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2073 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2074 2075 /* Catch-all */ 2076 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2077 }; 2078 const struct rtl_mac_info *p = mac_info; 2079 enum mac_version ver; 2080 2081 while ((xid & p->mask) != p->val) 2082 p++; 2083 ver = p->ver; 2084 2085 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2086 if (ver == RTL_GIGA_MAC_VER_42) 2087 ver = RTL_GIGA_MAC_VER_43; 2088 else if (ver == RTL_GIGA_MAC_VER_45) 2089 ver = RTL_GIGA_MAC_VER_47; 2090 else if (ver == RTL_GIGA_MAC_VER_46) 2091 ver = RTL_GIGA_MAC_VER_48; 2092 } 2093 2094 return ver; 2095 } 2096 2097 static void rtl_release_firmware(struct rtl8169_private *tp) 2098 { 2099 if (tp->rtl_fw) { 2100 rtl_fw_release_firmware(tp->rtl_fw); 2101 kfree(tp->rtl_fw); 2102 tp->rtl_fw = NULL; 2103 } 2104 } 2105 2106 void r8169_apply_firmware(struct rtl8169_private *tp) 2107 { 2108 int val; 2109 2110 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2111 if (tp->rtl_fw) { 2112 rtl_fw_write_firmware(tp, tp->rtl_fw); 2113 /* At least one firmware doesn't reset tp->ocp_base. */ 2114 tp->ocp_base = OCP_STD_PHY_BASE; 2115 2116 /* PHY soft reset may still be in progress */ 2117 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2118 !(val & BMCR_RESET), 2119 50000, 600000, true); 2120 } 2121 } 2122 2123 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2124 { 2125 /* Adjust EEE LED frequency */ 2126 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2127 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2128 2129 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2130 } 2131 2132 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2133 { 2134 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2135 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2136 } 2137 2138 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2139 { 2140 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2141 } 2142 2143 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2144 { 2145 rtl8125_set_eee_txidle_timer(tp); 2146 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2147 } 2148 2149 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2150 { 2151 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2152 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2153 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2154 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2155 } 2156 2157 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2158 { 2159 u16 data1, data2, ioffset; 2160 2161 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2162 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2163 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2164 2165 ioffset = (data2 >> 1) & 0x7ff8; 2166 ioffset |= data2 & 0x0007; 2167 if (data1 & BIT(7)) 2168 ioffset |= BIT(15); 2169 2170 return ioffset; 2171 } 2172 2173 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2174 { 2175 set_bit(flag, tp->wk.flags); 2176 schedule_work(&tp->wk.work); 2177 } 2178 2179 static void rtl8169_init_phy(struct rtl8169_private *tp) 2180 { 2181 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2182 2183 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2184 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2185 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2186 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2187 RTL_W8(tp, 0x82, 0x01); 2188 } 2189 2190 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2191 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2192 tp->pci_dev->subsystem_device == 0xe000) 2193 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2194 2195 /* We may have called phy_speed_down before */ 2196 phy_speed_up(tp->phydev); 2197 2198 if (rtl_supports_eee(tp)) 2199 rtl_enable_eee(tp); 2200 2201 genphy_soft_reset(tp->phydev); 2202 } 2203 2204 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2205 { 2206 rtl_unlock_config_regs(tp); 2207 2208 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2209 rtl_pci_commit(tp); 2210 2211 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2212 rtl_pci_commit(tp); 2213 2214 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2215 rtl_rar_exgmac_set(tp, addr); 2216 2217 rtl_lock_config_regs(tp); 2218 } 2219 2220 static int rtl_set_mac_address(struct net_device *dev, void *p) 2221 { 2222 struct rtl8169_private *tp = netdev_priv(dev); 2223 int ret; 2224 2225 ret = eth_mac_addr(dev, p); 2226 if (ret) 2227 return ret; 2228 2229 rtl_rar_set(tp, dev->dev_addr); 2230 2231 return 0; 2232 } 2233 2234 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2235 { 2236 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2237 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2238 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2239 } 2240 2241 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2242 { 2243 if (tp->dash_type != RTL_DASH_NONE) 2244 return; 2245 2246 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2247 tp->mac_version == RTL_GIGA_MAC_VER_33) 2248 rtl_ephy_write(tp, 0x19, 0xff64); 2249 2250 if (device_may_wakeup(tp_to_dev(tp))) { 2251 phy_speed_down(tp->phydev, false); 2252 rtl_wol_enable_rx(tp); 2253 } 2254 } 2255 2256 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2257 { 2258 switch (tp->mac_version) { 2259 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2260 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2261 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2262 break; 2263 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2264 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2265 case RTL_GIGA_MAC_VER_38: 2266 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2267 break; 2268 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2269 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2270 break; 2271 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2272 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2273 break; 2274 default: 2275 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2276 break; 2277 } 2278 } 2279 2280 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2281 { 2282 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2283 } 2284 2285 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2286 { 2287 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2288 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2289 } 2290 2291 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2292 { 2293 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2294 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2295 } 2296 2297 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2298 { 2299 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2300 } 2301 2302 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2303 { 2304 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2305 } 2306 2307 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2308 { 2309 RTL_W8(tp, MaxTxPacketSize, 0x24); 2310 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2311 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2312 } 2313 2314 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2315 { 2316 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2317 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2318 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2319 } 2320 2321 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2322 { 2323 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2324 } 2325 2326 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2327 { 2328 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2329 } 2330 2331 static void rtl_jumbo_config(struct rtl8169_private *tp) 2332 { 2333 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2334 int readrq = 4096; 2335 2336 rtl_unlock_config_regs(tp); 2337 switch (tp->mac_version) { 2338 case RTL_GIGA_MAC_VER_12: 2339 case RTL_GIGA_MAC_VER_17: 2340 if (jumbo) { 2341 readrq = 512; 2342 r8168b_1_hw_jumbo_enable(tp); 2343 } else { 2344 r8168b_1_hw_jumbo_disable(tp); 2345 } 2346 break; 2347 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2348 if (jumbo) { 2349 readrq = 512; 2350 r8168c_hw_jumbo_enable(tp); 2351 } else { 2352 r8168c_hw_jumbo_disable(tp); 2353 } 2354 break; 2355 case RTL_GIGA_MAC_VER_28: 2356 if (jumbo) 2357 r8168dp_hw_jumbo_enable(tp); 2358 else 2359 r8168dp_hw_jumbo_disable(tp); 2360 break; 2361 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2362 if (jumbo) 2363 r8168e_hw_jumbo_enable(tp); 2364 else 2365 r8168e_hw_jumbo_disable(tp); 2366 break; 2367 default: 2368 break; 2369 } 2370 rtl_lock_config_regs(tp); 2371 2372 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2373 pcie_set_readrq(tp->pci_dev, readrq); 2374 2375 /* Chip doesn't support pause in jumbo mode */ 2376 if (jumbo) { 2377 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2378 tp->phydev->advertising); 2379 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2380 tp->phydev->advertising); 2381 phy_start_aneg(tp->phydev); 2382 } 2383 } 2384 2385 DECLARE_RTL_COND(rtl_chipcmd_cond) 2386 { 2387 return RTL_R8(tp, ChipCmd) & CmdReset; 2388 } 2389 2390 static void rtl_hw_reset(struct rtl8169_private *tp) 2391 { 2392 RTL_W8(tp, ChipCmd, CmdReset); 2393 2394 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2395 } 2396 2397 static void rtl_request_firmware(struct rtl8169_private *tp) 2398 { 2399 struct rtl_fw *rtl_fw; 2400 2401 /* firmware loaded already or no firmware available */ 2402 if (tp->rtl_fw || !tp->fw_name) 2403 return; 2404 2405 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2406 if (!rtl_fw) 2407 return; 2408 2409 rtl_fw->phy_write = rtl_writephy; 2410 rtl_fw->phy_read = rtl_readphy; 2411 rtl_fw->mac_mcu_write = mac_mcu_write; 2412 rtl_fw->mac_mcu_read = mac_mcu_read; 2413 rtl_fw->fw_name = tp->fw_name; 2414 rtl_fw->dev = tp_to_dev(tp); 2415 2416 if (rtl_fw_request_firmware(rtl_fw)) 2417 kfree(rtl_fw); 2418 else 2419 tp->rtl_fw = rtl_fw; 2420 } 2421 2422 static void rtl_rx_close(struct rtl8169_private *tp) 2423 { 2424 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2425 } 2426 2427 DECLARE_RTL_COND(rtl_npq_cond) 2428 { 2429 return RTL_R8(tp, TxPoll) & NPQ; 2430 } 2431 2432 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2433 { 2434 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2435 } 2436 2437 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2438 { 2439 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2440 } 2441 2442 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2443 { 2444 /* IntrMitigate has new functionality on RTL8125 */ 2445 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2446 } 2447 2448 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2449 { 2450 switch (tp->mac_version) { 2451 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2452 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2453 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2454 break; 2455 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2456 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2457 break; 2458 case RTL_GIGA_MAC_VER_63: 2459 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2460 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2461 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2462 break; 2463 default: 2464 break; 2465 } 2466 } 2467 2468 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2469 { 2470 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2471 fsleep(2000); 2472 rtl_wait_txrx_fifo_empty(tp); 2473 } 2474 2475 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2476 { 2477 u32 val = TX_DMA_BURST << TxDMAShift | 2478 InterFrameGap << TxInterFrameGapShift; 2479 2480 if (rtl_is_8168evl_up(tp)) 2481 val |= TXCFG_AUTO_FIFO; 2482 2483 RTL_W32(tp, TxConfig, val); 2484 } 2485 2486 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2487 { 2488 /* Low hurts. Let's disable the filtering. */ 2489 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2490 } 2491 2492 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2493 { 2494 /* 2495 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2496 * register to be written before TxDescAddrLow to work. 2497 * Switching from MMIO to I/O access fixes the issue as well. 2498 */ 2499 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2500 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2501 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2502 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2503 } 2504 2505 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2506 { 2507 u32 val; 2508 2509 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2510 val = 0x000fff00; 2511 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2512 val = 0x00ffff00; 2513 else 2514 return; 2515 2516 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2517 val |= 0xff; 2518 2519 RTL_W32(tp, 0x7c, val); 2520 } 2521 2522 static void rtl_set_rx_mode(struct net_device *dev) 2523 { 2524 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2525 /* Multicast hash filter */ 2526 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2527 struct rtl8169_private *tp = netdev_priv(dev); 2528 u32 tmp; 2529 2530 if (dev->flags & IFF_PROMISC) { 2531 rx_mode |= AcceptAllPhys; 2532 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2533 dev->flags & IFF_ALLMULTI || 2534 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2535 /* accept all multicasts */ 2536 } else if (netdev_mc_empty(dev)) { 2537 rx_mode &= ~AcceptMulticast; 2538 } else { 2539 struct netdev_hw_addr *ha; 2540 2541 mc_filter[1] = mc_filter[0] = 0; 2542 netdev_for_each_mc_addr(ha, dev) { 2543 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2544 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2545 } 2546 2547 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2548 tmp = mc_filter[0]; 2549 mc_filter[0] = swab32(mc_filter[1]); 2550 mc_filter[1] = swab32(tmp); 2551 } 2552 } 2553 2554 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2555 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2556 2557 tmp = RTL_R32(tp, RxConfig); 2558 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2559 } 2560 2561 DECLARE_RTL_COND(rtl_csiar_cond) 2562 { 2563 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2564 } 2565 2566 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2567 { 2568 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2569 2570 RTL_W32(tp, CSIDR, value); 2571 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2572 CSIAR_BYTE_ENABLE | func << 16); 2573 2574 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2575 } 2576 2577 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2578 { 2579 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2580 2581 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2582 CSIAR_BYTE_ENABLE); 2583 2584 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2585 RTL_R32(tp, CSIDR) : ~0; 2586 } 2587 2588 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2589 { 2590 struct pci_dev *pdev = tp->pci_dev; 2591 u32 csi; 2592 2593 /* According to Realtek the value at config space address 0x070f 2594 * controls the L0s/L1 entrance latency. We try standard ECAM access 2595 * first and if it fails fall back to CSI. 2596 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2597 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2598 */ 2599 if (pdev->cfg_size > 0x070f && 2600 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2601 return; 2602 2603 netdev_notice_once(tp->dev, 2604 "No native access to PCI extended config space, falling back to CSI\n"); 2605 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2606 rtl_csi_write(tp, 0x070c, csi | val << 24); 2607 } 2608 2609 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2610 { 2611 /* L0 7us, L1 16us */ 2612 rtl_set_aspm_entry_latency(tp, 0x27); 2613 } 2614 2615 struct ephy_info { 2616 unsigned int offset; 2617 u16 mask; 2618 u16 bits; 2619 }; 2620 2621 static void __rtl_ephy_init(struct rtl8169_private *tp, 2622 const struct ephy_info *e, int len) 2623 { 2624 u16 w; 2625 2626 while (len-- > 0) { 2627 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2628 rtl_ephy_write(tp, e->offset, w); 2629 e++; 2630 } 2631 } 2632 2633 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2634 2635 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2636 { 2637 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2638 PCI_EXP_LNKCTL_CLKREQ_EN); 2639 } 2640 2641 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2642 { 2643 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2644 PCI_EXP_LNKCTL_CLKREQ_EN); 2645 } 2646 2647 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2648 { 2649 /* work around an issue when PCI reset occurs during L2/L3 state */ 2650 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2651 } 2652 2653 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2654 { 2655 /* Bits control which events trigger ASPM L1 exit: 2656 * Bit 12: rxdv 2657 * Bit 11: ltr_msg 2658 * Bit 10: txdma_poll 2659 * Bit 9: xadm 2660 * Bit 8: pktavi 2661 * Bit 7: txpla 2662 */ 2663 switch (tp->mac_version) { 2664 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2665 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2666 break; 2667 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2668 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2669 break; 2670 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2671 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2672 break; 2673 default: 2674 break; 2675 } 2676 } 2677 2678 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2679 { 2680 switch (tp->mac_version) { 2681 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2682 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2683 break; 2684 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2685 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2686 break; 2687 default: 2688 break; 2689 } 2690 } 2691 2692 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2693 { 2694 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2695 if (enable && tp->aspm_manageable) { 2696 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2697 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2698 2699 switch (tp->mac_version) { 2700 case RTL_GIGA_MAC_VER_45 ... RTL_GIGA_MAC_VER_48: 2701 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2702 /* reset ephy tx/rx disable timer */ 2703 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2704 /* chip can trigger L1.2 */ 2705 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2706 break; 2707 default: 2708 break; 2709 } 2710 } else { 2711 switch (tp->mac_version) { 2712 case RTL_GIGA_MAC_VER_45 ... RTL_GIGA_MAC_VER_48: 2713 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2714 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2715 break; 2716 default: 2717 break; 2718 } 2719 2720 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2721 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2722 } 2723 2724 udelay(10); 2725 } 2726 2727 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2728 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2729 { 2730 /* Usage of dynamic vs. static FIFO is controlled by bit 2731 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2732 */ 2733 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2734 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2735 } 2736 2737 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2738 u8 low, u8 high) 2739 { 2740 /* FIFO thresholds for pause flow control */ 2741 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2742 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2743 } 2744 2745 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2746 { 2747 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2748 } 2749 2750 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2751 { 2752 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2753 2754 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2755 2756 rtl_disable_clock_request(tp); 2757 } 2758 2759 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2760 { 2761 static const struct ephy_info e_info_8168cp[] = { 2762 { 0x01, 0, 0x0001 }, 2763 { 0x02, 0x0800, 0x1000 }, 2764 { 0x03, 0, 0x0042 }, 2765 { 0x06, 0x0080, 0x0000 }, 2766 { 0x07, 0, 0x2000 } 2767 }; 2768 2769 rtl_set_def_aspm_entry_latency(tp); 2770 2771 rtl_ephy_init(tp, e_info_8168cp); 2772 2773 __rtl_hw_start_8168cp(tp); 2774 } 2775 2776 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2777 { 2778 rtl_set_def_aspm_entry_latency(tp); 2779 2780 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2781 } 2782 2783 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2784 { 2785 rtl_set_def_aspm_entry_latency(tp); 2786 2787 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2788 2789 /* Magic. */ 2790 RTL_W8(tp, DBG_REG, 0x20); 2791 } 2792 2793 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2794 { 2795 static const struct ephy_info e_info_8168c_1[] = { 2796 { 0x02, 0x0800, 0x1000 }, 2797 { 0x03, 0, 0x0002 }, 2798 { 0x06, 0x0080, 0x0000 } 2799 }; 2800 2801 rtl_set_def_aspm_entry_latency(tp); 2802 2803 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2804 2805 rtl_ephy_init(tp, e_info_8168c_1); 2806 2807 __rtl_hw_start_8168cp(tp); 2808 } 2809 2810 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2811 { 2812 static const struct ephy_info e_info_8168c_2[] = { 2813 { 0x01, 0, 0x0001 }, 2814 { 0x03, 0x0400, 0x0020 } 2815 }; 2816 2817 rtl_set_def_aspm_entry_latency(tp); 2818 2819 rtl_ephy_init(tp, e_info_8168c_2); 2820 2821 __rtl_hw_start_8168cp(tp); 2822 } 2823 2824 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2825 { 2826 rtl_set_def_aspm_entry_latency(tp); 2827 2828 __rtl_hw_start_8168cp(tp); 2829 } 2830 2831 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2832 { 2833 rtl_set_def_aspm_entry_latency(tp); 2834 2835 rtl_disable_clock_request(tp); 2836 } 2837 2838 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2839 { 2840 static const struct ephy_info e_info_8168d_4[] = { 2841 { 0x0b, 0x0000, 0x0048 }, 2842 { 0x19, 0x0020, 0x0050 }, 2843 { 0x0c, 0x0100, 0x0020 }, 2844 { 0x10, 0x0004, 0x0000 }, 2845 }; 2846 2847 rtl_set_def_aspm_entry_latency(tp); 2848 2849 rtl_ephy_init(tp, e_info_8168d_4); 2850 2851 rtl_enable_clock_request(tp); 2852 } 2853 2854 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2855 { 2856 static const struct ephy_info e_info_8168e_1[] = { 2857 { 0x00, 0x0200, 0x0100 }, 2858 { 0x00, 0x0000, 0x0004 }, 2859 { 0x06, 0x0002, 0x0001 }, 2860 { 0x06, 0x0000, 0x0030 }, 2861 { 0x07, 0x0000, 0x2000 }, 2862 { 0x00, 0x0000, 0x0020 }, 2863 { 0x03, 0x5800, 0x2000 }, 2864 { 0x03, 0x0000, 0x0001 }, 2865 { 0x01, 0x0800, 0x1000 }, 2866 { 0x07, 0x0000, 0x4000 }, 2867 { 0x1e, 0x0000, 0x2000 }, 2868 { 0x19, 0xffff, 0xfe6c }, 2869 { 0x0a, 0x0000, 0x0040 } 2870 }; 2871 2872 rtl_set_def_aspm_entry_latency(tp); 2873 2874 rtl_ephy_init(tp, e_info_8168e_1); 2875 2876 rtl_disable_clock_request(tp); 2877 2878 /* Reset tx FIFO pointer */ 2879 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2880 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2881 2882 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2883 } 2884 2885 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2886 { 2887 static const struct ephy_info e_info_8168e_2[] = { 2888 { 0x09, 0x0000, 0x0080 }, 2889 { 0x19, 0x0000, 0x0224 }, 2890 { 0x00, 0x0000, 0x0004 }, 2891 { 0x0c, 0x3df0, 0x0200 }, 2892 }; 2893 2894 rtl_set_def_aspm_entry_latency(tp); 2895 2896 rtl_ephy_init(tp, e_info_8168e_2); 2897 2898 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2899 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2900 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2901 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2902 rtl_reset_packet_filter(tp); 2903 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2904 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2905 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2906 2907 rtl_disable_clock_request(tp); 2908 2909 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2910 2911 rtl8168_config_eee_mac(tp); 2912 2913 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2914 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2915 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2916 2917 rtl_hw_aspm_clkreq_enable(tp, true); 2918 } 2919 2920 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2921 { 2922 rtl_set_def_aspm_entry_latency(tp); 2923 2924 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2925 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2926 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2927 rtl_reset_packet_filter(tp); 2928 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2929 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2930 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2931 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2932 2933 rtl_disable_clock_request(tp); 2934 2935 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2936 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2937 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2938 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2939 2940 rtl8168_config_eee_mac(tp); 2941 } 2942 2943 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2944 { 2945 static const struct ephy_info e_info_8168f_1[] = { 2946 { 0x06, 0x00c0, 0x0020 }, 2947 { 0x08, 0x0001, 0x0002 }, 2948 { 0x09, 0x0000, 0x0080 }, 2949 { 0x19, 0x0000, 0x0224 }, 2950 { 0x00, 0x0000, 0x0008 }, 2951 { 0x0c, 0x3df0, 0x0200 }, 2952 }; 2953 2954 rtl_hw_start_8168f(tp); 2955 2956 rtl_ephy_init(tp, e_info_8168f_1); 2957 } 2958 2959 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2960 { 2961 static const struct ephy_info e_info_8168f_1[] = { 2962 { 0x06, 0x00c0, 0x0020 }, 2963 { 0x0f, 0xffff, 0x5200 }, 2964 { 0x19, 0x0000, 0x0224 }, 2965 { 0x00, 0x0000, 0x0008 }, 2966 { 0x0c, 0x3df0, 0x0200 }, 2967 }; 2968 2969 rtl_hw_start_8168f(tp); 2970 rtl_pcie_state_l2l3_disable(tp); 2971 2972 rtl_ephy_init(tp, e_info_8168f_1); 2973 } 2974 2975 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2976 { 2977 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2978 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2979 2980 rtl_set_def_aspm_entry_latency(tp); 2981 2982 rtl_reset_packet_filter(tp); 2983 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2984 2985 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2986 2987 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2988 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2989 2990 rtl8168_config_eee_mac(tp); 2991 2992 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2993 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2994 2995 rtl_pcie_state_l2l3_disable(tp); 2996 } 2997 2998 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2999 { 3000 static const struct ephy_info e_info_8168g_1[] = { 3001 { 0x00, 0x0008, 0x0000 }, 3002 { 0x0c, 0x3ff0, 0x0820 }, 3003 { 0x1e, 0x0000, 0x0001 }, 3004 { 0x19, 0x8000, 0x0000 } 3005 }; 3006 3007 rtl_hw_start_8168g(tp); 3008 3009 /* disable aspm and clock request before access ephy */ 3010 rtl_hw_aspm_clkreq_enable(tp, false); 3011 rtl_ephy_init(tp, e_info_8168g_1); 3012 rtl_hw_aspm_clkreq_enable(tp, true); 3013 } 3014 3015 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3016 { 3017 static const struct ephy_info e_info_8168g_2[] = { 3018 { 0x00, 0x0008, 0x0000 }, 3019 { 0x0c, 0x3ff0, 0x0820 }, 3020 { 0x19, 0xffff, 0x7c00 }, 3021 { 0x1e, 0xffff, 0x20eb }, 3022 { 0x0d, 0xffff, 0x1666 }, 3023 { 0x00, 0xffff, 0x10a3 }, 3024 { 0x06, 0xffff, 0xf050 }, 3025 { 0x04, 0x0000, 0x0010 }, 3026 { 0x1d, 0x4000, 0x0000 }, 3027 }; 3028 3029 rtl_hw_start_8168g(tp); 3030 3031 /* disable aspm and clock request before access ephy */ 3032 rtl_hw_aspm_clkreq_enable(tp, false); 3033 rtl_ephy_init(tp, e_info_8168g_2); 3034 } 3035 3036 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3037 { 3038 static const struct ephy_info e_info_8411_2[] = { 3039 { 0x00, 0x0008, 0x0000 }, 3040 { 0x0c, 0x37d0, 0x0820 }, 3041 { 0x1e, 0x0000, 0x0001 }, 3042 { 0x19, 0x8021, 0x0000 }, 3043 { 0x1e, 0x0000, 0x2000 }, 3044 { 0x0d, 0x0100, 0x0200 }, 3045 { 0x00, 0x0000, 0x0080 }, 3046 { 0x06, 0x0000, 0x0010 }, 3047 { 0x04, 0x0000, 0x0010 }, 3048 { 0x1d, 0x0000, 0x4000 }, 3049 }; 3050 3051 rtl_hw_start_8168g(tp); 3052 3053 /* disable aspm and clock request before access ephy */ 3054 rtl_hw_aspm_clkreq_enable(tp, false); 3055 rtl_ephy_init(tp, e_info_8411_2); 3056 3057 /* The following Realtek-provided magic fixes an issue with the RX unit 3058 * getting confused after the PHY having been powered-down. 3059 */ 3060 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3061 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3062 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3063 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3064 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3065 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3066 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3067 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3068 mdelay(3); 3069 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3070 3071 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3072 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3073 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3074 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3075 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3076 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3077 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3078 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3079 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3080 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3081 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3082 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3083 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3084 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3085 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3086 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3087 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3088 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3089 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3090 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3091 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3092 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3093 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3094 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3095 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3096 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3097 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3098 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3099 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3100 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3101 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3102 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3103 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3104 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3105 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3106 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3107 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3108 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3109 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3110 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3111 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3112 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3113 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3114 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3115 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3116 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3117 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3118 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3119 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3120 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3121 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3122 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3123 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3124 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3125 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3126 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3127 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3128 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3129 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3130 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3131 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3132 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3133 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3134 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3135 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3136 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3137 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3138 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3139 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3140 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3141 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3142 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3143 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3144 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3145 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3146 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3147 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3148 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3149 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3150 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3151 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3152 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3153 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3154 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3155 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3156 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3157 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3158 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3159 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3160 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3161 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3162 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3163 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3164 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3165 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3166 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3167 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3168 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3169 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3170 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3171 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3172 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3173 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3174 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3175 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3176 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3177 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3178 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3179 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3180 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3181 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3182 3183 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3184 3185 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3186 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3187 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3188 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3189 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3190 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3191 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3192 3193 rtl_hw_aspm_clkreq_enable(tp, true); 3194 } 3195 3196 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3197 { 3198 static const struct ephy_info e_info_8168h_1[] = { 3199 { 0x1e, 0x0800, 0x0001 }, 3200 { 0x1d, 0x0000, 0x0800 }, 3201 { 0x05, 0xffff, 0x2089 }, 3202 { 0x06, 0xffff, 0x5881 }, 3203 { 0x04, 0xffff, 0x854a }, 3204 { 0x01, 0xffff, 0x068b } 3205 }; 3206 int rg_saw_cnt; 3207 3208 /* disable aspm and clock request before access ephy */ 3209 rtl_hw_aspm_clkreq_enable(tp, false); 3210 rtl_ephy_init(tp, e_info_8168h_1); 3211 3212 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3213 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3214 3215 rtl_set_def_aspm_entry_latency(tp); 3216 3217 rtl_reset_packet_filter(tp); 3218 3219 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3220 3221 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3222 3223 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3224 3225 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3226 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3227 3228 rtl8168_config_eee_mac(tp); 3229 3230 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3231 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3232 3233 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3234 3235 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3236 3237 rtl_pcie_state_l2l3_disable(tp); 3238 3239 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3240 if (rg_saw_cnt > 0) { 3241 u16 sw_cnt_1ms_ini; 3242 3243 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3244 sw_cnt_1ms_ini &= 0x0fff; 3245 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3246 } 3247 3248 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3249 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3250 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3251 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3252 3253 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3254 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3255 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3256 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3257 3258 rtl_hw_aspm_clkreq_enable(tp, true); 3259 } 3260 3261 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3262 { 3263 rtl8168ep_stop_cmac(tp); 3264 3265 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3266 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3267 3268 rtl_set_def_aspm_entry_latency(tp); 3269 3270 rtl_reset_packet_filter(tp); 3271 3272 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3273 3274 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3275 3276 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3277 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3278 3279 rtl8168_config_eee_mac(tp); 3280 3281 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3282 3283 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3284 3285 rtl_pcie_state_l2l3_disable(tp); 3286 } 3287 3288 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3289 { 3290 static const struct ephy_info e_info_8168ep_1[] = { 3291 { 0x00, 0xffff, 0x10ab }, 3292 { 0x06, 0xffff, 0xf030 }, 3293 { 0x08, 0xffff, 0x2006 }, 3294 { 0x0d, 0xffff, 0x1666 }, 3295 { 0x0c, 0x3ff0, 0x0000 } 3296 }; 3297 3298 /* disable aspm and clock request before access ephy */ 3299 rtl_hw_aspm_clkreq_enable(tp, false); 3300 rtl_ephy_init(tp, e_info_8168ep_1); 3301 3302 rtl_hw_start_8168ep(tp); 3303 3304 rtl_hw_aspm_clkreq_enable(tp, true); 3305 } 3306 3307 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3308 { 3309 static const struct ephy_info e_info_8168ep_2[] = { 3310 { 0x00, 0xffff, 0x10a3 }, 3311 { 0x19, 0xffff, 0xfc00 }, 3312 { 0x1e, 0xffff, 0x20ea } 3313 }; 3314 3315 /* disable aspm and clock request before access ephy */ 3316 rtl_hw_aspm_clkreq_enable(tp, false); 3317 rtl_ephy_init(tp, e_info_8168ep_2); 3318 3319 rtl_hw_start_8168ep(tp); 3320 3321 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3322 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3323 3324 rtl_hw_aspm_clkreq_enable(tp, true); 3325 } 3326 3327 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3328 { 3329 static const struct ephy_info e_info_8168ep_3[] = { 3330 { 0x00, 0x0000, 0x0080 }, 3331 { 0x0d, 0x0100, 0x0200 }, 3332 { 0x19, 0x8021, 0x0000 }, 3333 { 0x1e, 0x0000, 0x2000 }, 3334 }; 3335 3336 /* disable aspm and clock request before access ephy */ 3337 rtl_hw_aspm_clkreq_enable(tp, false); 3338 rtl_ephy_init(tp, e_info_8168ep_3); 3339 3340 rtl_hw_start_8168ep(tp); 3341 3342 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3343 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3344 3345 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3346 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3347 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3348 3349 rtl_hw_aspm_clkreq_enable(tp, true); 3350 } 3351 3352 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3353 { 3354 static const struct ephy_info e_info_8117[] = { 3355 { 0x19, 0x0040, 0x1100 }, 3356 { 0x59, 0x0040, 0x1100 }, 3357 }; 3358 int rg_saw_cnt; 3359 3360 rtl8168ep_stop_cmac(tp); 3361 3362 /* disable aspm and clock request before access ephy */ 3363 rtl_hw_aspm_clkreq_enable(tp, false); 3364 rtl_ephy_init(tp, e_info_8117); 3365 3366 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3367 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3368 3369 rtl_set_def_aspm_entry_latency(tp); 3370 3371 rtl_reset_packet_filter(tp); 3372 3373 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3374 3375 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3376 3377 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3378 3379 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3380 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3381 3382 rtl8168_config_eee_mac(tp); 3383 3384 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3385 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3386 3387 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3388 3389 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3390 3391 rtl_pcie_state_l2l3_disable(tp); 3392 3393 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3394 if (rg_saw_cnt > 0) { 3395 u16 sw_cnt_1ms_ini; 3396 3397 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3398 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3399 } 3400 3401 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3402 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3403 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3404 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3405 3406 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3407 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3408 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3409 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3410 3411 /* firmware is for MAC only */ 3412 r8169_apply_firmware(tp); 3413 3414 rtl_hw_aspm_clkreq_enable(tp, true); 3415 } 3416 3417 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3418 { 3419 static const struct ephy_info e_info_8102e_1[] = { 3420 { 0x01, 0, 0x6e65 }, 3421 { 0x02, 0, 0x091f }, 3422 { 0x03, 0, 0xc2f9 }, 3423 { 0x06, 0, 0xafb5 }, 3424 { 0x07, 0, 0x0e00 }, 3425 { 0x19, 0, 0xec80 }, 3426 { 0x01, 0, 0x2e65 }, 3427 { 0x01, 0, 0x6e65 } 3428 }; 3429 u8 cfg1; 3430 3431 rtl_set_def_aspm_entry_latency(tp); 3432 3433 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3434 3435 RTL_W8(tp, Config1, 3436 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3437 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3438 3439 cfg1 = RTL_R8(tp, Config1); 3440 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3441 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3442 3443 rtl_ephy_init(tp, e_info_8102e_1); 3444 } 3445 3446 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3447 { 3448 rtl_set_def_aspm_entry_latency(tp); 3449 3450 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3451 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3452 } 3453 3454 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3455 { 3456 rtl_hw_start_8102e_2(tp); 3457 3458 rtl_ephy_write(tp, 0x03, 0xc2f9); 3459 } 3460 3461 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3462 { 3463 static const struct ephy_info e_info_8401[] = { 3464 { 0x01, 0xffff, 0x6fe5 }, 3465 { 0x03, 0xffff, 0x0599 }, 3466 { 0x06, 0xffff, 0xaf25 }, 3467 { 0x07, 0xffff, 0x8e68 }, 3468 }; 3469 3470 rtl_ephy_init(tp, e_info_8401); 3471 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3472 } 3473 3474 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3475 { 3476 static const struct ephy_info e_info_8105e_1[] = { 3477 { 0x07, 0, 0x4000 }, 3478 { 0x19, 0, 0x0200 }, 3479 { 0x19, 0, 0x0020 }, 3480 { 0x1e, 0, 0x2000 }, 3481 { 0x03, 0, 0x0001 }, 3482 { 0x19, 0, 0x0100 }, 3483 { 0x19, 0, 0x0004 }, 3484 { 0x0a, 0, 0x0020 } 3485 }; 3486 3487 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3488 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3489 3490 /* Disable Early Tally Counter */ 3491 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3492 3493 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3494 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3495 3496 rtl_ephy_init(tp, e_info_8105e_1); 3497 3498 rtl_pcie_state_l2l3_disable(tp); 3499 } 3500 3501 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3502 { 3503 rtl_hw_start_8105e_1(tp); 3504 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3505 } 3506 3507 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3508 { 3509 static const struct ephy_info e_info_8402[] = { 3510 { 0x19, 0xffff, 0xff64 }, 3511 { 0x1e, 0, 0x4000 } 3512 }; 3513 3514 rtl_set_def_aspm_entry_latency(tp); 3515 3516 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3517 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3518 3519 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3520 3521 rtl_ephy_init(tp, e_info_8402); 3522 3523 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3524 rtl_reset_packet_filter(tp); 3525 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3526 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3527 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3528 3529 /* disable EEE */ 3530 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3531 3532 rtl_pcie_state_l2l3_disable(tp); 3533 } 3534 3535 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3536 { 3537 rtl_hw_aspm_clkreq_enable(tp, false); 3538 3539 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3540 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3541 3542 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3543 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3544 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3545 3546 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3547 rtl_set_aspm_entry_latency(tp, 0x2f); 3548 3549 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3550 3551 /* disable EEE */ 3552 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3553 3554 rtl_pcie_state_l2l3_disable(tp); 3555 rtl_hw_aspm_clkreq_enable(tp, true); 3556 } 3557 3558 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3559 { 3560 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3561 } 3562 3563 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3564 { 3565 rtl_pcie_state_l2l3_disable(tp); 3566 3567 RTL_W16(tp, 0x382, 0x221b); 3568 RTL_W8(tp, 0x4500, 0); 3569 RTL_W16(tp, 0x4800, 0); 3570 3571 /* disable UPS */ 3572 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3573 3574 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3575 3576 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3577 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3578 3579 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3580 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3581 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3582 3583 /* disable new tx descriptor format */ 3584 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3585 3586 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3587 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3588 else 3589 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3590 3591 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3592 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3593 else 3594 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3595 3596 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3597 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3598 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3599 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3600 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3601 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3602 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3603 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3604 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3605 3606 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3607 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3608 udelay(1); 3609 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3610 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3611 3612 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3613 3614 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3615 3616 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3617 rtl8125b_config_eee_mac(tp); 3618 else 3619 rtl8125a_config_eee_mac(tp); 3620 3621 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3622 udelay(10); 3623 } 3624 3625 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) 3626 { 3627 static const struct ephy_info e_info_8125a_1[] = { 3628 { 0x01, 0xffff, 0xa812 }, 3629 { 0x09, 0xffff, 0x520c }, 3630 { 0x04, 0xffff, 0xd000 }, 3631 { 0x0d, 0xffff, 0xf702 }, 3632 { 0x0a, 0xffff, 0x8653 }, 3633 { 0x06, 0xffff, 0x001e }, 3634 { 0x08, 0xffff, 0x3595 }, 3635 { 0x20, 0xffff, 0x9455 }, 3636 { 0x21, 0xffff, 0x99ff }, 3637 { 0x02, 0xffff, 0x6046 }, 3638 { 0x29, 0xffff, 0xfe00 }, 3639 { 0x23, 0xffff, 0xab62 }, 3640 3641 { 0x41, 0xffff, 0xa80c }, 3642 { 0x49, 0xffff, 0x520c }, 3643 { 0x44, 0xffff, 0xd000 }, 3644 { 0x4d, 0xffff, 0xf702 }, 3645 { 0x4a, 0xffff, 0x8653 }, 3646 { 0x46, 0xffff, 0x001e }, 3647 { 0x48, 0xffff, 0x3595 }, 3648 { 0x60, 0xffff, 0x9455 }, 3649 { 0x61, 0xffff, 0x99ff }, 3650 { 0x42, 0xffff, 0x6046 }, 3651 { 0x69, 0xffff, 0xfe00 }, 3652 { 0x63, 0xffff, 0xab62 }, 3653 }; 3654 3655 rtl_set_def_aspm_entry_latency(tp); 3656 3657 /* disable aspm and clock request before access ephy */ 3658 rtl_hw_aspm_clkreq_enable(tp, false); 3659 rtl_ephy_init(tp, e_info_8125a_1); 3660 3661 rtl_hw_start_8125_common(tp); 3662 rtl_hw_aspm_clkreq_enable(tp, true); 3663 } 3664 3665 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3666 { 3667 static const struct ephy_info e_info_8125a_2[] = { 3668 { 0x04, 0xffff, 0xd000 }, 3669 { 0x0a, 0xffff, 0x8653 }, 3670 { 0x23, 0xffff, 0xab66 }, 3671 { 0x20, 0xffff, 0x9455 }, 3672 { 0x21, 0xffff, 0x99ff }, 3673 { 0x29, 0xffff, 0xfe04 }, 3674 3675 { 0x44, 0xffff, 0xd000 }, 3676 { 0x4a, 0xffff, 0x8653 }, 3677 { 0x63, 0xffff, 0xab66 }, 3678 { 0x60, 0xffff, 0x9455 }, 3679 { 0x61, 0xffff, 0x99ff }, 3680 { 0x69, 0xffff, 0xfe04 }, 3681 }; 3682 3683 rtl_set_def_aspm_entry_latency(tp); 3684 3685 /* disable aspm and clock request before access ephy */ 3686 rtl_hw_aspm_clkreq_enable(tp, false); 3687 rtl_ephy_init(tp, e_info_8125a_2); 3688 3689 rtl_hw_start_8125_common(tp); 3690 rtl_hw_aspm_clkreq_enable(tp, true); 3691 } 3692 3693 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3694 { 3695 static const struct ephy_info e_info_8125b[] = { 3696 { 0x0b, 0xffff, 0xa908 }, 3697 { 0x1e, 0xffff, 0x20eb }, 3698 { 0x4b, 0xffff, 0xa908 }, 3699 { 0x5e, 0xffff, 0x20eb }, 3700 { 0x22, 0x0030, 0x0020 }, 3701 { 0x62, 0x0030, 0x0020 }, 3702 }; 3703 3704 rtl_set_def_aspm_entry_latency(tp); 3705 rtl_hw_aspm_clkreq_enable(tp, false); 3706 3707 rtl_ephy_init(tp, e_info_8125b); 3708 rtl_hw_start_8125_common(tp); 3709 3710 rtl_hw_aspm_clkreq_enable(tp, true); 3711 } 3712 3713 static void rtl_hw_config(struct rtl8169_private *tp) 3714 { 3715 static const rtl_generic_fct hw_configs[] = { 3716 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3717 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3718 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3719 [RTL_GIGA_MAC_VER_10] = NULL, 3720 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3721 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3722 [RTL_GIGA_MAC_VER_13] = NULL, 3723 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3724 [RTL_GIGA_MAC_VER_16] = NULL, 3725 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3726 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3727 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3728 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3729 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3730 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3731 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3732 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3733 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3734 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3735 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3736 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3737 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3738 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3739 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3740 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3741 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3742 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3743 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3744 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3745 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3746 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3747 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3748 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3749 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3750 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3751 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3752 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3753 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3754 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3755 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3756 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3757 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3758 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3759 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3760 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3761 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, 3762 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3763 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3764 }; 3765 3766 if (hw_configs[tp->mac_version]) 3767 hw_configs[tp->mac_version](tp); 3768 } 3769 3770 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3771 { 3772 int i; 3773 3774 /* disable interrupt coalescing */ 3775 for (i = 0xa00; i < 0xb00; i += 4) 3776 RTL_W32(tp, i, 0); 3777 3778 rtl_hw_config(tp); 3779 } 3780 3781 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3782 { 3783 if (rtl_is_8168evl_up(tp)) 3784 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3785 else 3786 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3787 3788 rtl_hw_config(tp); 3789 3790 /* disable interrupt coalescing */ 3791 RTL_W16(tp, IntrMitigate, 0x0000); 3792 } 3793 3794 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3795 { 3796 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3797 3798 tp->cp_cmd |= PCIMulRW; 3799 3800 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3801 tp->mac_version == RTL_GIGA_MAC_VER_03) 3802 tp->cp_cmd |= EnAnaPLL; 3803 3804 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3805 3806 rtl8169_set_magic_reg(tp); 3807 3808 /* disable interrupt coalescing */ 3809 RTL_W16(tp, IntrMitigate, 0x0000); 3810 } 3811 3812 static void rtl_hw_start(struct rtl8169_private *tp) 3813 { 3814 rtl_unlock_config_regs(tp); 3815 3816 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3817 3818 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3819 rtl_hw_start_8169(tp); 3820 else if (rtl_is_8125(tp)) 3821 rtl_hw_start_8125(tp); 3822 else 3823 rtl_hw_start_8168(tp); 3824 3825 rtl_enable_exit_l1(tp); 3826 rtl_set_rx_max_size(tp); 3827 rtl_set_rx_tx_desc_registers(tp); 3828 rtl_lock_config_regs(tp); 3829 3830 rtl_jumbo_config(tp); 3831 3832 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3833 rtl_pci_commit(tp); 3834 3835 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3836 rtl_init_rxcfg(tp); 3837 rtl_set_tx_config_registers(tp); 3838 rtl_set_rx_config_features(tp, tp->dev->features); 3839 rtl_set_rx_mode(tp->dev); 3840 rtl_irq_enable(tp); 3841 } 3842 3843 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3844 { 3845 struct rtl8169_private *tp = netdev_priv(dev); 3846 3847 dev->mtu = new_mtu; 3848 netdev_update_features(dev); 3849 rtl_jumbo_config(tp); 3850 3851 switch (tp->mac_version) { 3852 case RTL_GIGA_MAC_VER_61: 3853 case RTL_GIGA_MAC_VER_63: 3854 rtl8125_set_eee_txidle_timer(tp); 3855 break; 3856 default: 3857 break; 3858 } 3859 3860 return 0; 3861 } 3862 3863 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3864 { 3865 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3866 3867 desc->opts2 = 0; 3868 /* Force memory writes to complete before releasing descriptor */ 3869 dma_wmb(); 3870 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3871 } 3872 3873 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3874 struct RxDesc *desc) 3875 { 3876 struct device *d = tp_to_dev(tp); 3877 int node = dev_to_node(d); 3878 dma_addr_t mapping; 3879 struct page *data; 3880 3881 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3882 if (!data) 3883 return NULL; 3884 3885 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3886 if (unlikely(dma_mapping_error(d, mapping))) { 3887 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3888 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3889 return NULL; 3890 } 3891 3892 desc->addr = cpu_to_le64(mapping); 3893 rtl8169_mark_to_asic(desc); 3894 3895 return data; 3896 } 3897 3898 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3899 { 3900 int i; 3901 3902 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3903 dma_unmap_page(tp_to_dev(tp), 3904 le64_to_cpu(tp->RxDescArray[i].addr), 3905 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3906 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3907 tp->Rx_databuff[i] = NULL; 3908 tp->RxDescArray[i].addr = 0; 3909 tp->RxDescArray[i].opts1 = 0; 3910 } 3911 } 3912 3913 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3914 { 3915 int i; 3916 3917 for (i = 0; i < NUM_RX_DESC; i++) { 3918 struct page *data; 3919 3920 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3921 if (!data) { 3922 rtl8169_rx_clear(tp); 3923 return -ENOMEM; 3924 } 3925 tp->Rx_databuff[i] = data; 3926 } 3927 3928 /* mark as last descriptor in the ring */ 3929 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3930 3931 return 0; 3932 } 3933 3934 static int rtl8169_init_ring(struct rtl8169_private *tp) 3935 { 3936 rtl8169_init_ring_indexes(tp); 3937 3938 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3939 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3940 3941 return rtl8169_rx_fill(tp); 3942 } 3943 3944 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3945 { 3946 struct ring_info *tx_skb = tp->tx_skb + entry; 3947 struct TxDesc *desc = tp->TxDescArray + entry; 3948 3949 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3950 DMA_TO_DEVICE); 3951 memset(desc, 0, sizeof(*desc)); 3952 memset(tx_skb, 0, sizeof(*tx_skb)); 3953 } 3954 3955 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3956 unsigned int n) 3957 { 3958 unsigned int i; 3959 3960 for (i = 0; i < n; i++) { 3961 unsigned int entry = (start + i) % NUM_TX_DESC; 3962 struct ring_info *tx_skb = tp->tx_skb + entry; 3963 unsigned int len = tx_skb->len; 3964 3965 if (len) { 3966 struct sk_buff *skb = tx_skb->skb; 3967 3968 rtl8169_unmap_tx_skb(tp, entry); 3969 if (skb) 3970 dev_consume_skb_any(skb); 3971 } 3972 } 3973 } 3974 3975 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3976 { 3977 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3978 netdev_reset_queue(tp->dev); 3979 } 3980 3981 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3982 { 3983 napi_disable(&tp->napi); 3984 3985 /* Give a racing hard_start_xmit a few cycles to complete. */ 3986 synchronize_net(); 3987 3988 /* Disable interrupts */ 3989 rtl8169_irq_mask_and_ack(tp); 3990 3991 rtl_rx_close(tp); 3992 3993 if (going_down && tp->dev->wol_enabled) 3994 goto no_reset; 3995 3996 switch (tp->mac_version) { 3997 case RTL_GIGA_MAC_VER_28: 3998 case RTL_GIGA_MAC_VER_31: 3999 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4000 break; 4001 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4002 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4003 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4004 break; 4005 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 4006 rtl_enable_rxdvgate(tp); 4007 fsleep(2000); 4008 break; 4009 default: 4010 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4011 fsleep(100); 4012 break; 4013 } 4014 4015 rtl_hw_reset(tp); 4016 no_reset: 4017 rtl8169_tx_clear(tp); 4018 rtl8169_init_ring_indexes(tp); 4019 } 4020 4021 static void rtl_reset_work(struct rtl8169_private *tp) 4022 { 4023 int i; 4024 4025 netif_stop_queue(tp->dev); 4026 4027 rtl8169_cleanup(tp, false); 4028 4029 for (i = 0; i < NUM_RX_DESC; i++) 4030 rtl8169_mark_to_asic(tp->RxDescArray + i); 4031 4032 napi_enable(&tp->napi); 4033 rtl_hw_start(tp); 4034 } 4035 4036 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4037 { 4038 struct rtl8169_private *tp = netdev_priv(dev); 4039 4040 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4041 } 4042 4043 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4044 void *addr, unsigned int entry, bool desc_own) 4045 { 4046 struct TxDesc *txd = tp->TxDescArray + entry; 4047 struct device *d = tp_to_dev(tp); 4048 dma_addr_t mapping; 4049 u32 opts1; 4050 int ret; 4051 4052 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4053 ret = dma_mapping_error(d, mapping); 4054 if (unlikely(ret)) { 4055 if (net_ratelimit()) 4056 netdev_err(tp->dev, "Failed to map TX data!\n"); 4057 return ret; 4058 } 4059 4060 txd->addr = cpu_to_le64(mapping); 4061 txd->opts2 = cpu_to_le32(opts[1]); 4062 4063 opts1 = opts[0] | len; 4064 if (entry == NUM_TX_DESC - 1) 4065 opts1 |= RingEnd; 4066 if (desc_own) 4067 opts1 |= DescOwn; 4068 txd->opts1 = cpu_to_le32(opts1); 4069 4070 tp->tx_skb[entry].len = len; 4071 4072 return 0; 4073 } 4074 4075 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4076 const u32 *opts, unsigned int entry) 4077 { 4078 struct skb_shared_info *info = skb_shinfo(skb); 4079 unsigned int cur_frag; 4080 4081 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4082 const skb_frag_t *frag = info->frags + cur_frag; 4083 void *addr = skb_frag_address(frag); 4084 u32 len = skb_frag_size(frag); 4085 4086 entry = (entry + 1) % NUM_TX_DESC; 4087 4088 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4089 goto err_out; 4090 } 4091 4092 return 0; 4093 4094 err_out: 4095 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4096 return -EIO; 4097 } 4098 4099 static bool rtl_skb_is_udp(struct sk_buff *skb) 4100 { 4101 int no = skb_network_offset(skb); 4102 struct ipv6hdr *i6h, _i6h; 4103 struct iphdr *ih, _ih; 4104 4105 switch (vlan_get_protocol(skb)) { 4106 case htons(ETH_P_IP): 4107 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4108 return ih && ih->protocol == IPPROTO_UDP; 4109 case htons(ETH_P_IPV6): 4110 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4111 return i6h && i6h->nexthdr == IPPROTO_UDP; 4112 default: 4113 return false; 4114 } 4115 } 4116 4117 #define RTL_MIN_PATCH_LEN 47 4118 4119 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4120 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4121 struct sk_buff *skb) 4122 { 4123 unsigned int padto = 0, len = skb->len; 4124 4125 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4126 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4127 unsigned int trans_data_len = skb_tail_pointer(skb) - 4128 skb_transport_header(skb); 4129 4130 if (trans_data_len >= offsetof(struct udphdr, len) && 4131 trans_data_len < RTL_MIN_PATCH_LEN) { 4132 u16 dest = ntohs(udp_hdr(skb)->dest); 4133 4134 /* dest is a standard PTP port */ 4135 if (dest == 319 || dest == 320) 4136 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4137 } 4138 4139 if (trans_data_len < sizeof(struct udphdr)) 4140 padto = max_t(unsigned int, padto, 4141 len + sizeof(struct udphdr) - trans_data_len); 4142 } 4143 4144 return padto; 4145 } 4146 4147 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4148 struct sk_buff *skb) 4149 { 4150 unsigned int padto; 4151 4152 padto = rtl8125_quirk_udp_padto(tp, skb); 4153 4154 switch (tp->mac_version) { 4155 case RTL_GIGA_MAC_VER_34: 4156 case RTL_GIGA_MAC_VER_60: 4157 case RTL_GIGA_MAC_VER_61: 4158 case RTL_GIGA_MAC_VER_63: 4159 padto = max_t(unsigned int, padto, ETH_ZLEN); 4160 break; 4161 default: 4162 break; 4163 } 4164 4165 return padto; 4166 } 4167 4168 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4169 { 4170 u32 mss = skb_shinfo(skb)->gso_size; 4171 4172 if (mss) { 4173 opts[0] |= TD_LSO; 4174 opts[0] |= mss << TD0_MSS_SHIFT; 4175 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4176 const struct iphdr *ip = ip_hdr(skb); 4177 4178 if (ip->protocol == IPPROTO_TCP) 4179 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4180 else if (ip->protocol == IPPROTO_UDP) 4181 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4182 else 4183 WARN_ON_ONCE(1); 4184 } 4185 } 4186 4187 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4188 struct sk_buff *skb, u32 *opts) 4189 { 4190 u32 transport_offset = (u32)skb_transport_offset(skb); 4191 struct skb_shared_info *shinfo = skb_shinfo(skb); 4192 u32 mss = shinfo->gso_size; 4193 4194 if (mss) { 4195 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4196 opts[0] |= TD1_GTSENV4; 4197 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4198 if (skb_cow_head(skb, 0)) 4199 return false; 4200 4201 tcp_v6_gso_csum_prep(skb); 4202 opts[0] |= TD1_GTSENV6; 4203 } else { 4204 WARN_ON_ONCE(1); 4205 } 4206 4207 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4208 opts[1] |= mss << TD1_MSS_SHIFT; 4209 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4210 u8 ip_protocol; 4211 4212 switch (vlan_get_protocol(skb)) { 4213 case htons(ETH_P_IP): 4214 opts[1] |= TD1_IPv4_CS; 4215 ip_protocol = ip_hdr(skb)->protocol; 4216 break; 4217 4218 case htons(ETH_P_IPV6): 4219 opts[1] |= TD1_IPv6_CS; 4220 ip_protocol = ipv6_hdr(skb)->nexthdr; 4221 break; 4222 4223 default: 4224 ip_protocol = IPPROTO_RAW; 4225 break; 4226 } 4227 4228 if (ip_protocol == IPPROTO_TCP) 4229 opts[1] |= TD1_TCP_CS; 4230 else if (ip_protocol == IPPROTO_UDP) 4231 opts[1] |= TD1_UDP_CS; 4232 else 4233 WARN_ON_ONCE(1); 4234 4235 opts[1] |= transport_offset << TCPHO_SHIFT; 4236 } else { 4237 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4238 4239 /* skb_padto would free the skb on error */ 4240 return !__skb_put_padto(skb, padto, false); 4241 } 4242 4243 return true; 4244 } 4245 4246 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4247 { 4248 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4249 - READ_ONCE(tp->cur_tx); 4250 4251 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4252 return slots_avail > MAX_SKB_FRAGS; 4253 } 4254 4255 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4256 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4257 { 4258 switch (tp->mac_version) { 4259 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4260 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4261 return false; 4262 default: 4263 return true; 4264 } 4265 } 4266 4267 static void rtl8169_doorbell(struct rtl8169_private *tp) 4268 { 4269 if (rtl_is_8125(tp)) 4270 RTL_W16(tp, TxPoll_8125, BIT(0)); 4271 else 4272 RTL_W8(tp, TxPoll, NPQ); 4273 } 4274 4275 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4276 struct net_device *dev) 4277 { 4278 unsigned int frags = skb_shinfo(skb)->nr_frags; 4279 struct rtl8169_private *tp = netdev_priv(dev); 4280 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4281 struct TxDesc *txd_first, *txd_last; 4282 bool stop_queue, door_bell; 4283 u32 opts[2]; 4284 4285 if (unlikely(!rtl_tx_slots_avail(tp))) { 4286 if (net_ratelimit()) 4287 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4288 goto err_stop_0; 4289 } 4290 4291 opts[1] = rtl8169_tx_vlan_tag(skb); 4292 opts[0] = 0; 4293 4294 if (!rtl_chip_supports_csum_v2(tp)) 4295 rtl8169_tso_csum_v1(skb, opts); 4296 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4297 goto err_dma_0; 4298 4299 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4300 entry, false))) 4301 goto err_dma_0; 4302 4303 txd_first = tp->TxDescArray + entry; 4304 4305 if (frags) { 4306 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4307 goto err_dma_1; 4308 entry = (entry + frags) % NUM_TX_DESC; 4309 } 4310 4311 txd_last = tp->TxDescArray + entry; 4312 txd_last->opts1 |= cpu_to_le32(LastFrag); 4313 tp->tx_skb[entry].skb = skb; 4314 4315 skb_tx_timestamp(skb); 4316 4317 /* Force memory writes to complete before releasing descriptor */ 4318 dma_wmb(); 4319 4320 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4321 4322 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4323 4324 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4325 smp_wmb(); 4326 4327 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4328 4329 stop_queue = !rtl_tx_slots_avail(tp); 4330 if (unlikely(stop_queue)) { 4331 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4332 * not miss a ring update when it notices a stopped queue. 4333 */ 4334 smp_wmb(); 4335 netif_stop_queue(dev); 4336 /* Sync with rtl_tx: 4337 * - publish queue status and cur_tx ring index (write barrier) 4338 * - refresh dirty_tx ring index (read barrier). 4339 * May the current thread have a pessimistic view of the ring 4340 * status and forget to wake up queue, a racing rtl_tx thread 4341 * can't. 4342 */ 4343 smp_mb__after_atomic(); 4344 if (rtl_tx_slots_avail(tp)) 4345 netif_start_queue(dev); 4346 door_bell = true; 4347 } 4348 4349 if (door_bell) 4350 rtl8169_doorbell(tp); 4351 4352 return NETDEV_TX_OK; 4353 4354 err_dma_1: 4355 rtl8169_unmap_tx_skb(tp, entry); 4356 err_dma_0: 4357 dev_kfree_skb_any(skb); 4358 dev->stats.tx_dropped++; 4359 return NETDEV_TX_OK; 4360 4361 err_stop_0: 4362 netif_stop_queue(dev); 4363 dev->stats.tx_dropped++; 4364 return NETDEV_TX_BUSY; 4365 } 4366 4367 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4368 { 4369 struct skb_shared_info *info = skb_shinfo(skb); 4370 unsigned int nr_frags = info->nr_frags; 4371 4372 if (!nr_frags) 4373 return UINT_MAX; 4374 4375 return skb_frag_size(info->frags + nr_frags - 1); 4376 } 4377 4378 /* Workaround for hw issues with TSO on RTL8168evl */ 4379 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4380 netdev_features_t features) 4381 { 4382 /* IPv4 header has options field */ 4383 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4384 ip_hdrlen(skb) > sizeof(struct iphdr)) 4385 features &= ~NETIF_F_ALL_TSO; 4386 4387 /* IPv4 TCP header has options field */ 4388 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4389 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4390 features &= ~NETIF_F_ALL_TSO; 4391 4392 else if (rtl_last_frag_len(skb) <= 6) 4393 features &= ~NETIF_F_ALL_TSO; 4394 4395 return features; 4396 } 4397 4398 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4399 struct net_device *dev, 4400 netdev_features_t features) 4401 { 4402 int transport_offset = skb_transport_offset(skb); 4403 struct rtl8169_private *tp = netdev_priv(dev); 4404 4405 if (skb_is_gso(skb)) { 4406 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4407 features = rtl8168evl_fix_tso(skb, features); 4408 4409 if (transport_offset > GTTCPHO_MAX && 4410 rtl_chip_supports_csum_v2(tp)) 4411 features &= ~NETIF_F_ALL_TSO; 4412 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4413 /* work around hw bug on some chip versions */ 4414 if (skb->len < ETH_ZLEN) 4415 features &= ~NETIF_F_CSUM_MASK; 4416 4417 if (rtl_quirk_packet_padto(tp, skb)) 4418 features &= ~NETIF_F_CSUM_MASK; 4419 4420 if (transport_offset > TCPHO_MAX && 4421 rtl_chip_supports_csum_v2(tp)) 4422 features &= ~NETIF_F_CSUM_MASK; 4423 } 4424 4425 return vlan_features_check(skb, features); 4426 } 4427 4428 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4429 { 4430 struct rtl8169_private *tp = netdev_priv(dev); 4431 struct pci_dev *pdev = tp->pci_dev; 4432 int pci_status_errs; 4433 u16 pci_cmd; 4434 4435 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4436 4437 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4438 4439 if (net_ratelimit()) 4440 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4441 pci_cmd, pci_status_errs); 4442 4443 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4444 } 4445 4446 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4447 int budget) 4448 { 4449 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4450 struct sk_buff *skb; 4451 4452 dirty_tx = tp->dirty_tx; 4453 4454 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4455 unsigned int entry = dirty_tx % NUM_TX_DESC; 4456 u32 status; 4457 4458 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4459 if (status & DescOwn) 4460 break; 4461 4462 skb = tp->tx_skb[entry].skb; 4463 rtl8169_unmap_tx_skb(tp, entry); 4464 4465 if (skb) { 4466 pkts_compl++; 4467 bytes_compl += skb->len; 4468 napi_consume_skb(skb, budget); 4469 } 4470 dirty_tx++; 4471 } 4472 4473 if (tp->dirty_tx != dirty_tx) { 4474 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4475 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4476 4477 /* Sync with rtl8169_start_xmit: 4478 * - publish dirty_tx ring index (write barrier) 4479 * - refresh cur_tx ring index and queue status (read barrier) 4480 * May the current thread miss the stopped queue condition, 4481 * a racing xmit thread can only have a right view of the 4482 * ring status. 4483 */ 4484 smp_store_mb(tp->dirty_tx, dirty_tx); 4485 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4486 netif_wake_queue(dev); 4487 /* 4488 * 8168 hack: TxPoll requests are lost when the Tx packets are 4489 * too close. Let's kick an extra TxPoll request when a burst 4490 * of start_xmit activity is detected (if it is not detected, 4491 * it is slow enough). -- FR 4492 * If skb is NULL then we come here again once a tx irq is 4493 * triggered after the last fragment is marked transmitted. 4494 */ 4495 if (tp->cur_tx != dirty_tx && skb) 4496 rtl8169_doorbell(tp); 4497 } 4498 } 4499 4500 static inline int rtl8169_fragmented_frame(u32 status) 4501 { 4502 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4503 } 4504 4505 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4506 { 4507 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4508 4509 if (status == RxProtoTCP || status == RxProtoUDP) 4510 skb->ip_summed = CHECKSUM_UNNECESSARY; 4511 else 4512 skb_checksum_none_assert(skb); 4513 } 4514 4515 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4516 { 4517 struct device *d = tp_to_dev(tp); 4518 int count; 4519 4520 for (count = 0; count < budget; count++, tp->cur_rx++) { 4521 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4522 struct RxDesc *desc = tp->RxDescArray + entry; 4523 struct sk_buff *skb; 4524 const void *rx_buf; 4525 dma_addr_t addr; 4526 u32 status; 4527 4528 status = le32_to_cpu(desc->opts1); 4529 if (status & DescOwn) 4530 break; 4531 4532 /* This barrier is needed to keep us from reading 4533 * any other fields out of the Rx descriptor until 4534 * we know the status of DescOwn 4535 */ 4536 dma_rmb(); 4537 4538 if (unlikely(status & RxRES)) { 4539 if (net_ratelimit()) 4540 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4541 status); 4542 dev->stats.rx_errors++; 4543 if (status & (RxRWT | RxRUNT)) 4544 dev->stats.rx_length_errors++; 4545 if (status & RxCRC) 4546 dev->stats.rx_crc_errors++; 4547 4548 if (!(dev->features & NETIF_F_RXALL)) 4549 goto release_descriptor; 4550 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4551 goto release_descriptor; 4552 } 4553 4554 pkt_size = status & GENMASK(13, 0); 4555 if (likely(!(dev->features & NETIF_F_RXFCS))) 4556 pkt_size -= ETH_FCS_LEN; 4557 4558 /* The driver does not support incoming fragmented frames. 4559 * They are seen as a symptom of over-mtu sized frames. 4560 */ 4561 if (unlikely(rtl8169_fragmented_frame(status))) { 4562 dev->stats.rx_dropped++; 4563 dev->stats.rx_length_errors++; 4564 goto release_descriptor; 4565 } 4566 4567 skb = napi_alloc_skb(&tp->napi, pkt_size); 4568 if (unlikely(!skb)) { 4569 dev->stats.rx_dropped++; 4570 goto release_descriptor; 4571 } 4572 4573 addr = le64_to_cpu(desc->addr); 4574 rx_buf = page_address(tp->Rx_databuff[entry]); 4575 4576 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4577 prefetch(rx_buf); 4578 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4579 skb->tail += pkt_size; 4580 skb->len = pkt_size; 4581 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4582 4583 rtl8169_rx_csum(skb, status); 4584 skb->protocol = eth_type_trans(skb, dev); 4585 4586 rtl8169_rx_vlan_tag(desc, skb); 4587 4588 if (skb->pkt_type == PACKET_MULTICAST) 4589 dev->stats.multicast++; 4590 4591 napi_gro_receive(&tp->napi, skb); 4592 4593 dev_sw_netstats_rx_add(dev, pkt_size); 4594 release_descriptor: 4595 rtl8169_mark_to_asic(desc); 4596 } 4597 4598 return count; 4599 } 4600 4601 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4602 { 4603 struct rtl8169_private *tp = dev_instance; 4604 u32 status = rtl_get_events(tp); 4605 4606 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4607 return IRQ_NONE; 4608 4609 if (unlikely(status & SYSErr)) { 4610 rtl8169_pcierr_interrupt(tp->dev); 4611 goto out; 4612 } 4613 4614 if (status & LinkChg) 4615 phy_mac_interrupt(tp->phydev); 4616 4617 if (unlikely(status & RxFIFOOver && 4618 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4619 netif_stop_queue(tp->dev); 4620 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4621 } 4622 4623 if (napi_schedule_prep(&tp->napi)) { 4624 rtl_irq_disable(tp); 4625 __napi_schedule(&tp->napi); 4626 } 4627 out: 4628 rtl_ack_events(tp, status); 4629 4630 return IRQ_HANDLED; 4631 } 4632 4633 static void rtl_task(struct work_struct *work) 4634 { 4635 struct rtl8169_private *tp = 4636 container_of(work, struct rtl8169_private, wk.work); 4637 4638 rtnl_lock(); 4639 4640 if (!netif_running(tp->dev) || 4641 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4642 goto out_unlock; 4643 4644 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4645 rtl_reset_work(tp); 4646 netif_wake_queue(tp->dev); 4647 } 4648 out_unlock: 4649 rtnl_unlock(); 4650 } 4651 4652 static int rtl8169_poll(struct napi_struct *napi, int budget) 4653 { 4654 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4655 struct net_device *dev = tp->dev; 4656 int work_done; 4657 4658 rtl_tx(dev, tp, budget); 4659 4660 work_done = rtl_rx(dev, tp, budget); 4661 4662 if (work_done < budget && napi_complete_done(napi, work_done)) 4663 rtl_irq_enable(tp); 4664 4665 return work_done; 4666 } 4667 4668 static void r8169_phylink_handler(struct net_device *ndev) 4669 { 4670 struct rtl8169_private *tp = netdev_priv(ndev); 4671 4672 if (netif_carrier_ok(ndev)) { 4673 rtl_link_chg_patch(tp); 4674 pm_request_resume(&tp->pci_dev->dev); 4675 } else { 4676 pm_runtime_idle(&tp->pci_dev->dev); 4677 } 4678 4679 if (net_ratelimit()) 4680 phy_print_status(tp->phydev); 4681 } 4682 4683 static int r8169_phy_connect(struct rtl8169_private *tp) 4684 { 4685 struct phy_device *phydev = tp->phydev; 4686 phy_interface_t phy_mode; 4687 int ret; 4688 4689 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4690 PHY_INTERFACE_MODE_MII; 4691 4692 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4693 phy_mode); 4694 if (ret) 4695 return ret; 4696 4697 if (!tp->supports_gmii) 4698 phy_set_max_speed(phydev, SPEED_100); 4699 4700 phy_attached_info(phydev); 4701 4702 return 0; 4703 } 4704 4705 static void rtl8169_down(struct rtl8169_private *tp) 4706 { 4707 /* Clear all task flags */ 4708 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4709 4710 phy_stop(tp->phydev); 4711 4712 rtl8169_update_counters(tp); 4713 4714 pci_clear_master(tp->pci_dev); 4715 rtl_pci_commit(tp); 4716 4717 rtl8169_cleanup(tp, true); 4718 rtl_disable_exit_l1(tp); 4719 rtl_prepare_power_down(tp); 4720 } 4721 4722 static void rtl8169_up(struct rtl8169_private *tp) 4723 { 4724 pci_set_master(tp->pci_dev); 4725 phy_init_hw(tp->phydev); 4726 phy_resume(tp->phydev); 4727 rtl8169_init_phy(tp); 4728 napi_enable(&tp->napi); 4729 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4730 rtl_reset_work(tp); 4731 4732 phy_start(tp->phydev); 4733 } 4734 4735 static int rtl8169_close(struct net_device *dev) 4736 { 4737 struct rtl8169_private *tp = netdev_priv(dev); 4738 struct pci_dev *pdev = tp->pci_dev; 4739 4740 pm_runtime_get_sync(&pdev->dev); 4741 4742 netif_stop_queue(dev); 4743 rtl8169_down(tp); 4744 rtl8169_rx_clear(tp); 4745 4746 cancel_work_sync(&tp->wk.work); 4747 4748 free_irq(tp->irq, tp); 4749 4750 phy_disconnect(tp->phydev); 4751 4752 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4753 tp->RxPhyAddr); 4754 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4755 tp->TxPhyAddr); 4756 tp->TxDescArray = NULL; 4757 tp->RxDescArray = NULL; 4758 4759 pm_runtime_put_sync(&pdev->dev); 4760 4761 return 0; 4762 } 4763 4764 #ifdef CONFIG_NET_POLL_CONTROLLER 4765 static void rtl8169_netpoll(struct net_device *dev) 4766 { 4767 struct rtl8169_private *tp = netdev_priv(dev); 4768 4769 rtl8169_interrupt(tp->irq, tp); 4770 } 4771 #endif 4772 4773 static int rtl_open(struct net_device *dev) 4774 { 4775 struct rtl8169_private *tp = netdev_priv(dev); 4776 struct pci_dev *pdev = tp->pci_dev; 4777 unsigned long irqflags; 4778 int retval = -ENOMEM; 4779 4780 pm_runtime_get_sync(&pdev->dev); 4781 4782 /* 4783 * Rx and Tx descriptors needs 256 bytes alignment. 4784 * dma_alloc_coherent provides more. 4785 */ 4786 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4787 &tp->TxPhyAddr, GFP_KERNEL); 4788 if (!tp->TxDescArray) 4789 goto out; 4790 4791 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4792 &tp->RxPhyAddr, GFP_KERNEL); 4793 if (!tp->RxDescArray) 4794 goto err_free_tx_0; 4795 4796 retval = rtl8169_init_ring(tp); 4797 if (retval < 0) 4798 goto err_free_rx_1; 4799 4800 rtl_request_firmware(tp); 4801 4802 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4803 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4804 if (retval < 0) 4805 goto err_release_fw_2; 4806 4807 retval = r8169_phy_connect(tp); 4808 if (retval) 4809 goto err_free_irq; 4810 4811 rtl8169_up(tp); 4812 rtl8169_init_counter_offsets(tp); 4813 netif_start_queue(dev); 4814 out: 4815 pm_runtime_put_sync(&pdev->dev); 4816 4817 return retval; 4818 4819 err_free_irq: 4820 free_irq(tp->irq, tp); 4821 err_release_fw_2: 4822 rtl_release_firmware(tp); 4823 rtl8169_rx_clear(tp); 4824 err_free_rx_1: 4825 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4826 tp->RxPhyAddr); 4827 tp->RxDescArray = NULL; 4828 err_free_tx_0: 4829 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4830 tp->TxPhyAddr); 4831 tp->TxDescArray = NULL; 4832 goto out; 4833 } 4834 4835 static void 4836 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4837 { 4838 struct rtl8169_private *tp = netdev_priv(dev); 4839 struct pci_dev *pdev = tp->pci_dev; 4840 struct rtl8169_counters *counters = tp->counters; 4841 4842 pm_runtime_get_noresume(&pdev->dev); 4843 4844 netdev_stats_to_stats64(stats, &dev->stats); 4845 dev_fetch_sw_netstats(stats, dev->tstats); 4846 4847 /* 4848 * Fetch additional counter values missing in stats collected by driver 4849 * from tally counters. 4850 */ 4851 if (pm_runtime_active(&pdev->dev)) 4852 rtl8169_update_counters(tp); 4853 4854 /* 4855 * Subtract values fetched during initalization. 4856 * See rtl8169_init_counter_offsets for a description why we do that. 4857 */ 4858 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4859 le64_to_cpu(tp->tc_offset.tx_errors); 4860 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4861 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4862 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4863 le16_to_cpu(tp->tc_offset.tx_aborted); 4864 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4865 le16_to_cpu(tp->tc_offset.rx_missed); 4866 4867 pm_runtime_put_noidle(&pdev->dev); 4868 } 4869 4870 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4871 { 4872 netif_device_detach(tp->dev); 4873 4874 if (netif_running(tp->dev)) 4875 rtl8169_down(tp); 4876 } 4877 4878 static int rtl8169_runtime_resume(struct device *dev) 4879 { 4880 struct rtl8169_private *tp = dev_get_drvdata(dev); 4881 4882 rtl_rar_set(tp, tp->dev->dev_addr); 4883 __rtl8169_set_wol(tp, tp->saved_wolopts); 4884 4885 if (tp->TxDescArray) 4886 rtl8169_up(tp); 4887 4888 netif_device_attach(tp->dev); 4889 4890 return 0; 4891 } 4892 4893 static int rtl8169_suspend(struct device *device) 4894 { 4895 struct rtl8169_private *tp = dev_get_drvdata(device); 4896 4897 rtnl_lock(); 4898 rtl8169_net_suspend(tp); 4899 if (!device_may_wakeup(tp_to_dev(tp))) 4900 clk_disable_unprepare(tp->clk); 4901 rtnl_unlock(); 4902 4903 return 0; 4904 } 4905 4906 static int rtl8169_resume(struct device *device) 4907 { 4908 struct rtl8169_private *tp = dev_get_drvdata(device); 4909 4910 if (!device_may_wakeup(tp_to_dev(tp))) 4911 clk_prepare_enable(tp->clk); 4912 4913 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4914 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4915 rtl_init_rxcfg(tp); 4916 4917 return rtl8169_runtime_resume(device); 4918 } 4919 4920 static int rtl8169_runtime_suspend(struct device *device) 4921 { 4922 struct rtl8169_private *tp = dev_get_drvdata(device); 4923 4924 if (!tp->TxDescArray) { 4925 netif_device_detach(tp->dev); 4926 return 0; 4927 } 4928 4929 rtnl_lock(); 4930 __rtl8169_set_wol(tp, WAKE_PHY); 4931 rtl8169_net_suspend(tp); 4932 rtnl_unlock(); 4933 4934 return 0; 4935 } 4936 4937 static int rtl8169_runtime_idle(struct device *device) 4938 { 4939 struct rtl8169_private *tp = dev_get_drvdata(device); 4940 4941 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4942 pm_schedule_suspend(device, 10000); 4943 4944 return -EBUSY; 4945 } 4946 4947 static const struct dev_pm_ops rtl8169_pm_ops = { 4948 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4949 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4950 rtl8169_runtime_idle) 4951 }; 4952 4953 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4954 { 4955 /* WoL fails with 8168b when the receiver is disabled. */ 4956 switch (tp->mac_version) { 4957 case RTL_GIGA_MAC_VER_11: 4958 case RTL_GIGA_MAC_VER_12: 4959 case RTL_GIGA_MAC_VER_17: 4960 pci_clear_master(tp->pci_dev); 4961 4962 RTL_W8(tp, ChipCmd, CmdRxEnb); 4963 rtl_pci_commit(tp); 4964 break; 4965 default: 4966 break; 4967 } 4968 } 4969 4970 static void rtl_shutdown(struct pci_dev *pdev) 4971 { 4972 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4973 4974 rtnl_lock(); 4975 rtl8169_net_suspend(tp); 4976 rtnl_unlock(); 4977 4978 /* Restore original MAC address */ 4979 rtl_rar_set(tp, tp->dev->perm_addr); 4980 4981 if (system_state == SYSTEM_POWER_OFF) { 4982 if (tp->saved_wolopts) 4983 rtl_wol_shutdown_quirk(tp); 4984 4985 pci_wake_from_d3(pdev, tp->saved_wolopts); 4986 pci_set_power_state(pdev, PCI_D3hot); 4987 } 4988 } 4989 4990 static void rtl_remove_one(struct pci_dev *pdev) 4991 { 4992 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4993 4994 if (pci_dev_run_wake(pdev)) 4995 pm_runtime_get_noresume(&pdev->dev); 4996 4997 unregister_netdev(tp->dev); 4998 4999 if (tp->dash_type != RTL_DASH_NONE) 5000 rtl8168_driver_stop(tp); 5001 5002 rtl_release_firmware(tp); 5003 5004 /* restore original MAC address */ 5005 rtl_rar_set(tp, tp->dev->perm_addr); 5006 } 5007 5008 static const struct net_device_ops rtl_netdev_ops = { 5009 .ndo_open = rtl_open, 5010 .ndo_stop = rtl8169_close, 5011 .ndo_get_stats64 = rtl8169_get_stats64, 5012 .ndo_start_xmit = rtl8169_start_xmit, 5013 .ndo_features_check = rtl8169_features_check, 5014 .ndo_tx_timeout = rtl8169_tx_timeout, 5015 .ndo_validate_addr = eth_validate_addr, 5016 .ndo_change_mtu = rtl8169_change_mtu, 5017 .ndo_fix_features = rtl8169_fix_features, 5018 .ndo_set_features = rtl8169_set_features, 5019 .ndo_set_mac_address = rtl_set_mac_address, 5020 .ndo_eth_ioctl = phy_do_ioctl_running, 5021 .ndo_set_rx_mode = rtl_set_rx_mode, 5022 #ifdef CONFIG_NET_POLL_CONTROLLER 5023 .ndo_poll_controller = rtl8169_netpoll, 5024 #endif 5025 5026 }; 5027 5028 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5029 { 5030 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5031 5032 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5033 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5034 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5035 /* special workaround needed */ 5036 tp->irq_mask |= RxFIFOOver; 5037 else 5038 tp->irq_mask |= RxOverflow; 5039 } 5040 5041 static int rtl_alloc_irq(struct rtl8169_private *tp) 5042 { 5043 unsigned int flags; 5044 5045 switch (tp->mac_version) { 5046 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5047 rtl_unlock_config_regs(tp); 5048 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5049 rtl_lock_config_regs(tp); 5050 fallthrough; 5051 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5052 flags = PCI_IRQ_LEGACY; 5053 break; 5054 default: 5055 flags = PCI_IRQ_ALL_TYPES; 5056 break; 5057 } 5058 5059 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5060 } 5061 5062 static void rtl_read_mac_address(struct rtl8169_private *tp, 5063 u8 mac_addr[ETH_ALEN]) 5064 { 5065 /* Get MAC address */ 5066 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5067 u32 value; 5068 5069 value = rtl_eri_read(tp, 0xe0); 5070 put_unaligned_le32(value, mac_addr); 5071 value = rtl_eri_read(tp, 0xe4); 5072 put_unaligned_le16(value, mac_addr + 4); 5073 } else if (rtl_is_8125(tp)) { 5074 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5075 } 5076 } 5077 5078 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5079 { 5080 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5081 } 5082 5083 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5084 { 5085 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5086 } 5087 5088 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5089 { 5090 struct rtl8169_private *tp = mii_bus->priv; 5091 5092 if (phyaddr > 0) 5093 return -ENODEV; 5094 5095 return rtl_readphy(tp, phyreg); 5096 } 5097 5098 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5099 int phyreg, u16 val) 5100 { 5101 struct rtl8169_private *tp = mii_bus->priv; 5102 5103 if (phyaddr > 0) 5104 return -ENODEV; 5105 5106 rtl_writephy(tp, phyreg, val); 5107 5108 return 0; 5109 } 5110 5111 static int r8169_mdio_register(struct rtl8169_private *tp) 5112 { 5113 struct pci_dev *pdev = tp->pci_dev; 5114 struct mii_bus *new_bus; 5115 int ret; 5116 5117 new_bus = devm_mdiobus_alloc(&pdev->dev); 5118 if (!new_bus) 5119 return -ENOMEM; 5120 5121 new_bus->name = "r8169"; 5122 new_bus->priv = tp; 5123 new_bus->parent = &pdev->dev; 5124 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5125 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5126 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5127 5128 new_bus->read = r8169_mdio_read_reg; 5129 new_bus->write = r8169_mdio_write_reg; 5130 5131 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5132 if (ret) 5133 return ret; 5134 5135 tp->phydev = mdiobus_get_phy(new_bus, 0); 5136 if (!tp->phydev) { 5137 return -ENODEV; 5138 } else if (!tp->phydev->drv) { 5139 /* Most chip versions fail with the genphy driver. 5140 * Therefore ensure that the dedicated PHY driver is loaded. 5141 */ 5142 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5143 tp->phydev->phy_id); 5144 return -EUNATCH; 5145 } 5146 5147 tp->phydev->mac_managed_pm = 1; 5148 5149 phy_support_asym_pause(tp->phydev); 5150 5151 /* PHY will be woken up in rtl_open() */ 5152 phy_suspend(tp->phydev); 5153 5154 return 0; 5155 } 5156 5157 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5158 { 5159 rtl_enable_rxdvgate(tp); 5160 5161 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5162 msleep(1); 5163 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5164 5165 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5166 r8168g_wait_ll_share_fifo_ready(tp); 5167 5168 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5169 r8168g_wait_ll_share_fifo_ready(tp); 5170 } 5171 5172 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5173 { 5174 rtl_enable_rxdvgate(tp); 5175 5176 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5177 msleep(1); 5178 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5179 5180 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5181 r8168g_wait_ll_share_fifo_ready(tp); 5182 5183 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5184 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5185 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5186 r8168g_wait_ll_share_fifo_ready(tp); 5187 } 5188 5189 static void rtl_hw_initialize(struct rtl8169_private *tp) 5190 { 5191 switch (tp->mac_version) { 5192 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 5193 rtl8168ep_stop_cmac(tp); 5194 fallthrough; 5195 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5196 rtl_hw_init_8168g(tp); 5197 break; 5198 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 5199 rtl_hw_init_8125(tp); 5200 break; 5201 default: 5202 break; 5203 } 5204 } 5205 5206 static int rtl_jumbo_max(struct rtl8169_private *tp) 5207 { 5208 /* Non-GBit versions don't support jumbo frames */ 5209 if (!tp->supports_gmii) 5210 return 0; 5211 5212 switch (tp->mac_version) { 5213 /* RTL8169 */ 5214 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5215 return JUMBO_7K; 5216 /* RTL8168b */ 5217 case RTL_GIGA_MAC_VER_11: 5218 case RTL_GIGA_MAC_VER_12: 5219 case RTL_GIGA_MAC_VER_17: 5220 return JUMBO_4K; 5221 /* RTL8168c */ 5222 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5223 return JUMBO_6K; 5224 default: 5225 return JUMBO_9K; 5226 } 5227 } 5228 5229 static void rtl_disable_clk(void *data) 5230 { 5231 clk_disable_unprepare(data); 5232 } 5233 5234 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5235 { 5236 struct device *d = tp_to_dev(tp); 5237 struct clk *clk; 5238 int rc; 5239 5240 clk = devm_clk_get(d, "ether_clk"); 5241 if (IS_ERR(clk)) { 5242 rc = PTR_ERR(clk); 5243 if (rc == -ENOENT) 5244 /* clk-core allows NULL (for suspend / resume) */ 5245 rc = 0; 5246 else 5247 dev_err_probe(d, rc, "failed to get clk\n"); 5248 } else { 5249 tp->clk = clk; 5250 rc = clk_prepare_enable(clk); 5251 if (rc) 5252 dev_err(d, "failed to enable clk: %d\n", rc); 5253 else 5254 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5255 } 5256 5257 return rc; 5258 } 5259 5260 static void rtl_init_mac_address(struct rtl8169_private *tp) 5261 { 5262 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5263 struct net_device *dev = tp->dev; 5264 int rc; 5265 5266 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5267 if (!rc) 5268 goto done; 5269 5270 rtl_read_mac_address(tp, mac_addr); 5271 if (is_valid_ether_addr(mac_addr)) 5272 goto done; 5273 5274 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5275 if (is_valid_ether_addr(mac_addr)) 5276 goto done; 5277 5278 eth_random_addr(mac_addr); 5279 dev->addr_assign_type = NET_ADDR_RANDOM; 5280 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5281 done: 5282 eth_hw_addr_set(dev, mac_addr); 5283 rtl_rar_set(tp, mac_addr); 5284 } 5285 5286 /* register is set if system vendor successfully tested ASPM 1.2 */ 5287 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5288 { 5289 if (tp->mac_version >= RTL_GIGA_MAC_VER_60 && 5290 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5291 return true; 5292 5293 return false; 5294 } 5295 5296 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5297 { 5298 struct rtl8169_private *tp; 5299 int jumbo_max, region, rc; 5300 enum mac_version chipset; 5301 struct net_device *dev; 5302 u16 xid; 5303 5304 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5305 if (!dev) 5306 return -ENOMEM; 5307 5308 SET_NETDEV_DEV(dev, &pdev->dev); 5309 dev->netdev_ops = &rtl_netdev_ops; 5310 tp = netdev_priv(dev); 5311 tp->dev = dev; 5312 tp->pci_dev = pdev; 5313 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5314 tp->eee_adv = -1; 5315 tp->ocp_base = OCP_STD_PHY_BASE; 5316 5317 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5318 struct pcpu_sw_netstats); 5319 if (!dev->tstats) 5320 return -ENOMEM; 5321 5322 /* Get the *optional* external "ether_clk" used on some boards */ 5323 rc = rtl_get_ether_clk(tp); 5324 if (rc) 5325 return rc; 5326 5327 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5328 rc = pcim_enable_device(pdev); 5329 if (rc < 0) { 5330 dev_err(&pdev->dev, "enable failure\n"); 5331 return rc; 5332 } 5333 5334 if (pcim_set_mwi(pdev) < 0) 5335 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5336 5337 /* use first MMIO region */ 5338 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5339 if (region < 0) { 5340 dev_err(&pdev->dev, "no MMIO resource found\n"); 5341 return -ENODEV; 5342 } 5343 5344 /* check for weird/broken PCI region reporting */ 5345 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5346 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5347 return -ENODEV; 5348 } 5349 5350 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5351 if (rc < 0) { 5352 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5353 return rc; 5354 } 5355 5356 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5357 5358 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5359 5360 /* Identify chip attached to board */ 5361 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5362 if (chipset == RTL_GIGA_MAC_NONE) { 5363 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5364 return -ENODEV; 5365 } 5366 5367 tp->mac_version = chipset; 5368 5369 /* Disable ASPM L1 as that cause random device stop working 5370 * problems as well as full system hangs for some PCIe devices users. 5371 * Chips from RTL8168h partially have issues with L1.2, but seem 5372 * to work fine with L1 and L1.1. 5373 */ 5374 if (rtl_aspm_is_safe(tp)) 5375 rc = 0; 5376 else if (tp->mac_version >= RTL_GIGA_MAC_VER_45) 5377 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2); 5378 else 5379 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5380 tp->aspm_manageable = !rc; 5381 5382 tp->dash_type = rtl_check_dash(tp); 5383 5384 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5385 5386 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5387 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5388 dev->features |= NETIF_F_HIGHDMA; 5389 5390 rtl_init_rxcfg(tp); 5391 5392 rtl8169_irq_mask_and_ack(tp); 5393 5394 rtl_hw_initialize(tp); 5395 5396 rtl_hw_reset(tp); 5397 5398 rc = rtl_alloc_irq(tp); 5399 if (rc < 0) { 5400 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5401 return rc; 5402 } 5403 tp->irq = pci_irq_vector(pdev, 0); 5404 5405 INIT_WORK(&tp->wk.work, rtl_task); 5406 5407 rtl_init_mac_address(tp); 5408 5409 dev->ethtool_ops = &rtl8169_ethtool_ops; 5410 5411 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5412 5413 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5414 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5415 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5416 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5417 5418 /* 5419 * Pretend we are using VLANs; This bypasses a nasty bug where 5420 * Interrupts stop flowing on high load on 8110SCd controllers. 5421 */ 5422 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5423 /* Disallow toggling */ 5424 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5425 5426 if (rtl_chip_supports_csum_v2(tp)) 5427 dev->hw_features |= NETIF_F_IPV6_CSUM; 5428 5429 dev->features |= dev->hw_features; 5430 5431 /* There has been a number of reports that using SG/TSO results in 5432 * tx timeouts. However for a lot of people SG/TSO works fine. 5433 * Therefore disable both features by default, but allow users to 5434 * enable them. Use at own risk! 5435 */ 5436 if (rtl_chip_supports_csum_v2(tp)) { 5437 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5438 netif_set_gso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5439 netif_set_gso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5440 } else { 5441 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5442 netif_set_gso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5443 netif_set_gso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5444 } 5445 5446 dev->hw_features |= NETIF_F_RXALL; 5447 dev->hw_features |= NETIF_F_RXFCS; 5448 5449 /* configure chip for default features */ 5450 rtl8169_set_features(dev, dev->features); 5451 5452 rtl_set_d3_pll_down(tp, true); 5453 5454 jumbo_max = rtl_jumbo_max(tp); 5455 if (jumbo_max) 5456 dev->max_mtu = jumbo_max; 5457 5458 rtl_set_irq_mask(tp); 5459 5460 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5461 5462 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5463 &tp->counters_phys_addr, 5464 GFP_KERNEL); 5465 if (!tp->counters) 5466 return -ENOMEM; 5467 5468 pci_set_drvdata(pdev, tp); 5469 5470 rc = r8169_mdio_register(tp); 5471 if (rc) 5472 return rc; 5473 5474 rc = register_netdev(dev); 5475 if (rc) 5476 return rc; 5477 5478 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5479 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5480 5481 if (jumbo_max) 5482 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5483 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5484 "ok" : "ko"); 5485 5486 if (tp->dash_type != RTL_DASH_NONE) { 5487 netdev_info(dev, "DASH enabled\n"); 5488 rtl8168_driver_start(tp); 5489 } 5490 5491 if (pci_dev_run_wake(pdev)) 5492 pm_runtime_put_sync(&pdev->dev); 5493 5494 return 0; 5495 } 5496 5497 static struct pci_driver rtl8169_pci_driver = { 5498 .name = KBUILD_MODNAME, 5499 .id_table = rtl8169_pci_tbl, 5500 .probe = rtl_init_one, 5501 .remove = rtl_remove_one, 5502 .shutdown = rtl_shutdown, 5503 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5504 }; 5505 5506 module_pci_driver(rtl8169_pci_driver); 5507