1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define MODULENAME "r8169" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 56 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 59 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 60 61 #define R8169_MSG_DEFAULT \ 62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 63 64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 65 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 66 #define MC_FILTER_LIMIT 32 67 68 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 69 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 70 71 #define R8169_REGS_SIZE 256 72 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 73 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 74 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 77 78 #define OCP_STD_PHY_BASE 0xa400 79 80 #define RTL_CFG_NO_GBIT 1 81 82 /* write/read MMIO register */ 83 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 84 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 85 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 86 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 87 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 88 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 89 90 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) 91 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) 92 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) 93 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) 94 95 static const struct { 96 const char *name; 97 const char *fw_name; 98 } rtl_chip_infos[] = { 99 /* PCI devices. */ 100 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 101 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 102 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 103 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 104 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 105 /* PCI-E devices. */ 106 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 107 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 108 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 109 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 110 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 111 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 112 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 113 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 114 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 115 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 116 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 117 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 118 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 119 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 120 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 121 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 122 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 123 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 124 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 125 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 126 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 127 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 128 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 129 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 130 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 131 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 132 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 133 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 134 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 135 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 136 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 137 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 138 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 139 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 140 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 141 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 142 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 143 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 144 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 145 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 146 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 147 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 148 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 149 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 150 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 151 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 152 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 153 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 154 }; 155 156 static const struct pci_device_id rtl8169_pci_tbl[] = { 157 { PCI_VDEVICE(REALTEK, 0x2502) }, 158 { PCI_VDEVICE(REALTEK, 0x2600) }, 159 { PCI_VDEVICE(REALTEK, 0x8129) }, 160 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 161 { PCI_VDEVICE(REALTEK, 0x8161) }, 162 { PCI_VDEVICE(REALTEK, 0x8167) }, 163 { PCI_VDEVICE(REALTEK, 0x8168) }, 164 { PCI_VDEVICE(NCUBE, 0x8168) }, 165 { PCI_VDEVICE(REALTEK, 0x8169) }, 166 { PCI_VENDOR_ID_DLINK, 0x4300, 167 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 168 { PCI_VDEVICE(DLINK, 0x4300) }, 169 { PCI_VDEVICE(DLINK, 0x4302) }, 170 { PCI_VDEVICE(AT, 0xc107) }, 171 { PCI_VDEVICE(USR, 0x0116) }, 172 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 173 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 174 { PCI_VDEVICE(REALTEK, 0x8125) }, 175 { PCI_VDEVICE(REALTEK, 0x3000) }, 176 {} 177 }; 178 179 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 180 181 static struct { 182 u32 msg_enable; 183 } debug = { -1 }; 184 185 enum rtl_registers { 186 MAC0 = 0, /* Ethernet hardware address. */ 187 MAC4 = 4, 188 MAR0 = 8, /* Multicast filter. */ 189 CounterAddrLow = 0x10, 190 CounterAddrHigh = 0x14, 191 TxDescStartAddrLow = 0x20, 192 TxDescStartAddrHigh = 0x24, 193 TxHDescStartAddrLow = 0x28, 194 TxHDescStartAddrHigh = 0x2c, 195 FLASH = 0x30, 196 ERSR = 0x36, 197 ChipCmd = 0x37, 198 TxPoll = 0x38, 199 IntrMask = 0x3c, 200 IntrStatus = 0x3e, 201 202 TxConfig = 0x40, 203 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 204 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 205 206 RxConfig = 0x44, 207 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 208 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 209 #define RXCFG_FIFO_SHIFT 13 210 /* No threshold before first PCI xfer */ 211 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 212 #define RX_EARLY_OFF (1 << 11) 213 #define RXCFG_DMA_SHIFT 8 214 /* Unlimited maximum PCI burst. */ 215 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 216 217 Cfg9346 = 0x50, 218 Config0 = 0x51, 219 Config1 = 0x52, 220 Config2 = 0x53, 221 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 222 223 Config3 = 0x54, 224 Config4 = 0x55, 225 Config5 = 0x56, 226 PHYAR = 0x60, 227 PHYstatus = 0x6c, 228 RxMaxSize = 0xda, 229 CPlusCmd = 0xe0, 230 IntrMitigate = 0xe2, 231 232 #define RTL_COALESCE_MASK 0x0f 233 #define RTL_COALESCE_SHIFT 4 234 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) 235 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) 236 237 RxDescAddrLow = 0xe4, 238 RxDescAddrHigh = 0xe8, 239 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 240 241 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 242 243 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 244 245 #define TxPacketMax (8064 >> 7) 246 #define EarlySize 0x27 247 248 FuncEvent = 0xf0, 249 FuncEventMask = 0xf4, 250 FuncPresetState = 0xf8, 251 IBCR0 = 0xf8, 252 IBCR2 = 0xf9, 253 IBIMR0 = 0xfa, 254 IBISR0 = 0xfb, 255 FuncForceEvent = 0xfc, 256 }; 257 258 enum rtl8168_8101_registers { 259 CSIDR = 0x64, 260 CSIAR = 0x68, 261 #define CSIAR_FLAG 0x80000000 262 #define CSIAR_WRITE_CMD 0x80000000 263 #define CSIAR_BYTE_ENABLE 0x0000f000 264 #define CSIAR_ADDR_MASK 0x00000fff 265 PMCH = 0x6f, 266 EPHYAR = 0x80, 267 #define EPHYAR_FLAG 0x80000000 268 #define EPHYAR_WRITE_CMD 0x80000000 269 #define EPHYAR_REG_MASK 0x1f 270 #define EPHYAR_REG_SHIFT 16 271 #define EPHYAR_DATA_MASK 0xffff 272 DLLPR = 0xd0, 273 #define PFM_EN (1 << 6) 274 #define TX_10M_PS_EN (1 << 7) 275 DBG_REG = 0xd1, 276 #define FIX_NAK_1 (1 << 4) 277 #define FIX_NAK_2 (1 << 3) 278 TWSI = 0xd2, 279 MCU = 0xd3, 280 #define NOW_IS_OOB (1 << 7) 281 #define TX_EMPTY (1 << 5) 282 #define RX_EMPTY (1 << 4) 283 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 284 #define EN_NDP (1 << 3) 285 #define EN_OOB_RESET (1 << 2) 286 #define LINK_LIST_RDY (1 << 1) 287 EFUSEAR = 0xdc, 288 #define EFUSEAR_FLAG 0x80000000 289 #define EFUSEAR_WRITE_CMD 0x80000000 290 #define EFUSEAR_READ_CMD 0x00000000 291 #define EFUSEAR_REG_MASK 0x03ff 292 #define EFUSEAR_REG_SHIFT 8 293 #define EFUSEAR_DATA_MASK 0xff 294 MISC_1 = 0xf2, 295 #define PFM_D3COLD_EN (1 << 6) 296 }; 297 298 enum rtl8168_registers { 299 LED_FREQ = 0x1a, 300 EEE_LED = 0x1b, 301 ERIDR = 0x70, 302 ERIAR = 0x74, 303 #define ERIAR_FLAG 0x80000000 304 #define ERIAR_WRITE_CMD 0x80000000 305 #define ERIAR_READ_CMD 0x00000000 306 #define ERIAR_ADDR_BYTE_ALIGN 4 307 #define ERIAR_TYPE_SHIFT 16 308 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 310 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 312 #define ERIAR_MASK_SHIFT 12 313 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 315 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 317 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 318 EPHY_RXER_NUM = 0x7c, 319 OCPDR = 0xb0, /* OCP GPHY access */ 320 #define OCPDR_WRITE_CMD 0x80000000 321 #define OCPDR_READ_CMD 0x00000000 322 #define OCPDR_REG_MASK 0x7f 323 #define OCPDR_GPHY_REG_SHIFT 16 324 #define OCPDR_DATA_MASK 0xffff 325 OCPAR = 0xb4, 326 #define OCPAR_FLAG 0x80000000 327 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 328 #define OCPAR_GPHY_READ_CMD 0x0000f060 329 GPHY_OCP = 0xb8, 330 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 331 MISC = 0xf0, /* 8168e only. */ 332 #define TXPLA_RST (1 << 29) 333 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 334 #define PWM_EN (1 << 22) 335 #define RXDV_GATED_EN (1 << 19) 336 #define EARLY_TALLY_EN (1 << 16) 337 }; 338 339 enum rtl8125_registers { 340 IntrMask_8125 = 0x38, 341 IntrStatus_8125 = 0x3c, 342 TxPoll_8125 = 0x90, 343 MAC0_BKP = 0x19e0, 344 }; 345 346 #define RX_VLAN_INNER_8125 BIT(22) 347 #define RX_VLAN_OUTER_8125 BIT(23) 348 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 349 350 #define RX_FETCH_DFLT_8125 (8 << 27) 351 352 enum rtl_register_content { 353 /* InterruptStatusBits */ 354 SYSErr = 0x8000, 355 PCSTimeout = 0x4000, 356 SWInt = 0x0100, 357 TxDescUnavail = 0x0080, 358 RxFIFOOver = 0x0040, 359 LinkChg = 0x0020, 360 RxOverflow = 0x0010, 361 TxErr = 0x0008, 362 TxOK = 0x0004, 363 RxErr = 0x0002, 364 RxOK = 0x0001, 365 366 /* RxStatusDesc */ 367 RxRWT = (1 << 22), 368 RxRES = (1 << 21), 369 RxRUNT = (1 << 20), 370 RxCRC = (1 << 19), 371 372 /* ChipCmdBits */ 373 StopReq = 0x80, 374 CmdReset = 0x10, 375 CmdRxEnb = 0x08, 376 CmdTxEnb = 0x04, 377 RxBufEmpty = 0x01, 378 379 /* TXPoll register p.5 */ 380 HPQ = 0x80, /* Poll cmd on the high prio queue */ 381 NPQ = 0x40, /* Poll cmd on the low prio queue */ 382 FSWInt = 0x01, /* Forced software interrupt */ 383 384 /* Cfg9346Bits */ 385 Cfg9346_Lock = 0x00, 386 Cfg9346_Unlock = 0xc0, 387 388 /* rx_mode_bits */ 389 AcceptErr = 0x20, 390 AcceptRunt = 0x10, 391 AcceptBroadcast = 0x08, 392 AcceptMulticast = 0x04, 393 AcceptMyPhys = 0x02, 394 AcceptAllPhys = 0x01, 395 #define RX_CONFIG_ACCEPT_MASK 0x3f 396 397 /* TxConfigBits */ 398 TxInterFrameGapShift = 24, 399 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 400 401 /* Config1 register p.24 */ 402 LEDS1 = (1 << 7), 403 LEDS0 = (1 << 6), 404 Speed_down = (1 << 4), 405 MEMMAP = (1 << 3), 406 IOMAP = (1 << 2), 407 VPD = (1 << 1), 408 PMEnable = (1 << 0), /* Power Management Enable */ 409 410 /* Config2 register p. 25 */ 411 ClkReqEn = (1 << 7), /* Clock Request Enable */ 412 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 413 PCI_Clock_66MHz = 0x01, 414 PCI_Clock_33MHz = 0x00, 415 416 /* Config3 register p.25 */ 417 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 418 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 419 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 420 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 421 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 422 423 /* Config4 register */ 424 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 425 426 /* Config5 register p.27 */ 427 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 428 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 429 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 430 Spi_en = (1 << 3), 431 LanWake = (1 << 1), /* LanWake enable/disable */ 432 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 433 ASPM_en = (1 << 0), /* ASPM enable */ 434 435 /* CPlusCmd p.31 */ 436 EnableBist = (1 << 15), // 8168 8101 437 Mac_dbgo_oe = (1 << 14), // 8168 8101 438 EnAnaPLL = (1 << 14), // 8169 439 Normal_mode = (1 << 13), // unused 440 Force_half_dup = (1 << 12), // 8168 8101 441 Force_rxflow_en = (1 << 11), // 8168 8101 442 Force_txflow_en = (1 << 10), // 8168 8101 443 Cxpl_dbg_sel = (1 << 9), // 8168 8101 444 ASF = (1 << 8), // 8168 8101 445 PktCntrDisable = (1 << 7), // 8168 8101 446 Mac_dbgo_sel = 0x001c, // 8168 447 RxVlan = (1 << 6), 448 RxChkSum = (1 << 5), 449 PCIDAC = (1 << 4), 450 PCIMulRW = (1 << 3), 451 #define INTT_MASK GENMASK(1, 0) 452 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 453 454 /* rtl8169_PHYstatus */ 455 TBI_Enable = 0x80, 456 TxFlowCtrl = 0x40, 457 RxFlowCtrl = 0x20, 458 _1000bpsF = 0x10, 459 _100bps = 0x08, 460 _10bps = 0x04, 461 LinkStatus = 0x02, 462 FullDup = 0x01, 463 464 /* ResetCounterCommand */ 465 CounterReset = 0x1, 466 467 /* DumpCounterCommand */ 468 CounterDump = 0x8, 469 470 /* magic enable v2 */ 471 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 472 }; 473 474 enum rtl_desc_bit { 475 /* First doubleword. */ 476 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 477 RingEnd = (1 << 30), /* End of descriptor ring */ 478 FirstFrag = (1 << 29), /* First segment of a packet */ 479 LastFrag = (1 << 28), /* Final segment of a packet */ 480 }; 481 482 /* Generic case. */ 483 enum rtl_tx_desc_bit { 484 /* First doubleword. */ 485 TD_LSO = (1 << 27), /* Large Send Offload */ 486 #define TD_MSS_MAX 0x07ffu /* MSS value */ 487 488 /* Second doubleword. */ 489 TxVlanTag = (1 << 17), /* Add VLAN tag */ 490 }; 491 492 /* 8169, 8168b and 810x except 8102e. */ 493 enum rtl_tx_desc_bit_0 { 494 /* First doubleword. */ 495 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 496 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 497 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 498 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 499 }; 500 501 /* 8102e, 8168c and beyond. */ 502 enum rtl_tx_desc_bit_1 { 503 /* First doubleword. */ 504 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 505 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 506 #define GTTCPHO_SHIFT 18 507 #define GTTCPHO_MAX 0x7f 508 509 /* Second doubleword. */ 510 #define TCPHO_SHIFT 18 511 #define TCPHO_MAX 0x3ff 512 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 513 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 514 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 515 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 516 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 517 }; 518 519 enum rtl_rx_desc_bit { 520 /* Rx private */ 521 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 522 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 523 524 #define RxProtoUDP (PID1) 525 #define RxProtoTCP (PID0) 526 #define RxProtoIP (PID1 | PID0) 527 #define RxProtoMask RxProtoIP 528 529 IPFail = (1 << 16), /* IP checksum failed */ 530 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 531 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 532 RxVlanTag = (1 << 16), /* VLAN tag available */ 533 }; 534 535 #define RsvdMask 0x3fffc000 536 537 #define RTL_GSO_MAX_SIZE_V1 32000 538 #define RTL_GSO_MAX_SEGS_V1 24 539 #define RTL_GSO_MAX_SIZE_V2 64000 540 #define RTL_GSO_MAX_SEGS_V2 64 541 542 struct TxDesc { 543 __le32 opts1; 544 __le32 opts2; 545 __le64 addr; 546 }; 547 548 struct RxDesc { 549 __le32 opts1; 550 __le32 opts2; 551 __le64 addr; 552 }; 553 554 struct ring_info { 555 struct sk_buff *skb; 556 u32 len; 557 }; 558 559 struct rtl8169_counters { 560 __le64 tx_packets; 561 __le64 rx_packets; 562 __le64 tx_errors; 563 __le32 rx_errors; 564 __le16 rx_missed; 565 __le16 align_errors; 566 __le32 tx_one_collision; 567 __le32 tx_multi_collision; 568 __le64 rx_unicast; 569 __le64 rx_broadcast; 570 __le32 rx_multicast; 571 __le16 tx_aborted; 572 __le16 tx_underun; 573 }; 574 575 struct rtl8169_tc_offsets { 576 bool inited; 577 __le64 tx_errors; 578 __le32 tx_multi_collision; 579 __le16 tx_aborted; 580 __le16 rx_missed; 581 }; 582 583 enum rtl_flag { 584 RTL_FLAG_TASK_ENABLED = 0, 585 RTL_FLAG_TASK_RESET_PENDING, 586 RTL_FLAG_MAX 587 }; 588 589 struct rtl8169_stats { 590 u64 packets; 591 u64 bytes; 592 struct u64_stats_sync syncp; 593 }; 594 595 struct rtl8169_private { 596 void __iomem *mmio_addr; /* memory map physical address */ 597 struct pci_dev *pci_dev; 598 struct net_device *dev; 599 struct phy_device *phydev; 600 struct napi_struct napi; 601 u32 msg_enable; 602 enum mac_version mac_version; 603 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 604 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 605 u32 dirty_tx; 606 struct rtl8169_stats rx_stats; 607 struct rtl8169_stats tx_stats; 608 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 609 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 610 dma_addr_t TxPhyAddr; 611 dma_addr_t RxPhyAddr; 612 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 613 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 614 u16 cp_cmd; 615 u32 irq_mask; 616 struct clk *clk; 617 618 struct { 619 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 620 struct mutex mutex; 621 struct work_struct work; 622 } wk; 623 624 unsigned irq_enabled:1; 625 unsigned supports_gmii:1; 626 unsigned aspm_manageable:1; 627 dma_addr_t counters_phys_addr; 628 struct rtl8169_counters *counters; 629 struct rtl8169_tc_offsets tc_offset; 630 u32 saved_wolopts; 631 int eee_adv; 632 633 const char *fw_name; 634 struct rtl_fw *rtl_fw; 635 636 u32 ocp_base; 637 }; 638 639 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 640 641 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 642 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 643 module_param_named(debug, debug.msg_enable, int, 0); 644 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 645 MODULE_SOFTDEP("pre: realtek"); 646 MODULE_LICENSE("GPL"); 647 MODULE_FIRMWARE(FIRMWARE_8168D_1); 648 MODULE_FIRMWARE(FIRMWARE_8168D_2); 649 MODULE_FIRMWARE(FIRMWARE_8168E_1); 650 MODULE_FIRMWARE(FIRMWARE_8168E_2); 651 MODULE_FIRMWARE(FIRMWARE_8168E_3); 652 MODULE_FIRMWARE(FIRMWARE_8105E_1); 653 MODULE_FIRMWARE(FIRMWARE_8168F_1); 654 MODULE_FIRMWARE(FIRMWARE_8168F_2); 655 MODULE_FIRMWARE(FIRMWARE_8402_1); 656 MODULE_FIRMWARE(FIRMWARE_8411_1); 657 MODULE_FIRMWARE(FIRMWARE_8411_2); 658 MODULE_FIRMWARE(FIRMWARE_8106E_1); 659 MODULE_FIRMWARE(FIRMWARE_8106E_2); 660 MODULE_FIRMWARE(FIRMWARE_8168G_2); 661 MODULE_FIRMWARE(FIRMWARE_8168G_3); 662 MODULE_FIRMWARE(FIRMWARE_8168H_1); 663 MODULE_FIRMWARE(FIRMWARE_8168H_2); 664 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 665 MODULE_FIRMWARE(FIRMWARE_8107E_1); 666 MODULE_FIRMWARE(FIRMWARE_8107E_2); 667 MODULE_FIRMWARE(FIRMWARE_8125A_3); 668 669 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 670 { 671 return &tp->pci_dev->dev; 672 } 673 674 static void rtl_lock_work(struct rtl8169_private *tp) 675 { 676 mutex_lock(&tp->wk.mutex); 677 } 678 679 static void rtl_unlock_work(struct rtl8169_private *tp) 680 { 681 mutex_unlock(&tp->wk.mutex); 682 } 683 684 static void rtl_lock_config_regs(struct rtl8169_private *tp) 685 { 686 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 687 } 688 689 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 690 { 691 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 692 } 693 694 static void rtl_pci_commit(struct rtl8169_private *tp) 695 { 696 /* Read an arbitrary register to commit a preceding PCI write */ 697 RTL_R8(tp, ChipCmd); 698 } 699 700 static bool rtl_is_8125(struct rtl8169_private *tp) 701 { 702 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 703 } 704 705 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 706 { 707 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 708 tp->mac_version != RTL_GIGA_MAC_VER_39 && 709 tp->mac_version <= RTL_GIGA_MAC_VER_52; 710 } 711 712 static bool rtl_supports_eee(struct rtl8169_private *tp) 713 { 714 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 715 tp->mac_version != RTL_GIGA_MAC_VER_37 && 716 tp->mac_version != RTL_GIGA_MAC_VER_39; 717 } 718 719 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 720 { 721 int i; 722 723 for (i = 0; i < ETH_ALEN; i++) 724 mac[i] = RTL_R8(tp, reg + i); 725 } 726 727 struct rtl_cond { 728 bool (*check)(struct rtl8169_private *); 729 const char *msg; 730 }; 731 732 static void rtl_udelay(unsigned int d) 733 { 734 udelay(d); 735 } 736 737 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 738 void (*delay)(unsigned int), unsigned int d, int n, 739 bool high) 740 { 741 int i; 742 743 for (i = 0; i < n; i++) { 744 if (c->check(tp) == high) 745 return true; 746 delay(d); 747 } 748 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", 749 c->msg, !high, n, d); 750 return false; 751 } 752 753 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 754 const struct rtl_cond *c, 755 unsigned int d, int n) 756 { 757 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 758 } 759 760 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 761 const struct rtl_cond *c, 762 unsigned int d, int n) 763 { 764 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 765 } 766 767 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 768 const struct rtl_cond *c, 769 unsigned int d, int n) 770 { 771 return rtl_loop_wait(tp, c, msleep, d, n, true); 772 } 773 774 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 775 const struct rtl_cond *c, 776 unsigned int d, int n) 777 { 778 return rtl_loop_wait(tp, c, msleep, d, n, false); 779 } 780 781 #define DECLARE_RTL_COND(name) \ 782 static bool name ## _check(struct rtl8169_private *); \ 783 \ 784 static const struct rtl_cond name = { \ 785 .check = name ## _check, \ 786 .msg = #name \ 787 }; \ 788 \ 789 static bool name ## _check(struct rtl8169_private *tp) 790 791 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 792 { 793 if (reg & 0xffff0001) { 794 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); 795 return true; 796 } 797 return false; 798 } 799 800 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 801 { 802 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 803 } 804 805 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 806 { 807 if (rtl_ocp_reg_failure(tp, reg)) 808 return; 809 810 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 811 812 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 813 } 814 815 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 816 { 817 if (rtl_ocp_reg_failure(tp, reg)) 818 return 0; 819 820 RTL_W32(tp, GPHY_OCP, reg << 15); 821 822 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 823 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 824 } 825 826 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 827 { 828 if (rtl_ocp_reg_failure(tp, reg)) 829 return; 830 831 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 832 } 833 834 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 835 { 836 if (rtl_ocp_reg_failure(tp, reg)) 837 return 0; 838 839 RTL_W32(tp, OCPDR, reg << 15); 840 841 return RTL_R32(tp, OCPDR); 842 } 843 844 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 845 u16 set) 846 { 847 u16 data = r8168_mac_ocp_read(tp, reg); 848 849 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 850 } 851 852 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 853 { 854 if (reg == 0x1f) { 855 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 856 return; 857 } 858 859 if (tp->ocp_base != OCP_STD_PHY_BASE) 860 reg -= 0x10; 861 862 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 863 } 864 865 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 866 { 867 if (reg == 0x1f) 868 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 869 870 if (tp->ocp_base != OCP_STD_PHY_BASE) 871 reg -= 0x10; 872 873 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 874 } 875 876 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 877 { 878 if (reg == 0x1f) { 879 tp->ocp_base = value << 4; 880 return; 881 } 882 883 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 884 } 885 886 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 887 { 888 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 889 } 890 891 DECLARE_RTL_COND(rtl_phyar_cond) 892 { 893 return RTL_R32(tp, PHYAR) & 0x80000000; 894 } 895 896 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 897 { 898 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 899 900 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 901 /* 902 * According to hardware specs a 20us delay is required after write 903 * complete indication, but before sending next command. 904 */ 905 udelay(20); 906 } 907 908 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 909 { 910 int value; 911 912 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 913 914 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 915 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 916 917 /* 918 * According to hardware specs a 20us delay is required after read 919 * complete indication, but before sending next command. 920 */ 921 udelay(20); 922 923 return value; 924 } 925 926 DECLARE_RTL_COND(rtl_ocpar_cond) 927 { 928 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 929 } 930 931 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 932 { 933 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 934 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 935 RTL_W32(tp, EPHY_RXER_NUM, 0); 936 937 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 938 } 939 940 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 941 { 942 r8168dp_1_mdio_access(tp, reg, 943 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 944 } 945 946 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 947 { 948 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 949 950 mdelay(1); 951 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 952 RTL_W32(tp, EPHY_RXER_NUM, 0); 953 954 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 955 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 956 } 957 958 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 959 960 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 961 { 962 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 963 } 964 965 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 966 { 967 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 968 } 969 970 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 971 { 972 r8168dp_2_mdio_start(tp); 973 974 r8169_mdio_write(tp, reg, value); 975 976 r8168dp_2_mdio_stop(tp); 977 } 978 979 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 980 { 981 int value; 982 983 /* Work around issue with chip reporting wrong PHY ID */ 984 if (reg == MII_PHYSID2) 985 return 0xc912; 986 987 r8168dp_2_mdio_start(tp); 988 989 value = r8169_mdio_read(tp, reg); 990 991 r8168dp_2_mdio_stop(tp); 992 993 return value; 994 } 995 996 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 997 { 998 switch (tp->mac_version) { 999 case RTL_GIGA_MAC_VER_27: 1000 r8168dp_1_mdio_write(tp, location, val); 1001 break; 1002 case RTL_GIGA_MAC_VER_28: 1003 case RTL_GIGA_MAC_VER_31: 1004 r8168dp_2_mdio_write(tp, location, val); 1005 break; 1006 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1007 r8168g_mdio_write(tp, location, val); 1008 break; 1009 default: 1010 r8169_mdio_write(tp, location, val); 1011 break; 1012 } 1013 } 1014 1015 static int rtl_readphy(struct rtl8169_private *tp, int location) 1016 { 1017 switch (tp->mac_version) { 1018 case RTL_GIGA_MAC_VER_27: 1019 return r8168dp_1_mdio_read(tp, location); 1020 case RTL_GIGA_MAC_VER_28: 1021 case RTL_GIGA_MAC_VER_31: 1022 return r8168dp_2_mdio_read(tp, location); 1023 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1024 return r8168g_mdio_read(tp, location); 1025 default: 1026 return r8169_mdio_read(tp, location); 1027 } 1028 } 1029 1030 DECLARE_RTL_COND(rtl_ephyar_cond) 1031 { 1032 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1033 } 1034 1035 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1036 { 1037 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1038 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1039 1040 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1041 1042 udelay(10); 1043 } 1044 1045 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1046 { 1047 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1048 1049 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1050 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1051 } 1052 1053 DECLARE_RTL_COND(rtl_eriar_cond) 1054 { 1055 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1056 } 1057 1058 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1059 u32 val, int type) 1060 { 1061 BUG_ON((addr & 3) || (mask == 0)); 1062 RTL_W32(tp, ERIDR, val); 1063 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1064 1065 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1066 } 1067 1068 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1069 u32 val) 1070 { 1071 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1072 } 1073 1074 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1075 { 1076 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1077 1078 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1079 RTL_R32(tp, ERIDR) : ~0; 1080 } 1081 1082 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1083 { 1084 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1085 } 1086 1087 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1088 u32 m) 1089 { 1090 u32 val; 1091 1092 val = rtl_eri_read(tp, addr); 1093 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1094 } 1095 1096 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1097 u32 p) 1098 { 1099 rtl_w0w1_eri(tp, addr, mask, p, 0); 1100 } 1101 1102 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1103 u32 m) 1104 { 1105 rtl_w0w1_eri(tp, addr, mask, 0, m); 1106 } 1107 1108 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1109 { 1110 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1111 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1112 RTL_R32(tp, OCPDR) : ~0; 1113 } 1114 1115 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1116 { 1117 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1118 } 1119 1120 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1121 u32 data) 1122 { 1123 RTL_W32(tp, OCPDR, data); 1124 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1125 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1126 } 1127 1128 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1129 u32 data) 1130 { 1131 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1132 data, ERIAR_OOB); 1133 } 1134 1135 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1136 { 1137 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1138 1139 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1140 } 1141 1142 #define OOB_CMD_RESET 0x00 1143 #define OOB_CMD_DRIVER_START 0x05 1144 #define OOB_CMD_DRIVER_STOP 0x06 1145 1146 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1147 { 1148 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1149 } 1150 1151 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1152 { 1153 u16 reg; 1154 1155 reg = rtl8168_get_ocp_reg(tp); 1156 1157 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1158 } 1159 1160 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1161 { 1162 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1163 } 1164 1165 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1166 { 1167 return RTL_R8(tp, IBISR0) & 0x20; 1168 } 1169 1170 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1171 { 1172 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1173 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1174 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1175 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1176 } 1177 1178 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1179 { 1180 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1181 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1182 } 1183 1184 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1185 { 1186 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1187 r8168ep_ocp_write(tp, 0x01, 0x30, 1188 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1189 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1190 } 1191 1192 static void rtl8168_driver_start(struct rtl8169_private *tp) 1193 { 1194 switch (tp->mac_version) { 1195 case RTL_GIGA_MAC_VER_27: 1196 case RTL_GIGA_MAC_VER_28: 1197 case RTL_GIGA_MAC_VER_31: 1198 rtl8168dp_driver_start(tp); 1199 break; 1200 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1201 rtl8168ep_driver_start(tp); 1202 break; 1203 default: 1204 BUG(); 1205 break; 1206 } 1207 } 1208 1209 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1210 { 1211 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1212 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1213 } 1214 1215 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1216 { 1217 rtl8168ep_stop_cmac(tp); 1218 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1219 r8168ep_ocp_write(tp, 0x01, 0x30, 1220 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1221 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1222 } 1223 1224 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1225 { 1226 switch (tp->mac_version) { 1227 case RTL_GIGA_MAC_VER_27: 1228 case RTL_GIGA_MAC_VER_28: 1229 case RTL_GIGA_MAC_VER_31: 1230 rtl8168dp_driver_stop(tp); 1231 break; 1232 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1233 rtl8168ep_driver_stop(tp); 1234 break; 1235 default: 1236 BUG(); 1237 break; 1238 } 1239 } 1240 1241 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1242 { 1243 u16 reg = rtl8168_get_ocp_reg(tp); 1244 1245 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1246 } 1247 1248 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1249 { 1250 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1251 } 1252 1253 static bool r8168_check_dash(struct rtl8169_private *tp) 1254 { 1255 switch (tp->mac_version) { 1256 case RTL_GIGA_MAC_VER_27: 1257 case RTL_GIGA_MAC_VER_28: 1258 case RTL_GIGA_MAC_VER_31: 1259 return r8168dp_check_dash(tp); 1260 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1261 return r8168ep_check_dash(tp); 1262 default: 1263 return false; 1264 } 1265 } 1266 1267 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1268 { 1269 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1270 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1271 } 1272 1273 DECLARE_RTL_COND(rtl_efusear_cond) 1274 { 1275 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1276 } 1277 1278 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1279 { 1280 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1281 1282 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1283 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1284 } 1285 1286 static u32 rtl_get_events(struct rtl8169_private *tp) 1287 { 1288 if (rtl_is_8125(tp)) 1289 return RTL_R32(tp, IntrStatus_8125); 1290 else 1291 return RTL_R16(tp, IntrStatus); 1292 } 1293 1294 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1295 { 1296 if (rtl_is_8125(tp)) 1297 RTL_W32(tp, IntrStatus_8125, bits); 1298 else 1299 RTL_W16(tp, IntrStatus, bits); 1300 } 1301 1302 static void rtl_irq_disable(struct rtl8169_private *tp) 1303 { 1304 if (rtl_is_8125(tp)) 1305 RTL_W32(tp, IntrMask_8125, 0); 1306 else 1307 RTL_W16(tp, IntrMask, 0); 1308 tp->irq_enabled = 0; 1309 } 1310 1311 static void rtl_irq_enable(struct rtl8169_private *tp) 1312 { 1313 tp->irq_enabled = 1; 1314 if (rtl_is_8125(tp)) 1315 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1316 else 1317 RTL_W16(tp, IntrMask, tp->irq_mask); 1318 } 1319 1320 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1321 { 1322 rtl_irq_disable(tp); 1323 rtl_ack_events(tp, 0xffffffff); 1324 rtl_pci_commit(tp); 1325 } 1326 1327 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1328 { 1329 struct phy_device *phydev = tp->phydev; 1330 1331 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1332 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1333 if (phydev->speed == SPEED_1000) { 1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1335 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1336 } else if (phydev->speed == SPEED_100) { 1337 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1338 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1339 } else { 1340 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1341 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1342 } 1343 rtl_reset_packet_filter(tp); 1344 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1345 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1346 if (phydev->speed == SPEED_1000) { 1347 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1348 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1349 } else { 1350 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1351 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1352 } 1353 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1354 if (phydev->speed == SPEED_10) { 1355 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1356 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1357 } else { 1358 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1359 } 1360 } 1361 } 1362 1363 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1364 1365 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1366 { 1367 struct rtl8169_private *tp = netdev_priv(dev); 1368 1369 rtl_lock_work(tp); 1370 wol->supported = WAKE_ANY; 1371 wol->wolopts = tp->saved_wolopts; 1372 rtl_unlock_work(tp); 1373 } 1374 1375 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1376 { 1377 static const struct { 1378 u32 opt; 1379 u16 reg; 1380 u8 mask; 1381 } cfg[] = { 1382 { WAKE_PHY, Config3, LinkUp }, 1383 { WAKE_UCAST, Config5, UWF }, 1384 { WAKE_BCAST, Config5, BWF }, 1385 { WAKE_MCAST, Config5, MWF }, 1386 { WAKE_ANY, Config5, LanWake }, 1387 { WAKE_MAGIC, Config3, MagicPacket } 1388 }; 1389 unsigned int i, tmp = ARRAY_SIZE(cfg); 1390 u8 options; 1391 1392 rtl_unlock_config_regs(tp); 1393 1394 if (rtl_is_8168evl_up(tp)) { 1395 tmp--; 1396 if (wolopts & WAKE_MAGIC) 1397 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1398 MagicPacket_v2); 1399 else 1400 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1401 MagicPacket_v2); 1402 } else if (rtl_is_8125(tp)) { 1403 tmp--; 1404 if (wolopts & WAKE_MAGIC) 1405 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1406 else 1407 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1408 } 1409 1410 for (i = 0; i < tmp; i++) { 1411 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1412 if (wolopts & cfg[i].opt) 1413 options |= cfg[i].mask; 1414 RTL_W8(tp, cfg[i].reg, options); 1415 } 1416 1417 switch (tp->mac_version) { 1418 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1419 options = RTL_R8(tp, Config1) & ~PMEnable; 1420 if (wolopts) 1421 options |= PMEnable; 1422 RTL_W8(tp, Config1, options); 1423 break; 1424 case RTL_GIGA_MAC_VER_34: 1425 case RTL_GIGA_MAC_VER_37: 1426 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52: 1427 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1428 if (wolopts) 1429 options |= PME_SIGNAL; 1430 RTL_W8(tp, Config2, options); 1431 break; 1432 default: 1433 break; 1434 } 1435 1436 rtl_lock_config_regs(tp); 1437 1438 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1439 tp->dev->wol_enabled = wolopts ? 1 : 0; 1440 } 1441 1442 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1443 { 1444 struct rtl8169_private *tp = netdev_priv(dev); 1445 struct device *d = tp_to_dev(tp); 1446 1447 if (wol->wolopts & ~WAKE_ANY) 1448 return -EINVAL; 1449 1450 pm_runtime_get_noresume(d); 1451 1452 rtl_lock_work(tp); 1453 1454 tp->saved_wolopts = wol->wolopts; 1455 1456 if (pm_runtime_active(d)) 1457 __rtl8169_set_wol(tp, tp->saved_wolopts); 1458 1459 rtl_unlock_work(tp); 1460 1461 pm_runtime_put_noidle(d); 1462 1463 return 0; 1464 } 1465 1466 static void rtl8169_get_drvinfo(struct net_device *dev, 1467 struct ethtool_drvinfo *info) 1468 { 1469 struct rtl8169_private *tp = netdev_priv(dev); 1470 struct rtl_fw *rtl_fw = tp->rtl_fw; 1471 1472 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1473 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1474 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1475 if (rtl_fw) 1476 strlcpy(info->fw_version, rtl_fw->version, 1477 sizeof(info->fw_version)); 1478 } 1479 1480 static int rtl8169_get_regs_len(struct net_device *dev) 1481 { 1482 return R8169_REGS_SIZE; 1483 } 1484 1485 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1486 netdev_features_t features) 1487 { 1488 struct rtl8169_private *tp = netdev_priv(dev); 1489 1490 if (dev->mtu > TD_MSS_MAX) 1491 features &= ~NETIF_F_ALL_TSO; 1492 1493 if (dev->mtu > ETH_DATA_LEN && 1494 tp->mac_version > RTL_GIGA_MAC_VER_06) 1495 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1496 1497 return features; 1498 } 1499 1500 static int rtl8169_set_features(struct net_device *dev, 1501 netdev_features_t features) 1502 { 1503 struct rtl8169_private *tp = netdev_priv(dev); 1504 u32 rx_config; 1505 1506 rtl_lock_work(tp); 1507 1508 rx_config = RTL_R32(tp, RxConfig); 1509 if (features & NETIF_F_RXALL) 1510 rx_config |= (AcceptErr | AcceptRunt); 1511 else 1512 rx_config &= ~(AcceptErr | AcceptRunt); 1513 1514 if (rtl_is_8125(tp)) { 1515 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1516 rx_config |= RX_VLAN_8125; 1517 else 1518 rx_config &= ~RX_VLAN_8125; 1519 } 1520 1521 RTL_W32(tp, RxConfig, rx_config); 1522 1523 if (features & NETIF_F_RXCSUM) 1524 tp->cp_cmd |= RxChkSum; 1525 else 1526 tp->cp_cmd &= ~RxChkSum; 1527 1528 if (!rtl_is_8125(tp)) { 1529 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1530 tp->cp_cmd |= RxVlan; 1531 else 1532 tp->cp_cmd &= ~RxVlan; 1533 } 1534 1535 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1536 rtl_pci_commit(tp); 1537 1538 rtl_unlock_work(tp); 1539 1540 return 0; 1541 } 1542 1543 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1544 { 1545 return (skb_vlan_tag_present(skb)) ? 1546 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1547 } 1548 1549 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1550 { 1551 u32 opts2 = le32_to_cpu(desc->opts2); 1552 1553 if (opts2 & RxVlanTag) 1554 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1555 } 1556 1557 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1558 void *p) 1559 { 1560 struct rtl8169_private *tp = netdev_priv(dev); 1561 u32 __iomem *data = tp->mmio_addr; 1562 u32 *dw = p; 1563 int i; 1564 1565 rtl_lock_work(tp); 1566 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1567 memcpy_fromio(dw++, data++, 4); 1568 rtl_unlock_work(tp); 1569 } 1570 1571 static u32 rtl8169_get_msglevel(struct net_device *dev) 1572 { 1573 struct rtl8169_private *tp = netdev_priv(dev); 1574 1575 return tp->msg_enable; 1576 } 1577 1578 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1579 { 1580 struct rtl8169_private *tp = netdev_priv(dev); 1581 1582 tp->msg_enable = value; 1583 } 1584 1585 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1586 "tx_packets", 1587 "rx_packets", 1588 "tx_errors", 1589 "rx_errors", 1590 "rx_missed", 1591 "align_errors", 1592 "tx_single_collisions", 1593 "tx_multi_collisions", 1594 "unicast", 1595 "broadcast", 1596 "multicast", 1597 "tx_aborted", 1598 "tx_underrun", 1599 }; 1600 1601 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1602 { 1603 switch (sset) { 1604 case ETH_SS_STATS: 1605 return ARRAY_SIZE(rtl8169_gstrings); 1606 default: 1607 return -EOPNOTSUPP; 1608 } 1609 } 1610 1611 DECLARE_RTL_COND(rtl_counters_cond) 1612 { 1613 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1614 } 1615 1616 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1617 { 1618 dma_addr_t paddr = tp->counters_phys_addr; 1619 u32 cmd; 1620 1621 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1622 rtl_pci_commit(tp); 1623 cmd = (u64)paddr & DMA_BIT_MASK(32); 1624 RTL_W32(tp, CounterAddrLow, cmd); 1625 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1626 1627 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1628 } 1629 1630 static bool rtl8169_reset_counters(struct rtl8169_private *tp) 1631 { 1632 /* 1633 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1634 * tally counters. 1635 */ 1636 if (tp->mac_version < RTL_GIGA_MAC_VER_19) 1637 return true; 1638 1639 return rtl8169_do_counters(tp, CounterReset); 1640 } 1641 1642 static bool rtl8169_update_counters(struct rtl8169_private *tp) 1643 { 1644 u8 val = RTL_R8(tp, ChipCmd); 1645 1646 /* 1647 * Some chips are unable to dump tally counters when the receiver 1648 * is disabled. If 0xff chip may be in a PCI power-save state. 1649 */ 1650 if (!(val & CmdRxEnb) || val == 0xff) 1651 return true; 1652 1653 return rtl8169_do_counters(tp, CounterDump); 1654 } 1655 1656 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1657 { 1658 struct rtl8169_counters *counters = tp->counters; 1659 bool ret = false; 1660 1661 /* 1662 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1663 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1664 * reset by a power cycle, while the counter values collected by the 1665 * driver are reset at every driver unload/load cycle. 1666 * 1667 * To make sure the HW values returned by @get_stats64 match the SW 1668 * values, we collect the initial values at first open(*) and use them 1669 * as offsets to normalize the values returned by @get_stats64. 1670 * 1671 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1672 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1673 * set at open time by rtl_hw_start. 1674 */ 1675 1676 if (tp->tc_offset.inited) 1677 return true; 1678 1679 /* If both, reset and update fail, propagate to caller. */ 1680 if (rtl8169_reset_counters(tp)) 1681 ret = true; 1682 1683 if (rtl8169_update_counters(tp)) 1684 ret = true; 1685 1686 tp->tc_offset.tx_errors = counters->tx_errors; 1687 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1688 tp->tc_offset.tx_aborted = counters->tx_aborted; 1689 tp->tc_offset.rx_missed = counters->rx_missed; 1690 tp->tc_offset.inited = true; 1691 1692 return ret; 1693 } 1694 1695 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1696 struct ethtool_stats *stats, u64 *data) 1697 { 1698 struct rtl8169_private *tp = netdev_priv(dev); 1699 struct device *d = tp_to_dev(tp); 1700 struct rtl8169_counters *counters = tp->counters; 1701 1702 ASSERT_RTNL(); 1703 1704 pm_runtime_get_noresume(d); 1705 1706 if (pm_runtime_active(d)) 1707 rtl8169_update_counters(tp); 1708 1709 pm_runtime_put_noidle(d); 1710 1711 data[0] = le64_to_cpu(counters->tx_packets); 1712 data[1] = le64_to_cpu(counters->rx_packets); 1713 data[2] = le64_to_cpu(counters->tx_errors); 1714 data[3] = le32_to_cpu(counters->rx_errors); 1715 data[4] = le16_to_cpu(counters->rx_missed); 1716 data[5] = le16_to_cpu(counters->align_errors); 1717 data[6] = le32_to_cpu(counters->tx_one_collision); 1718 data[7] = le32_to_cpu(counters->tx_multi_collision); 1719 data[8] = le64_to_cpu(counters->rx_unicast); 1720 data[9] = le64_to_cpu(counters->rx_broadcast); 1721 data[10] = le32_to_cpu(counters->rx_multicast); 1722 data[11] = le16_to_cpu(counters->tx_aborted); 1723 data[12] = le16_to_cpu(counters->tx_underun); 1724 } 1725 1726 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1727 { 1728 switch(stringset) { 1729 case ETH_SS_STATS: 1730 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1731 break; 1732 } 1733 } 1734 1735 /* 1736 * Interrupt coalescing 1737 * 1738 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1739 * > 8169, 8168 and 810x line of chipsets 1740 * 1741 * 8169, 8168, and 8136(810x) serial chipsets support it. 1742 * 1743 * > 2 - the Tx timer unit at gigabit speed 1744 * 1745 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1746 * (0xe0) bit 1 and bit 0. 1747 * 1748 * For 8169 1749 * bit[1:0] \ speed 1000M 100M 10M 1750 * 0 0 320ns 2.56us 40.96us 1751 * 0 1 2.56us 20.48us 327.7us 1752 * 1 0 5.12us 40.96us 655.4us 1753 * 1 1 10.24us 81.92us 1.31ms 1754 * 1755 * For the other 1756 * bit[1:0] \ speed 1000M 100M 10M 1757 * 0 0 5us 2.56us 40.96us 1758 * 0 1 40us 20.48us 327.7us 1759 * 1 0 80us 40.96us 655.4us 1760 * 1 1 160us 81.92us 1.31ms 1761 */ 1762 1763 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ 1764 struct rtl_coalesce_scale { 1765 /* Rx / Tx */ 1766 u32 nsecs[2]; 1767 }; 1768 1769 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1770 struct rtl_coalesce_info { 1771 u32 speed; 1772 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ 1773 }; 1774 1775 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ 1776 #define rxtx_x1822(r, t) { \ 1777 {{(r), (t)}}, \ 1778 {{(r)*8, (t)*8}}, \ 1779 {{(r)*8*2, (t)*8*2}}, \ 1780 {{(r)*8*2*2, (t)*8*2*2}}, \ 1781 } 1782 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1783 /* speed delays: rx00 tx00 */ 1784 { SPEED_10, rxtx_x1822(40960, 40960) }, 1785 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1786 { SPEED_1000, rxtx_x1822( 320, 320) }, 1787 { 0 }, 1788 }; 1789 1790 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1791 /* speed delays: rx00 tx00 */ 1792 { SPEED_10, rxtx_x1822(40960, 40960) }, 1793 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1794 { SPEED_1000, rxtx_x1822( 5000, 5000) }, 1795 { 0 }, 1796 }; 1797 #undef rxtx_x1822 1798 1799 /* get rx/tx scale vector corresponding to current speed */ 1800 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) 1801 { 1802 struct rtl8169_private *tp = netdev_priv(dev); 1803 const struct rtl_coalesce_info *ci; 1804 1805 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1806 ci = rtl_coalesce_info_8169; 1807 else 1808 ci = rtl_coalesce_info_8168_8136; 1809 1810 for (; ci->speed; ci++) { 1811 if (tp->phydev->speed == ci->speed) 1812 return ci; 1813 } 1814 1815 return ERR_PTR(-ELNRNG); 1816 } 1817 1818 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1819 { 1820 struct rtl8169_private *tp = netdev_priv(dev); 1821 const struct rtl_coalesce_info *ci; 1822 const struct rtl_coalesce_scale *scale; 1823 struct { 1824 u32 *max_frames; 1825 u32 *usecs; 1826 } coal_settings [] = { 1827 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, 1828 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } 1829 }, *p = coal_settings; 1830 int i; 1831 u16 w; 1832 1833 if (rtl_is_8125(tp)) 1834 return -EOPNOTSUPP; 1835 1836 memset(ec, 0, sizeof(*ec)); 1837 1838 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1839 ci = rtl_coalesce_info(dev); 1840 if (IS_ERR(ci)) 1841 return PTR_ERR(ci); 1842 1843 scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; 1844 1845 /* read IntrMitigate and adjust according to scale */ 1846 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { 1847 *p->max_frames = (w & RTL_COALESCE_MASK) << 2; 1848 w >>= RTL_COALESCE_SHIFT; 1849 *p->usecs = w & RTL_COALESCE_MASK; 1850 } 1851 1852 for (i = 0; i < 2; i++) { 1853 p = coal_settings + i; 1854 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; 1855 1856 /* 1857 * ethtool_coalesce says it is illegal to set both usecs and 1858 * max_frames to 0. 1859 */ 1860 if (!*p->usecs && !*p->max_frames) 1861 *p->max_frames = 1; 1862 } 1863 1864 return 0; 1865 } 1866 1867 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ 1868 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( 1869 struct net_device *dev, u32 nsec, u16 *cp01) 1870 { 1871 const struct rtl_coalesce_info *ci; 1872 u16 i; 1873 1874 ci = rtl_coalesce_info(dev); 1875 if (IS_ERR(ci)) 1876 return ERR_CAST(ci); 1877 1878 for (i = 0; i < 4; i++) { 1879 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], 1880 ci->scalev[i].nsecs[1]); 1881 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { 1882 *cp01 = i; 1883 return &ci->scalev[i]; 1884 } 1885 } 1886 1887 return ERR_PTR(-EINVAL); 1888 } 1889 1890 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1891 { 1892 struct rtl8169_private *tp = netdev_priv(dev); 1893 const struct rtl_coalesce_scale *scale; 1894 struct { 1895 u32 frames; 1896 u32 usecs; 1897 } coal_settings [] = { 1898 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, 1899 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } 1900 }, *p = coal_settings; 1901 u16 w = 0, cp01; 1902 int i; 1903 1904 if (rtl_is_8125(tp)) 1905 return -EOPNOTSUPP; 1906 1907 scale = rtl_coalesce_choose_scale(dev, 1908 max(p[0].usecs, p[1].usecs) * 1000, &cp01); 1909 if (IS_ERR(scale)) 1910 return PTR_ERR(scale); 1911 1912 for (i = 0; i < 2; i++, p++) { 1913 u32 units; 1914 1915 /* 1916 * accept max_frames=1 we returned in rtl_get_coalesce. 1917 * accept it not only when usecs=0 because of e.g. the following scenario: 1918 * 1919 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1920 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1921 * - then user does `ethtool -C eth0 rx-usecs 100` 1922 * 1923 * since ethtool sends to kernel whole ethtool_coalesce 1924 * settings, if we do not handle rx_usecs=!0, rx_frames=1 1925 * we'll reject it below in `frames % 4 != 0`. 1926 */ 1927 if (p->frames == 1) { 1928 p->frames = 0; 1929 } 1930 1931 units = p->usecs * 1000 / scale->nsecs[i]; 1932 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) 1933 return -EINVAL; 1934 1935 w <<= RTL_COALESCE_SHIFT; 1936 w |= units; 1937 w <<= RTL_COALESCE_SHIFT; 1938 w |= p->frames >> 2; 1939 } 1940 1941 rtl_lock_work(tp); 1942 1943 RTL_W16(tp, IntrMitigate, swab16(w)); 1944 1945 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1946 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1947 rtl_pci_commit(tp); 1948 1949 rtl_unlock_work(tp); 1950 1951 return 0; 1952 } 1953 1954 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1955 { 1956 struct rtl8169_private *tp = netdev_priv(dev); 1957 struct device *d = tp_to_dev(tp); 1958 int ret; 1959 1960 if (!rtl_supports_eee(tp)) 1961 return -EOPNOTSUPP; 1962 1963 pm_runtime_get_noresume(d); 1964 1965 if (!pm_runtime_active(d)) { 1966 ret = -EOPNOTSUPP; 1967 } else { 1968 ret = phy_ethtool_get_eee(tp->phydev, data); 1969 } 1970 1971 pm_runtime_put_noidle(d); 1972 1973 return ret; 1974 } 1975 1976 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1977 { 1978 struct rtl8169_private *tp = netdev_priv(dev); 1979 struct device *d = tp_to_dev(tp); 1980 int ret; 1981 1982 if (!rtl_supports_eee(tp)) 1983 return -EOPNOTSUPP; 1984 1985 pm_runtime_get_noresume(d); 1986 1987 if (!pm_runtime_active(d)) { 1988 ret = -EOPNOTSUPP; 1989 goto out; 1990 } 1991 1992 if (dev->phydev->autoneg == AUTONEG_DISABLE || 1993 dev->phydev->duplex != DUPLEX_FULL) { 1994 ret = -EPROTONOSUPPORT; 1995 goto out; 1996 } 1997 1998 ret = phy_ethtool_set_eee(tp->phydev, data); 1999 2000 if (!ret) 2001 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 2002 MDIO_AN_EEE_ADV); 2003 out: 2004 pm_runtime_put_noidle(d); 2005 return ret; 2006 } 2007 2008 static const struct ethtool_ops rtl8169_ethtool_ops = { 2009 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2010 ETHTOOL_COALESCE_MAX_FRAMES, 2011 .get_drvinfo = rtl8169_get_drvinfo, 2012 .get_regs_len = rtl8169_get_regs_len, 2013 .get_link = ethtool_op_get_link, 2014 .get_coalesce = rtl_get_coalesce, 2015 .set_coalesce = rtl_set_coalesce, 2016 .get_msglevel = rtl8169_get_msglevel, 2017 .set_msglevel = rtl8169_set_msglevel, 2018 .get_regs = rtl8169_get_regs, 2019 .get_wol = rtl8169_get_wol, 2020 .set_wol = rtl8169_set_wol, 2021 .get_strings = rtl8169_get_strings, 2022 .get_sset_count = rtl8169_get_sset_count, 2023 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2024 .get_ts_info = ethtool_op_get_ts_info, 2025 .nway_reset = phy_ethtool_nway_reset, 2026 .get_eee = rtl8169_get_eee, 2027 .set_eee = rtl8169_set_eee, 2028 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2029 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2030 }; 2031 2032 static void rtl_enable_eee(struct rtl8169_private *tp) 2033 { 2034 struct phy_device *phydev = tp->phydev; 2035 int adv; 2036 2037 /* respect EEE advertisement the user may have set */ 2038 if (tp->eee_adv >= 0) 2039 adv = tp->eee_adv; 2040 else 2041 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2042 2043 if (adv >= 0) 2044 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2045 } 2046 2047 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2048 { 2049 /* 2050 * The driver currently handles the 8168Bf and the 8168Be identically 2051 * but they can be identified more specifically through the test below 2052 * if needed: 2053 * 2054 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2055 * 2056 * Same thing for the 8101Eb and the 8101Ec: 2057 * 2058 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2059 */ 2060 static const struct rtl_mac_info { 2061 u16 mask; 2062 u16 val; 2063 enum mac_version ver; 2064 } mac_info[] = { 2065 /* 8125 family. */ 2066 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2067 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2068 2069 /* RTL8117 */ 2070 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2071 2072 /* 8168EP family. */ 2073 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2074 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2075 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2076 2077 /* 8168H family. */ 2078 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2079 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2080 2081 /* 8168G family. */ 2082 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2083 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2084 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2085 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2086 2087 /* 8168F family. */ 2088 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2089 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2090 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2091 2092 /* 8168E family. */ 2093 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2094 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2095 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2096 2097 /* 8168D family. */ 2098 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2099 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2100 2101 /* 8168DP family. */ 2102 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2103 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2104 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2105 2106 /* 8168C family. */ 2107 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2108 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2109 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2110 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2111 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2112 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2113 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2114 2115 /* 8168B family. */ 2116 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2117 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2118 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2119 2120 /* 8101 family. */ 2121 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2122 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2123 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2124 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2125 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2126 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2127 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2128 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2129 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2130 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2131 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2132 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2133 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2134 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2135 /* FIXME: where did these entries come from ? -- FR */ 2136 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2137 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2138 2139 /* 8110 family. */ 2140 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2141 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2142 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2143 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2144 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2145 2146 /* Catch-all */ 2147 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2148 }; 2149 const struct rtl_mac_info *p = mac_info; 2150 enum mac_version ver; 2151 2152 while ((xid & p->mask) != p->val) 2153 p++; 2154 ver = p->ver; 2155 2156 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2157 if (ver == RTL_GIGA_MAC_VER_42) 2158 ver = RTL_GIGA_MAC_VER_43; 2159 else if (ver == RTL_GIGA_MAC_VER_45) 2160 ver = RTL_GIGA_MAC_VER_47; 2161 else if (ver == RTL_GIGA_MAC_VER_46) 2162 ver = RTL_GIGA_MAC_VER_48; 2163 } 2164 2165 return ver; 2166 } 2167 2168 static void rtl_release_firmware(struct rtl8169_private *tp) 2169 { 2170 if (tp->rtl_fw) { 2171 rtl_fw_release_firmware(tp->rtl_fw); 2172 kfree(tp->rtl_fw); 2173 tp->rtl_fw = NULL; 2174 } 2175 } 2176 2177 void r8169_apply_firmware(struct rtl8169_private *tp) 2178 { 2179 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2180 if (tp->rtl_fw) 2181 rtl_fw_write_firmware(tp, tp->rtl_fw); 2182 } 2183 2184 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2185 { 2186 /* Adjust EEE LED frequency */ 2187 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2188 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2189 2190 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2191 } 2192 2193 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2194 { 2195 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2196 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2197 } 2198 2199 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2200 { 2201 const u16 w[] = { 2202 addr[0] | (addr[1] << 8), 2203 addr[2] | (addr[3] << 8), 2204 addr[4] | (addr[5] << 8) 2205 }; 2206 2207 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2208 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2209 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2210 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2211 } 2212 2213 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2214 { 2215 u16 data1, data2, ioffset; 2216 2217 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2218 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2219 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2220 2221 ioffset = (data2 >> 1) & 0x7ff8; 2222 ioffset |= data2 & 0x0007; 2223 if (data1 & BIT(7)) 2224 ioffset |= BIT(15); 2225 2226 return ioffset; 2227 } 2228 2229 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2230 { 2231 set_bit(flag, tp->wk.flags); 2232 schedule_work(&tp->wk.work); 2233 } 2234 2235 static void rtl8169_init_phy(struct rtl8169_private *tp) 2236 { 2237 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2238 2239 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2240 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2241 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2242 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2243 RTL_W8(tp, 0x82, 0x01); 2244 } 2245 2246 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2247 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2248 tp->pci_dev->subsystem_device == 0xe000) 2249 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2250 2251 /* We may have called phy_speed_down before */ 2252 phy_speed_up(tp->phydev); 2253 2254 if (rtl_supports_eee(tp)) 2255 rtl_enable_eee(tp); 2256 2257 genphy_soft_reset(tp->phydev); 2258 } 2259 2260 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 2261 { 2262 rtl_lock_work(tp); 2263 2264 rtl_unlock_config_regs(tp); 2265 2266 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 2267 rtl_pci_commit(tp); 2268 2269 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2270 rtl_pci_commit(tp); 2271 2272 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2273 rtl_rar_exgmac_set(tp, addr); 2274 2275 rtl_lock_config_regs(tp); 2276 2277 rtl_unlock_work(tp); 2278 } 2279 2280 static int rtl_set_mac_address(struct net_device *dev, void *p) 2281 { 2282 struct rtl8169_private *tp = netdev_priv(dev); 2283 struct device *d = tp_to_dev(tp); 2284 int ret; 2285 2286 ret = eth_mac_addr(dev, p); 2287 if (ret) 2288 return ret; 2289 2290 pm_runtime_get_noresume(d); 2291 2292 if (pm_runtime_active(d)) 2293 rtl_rar_set(tp, dev->dev_addr); 2294 2295 pm_runtime_put_noidle(d); 2296 2297 return 0; 2298 } 2299 2300 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 2301 { 2302 switch (tp->mac_version) { 2303 case RTL_GIGA_MAC_VER_25: 2304 case RTL_GIGA_MAC_VER_26: 2305 case RTL_GIGA_MAC_VER_29: 2306 case RTL_GIGA_MAC_VER_30: 2307 case RTL_GIGA_MAC_VER_32: 2308 case RTL_GIGA_MAC_VER_33: 2309 case RTL_GIGA_MAC_VER_34: 2310 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61: 2311 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2312 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2313 break; 2314 default: 2315 break; 2316 } 2317 } 2318 2319 static void rtl_pll_power_down(struct rtl8169_private *tp) 2320 { 2321 if (r8168_check_dash(tp)) 2322 return; 2323 2324 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2325 tp->mac_version == RTL_GIGA_MAC_VER_33) 2326 rtl_ephy_write(tp, 0x19, 0xff64); 2327 2328 if (device_may_wakeup(tp_to_dev(tp))) { 2329 phy_speed_down(tp->phydev, false); 2330 rtl_wol_suspend_quirk(tp); 2331 return; 2332 } 2333 2334 switch (tp->mac_version) { 2335 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2336 case RTL_GIGA_MAC_VER_37: 2337 case RTL_GIGA_MAC_VER_39: 2338 case RTL_GIGA_MAC_VER_43: 2339 case RTL_GIGA_MAC_VER_44: 2340 case RTL_GIGA_MAC_VER_45: 2341 case RTL_GIGA_MAC_VER_46: 2342 case RTL_GIGA_MAC_VER_47: 2343 case RTL_GIGA_MAC_VER_48: 2344 case RTL_GIGA_MAC_VER_50: 2345 case RTL_GIGA_MAC_VER_51: 2346 case RTL_GIGA_MAC_VER_52: 2347 case RTL_GIGA_MAC_VER_60: 2348 case RTL_GIGA_MAC_VER_61: 2349 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2350 break; 2351 case RTL_GIGA_MAC_VER_40: 2352 case RTL_GIGA_MAC_VER_41: 2353 case RTL_GIGA_MAC_VER_49: 2354 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 2355 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2356 break; 2357 default: 2358 break; 2359 } 2360 } 2361 2362 static void rtl_pll_power_up(struct rtl8169_private *tp) 2363 { 2364 switch (tp->mac_version) { 2365 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2366 case RTL_GIGA_MAC_VER_37: 2367 case RTL_GIGA_MAC_VER_39: 2368 case RTL_GIGA_MAC_VER_43: 2369 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 2370 break; 2371 case RTL_GIGA_MAC_VER_44: 2372 case RTL_GIGA_MAC_VER_45: 2373 case RTL_GIGA_MAC_VER_46: 2374 case RTL_GIGA_MAC_VER_47: 2375 case RTL_GIGA_MAC_VER_48: 2376 case RTL_GIGA_MAC_VER_50: 2377 case RTL_GIGA_MAC_VER_51: 2378 case RTL_GIGA_MAC_VER_52: 2379 case RTL_GIGA_MAC_VER_60: 2380 case RTL_GIGA_MAC_VER_61: 2381 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2382 break; 2383 case RTL_GIGA_MAC_VER_40: 2384 case RTL_GIGA_MAC_VER_41: 2385 case RTL_GIGA_MAC_VER_49: 2386 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2387 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 2388 break; 2389 default: 2390 break; 2391 } 2392 2393 phy_resume(tp->phydev); 2394 } 2395 2396 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2397 { 2398 u32 vlan; 2399 2400 switch (tp->mac_version) { 2401 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2402 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2403 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2404 break; 2405 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2406 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2407 case RTL_GIGA_MAC_VER_38: 2408 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2409 break; 2410 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2411 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2412 break; 2413 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2414 /* VLAN flags are controlled by NETIF_F_HW_VLAN_CTAG_RX */ 2415 vlan = RTL_R32(tp, RxConfig) & RX_VLAN_8125; 2416 RTL_W32(tp, RxConfig, vlan | RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2417 break; 2418 default: 2419 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2420 break; 2421 } 2422 } 2423 2424 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2425 { 2426 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2427 } 2428 2429 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2430 { 2431 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2432 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2433 } 2434 2435 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2436 { 2437 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2438 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2439 } 2440 2441 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2442 { 2443 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2444 } 2445 2446 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2447 { 2448 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2449 } 2450 2451 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2452 { 2453 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2454 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2455 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2456 } 2457 2458 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2459 { 2460 RTL_W8(tp, MaxTxPacketSize, 0x0c); 2461 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2462 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2463 } 2464 2465 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2466 { 2467 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2468 } 2469 2470 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2471 { 2472 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2473 } 2474 2475 static void rtl_jumbo_config(struct rtl8169_private *tp) 2476 { 2477 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2478 2479 rtl_unlock_config_regs(tp); 2480 switch (tp->mac_version) { 2481 case RTL_GIGA_MAC_VER_12: 2482 case RTL_GIGA_MAC_VER_17: 2483 if (jumbo) { 2484 pcie_set_readrq(tp->pci_dev, 512); 2485 r8168b_1_hw_jumbo_enable(tp); 2486 } else { 2487 r8168b_1_hw_jumbo_disable(tp); 2488 } 2489 break; 2490 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2491 if (jumbo) { 2492 pcie_set_readrq(tp->pci_dev, 512); 2493 r8168c_hw_jumbo_enable(tp); 2494 } else { 2495 r8168c_hw_jumbo_disable(tp); 2496 } 2497 break; 2498 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2499 if (jumbo) 2500 r8168dp_hw_jumbo_enable(tp); 2501 else 2502 r8168dp_hw_jumbo_disable(tp); 2503 break; 2504 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2505 if (jumbo) { 2506 pcie_set_readrq(tp->pci_dev, 512); 2507 r8168e_hw_jumbo_enable(tp); 2508 } else { 2509 r8168e_hw_jumbo_disable(tp); 2510 } 2511 break; 2512 default: 2513 break; 2514 } 2515 rtl_lock_config_regs(tp); 2516 2517 if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2518 pcie_set_readrq(tp->pci_dev, 4096); 2519 } 2520 2521 DECLARE_RTL_COND(rtl_chipcmd_cond) 2522 { 2523 return RTL_R8(tp, ChipCmd) & CmdReset; 2524 } 2525 2526 static void rtl_hw_reset(struct rtl8169_private *tp) 2527 { 2528 RTL_W8(tp, ChipCmd, CmdReset); 2529 2530 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2531 } 2532 2533 static void rtl_request_firmware(struct rtl8169_private *tp) 2534 { 2535 struct rtl_fw *rtl_fw; 2536 2537 /* firmware loaded already or no firmware available */ 2538 if (tp->rtl_fw || !tp->fw_name) 2539 return; 2540 2541 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2542 if (!rtl_fw) { 2543 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n"); 2544 return; 2545 } 2546 2547 rtl_fw->phy_write = rtl_writephy; 2548 rtl_fw->phy_read = rtl_readphy; 2549 rtl_fw->mac_mcu_write = mac_mcu_write; 2550 rtl_fw->mac_mcu_read = mac_mcu_read; 2551 rtl_fw->fw_name = tp->fw_name; 2552 rtl_fw->dev = tp_to_dev(tp); 2553 2554 if (rtl_fw_request_firmware(rtl_fw)) 2555 kfree(rtl_fw); 2556 else 2557 tp->rtl_fw = rtl_fw; 2558 } 2559 2560 static void rtl_rx_close(struct rtl8169_private *tp) 2561 { 2562 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2563 } 2564 2565 DECLARE_RTL_COND(rtl_npq_cond) 2566 { 2567 return RTL_R8(tp, TxPoll) & NPQ; 2568 } 2569 2570 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2571 { 2572 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2573 } 2574 2575 static void rtl8169_hw_reset(struct rtl8169_private *tp) 2576 { 2577 /* Disable interrupts */ 2578 rtl8169_irq_mask_and_ack(tp); 2579 2580 rtl_rx_close(tp); 2581 2582 switch (tp->mac_version) { 2583 case RTL_GIGA_MAC_VER_27: 2584 case RTL_GIGA_MAC_VER_28: 2585 case RTL_GIGA_MAC_VER_31: 2586 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 2587 break; 2588 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2589 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2590 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2591 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 2592 break; 2593 default: 2594 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2595 udelay(100); 2596 break; 2597 } 2598 2599 rtl_hw_reset(tp); 2600 } 2601 2602 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2603 { 2604 u32 val = TX_DMA_BURST << TxDMAShift | 2605 InterFrameGap << TxInterFrameGapShift; 2606 2607 if (rtl_is_8168evl_up(tp)) 2608 val |= TXCFG_AUTO_FIFO; 2609 2610 RTL_W32(tp, TxConfig, val); 2611 } 2612 2613 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2614 { 2615 /* Low hurts. Let's disable the filtering. */ 2616 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2617 } 2618 2619 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2620 { 2621 /* 2622 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2623 * register to be written before TxDescAddrLow to work. 2624 * Switching from MMIO to I/O access fixes the issue as well. 2625 */ 2626 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2627 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2628 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2629 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2630 } 2631 2632 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) 2633 { 2634 u32 val; 2635 2636 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2637 val = 0x000fff00; 2638 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2639 val = 0x00ffff00; 2640 else 2641 return; 2642 2643 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2644 val |= 0xff; 2645 2646 RTL_W32(tp, 0x7c, val); 2647 } 2648 2649 static void rtl_set_rx_mode(struct net_device *dev) 2650 { 2651 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2652 /* Multicast hash filter */ 2653 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2654 struct rtl8169_private *tp = netdev_priv(dev); 2655 u32 tmp; 2656 2657 if (dev->flags & IFF_PROMISC) { 2658 /* Unconditionally log net taps. */ 2659 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); 2660 rx_mode |= AcceptAllPhys; 2661 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2662 dev->flags & IFF_ALLMULTI || 2663 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2664 /* accept all multicasts */ 2665 } else if (netdev_mc_empty(dev)) { 2666 rx_mode &= ~AcceptMulticast; 2667 } else { 2668 struct netdev_hw_addr *ha; 2669 2670 mc_filter[1] = mc_filter[0] = 0; 2671 netdev_for_each_mc_addr(ha, dev) { 2672 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2673 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2674 } 2675 2676 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2677 tmp = mc_filter[0]; 2678 mc_filter[0] = swab32(mc_filter[1]); 2679 mc_filter[1] = swab32(tmp); 2680 } 2681 } 2682 2683 if (dev->features & NETIF_F_RXALL) 2684 rx_mode |= (AcceptErr | AcceptRunt); 2685 2686 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2687 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2688 2689 tmp = RTL_R32(tp, RxConfig); 2690 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); 2691 } 2692 2693 DECLARE_RTL_COND(rtl_csiar_cond) 2694 { 2695 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2696 } 2697 2698 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2699 { 2700 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2701 2702 RTL_W32(tp, CSIDR, value); 2703 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2704 CSIAR_BYTE_ENABLE | func << 16); 2705 2706 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2707 } 2708 2709 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2710 { 2711 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2712 2713 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2714 CSIAR_BYTE_ENABLE); 2715 2716 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2717 RTL_R32(tp, CSIDR) : ~0; 2718 } 2719 2720 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2721 { 2722 struct pci_dev *pdev = tp->pci_dev; 2723 u32 csi; 2724 2725 /* According to Realtek the value at config space address 0x070f 2726 * controls the L0s/L1 entrance latency. We try standard ECAM access 2727 * first and if it fails fall back to CSI. 2728 */ 2729 if (pdev->cfg_size > 0x070f && 2730 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2731 return; 2732 2733 netdev_notice_once(tp->dev, 2734 "No native access to PCI extended config space, falling back to CSI\n"); 2735 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2736 rtl_csi_write(tp, 0x070c, csi | val << 24); 2737 } 2738 2739 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2740 { 2741 rtl_csi_access_enable(tp, 0x27); 2742 } 2743 2744 struct ephy_info { 2745 unsigned int offset; 2746 u16 mask; 2747 u16 bits; 2748 }; 2749 2750 static void __rtl_ephy_init(struct rtl8169_private *tp, 2751 const struct ephy_info *e, int len) 2752 { 2753 u16 w; 2754 2755 while (len-- > 0) { 2756 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2757 rtl_ephy_write(tp, e->offset, w); 2758 e++; 2759 } 2760 } 2761 2762 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2763 2764 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2765 { 2766 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2767 PCI_EXP_LNKCTL_CLKREQ_EN); 2768 } 2769 2770 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2771 { 2772 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2773 PCI_EXP_LNKCTL_CLKREQ_EN); 2774 } 2775 2776 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2777 { 2778 /* work around an issue when PCI reset occurs during L2/L3 state */ 2779 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2780 } 2781 2782 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2783 { 2784 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2785 if (enable && tp->aspm_manageable) { 2786 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2787 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2788 } else { 2789 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2790 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2791 } 2792 2793 udelay(10); 2794 } 2795 2796 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2797 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2798 { 2799 /* Usage of dynamic vs. static FIFO is controlled by bit 2800 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2801 */ 2802 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2803 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2804 } 2805 2806 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2807 u8 low, u8 high) 2808 { 2809 /* FIFO thresholds for pause flow control */ 2810 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2811 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2812 } 2813 2814 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2815 { 2816 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2817 } 2818 2819 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2820 { 2821 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2822 2823 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2824 2825 rtl_disable_clock_request(tp); 2826 } 2827 2828 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2829 { 2830 static const struct ephy_info e_info_8168cp[] = { 2831 { 0x01, 0, 0x0001 }, 2832 { 0x02, 0x0800, 0x1000 }, 2833 { 0x03, 0, 0x0042 }, 2834 { 0x06, 0x0080, 0x0000 }, 2835 { 0x07, 0, 0x2000 } 2836 }; 2837 2838 rtl_set_def_aspm_entry_latency(tp); 2839 2840 rtl_ephy_init(tp, e_info_8168cp); 2841 2842 __rtl_hw_start_8168cp(tp); 2843 } 2844 2845 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2846 { 2847 rtl_set_def_aspm_entry_latency(tp); 2848 2849 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2850 } 2851 2852 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2853 { 2854 rtl_set_def_aspm_entry_latency(tp); 2855 2856 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2857 2858 /* Magic. */ 2859 RTL_W8(tp, DBG_REG, 0x20); 2860 } 2861 2862 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2863 { 2864 static const struct ephy_info e_info_8168c_1[] = { 2865 { 0x02, 0x0800, 0x1000 }, 2866 { 0x03, 0, 0x0002 }, 2867 { 0x06, 0x0080, 0x0000 } 2868 }; 2869 2870 rtl_set_def_aspm_entry_latency(tp); 2871 2872 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2873 2874 rtl_ephy_init(tp, e_info_8168c_1); 2875 2876 __rtl_hw_start_8168cp(tp); 2877 } 2878 2879 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2880 { 2881 static const struct ephy_info e_info_8168c_2[] = { 2882 { 0x01, 0, 0x0001 }, 2883 { 0x03, 0x0400, 0x0020 } 2884 }; 2885 2886 rtl_set_def_aspm_entry_latency(tp); 2887 2888 rtl_ephy_init(tp, e_info_8168c_2); 2889 2890 __rtl_hw_start_8168cp(tp); 2891 } 2892 2893 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2894 { 2895 rtl_hw_start_8168c_2(tp); 2896 } 2897 2898 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2899 { 2900 rtl_set_def_aspm_entry_latency(tp); 2901 2902 __rtl_hw_start_8168cp(tp); 2903 } 2904 2905 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2906 { 2907 rtl_set_def_aspm_entry_latency(tp); 2908 2909 rtl_disable_clock_request(tp); 2910 } 2911 2912 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2913 { 2914 static const struct ephy_info e_info_8168d_4[] = { 2915 { 0x0b, 0x0000, 0x0048 }, 2916 { 0x19, 0x0020, 0x0050 }, 2917 { 0x0c, 0x0100, 0x0020 }, 2918 { 0x10, 0x0004, 0x0000 }, 2919 }; 2920 2921 rtl_set_def_aspm_entry_latency(tp); 2922 2923 rtl_ephy_init(tp, e_info_8168d_4); 2924 2925 rtl_enable_clock_request(tp); 2926 } 2927 2928 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2929 { 2930 static const struct ephy_info e_info_8168e_1[] = { 2931 { 0x00, 0x0200, 0x0100 }, 2932 { 0x00, 0x0000, 0x0004 }, 2933 { 0x06, 0x0002, 0x0001 }, 2934 { 0x06, 0x0000, 0x0030 }, 2935 { 0x07, 0x0000, 0x2000 }, 2936 { 0x00, 0x0000, 0x0020 }, 2937 { 0x03, 0x5800, 0x2000 }, 2938 { 0x03, 0x0000, 0x0001 }, 2939 { 0x01, 0x0800, 0x1000 }, 2940 { 0x07, 0x0000, 0x4000 }, 2941 { 0x1e, 0x0000, 0x2000 }, 2942 { 0x19, 0xffff, 0xfe6c }, 2943 { 0x0a, 0x0000, 0x0040 } 2944 }; 2945 2946 rtl_set_def_aspm_entry_latency(tp); 2947 2948 rtl_ephy_init(tp, e_info_8168e_1); 2949 2950 rtl_disable_clock_request(tp); 2951 2952 /* Reset tx FIFO pointer */ 2953 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2954 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2955 2956 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2957 } 2958 2959 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2960 { 2961 static const struct ephy_info e_info_8168e_2[] = { 2962 { 0x09, 0x0000, 0x0080 }, 2963 { 0x19, 0x0000, 0x0224 }, 2964 { 0x00, 0x0000, 0x0004 }, 2965 { 0x0c, 0x3df0, 0x0200 }, 2966 }; 2967 2968 rtl_set_def_aspm_entry_latency(tp); 2969 2970 rtl_ephy_init(tp, e_info_8168e_2); 2971 2972 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2973 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2974 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2975 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2976 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2977 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 2978 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 2979 2980 rtl_disable_clock_request(tp); 2981 2982 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2983 2984 rtl8168_config_eee_mac(tp); 2985 2986 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2987 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2988 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2989 2990 rtl_hw_aspm_clkreq_enable(tp, true); 2991 } 2992 2993 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2994 { 2995 rtl_set_def_aspm_entry_latency(tp); 2996 2997 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2998 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2999 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3000 rtl_reset_packet_filter(tp); 3001 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 3002 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 3003 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3004 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3005 3006 rtl_disable_clock_request(tp); 3007 3008 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3009 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3010 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3011 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 3012 3013 rtl8168_config_eee_mac(tp); 3014 } 3015 3016 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3017 { 3018 static const struct ephy_info e_info_8168f_1[] = { 3019 { 0x06, 0x00c0, 0x0020 }, 3020 { 0x08, 0x0001, 0x0002 }, 3021 { 0x09, 0x0000, 0x0080 }, 3022 { 0x19, 0x0000, 0x0224 }, 3023 { 0x00, 0x0000, 0x0004 }, 3024 { 0x0c, 0x3df0, 0x0200 }, 3025 }; 3026 3027 rtl_hw_start_8168f(tp); 3028 3029 rtl_ephy_init(tp, e_info_8168f_1); 3030 3031 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 3032 } 3033 3034 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3035 { 3036 static const struct ephy_info e_info_8168f_1[] = { 3037 { 0x06, 0x00c0, 0x0020 }, 3038 { 0x0f, 0xffff, 0x5200 }, 3039 { 0x19, 0x0000, 0x0224 }, 3040 { 0x00, 0x0000, 0x0004 }, 3041 { 0x0c, 0x3df0, 0x0200 }, 3042 }; 3043 3044 rtl_hw_start_8168f(tp); 3045 rtl_pcie_state_l2l3_disable(tp); 3046 3047 rtl_ephy_init(tp, e_info_8168f_1); 3048 3049 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 3050 } 3051 3052 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3053 { 3054 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3055 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3056 3057 rtl_set_def_aspm_entry_latency(tp); 3058 3059 rtl_reset_packet_filter(tp); 3060 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3061 3062 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3063 3064 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3065 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3066 3067 rtl8168_config_eee_mac(tp); 3068 3069 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 3070 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3071 3072 rtl_pcie_state_l2l3_disable(tp); 3073 } 3074 3075 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3076 { 3077 static const struct ephy_info e_info_8168g_1[] = { 3078 { 0x00, 0x0008, 0x0000 }, 3079 { 0x0c, 0x3ff0, 0x0820 }, 3080 { 0x1e, 0x0000, 0x0001 }, 3081 { 0x19, 0x8000, 0x0000 } 3082 }; 3083 3084 rtl_hw_start_8168g(tp); 3085 3086 /* disable aspm and clock request before access ephy */ 3087 rtl_hw_aspm_clkreq_enable(tp, false); 3088 rtl_ephy_init(tp, e_info_8168g_1); 3089 rtl_hw_aspm_clkreq_enable(tp, true); 3090 } 3091 3092 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3093 { 3094 static const struct ephy_info e_info_8168g_2[] = { 3095 { 0x00, 0x0008, 0x0000 }, 3096 { 0x0c, 0x3ff0, 0x0820 }, 3097 { 0x19, 0xffff, 0x7c00 }, 3098 { 0x1e, 0xffff, 0x20eb }, 3099 { 0x0d, 0xffff, 0x1666 }, 3100 { 0x00, 0xffff, 0x10a3 }, 3101 { 0x06, 0xffff, 0xf050 }, 3102 { 0x04, 0x0000, 0x0010 }, 3103 { 0x1d, 0x4000, 0x0000 }, 3104 }; 3105 3106 rtl_hw_start_8168g(tp); 3107 3108 /* disable aspm and clock request before access ephy */ 3109 rtl_hw_aspm_clkreq_enable(tp, false); 3110 rtl_ephy_init(tp, e_info_8168g_2); 3111 } 3112 3113 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3114 { 3115 static const struct ephy_info e_info_8411_2[] = { 3116 { 0x00, 0x0008, 0x0000 }, 3117 { 0x0c, 0x37d0, 0x0820 }, 3118 { 0x1e, 0x0000, 0x0001 }, 3119 { 0x19, 0x8021, 0x0000 }, 3120 { 0x1e, 0x0000, 0x2000 }, 3121 { 0x0d, 0x0100, 0x0200 }, 3122 { 0x00, 0x0000, 0x0080 }, 3123 { 0x06, 0x0000, 0x0010 }, 3124 { 0x04, 0x0000, 0x0010 }, 3125 { 0x1d, 0x0000, 0x4000 }, 3126 }; 3127 3128 rtl_hw_start_8168g(tp); 3129 3130 /* disable aspm and clock request before access ephy */ 3131 rtl_hw_aspm_clkreq_enable(tp, false); 3132 rtl_ephy_init(tp, e_info_8411_2); 3133 3134 /* The following Realtek-provided magic fixes an issue with the RX unit 3135 * getting confused after the PHY having been powered-down. 3136 */ 3137 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3138 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3139 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3140 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3141 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3142 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3143 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3144 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3145 mdelay(3); 3146 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3147 3148 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3149 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3150 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3151 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3152 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3153 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3154 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3155 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3156 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3157 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3158 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3159 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3160 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3161 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3162 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3163 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3164 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3165 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3166 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3167 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3168 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3169 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3170 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3171 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3172 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3173 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3174 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3175 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3176 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3177 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3178 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3179 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3180 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3181 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3182 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3183 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3184 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3185 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3186 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3187 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3188 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3189 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3190 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3191 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3192 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3193 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3194 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3195 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3196 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3197 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3198 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3199 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3200 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3201 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3202 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3203 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3204 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3205 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3206 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3207 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3208 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3209 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3210 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3211 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3212 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3213 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3214 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3215 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3216 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3217 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3218 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3219 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3220 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3221 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3222 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3223 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3224 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3225 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3226 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3227 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3228 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3229 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3230 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3231 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3232 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3233 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3234 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3235 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3236 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3237 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3238 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3239 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3240 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3241 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3242 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3243 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3244 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3245 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3246 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3247 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3248 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3249 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3250 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3251 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3252 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3253 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3254 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3255 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3256 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3257 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3258 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3259 3260 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3261 3262 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3263 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3264 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3265 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3266 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3267 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3268 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3269 3270 rtl_hw_aspm_clkreq_enable(tp, true); 3271 } 3272 3273 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3274 { 3275 static const struct ephy_info e_info_8168h_1[] = { 3276 { 0x1e, 0x0800, 0x0001 }, 3277 { 0x1d, 0x0000, 0x0800 }, 3278 { 0x05, 0xffff, 0x2089 }, 3279 { 0x06, 0xffff, 0x5881 }, 3280 { 0x04, 0xffff, 0x854a }, 3281 { 0x01, 0xffff, 0x068b } 3282 }; 3283 int rg_saw_cnt; 3284 3285 /* disable aspm and clock request before access ephy */ 3286 rtl_hw_aspm_clkreq_enable(tp, false); 3287 rtl_ephy_init(tp, e_info_8168h_1); 3288 3289 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3290 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3291 3292 rtl_set_def_aspm_entry_latency(tp); 3293 3294 rtl_reset_packet_filter(tp); 3295 3296 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 3297 3298 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 3299 3300 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3301 3302 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3303 3304 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3305 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3306 3307 rtl8168_config_eee_mac(tp); 3308 3309 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3310 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3311 3312 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3313 3314 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3315 3316 rtl_pcie_state_l2l3_disable(tp); 3317 3318 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3319 if (rg_saw_cnt > 0) { 3320 u16 sw_cnt_1ms_ini; 3321 3322 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3323 sw_cnt_1ms_ini &= 0x0fff; 3324 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3325 } 3326 3327 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3328 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3329 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3330 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3331 3332 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3333 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3334 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3335 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3336 3337 rtl_hw_aspm_clkreq_enable(tp, true); 3338 } 3339 3340 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3341 { 3342 rtl8168ep_stop_cmac(tp); 3343 3344 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3345 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3346 3347 rtl_set_def_aspm_entry_latency(tp); 3348 3349 rtl_reset_packet_filter(tp); 3350 3351 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 3352 3353 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3354 3355 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3356 3357 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3358 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3359 3360 rtl8168_config_eee_mac(tp); 3361 3362 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 3363 3364 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3365 3366 rtl_pcie_state_l2l3_disable(tp); 3367 } 3368 3369 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3370 { 3371 static const struct ephy_info e_info_8168ep_1[] = { 3372 { 0x00, 0xffff, 0x10ab }, 3373 { 0x06, 0xffff, 0xf030 }, 3374 { 0x08, 0xffff, 0x2006 }, 3375 { 0x0d, 0xffff, 0x1666 }, 3376 { 0x0c, 0x3ff0, 0x0000 } 3377 }; 3378 3379 /* disable aspm and clock request before access ephy */ 3380 rtl_hw_aspm_clkreq_enable(tp, false); 3381 rtl_ephy_init(tp, e_info_8168ep_1); 3382 3383 rtl_hw_start_8168ep(tp); 3384 3385 rtl_hw_aspm_clkreq_enable(tp, true); 3386 } 3387 3388 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3389 { 3390 static const struct ephy_info e_info_8168ep_2[] = { 3391 { 0x00, 0xffff, 0x10a3 }, 3392 { 0x19, 0xffff, 0xfc00 }, 3393 { 0x1e, 0xffff, 0x20ea } 3394 }; 3395 3396 /* disable aspm and clock request before access ephy */ 3397 rtl_hw_aspm_clkreq_enable(tp, false); 3398 rtl_ephy_init(tp, e_info_8168ep_2); 3399 3400 rtl_hw_start_8168ep(tp); 3401 3402 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3403 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3404 3405 rtl_hw_aspm_clkreq_enable(tp, true); 3406 } 3407 3408 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3409 { 3410 static const struct ephy_info e_info_8168ep_3[] = { 3411 { 0x00, 0x0000, 0x0080 }, 3412 { 0x0d, 0x0100, 0x0200 }, 3413 { 0x19, 0x8021, 0x0000 }, 3414 { 0x1e, 0x0000, 0x2000 }, 3415 }; 3416 3417 /* disable aspm and clock request before access ephy */ 3418 rtl_hw_aspm_clkreq_enable(tp, false); 3419 rtl_ephy_init(tp, e_info_8168ep_3); 3420 3421 rtl_hw_start_8168ep(tp); 3422 3423 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3424 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3425 3426 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3427 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3428 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3429 3430 rtl_hw_aspm_clkreq_enable(tp, true); 3431 } 3432 3433 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3434 { 3435 static const struct ephy_info e_info_8117[] = { 3436 { 0x19, 0x0040, 0x1100 }, 3437 { 0x59, 0x0040, 0x1100 }, 3438 }; 3439 int rg_saw_cnt; 3440 3441 rtl8168ep_stop_cmac(tp); 3442 3443 /* disable aspm and clock request before access ephy */ 3444 rtl_hw_aspm_clkreq_enable(tp, false); 3445 rtl_ephy_init(tp, e_info_8117); 3446 3447 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3448 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3449 3450 rtl_set_def_aspm_entry_latency(tp); 3451 3452 rtl_reset_packet_filter(tp); 3453 3454 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90); 3455 3456 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3457 3458 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3459 3460 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3461 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3462 3463 rtl8168_config_eee_mac(tp); 3464 3465 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3466 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3467 3468 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3469 3470 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3471 3472 rtl_pcie_state_l2l3_disable(tp); 3473 3474 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3475 if (rg_saw_cnt > 0) { 3476 u16 sw_cnt_1ms_ini; 3477 3478 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3479 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3480 } 3481 3482 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3483 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3484 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3485 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3486 3487 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3488 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3489 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3490 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3491 3492 /* firmware is for MAC only */ 3493 r8169_apply_firmware(tp); 3494 3495 rtl_hw_aspm_clkreq_enable(tp, true); 3496 } 3497 3498 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3499 { 3500 static const struct ephy_info e_info_8102e_1[] = { 3501 { 0x01, 0, 0x6e65 }, 3502 { 0x02, 0, 0x091f }, 3503 { 0x03, 0, 0xc2f9 }, 3504 { 0x06, 0, 0xafb5 }, 3505 { 0x07, 0, 0x0e00 }, 3506 { 0x19, 0, 0xec80 }, 3507 { 0x01, 0, 0x2e65 }, 3508 { 0x01, 0, 0x6e65 } 3509 }; 3510 u8 cfg1; 3511 3512 rtl_set_def_aspm_entry_latency(tp); 3513 3514 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3515 3516 RTL_W8(tp, Config1, 3517 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3518 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3519 3520 cfg1 = RTL_R8(tp, Config1); 3521 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3522 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3523 3524 rtl_ephy_init(tp, e_info_8102e_1); 3525 } 3526 3527 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3528 { 3529 rtl_set_def_aspm_entry_latency(tp); 3530 3531 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3532 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3533 } 3534 3535 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3536 { 3537 rtl_hw_start_8102e_2(tp); 3538 3539 rtl_ephy_write(tp, 0x03, 0xc2f9); 3540 } 3541 3542 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3543 { 3544 static const struct ephy_info e_info_8105e_1[] = { 3545 { 0x07, 0, 0x4000 }, 3546 { 0x19, 0, 0x0200 }, 3547 { 0x19, 0, 0x0020 }, 3548 { 0x1e, 0, 0x2000 }, 3549 { 0x03, 0, 0x0001 }, 3550 { 0x19, 0, 0x0100 }, 3551 { 0x19, 0, 0x0004 }, 3552 { 0x0a, 0, 0x0020 } 3553 }; 3554 3555 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3556 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3557 3558 /* Disable Early Tally Counter */ 3559 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3560 3561 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3562 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3563 3564 rtl_ephy_init(tp, e_info_8105e_1); 3565 3566 rtl_pcie_state_l2l3_disable(tp); 3567 } 3568 3569 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3570 { 3571 rtl_hw_start_8105e_1(tp); 3572 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3573 } 3574 3575 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3576 { 3577 static const struct ephy_info e_info_8402[] = { 3578 { 0x19, 0xffff, 0xff64 }, 3579 { 0x1e, 0, 0x4000 } 3580 }; 3581 3582 rtl_set_def_aspm_entry_latency(tp); 3583 3584 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3585 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3586 3587 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3588 3589 rtl_ephy_init(tp, e_info_8402); 3590 3591 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3592 rtl_reset_packet_filter(tp); 3593 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3594 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3595 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 3596 3597 /* disable EEE */ 3598 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3599 3600 rtl_pcie_state_l2l3_disable(tp); 3601 } 3602 3603 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3604 { 3605 rtl_hw_aspm_clkreq_enable(tp, false); 3606 3607 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3608 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3609 3610 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3611 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3612 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3613 3614 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3615 3616 /* disable EEE */ 3617 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3618 3619 rtl_pcie_state_l2l3_disable(tp); 3620 rtl_hw_aspm_clkreq_enable(tp, true); 3621 } 3622 3623 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3624 { 3625 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3626 } 3627 3628 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3629 { 3630 rtl_pcie_state_l2l3_disable(tp); 3631 3632 RTL_W16(tp, 0x382, 0x221b); 3633 RTL_W8(tp, 0x4500, 0); 3634 RTL_W16(tp, 0x4800, 0); 3635 3636 /* disable UPS */ 3637 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3638 3639 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3640 3641 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3642 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3643 3644 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3645 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3646 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3647 3648 /* disable new tx descriptor format */ 3649 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3650 3651 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3652 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3653 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3654 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3655 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3656 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3657 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3658 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3659 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 3660 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3661 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3662 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 3663 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3664 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3665 udelay(1); 3666 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3667 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3668 3669 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3670 3671 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3672 3673 rtl8125_config_eee_mac(tp); 3674 3675 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3676 udelay(10); 3677 } 3678 3679 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 3680 { 3681 static const struct ephy_info e_info_8125_1[] = { 3682 { 0x01, 0xffff, 0xa812 }, 3683 { 0x09, 0xffff, 0x520c }, 3684 { 0x04, 0xffff, 0xd000 }, 3685 { 0x0d, 0xffff, 0xf702 }, 3686 { 0x0a, 0xffff, 0x8653 }, 3687 { 0x06, 0xffff, 0x001e }, 3688 { 0x08, 0xffff, 0x3595 }, 3689 { 0x20, 0xffff, 0x9455 }, 3690 { 0x21, 0xffff, 0x99ff }, 3691 { 0x02, 0xffff, 0x6046 }, 3692 { 0x29, 0xffff, 0xfe00 }, 3693 { 0x23, 0xffff, 0xab62 }, 3694 3695 { 0x41, 0xffff, 0xa80c }, 3696 { 0x49, 0xffff, 0x520c }, 3697 { 0x44, 0xffff, 0xd000 }, 3698 { 0x4d, 0xffff, 0xf702 }, 3699 { 0x4a, 0xffff, 0x8653 }, 3700 { 0x46, 0xffff, 0x001e }, 3701 { 0x48, 0xffff, 0x3595 }, 3702 { 0x60, 0xffff, 0x9455 }, 3703 { 0x61, 0xffff, 0x99ff }, 3704 { 0x42, 0xffff, 0x6046 }, 3705 { 0x69, 0xffff, 0xfe00 }, 3706 { 0x63, 0xffff, 0xab62 }, 3707 }; 3708 3709 rtl_set_def_aspm_entry_latency(tp); 3710 3711 /* disable aspm and clock request before access ephy */ 3712 rtl_hw_aspm_clkreq_enable(tp, false); 3713 rtl_ephy_init(tp, e_info_8125_1); 3714 3715 rtl_hw_start_8125_common(tp); 3716 } 3717 3718 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 3719 { 3720 static const struct ephy_info e_info_8125_2[] = { 3721 { 0x04, 0xffff, 0xd000 }, 3722 { 0x0a, 0xffff, 0x8653 }, 3723 { 0x23, 0xffff, 0xab66 }, 3724 { 0x20, 0xffff, 0x9455 }, 3725 { 0x21, 0xffff, 0x99ff }, 3726 { 0x29, 0xffff, 0xfe04 }, 3727 3728 { 0x44, 0xffff, 0xd000 }, 3729 { 0x4a, 0xffff, 0x8653 }, 3730 { 0x63, 0xffff, 0xab66 }, 3731 { 0x60, 0xffff, 0x9455 }, 3732 { 0x61, 0xffff, 0x99ff }, 3733 { 0x69, 0xffff, 0xfe04 }, 3734 }; 3735 3736 rtl_set_def_aspm_entry_latency(tp); 3737 3738 /* disable aspm and clock request before access ephy */ 3739 rtl_hw_aspm_clkreq_enable(tp, false); 3740 rtl_ephy_init(tp, e_info_8125_2); 3741 3742 rtl_hw_start_8125_common(tp); 3743 } 3744 3745 static void rtl_hw_config(struct rtl8169_private *tp) 3746 { 3747 static const rtl_generic_fct hw_configs[] = { 3748 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3749 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3750 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3751 [RTL_GIGA_MAC_VER_10] = NULL, 3752 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3753 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3754 [RTL_GIGA_MAC_VER_13] = NULL, 3755 [RTL_GIGA_MAC_VER_14] = NULL, 3756 [RTL_GIGA_MAC_VER_15] = NULL, 3757 [RTL_GIGA_MAC_VER_16] = NULL, 3758 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3759 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3760 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3761 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3762 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3763 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3764 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3765 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3766 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3767 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3768 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3769 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3770 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3771 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3772 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3773 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3774 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3775 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3776 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3777 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3778 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3779 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3780 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3781 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3782 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3783 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3784 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3785 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3786 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3787 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3788 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3789 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3790 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3791 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3792 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3793 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3794 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 3795 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 3796 }; 3797 3798 if (hw_configs[tp->mac_version]) 3799 hw_configs[tp->mac_version](tp); 3800 } 3801 3802 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3803 { 3804 int i; 3805 3806 /* disable interrupt coalescing */ 3807 for (i = 0xa00; i < 0xb00; i += 4) 3808 RTL_W32(tp, i, 0); 3809 3810 rtl_hw_config(tp); 3811 } 3812 3813 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3814 { 3815 if (rtl_is_8168evl_up(tp)) 3816 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3817 else 3818 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3819 3820 rtl_hw_config(tp); 3821 3822 /* disable interrupt coalescing */ 3823 RTL_W16(tp, IntrMitigate, 0x0000); 3824 } 3825 3826 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3827 { 3828 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3829 3830 tp->cp_cmd |= PCIMulRW; 3831 3832 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3833 tp->mac_version == RTL_GIGA_MAC_VER_03) 3834 tp->cp_cmd |= EnAnaPLL; 3835 3836 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3837 3838 rtl8169_set_magic_reg(tp, tp->mac_version); 3839 3840 /* disable interrupt coalescing */ 3841 RTL_W16(tp, IntrMitigate, 0x0000); 3842 } 3843 3844 static void rtl_hw_start(struct rtl8169_private *tp) 3845 { 3846 rtl_unlock_config_regs(tp); 3847 3848 tp->cp_cmd &= CPCMD_MASK; 3849 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3850 3851 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3852 rtl_hw_start_8169(tp); 3853 else if (rtl_is_8125(tp)) 3854 rtl_hw_start_8125(tp); 3855 else 3856 rtl_hw_start_8168(tp); 3857 3858 rtl_set_rx_max_size(tp); 3859 rtl_set_rx_tx_desc_registers(tp); 3860 rtl_lock_config_regs(tp); 3861 3862 rtl_jumbo_config(tp); 3863 3864 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3865 rtl_pci_commit(tp); 3866 3867 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3868 rtl_init_rxcfg(tp); 3869 rtl_set_tx_config_registers(tp); 3870 rtl_set_rx_mode(tp->dev); 3871 rtl_irq_enable(tp); 3872 } 3873 3874 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3875 { 3876 struct rtl8169_private *tp = netdev_priv(dev); 3877 3878 dev->mtu = new_mtu; 3879 netdev_update_features(dev); 3880 rtl_jumbo_config(tp); 3881 3882 return 0; 3883 } 3884 3885 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 3886 { 3887 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3888 3889 desc->opts2 = 0; 3890 /* Force memory writes to complete before releasing descriptor */ 3891 dma_wmb(); 3892 3893 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 3894 } 3895 3896 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3897 struct RxDesc *desc) 3898 { 3899 struct device *d = tp_to_dev(tp); 3900 int node = dev_to_node(d); 3901 dma_addr_t mapping; 3902 struct page *data; 3903 3904 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3905 if (!data) 3906 return NULL; 3907 3908 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3909 if (unlikely(dma_mapping_error(d, mapping))) { 3910 if (net_ratelimit()) 3911 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); 3912 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3913 return NULL; 3914 } 3915 3916 desc->addr = cpu_to_le64(mapping); 3917 rtl8169_mark_to_asic(desc); 3918 3919 return data; 3920 } 3921 3922 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3923 { 3924 unsigned int i; 3925 3926 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3927 dma_unmap_page(tp_to_dev(tp), 3928 le64_to_cpu(tp->RxDescArray[i].addr), 3929 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3930 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3931 tp->Rx_databuff[i] = NULL; 3932 tp->RxDescArray[i].addr = 0; 3933 tp->RxDescArray[i].opts1 = 0; 3934 } 3935 } 3936 3937 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3938 { 3939 unsigned int i; 3940 3941 for (i = 0; i < NUM_RX_DESC; i++) { 3942 struct page *data; 3943 3944 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3945 if (!data) { 3946 rtl8169_rx_clear(tp); 3947 return -ENOMEM; 3948 } 3949 tp->Rx_databuff[i] = data; 3950 } 3951 3952 /* mark as last descriptor in the ring */ 3953 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3954 3955 return 0; 3956 } 3957 3958 static int rtl8169_init_ring(struct rtl8169_private *tp) 3959 { 3960 rtl8169_init_ring_indexes(tp); 3961 3962 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3963 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3964 3965 return rtl8169_rx_fill(tp); 3966 } 3967 3968 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3969 { 3970 struct ring_info *tx_skb = tp->tx_skb + entry; 3971 struct TxDesc *desc = tp->TxDescArray + entry; 3972 3973 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3974 DMA_TO_DEVICE); 3975 memset(desc, 0, sizeof(*desc)); 3976 memset(tx_skb, 0, sizeof(*tx_skb)); 3977 } 3978 3979 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3980 unsigned int n) 3981 { 3982 unsigned int i; 3983 3984 for (i = 0; i < n; i++) { 3985 unsigned int entry = (start + i) % NUM_TX_DESC; 3986 struct ring_info *tx_skb = tp->tx_skb + entry; 3987 unsigned int len = tx_skb->len; 3988 3989 if (len) { 3990 struct sk_buff *skb = tx_skb->skb; 3991 3992 rtl8169_unmap_tx_skb(tp, entry); 3993 if (skb) 3994 dev_consume_skb_any(skb); 3995 } 3996 } 3997 } 3998 3999 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4000 { 4001 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4002 tp->cur_tx = tp->dirty_tx = 0; 4003 netdev_reset_queue(tp->dev); 4004 } 4005 4006 static void rtl_reset_work(struct rtl8169_private *tp) 4007 { 4008 struct net_device *dev = tp->dev; 4009 int i; 4010 4011 napi_disable(&tp->napi); 4012 netif_stop_queue(dev); 4013 synchronize_rcu(); 4014 4015 rtl8169_hw_reset(tp); 4016 4017 for (i = 0; i < NUM_RX_DESC; i++) 4018 rtl8169_mark_to_asic(tp->RxDescArray + i); 4019 4020 rtl8169_tx_clear(tp); 4021 rtl8169_init_ring_indexes(tp); 4022 4023 napi_enable(&tp->napi); 4024 rtl_hw_start(tp); 4025 netif_wake_queue(dev); 4026 } 4027 4028 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4029 { 4030 struct rtl8169_private *tp = netdev_priv(dev); 4031 4032 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4033 } 4034 4035 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4036 void *addr, unsigned int entry, bool desc_own) 4037 { 4038 struct TxDesc *txd = tp->TxDescArray + entry; 4039 struct device *d = tp_to_dev(tp); 4040 dma_addr_t mapping; 4041 u32 opts1; 4042 int ret; 4043 4044 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4045 ret = dma_mapping_error(d, mapping); 4046 if (unlikely(ret)) { 4047 if (net_ratelimit()) 4048 netif_err(tp, drv, tp->dev, "Failed to map TX data!\n"); 4049 return ret; 4050 } 4051 4052 txd->addr = cpu_to_le64(mapping); 4053 txd->opts2 = cpu_to_le32(opts[1]); 4054 4055 opts1 = opts[0] | len; 4056 if (entry == NUM_TX_DESC - 1) 4057 opts1 |= RingEnd; 4058 if (desc_own) 4059 opts1 |= DescOwn; 4060 txd->opts1 = cpu_to_le32(opts1); 4061 4062 tp->tx_skb[entry].len = len; 4063 4064 return 0; 4065 } 4066 4067 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4068 const u32 *opts, unsigned int entry) 4069 { 4070 struct skb_shared_info *info = skb_shinfo(skb); 4071 unsigned int cur_frag; 4072 4073 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4074 const skb_frag_t *frag = info->frags + cur_frag; 4075 void *addr = skb_frag_address(frag); 4076 u32 len = skb_frag_size(frag); 4077 4078 entry = (entry + 1) % NUM_TX_DESC; 4079 4080 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4081 goto err_out; 4082 } 4083 4084 return 0; 4085 4086 err_out: 4087 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4088 return -EIO; 4089 } 4090 4091 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 4092 { 4093 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 4094 } 4095 4096 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4097 { 4098 u32 mss = skb_shinfo(skb)->gso_size; 4099 4100 if (mss) { 4101 opts[0] |= TD_LSO; 4102 opts[0] |= mss << TD0_MSS_SHIFT; 4103 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4104 const struct iphdr *ip = ip_hdr(skb); 4105 4106 if (ip->protocol == IPPROTO_TCP) 4107 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4108 else if (ip->protocol == IPPROTO_UDP) 4109 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4110 else 4111 WARN_ON_ONCE(1); 4112 } 4113 } 4114 4115 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4116 struct sk_buff *skb, u32 *opts) 4117 { 4118 u32 transport_offset = (u32)skb_transport_offset(skb); 4119 struct skb_shared_info *shinfo = skb_shinfo(skb); 4120 u32 mss = shinfo->gso_size; 4121 4122 if (mss) { 4123 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4124 opts[0] |= TD1_GTSENV4; 4125 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4126 if (skb_cow_head(skb, 0)) 4127 return false; 4128 4129 tcp_v6_gso_csum_prep(skb); 4130 opts[0] |= TD1_GTSENV6; 4131 } else { 4132 WARN_ON_ONCE(1); 4133 } 4134 4135 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4136 opts[1] |= mss << TD1_MSS_SHIFT; 4137 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4138 u8 ip_protocol; 4139 4140 switch (vlan_get_protocol(skb)) { 4141 case htons(ETH_P_IP): 4142 opts[1] |= TD1_IPv4_CS; 4143 ip_protocol = ip_hdr(skb)->protocol; 4144 break; 4145 4146 case htons(ETH_P_IPV6): 4147 opts[1] |= TD1_IPv6_CS; 4148 ip_protocol = ipv6_hdr(skb)->nexthdr; 4149 break; 4150 4151 default: 4152 ip_protocol = IPPROTO_RAW; 4153 break; 4154 } 4155 4156 if (ip_protocol == IPPROTO_TCP) 4157 opts[1] |= TD1_TCP_CS; 4158 else if (ip_protocol == IPPROTO_UDP) 4159 opts[1] |= TD1_UDP_CS; 4160 else 4161 WARN_ON_ONCE(1); 4162 4163 opts[1] |= transport_offset << TCPHO_SHIFT; 4164 } else { 4165 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 4166 return !eth_skb_pad(skb); 4167 } 4168 4169 return true; 4170 } 4171 4172 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 4173 unsigned int nr_frags) 4174 { 4175 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 4176 4177 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4178 return slots_avail > nr_frags; 4179 } 4180 4181 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4182 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4183 { 4184 switch (tp->mac_version) { 4185 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4186 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4187 return false; 4188 default: 4189 return true; 4190 } 4191 } 4192 4193 static void rtl8169_doorbell(struct rtl8169_private *tp) 4194 { 4195 if (rtl_is_8125(tp)) 4196 RTL_W16(tp, TxPoll_8125, BIT(0)); 4197 else 4198 RTL_W8(tp, TxPoll, NPQ); 4199 } 4200 4201 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4202 struct net_device *dev) 4203 { 4204 unsigned int frags = skb_shinfo(skb)->nr_frags; 4205 struct rtl8169_private *tp = netdev_priv(dev); 4206 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4207 struct TxDesc *txd_first, *txd_last; 4208 bool stop_queue, door_bell; 4209 u32 opts[2]; 4210 4211 txd_first = tp->TxDescArray + entry; 4212 4213 if (unlikely(!rtl_tx_slots_avail(tp, frags))) { 4214 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 4215 goto err_stop_0; 4216 } 4217 4218 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn)) 4219 goto err_stop_0; 4220 4221 opts[1] = rtl8169_tx_vlan_tag(skb); 4222 opts[0] = 0; 4223 4224 if (!rtl_chip_supports_csum_v2(tp)) 4225 rtl8169_tso_csum_v1(skb, opts); 4226 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4227 goto err_dma_0; 4228 4229 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4230 entry, false))) 4231 goto err_dma_0; 4232 4233 if (frags) { 4234 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4235 goto err_dma_1; 4236 entry = (entry + frags) % NUM_TX_DESC; 4237 } 4238 4239 txd_last = tp->TxDescArray + entry; 4240 txd_last->opts1 |= cpu_to_le32(LastFrag); 4241 tp->tx_skb[entry].skb = skb; 4242 4243 skb_tx_timestamp(skb); 4244 4245 /* Force memory writes to complete before releasing descriptor */ 4246 dma_wmb(); 4247 4248 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4249 4250 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4251 4252 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4253 smp_wmb(); 4254 4255 tp->cur_tx += frags + 1; 4256 4257 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 4258 if (unlikely(stop_queue)) { 4259 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4260 * not miss a ring update when it notices a stopped queue. 4261 */ 4262 smp_wmb(); 4263 netif_stop_queue(dev); 4264 door_bell = true; 4265 } 4266 4267 if (door_bell) 4268 rtl8169_doorbell(tp); 4269 4270 if (unlikely(stop_queue)) { 4271 /* Sync with rtl_tx: 4272 * - publish queue status and cur_tx ring index (write barrier) 4273 * - refresh dirty_tx ring index (read barrier). 4274 * May the current thread have a pessimistic view of the ring 4275 * status and forget to wake up queue, a racing rtl_tx thread 4276 * can't. 4277 */ 4278 smp_mb(); 4279 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 4280 netif_start_queue(dev); 4281 } 4282 4283 return NETDEV_TX_OK; 4284 4285 err_dma_1: 4286 rtl8169_unmap_tx_skb(tp, entry); 4287 err_dma_0: 4288 dev_kfree_skb_any(skb); 4289 dev->stats.tx_dropped++; 4290 return NETDEV_TX_OK; 4291 4292 err_stop_0: 4293 netif_stop_queue(dev); 4294 dev->stats.tx_dropped++; 4295 return NETDEV_TX_BUSY; 4296 } 4297 4298 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4299 { 4300 struct skb_shared_info *info = skb_shinfo(skb); 4301 unsigned int nr_frags = info->nr_frags; 4302 4303 if (!nr_frags) 4304 return UINT_MAX; 4305 4306 return skb_frag_size(info->frags + nr_frags - 1); 4307 } 4308 4309 /* Workaround for hw issues with TSO on RTL8168evl */ 4310 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4311 netdev_features_t features) 4312 { 4313 /* IPv4 header has options field */ 4314 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4315 ip_hdrlen(skb) > sizeof(struct iphdr)) 4316 features &= ~NETIF_F_ALL_TSO; 4317 4318 /* IPv4 TCP header has options field */ 4319 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4320 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4321 features &= ~NETIF_F_ALL_TSO; 4322 4323 else if (rtl_last_frag_len(skb) <= 6) 4324 features &= ~NETIF_F_ALL_TSO; 4325 4326 return features; 4327 } 4328 4329 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4330 struct net_device *dev, 4331 netdev_features_t features) 4332 { 4333 int transport_offset = skb_transport_offset(skb); 4334 struct rtl8169_private *tp = netdev_priv(dev); 4335 4336 if (skb_is_gso(skb)) { 4337 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4338 features = rtl8168evl_fix_tso(skb, features); 4339 4340 if (transport_offset > GTTCPHO_MAX && 4341 rtl_chip_supports_csum_v2(tp)) 4342 features &= ~NETIF_F_ALL_TSO; 4343 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4344 if (skb->len < ETH_ZLEN) { 4345 switch (tp->mac_version) { 4346 case RTL_GIGA_MAC_VER_11: 4347 case RTL_GIGA_MAC_VER_12: 4348 case RTL_GIGA_MAC_VER_17: 4349 case RTL_GIGA_MAC_VER_34: 4350 features &= ~NETIF_F_CSUM_MASK; 4351 break; 4352 default: 4353 break; 4354 } 4355 } 4356 4357 if (transport_offset > TCPHO_MAX && 4358 rtl_chip_supports_csum_v2(tp)) 4359 features &= ~NETIF_F_CSUM_MASK; 4360 } 4361 4362 return vlan_features_check(skb, features); 4363 } 4364 4365 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4366 { 4367 struct rtl8169_private *tp = netdev_priv(dev); 4368 struct pci_dev *pdev = tp->pci_dev; 4369 int pci_status_errs; 4370 u16 pci_cmd; 4371 4372 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4373 4374 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4375 4376 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4377 pci_cmd, pci_status_errs); 4378 4379 /* 4380 * The recovery sequence below admits a very elaborated explanation: 4381 * - it seems to work; 4382 * - I did not see what else could be done; 4383 * - it makes iop3xx happy. 4384 * 4385 * Feel free to adjust to your needs. 4386 */ 4387 if (pdev->broken_parity_status) 4388 pci_cmd &= ~PCI_COMMAND_PARITY; 4389 else 4390 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4391 4392 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4393 4394 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4395 } 4396 4397 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4398 int budget) 4399 { 4400 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 4401 4402 dirty_tx = tp->dirty_tx; 4403 smp_rmb(); 4404 4405 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) { 4406 unsigned int entry = dirty_tx % NUM_TX_DESC; 4407 struct sk_buff *skb = tp->tx_skb[entry].skb; 4408 u32 status; 4409 4410 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4411 if (status & DescOwn) 4412 break; 4413 4414 rtl8169_unmap_tx_skb(tp, entry); 4415 4416 if (skb) { 4417 pkts_compl++; 4418 bytes_compl += skb->len; 4419 napi_consume_skb(skb, budget); 4420 } 4421 dirty_tx++; 4422 } 4423 4424 if (tp->dirty_tx != dirty_tx) { 4425 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4426 4427 u64_stats_update_begin(&tp->tx_stats.syncp); 4428 tp->tx_stats.packets += pkts_compl; 4429 tp->tx_stats.bytes += bytes_compl; 4430 u64_stats_update_end(&tp->tx_stats.syncp); 4431 4432 tp->dirty_tx = dirty_tx; 4433 /* Sync with rtl8169_start_xmit: 4434 * - publish dirty_tx ring index (write barrier) 4435 * - refresh cur_tx ring index and queue status (read barrier) 4436 * May the current thread miss the stopped queue condition, 4437 * a racing xmit thread can only have a right view of the 4438 * ring status. 4439 */ 4440 smp_mb(); 4441 if (netif_queue_stopped(dev) && 4442 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 4443 netif_wake_queue(dev); 4444 } 4445 /* 4446 * 8168 hack: TxPoll requests are lost when the Tx packets are 4447 * too close. Let's kick an extra TxPoll request when a burst 4448 * of start_xmit activity is detected (if it is not detected, 4449 * it is slow enough). -- FR 4450 */ 4451 if (tp->cur_tx != dirty_tx) 4452 rtl8169_doorbell(tp); 4453 } 4454 } 4455 4456 static inline int rtl8169_fragmented_frame(u32 status) 4457 { 4458 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4459 } 4460 4461 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4462 { 4463 u32 status = opts1 & RxProtoMask; 4464 4465 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4466 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 4467 skb->ip_summed = CHECKSUM_UNNECESSARY; 4468 else 4469 skb_checksum_none_assert(skb); 4470 } 4471 4472 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 4473 { 4474 unsigned int cur_rx, rx_left; 4475 unsigned int count; 4476 4477 cur_rx = tp->cur_rx; 4478 4479 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 4480 unsigned int entry = cur_rx % NUM_RX_DESC; 4481 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 4482 struct RxDesc *desc = tp->RxDescArray + entry; 4483 u32 status; 4484 4485 status = le32_to_cpu(desc->opts1); 4486 if (status & DescOwn) 4487 break; 4488 4489 /* This barrier is needed to keep us from reading 4490 * any other fields out of the Rx descriptor until 4491 * we know the status of DescOwn 4492 */ 4493 dma_rmb(); 4494 4495 if (unlikely(status & RxRES)) { 4496 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", 4497 status); 4498 dev->stats.rx_errors++; 4499 if (status & (RxRWT | RxRUNT)) 4500 dev->stats.rx_length_errors++; 4501 if (status & RxCRC) 4502 dev->stats.rx_crc_errors++; 4503 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 4504 dev->features & NETIF_F_RXALL) { 4505 goto process_pkt; 4506 } 4507 } else { 4508 unsigned int pkt_size; 4509 struct sk_buff *skb; 4510 4511 process_pkt: 4512 pkt_size = status & GENMASK(13, 0); 4513 if (likely(!(dev->features & NETIF_F_RXFCS))) 4514 pkt_size -= ETH_FCS_LEN; 4515 /* 4516 * The driver does not support incoming fragmented 4517 * frames. They are seen as a symptom of over-mtu 4518 * sized frames. 4519 */ 4520 if (unlikely(rtl8169_fragmented_frame(status))) { 4521 dev->stats.rx_dropped++; 4522 dev->stats.rx_length_errors++; 4523 goto release_descriptor; 4524 } 4525 4526 skb = napi_alloc_skb(&tp->napi, pkt_size); 4527 if (unlikely(!skb)) { 4528 dev->stats.rx_dropped++; 4529 goto release_descriptor; 4530 } 4531 4532 dma_sync_single_for_cpu(tp_to_dev(tp), 4533 le64_to_cpu(desc->addr), 4534 pkt_size, DMA_FROM_DEVICE); 4535 prefetch(rx_buf); 4536 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4537 skb->tail += pkt_size; 4538 skb->len = pkt_size; 4539 4540 dma_sync_single_for_device(tp_to_dev(tp), 4541 le64_to_cpu(desc->addr), 4542 pkt_size, DMA_FROM_DEVICE); 4543 4544 rtl8169_rx_csum(skb, status); 4545 skb->protocol = eth_type_trans(skb, dev); 4546 4547 rtl8169_rx_vlan_tag(desc, skb); 4548 4549 if (skb->pkt_type == PACKET_MULTICAST) 4550 dev->stats.multicast++; 4551 4552 napi_gro_receive(&tp->napi, skb); 4553 4554 u64_stats_update_begin(&tp->rx_stats.syncp); 4555 tp->rx_stats.packets++; 4556 tp->rx_stats.bytes += pkt_size; 4557 u64_stats_update_end(&tp->rx_stats.syncp); 4558 } 4559 release_descriptor: 4560 rtl8169_mark_to_asic(desc); 4561 } 4562 4563 count = cur_rx - tp->cur_rx; 4564 tp->cur_rx = cur_rx; 4565 4566 return count; 4567 } 4568 4569 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4570 { 4571 struct rtl8169_private *tp = dev_instance; 4572 u32 status = rtl_get_events(tp); 4573 4574 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 4575 !(status & tp->irq_mask)) 4576 return IRQ_NONE; 4577 4578 if (unlikely(status & SYSErr)) { 4579 rtl8169_pcierr_interrupt(tp->dev); 4580 goto out; 4581 } 4582 4583 if (status & LinkChg) 4584 phy_mac_interrupt(tp->phydev); 4585 4586 if (unlikely(status & RxFIFOOver && 4587 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4588 netif_stop_queue(tp->dev); 4589 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4590 } 4591 4592 rtl_irq_disable(tp); 4593 napi_schedule_irqoff(&tp->napi); 4594 out: 4595 rtl_ack_events(tp, status); 4596 4597 return IRQ_HANDLED; 4598 } 4599 4600 static void rtl_task(struct work_struct *work) 4601 { 4602 struct rtl8169_private *tp = 4603 container_of(work, struct rtl8169_private, wk.work); 4604 4605 rtl_lock_work(tp); 4606 4607 if (!netif_running(tp->dev) || 4608 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4609 goto out_unlock; 4610 4611 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) 4612 rtl_reset_work(tp); 4613 out_unlock: 4614 rtl_unlock_work(tp); 4615 } 4616 4617 static int rtl8169_poll(struct napi_struct *napi, int budget) 4618 { 4619 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4620 struct net_device *dev = tp->dev; 4621 int work_done; 4622 4623 work_done = rtl_rx(dev, tp, (u32) budget); 4624 4625 rtl_tx(dev, tp, budget); 4626 4627 if (work_done < budget) { 4628 napi_complete_done(napi, work_done); 4629 rtl_irq_enable(tp); 4630 } 4631 4632 return work_done; 4633 } 4634 4635 static void r8169_phylink_handler(struct net_device *ndev) 4636 { 4637 struct rtl8169_private *tp = netdev_priv(ndev); 4638 4639 if (netif_carrier_ok(ndev)) { 4640 rtl_link_chg_patch(tp); 4641 pm_request_resume(&tp->pci_dev->dev); 4642 } else { 4643 pm_runtime_idle(&tp->pci_dev->dev); 4644 } 4645 4646 if (net_ratelimit()) 4647 phy_print_status(tp->phydev); 4648 } 4649 4650 static int r8169_phy_connect(struct rtl8169_private *tp) 4651 { 4652 struct phy_device *phydev = tp->phydev; 4653 phy_interface_t phy_mode; 4654 int ret; 4655 4656 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4657 PHY_INTERFACE_MODE_MII; 4658 4659 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4660 phy_mode); 4661 if (ret) 4662 return ret; 4663 4664 if (!tp->supports_gmii) 4665 phy_set_max_speed(phydev, SPEED_100); 4666 4667 phy_support_asym_pause(phydev); 4668 4669 phy_attached_info(phydev); 4670 4671 return 0; 4672 } 4673 4674 static void rtl8169_down(struct net_device *dev) 4675 { 4676 struct rtl8169_private *tp = netdev_priv(dev); 4677 4678 phy_stop(tp->phydev); 4679 4680 napi_disable(&tp->napi); 4681 netif_stop_queue(dev); 4682 4683 rtl8169_hw_reset(tp); 4684 4685 /* Give a racing hard_start_xmit a few cycles to complete. */ 4686 synchronize_rcu(); 4687 4688 rtl8169_tx_clear(tp); 4689 4690 rtl8169_rx_clear(tp); 4691 4692 rtl_pll_power_down(tp); 4693 } 4694 4695 static int rtl8169_close(struct net_device *dev) 4696 { 4697 struct rtl8169_private *tp = netdev_priv(dev); 4698 struct pci_dev *pdev = tp->pci_dev; 4699 4700 pm_runtime_get_sync(&pdev->dev); 4701 4702 /* Update counters before going down */ 4703 rtl8169_update_counters(tp); 4704 4705 rtl_lock_work(tp); 4706 /* Clear all task flags */ 4707 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4708 4709 rtl8169_down(dev); 4710 rtl_unlock_work(tp); 4711 4712 cancel_work_sync(&tp->wk.work); 4713 4714 phy_disconnect(tp->phydev); 4715 4716 pci_free_irq(pdev, 0, tp); 4717 4718 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4719 tp->RxPhyAddr); 4720 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4721 tp->TxPhyAddr); 4722 tp->TxDescArray = NULL; 4723 tp->RxDescArray = NULL; 4724 4725 pm_runtime_put_sync(&pdev->dev); 4726 4727 return 0; 4728 } 4729 4730 #ifdef CONFIG_NET_POLL_CONTROLLER 4731 static void rtl8169_netpoll(struct net_device *dev) 4732 { 4733 struct rtl8169_private *tp = netdev_priv(dev); 4734 4735 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4736 } 4737 #endif 4738 4739 static int rtl_open(struct net_device *dev) 4740 { 4741 struct rtl8169_private *tp = netdev_priv(dev); 4742 struct pci_dev *pdev = tp->pci_dev; 4743 int retval = -ENOMEM; 4744 4745 pm_runtime_get_sync(&pdev->dev); 4746 4747 /* 4748 * Rx and Tx descriptors needs 256 bytes alignment. 4749 * dma_alloc_coherent provides more. 4750 */ 4751 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4752 &tp->TxPhyAddr, GFP_KERNEL); 4753 if (!tp->TxDescArray) 4754 goto err_pm_runtime_put; 4755 4756 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4757 &tp->RxPhyAddr, GFP_KERNEL); 4758 if (!tp->RxDescArray) 4759 goto err_free_tx_0; 4760 4761 retval = rtl8169_init_ring(tp); 4762 if (retval < 0) 4763 goto err_free_rx_1; 4764 4765 rtl_request_firmware(tp); 4766 4767 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 4768 dev->name); 4769 if (retval < 0) 4770 goto err_release_fw_2; 4771 4772 retval = r8169_phy_connect(tp); 4773 if (retval) 4774 goto err_free_irq; 4775 4776 rtl_lock_work(tp); 4777 4778 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4779 4780 napi_enable(&tp->napi); 4781 4782 rtl8169_init_phy(tp); 4783 4784 rtl_pll_power_up(tp); 4785 4786 rtl_hw_start(tp); 4787 4788 if (!rtl8169_init_counter_offsets(tp)) 4789 netif_warn(tp, hw, dev, "counter reset/update failed\n"); 4790 4791 phy_start(tp->phydev); 4792 netif_start_queue(dev); 4793 4794 rtl_unlock_work(tp); 4795 4796 pm_runtime_put_sync(&pdev->dev); 4797 out: 4798 return retval; 4799 4800 err_free_irq: 4801 pci_free_irq(pdev, 0, tp); 4802 err_release_fw_2: 4803 rtl_release_firmware(tp); 4804 rtl8169_rx_clear(tp); 4805 err_free_rx_1: 4806 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4807 tp->RxPhyAddr); 4808 tp->RxDescArray = NULL; 4809 err_free_tx_0: 4810 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4811 tp->TxPhyAddr); 4812 tp->TxDescArray = NULL; 4813 err_pm_runtime_put: 4814 pm_runtime_put_noidle(&pdev->dev); 4815 goto out; 4816 } 4817 4818 static void 4819 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4820 { 4821 struct rtl8169_private *tp = netdev_priv(dev); 4822 struct pci_dev *pdev = tp->pci_dev; 4823 struct rtl8169_counters *counters = tp->counters; 4824 unsigned int start; 4825 4826 pm_runtime_get_noresume(&pdev->dev); 4827 4828 netdev_stats_to_stats64(stats, &dev->stats); 4829 4830 do { 4831 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 4832 stats->rx_packets = tp->rx_stats.packets; 4833 stats->rx_bytes = tp->rx_stats.bytes; 4834 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 4835 4836 do { 4837 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 4838 stats->tx_packets = tp->tx_stats.packets; 4839 stats->tx_bytes = tp->tx_stats.bytes; 4840 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 4841 4842 /* 4843 * Fetch additional counter values missing in stats collected by driver 4844 * from tally counters. 4845 */ 4846 if (pm_runtime_active(&pdev->dev)) 4847 rtl8169_update_counters(tp); 4848 4849 /* 4850 * Subtract values fetched during initalization. 4851 * See rtl8169_init_counter_offsets for a description why we do that. 4852 */ 4853 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4854 le64_to_cpu(tp->tc_offset.tx_errors); 4855 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4856 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4857 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4858 le16_to_cpu(tp->tc_offset.tx_aborted); 4859 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4860 le16_to_cpu(tp->tc_offset.rx_missed); 4861 4862 pm_runtime_put_noidle(&pdev->dev); 4863 } 4864 4865 static void rtl8169_net_suspend(struct net_device *dev) 4866 { 4867 struct rtl8169_private *tp = netdev_priv(dev); 4868 4869 if (!netif_running(dev)) 4870 return; 4871 4872 phy_stop(tp->phydev); 4873 netif_device_detach(dev); 4874 4875 rtl_lock_work(tp); 4876 napi_disable(&tp->napi); 4877 /* Clear all task flags */ 4878 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4879 4880 rtl_unlock_work(tp); 4881 4882 rtl_pll_power_down(tp); 4883 } 4884 4885 #ifdef CONFIG_PM 4886 4887 static int rtl8169_suspend(struct device *device) 4888 { 4889 struct net_device *dev = dev_get_drvdata(device); 4890 struct rtl8169_private *tp = netdev_priv(dev); 4891 4892 rtl8169_net_suspend(dev); 4893 clk_disable_unprepare(tp->clk); 4894 4895 return 0; 4896 } 4897 4898 static void __rtl8169_resume(struct net_device *dev) 4899 { 4900 struct rtl8169_private *tp = netdev_priv(dev); 4901 4902 netif_device_attach(dev); 4903 4904 rtl_pll_power_up(tp); 4905 rtl8169_init_phy(tp); 4906 4907 phy_start(tp->phydev); 4908 4909 rtl_lock_work(tp); 4910 napi_enable(&tp->napi); 4911 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4912 rtl_reset_work(tp); 4913 rtl_unlock_work(tp); 4914 } 4915 4916 static int rtl8169_resume(struct device *device) 4917 { 4918 struct net_device *dev = dev_get_drvdata(device); 4919 struct rtl8169_private *tp = netdev_priv(dev); 4920 4921 rtl_rar_set(tp, dev->dev_addr); 4922 4923 clk_prepare_enable(tp->clk); 4924 4925 if (netif_running(dev)) 4926 __rtl8169_resume(dev); 4927 4928 return 0; 4929 } 4930 4931 static int rtl8169_runtime_suspend(struct device *device) 4932 { 4933 struct net_device *dev = dev_get_drvdata(device); 4934 struct rtl8169_private *tp = netdev_priv(dev); 4935 4936 if (!tp->TxDescArray) 4937 return 0; 4938 4939 rtl_lock_work(tp); 4940 __rtl8169_set_wol(tp, WAKE_ANY); 4941 rtl_unlock_work(tp); 4942 4943 rtl8169_net_suspend(dev); 4944 4945 /* Update counters before going runtime suspend */ 4946 rtl8169_update_counters(tp); 4947 4948 return 0; 4949 } 4950 4951 static int rtl8169_runtime_resume(struct device *device) 4952 { 4953 struct net_device *dev = dev_get_drvdata(device); 4954 struct rtl8169_private *tp = netdev_priv(dev); 4955 4956 rtl_rar_set(tp, dev->dev_addr); 4957 4958 if (!tp->TxDescArray) 4959 return 0; 4960 4961 rtl_lock_work(tp); 4962 __rtl8169_set_wol(tp, tp->saved_wolopts); 4963 rtl_unlock_work(tp); 4964 4965 __rtl8169_resume(dev); 4966 4967 return 0; 4968 } 4969 4970 static int rtl8169_runtime_idle(struct device *device) 4971 { 4972 struct net_device *dev = dev_get_drvdata(device); 4973 4974 if (!netif_running(dev) || !netif_carrier_ok(dev)) 4975 pm_schedule_suspend(device, 10000); 4976 4977 return -EBUSY; 4978 } 4979 4980 static const struct dev_pm_ops rtl8169_pm_ops = { 4981 .suspend = rtl8169_suspend, 4982 .resume = rtl8169_resume, 4983 .freeze = rtl8169_suspend, 4984 .thaw = rtl8169_resume, 4985 .poweroff = rtl8169_suspend, 4986 .restore = rtl8169_resume, 4987 .runtime_suspend = rtl8169_runtime_suspend, 4988 .runtime_resume = rtl8169_runtime_resume, 4989 .runtime_idle = rtl8169_runtime_idle, 4990 }; 4991 4992 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 4993 4994 #else /* !CONFIG_PM */ 4995 4996 #define RTL8169_PM_OPS NULL 4997 4998 #endif /* !CONFIG_PM */ 4999 5000 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 5001 { 5002 /* WoL fails with 8168b when the receiver is disabled. */ 5003 switch (tp->mac_version) { 5004 case RTL_GIGA_MAC_VER_11: 5005 case RTL_GIGA_MAC_VER_12: 5006 case RTL_GIGA_MAC_VER_17: 5007 pci_clear_master(tp->pci_dev); 5008 5009 RTL_W8(tp, ChipCmd, CmdRxEnb); 5010 rtl_pci_commit(tp); 5011 break; 5012 default: 5013 break; 5014 } 5015 } 5016 5017 static void rtl_shutdown(struct pci_dev *pdev) 5018 { 5019 struct net_device *dev = pci_get_drvdata(pdev); 5020 struct rtl8169_private *tp = netdev_priv(dev); 5021 5022 rtl8169_net_suspend(dev); 5023 5024 /* Restore original MAC address */ 5025 rtl_rar_set(tp, dev->perm_addr); 5026 5027 rtl8169_hw_reset(tp); 5028 5029 if (system_state == SYSTEM_POWER_OFF) { 5030 if (tp->saved_wolopts) { 5031 rtl_wol_suspend_quirk(tp); 5032 rtl_wol_shutdown_quirk(tp); 5033 } 5034 5035 pci_wake_from_d3(pdev, true); 5036 pci_set_power_state(pdev, PCI_D3hot); 5037 } 5038 } 5039 5040 static void rtl_remove_one(struct pci_dev *pdev) 5041 { 5042 struct net_device *dev = pci_get_drvdata(pdev); 5043 struct rtl8169_private *tp = netdev_priv(dev); 5044 5045 if (r8168_check_dash(tp)) 5046 rtl8168_driver_stop(tp); 5047 5048 netif_napi_del(&tp->napi); 5049 5050 unregister_netdev(dev); 5051 mdiobus_unregister(tp->phydev->mdio.bus); 5052 5053 rtl_release_firmware(tp); 5054 5055 if (pci_dev_run_wake(pdev)) 5056 pm_runtime_get_noresume(&pdev->dev); 5057 5058 /* restore original MAC address */ 5059 rtl_rar_set(tp, dev->perm_addr); 5060 } 5061 5062 static const struct net_device_ops rtl_netdev_ops = { 5063 .ndo_open = rtl_open, 5064 .ndo_stop = rtl8169_close, 5065 .ndo_get_stats64 = rtl8169_get_stats64, 5066 .ndo_start_xmit = rtl8169_start_xmit, 5067 .ndo_features_check = rtl8169_features_check, 5068 .ndo_tx_timeout = rtl8169_tx_timeout, 5069 .ndo_validate_addr = eth_validate_addr, 5070 .ndo_change_mtu = rtl8169_change_mtu, 5071 .ndo_fix_features = rtl8169_fix_features, 5072 .ndo_set_features = rtl8169_set_features, 5073 .ndo_set_mac_address = rtl_set_mac_address, 5074 .ndo_do_ioctl = phy_do_ioctl_running, 5075 .ndo_set_rx_mode = rtl_set_rx_mode, 5076 #ifdef CONFIG_NET_POLL_CONTROLLER 5077 .ndo_poll_controller = rtl8169_netpoll, 5078 #endif 5079 5080 }; 5081 5082 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5083 { 5084 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5085 5086 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5087 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5088 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5089 /* special workaround needed */ 5090 tp->irq_mask |= RxFIFOOver; 5091 else 5092 tp->irq_mask |= RxOverflow; 5093 } 5094 5095 static int rtl_alloc_irq(struct rtl8169_private *tp) 5096 { 5097 unsigned int flags; 5098 5099 switch (tp->mac_version) { 5100 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5101 rtl_unlock_config_regs(tp); 5102 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5103 rtl_lock_config_regs(tp); 5104 /* fall through */ 5105 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5106 flags = PCI_IRQ_LEGACY; 5107 break; 5108 default: 5109 flags = PCI_IRQ_ALL_TYPES; 5110 break; 5111 } 5112 5113 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5114 } 5115 5116 static void rtl_read_mac_address(struct rtl8169_private *tp, 5117 u8 mac_addr[ETH_ALEN]) 5118 { 5119 /* Get MAC address */ 5120 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5121 u32 value = rtl_eri_read(tp, 0xe0); 5122 5123 mac_addr[0] = (value >> 0) & 0xff; 5124 mac_addr[1] = (value >> 8) & 0xff; 5125 mac_addr[2] = (value >> 16) & 0xff; 5126 mac_addr[3] = (value >> 24) & 0xff; 5127 5128 value = rtl_eri_read(tp, 0xe4); 5129 mac_addr[4] = (value >> 0) & 0xff; 5130 mac_addr[5] = (value >> 8) & 0xff; 5131 } else if (rtl_is_8125(tp)) { 5132 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5133 } 5134 } 5135 5136 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5137 { 5138 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5139 } 5140 5141 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 5142 { 5143 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 5144 } 5145 5146 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5147 { 5148 struct rtl8169_private *tp = mii_bus->priv; 5149 5150 if (phyaddr > 0) 5151 return -ENODEV; 5152 5153 return rtl_readphy(tp, phyreg); 5154 } 5155 5156 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5157 int phyreg, u16 val) 5158 { 5159 struct rtl8169_private *tp = mii_bus->priv; 5160 5161 if (phyaddr > 0) 5162 return -ENODEV; 5163 5164 rtl_writephy(tp, phyreg, val); 5165 5166 return 0; 5167 } 5168 5169 static int r8169_mdio_register(struct rtl8169_private *tp) 5170 { 5171 struct pci_dev *pdev = tp->pci_dev; 5172 struct mii_bus *new_bus; 5173 int ret; 5174 5175 new_bus = devm_mdiobus_alloc(&pdev->dev); 5176 if (!new_bus) 5177 return -ENOMEM; 5178 5179 new_bus->name = "r8169"; 5180 new_bus->priv = tp; 5181 new_bus->parent = &pdev->dev; 5182 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5183 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5184 5185 new_bus->read = r8169_mdio_read_reg; 5186 new_bus->write = r8169_mdio_write_reg; 5187 5188 ret = devm_mdiobus_register(new_bus); 5189 if (ret) 5190 return ret; 5191 5192 tp->phydev = mdiobus_get_phy(new_bus, 0); 5193 if (!tp->phydev) { 5194 return -ENODEV; 5195 } else if (!tp->phydev->drv) { 5196 /* Most chip versions fail with the genphy driver. 5197 * Therefore ensure that the dedicated PHY driver is loaded. 5198 */ 5199 dev_err(&pdev->dev, "realtek.ko not loaded, maybe it needs to be added to initramfs?\n"); 5200 return -EUNATCH; 5201 } 5202 5203 /* PHY will be woken up in rtl_open() */ 5204 phy_suspend(tp->phydev); 5205 5206 return 0; 5207 } 5208 5209 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5210 { 5211 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 5212 5213 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 5214 return; 5215 5216 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 5217 return; 5218 5219 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5220 msleep(1); 5221 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5222 5223 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5224 5225 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 5226 return; 5227 5228 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5229 5230 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5231 } 5232 5233 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5234 { 5235 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 5236 5237 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 5238 return; 5239 5240 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5241 msleep(1); 5242 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5243 5244 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5245 5246 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 5247 return; 5248 5249 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5250 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5251 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5252 5253 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5254 } 5255 5256 static void rtl_hw_initialize(struct rtl8169_private *tp) 5257 { 5258 switch (tp->mac_version) { 5259 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 5260 rtl8168ep_stop_cmac(tp); 5261 /* fall through */ 5262 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5263 rtl_hw_init_8168g(tp); 5264 break; 5265 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 5266 rtl_hw_init_8125(tp); 5267 break; 5268 default: 5269 break; 5270 } 5271 } 5272 5273 static int rtl_jumbo_max(struct rtl8169_private *tp) 5274 { 5275 /* Non-GBit versions don't support jumbo frames */ 5276 if (!tp->supports_gmii) 5277 return 0; 5278 5279 switch (tp->mac_version) { 5280 /* RTL8169 */ 5281 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5282 return JUMBO_7K; 5283 /* RTL8168b */ 5284 case RTL_GIGA_MAC_VER_11: 5285 case RTL_GIGA_MAC_VER_12: 5286 case RTL_GIGA_MAC_VER_17: 5287 return JUMBO_4K; 5288 /* RTL8168c */ 5289 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5290 return JUMBO_6K; 5291 default: 5292 return JUMBO_9K; 5293 } 5294 } 5295 5296 static void rtl_disable_clk(void *data) 5297 { 5298 clk_disable_unprepare(data); 5299 } 5300 5301 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5302 { 5303 struct device *d = tp_to_dev(tp); 5304 struct clk *clk; 5305 int rc; 5306 5307 clk = devm_clk_get(d, "ether_clk"); 5308 if (IS_ERR(clk)) { 5309 rc = PTR_ERR(clk); 5310 if (rc == -ENOENT) 5311 /* clk-core allows NULL (for suspend / resume) */ 5312 rc = 0; 5313 else if (rc != -EPROBE_DEFER) 5314 dev_err(d, "failed to get clk: %d\n", rc); 5315 } else { 5316 tp->clk = clk; 5317 rc = clk_prepare_enable(clk); 5318 if (rc) 5319 dev_err(d, "failed to enable clk: %d\n", rc); 5320 else 5321 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5322 } 5323 5324 return rc; 5325 } 5326 5327 static void rtl_init_mac_address(struct rtl8169_private *tp) 5328 { 5329 struct net_device *dev = tp->dev; 5330 u8 *mac_addr = dev->dev_addr; 5331 int rc; 5332 5333 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5334 if (!rc) 5335 goto done; 5336 5337 rtl_read_mac_address(tp, mac_addr); 5338 if (is_valid_ether_addr(mac_addr)) 5339 goto done; 5340 5341 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5342 if (is_valid_ether_addr(mac_addr)) 5343 goto done; 5344 5345 eth_hw_addr_random(dev); 5346 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5347 done: 5348 rtl_rar_set(tp, mac_addr); 5349 } 5350 5351 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5352 { 5353 struct rtl8169_private *tp; 5354 int jumbo_max, region, rc; 5355 enum mac_version chipset; 5356 struct net_device *dev; 5357 u16 xid; 5358 5359 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5360 if (!dev) 5361 return -ENOMEM; 5362 5363 SET_NETDEV_DEV(dev, &pdev->dev); 5364 dev->netdev_ops = &rtl_netdev_ops; 5365 tp = netdev_priv(dev); 5366 tp->dev = dev; 5367 tp->pci_dev = pdev; 5368 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 5369 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5370 tp->eee_adv = -1; 5371 tp->ocp_base = OCP_STD_PHY_BASE; 5372 5373 /* Get the *optional* external "ether_clk" used on some boards */ 5374 rc = rtl_get_ether_clk(tp); 5375 if (rc) 5376 return rc; 5377 5378 /* Disable ASPM completely as that cause random device stop working 5379 * problems as well as full system hangs for some PCIe devices users. 5380 */ 5381 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5382 PCIE_LINK_STATE_L1); 5383 tp->aspm_manageable = !rc; 5384 5385 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5386 rc = pcim_enable_device(pdev); 5387 if (rc < 0) { 5388 dev_err(&pdev->dev, "enable failure\n"); 5389 return rc; 5390 } 5391 5392 if (pcim_set_mwi(pdev) < 0) 5393 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5394 5395 /* use first MMIO region */ 5396 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5397 if (region < 0) { 5398 dev_err(&pdev->dev, "no MMIO resource found\n"); 5399 return -ENODEV; 5400 } 5401 5402 /* check for weird/broken PCI region reporting */ 5403 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5404 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5405 return -ENODEV; 5406 } 5407 5408 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5409 if (rc < 0) { 5410 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5411 return rc; 5412 } 5413 5414 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5415 5416 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5417 5418 /* Identify chip attached to board */ 5419 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5420 if (chipset == RTL_GIGA_MAC_NONE) { 5421 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid); 5422 return -ENODEV; 5423 } 5424 5425 tp->mac_version = chipset; 5426 5427 tp->cp_cmd = RTL_R16(tp, CPlusCmd); 5428 5429 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5430 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5431 dev->features |= NETIF_F_HIGHDMA; 5432 5433 rtl_init_rxcfg(tp); 5434 5435 rtl8169_irq_mask_and_ack(tp); 5436 5437 rtl_hw_initialize(tp); 5438 5439 rtl_hw_reset(tp); 5440 5441 pci_set_master(pdev); 5442 5443 rc = rtl_alloc_irq(tp); 5444 if (rc < 0) { 5445 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5446 return rc; 5447 } 5448 5449 mutex_init(&tp->wk.mutex); 5450 INIT_WORK(&tp->wk.work, rtl_task); 5451 u64_stats_init(&tp->rx_stats.syncp); 5452 u64_stats_init(&tp->tx_stats.syncp); 5453 5454 rtl_init_mac_address(tp); 5455 5456 dev->ethtool_ops = &rtl8169_ethtool_ops; 5457 5458 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5459 5460 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5461 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5462 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5463 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5464 5465 /* 5466 * Pretend we are using VLANs; This bypasses a nasty bug where 5467 * Interrupts stop flowing on high load on 8110SCd controllers. 5468 */ 5469 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5470 /* Disallow toggling */ 5471 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5472 5473 if (rtl_chip_supports_csum_v2(tp)) 5474 dev->hw_features |= NETIF_F_IPV6_CSUM; 5475 5476 dev->features |= dev->hw_features; 5477 5478 /* There has been a number of reports that using SG/TSO results in 5479 * tx timeouts. However for a lot of people SG/TSO works fine. 5480 * Therefore disable both features by default, but allow users to 5481 * enable them. Use at own risk! 5482 */ 5483 if (rtl_chip_supports_csum_v2(tp)) { 5484 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5485 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5486 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5487 } else { 5488 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5489 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5490 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5491 } 5492 5493 dev->hw_features |= NETIF_F_RXALL; 5494 dev->hw_features |= NETIF_F_RXFCS; 5495 5496 /* configure chip for default features */ 5497 rtl8169_set_features(dev, dev->features); 5498 5499 jumbo_max = rtl_jumbo_max(tp); 5500 if (jumbo_max) 5501 dev->max_mtu = jumbo_max; 5502 5503 rtl_set_irq_mask(tp); 5504 5505 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5506 5507 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5508 &tp->counters_phys_addr, 5509 GFP_KERNEL); 5510 if (!tp->counters) 5511 return -ENOMEM; 5512 5513 pci_set_drvdata(pdev, dev); 5514 5515 rc = r8169_mdio_register(tp); 5516 if (rc) 5517 return rc; 5518 5519 /* chip gets powered up in rtl_open() */ 5520 rtl_pll_power_down(tp); 5521 5522 rc = register_netdev(dev); 5523 if (rc) 5524 return rc; 5525 5526 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n", 5527 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5528 pci_irq_vector(pdev, 0)); 5529 5530 if (jumbo_max) 5531 netif_info(tp, probe, dev, 5532 "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5533 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5534 "ok" : "ko"); 5535 5536 if (r8168_check_dash(tp)) 5537 rtl8168_driver_start(tp); 5538 5539 if (pci_dev_run_wake(pdev)) 5540 pm_runtime_put_sync(&pdev->dev); 5541 5542 return 0; 5543 } 5544 5545 static struct pci_driver rtl8169_pci_driver = { 5546 .name = MODULENAME, 5547 .id_table = rtl8169_pci_tbl, 5548 .probe = rtl_init_one, 5549 .remove = rtl_remove_one, 5550 .shutdown = rtl_shutdown, 5551 .driver.pm = RTL8169_PM_OPS, 5552 }; 5553 5554 module_pci_driver(rtl8169_pci_driver); 5555