1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169_firmware.h" 35 36 #define MODULENAME "r8169" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 59 #define R8169_MSG_DEFAULT \ 60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 61 62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 64 #define MC_FILTER_LIMIT 32 65 66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 68 69 #define R8169_REGS_SIZE 256 70 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 enum mac_version { 87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */ 88 RTL_GIGA_MAC_VER_02, 89 RTL_GIGA_MAC_VER_03, 90 RTL_GIGA_MAC_VER_04, 91 RTL_GIGA_MAC_VER_05, 92 RTL_GIGA_MAC_VER_06, 93 RTL_GIGA_MAC_VER_07, 94 RTL_GIGA_MAC_VER_08, 95 RTL_GIGA_MAC_VER_09, 96 RTL_GIGA_MAC_VER_10, 97 RTL_GIGA_MAC_VER_11, 98 RTL_GIGA_MAC_VER_12, 99 RTL_GIGA_MAC_VER_13, 100 RTL_GIGA_MAC_VER_14, 101 RTL_GIGA_MAC_VER_15, 102 RTL_GIGA_MAC_VER_16, 103 RTL_GIGA_MAC_VER_17, 104 RTL_GIGA_MAC_VER_18, 105 RTL_GIGA_MAC_VER_19, 106 RTL_GIGA_MAC_VER_20, 107 RTL_GIGA_MAC_VER_21, 108 RTL_GIGA_MAC_VER_22, 109 RTL_GIGA_MAC_VER_23, 110 RTL_GIGA_MAC_VER_24, 111 RTL_GIGA_MAC_VER_25, 112 RTL_GIGA_MAC_VER_26, 113 RTL_GIGA_MAC_VER_27, 114 RTL_GIGA_MAC_VER_28, 115 RTL_GIGA_MAC_VER_29, 116 RTL_GIGA_MAC_VER_30, 117 RTL_GIGA_MAC_VER_31, 118 RTL_GIGA_MAC_VER_32, 119 RTL_GIGA_MAC_VER_33, 120 RTL_GIGA_MAC_VER_34, 121 RTL_GIGA_MAC_VER_35, 122 RTL_GIGA_MAC_VER_36, 123 RTL_GIGA_MAC_VER_37, 124 RTL_GIGA_MAC_VER_38, 125 RTL_GIGA_MAC_VER_39, 126 RTL_GIGA_MAC_VER_40, 127 RTL_GIGA_MAC_VER_41, 128 RTL_GIGA_MAC_VER_42, 129 RTL_GIGA_MAC_VER_43, 130 RTL_GIGA_MAC_VER_44, 131 RTL_GIGA_MAC_VER_45, 132 RTL_GIGA_MAC_VER_46, 133 RTL_GIGA_MAC_VER_47, 134 RTL_GIGA_MAC_VER_48, 135 RTL_GIGA_MAC_VER_49, 136 RTL_GIGA_MAC_VER_50, 137 RTL_GIGA_MAC_VER_51, 138 RTL_GIGA_MAC_VER_52, 139 RTL_GIGA_MAC_VER_60, 140 RTL_GIGA_MAC_VER_61, 141 RTL_GIGA_MAC_NONE 142 }; 143 144 #define JUMBO_1K ETH_DATA_LEN 145 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) 146 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) 147 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) 148 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) 149 150 static const struct { 151 const char *name; 152 const char *fw_name; 153 } rtl_chip_infos[] = { 154 /* PCI devices. */ 155 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 156 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 157 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 158 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 159 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 160 /* PCI-E devices. */ 161 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 162 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 163 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 164 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 165 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 166 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 167 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 168 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 169 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 170 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 171 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 172 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 173 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 174 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 175 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 176 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 177 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 178 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 179 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 180 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 181 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 182 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 183 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 184 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 185 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 186 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 187 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 188 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 189 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 190 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 191 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 192 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 193 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 194 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 195 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 196 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 197 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 198 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 199 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 200 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 201 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 202 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 203 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 204 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 205 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 206 [RTL_GIGA_MAC_VER_52] = {"RTL8117" }, 207 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 208 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 209 }; 210 211 static const struct pci_device_id rtl8169_pci_tbl[] = { 212 { PCI_VDEVICE(REALTEK, 0x2502) }, 213 { PCI_VDEVICE(REALTEK, 0x2600) }, 214 { PCI_VDEVICE(REALTEK, 0x8129) }, 215 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 216 { PCI_VDEVICE(REALTEK, 0x8161) }, 217 { PCI_VDEVICE(REALTEK, 0x8167) }, 218 { PCI_VDEVICE(REALTEK, 0x8168) }, 219 { PCI_VDEVICE(NCUBE, 0x8168) }, 220 { PCI_VDEVICE(REALTEK, 0x8169) }, 221 { PCI_VENDOR_ID_DLINK, 0x4300, 222 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 223 { PCI_VDEVICE(DLINK, 0x4300) }, 224 { PCI_VDEVICE(DLINK, 0x4302) }, 225 { PCI_VDEVICE(AT, 0xc107) }, 226 { PCI_VDEVICE(USR, 0x0116) }, 227 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 228 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 229 { PCI_VDEVICE(REALTEK, 0x8125) }, 230 { PCI_VDEVICE(REALTEK, 0x3000) }, 231 {} 232 }; 233 234 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 235 236 static struct { 237 u32 msg_enable; 238 } debug = { -1 }; 239 240 enum rtl_registers { 241 MAC0 = 0, /* Ethernet hardware address. */ 242 MAC4 = 4, 243 MAR0 = 8, /* Multicast filter. */ 244 CounterAddrLow = 0x10, 245 CounterAddrHigh = 0x14, 246 TxDescStartAddrLow = 0x20, 247 TxDescStartAddrHigh = 0x24, 248 TxHDescStartAddrLow = 0x28, 249 TxHDescStartAddrHigh = 0x2c, 250 FLASH = 0x30, 251 ERSR = 0x36, 252 ChipCmd = 0x37, 253 TxPoll = 0x38, 254 IntrMask = 0x3c, 255 IntrStatus = 0x3e, 256 257 TxConfig = 0x40, 258 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 259 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 260 261 RxConfig = 0x44, 262 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 263 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 264 #define RXCFG_FIFO_SHIFT 13 265 /* No threshold before first PCI xfer */ 266 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 267 #define RX_EARLY_OFF (1 << 11) 268 #define RXCFG_DMA_SHIFT 8 269 /* Unlimited maximum PCI burst. */ 270 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 271 272 RxMissed = 0x4c, 273 Cfg9346 = 0x50, 274 Config0 = 0x51, 275 Config1 = 0x52, 276 Config2 = 0x53, 277 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 278 279 Config3 = 0x54, 280 Config4 = 0x55, 281 Config5 = 0x56, 282 PHYAR = 0x60, 283 PHYstatus = 0x6c, 284 RxMaxSize = 0xda, 285 CPlusCmd = 0xe0, 286 IntrMitigate = 0xe2, 287 288 #define RTL_COALESCE_MASK 0x0f 289 #define RTL_COALESCE_SHIFT 4 290 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) 291 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) 292 293 RxDescAddrLow = 0xe4, 294 RxDescAddrHigh = 0xe8, 295 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 296 297 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 298 299 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 300 301 #define TxPacketMax (8064 >> 7) 302 #define EarlySize 0x27 303 304 FuncEvent = 0xf0, 305 FuncEventMask = 0xf4, 306 FuncPresetState = 0xf8, 307 IBCR0 = 0xf8, 308 IBCR2 = 0xf9, 309 IBIMR0 = 0xfa, 310 IBISR0 = 0xfb, 311 FuncForceEvent = 0xfc, 312 }; 313 314 enum rtl8168_8101_registers { 315 CSIDR = 0x64, 316 CSIAR = 0x68, 317 #define CSIAR_FLAG 0x80000000 318 #define CSIAR_WRITE_CMD 0x80000000 319 #define CSIAR_BYTE_ENABLE 0x0000f000 320 #define CSIAR_ADDR_MASK 0x00000fff 321 PMCH = 0x6f, 322 EPHYAR = 0x80, 323 #define EPHYAR_FLAG 0x80000000 324 #define EPHYAR_WRITE_CMD 0x80000000 325 #define EPHYAR_REG_MASK 0x1f 326 #define EPHYAR_REG_SHIFT 16 327 #define EPHYAR_DATA_MASK 0xffff 328 DLLPR = 0xd0, 329 #define PFM_EN (1 << 6) 330 #define TX_10M_PS_EN (1 << 7) 331 DBG_REG = 0xd1, 332 #define FIX_NAK_1 (1 << 4) 333 #define FIX_NAK_2 (1 << 3) 334 TWSI = 0xd2, 335 MCU = 0xd3, 336 #define NOW_IS_OOB (1 << 7) 337 #define TX_EMPTY (1 << 5) 338 #define RX_EMPTY (1 << 4) 339 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 340 #define EN_NDP (1 << 3) 341 #define EN_OOB_RESET (1 << 2) 342 #define LINK_LIST_RDY (1 << 1) 343 EFUSEAR = 0xdc, 344 #define EFUSEAR_FLAG 0x80000000 345 #define EFUSEAR_WRITE_CMD 0x80000000 346 #define EFUSEAR_READ_CMD 0x00000000 347 #define EFUSEAR_REG_MASK 0x03ff 348 #define EFUSEAR_REG_SHIFT 8 349 #define EFUSEAR_DATA_MASK 0xff 350 MISC_1 = 0xf2, 351 #define PFM_D3COLD_EN (1 << 6) 352 }; 353 354 enum rtl8168_registers { 355 LED_FREQ = 0x1a, 356 EEE_LED = 0x1b, 357 ERIDR = 0x70, 358 ERIAR = 0x74, 359 #define ERIAR_FLAG 0x80000000 360 #define ERIAR_WRITE_CMD 0x80000000 361 #define ERIAR_READ_CMD 0x00000000 362 #define ERIAR_ADDR_BYTE_ALIGN 4 363 #define ERIAR_TYPE_SHIFT 16 364 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 365 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 366 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 367 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 368 #define ERIAR_MASK_SHIFT 12 369 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 370 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 371 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 372 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 373 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 374 EPHY_RXER_NUM = 0x7c, 375 OCPDR = 0xb0, /* OCP GPHY access */ 376 #define OCPDR_WRITE_CMD 0x80000000 377 #define OCPDR_READ_CMD 0x00000000 378 #define OCPDR_REG_MASK 0x7f 379 #define OCPDR_GPHY_REG_SHIFT 16 380 #define OCPDR_DATA_MASK 0xffff 381 OCPAR = 0xb4, 382 #define OCPAR_FLAG 0x80000000 383 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 384 #define OCPAR_GPHY_READ_CMD 0x0000f060 385 GPHY_OCP = 0xb8, 386 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 387 MISC = 0xf0, /* 8168e only. */ 388 #define TXPLA_RST (1 << 29) 389 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 390 #define PWM_EN (1 << 22) 391 #define RXDV_GATED_EN (1 << 19) 392 #define EARLY_TALLY_EN (1 << 16) 393 }; 394 395 enum rtl8125_registers { 396 IntrMask_8125 = 0x38, 397 IntrStatus_8125 = 0x3c, 398 TxPoll_8125 = 0x90, 399 MAC0_BKP = 0x19e0, 400 }; 401 402 #define RX_VLAN_INNER_8125 BIT(22) 403 #define RX_VLAN_OUTER_8125 BIT(23) 404 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 405 406 #define RX_FETCH_DFLT_8125 (8 << 27) 407 408 enum rtl_register_content { 409 /* InterruptStatusBits */ 410 SYSErr = 0x8000, 411 PCSTimeout = 0x4000, 412 SWInt = 0x0100, 413 TxDescUnavail = 0x0080, 414 RxFIFOOver = 0x0040, 415 LinkChg = 0x0020, 416 RxOverflow = 0x0010, 417 TxErr = 0x0008, 418 TxOK = 0x0004, 419 RxErr = 0x0002, 420 RxOK = 0x0001, 421 422 /* RxStatusDesc */ 423 RxRWT = (1 << 22), 424 RxRES = (1 << 21), 425 RxRUNT = (1 << 20), 426 RxCRC = (1 << 19), 427 428 /* ChipCmdBits */ 429 StopReq = 0x80, 430 CmdReset = 0x10, 431 CmdRxEnb = 0x08, 432 CmdTxEnb = 0x04, 433 RxBufEmpty = 0x01, 434 435 /* TXPoll register p.5 */ 436 HPQ = 0x80, /* Poll cmd on the high prio queue */ 437 NPQ = 0x40, /* Poll cmd on the low prio queue */ 438 FSWInt = 0x01, /* Forced software interrupt */ 439 440 /* Cfg9346Bits */ 441 Cfg9346_Lock = 0x00, 442 Cfg9346_Unlock = 0xc0, 443 444 /* rx_mode_bits */ 445 AcceptErr = 0x20, 446 AcceptRunt = 0x10, 447 AcceptBroadcast = 0x08, 448 AcceptMulticast = 0x04, 449 AcceptMyPhys = 0x02, 450 AcceptAllPhys = 0x01, 451 #define RX_CONFIG_ACCEPT_MASK 0x3f 452 453 /* TxConfigBits */ 454 TxInterFrameGapShift = 24, 455 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 456 457 /* Config1 register p.24 */ 458 LEDS1 = (1 << 7), 459 LEDS0 = (1 << 6), 460 Speed_down = (1 << 4), 461 MEMMAP = (1 << 3), 462 IOMAP = (1 << 2), 463 VPD = (1 << 1), 464 PMEnable = (1 << 0), /* Power Management Enable */ 465 466 /* Config2 register p. 25 */ 467 ClkReqEn = (1 << 7), /* Clock Request Enable */ 468 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 469 PCI_Clock_66MHz = 0x01, 470 PCI_Clock_33MHz = 0x00, 471 472 /* Config3 register p.25 */ 473 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 474 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 475 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 476 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 477 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 478 479 /* Config4 register */ 480 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 481 482 /* Config5 register p.27 */ 483 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 484 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 485 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 486 Spi_en = (1 << 3), 487 LanWake = (1 << 1), /* LanWake enable/disable */ 488 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 489 ASPM_en = (1 << 0), /* ASPM enable */ 490 491 /* CPlusCmd p.31 */ 492 EnableBist = (1 << 15), // 8168 8101 493 Mac_dbgo_oe = (1 << 14), // 8168 8101 494 Normal_mode = (1 << 13), // unused 495 Force_half_dup = (1 << 12), // 8168 8101 496 Force_rxflow_en = (1 << 11), // 8168 8101 497 Force_txflow_en = (1 << 10), // 8168 8101 498 Cxpl_dbg_sel = (1 << 9), // 8168 8101 499 ASF = (1 << 8), // 8168 8101 500 PktCntrDisable = (1 << 7), // 8168 8101 501 Mac_dbgo_sel = 0x001c, // 8168 502 RxVlan = (1 << 6), 503 RxChkSum = (1 << 5), 504 PCIDAC = (1 << 4), 505 PCIMulRW = (1 << 3), 506 #define INTT_MASK GENMASK(1, 0) 507 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 508 509 /* rtl8169_PHYstatus */ 510 TBI_Enable = 0x80, 511 TxFlowCtrl = 0x40, 512 RxFlowCtrl = 0x20, 513 _1000bpsF = 0x10, 514 _100bps = 0x08, 515 _10bps = 0x04, 516 LinkStatus = 0x02, 517 FullDup = 0x01, 518 519 /* ResetCounterCommand */ 520 CounterReset = 0x1, 521 522 /* DumpCounterCommand */ 523 CounterDump = 0x8, 524 525 /* magic enable v2 */ 526 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 527 }; 528 529 enum rtl_desc_bit { 530 /* First doubleword. */ 531 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 532 RingEnd = (1 << 30), /* End of descriptor ring */ 533 FirstFrag = (1 << 29), /* First segment of a packet */ 534 LastFrag = (1 << 28), /* Final segment of a packet */ 535 }; 536 537 /* Generic case. */ 538 enum rtl_tx_desc_bit { 539 /* First doubleword. */ 540 TD_LSO = (1 << 27), /* Large Send Offload */ 541 #define TD_MSS_MAX 0x07ffu /* MSS value */ 542 543 /* Second doubleword. */ 544 TxVlanTag = (1 << 17), /* Add VLAN tag */ 545 }; 546 547 /* 8169, 8168b and 810x except 8102e. */ 548 enum rtl_tx_desc_bit_0 { 549 /* First doubleword. */ 550 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 551 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 552 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 553 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 554 }; 555 556 /* 8102e, 8168c and beyond. */ 557 enum rtl_tx_desc_bit_1 { 558 /* First doubleword. */ 559 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 560 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 561 #define GTTCPHO_SHIFT 18 562 #define GTTCPHO_MAX 0x7f 563 564 /* Second doubleword. */ 565 #define TCPHO_SHIFT 18 566 #define TCPHO_MAX 0x3ff 567 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 568 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 569 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 570 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 571 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 572 }; 573 574 enum rtl_rx_desc_bit { 575 /* Rx private */ 576 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 577 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 578 579 #define RxProtoUDP (PID1) 580 #define RxProtoTCP (PID0) 581 #define RxProtoIP (PID1 | PID0) 582 #define RxProtoMask RxProtoIP 583 584 IPFail = (1 << 16), /* IP checksum failed */ 585 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 586 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 587 RxVlanTag = (1 << 16), /* VLAN tag available */ 588 }; 589 590 #define RsvdMask 0x3fffc000 591 592 #define RTL_GSO_MAX_SIZE_V1 32000 593 #define RTL_GSO_MAX_SEGS_V1 24 594 #define RTL_GSO_MAX_SIZE_V2 64000 595 #define RTL_GSO_MAX_SEGS_V2 64 596 597 struct TxDesc { 598 __le32 opts1; 599 __le32 opts2; 600 __le64 addr; 601 }; 602 603 struct RxDesc { 604 __le32 opts1; 605 __le32 opts2; 606 __le64 addr; 607 }; 608 609 struct ring_info { 610 struct sk_buff *skb; 611 u32 len; 612 }; 613 614 struct rtl8169_counters { 615 __le64 tx_packets; 616 __le64 rx_packets; 617 __le64 tx_errors; 618 __le32 rx_errors; 619 __le16 rx_missed; 620 __le16 align_errors; 621 __le32 tx_one_collision; 622 __le32 tx_multi_collision; 623 __le64 rx_unicast; 624 __le64 rx_broadcast; 625 __le32 rx_multicast; 626 __le16 tx_aborted; 627 __le16 tx_underun; 628 }; 629 630 struct rtl8169_tc_offsets { 631 bool inited; 632 __le64 tx_errors; 633 __le32 tx_multi_collision; 634 __le16 tx_aborted; 635 }; 636 637 enum rtl_flag { 638 RTL_FLAG_TASK_ENABLED = 0, 639 RTL_FLAG_TASK_RESET_PENDING, 640 RTL_FLAG_MAX 641 }; 642 643 struct rtl8169_stats { 644 u64 packets; 645 u64 bytes; 646 struct u64_stats_sync syncp; 647 }; 648 649 struct rtl8169_private { 650 void __iomem *mmio_addr; /* memory map physical address */ 651 struct pci_dev *pci_dev; 652 struct net_device *dev; 653 struct phy_device *phydev; 654 struct napi_struct napi; 655 u32 msg_enable; 656 enum mac_version mac_version; 657 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 658 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 659 u32 dirty_tx; 660 struct rtl8169_stats rx_stats; 661 struct rtl8169_stats tx_stats; 662 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 663 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 664 dma_addr_t TxPhyAddr; 665 dma_addr_t RxPhyAddr; 666 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 667 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 668 u16 cp_cmd; 669 u32 irq_mask; 670 struct clk *clk; 671 672 struct { 673 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 674 struct mutex mutex; 675 struct work_struct work; 676 } wk; 677 678 unsigned irq_enabled:1; 679 unsigned supports_gmii:1; 680 unsigned aspm_manageable:1; 681 dma_addr_t counters_phys_addr; 682 struct rtl8169_counters *counters; 683 struct rtl8169_tc_offsets tc_offset; 684 u32 saved_wolopts; 685 int eee_adv; 686 687 const char *fw_name; 688 struct rtl_fw *rtl_fw; 689 690 u32 ocp_base; 691 }; 692 693 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 694 695 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 696 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 697 module_param_named(debug, debug.msg_enable, int, 0); 698 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 699 MODULE_SOFTDEP("pre: realtek"); 700 MODULE_LICENSE("GPL"); 701 MODULE_FIRMWARE(FIRMWARE_8168D_1); 702 MODULE_FIRMWARE(FIRMWARE_8168D_2); 703 MODULE_FIRMWARE(FIRMWARE_8168E_1); 704 MODULE_FIRMWARE(FIRMWARE_8168E_2); 705 MODULE_FIRMWARE(FIRMWARE_8168E_3); 706 MODULE_FIRMWARE(FIRMWARE_8105E_1); 707 MODULE_FIRMWARE(FIRMWARE_8168F_1); 708 MODULE_FIRMWARE(FIRMWARE_8168F_2); 709 MODULE_FIRMWARE(FIRMWARE_8402_1); 710 MODULE_FIRMWARE(FIRMWARE_8411_1); 711 MODULE_FIRMWARE(FIRMWARE_8411_2); 712 MODULE_FIRMWARE(FIRMWARE_8106E_1); 713 MODULE_FIRMWARE(FIRMWARE_8106E_2); 714 MODULE_FIRMWARE(FIRMWARE_8168G_2); 715 MODULE_FIRMWARE(FIRMWARE_8168G_3); 716 MODULE_FIRMWARE(FIRMWARE_8168H_1); 717 MODULE_FIRMWARE(FIRMWARE_8168H_2); 718 MODULE_FIRMWARE(FIRMWARE_8107E_1); 719 MODULE_FIRMWARE(FIRMWARE_8107E_2); 720 MODULE_FIRMWARE(FIRMWARE_8125A_3); 721 722 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 723 { 724 return &tp->pci_dev->dev; 725 } 726 727 static void rtl_lock_work(struct rtl8169_private *tp) 728 { 729 mutex_lock(&tp->wk.mutex); 730 } 731 732 static void rtl_unlock_work(struct rtl8169_private *tp) 733 { 734 mutex_unlock(&tp->wk.mutex); 735 } 736 737 static void rtl_lock_config_regs(struct rtl8169_private *tp) 738 { 739 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 740 } 741 742 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 743 { 744 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 745 } 746 747 static bool rtl_is_8125(struct rtl8169_private *tp) 748 { 749 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 750 } 751 752 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 753 { 754 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 755 tp->mac_version != RTL_GIGA_MAC_VER_39 && 756 tp->mac_version <= RTL_GIGA_MAC_VER_52; 757 } 758 759 static bool rtl_supports_eee(struct rtl8169_private *tp) 760 { 761 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 762 tp->mac_version != RTL_GIGA_MAC_VER_37 && 763 tp->mac_version != RTL_GIGA_MAC_VER_39; 764 } 765 766 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 767 { 768 int i; 769 770 for (i = 0; i < ETH_ALEN; i++) 771 mac[i] = RTL_R8(tp, reg + i); 772 } 773 774 struct rtl_cond { 775 bool (*check)(struct rtl8169_private *); 776 const char *msg; 777 }; 778 779 static void rtl_udelay(unsigned int d) 780 { 781 udelay(d); 782 } 783 784 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 785 void (*delay)(unsigned int), unsigned int d, int n, 786 bool high) 787 { 788 int i; 789 790 for (i = 0; i < n; i++) { 791 if (c->check(tp) == high) 792 return true; 793 delay(d); 794 } 795 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", 796 c->msg, !high, n, d); 797 return false; 798 } 799 800 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 801 const struct rtl_cond *c, 802 unsigned int d, int n) 803 { 804 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 805 } 806 807 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 808 const struct rtl_cond *c, 809 unsigned int d, int n) 810 { 811 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 812 } 813 814 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 815 const struct rtl_cond *c, 816 unsigned int d, int n) 817 { 818 return rtl_loop_wait(tp, c, msleep, d, n, true); 819 } 820 821 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 822 const struct rtl_cond *c, 823 unsigned int d, int n) 824 { 825 return rtl_loop_wait(tp, c, msleep, d, n, false); 826 } 827 828 #define DECLARE_RTL_COND(name) \ 829 static bool name ## _check(struct rtl8169_private *); \ 830 \ 831 static const struct rtl_cond name = { \ 832 .check = name ## _check, \ 833 .msg = #name \ 834 }; \ 835 \ 836 static bool name ## _check(struct rtl8169_private *tp) 837 838 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 839 { 840 if (reg & 0xffff0001) { 841 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); 842 return true; 843 } 844 return false; 845 } 846 847 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 848 { 849 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 850 } 851 852 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 853 { 854 if (rtl_ocp_reg_failure(tp, reg)) 855 return; 856 857 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 858 859 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 860 } 861 862 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 863 { 864 if (rtl_ocp_reg_failure(tp, reg)) 865 return 0; 866 867 RTL_W32(tp, GPHY_OCP, reg << 15); 868 869 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 870 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 871 } 872 873 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 874 { 875 if (rtl_ocp_reg_failure(tp, reg)) 876 return; 877 878 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 879 } 880 881 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 882 { 883 if (rtl_ocp_reg_failure(tp, reg)) 884 return 0; 885 886 RTL_W32(tp, OCPDR, reg << 15); 887 888 return RTL_R32(tp, OCPDR); 889 } 890 891 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 892 u16 set) 893 { 894 u16 data = r8168_mac_ocp_read(tp, reg); 895 896 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 897 } 898 899 #define OCP_STD_PHY_BASE 0xa400 900 901 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 902 { 903 if (reg == 0x1f) { 904 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 905 return; 906 } 907 908 if (tp->ocp_base != OCP_STD_PHY_BASE) 909 reg -= 0x10; 910 911 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 912 } 913 914 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 915 { 916 if (reg == 0x1f) 917 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 918 919 if (tp->ocp_base != OCP_STD_PHY_BASE) 920 reg -= 0x10; 921 922 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 923 } 924 925 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 926 { 927 if (reg == 0x1f) { 928 tp->ocp_base = value << 4; 929 return; 930 } 931 932 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 933 } 934 935 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 936 { 937 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 938 } 939 940 DECLARE_RTL_COND(rtl_phyar_cond) 941 { 942 return RTL_R32(tp, PHYAR) & 0x80000000; 943 } 944 945 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 946 { 947 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 948 949 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 950 /* 951 * According to hardware specs a 20us delay is required after write 952 * complete indication, but before sending next command. 953 */ 954 udelay(20); 955 } 956 957 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 958 { 959 int value; 960 961 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 962 963 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 964 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 965 966 /* 967 * According to hardware specs a 20us delay is required after read 968 * complete indication, but before sending next command. 969 */ 970 udelay(20); 971 972 return value; 973 } 974 975 DECLARE_RTL_COND(rtl_ocpar_cond) 976 { 977 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 978 } 979 980 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 981 { 982 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 983 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 984 RTL_W32(tp, EPHY_RXER_NUM, 0); 985 986 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 987 } 988 989 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 990 { 991 r8168dp_1_mdio_access(tp, reg, 992 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 993 } 994 995 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 996 { 997 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 998 999 mdelay(1); 1000 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 1001 RTL_W32(tp, EPHY_RXER_NUM, 0); 1002 1003 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 1004 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 1005 } 1006 1007 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1008 1009 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1010 { 1011 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1012 } 1013 1014 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1015 { 1016 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1017 } 1018 1019 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1020 { 1021 r8168dp_2_mdio_start(tp); 1022 1023 r8169_mdio_write(tp, reg, value); 1024 1025 r8168dp_2_mdio_stop(tp); 1026 } 1027 1028 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1029 { 1030 int value; 1031 1032 /* Work around issue with chip reporting wrong PHY ID */ 1033 if (reg == MII_PHYSID2) 1034 return 0xc912; 1035 1036 r8168dp_2_mdio_start(tp); 1037 1038 value = r8169_mdio_read(tp, reg); 1039 1040 r8168dp_2_mdio_stop(tp); 1041 1042 return value; 1043 } 1044 1045 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1046 { 1047 switch (tp->mac_version) { 1048 case RTL_GIGA_MAC_VER_27: 1049 r8168dp_1_mdio_write(tp, location, val); 1050 break; 1051 case RTL_GIGA_MAC_VER_28: 1052 case RTL_GIGA_MAC_VER_31: 1053 r8168dp_2_mdio_write(tp, location, val); 1054 break; 1055 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1056 r8168g_mdio_write(tp, location, val); 1057 break; 1058 default: 1059 r8169_mdio_write(tp, location, val); 1060 break; 1061 } 1062 } 1063 1064 static int rtl_readphy(struct rtl8169_private *tp, int location) 1065 { 1066 switch (tp->mac_version) { 1067 case RTL_GIGA_MAC_VER_27: 1068 return r8168dp_1_mdio_read(tp, location); 1069 case RTL_GIGA_MAC_VER_28: 1070 case RTL_GIGA_MAC_VER_31: 1071 return r8168dp_2_mdio_read(tp, location); 1072 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1073 return r8168g_mdio_read(tp, location); 1074 default: 1075 return r8169_mdio_read(tp, location); 1076 } 1077 } 1078 1079 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) 1080 { 1081 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); 1082 } 1083 1084 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) 1085 { 1086 int val; 1087 1088 val = rtl_readphy(tp, reg_addr); 1089 rtl_writephy(tp, reg_addr, (val & ~m) | p); 1090 } 1091 1092 static void r8168d_modify_extpage(struct phy_device *phydev, int extpage, 1093 int reg, u16 mask, u16 val) 1094 { 1095 int oldpage = phy_select_page(phydev, 0x0007); 1096 1097 __phy_write(phydev, 0x1e, extpage); 1098 __phy_modify(phydev, reg, mask, val); 1099 1100 phy_restore_page(phydev, oldpage, 0); 1101 } 1102 1103 static void r8168d_phy_param(struct phy_device *phydev, u16 parm, 1104 u16 mask, u16 val) 1105 { 1106 int oldpage = phy_select_page(phydev, 0x0005); 1107 1108 __phy_write(phydev, 0x05, parm); 1109 __phy_modify(phydev, 0x06, mask, val); 1110 1111 phy_restore_page(phydev, oldpage, 0); 1112 } 1113 1114 static void r8168g_phy_param(struct phy_device *phydev, u16 parm, 1115 u16 mask, u16 val) 1116 { 1117 int oldpage = phy_select_page(phydev, 0x0a43); 1118 1119 __phy_write(phydev, 0x13, parm); 1120 __phy_modify(phydev, 0x14, mask, val); 1121 1122 phy_restore_page(phydev, oldpage, 0); 1123 } 1124 1125 DECLARE_RTL_COND(rtl_ephyar_cond) 1126 { 1127 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1128 } 1129 1130 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1131 { 1132 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1133 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1134 1135 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1136 1137 udelay(10); 1138 } 1139 1140 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1141 { 1142 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1143 1144 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1145 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1146 } 1147 1148 DECLARE_RTL_COND(rtl_eriar_cond) 1149 { 1150 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1151 } 1152 1153 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1154 u32 val, int type) 1155 { 1156 BUG_ON((addr & 3) || (mask == 0)); 1157 RTL_W32(tp, ERIDR, val); 1158 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1159 1160 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1161 } 1162 1163 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1164 u32 val) 1165 { 1166 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1167 } 1168 1169 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1170 { 1171 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1172 1173 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1174 RTL_R32(tp, ERIDR) : ~0; 1175 } 1176 1177 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1178 { 1179 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1180 } 1181 1182 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1183 u32 m) 1184 { 1185 u32 val; 1186 1187 val = rtl_eri_read(tp, addr); 1188 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1189 } 1190 1191 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1192 u32 p) 1193 { 1194 rtl_w0w1_eri(tp, addr, mask, p, 0); 1195 } 1196 1197 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1198 u32 m) 1199 { 1200 rtl_w0w1_eri(tp, addr, mask, 0, m); 1201 } 1202 1203 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1204 { 1205 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1206 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1207 RTL_R32(tp, OCPDR) : ~0; 1208 } 1209 1210 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1211 { 1212 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1213 } 1214 1215 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1216 u32 data) 1217 { 1218 RTL_W32(tp, OCPDR, data); 1219 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1220 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1221 } 1222 1223 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1224 u32 data) 1225 { 1226 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1227 data, ERIAR_OOB); 1228 } 1229 1230 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1231 { 1232 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1233 1234 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1235 } 1236 1237 #define OOB_CMD_RESET 0x00 1238 #define OOB_CMD_DRIVER_START 0x05 1239 #define OOB_CMD_DRIVER_STOP 0x06 1240 1241 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1242 { 1243 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1244 } 1245 1246 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1247 { 1248 u16 reg; 1249 1250 reg = rtl8168_get_ocp_reg(tp); 1251 1252 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1253 } 1254 1255 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1256 { 1257 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1258 } 1259 1260 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1261 { 1262 return RTL_R8(tp, IBISR0) & 0x20; 1263 } 1264 1265 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1266 { 1267 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1268 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1269 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1270 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1271 } 1272 1273 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1274 { 1275 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1276 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1277 } 1278 1279 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1280 { 1281 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1282 r8168ep_ocp_write(tp, 0x01, 0x30, 1283 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1284 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1285 } 1286 1287 static void rtl8168_driver_start(struct rtl8169_private *tp) 1288 { 1289 switch (tp->mac_version) { 1290 case RTL_GIGA_MAC_VER_27: 1291 case RTL_GIGA_MAC_VER_28: 1292 case RTL_GIGA_MAC_VER_31: 1293 rtl8168dp_driver_start(tp); 1294 break; 1295 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1296 rtl8168ep_driver_start(tp); 1297 break; 1298 default: 1299 BUG(); 1300 break; 1301 } 1302 } 1303 1304 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1305 { 1306 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1307 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1308 } 1309 1310 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1311 { 1312 rtl8168ep_stop_cmac(tp); 1313 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1314 r8168ep_ocp_write(tp, 0x01, 0x30, 1315 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1316 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1317 } 1318 1319 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1320 { 1321 switch (tp->mac_version) { 1322 case RTL_GIGA_MAC_VER_27: 1323 case RTL_GIGA_MAC_VER_28: 1324 case RTL_GIGA_MAC_VER_31: 1325 rtl8168dp_driver_stop(tp); 1326 break; 1327 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1328 rtl8168ep_driver_stop(tp); 1329 break; 1330 default: 1331 BUG(); 1332 break; 1333 } 1334 } 1335 1336 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1337 { 1338 u16 reg = rtl8168_get_ocp_reg(tp); 1339 1340 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1341 } 1342 1343 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1344 { 1345 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1346 } 1347 1348 static bool r8168_check_dash(struct rtl8169_private *tp) 1349 { 1350 switch (tp->mac_version) { 1351 case RTL_GIGA_MAC_VER_27: 1352 case RTL_GIGA_MAC_VER_28: 1353 case RTL_GIGA_MAC_VER_31: 1354 return r8168dp_check_dash(tp); 1355 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1356 return r8168ep_check_dash(tp); 1357 default: 1358 return false; 1359 } 1360 } 1361 1362 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1363 { 1364 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1365 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1366 } 1367 1368 DECLARE_RTL_COND(rtl_efusear_cond) 1369 { 1370 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1371 } 1372 1373 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1374 { 1375 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1376 1377 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1378 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1379 } 1380 1381 static u32 rtl_get_events(struct rtl8169_private *tp) 1382 { 1383 if (rtl_is_8125(tp)) 1384 return RTL_R32(tp, IntrStatus_8125); 1385 else 1386 return RTL_R16(tp, IntrStatus); 1387 } 1388 1389 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1390 { 1391 if (rtl_is_8125(tp)) 1392 RTL_W32(tp, IntrStatus_8125, bits); 1393 else 1394 RTL_W16(tp, IntrStatus, bits); 1395 } 1396 1397 static void rtl_irq_disable(struct rtl8169_private *tp) 1398 { 1399 if (rtl_is_8125(tp)) 1400 RTL_W32(tp, IntrMask_8125, 0); 1401 else 1402 RTL_W16(tp, IntrMask, 0); 1403 tp->irq_enabled = 0; 1404 } 1405 1406 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) 1407 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) 1408 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) 1409 1410 static void rtl_irq_enable(struct rtl8169_private *tp) 1411 { 1412 tp->irq_enabled = 1; 1413 if (rtl_is_8125(tp)) 1414 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1415 else 1416 RTL_W16(tp, IntrMask, tp->irq_mask); 1417 } 1418 1419 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1420 { 1421 rtl_irq_disable(tp); 1422 rtl_ack_events(tp, 0xffffffff); 1423 /* PCI commit */ 1424 RTL_R8(tp, ChipCmd); 1425 } 1426 1427 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1428 { 1429 struct net_device *dev = tp->dev; 1430 struct phy_device *phydev = tp->phydev; 1431 1432 if (!netif_running(dev)) 1433 return; 1434 1435 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1436 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1437 if (phydev->speed == SPEED_1000) { 1438 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1439 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1440 } else if (phydev->speed == SPEED_100) { 1441 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1442 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1443 } else { 1444 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1445 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1446 } 1447 rtl_reset_packet_filter(tp); 1448 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1449 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1450 if (phydev->speed == SPEED_1000) { 1451 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1452 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1453 } else { 1454 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1455 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1456 } 1457 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1458 if (phydev->speed == SPEED_10) { 1459 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1460 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1461 } else { 1462 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1463 } 1464 } 1465 } 1466 1467 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1468 1469 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1470 { 1471 struct rtl8169_private *tp = netdev_priv(dev); 1472 1473 rtl_lock_work(tp); 1474 wol->supported = WAKE_ANY; 1475 wol->wolopts = tp->saved_wolopts; 1476 rtl_unlock_work(tp); 1477 } 1478 1479 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1480 { 1481 static const struct { 1482 u32 opt; 1483 u16 reg; 1484 u8 mask; 1485 } cfg[] = { 1486 { WAKE_PHY, Config3, LinkUp }, 1487 { WAKE_UCAST, Config5, UWF }, 1488 { WAKE_BCAST, Config5, BWF }, 1489 { WAKE_MCAST, Config5, MWF }, 1490 { WAKE_ANY, Config5, LanWake }, 1491 { WAKE_MAGIC, Config3, MagicPacket } 1492 }; 1493 unsigned int i, tmp = ARRAY_SIZE(cfg); 1494 u8 options; 1495 1496 rtl_unlock_config_regs(tp); 1497 1498 if (rtl_is_8168evl_up(tp)) { 1499 tmp--; 1500 if (wolopts & WAKE_MAGIC) 1501 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1502 MagicPacket_v2); 1503 else 1504 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1505 MagicPacket_v2); 1506 } else if (rtl_is_8125(tp)) { 1507 tmp--; 1508 if (wolopts & WAKE_MAGIC) 1509 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1510 else 1511 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1512 } 1513 1514 for (i = 0; i < tmp; i++) { 1515 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1516 if (wolopts & cfg[i].opt) 1517 options |= cfg[i].mask; 1518 RTL_W8(tp, cfg[i].reg, options); 1519 } 1520 1521 switch (tp->mac_version) { 1522 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1523 options = RTL_R8(tp, Config1) & ~PMEnable; 1524 if (wolopts) 1525 options |= PMEnable; 1526 RTL_W8(tp, Config1, options); 1527 break; 1528 case RTL_GIGA_MAC_VER_34: 1529 case RTL_GIGA_MAC_VER_37: 1530 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52: 1531 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1532 if (wolopts) 1533 options |= PME_SIGNAL; 1534 RTL_W8(tp, Config2, options); 1535 break; 1536 default: 1537 break; 1538 } 1539 1540 rtl_lock_config_regs(tp); 1541 1542 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1543 } 1544 1545 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1546 { 1547 struct rtl8169_private *tp = netdev_priv(dev); 1548 struct device *d = tp_to_dev(tp); 1549 1550 if (wol->wolopts & ~WAKE_ANY) 1551 return -EINVAL; 1552 1553 pm_runtime_get_noresume(d); 1554 1555 rtl_lock_work(tp); 1556 1557 tp->saved_wolopts = wol->wolopts; 1558 1559 if (pm_runtime_active(d)) 1560 __rtl8169_set_wol(tp, tp->saved_wolopts); 1561 1562 rtl_unlock_work(tp); 1563 1564 pm_runtime_put_noidle(d); 1565 1566 return 0; 1567 } 1568 1569 static void rtl8169_get_drvinfo(struct net_device *dev, 1570 struct ethtool_drvinfo *info) 1571 { 1572 struct rtl8169_private *tp = netdev_priv(dev); 1573 struct rtl_fw *rtl_fw = tp->rtl_fw; 1574 1575 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1576 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1577 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1578 if (rtl_fw) 1579 strlcpy(info->fw_version, rtl_fw->version, 1580 sizeof(info->fw_version)); 1581 } 1582 1583 static int rtl8169_get_regs_len(struct net_device *dev) 1584 { 1585 return R8169_REGS_SIZE; 1586 } 1587 1588 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1589 netdev_features_t features) 1590 { 1591 struct rtl8169_private *tp = netdev_priv(dev); 1592 1593 if (dev->mtu > TD_MSS_MAX) 1594 features &= ~NETIF_F_ALL_TSO; 1595 1596 if (dev->mtu > JUMBO_1K && 1597 tp->mac_version > RTL_GIGA_MAC_VER_06) 1598 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1599 1600 return features; 1601 } 1602 1603 static int rtl8169_set_features(struct net_device *dev, 1604 netdev_features_t features) 1605 { 1606 struct rtl8169_private *tp = netdev_priv(dev); 1607 u32 rx_config; 1608 1609 rtl_lock_work(tp); 1610 1611 rx_config = RTL_R32(tp, RxConfig); 1612 if (features & NETIF_F_RXALL) 1613 rx_config |= (AcceptErr | AcceptRunt); 1614 else 1615 rx_config &= ~(AcceptErr | AcceptRunt); 1616 1617 if (rtl_is_8125(tp)) { 1618 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1619 rx_config |= RX_VLAN_8125; 1620 else 1621 rx_config &= ~RX_VLAN_8125; 1622 } 1623 1624 RTL_W32(tp, RxConfig, rx_config); 1625 1626 if (features & NETIF_F_RXCSUM) 1627 tp->cp_cmd |= RxChkSum; 1628 else 1629 tp->cp_cmd &= ~RxChkSum; 1630 1631 if (!rtl_is_8125(tp)) { 1632 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1633 tp->cp_cmd |= RxVlan; 1634 else 1635 tp->cp_cmd &= ~RxVlan; 1636 } 1637 1638 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1639 RTL_R16(tp, CPlusCmd); 1640 1641 rtl_unlock_work(tp); 1642 1643 return 0; 1644 } 1645 1646 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1647 { 1648 return (skb_vlan_tag_present(skb)) ? 1649 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1650 } 1651 1652 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1653 { 1654 u32 opts2 = le32_to_cpu(desc->opts2); 1655 1656 if (opts2 & RxVlanTag) 1657 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1658 } 1659 1660 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1661 void *p) 1662 { 1663 struct rtl8169_private *tp = netdev_priv(dev); 1664 u32 __iomem *data = tp->mmio_addr; 1665 u32 *dw = p; 1666 int i; 1667 1668 rtl_lock_work(tp); 1669 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1670 memcpy_fromio(dw++, data++, 4); 1671 rtl_unlock_work(tp); 1672 } 1673 1674 static u32 rtl8169_get_msglevel(struct net_device *dev) 1675 { 1676 struct rtl8169_private *tp = netdev_priv(dev); 1677 1678 return tp->msg_enable; 1679 } 1680 1681 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1682 { 1683 struct rtl8169_private *tp = netdev_priv(dev); 1684 1685 tp->msg_enable = value; 1686 } 1687 1688 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1689 "tx_packets", 1690 "rx_packets", 1691 "tx_errors", 1692 "rx_errors", 1693 "rx_missed", 1694 "align_errors", 1695 "tx_single_collisions", 1696 "tx_multi_collisions", 1697 "unicast", 1698 "broadcast", 1699 "multicast", 1700 "tx_aborted", 1701 "tx_underrun", 1702 }; 1703 1704 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1705 { 1706 switch (sset) { 1707 case ETH_SS_STATS: 1708 return ARRAY_SIZE(rtl8169_gstrings); 1709 default: 1710 return -EOPNOTSUPP; 1711 } 1712 } 1713 1714 DECLARE_RTL_COND(rtl_counters_cond) 1715 { 1716 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1717 } 1718 1719 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1720 { 1721 dma_addr_t paddr = tp->counters_phys_addr; 1722 u32 cmd; 1723 1724 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1725 RTL_R32(tp, CounterAddrHigh); 1726 cmd = (u64)paddr & DMA_BIT_MASK(32); 1727 RTL_W32(tp, CounterAddrLow, cmd); 1728 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1729 1730 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1731 } 1732 1733 static bool rtl8169_reset_counters(struct rtl8169_private *tp) 1734 { 1735 /* 1736 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1737 * tally counters. 1738 */ 1739 if (tp->mac_version < RTL_GIGA_MAC_VER_19) 1740 return true; 1741 1742 return rtl8169_do_counters(tp, CounterReset); 1743 } 1744 1745 static bool rtl8169_update_counters(struct rtl8169_private *tp) 1746 { 1747 u8 val = RTL_R8(tp, ChipCmd); 1748 1749 /* 1750 * Some chips are unable to dump tally counters when the receiver 1751 * is disabled. If 0xff chip may be in a PCI power-save state. 1752 */ 1753 if (!(val & CmdRxEnb) || val == 0xff) 1754 return true; 1755 1756 return rtl8169_do_counters(tp, CounterDump); 1757 } 1758 1759 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1760 { 1761 struct rtl8169_counters *counters = tp->counters; 1762 bool ret = false; 1763 1764 /* 1765 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1766 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1767 * reset by a power cycle, while the counter values collected by the 1768 * driver are reset at every driver unload/load cycle. 1769 * 1770 * To make sure the HW values returned by @get_stats64 match the SW 1771 * values, we collect the initial values at first open(*) and use them 1772 * as offsets to normalize the values returned by @get_stats64. 1773 * 1774 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1775 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1776 * set at open time by rtl_hw_start. 1777 */ 1778 1779 if (tp->tc_offset.inited) 1780 return true; 1781 1782 /* If both, reset and update fail, propagate to caller. */ 1783 if (rtl8169_reset_counters(tp)) 1784 ret = true; 1785 1786 if (rtl8169_update_counters(tp)) 1787 ret = true; 1788 1789 tp->tc_offset.tx_errors = counters->tx_errors; 1790 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1791 tp->tc_offset.tx_aborted = counters->tx_aborted; 1792 tp->tc_offset.inited = true; 1793 1794 return ret; 1795 } 1796 1797 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1798 struct ethtool_stats *stats, u64 *data) 1799 { 1800 struct rtl8169_private *tp = netdev_priv(dev); 1801 struct device *d = tp_to_dev(tp); 1802 struct rtl8169_counters *counters = tp->counters; 1803 1804 ASSERT_RTNL(); 1805 1806 pm_runtime_get_noresume(d); 1807 1808 if (pm_runtime_active(d)) 1809 rtl8169_update_counters(tp); 1810 1811 pm_runtime_put_noidle(d); 1812 1813 data[0] = le64_to_cpu(counters->tx_packets); 1814 data[1] = le64_to_cpu(counters->rx_packets); 1815 data[2] = le64_to_cpu(counters->tx_errors); 1816 data[3] = le32_to_cpu(counters->rx_errors); 1817 data[4] = le16_to_cpu(counters->rx_missed); 1818 data[5] = le16_to_cpu(counters->align_errors); 1819 data[6] = le32_to_cpu(counters->tx_one_collision); 1820 data[7] = le32_to_cpu(counters->tx_multi_collision); 1821 data[8] = le64_to_cpu(counters->rx_unicast); 1822 data[9] = le64_to_cpu(counters->rx_broadcast); 1823 data[10] = le32_to_cpu(counters->rx_multicast); 1824 data[11] = le16_to_cpu(counters->tx_aborted); 1825 data[12] = le16_to_cpu(counters->tx_underun); 1826 } 1827 1828 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1829 { 1830 switch(stringset) { 1831 case ETH_SS_STATS: 1832 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1833 break; 1834 } 1835 } 1836 1837 /* 1838 * Interrupt coalescing 1839 * 1840 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1841 * > 8169, 8168 and 810x line of chipsets 1842 * 1843 * 8169, 8168, and 8136(810x) serial chipsets support it. 1844 * 1845 * > 2 - the Tx timer unit at gigabit speed 1846 * 1847 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1848 * (0xe0) bit 1 and bit 0. 1849 * 1850 * For 8169 1851 * bit[1:0] \ speed 1000M 100M 10M 1852 * 0 0 320ns 2.56us 40.96us 1853 * 0 1 2.56us 20.48us 327.7us 1854 * 1 0 5.12us 40.96us 655.4us 1855 * 1 1 10.24us 81.92us 1.31ms 1856 * 1857 * For the other 1858 * bit[1:0] \ speed 1000M 100M 10M 1859 * 0 0 5us 2.56us 40.96us 1860 * 0 1 40us 20.48us 327.7us 1861 * 1 0 80us 40.96us 655.4us 1862 * 1 1 160us 81.92us 1.31ms 1863 */ 1864 1865 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ 1866 struct rtl_coalesce_scale { 1867 /* Rx / Tx */ 1868 u32 nsecs[2]; 1869 }; 1870 1871 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1872 struct rtl_coalesce_info { 1873 u32 speed; 1874 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ 1875 }; 1876 1877 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ 1878 #define rxtx_x1822(r, t) { \ 1879 {{(r), (t)}}, \ 1880 {{(r)*8, (t)*8}}, \ 1881 {{(r)*8*2, (t)*8*2}}, \ 1882 {{(r)*8*2*2, (t)*8*2*2}}, \ 1883 } 1884 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1885 /* speed delays: rx00 tx00 */ 1886 { SPEED_10, rxtx_x1822(40960, 40960) }, 1887 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1888 { SPEED_1000, rxtx_x1822( 320, 320) }, 1889 { 0 }, 1890 }; 1891 1892 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1893 /* speed delays: rx00 tx00 */ 1894 { SPEED_10, rxtx_x1822(40960, 40960) }, 1895 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1896 { SPEED_1000, rxtx_x1822( 5000, 5000) }, 1897 { 0 }, 1898 }; 1899 #undef rxtx_x1822 1900 1901 /* get rx/tx scale vector corresponding to current speed */ 1902 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) 1903 { 1904 struct rtl8169_private *tp = netdev_priv(dev); 1905 const struct rtl_coalesce_info *ci; 1906 1907 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1908 ci = rtl_coalesce_info_8169; 1909 else 1910 ci = rtl_coalesce_info_8168_8136; 1911 1912 for (; ci->speed; ci++) { 1913 if (tp->phydev->speed == ci->speed) 1914 return ci; 1915 } 1916 1917 return ERR_PTR(-ELNRNG); 1918 } 1919 1920 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1921 { 1922 struct rtl8169_private *tp = netdev_priv(dev); 1923 const struct rtl_coalesce_info *ci; 1924 const struct rtl_coalesce_scale *scale; 1925 struct { 1926 u32 *max_frames; 1927 u32 *usecs; 1928 } coal_settings [] = { 1929 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, 1930 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } 1931 }, *p = coal_settings; 1932 int i; 1933 u16 w; 1934 1935 if (rtl_is_8125(tp)) 1936 return -EOPNOTSUPP; 1937 1938 memset(ec, 0, sizeof(*ec)); 1939 1940 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1941 ci = rtl_coalesce_info(dev); 1942 if (IS_ERR(ci)) 1943 return PTR_ERR(ci); 1944 1945 scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; 1946 1947 /* read IntrMitigate and adjust according to scale */ 1948 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { 1949 *p->max_frames = (w & RTL_COALESCE_MASK) << 2; 1950 w >>= RTL_COALESCE_SHIFT; 1951 *p->usecs = w & RTL_COALESCE_MASK; 1952 } 1953 1954 for (i = 0; i < 2; i++) { 1955 p = coal_settings + i; 1956 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; 1957 1958 /* 1959 * ethtool_coalesce says it is illegal to set both usecs and 1960 * max_frames to 0. 1961 */ 1962 if (!*p->usecs && !*p->max_frames) 1963 *p->max_frames = 1; 1964 } 1965 1966 return 0; 1967 } 1968 1969 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ 1970 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( 1971 struct net_device *dev, u32 nsec, u16 *cp01) 1972 { 1973 const struct rtl_coalesce_info *ci; 1974 u16 i; 1975 1976 ci = rtl_coalesce_info(dev); 1977 if (IS_ERR(ci)) 1978 return ERR_CAST(ci); 1979 1980 for (i = 0; i < 4; i++) { 1981 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], 1982 ci->scalev[i].nsecs[1]); 1983 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { 1984 *cp01 = i; 1985 return &ci->scalev[i]; 1986 } 1987 } 1988 1989 return ERR_PTR(-EINVAL); 1990 } 1991 1992 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1993 { 1994 struct rtl8169_private *tp = netdev_priv(dev); 1995 const struct rtl_coalesce_scale *scale; 1996 struct { 1997 u32 frames; 1998 u32 usecs; 1999 } coal_settings [] = { 2000 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, 2001 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } 2002 }, *p = coal_settings; 2003 u16 w = 0, cp01; 2004 int i; 2005 2006 if (rtl_is_8125(tp)) 2007 return -EOPNOTSUPP; 2008 2009 scale = rtl_coalesce_choose_scale(dev, 2010 max(p[0].usecs, p[1].usecs) * 1000, &cp01); 2011 if (IS_ERR(scale)) 2012 return PTR_ERR(scale); 2013 2014 for (i = 0; i < 2; i++, p++) { 2015 u32 units; 2016 2017 /* 2018 * accept max_frames=1 we returned in rtl_get_coalesce. 2019 * accept it not only when usecs=0 because of e.g. the following scenario: 2020 * 2021 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2022 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2023 * - then user does `ethtool -C eth0 rx-usecs 100` 2024 * 2025 * since ethtool sends to kernel whole ethtool_coalesce 2026 * settings, if we do not handle rx_usecs=!0, rx_frames=1 2027 * we'll reject it below in `frames % 4 != 0`. 2028 */ 2029 if (p->frames == 1) { 2030 p->frames = 0; 2031 } 2032 2033 units = p->usecs * 1000 / scale->nsecs[i]; 2034 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) 2035 return -EINVAL; 2036 2037 w <<= RTL_COALESCE_SHIFT; 2038 w |= units; 2039 w <<= RTL_COALESCE_SHIFT; 2040 w |= p->frames >> 2; 2041 } 2042 2043 rtl_lock_work(tp); 2044 2045 RTL_W16(tp, IntrMitigate, swab16(w)); 2046 2047 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2048 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2049 RTL_R16(tp, CPlusCmd); 2050 2051 rtl_unlock_work(tp); 2052 2053 return 0; 2054 } 2055 2056 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 2057 { 2058 struct rtl8169_private *tp = netdev_priv(dev); 2059 struct device *d = tp_to_dev(tp); 2060 int ret; 2061 2062 if (!rtl_supports_eee(tp)) 2063 return -EOPNOTSUPP; 2064 2065 pm_runtime_get_noresume(d); 2066 2067 if (!pm_runtime_active(d)) { 2068 ret = -EOPNOTSUPP; 2069 } else { 2070 ret = phy_ethtool_get_eee(tp->phydev, data); 2071 } 2072 2073 pm_runtime_put_noidle(d); 2074 2075 return ret; 2076 } 2077 2078 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 2079 { 2080 struct rtl8169_private *tp = netdev_priv(dev); 2081 struct device *d = tp_to_dev(tp); 2082 int ret; 2083 2084 if (!rtl_supports_eee(tp)) 2085 return -EOPNOTSUPP; 2086 2087 pm_runtime_get_noresume(d); 2088 2089 if (!pm_runtime_active(d)) { 2090 ret = -EOPNOTSUPP; 2091 goto out; 2092 } 2093 2094 if (dev->phydev->autoneg == AUTONEG_DISABLE || 2095 dev->phydev->duplex != DUPLEX_FULL) { 2096 ret = -EPROTONOSUPPORT; 2097 goto out; 2098 } 2099 2100 ret = phy_ethtool_set_eee(tp->phydev, data); 2101 2102 if (!ret) 2103 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 2104 MDIO_AN_EEE_ADV); 2105 out: 2106 pm_runtime_put_noidle(d); 2107 return ret; 2108 } 2109 2110 static const struct ethtool_ops rtl8169_ethtool_ops = { 2111 .get_drvinfo = rtl8169_get_drvinfo, 2112 .get_regs_len = rtl8169_get_regs_len, 2113 .get_link = ethtool_op_get_link, 2114 .get_coalesce = rtl_get_coalesce, 2115 .set_coalesce = rtl_set_coalesce, 2116 .get_msglevel = rtl8169_get_msglevel, 2117 .set_msglevel = rtl8169_set_msglevel, 2118 .get_regs = rtl8169_get_regs, 2119 .get_wol = rtl8169_get_wol, 2120 .set_wol = rtl8169_set_wol, 2121 .get_strings = rtl8169_get_strings, 2122 .get_sset_count = rtl8169_get_sset_count, 2123 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2124 .get_ts_info = ethtool_op_get_ts_info, 2125 .nway_reset = phy_ethtool_nway_reset, 2126 .get_eee = rtl8169_get_eee, 2127 .set_eee = rtl8169_set_eee, 2128 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2129 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2130 }; 2131 2132 static void rtl_enable_eee(struct rtl8169_private *tp) 2133 { 2134 struct phy_device *phydev = tp->phydev; 2135 int adv; 2136 2137 /* respect EEE advertisement the user may have set */ 2138 if (tp->eee_adv >= 0) 2139 adv = tp->eee_adv; 2140 else 2141 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2142 2143 if (adv >= 0) 2144 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2145 } 2146 2147 static void rtl8169_get_mac_version(struct rtl8169_private *tp) 2148 { 2149 /* 2150 * The driver currently handles the 8168Bf and the 8168Be identically 2151 * but they can be identified more specifically through the test below 2152 * if needed: 2153 * 2154 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2155 * 2156 * Same thing for the 8101Eb and the 8101Ec: 2157 * 2158 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2159 */ 2160 static const struct rtl_mac_info { 2161 u16 mask; 2162 u16 val; 2163 u16 mac_version; 2164 } mac_info[] = { 2165 /* 8125 family. */ 2166 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2167 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2168 2169 /* RTL8117 */ 2170 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2171 2172 /* 8168EP family. */ 2173 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2174 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2175 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2176 2177 /* 8168H family. */ 2178 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2179 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2180 2181 /* 8168G family. */ 2182 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2183 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2184 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2185 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2186 2187 /* 8168F family. */ 2188 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2189 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2190 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2191 2192 /* 8168E family. */ 2193 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2194 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2195 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2196 2197 /* 8168D family. */ 2198 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2199 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2200 2201 /* 8168DP family. */ 2202 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2203 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2204 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2205 2206 /* 8168C family. */ 2207 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2208 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2209 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2210 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2211 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2212 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2213 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2214 2215 /* 8168B family. */ 2216 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2217 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2218 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2219 2220 /* 8101 family. */ 2221 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2222 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2223 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2224 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2225 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2226 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2227 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2228 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2229 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2230 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2231 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2232 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2233 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2234 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2235 /* FIXME: where did these entries come from ? -- FR */ 2236 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2237 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2238 2239 /* 8110 family. */ 2240 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2241 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2242 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2243 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2244 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2245 2246 /* Catch-all */ 2247 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2248 }; 2249 const struct rtl_mac_info *p = mac_info; 2250 u16 reg = RTL_R32(tp, TxConfig) >> 20; 2251 2252 while ((reg & p->mask) != p->val) 2253 p++; 2254 tp->mac_version = p->mac_version; 2255 2256 if (tp->mac_version == RTL_GIGA_MAC_NONE) { 2257 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf); 2258 } else if (!tp->supports_gmii) { 2259 if (tp->mac_version == RTL_GIGA_MAC_VER_42) 2260 tp->mac_version = RTL_GIGA_MAC_VER_43; 2261 else if (tp->mac_version == RTL_GIGA_MAC_VER_45) 2262 tp->mac_version = RTL_GIGA_MAC_VER_47; 2263 else if (tp->mac_version == RTL_GIGA_MAC_VER_46) 2264 tp->mac_version = RTL_GIGA_MAC_VER_48; 2265 } 2266 } 2267 2268 struct phy_reg { 2269 u16 reg; 2270 u16 val; 2271 }; 2272 2273 static void __rtl_writephy_batch(struct rtl8169_private *tp, 2274 const struct phy_reg *regs, int len) 2275 { 2276 while (len-- > 0) { 2277 rtl_writephy(tp, regs->reg, regs->val); 2278 regs++; 2279 } 2280 } 2281 2282 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a)) 2283 2284 static void rtl_release_firmware(struct rtl8169_private *tp) 2285 { 2286 if (tp->rtl_fw) { 2287 rtl_fw_release_firmware(tp->rtl_fw); 2288 kfree(tp->rtl_fw); 2289 tp->rtl_fw = NULL; 2290 } 2291 } 2292 2293 static void rtl_apply_firmware(struct rtl8169_private *tp) 2294 { 2295 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2296 if (tp->rtl_fw) 2297 rtl_fw_write_firmware(tp, tp->rtl_fw); 2298 } 2299 2300 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) 2301 { 2302 if (rtl_readphy(tp, reg) != val) 2303 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); 2304 else 2305 rtl_apply_firmware(tp); 2306 } 2307 2308 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2309 { 2310 /* Adjust EEE LED frequency */ 2311 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2312 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2313 2314 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2315 } 2316 2317 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2318 { 2319 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2320 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2321 } 2322 2323 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp) 2324 { 2325 struct phy_device *phydev = tp->phydev; 2326 2327 phy_write(phydev, 0x1f, 0x0007); 2328 phy_write(phydev, 0x1e, 0x0020); 2329 phy_set_bits(phydev, 0x15, BIT(8)); 2330 phy_write(phydev, 0x1f, 0x0000); 2331 2332 r8168d_phy_param(phydev, 0x8b85, 0, BIT(13)); 2333 } 2334 2335 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp) 2336 { 2337 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4)); 2338 } 2339 2340 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp) 2341 { 2342 struct phy_device *phydev = tp->phydev; 2343 2344 rtl8168g_config_eee_phy(tp); 2345 2346 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 2347 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 2348 } 2349 2350 static void rtl8125_config_eee_phy(struct rtl8169_private *tp) 2351 { 2352 struct phy_device *phydev = tp->phydev; 2353 2354 rtl8168h_config_eee_phy(tp); 2355 2356 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 2357 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 2358 } 2359 2360 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) 2361 { 2362 static const struct phy_reg phy_reg_init[] = { 2363 { 0x1f, 0x0001 }, 2364 { 0x06, 0x006e }, 2365 { 0x08, 0x0708 }, 2366 { 0x15, 0x4000 }, 2367 { 0x18, 0x65c7 }, 2368 2369 { 0x1f, 0x0001 }, 2370 { 0x03, 0x00a1 }, 2371 { 0x02, 0x0008 }, 2372 { 0x01, 0x0120 }, 2373 { 0x00, 0x1000 }, 2374 { 0x04, 0x0800 }, 2375 { 0x04, 0x0000 }, 2376 2377 { 0x03, 0xff41 }, 2378 { 0x02, 0xdf60 }, 2379 { 0x01, 0x0140 }, 2380 { 0x00, 0x0077 }, 2381 { 0x04, 0x7800 }, 2382 { 0x04, 0x7000 }, 2383 2384 { 0x03, 0x802f }, 2385 { 0x02, 0x4f02 }, 2386 { 0x01, 0x0409 }, 2387 { 0x00, 0xf0f9 }, 2388 { 0x04, 0x9800 }, 2389 { 0x04, 0x9000 }, 2390 2391 { 0x03, 0xdf01 }, 2392 { 0x02, 0xdf20 }, 2393 { 0x01, 0xff95 }, 2394 { 0x00, 0xba00 }, 2395 { 0x04, 0xa800 }, 2396 { 0x04, 0xa000 }, 2397 2398 { 0x03, 0xff41 }, 2399 { 0x02, 0xdf20 }, 2400 { 0x01, 0x0140 }, 2401 { 0x00, 0x00bb }, 2402 { 0x04, 0xb800 }, 2403 { 0x04, 0xb000 }, 2404 2405 { 0x03, 0xdf41 }, 2406 { 0x02, 0xdc60 }, 2407 { 0x01, 0x6340 }, 2408 { 0x00, 0x007d }, 2409 { 0x04, 0xd800 }, 2410 { 0x04, 0xd000 }, 2411 2412 { 0x03, 0xdf01 }, 2413 { 0x02, 0xdf20 }, 2414 { 0x01, 0x100a }, 2415 { 0x00, 0xa0ff }, 2416 { 0x04, 0xf800 }, 2417 { 0x04, 0xf000 }, 2418 2419 { 0x1f, 0x0000 }, 2420 { 0x0b, 0x0000 }, 2421 { 0x00, 0x9200 } 2422 }; 2423 2424 rtl_writephy_batch(tp, phy_reg_init); 2425 } 2426 2427 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) 2428 { 2429 phy_write_paged(tp->phydev, 0x0002, 0x01, 0x90d0); 2430 } 2431 2432 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) 2433 { 2434 struct pci_dev *pdev = tp->pci_dev; 2435 2436 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || 2437 (pdev->subsystem_device != 0xe000)) 2438 return; 2439 2440 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2441 } 2442 2443 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) 2444 { 2445 static const struct phy_reg phy_reg_init[] = { 2446 { 0x1f, 0x0001 }, 2447 { 0x04, 0x0000 }, 2448 { 0x03, 0x00a1 }, 2449 { 0x02, 0x0008 }, 2450 { 0x01, 0x0120 }, 2451 { 0x00, 0x1000 }, 2452 { 0x04, 0x0800 }, 2453 { 0x04, 0x9000 }, 2454 { 0x03, 0x802f }, 2455 { 0x02, 0x4f02 }, 2456 { 0x01, 0x0409 }, 2457 { 0x00, 0xf099 }, 2458 { 0x04, 0x9800 }, 2459 { 0x04, 0xa000 }, 2460 { 0x03, 0xdf01 }, 2461 { 0x02, 0xdf20 }, 2462 { 0x01, 0xff95 }, 2463 { 0x00, 0xba00 }, 2464 { 0x04, 0xa800 }, 2465 { 0x04, 0xf000 }, 2466 { 0x03, 0xdf01 }, 2467 { 0x02, 0xdf20 }, 2468 { 0x01, 0x101a }, 2469 { 0x00, 0xa0ff }, 2470 { 0x04, 0xf800 }, 2471 { 0x04, 0x0000 }, 2472 { 0x1f, 0x0000 }, 2473 2474 { 0x1f, 0x0001 }, 2475 { 0x10, 0xf41b }, 2476 { 0x14, 0xfb54 }, 2477 { 0x18, 0xf5c7 }, 2478 { 0x1f, 0x0000 }, 2479 2480 { 0x1f, 0x0001 }, 2481 { 0x17, 0x0cc0 }, 2482 { 0x1f, 0x0000 } 2483 }; 2484 2485 rtl_writephy_batch(tp, phy_reg_init); 2486 2487 rtl8169scd_hw_phy_config_quirk(tp); 2488 } 2489 2490 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) 2491 { 2492 static const struct phy_reg phy_reg_init[] = { 2493 { 0x1f, 0x0001 }, 2494 { 0x04, 0x0000 }, 2495 { 0x03, 0x00a1 }, 2496 { 0x02, 0x0008 }, 2497 { 0x01, 0x0120 }, 2498 { 0x00, 0x1000 }, 2499 { 0x04, 0x0800 }, 2500 { 0x04, 0x9000 }, 2501 { 0x03, 0x802f }, 2502 { 0x02, 0x4f02 }, 2503 { 0x01, 0x0409 }, 2504 { 0x00, 0xf099 }, 2505 { 0x04, 0x9800 }, 2506 { 0x04, 0xa000 }, 2507 { 0x03, 0xdf01 }, 2508 { 0x02, 0xdf20 }, 2509 { 0x01, 0xff95 }, 2510 { 0x00, 0xba00 }, 2511 { 0x04, 0xa800 }, 2512 { 0x04, 0xf000 }, 2513 { 0x03, 0xdf01 }, 2514 { 0x02, 0xdf20 }, 2515 { 0x01, 0x101a }, 2516 { 0x00, 0xa0ff }, 2517 { 0x04, 0xf800 }, 2518 { 0x04, 0x0000 }, 2519 { 0x1f, 0x0000 }, 2520 2521 { 0x1f, 0x0001 }, 2522 { 0x0b, 0x8480 }, 2523 { 0x1f, 0x0000 }, 2524 2525 { 0x1f, 0x0001 }, 2526 { 0x18, 0x67c7 }, 2527 { 0x04, 0x2000 }, 2528 { 0x03, 0x002f }, 2529 { 0x02, 0x4360 }, 2530 { 0x01, 0x0109 }, 2531 { 0x00, 0x3022 }, 2532 { 0x04, 0x2800 }, 2533 { 0x1f, 0x0000 }, 2534 2535 { 0x1f, 0x0001 }, 2536 { 0x17, 0x0cc0 }, 2537 { 0x1f, 0x0000 } 2538 }; 2539 2540 rtl_writephy_batch(tp, phy_reg_init); 2541 } 2542 2543 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) 2544 { 2545 rtl_writephy(tp, 0x1f, 0x0001); 2546 rtl_patchphy(tp, 0x16, 1 << 0); 2547 rtl_writephy(tp, 0x10, 0xf41b); 2548 rtl_writephy(tp, 0x1f, 0x0000); 2549 } 2550 2551 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) 2552 { 2553 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf41b); 2554 } 2555 2556 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) 2557 { 2558 phy_write(tp->phydev, 0x1d, 0x0f00); 2559 phy_write_paged(tp->phydev, 0x0002, 0x0c, 0x1ec8); 2560 } 2561 2562 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) 2563 { 2564 phy_set_bits(tp->phydev, 0x14, BIT(5)); 2565 phy_set_bits(tp->phydev, 0x0d, BIT(5)); 2566 phy_write_paged(tp->phydev, 0x0001, 0x1d, 0x3d98); 2567 } 2568 2569 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) 2570 { 2571 static const struct phy_reg phy_reg_init[] = { 2572 { 0x1f, 0x0001 }, 2573 { 0x12, 0x2300 }, 2574 { 0x1f, 0x0002 }, 2575 { 0x00, 0x88d4 }, 2576 { 0x01, 0x82b1 }, 2577 { 0x03, 0x7002 }, 2578 { 0x08, 0x9e30 }, 2579 { 0x09, 0x01f0 }, 2580 { 0x0a, 0x5500 }, 2581 { 0x0c, 0x00c8 }, 2582 { 0x1f, 0x0003 }, 2583 { 0x12, 0xc096 }, 2584 { 0x16, 0x000a }, 2585 { 0x1f, 0x0000 }, 2586 { 0x1f, 0x0000 }, 2587 { 0x09, 0x2000 }, 2588 { 0x09, 0x0000 } 2589 }; 2590 2591 rtl_writephy_batch(tp, phy_reg_init); 2592 2593 rtl_patchphy(tp, 0x14, 1 << 5); 2594 rtl_patchphy(tp, 0x0d, 1 << 5); 2595 rtl_writephy(tp, 0x1f, 0x0000); 2596 } 2597 2598 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) 2599 { 2600 static const struct phy_reg phy_reg_init[] = { 2601 { 0x1f, 0x0001 }, 2602 { 0x12, 0x2300 }, 2603 { 0x03, 0x802f }, 2604 { 0x02, 0x4f02 }, 2605 { 0x01, 0x0409 }, 2606 { 0x00, 0xf099 }, 2607 { 0x04, 0x9800 }, 2608 { 0x04, 0x9000 }, 2609 { 0x1d, 0x3d98 }, 2610 { 0x1f, 0x0002 }, 2611 { 0x0c, 0x7eb8 }, 2612 { 0x06, 0x0761 }, 2613 { 0x1f, 0x0003 }, 2614 { 0x16, 0x0f0a }, 2615 { 0x1f, 0x0000 } 2616 }; 2617 2618 rtl_writephy_batch(tp, phy_reg_init); 2619 2620 rtl_patchphy(tp, 0x16, 1 << 0); 2621 rtl_patchphy(tp, 0x14, 1 << 5); 2622 rtl_patchphy(tp, 0x0d, 1 << 5); 2623 rtl_writephy(tp, 0x1f, 0x0000); 2624 } 2625 2626 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) 2627 { 2628 static const struct phy_reg phy_reg_init[] = { 2629 { 0x1f, 0x0001 }, 2630 { 0x12, 0x2300 }, 2631 { 0x1d, 0x3d98 }, 2632 { 0x1f, 0x0002 }, 2633 { 0x0c, 0x7eb8 }, 2634 { 0x06, 0x5461 }, 2635 { 0x1f, 0x0003 }, 2636 { 0x16, 0x0f0a }, 2637 { 0x1f, 0x0000 } 2638 }; 2639 2640 rtl_writephy_batch(tp, phy_reg_init); 2641 2642 rtl_patchphy(tp, 0x16, 1 << 0); 2643 rtl_patchphy(tp, 0x14, 1 << 5); 2644 rtl_patchphy(tp, 0x0d, 1 << 5); 2645 rtl_writephy(tp, 0x1f, 0x0000); 2646 } 2647 2648 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 2649 /* Channel Estimation */ 2650 { 0x1f, 0x0001 }, 2651 { 0x06, 0x4064 }, 2652 { 0x07, 0x2863 }, 2653 { 0x08, 0x059c }, 2654 { 0x09, 0x26b4 }, 2655 { 0x0a, 0x6a19 }, 2656 { 0x0b, 0xdcc8 }, 2657 { 0x10, 0xf06d }, 2658 { 0x14, 0x7f68 }, 2659 { 0x18, 0x7fd9 }, 2660 { 0x1c, 0xf0ff }, 2661 { 0x1d, 0x3d9c }, 2662 { 0x1f, 0x0003 }, 2663 { 0x12, 0xf49f }, 2664 { 0x13, 0x070b }, 2665 { 0x1a, 0x05ad }, 2666 { 0x14, 0x94c0 }, 2667 2668 /* 2669 * Tx Error Issue 2670 * Enhance line driver power 2671 */ 2672 { 0x1f, 0x0002 }, 2673 { 0x06, 0x5561 }, 2674 { 0x1f, 0x0005 }, 2675 { 0x05, 0x8332 }, 2676 { 0x06, 0x5561 }, 2677 2678 /* 2679 * Can not link to 1Gbps with bad cable 2680 * Decrease SNR threshold form 21.07dB to 19.04dB 2681 */ 2682 { 0x1f, 0x0001 }, 2683 { 0x17, 0x0cc0 }, 2684 2685 { 0x1f, 0x0000 }, 2686 { 0x0d, 0xf880 } 2687 }; 2688 2689 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = { 2690 { 0x1f, 0x0002 }, 2691 { 0x05, 0x669a }, 2692 { 0x1f, 0x0005 }, 2693 { 0x05, 0x8330 }, 2694 { 0x06, 0x669a }, 2695 { 0x1f, 0x0002 } 2696 }; 2697 2698 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) 2699 { 2700 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2701 2702 /* 2703 * Rx Error Issue 2704 * Fine Tune Switching regulator parameter 2705 */ 2706 rtl_writephy(tp, 0x1f, 0x0002); 2707 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef); 2708 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00); 2709 2710 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2711 int val; 2712 2713 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2714 2715 val = rtl_readphy(tp, 0x0d); 2716 2717 if ((val & 0x00ff) != 0x006c) { 2718 static const u32 set[] = { 2719 0x0065, 0x0066, 0x0067, 0x0068, 2720 0x0069, 0x006a, 0x006b, 0x006c 2721 }; 2722 int i; 2723 2724 rtl_writephy(tp, 0x1f, 0x0002); 2725 2726 val &= 0xff00; 2727 for (i = 0; i < ARRAY_SIZE(set); i++) 2728 rtl_writephy(tp, 0x0d, val | set[i]); 2729 } 2730 } else { 2731 phy_write_paged(tp->phydev, 0x0002, 0x05, 0x6662); 2732 r8168d_phy_param(tp->phydev, 0x8330, 0xffff, 0x6662); 2733 } 2734 2735 /* RSET couple improve */ 2736 rtl_writephy(tp, 0x1f, 0x0002); 2737 rtl_patchphy(tp, 0x0d, 0x0300); 2738 rtl_patchphy(tp, 0x0f, 0x0010); 2739 2740 /* Fine tune PLL performance */ 2741 rtl_writephy(tp, 0x1f, 0x0002); 2742 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2743 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2744 2745 rtl_writephy(tp, 0x1f, 0x0005); 2746 rtl_writephy(tp, 0x05, 0x001b); 2747 2748 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); 2749 2750 rtl_writephy(tp, 0x1f, 0x0000); 2751 } 2752 2753 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) 2754 { 2755 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2756 2757 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2758 int val; 2759 2760 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2761 2762 val = rtl_readphy(tp, 0x0d); 2763 if ((val & 0x00ff) != 0x006c) { 2764 static const u32 set[] = { 2765 0x0065, 0x0066, 0x0067, 0x0068, 2766 0x0069, 0x006a, 0x006b, 0x006c 2767 }; 2768 int i; 2769 2770 rtl_writephy(tp, 0x1f, 0x0002); 2771 2772 val &= 0xff00; 2773 for (i = 0; i < ARRAY_SIZE(set); i++) 2774 rtl_writephy(tp, 0x0d, val | set[i]); 2775 } 2776 } else { 2777 phy_write_paged(tp->phydev, 0x0002, 0x05, 0x2642); 2778 r8168d_phy_param(tp->phydev, 0x8330, 0xffff, 0x2642); 2779 } 2780 2781 /* Fine tune PLL performance */ 2782 rtl_writephy(tp, 0x1f, 0x0002); 2783 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2784 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2785 2786 /* Switching regulator Slew rate */ 2787 rtl_writephy(tp, 0x1f, 0x0002); 2788 rtl_patchphy(tp, 0x0f, 0x0017); 2789 2790 rtl_writephy(tp, 0x1f, 0x0005); 2791 rtl_writephy(tp, 0x05, 0x001b); 2792 2793 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); 2794 2795 rtl_writephy(tp, 0x1f, 0x0000); 2796 } 2797 2798 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) 2799 { 2800 static const struct phy_reg phy_reg_init[] = { 2801 { 0x1f, 0x0002 }, 2802 { 0x10, 0x0008 }, 2803 { 0x0d, 0x006c }, 2804 2805 { 0x1f, 0x0000 }, 2806 { 0x0d, 0xf880 }, 2807 2808 { 0x1f, 0x0001 }, 2809 { 0x17, 0x0cc0 }, 2810 2811 { 0x1f, 0x0001 }, 2812 { 0x0b, 0xa4d8 }, 2813 { 0x09, 0x281c }, 2814 { 0x07, 0x2883 }, 2815 { 0x0a, 0x6b35 }, 2816 { 0x1d, 0x3da4 }, 2817 { 0x1c, 0xeffd }, 2818 { 0x14, 0x7f52 }, 2819 { 0x18, 0x7fc6 }, 2820 { 0x08, 0x0601 }, 2821 { 0x06, 0x4063 }, 2822 { 0x10, 0xf074 }, 2823 { 0x1f, 0x0003 }, 2824 { 0x13, 0x0789 }, 2825 { 0x12, 0xf4bd }, 2826 { 0x1a, 0x04fd }, 2827 { 0x14, 0x84b0 }, 2828 { 0x1f, 0x0000 }, 2829 { 0x00, 0x9200 }, 2830 2831 { 0x1f, 0x0005 }, 2832 { 0x01, 0x0340 }, 2833 { 0x1f, 0x0001 }, 2834 { 0x04, 0x4000 }, 2835 { 0x03, 0x1d21 }, 2836 { 0x02, 0x0c32 }, 2837 { 0x01, 0x0200 }, 2838 { 0x00, 0x5554 }, 2839 { 0x04, 0x4800 }, 2840 { 0x04, 0x4000 }, 2841 { 0x04, 0xf000 }, 2842 { 0x03, 0xdf01 }, 2843 { 0x02, 0xdf20 }, 2844 { 0x01, 0x101a }, 2845 { 0x00, 0xa0ff }, 2846 { 0x04, 0xf800 }, 2847 { 0x04, 0xf000 }, 2848 { 0x1f, 0x0000 }, 2849 }; 2850 2851 rtl_writephy_batch(tp, phy_reg_init); 2852 2853 r8168d_modify_extpage(tp->phydev, 0x0023, 0x16, 0xffff, 0x0000); 2854 } 2855 2856 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) 2857 { 2858 phy_write_paged(tp->phydev, 0x0001, 0x17, 0x0cc0); 2859 r8168d_modify_extpage(tp->phydev, 0x002d, 0x18, 0xffff, 0x0040); 2860 phy_set_bits(tp->phydev, 0x0d, BIT(5)); 2861 } 2862 2863 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) 2864 { 2865 static const struct phy_reg phy_reg_init[] = { 2866 /* Channel estimation fine tune */ 2867 { 0x1f, 0x0001 }, 2868 { 0x0b, 0x6c20 }, 2869 { 0x07, 0x2872 }, 2870 { 0x1c, 0xefff }, 2871 { 0x1f, 0x0003 }, 2872 { 0x14, 0x6420 }, 2873 { 0x1f, 0x0000 }, 2874 }; 2875 struct phy_device *phydev = tp->phydev; 2876 2877 rtl_apply_firmware(tp); 2878 2879 /* Enable Delay cap */ 2880 r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896); 2881 2882 rtl_writephy_batch(tp, phy_reg_init); 2883 2884 /* Update PFM & 10M TX idle timer */ 2885 r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919); 2886 2887 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 2888 2889 /* DCO enable for 10M IDLE Power */ 2890 r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006); 2891 2892 /* For impedance matching */ 2893 phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000); 2894 2895 /* PHY auto speed down */ 2896 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050); 2897 phy_set_bits(phydev, 0x14, BIT(15)); 2898 2899 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 2900 r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000); 2901 2902 r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000); 2903 phy_write_paged(phydev, 0x0006, 0x00, 0x5a00); 2904 2905 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000); 2906 } 2907 2908 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2909 { 2910 const u16 w[] = { 2911 addr[0] | (addr[1] << 8), 2912 addr[2] | (addr[3] << 8), 2913 addr[4] | (addr[5] << 8) 2914 }; 2915 2916 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2917 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2918 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2919 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2920 } 2921 2922 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) 2923 { 2924 struct phy_device *phydev = tp->phydev; 2925 2926 rtl_apply_firmware(tp); 2927 2928 /* Enable Delay cap */ 2929 r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006); 2930 2931 /* Channel estimation fine tune */ 2932 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 2933 2934 /* Green Setting */ 2935 r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222); 2936 r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000); 2937 r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000); 2938 2939 /* For 4-corner performance improve */ 2940 rtl_writephy(tp, 0x1f, 0x0005); 2941 rtl_writephy(tp, 0x05, 0x8b80); 2942 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 2943 rtl_writephy(tp, 0x1f, 0x0000); 2944 2945 /* PHY auto speed down */ 2946 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 2947 phy_set_bits(phydev, 0x14, BIT(15)); 2948 2949 /* improve 10M EEE waveform */ 2950 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 2951 2952 /* Improve 2-pair detection performance */ 2953 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 2954 2955 rtl8168f_config_eee_phy(tp); 2956 rtl_enable_eee(tp); 2957 2958 /* Green feature */ 2959 rtl_writephy(tp, 0x1f, 0x0003); 2960 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000); 2961 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000); 2962 rtl_writephy(tp, 0x1f, 0x0000); 2963 rtl_writephy(tp, 0x1f, 0x0005); 2964 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000); 2965 rtl_writephy(tp, 0x1f, 0x0000); 2966 2967 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ 2968 rtl_rar_exgmac_set(tp, tp->dev->dev_addr); 2969 } 2970 2971 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) 2972 { 2973 struct phy_device *phydev = tp->phydev; 2974 2975 /* For 4-corner performance improve */ 2976 r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006); 2977 2978 /* PHY auto speed down */ 2979 r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010); 2980 phy_set_bits(phydev, 0x14, BIT(15)); 2981 2982 /* Improve 10M EEE waveform */ 2983 r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001); 2984 2985 rtl8168f_config_eee_phy(tp); 2986 rtl_enable_eee(tp); 2987 } 2988 2989 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) 2990 { 2991 struct phy_device *phydev = tp->phydev; 2992 2993 rtl_apply_firmware(tp); 2994 2995 /* Channel estimation fine tune */ 2996 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 2997 2998 /* Modify green table for giga & fnet */ 2999 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 3000 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 3001 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 3002 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 3003 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 3004 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb); 3005 3006 /* Modify green table for 10M */ 3007 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 3008 3009 /* Disable hiimpedance detection (RTCT) */ 3010 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 3011 3012 rtl8168f_hw_phy_config(tp); 3013 3014 /* Improve 2-pair detection performance */ 3015 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 3016 } 3017 3018 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) 3019 { 3020 rtl_apply_firmware(tp); 3021 3022 rtl8168f_hw_phy_config(tp); 3023 } 3024 3025 static void rtl8411_hw_phy_config(struct rtl8169_private *tp) 3026 { 3027 struct phy_device *phydev = tp->phydev; 3028 3029 rtl_apply_firmware(tp); 3030 3031 rtl8168f_hw_phy_config(tp); 3032 3033 /* Improve 2-pair detection performance */ 3034 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000); 3035 3036 /* Channel estimation fine tune */ 3037 phy_write_paged(phydev, 0x0003, 0x09, 0xa20f); 3038 3039 /* Modify green table for giga & fnet */ 3040 r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000); 3041 r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000); 3042 r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000); 3043 r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000); 3044 r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000); 3045 r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa); 3046 3047 /* Modify green table for 10M */ 3048 r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00); 3049 3050 /* Disable hiimpedance detection (RTCT) */ 3051 phy_write_paged(phydev, 0x0003, 0x01, 0x328a); 3052 3053 /* Modify green table for giga */ 3054 r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000); 3055 r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000); 3056 r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000); 3057 r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100); 3058 r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000); 3059 r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000); 3060 r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000); 3061 3062 /* uc same-seed solution */ 3063 r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000); 3064 3065 /* Green feature */ 3066 rtl_writephy(tp, 0x1f, 0x0003); 3067 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); 3068 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); 3069 rtl_writephy(tp, 0x1f, 0x0000); 3070 } 3071 3072 static void rtl8168g_disable_aldps(struct rtl8169_private *tp) 3073 { 3074 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0); 3075 } 3076 3077 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp) 3078 { 3079 struct phy_device *phydev = tp->phydev; 3080 3081 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 3082 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 3083 r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000); 3084 phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003); 3085 } 3086 3087 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) 3088 { 3089 int ret; 3090 3091 rtl_apply_firmware(tp); 3092 3093 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10); 3094 if (ret & BIT(8)) 3095 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0); 3096 else 3097 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15)); 3098 3099 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13); 3100 if (ret & BIT(8)) 3101 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1)); 3102 else 3103 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0); 3104 3105 /* Enable PHY auto speed down */ 3106 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3107 3108 rtl8168g_phy_adjust_10m_aldps(tp); 3109 3110 /* EEE auto-fallback function */ 3111 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3112 3113 /* Enable UC LPF tune function */ 3114 r8168g_phy_param(tp->phydev, 0x8012, 0x0000, 0x8000); 3115 3116 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3117 3118 /* Improve SWR Efficiency */ 3119 rtl_writephy(tp, 0x1f, 0x0bcd); 3120 rtl_writephy(tp, 0x14, 0x5065); 3121 rtl_writephy(tp, 0x14, 0xd065); 3122 rtl_writephy(tp, 0x1f, 0x0bc8); 3123 rtl_writephy(tp, 0x11, 0x5655); 3124 rtl_writephy(tp, 0x1f, 0x0bcd); 3125 rtl_writephy(tp, 0x14, 0x1065); 3126 rtl_writephy(tp, 0x14, 0x9065); 3127 rtl_writephy(tp, 0x14, 0x1065); 3128 rtl_writephy(tp, 0x1f, 0x0000); 3129 3130 rtl8168g_disable_aldps(tp); 3131 rtl8168g_config_eee_phy(tp); 3132 rtl_enable_eee(tp); 3133 } 3134 3135 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) 3136 { 3137 rtl_apply_firmware(tp); 3138 rtl8168g_config_eee_phy(tp); 3139 rtl_enable_eee(tp); 3140 } 3141 3142 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) 3143 { 3144 struct phy_device *phydev = tp->phydev; 3145 u16 dout_tapbin; 3146 u32 data; 3147 3148 rtl_apply_firmware(tp); 3149 3150 /* CHN EST parameters adjust - giga master */ 3151 r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000); 3152 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000); 3153 r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500); 3154 r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00); 3155 3156 /* CHN EST parameters adjust - giga slave */ 3157 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000); 3158 r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000); 3159 r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000); 3160 3161 /* CHN EST parameters adjust - fnet */ 3162 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200); 3163 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500); 3164 r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00); 3165 3166 /* enable R-tune & PGA-retune function */ 3167 dout_tapbin = 0; 3168 data = phy_read_paged(phydev, 0x0a46, 0x13); 3169 data &= 3; 3170 data <<= 2; 3171 dout_tapbin |= data; 3172 data = phy_read_paged(phydev, 0x0a46, 0x12); 3173 data &= 0xc000; 3174 data >>= 14; 3175 dout_tapbin |= data; 3176 dout_tapbin = ~(dout_tapbin^0x08); 3177 dout_tapbin <<= 12; 3178 dout_tapbin &= 0xf000; 3179 3180 r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin); 3181 r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin); 3182 r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin); 3183 r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin); 3184 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 3185 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 3186 3187 /* enable GPHY 10M */ 3188 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3189 3190 /* SAR ADC performance */ 3191 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); 3192 3193 r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000); 3194 r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000); 3195 r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000); 3196 r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000); 3197 r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000); 3198 r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000); 3199 r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000); 3200 3201 /* disable phy pfm mode */ 3202 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3203 3204 rtl8168g_disable_aldps(tp); 3205 rtl8168h_config_eee_phy(tp); 3206 rtl_enable_eee(tp); 3207 } 3208 3209 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) 3210 { 3211 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; 3212 struct phy_device *phydev = tp->phydev; 3213 u16 rlen; 3214 u32 data; 3215 3216 rtl_apply_firmware(tp); 3217 3218 /* CHIN EST parameter update */ 3219 r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a); 3220 3221 /* enable R-tune & PGA-retune function */ 3222 r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800); 3223 phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002); 3224 3225 /* enable GPHY 10M */ 3226 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3227 3228 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 3229 data = r8168_mac_ocp_read(tp, 0xdd02); 3230 ioffset_p3 = ((data & 0x80)>>7); 3231 ioffset_p3 <<= 3; 3232 3233 data = r8168_mac_ocp_read(tp, 0xdd00); 3234 ioffset_p3 |= ((data & (0xe000))>>13); 3235 ioffset_p2 = ((data & (0x1e00))>>9); 3236 ioffset_p1 = ((data & (0x01e0))>>5); 3237 ioffset_p0 = ((data & 0x0010)>>4); 3238 ioffset_p0 <<= 3; 3239 ioffset_p0 |= (data & (0x07)); 3240 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); 3241 3242 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) || 3243 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) 3244 phy_write_paged(phydev, 0x0bcf, 0x16, data); 3245 3246 /* Modify rlen (TX LPF corner frequency) level */ 3247 data = phy_read_paged(phydev, 0x0bcd, 0x16); 3248 data &= 0x000f; 3249 rlen = 0; 3250 if (data > 3) 3251 rlen = data - 3; 3252 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); 3253 phy_write_paged(phydev, 0x0bcd, 0x17, data); 3254 3255 /* disable phy pfm mode */ 3256 phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0); 3257 3258 rtl8168g_disable_aldps(tp); 3259 rtl8168g_config_eee_phy(tp); 3260 rtl_enable_eee(tp); 3261 } 3262 3263 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp) 3264 { 3265 struct phy_device *phydev = tp->phydev; 3266 3267 /* Enable PHY auto speed down */ 3268 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3269 3270 rtl8168g_phy_adjust_10m_aldps(tp); 3271 3272 /* Enable EEE auto-fallback function */ 3273 phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2)); 3274 3275 /* Enable UC LPF tune function */ 3276 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 3277 3278 /* set rg_sel_sdm_rate */ 3279 phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3280 3281 rtl8168g_disable_aldps(tp); 3282 rtl8168g_config_eee_phy(tp); 3283 rtl_enable_eee(tp); 3284 } 3285 3286 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp) 3287 { 3288 struct phy_device *phydev = tp->phydev; 3289 3290 rtl8168g_phy_adjust_10m_aldps(tp); 3291 3292 /* Enable UC LPF tune function */ 3293 r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000); 3294 3295 /* Set rg_sel_sdm_rate */ 3296 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3297 3298 /* Channel estimation parameters */ 3299 r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00); 3300 r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00); 3301 r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500); 3302 r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00); 3303 r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800); 3304 r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00); 3305 r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400); 3306 r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500); 3307 r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800); 3308 r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00); 3309 r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500); 3310 r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100); 3311 r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200); 3312 r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400); 3313 r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00); 3314 r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00); 3315 r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00); 3316 r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00); 3317 r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00); 3318 r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00); 3319 r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400); 3320 3321 /* Force PWM-mode */ 3322 rtl_writephy(tp, 0x1f, 0x0bcd); 3323 rtl_writephy(tp, 0x14, 0x5065); 3324 rtl_writephy(tp, 0x14, 0xd065); 3325 rtl_writephy(tp, 0x1f, 0x0bc8); 3326 rtl_writephy(tp, 0x12, 0x00ed); 3327 rtl_writephy(tp, 0x1f, 0x0bcd); 3328 rtl_writephy(tp, 0x14, 0x1065); 3329 rtl_writephy(tp, 0x14, 0x9065); 3330 rtl_writephy(tp, 0x14, 0x1065); 3331 rtl_writephy(tp, 0x1f, 0x0000); 3332 3333 rtl8168g_disable_aldps(tp); 3334 rtl8168g_config_eee_phy(tp); 3335 rtl_enable_eee(tp); 3336 } 3337 3338 static void rtl8117_hw_phy_config(struct rtl8169_private *tp) 3339 { 3340 struct phy_device *phydev = tp->phydev; 3341 3342 /* CHN EST parameters adjust - fnet */ 3343 r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800); 3344 r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00); 3345 r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000); 3346 3347 r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000); 3348 r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00); 3349 r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600); 3350 r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000); 3351 r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800); 3352 r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000); 3353 r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000); 3354 r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00); 3355 r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800); 3356 r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000); 3357 r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300); 3358 r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800); 3359 r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200); 3360 r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800); 3361 r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800); 3362 r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00); 3363 r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300); 3364 r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300); 3365 3366 r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800); 3367 3368 /* enable GPHY 10M */ 3369 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3370 3371 r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400); 3372 3373 rtl8168g_disable_aldps(tp); 3374 rtl8168h_config_eee_phy(tp); 3375 rtl_enable_eee(tp); 3376 } 3377 3378 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) 3379 { 3380 static const struct phy_reg phy_reg_init[] = { 3381 { 0x1f, 0x0003 }, 3382 { 0x08, 0x441d }, 3383 { 0x01, 0x9100 }, 3384 { 0x1f, 0x0000 } 3385 }; 3386 3387 rtl_writephy(tp, 0x1f, 0x0000); 3388 rtl_patchphy(tp, 0x11, 1 << 12); 3389 rtl_patchphy(tp, 0x19, 1 << 13); 3390 rtl_patchphy(tp, 0x10, 1 << 15); 3391 3392 rtl_writephy_batch(tp, phy_reg_init); 3393 } 3394 3395 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) 3396 { 3397 /* Disable ALDPS before ram code */ 3398 phy_write(tp->phydev, 0x18, 0x0310); 3399 msleep(100); 3400 3401 rtl_apply_firmware(tp); 3402 3403 phy_write_paged(tp->phydev, 0x0005, 0x1a, 0x0000); 3404 phy_write_paged(tp->phydev, 0x0004, 0x1c, 0x0000); 3405 phy_write_paged(tp->phydev, 0x0001, 0x15, 0x7701); 3406 } 3407 3408 static void rtl8402_hw_phy_config(struct rtl8169_private *tp) 3409 { 3410 /* Disable ALDPS before setting firmware */ 3411 phy_write(tp->phydev, 0x18, 0x0310); 3412 msleep(20); 3413 3414 rtl_apply_firmware(tp); 3415 3416 /* EEE setting */ 3417 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3418 rtl_writephy(tp, 0x1f, 0x0004); 3419 rtl_writephy(tp, 0x10, 0x401f); 3420 rtl_writephy(tp, 0x19, 0x7030); 3421 rtl_writephy(tp, 0x1f, 0x0000); 3422 } 3423 3424 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) 3425 { 3426 static const struct phy_reg phy_reg_init[] = { 3427 { 0x1f, 0x0004 }, 3428 { 0x10, 0xc07f }, 3429 { 0x19, 0x7030 }, 3430 { 0x1f, 0x0000 } 3431 }; 3432 3433 /* Disable ALDPS before ram code */ 3434 phy_write(tp->phydev, 0x18, 0x0310); 3435 msleep(100); 3436 3437 rtl_apply_firmware(tp); 3438 3439 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3440 rtl_writephy_batch(tp, phy_reg_init); 3441 3442 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3443 } 3444 3445 static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp) 3446 { 3447 struct phy_device *phydev = tp->phydev; 3448 3449 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084); 3450 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3451 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006); 3452 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3453 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100); 3454 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000); 3455 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400); 3456 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff); 3457 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff); 3458 3459 r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400); 3460 r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300); 3461 r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00); 3462 r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000); 3463 r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500); 3464 r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000); 3465 r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300); 3466 r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000); 3467 r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000); 3468 r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500); 3469 r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00); 3470 r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100); 3471 r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000); 3472 3473 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038); 3474 r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6); 3475 3476 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555); 3477 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00); 3478 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000); 3479 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3480 3481 rtl8125_config_eee_phy(tp); 3482 rtl_enable_eee(tp); 3483 } 3484 3485 static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp) 3486 { 3487 struct phy_device *phydev = tp->phydev; 3488 int i; 3489 3490 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3491 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 3492 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3493 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 3494 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 3495 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 3496 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 3497 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 3498 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 3499 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 3500 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 3501 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 3502 3503 phy_write(phydev, 0x1f, 0x0b87); 3504 phy_write(phydev, 0x16, 0x80a2); 3505 phy_write(phydev, 0x17, 0x0153); 3506 phy_write(phydev, 0x16, 0x809c); 3507 phy_write(phydev, 0x17, 0x0153); 3508 phy_write(phydev, 0x1f, 0x0000); 3509 3510 phy_write(phydev, 0x1f, 0x0a43); 3511 phy_write(phydev, 0x13, 0x81B3); 3512 phy_write(phydev, 0x14, 0x0043); 3513 phy_write(phydev, 0x14, 0x00A7); 3514 phy_write(phydev, 0x14, 0x00D6); 3515 phy_write(phydev, 0x14, 0x00EC); 3516 phy_write(phydev, 0x14, 0x00F6); 3517 phy_write(phydev, 0x14, 0x00FB); 3518 phy_write(phydev, 0x14, 0x00FD); 3519 phy_write(phydev, 0x14, 0x00FF); 3520 phy_write(phydev, 0x14, 0x00BB); 3521 phy_write(phydev, 0x14, 0x0058); 3522 phy_write(phydev, 0x14, 0x0029); 3523 phy_write(phydev, 0x14, 0x0013); 3524 phy_write(phydev, 0x14, 0x0009); 3525 phy_write(phydev, 0x14, 0x0004); 3526 phy_write(phydev, 0x14, 0x0002); 3527 for (i = 0; i < 25; i++) 3528 phy_write(phydev, 0x14, 0x0000); 3529 phy_write(phydev, 0x1f, 0x0000); 3530 3531 r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F); 3532 r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843); 3533 3534 rtl_apply_firmware(tp); 3535 3536 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 3537 3538 r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100); 3539 3540 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 3541 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 3542 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 3543 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 3544 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 3545 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3546 3547 rtl8125_config_eee_phy(tp); 3548 rtl_enable_eee(tp); 3549 } 3550 3551 static void rtl_hw_phy_config(struct net_device *dev) 3552 { 3553 static const rtl_generic_fct phy_configs[] = { 3554 /* PCI devices. */ 3555 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 3556 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 3557 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 3558 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 3559 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 3560 /* PCI-E devices. */ 3561 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 3562 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 3563 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 3564 [RTL_GIGA_MAC_VER_10] = NULL, 3565 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 3566 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config, 3567 [RTL_GIGA_MAC_VER_13] = NULL, 3568 [RTL_GIGA_MAC_VER_14] = NULL, 3569 [RTL_GIGA_MAC_VER_15] = NULL, 3570 [RTL_GIGA_MAC_VER_16] = NULL, 3571 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 3572 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 3573 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 3574 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 3575 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 3576 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config, 3577 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 3578 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 3579 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 3580 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 3581 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config, 3582 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 3583 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 3584 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 3585 [RTL_GIGA_MAC_VER_31] = NULL, 3586 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 3587 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 3588 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 3589 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 3590 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 3591 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 3592 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 3593 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 3594 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 3595 [RTL_GIGA_MAC_VER_41] = NULL, 3596 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 3597 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 3598 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 3599 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config, 3600 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 3601 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config, 3602 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 3603 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config, 3604 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config, 3605 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 3606 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config, 3607 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config, 3608 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config, 3609 }; 3610 struct rtl8169_private *tp = netdev_priv(dev); 3611 3612 if (phy_configs[tp->mac_version]) 3613 phy_configs[tp->mac_version](tp); 3614 } 3615 3616 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 3617 { 3618 if (!test_and_set_bit(flag, tp->wk.flags)) 3619 schedule_work(&tp->wk.work); 3620 } 3621 3622 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 3623 { 3624 rtl_hw_phy_config(dev); 3625 3626 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 3627 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 3628 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 3629 netif_dbg(tp, drv, dev, 3630 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 3631 RTL_W8(tp, 0x82, 0x01); 3632 } 3633 3634 /* We may have called phy_speed_down before */ 3635 phy_speed_up(tp->phydev); 3636 3637 genphy_soft_reset(tp->phydev); 3638 } 3639 3640 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 3641 { 3642 rtl_lock_work(tp); 3643 3644 rtl_unlock_config_regs(tp); 3645 3646 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 3647 RTL_R32(tp, MAC4); 3648 3649 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3650 RTL_R32(tp, MAC0); 3651 3652 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 3653 rtl_rar_exgmac_set(tp, addr); 3654 3655 rtl_lock_config_regs(tp); 3656 3657 rtl_unlock_work(tp); 3658 } 3659 3660 static int rtl_set_mac_address(struct net_device *dev, void *p) 3661 { 3662 struct rtl8169_private *tp = netdev_priv(dev); 3663 struct device *d = tp_to_dev(tp); 3664 int ret; 3665 3666 ret = eth_mac_addr(dev, p); 3667 if (ret) 3668 return ret; 3669 3670 pm_runtime_get_noresume(d); 3671 3672 if (pm_runtime_active(d)) 3673 rtl_rar_set(tp, dev->dev_addr); 3674 3675 pm_runtime_put_noidle(d); 3676 3677 return 0; 3678 } 3679 3680 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3681 { 3682 struct rtl8169_private *tp = netdev_priv(dev); 3683 3684 if (!netif_running(dev)) 3685 return -ENODEV; 3686 3687 return phy_mii_ioctl(tp->phydev, ifr, cmd); 3688 } 3689 3690 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 3691 { 3692 switch (tp->mac_version) { 3693 case RTL_GIGA_MAC_VER_25: 3694 case RTL_GIGA_MAC_VER_26: 3695 case RTL_GIGA_MAC_VER_29: 3696 case RTL_GIGA_MAC_VER_30: 3697 case RTL_GIGA_MAC_VER_32: 3698 case RTL_GIGA_MAC_VER_33: 3699 case RTL_GIGA_MAC_VER_34: 3700 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_52: 3701 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 3702 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 3703 break; 3704 default: 3705 break; 3706 } 3707 } 3708 3709 static void rtl_pll_power_down(struct rtl8169_private *tp) 3710 { 3711 if (r8168_check_dash(tp)) 3712 return; 3713 3714 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 3715 tp->mac_version == RTL_GIGA_MAC_VER_33) 3716 rtl_ephy_write(tp, 0x19, 0xff64); 3717 3718 if (device_may_wakeup(tp_to_dev(tp))) { 3719 phy_speed_down(tp->phydev, false); 3720 rtl_wol_suspend_quirk(tp); 3721 return; 3722 } 3723 3724 switch (tp->mac_version) { 3725 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3726 case RTL_GIGA_MAC_VER_37: 3727 case RTL_GIGA_MAC_VER_39: 3728 case RTL_GIGA_MAC_VER_43: 3729 case RTL_GIGA_MAC_VER_44: 3730 case RTL_GIGA_MAC_VER_45: 3731 case RTL_GIGA_MAC_VER_46: 3732 case RTL_GIGA_MAC_VER_47: 3733 case RTL_GIGA_MAC_VER_48: 3734 case RTL_GIGA_MAC_VER_50: 3735 case RTL_GIGA_MAC_VER_51: 3736 case RTL_GIGA_MAC_VER_52: 3737 case RTL_GIGA_MAC_VER_60: 3738 case RTL_GIGA_MAC_VER_61: 3739 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3740 break; 3741 case RTL_GIGA_MAC_VER_40: 3742 case RTL_GIGA_MAC_VER_41: 3743 case RTL_GIGA_MAC_VER_49: 3744 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3745 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3746 break; 3747 default: 3748 break; 3749 } 3750 } 3751 3752 static void rtl_pll_power_up(struct rtl8169_private *tp) 3753 { 3754 switch (tp->mac_version) { 3755 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3756 case RTL_GIGA_MAC_VER_37: 3757 case RTL_GIGA_MAC_VER_39: 3758 case RTL_GIGA_MAC_VER_43: 3759 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 3760 break; 3761 case RTL_GIGA_MAC_VER_44: 3762 case RTL_GIGA_MAC_VER_45: 3763 case RTL_GIGA_MAC_VER_46: 3764 case RTL_GIGA_MAC_VER_47: 3765 case RTL_GIGA_MAC_VER_48: 3766 case RTL_GIGA_MAC_VER_50: 3767 case RTL_GIGA_MAC_VER_51: 3768 case RTL_GIGA_MAC_VER_52: 3769 case RTL_GIGA_MAC_VER_60: 3770 case RTL_GIGA_MAC_VER_61: 3771 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3772 break; 3773 case RTL_GIGA_MAC_VER_40: 3774 case RTL_GIGA_MAC_VER_41: 3775 case RTL_GIGA_MAC_VER_49: 3776 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3777 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3778 break; 3779 default: 3780 break; 3781 } 3782 3783 phy_resume(tp->phydev); 3784 /* give MAC/PHY some time to resume */ 3785 msleep(20); 3786 } 3787 3788 static void rtl_init_rxcfg(struct rtl8169_private *tp) 3789 { 3790 switch (tp->mac_version) { 3791 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 3792 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 3793 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 3794 break; 3795 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 3796 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 3797 case RTL_GIGA_MAC_VER_38: 3798 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 3799 break; 3800 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 3801 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 3802 break; 3803 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 3804 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 | 3805 RX_DMA_BURST); 3806 break; 3807 default: 3808 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 3809 break; 3810 } 3811 } 3812 3813 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 3814 { 3815 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 3816 } 3817 3818 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 3819 { 3820 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 3821 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 3822 } 3823 3824 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 3825 { 3826 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 3827 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 3828 } 3829 3830 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 3831 { 3832 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 3833 } 3834 3835 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 3836 { 3837 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 3838 } 3839 3840 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 3841 { 3842 RTL_W8(tp, MaxTxPacketSize, 0x3f); 3843 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 3844 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 3845 } 3846 3847 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 3848 { 3849 RTL_W8(tp, MaxTxPacketSize, 0x0c); 3850 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 3851 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 3852 } 3853 3854 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 3855 { 3856 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 3857 } 3858 3859 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 3860 { 3861 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 3862 } 3863 3864 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) 3865 { 3866 rtl_unlock_config_regs(tp); 3867 switch (tp->mac_version) { 3868 case RTL_GIGA_MAC_VER_12: 3869 case RTL_GIGA_MAC_VER_17: 3870 r8168b_1_hw_jumbo_enable(tp); 3871 break; 3872 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 3873 r8168c_hw_jumbo_enable(tp); 3874 break; 3875 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 3876 r8168dp_hw_jumbo_enable(tp); 3877 break; 3878 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 3879 r8168e_hw_jumbo_enable(tp); 3880 break; 3881 default: 3882 break; 3883 } 3884 rtl_lock_config_regs(tp); 3885 } 3886 3887 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) 3888 { 3889 rtl_unlock_config_regs(tp); 3890 switch (tp->mac_version) { 3891 case RTL_GIGA_MAC_VER_12: 3892 case RTL_GIGA_MAC_VER_17: 3893 r8168b_1_hw_jumbo_disable(tp); 3894 break; 3895 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 3896 r8168c_hw_jumbo_disable(tp); 3897 break; 3898 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 3899 r8168dp_hw_jumbo_disable(tp); 3900 break; 3901 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 3902 r8168e_hw_jumbo_disable(tp); 3903 break; 3904 default: 3905 break; 3906 } 3907 rtl_lock_config_regs(tp); 3908 } 3909 3910 static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu) 3911 { 3912 if (mtu > ETH_DATA_LEN) 3913 rtl_hw_jumbo_enable(tp); 3914 else 3915 rtl_hw_jumbo_disable(tp); 3916 } 3917 3918 DECLARE_RTL_COND(rtl_chipcmd_cond) 3919 { 3920 return RTL_R8(tp, ChipCmd) & CmdReset; 3921 } 3922 3923 static void rtl_hw_reset(struct rtl8169_private *tp) 3924 { 3925 RTL_W8(tp, ChipCmd, CmdReset); 3926 3927 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 3928 } 3929 3930 static void rtl_request_firmware(struct rtl8169_private *tp) 3931 { 3932 struct rtl_fw *rtl_fw; 3933 3934 /* firmware loaded already or no firmware available */ 3935 if (tp->rtl_fw || !tp->fw_name) 3936 return; 3937 3938 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 3939 if (!rtl_fw) { 3940 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n"); 3941 return; 3942 } 3943 3944 rtl_fw->phy_write = rtl_writephy; 3945 rtl_fw->phy_read = rtl_readphy; 3946 rtl_fw->mac_mcu_write = mac_mcu_write; 3947 rtl_fw->mac_mcu_read = mac_mcu_read; 3948 rtl_fw->fw_name = tp->fw_name; 3949 rtl_fw->dev = tp_to_dev(tp); 3950 3951 if (rtl_fw_request_firmware(rtl_fw)) 3952 kfree(rtl_fw); 3953 else 3954 tp->rtl_fw = rtl_fw; 3955 } 3956 3957 static void rtl_rx_close(struct rtl8169_private *tp) 3958 { 3959 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 3960 } 3961 3962 DECLARE_RTL_COND(rtl_npq_cond) 3963 { 3964 return RTL_R8(tp, TxPoll) & NPQ; 3965 } 3966 3967 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 3968 { 3969 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 3970 } 3971 3972 static void rtl8169_hw_reset(struct rtl8169_private *tp) 3973 { 3974 /* Disable interrupts */ 3975 rtl8169_irq_mask_and_ack(tp); 3976 3977 rtl_rx_close(tp); 3978 3979 switch (tp->mac_version) { 3980 case RTL_GIGA_MAC_VER_27: 3981 case RTL_GIGA_MAC_VER_28: 3982 case RTL_GIGA_MAC_VER_31: 3983 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 3984 break; 3985 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3986 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 3987 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3988 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3989 break; 3990 default: 3991 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3992 udelay(100); 3993 break; 3994 } 3995 3996 rtl_hw_reset(tp); 3997 } 3998 3999 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 4000 { 4001 u32 val = TX_DMA_BURST << TxDMAShift | 4002 InterFrameGap << TxInterFrameGapShift; 4003 4004 if (rtl_is_8168evl_up(tp)) 4005 val |= TXCFG_AUTO_FIFO; 4006 4007 RTL_W32(tp, TxConfig, val); 4008 } 4009 4010 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 4011 { 4012 /* Low hurts. Let's disable the filtering. */ 4013 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 4014 } 4015 4016 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 4017 { 4018 /* 4019 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 4020 * register to be written before TxDescAddrLow to work. 4021 * Switching from MMIO to I/O access fixes the issue as well. 4022 */ 4023 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 4024 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 4025 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 4026 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 4027 } 4028 4029 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) 4030 { 4031 u32 val; 4032 4033 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 4034 val = 0x000fff00; 4035 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 4036 val = 0x00ffff00; 4037 else 4038 return; 4039 4040 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 4041 val |= 0xff; 4042 4043 RTL_W32(tp, 0x7c, val); 4044 } 4045 4046 static void rtl_set_rx_mode(struct net_device *dev) 4047 { 4048 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 4049 /* Multicast hash filter */ 4050 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 4051 struct rtl8169_private *tp = netdev_priv(dev); 4052 u32 tmp; 4053 4054 if (dev->flags & IFF_PROMISC) { 4055 /* Unconditionally log net taps. */ 4056 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); 4057 rx_mode |= AcceptAllPhys; 4058 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 4059 dev->flags & IFF_ALLMULTI || 4060 tp->mac_version == RTL_GIGA_MAC_VER_35) { 4061 /* accept all multicasts */ 4062 } else if (netdev_mc_empty(dev)) { 4063 rx_mode &= ~AcceptMulticast; 4064 } else { 4065 struct netdev_hw_addr *ha; 4066 4067 mc_filter[1] = mc_filter[0] = 0; 4068 netdev_for_each_mc_addr(ha, dev) { 4069 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 4070 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 4071 } 4072 4073 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 4074 tmp = mc_filter[0]; 4075 mc_filter[0] = swab32(mc_filter[1]); 4076 mc_filter[1] = swab32(tmp); 4077 } 4078 } 4079 4080 if (dev->features & NETIF_F_RXALL) 4081 rx_mode |= (AcceptErr | AcceptRunt); 4082 4083 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 4084 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 4085 4086 tmp = RTL_R32(tp, RxConfig); 4087 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); 4088 } 4089 4090 DECLARE_RTL_COND(rtl_csiar_cond) 4091 { 4092 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 4093 } 4094 4095 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 4096 { 4097 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4098 4099 RTL_W32(tp, CSIDR, value); 4100 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 4101 CSIAR_BYTE_ENABLE | func << 16); 4102 4103 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 4104 } 4105 4106 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 4107 { 4108 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4109 4110 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 4111 CSIAR_BYTE_ENABLE); 4112 4113 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 4114 RTL_R32(tp, CSIDR) : ~0; 4115 } 4116 4117 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 4118 { 4119 struct pci_dev *pdev = tp->pci_dev; 4120 u32 csi; 4121 4122 /* According to Realtek the value at config space address 0x070f 4123 * controls the L0s/L1 entrance latency. We try standard ECAM access 4124 * first and if it fails fall back to CSI. 4125 */ 4126 if (pdev->cfg_size > 0x070f && 4127 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 4128 return; 4129 4130 netdev_notice_once(tp->dev, 4131 "No native access to PCI extended config space, falling back to CSI\n"); 4132 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 4133 rtl_csi_write(tp, 0x070c, csi | val << 24); 4134 } 4135 4136 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 4137 { 4138 rtl_csi_access_enable(tp, 0x27); 4139 } 4140 4141 struct ephy_info { 4142 unsigned int offset; 4143 u16 mask; 4144 u16 bits; 4145 }; 4146 4147 static void __rtl_ephy_init(struct rtl8169_private *tp, 4148 const struct ephy_info *e, int len) 4149 { 4150 u16 w; 4151 4152 while (len-- > 0) { 4153 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 4154 rtl_ephy_write(tp, e->offset, w); 4155 e++; 4156 } 4157 } 4158 4159 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 4160 4161 static void rtl_disable_clock_request(struct rtl8169_private *tp) 4162 { 4163 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 4164 PCI_EXP_LNKCTL_CLKREQ_EN); 4165 } 4166 4167 static void rtl_enable_clock_request(struct rtl8169_private *tp) 4168 { 4169 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 4170 PCI_EXP_LNKCTL_CLKREQ_EN); 4171 } 4172 4173 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 4174 { 4175 /* work around an issue when PCI reset occurs during L2/L3 state */ 4176 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 4177 } 4178 4179 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 4180 { 4181 /* Don't enable ASPM in the chip if OS can't control ASPM */ 4182 if (enable && tp->aspm_manageable) { 4183 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 4184 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 4185 } else { 4186 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4187 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4188 } 4189 4190 udelay(10); 4191 } 4192 4193 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 4194 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 4195 { 4196 /* Usage of dynamic vs. static FIFO is controlled by bit 4197 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 4198 */ 4199 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 4200 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 4201 } 4202 4203 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 4204 u8 low, u8 high) 4205 { 4206 /* FIFO thresholds for pause flow control */ 4207 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 4208 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 4209 } 4210 4211 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 4212 { 4213 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4214 } 4215 4216 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 4217 { 4218 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 4219 4220 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4221 4222 rtl_disable_clock_request(tp); 4223 } 4224 4225 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 4226 { 4227 static const struct ephy_info e_info_8168cp[] = { 4228 { 0x01, 0, 0x0001 }, 4229 { 0x02, 0x0800, 0x1000 }, 4230 { 0x03, 0, 0x0042 }, 4231 { 0x06, 0x0080, 0x0000 }, 4232 { 0x07, 0, 0x2000 } 4233 }; 4234 4235 rtl_set_def_aspm_entry_latency(tp); 4236 4237 rtl_ephy_init(tp, e_info_8168cp); 4238 4239 __rtl_hw_start_8168cp(tp); 4240 } 4241 4242 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 4243 { 4244 rtl_set_def_aspm_entry_latency(tp); 4245 4246 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4247 } 4248 4249 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 4250 { 4251 rtl_set_def_aspm_entry_latency(tp); 4252 4253 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4254 4255 /* Magic. */ 4256 RTL_W8(tp, DBG_REG, 0x20); 4257 } 4258 4259 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 4260 { 4261 static const struct ephy_info e_info_8168c_1[] = { 4262 { 0x02, 0x0800, 0x1000 }, 4263 { 0x03, 0, 0x0002 }, 4264 { 0x06, 0x0080, 0x0000 } 4265 }; 4266 4267 rtl_set_def_aspm_entry_latency(tp); 4268 4269 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 4270 4271 rtl_ephy_init(tp, e_info_8168c_1); 4272 4273 __rtl_hw_start_8168cp(tp); 4274 } 4275 4276 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 4277 { 4278 static const struct ephy_info e_info_8168c_2[] = { 4279 { 0x01, 0, 0x0001 }, 4280 { 0x03, 0x0400, 0x0020 } 4281 }; 4282 4283 rtl_set_def_aspm_entry_latency(tp); 4284 4285 rtl_ephy_init(tp, e_info_8168c_2); 4286 4287 __rtl_hw_start_8168cp(tp); 4288 } 4289 4290 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 4291 { 4292 rtl_hw_start_8168c_2(tp); 4293 } 4294 4295 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 4296 { 4297 rtl_set_def_aspm_entry_latency(tp); 4298 4299 __rtl_hw_start_8168cp(tp); 4300 } 4301 4302 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 4303 { 4304 rtl_set_def_aspm_entry_latency(tp); 4305 4306 rtl_disable_clock_request(tp); 4307 } 4308 4309 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 4310 { 4311 static const struct ephy_info e_info_8168d_4[] = { 4312 { 0x0b, 0x0000, 0x0048 }, 4313 { 0x19, 0x0020, 0x0050 }, 4314 { 0x0c, 0x0100, 0x0020 }, 4315 { 0x10, 0x0004, 0x0000 }, 4316 }; 4317 4318 rtl_set_def_aspm_entry_latency(tp); 4319 4320 rtl_ephy_init(tp, e_info_8168d_4); 4321 4322 rtl_enable_clock_request(tp); 4323 } 4324 4325 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 4326 { 4327 static const struct ephy_info e_info_8168e_1[] = { 4328 { 0x00, 0x0200, 0x0100 }, 4329 { 0x00, 0x0000, 0x0004 }, 4330 { 0x06, 0x0002, 0x0001 }, 4331 { 0x06, 0x0000, 0x0030 }, 4332 { 0x07, 0x0000, 0x2000 }, 4333 { 0x00, 0x0000, 0x0020 }, 4334 { 0x03, 0x5800, 0x2000 }, 4335 { 0x03, 0x0000, 0x0001 }, 4336 { 0x01, 0x0800, 0x1000 }, 4337 { 0x07, 0x0000, 0x4000 }, 4338 { 0x1e, 0x0000, 0x2000 }, 4339 { 0x19, 0xffff, 0xfe6c }, 4340 { 0x0a, 0x0000, 0x0040 } 4341 }; 4342 4343 rtl_set_def_aspm_entry_latency(tp); 4344 4345 rtl_ephy_init(tp, e_info_8168e_1); 4346 4347 rtl_disable_clock_request(tp); 4348 4349 /* Reset tx FIFO pointer */ 4350 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 4351 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 4352 4353 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4354 } 4355 4356 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 4357 { 4358 static const struct ephy_info e_info_8168e_2[] = { 4359 { 0x09, 0x0000, 0x0080 }, 4360 { 0x19, 0x0000, 0x0224 }, 4361 { 0x00, 0x0000, 0x0004 }, 4362 { 0x0c, 0x3df0, 0x0200 }, 4363 }; 4364 4365 rtl_set_def_aspm_entry_latency(tp); 4366 4367 rtl_ephy_init(tp, e_info_8168e_2); 4368 4369 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4370 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4371 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4372 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4373 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 4374 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4375 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4376 4377 rtl_disable_clock_request(tp); 4378 4379 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4380 4381 rtl8168_config_eee_mac(tp); 4382 4383 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4384 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4385 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4386 4387 rtl_hw_aspm_clkreq_enable(tp, true); 4388 } 4389 4390 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 4391 { 4392 rtl_set_def_aspm_entry_latency(tp); 4393 4394 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4395 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4396 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4397 rtl_reset_packet_filter(tp); 4398 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4399 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 4400 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4401 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 4402 4403 rtl_disable_clock_request(tp); 4404 4405 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4406 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4407 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4408 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4409 4410 rtl8168_config_eee_mac(tp); 4411 } 4412 4413 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 4414 { 4415 static const struct ephy_info e_info_8168f_1[] = { 4416 { 0x06, 0x00c0, 0x0020 }, 4417 { 0x08, 0x0001, 0x0002 }, 4418 { 0x09, 0x0000, 0x0080 }, 4419 { 0x19, 0x0000, 0x0224 }, 4420 { 0x00, 0x0000, 0x0004 }, 4421 { 0x0c, 0x3df0, 0x0200 }, 4422 }; 4423 4424 rtl_hw_start_8168f(tp); 4425 4426 rtl_ephy_init(tp, e_info_8168f_1); 4427 4428 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4429 } 4430 4431 static void rtl_hw_start_8411(struct rtl8169_private *tp) 4432 { 4433 static const struct ephy_info e_info_8168f_1[] = { 4434 { 0x06, 0x00c0, 0x0020 }, 4435 { 0x0f, 0xffff, 0x5200 }, 4436 { 0x19, 0x0000, 0x0224 }, 4437 { 0x00, 0x0000, 0x0004 }, 4438 { 0x0c, 0x3df0, 0x0200 }, 4439 }; 4440 4441 rtl_hw_start_8168f(tp); 4442 rtl_pcie_state_l2l3_disable(tp); 4443 4444 rtl_ephy_init(tp, e_info_8168f_1); 4445 4446 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 4447 } 4448 4449 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 4450 { 4451 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4452 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4453 4454 rtl_set_def_aspm_entry_latency(tp); 4455 4456 rtl_reset_packet_filter(tp); 4457 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 4458 4459 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4460 4461 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4462 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4463 4464 rtl8168_config_eee_mac(tp); 4465 4466 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4467 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4468 4469 rtl_pcie_state_l2l3_disable(tp); 4470 } 4471 4472 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 4473 { 4474 static const struct ephy_info e_info_8168g_1[] = { 4475 { 0x00, 0x0008, 0x0000 }, 4476 { 0x0c, 0x3ff0, 0x0820 }, 4477 { 0x1e, 0x0000, 0x0001 }, 4478 { 0x19, 0x8000, 0x0000 } 4479 }; 4480 4481 rtl_hw_start_8168g(tp); 4482 4483 /* disable aspm and clock request before access ephy */ 4484 rtl_hw_aspm_clkreq_enable(tp, false); 4485 rtl_ephy_init(tp, e_info_8168g_1); 4486 rtl_hw_aspm_clkreq_enable(tp, true); 4487 } 4488 4489 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 4490 { 4491 static const struct ephy_info e_info_8168g_2[] = { 4492 { 0x00, 0x0008, 0x0000 }, 4493 { 0x0c, 0x3ff0, 0x0820 }, 4494 { 0x19, 0xffff, 0x7c00 }, 4495 { 0x1e, 0xffff, 0x20eb }, 4496 { 0x0d, 0xffff, 0x1666 }, 4497 { 0x00, 0xffff, 0x10a3 }, 4498 { 0x06, 0xffff, 0xf050 }, 4499 { 0x04, 0x0000, 0x0010 }, 4500 { 0x1d, 0x4000, 0x0000 }, 4501 }; 4502 4503 rtl_hw_start_8168g(tp); 4504 4505 /* disable aspm and clock request before access ephy */ 4506 rtl_hw_aspm_clkreq_enable(tp, false); 4507 rtl_ephy_init(tp, e_info_8168g_2); 4508 } 4509 4510 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 4511 { 4512 static const struct ephy_info e_info_8411_2[] = { 4513 { 0x00, 0x0008, 0x0000 }, 4514 { 0x0c, 0x37d0, 0x0820 }, 4515 { 0x1e, 0x0000, 0x0001 }, 4516 { 0x19, 0x8021, 0x0000 }, 4517 { 0x1e, 0x0000, 0x2000 }, 4518 { 0x0d, 0x0100, 0x0200 }, 4519 { 0x00, 0x0000, 0x0080 }, 4520 { 0x06, 0x0000, 0x0010 }, 4521 { 0x04, 0x0000, 0x0010 }, 4522 { 0x1d, 0x0000, 0x4000 }, 4523 }; 4524 4525 rtl_hw_start_8168g(tp); 4526 4527 /* disable aspm and clock request before access ephy */ 4528 rtl_hw_aspm_clkreq_enable(tp, false); 4529 rtl_ephy_init(tp, e_info_8411_2); 4530 4531 /* The following Realtek-provided magic fixes an issue with the RX unit 4532 * getting confused after the PHY having been powered-down. 4533 */ 4534 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 4535 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 4536 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 4537 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 4538 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 4539 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 4540 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 4541 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 4542 mdelay(3); 4543 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 4544 4545 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 4546 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 4547 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 4548 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 4549 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 4550 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 4551 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 4552 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 4553 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 4554 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 4555 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 4556 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 4557 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 4558 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 4559 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 4560 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 4561 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 4562 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 4563 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 4564 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 4565 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 4566 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 4567 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 4568 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 4569 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 4570 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 4571 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 4572 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 4573 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 4574 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 4575 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 4576 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 4577 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 4578 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 4579 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 4580 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 4581 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 4582 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 4583 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 4584 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 4585 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 4586 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 4587 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 4588 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 4589 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 4590 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 4591 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 4592 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 4593 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 4594 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 4595 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 4596 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 4597 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 4598 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 4599 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 4600 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 4601 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 4602 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 4603 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 4604 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 4605 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 4606 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 4607 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 4608 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 4609 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 4610 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 4611 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 4612 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 4613 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 4614 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 4615 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 4616 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 4617 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 4618 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 4619 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 4620 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 4621 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 4622 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 4623 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 4624 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 4625 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 4626 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 4627 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 4628 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 4629 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 4630 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 4631 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 4632 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 4633 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 4634 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 4635 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 4636 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 4637 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 4638 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 4639 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 4640 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 4641 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 4642 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 4643 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 4644 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 4645 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 4646 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 4647 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 4648 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 4649 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 4650 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 4651 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 4652 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 4653 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 4654 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 4655 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 4656 4657 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 4658 4659 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 4660 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 4661 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 4662 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 4663 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 4664 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 4665 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 4666 4667 rtl_hw_aspm_clkreq_enable(tp, true); 4668 } 4669 4670 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 4671 { 4672 static const struct ephy_info e_info_8168h_1[] = { 4673 { 0x1e, 0x0800, 0x0001 }, 4674 { 0x1d, 0x0000, 0x0800 }, 4675 { 0x05, 0xffff, 0x2089 }, 4676 { 0x06, 0xffff, 0x5881 }, 4677 { 0x04, 0xffff, 0x854a }, 4678 { 0x01, 0xffff, 0x068b } 4679 }; 4680 int rg_saw_cnt; 4681 4682 /* disable aspm and clock request before access ephy */ 4683 rtl_hw_aspm_clkreq_enable(tp, false); 4684 rtl_ephy_init(tp, e_info_8168h_1); 4685 4686 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4687 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4688 4689 rtl_set_def_aspm_entry_latency(tp); 4690 4691 rtl_reset_packet_filter(tp); 4692 4693 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 4694 4695 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 4696 4697 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4698 4699 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4700 4701 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4702 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4703 4704 rtl8168_config_eee_mac(tp); 4705 4706 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4707 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4708 4709 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4710 4711 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4712 4713 rtl_pcie_state_l2l3_disable(tp); 4714 4715 rtl_writephy(tp, 0x1f, 0x0c42); 4716 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff); 4717 rtl_writephy(tp, 0x1f, 0x0000); 4718 if (rg_saw_cnt > 0) { 4719 u16 sw_cnt_1ms_ini; 4720 4721 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 4722 sw_cnt_1ms_ini &= 0x0fff; 4723 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 4724 } 4725 4726 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 4727 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 4728 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 4729 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 4730 4731 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 4732 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 4733 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 4734 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 4735 4736 rtl_hw_aspm_clkreq_enable(tp, true); 4737 } 4738 4739 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 4740 { 4741 rtl8168ep_stop_cmac(tp); 4742 4743 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4744 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 4745 4746 rtl_set_def_aspm_entry_latency(tp); 4747 4748 rtl_reset_packet_filter(tp); 4749 4750 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 4751 4752 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4753 4754 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4755 4756 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4757 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4758 4759 rtl8168_config_eee_mac(tp); 4760 4761 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4762 4763 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4764 4765 rtl_pcie_state_l2l3_disable(tp); 4766 } 4767 4768 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 4769 { 4770 static const struct ephy_info e_info_8168ep_1[] = { 4771 { 0x00, 0xffff, 0x10ab }, 4772 { 0x06, 0xffff, 0xf030 }, 4773 { 0x08, 0xffff, 0x2006 }, 4774 { 0x0d, 0xffff, 0x1666 }, 4775 { 0x0c, 0x3ff0, 0x0000 } 4776 }; 4777 4778 /* disable aspm and clock request before access ephy */ 4779 rtl_hw_aspm_clkreq_enable(tp, false); 4780 rtl_ephy_init(tp, e_info_8168ep_1); 4781 4782 rtl_hw_start_8168ep(tp); 4783 4784 rtl_hw_aspm_clkreq_enable(tp, true); 4785 } 4786 4787 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 4788 { 4789 static const struct ephy_info e_info_8168ep_2[] = { 4790 { 0x00, 0xffff, 0x10a3 }, 4791 { 0x19, 0xffff, 0xfc00 }, 4792 { 0x1e, 0xffff, 0x20ea } 4793 }; 4794 4795 /* disable aspm and clock request before access ephy */ 4796 rtl_hw_aspm_clkreq_enable(tp, false); 4797 rtl_ephy_init(tp, e_info_8168ep_2); 4798 4799 rtl_hw_start_8168ep(tp); 4800 4801 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4802 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4803 4804 rtl_hw_aspm_clkreq_enable(tp, true); 4805 } 4806 4807 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 4808 { 4809 static const struct ephy_info e_info_8168ep_3[] = { 4810 { 0x00, 0x0000, 0x0080 }, 4811 { 0x0d, 0x0100, 0x0200 }, 4812 { 0x19, 0x8021, 0x0000 }, 4813 { 0x1e, 0x0000, 0x2000 }, 4814 }; 4815 4816 /* disable aspm and clock request before access ephy */ 4817 rtl_hw_aspm_clkreq_enable(tp, false); 4818 rtl_ephy_init(tp, e_info_8168ep_3); 4819 4820 rtl_hw_start_8168ep(tp); 4821 4822 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4823 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4824 4825 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 4826 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 4827 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 4828 4829 rtl_hw_aspm_clkreq_enable(tp, true); 4830 } 4831 4832 static void rtl_hw_start_8117(struct rtl8169_private *tp) 4833 { 4834 static const struct ephy_info e_info_8117[] = { 4835 { 0x19, 0x0040, 0x1100 }, 4836 { 0x59, 0x0040, 0x1100 }, 4837 }; 4838 int rg_saw_cnt; 4839 4840 rtl8168ep_stop_cmac(tp); 4841 4842 /* disable aspm and clock request before access ephy */ 4843 rtl_hw_aspm_clkreq_enable(tp, false); 4844 rtl_ephy_init(tp, e_info_8117); 4845 4846 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4847 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 4848 4849 rtl_set_def_aspm_entry_latency(tp); 4850 4851 rtl_reset_packet_filter(tp); 4852 4853 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90); 4854 4855 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4856 4857 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4858 4859 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4860 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4861 4862 rtl8168_config_eee_mac(tp); 4863 4864 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4865 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4866 4867 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4868 4869 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4870 4871 rtl_pcie_state_l2l3_disable(tp); 4872 4873 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 4874 if (rg_saw_cnt > 0) { 4875 u16 sw_cnt_1ms_ini; 4876 4877 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 4878 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 4879 } 4880 4881 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 4882 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 4883 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 4884 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 4885 4886 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 4887 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 4888 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 4889 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 4890 4891 rtl_hw_aspm_clkreq_enable(tp, true); 4892 } 4893 4894 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 4895 { 4896 static const struct ephy_info e_info_8102e_1[] = { 4897 { 0x01, 0, 0x6e65 }, 4898 { 0x02, 0, 0x091f }, 4899 { 0x03, 0, 0xc2f9 }, 4900 { 0x06, 0, 0xafb5 }, 4901 { 0x07, 0, 0x0e00 }, 4902 { 0x19, 0, 0xec80 }, 4903 { 0x01, 0, 0x2e65 }, 4904 { 0x01, 0, 0x6e65 } 4905 }; 4906 u8 cfg1; 4907 4908 rtl_set_def_aspm_entry_latency(tp); 4909 4910 RTL_W8(tp, DBG_REG, FIX_NAK_1); 4911 4912 RTL_W8(tp, Config1, 4913 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 4914 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4915 4916 cfg1 = RTL_R8(tp, Config1); 4917 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 4918 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 4919 4920 rtl_ephy_init(tp, e_info_8102e_1); 4921 } 4922 4923 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 4924 { 4925 rtl_set_def_aspm_entry_latency(tp); 4926 4927 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 4928 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4929 } 4930 4931 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 4932 { 4933 rtl_hw_start_8102e_2(tp); 4934 4935 rtl_ephy_write(tp, 0x03, 0xc2f9); 4936 } 4937 4938 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 4939 { 4940 static const struct ephy_info e_info_8105e_1[] = { 4941 { 0x07, 0, 0x4000 }, 4942 { 0x19, 0, 0x0200 }, 4943 { 0x19, 0, 0x0020 }, 4944 { 0x1e, 0, 0x2000 }, 4945 { 0x03, 0, 0x0001 }, 4946 { 0x19, 0, 0x0100 }, 4947 { 0x19, 0, 0x0004 }, 4948 { 0x0a, 0, 0x0020 } 4949 }; 4950 4951 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 4952 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 4953 4954 /* Disable Early Tally Counter */ 4955 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 4956 4957 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 4958 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4959 4960 rtl_ephy_init(tp, e_info_8105e_1); 4961 4962 rtl_pcie_state_l2l3_disable(tp); 4963 } 4964 4965 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 4966 { 4967 rtl_hw_start_8105e_1(tp); 4968 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 4969 } 4970 4971 static void rtl_hw_start_8402(struct rtl8169_private *tp) 4972 { 4973 static const struct ephy_info e_info_8402[] = { 4974 { 0x19, 0xffff, 0xff64 }, 4975 { 0x1e, 0, 0x4000 } 4976 }; 4977 4978 rtl_set_def_aspm_entry_latency(tp); 4979 4980 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 4981 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 4982 4983 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4984 4985 rtl_ephy_init(tp, e_info_8402); 4986 4987 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 4988 rtl_reset_packet_filter(tp); 4989 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4990 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4991 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 4992 4993 rtl_pcie_state_l2l3_disable(tp); 4994 } 4995 4996 static void rtl_hw_start_8106(struct rtl8169_private *tp) 4997 { 4998 rtl_hw_aspm_clkreq_enable(tp, false); 4999 5000 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5001 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5002 5003 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 5004 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5005 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5006 5007 rtl_pcie_state_l2l3_disable(tp); 5008 rtl_hw_aspm_clkreq_enable(tp, true); 5009 } 5010 5011 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 5012 { 5013 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 5014 } 5015 5016 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 5017 { 5018 rtl_pcie_state_l2l3_disable(tp); 5019 5020 RTL_W16(tp, 0x382, 0x221b); 5021 RTL_W8(tp, 0x4500, 0); 5022 RTL_W16(tp, 0x4800, 0); 5023 5024 /* disable UPS */ 5025 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 5026 5027 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 5028 5029 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 5030 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 5031 5032 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 5033 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 5034 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 5035 5036 /* disable new tx descriptor format */ 5037 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 5038 5039 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 5040 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 5041 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 5042 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 5043 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 5044 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 5045 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 5046 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 5047 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 5048 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 5049 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 5050 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 5051 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 5052 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 5053 udelay(1); 5054 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 5055 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 5056 5057 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 5058 5059 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 5060 5061 rtl8125_config_eee_mac(tp); 5062 5063 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 5064 udelay(10); 5065 } 5066 5067 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 5068 { 5069 static const struct ephy_info e_info_8125_1[] = { 5070 { 0x01, 0xffff, 0xa812 }, 5071 { 0x09, 0xffff, 0x520c }, 5072 { 0x04, 0xffff, 0xd000 }, 5073 { 0x0d, 0xffff, 0xf702 }, 5074 { 0x0a, 0xffff, 0x8653 }, 5075 { 0x06, 0xffff, 0x001e }, 5076 { 0x08, 0xffff, 0x3595 }, 5077 { 0x20, 0xffff, 0x9455 }, 5078 { 0x21, 0xffff, 0x99ff }, 5079 { 0x02, 0xffff, 0x6046 }, 5080 { 0x29, 0xffff, 0xfe00 }, 5081 { 0x23, 0xffff, 0xab62 }, 5082 5083 { 0x41, 0xffff, 0xa80c }, 5084 { 0x49, 0xffff, 0x520c }, 5085 { 0x44, 0xffff, 0xd000 }, 5086 { 0x4d, 0xffff, 0xf702 }, 5087 { 0x4a, 0xffff, 0x8653 }, 5088 { 0x46, 0xffff, 0x001e }, 5089 { 0x48, 0xffff, 0x3595 }, 5090 { 0x60, 0xffff, 0x9455 }, 5091 { 0x61, 0xffff, 0x99ff }, 5092 { 0x42, 0xffff, 0x6046 }, 5093 { 0x69, 0xffff, 0xfe00 }, 5094 { 0x63, 0xffff, 0xab62 }, 5095 }; 5096 5097 rtl_set_def_aspm_entry_latency(tp); 5098 5099 /* disable aspm and clock request before access ephy */ 5100 rtl_hw_aspm_clkreq_enable(tp, false); 5101 rtl_ephy_init(tp, e_info_8125_1); 5102 5103 rtl_hw_start_8125_common(tp); 5104 } 5105 5106 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 5107 { 5108 static const struct ephy_info e_info_8125_2[] = { 5109 { 0x04, 0xffff, 0xd000 }, 5110 { 0x0a, 0xffff, 0x8653 }, 5111 { 0x23, 0xffff, 0xab66 }, 5112 { 0x20, 0xffff, 0x9455 }, 5113 { 0x21, 0xffff, 0x99ff }, 5114 { 0x29, 0xffff, 0xfe04 }, 5115 5116 { 0x44, 0xffff, 0xd000 }, 5117 { 0x4a, 0xffff, 0x8653 }, 5118 { 0x63, 0xffff, 0xab66 }, 5119 { 0x60, 0xffff, 0x9455 }, 5120 { 0x61, 0xffff, 0x99ff }, 5121 { 0x69, 0xffff, 0xfe04 }, 5122 }; 5123 5124 rtl_set_def_aspm_entry_latency(tp); 5125 5126 /* disable aspm and clock request before access ephy */ 5127 rtl_hw_aspm_clkreq_enable(tp, false); 5128 rtl_ephy_init(tp, e_info_8125_2); 5129 5130 rtl_hw_start_8125_common(tp); 5131 } 5132 5133 static void rtl_hw_config(struct rtl8169_private *tp) 5134 { 5135 static const rtl_generic_fct hw_configs[] = { 5136 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 5137 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 5138 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 5139 [RTL_GIGA_MAC_VER_10] = NULL, 5140 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 5141 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 5142 [RTL_GIGA_MAC_VER_13] = NULL, 5143 [RTL_GIGA_MAC_VER_14] = NULL, 5144 [RTL_GIGA_MAC_VER_15] = NULL, 5145 [RTL_GIGA_MAC_VER_16] = NULL, 5146 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 5147 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 5148 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 5149 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 5150 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 5151 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 5152 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 5153 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 5154 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 5155 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 5156 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 5157 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 5158 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 5159 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 5160 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 5161 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 5162 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 5163 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 5164 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 5165 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 5166 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 5167 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 5168 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 5169 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 5170 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 5171 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 5172 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 5173 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 5174 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 5175 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 5176 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 5177 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 5178 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 5179 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 5180 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 5181 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 5182 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 5183 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 5184 }; 5185 5186 if (hw_configs[tp->mac_version]) 5187 hw_configs[tp->mac_version](tp); 5188 } 5189 5190 static void rtl_hw_start_8125(struct rtl8169_private *tp) 5191 { 5192 int i; 5193 5194 /* disable interrupt coalescing */ 5195 for (i = 0xa00; i < 0xb00; i += 4) 5196 RTL_W32(tp, i, 0); 5197 5198 rtl_hw_config(tp); 5199 } 5200 5201 static void rtl_hw_start_8168(struct rtl8169_private *tp) 5202 { 5203 if (rtl_is_8168evl_up(tp)) 5204 RTL_W8(tp, MaxTxPacketSize, EarlySize); 5205 else 5206 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5207 5208 rtl_hw_config(tp); 5209 5210 /* disable interrupt coalescing */ 5211 RTL_W16(tp, IntrMitigate, 0x0000); 5212 } 5213 5214 static void rtl_hw_start_8169(struct rtl8169_private *tp) 5215 { 5216 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5217 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 5218 5219 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 5220 5221 tp->cp_cmd |= PCIMulRW; 5222 5223 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 5224 tp->mac_version == RTL_GIGA_MAC_VER_03) { 5225 netif_dbg(tp, drv, tp->dev, 5226 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n"); 5227 tp->cp_cmd |= (1 << 14); 5228 } 5229 5230 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5231 5232 rtl8169_set_magic_reg(tp, tp->mac_version); 5233 5234 RTL_W32(tp, RxMissed, 0); 5235 5236 /* disable interrupt coalescing */ 5237 RTL_W16(tp, IntrMitigate, 0x0000); 5238 } 5239 5240 static void rtl_hw_start(struct rtl8169_private *tp) 5241 { 5242 rtl_unlock_config_regs(tp); 5243 5244 tp->cp_cmd &= CPCMD_MASK; 5245 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5246 5247 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5248 rtl_hw_start_8169(tp); 5249 else if (rtl_is_8125(tp)) 5250 rtl_hw_start_8125(tp); 5251 else 5252 rtl_hw_start_8168(tp); 5253 5254 rtl_set_rx_max_size(tp); 5255 rtl_set_rx_tx_desc_registers(tp); 5256 rtl_lock_config_regs(tp); 5257 5258 rtl_jumbo_config(tp, tp->dev->mtu); 5259 5260 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 5261 RTL_R16(tp, CPlusCmd); 5262 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 5263 rtl_init_rxcfg(tp); 5264 rtl_set_tx_config_registers(tp); 5265 rtl_set_rx_mode(tp->dev); 5266 rtl_irq_enable(tp); 5267 } 5268 5269 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 5270 { 5271 struct rtl8169_private *tp = netdev_priv(dev); 5272 5273 rtl_jumbo_config(tp, new_mtu); 5274 5275 dev->mtu = new_mtu; 5276 netdev_update_features(dev); 5277 5278 return 0; 5279 } 5280 5281 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) 5282 { 5283 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); 5284 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); 5285 } 5286 5287 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 5288 { 5289 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 5290 5291 /* Force memory writes to complete before releasing descriptor */ 5292 dma_wmb(); 5293 5294 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 5295 } 5296 5297 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 5298 struct RxDesc *desc) 5299 { 5300 struct device *d = tp_to_dev(tp); 5301 int node = dev_to_node(d); 5302 dma_addr_t mapping; 5303 struct page *data; 5304 5305 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 5306 if (!data) 5307 return NULL; 5308 5309 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5310 if (unlikely(dma_mapping_error(d, mapping))) { 5311 if (net_ratelimit()) 5312 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); 5313 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 5314 return NULL; 5315 } 5316 5317 desc->addr = cpu_to_le64(mapping); 5318 rtl8169_mark_to_asic(desc); 5319 5320 return data; 5321 } 5322 5323 static void rtl8169_rx_clear(struct rtl8169_private *tp) 5324 { 5325 unsigned int i; 5326 5327 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 5328 dma_unmap_page(tp_to_dev(tp), 5329 le64_to_cpu(tp->RxDescArray[i].addr), 5330 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5331 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 5332 tp->Rx_databuff[i] = NULL; 5333 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5334 } 5335 } 5336 5337 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) 5338 { 5339 desc->opts1 |= cpu_to_le32(RingEnd); 5340 } 5341 5342 static int rtl8169_rx_fill(struct rtl8169_private *tp) 5343 { 5344 unsigned int i; 5345 5346 for (i = 0; i < NUM_RX_DESC; i++) { 5347 struct page *data; 5348 5349 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 5350 if (!data) { 5351 rtl8169_rx_clear(tp); 5352 return -ENOMEM; 5353 } 5354 tp->Rx_databuff[i] = data; 5355 } 5356 5357 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); 5358 5359 return 0; 5360 } 5361 5362 static int rtl8169_init_ring(struct rtl8169_private *tp) 5363 { 5364 rtl8169_init_ring_indexes(tp); 5365 5366 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 5367 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 5368 5369 return rtl8169_rx_fill(tp); 5370 } 5371 5372 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, 5373 struct TxDesc *desc) 5374 { 5375 unsigned int len = tx_skb->len; 5376 5377 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); 5378 5379 desc->opts1 = 0x00; 5380 desc->opts2 = 0x00; 5381 desc->addr = 0x00; 5382 tx_skb->len = 0; 5383 } 5384 5385 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 5386 unsigned int n) 5387 { 5388 unsigned int i; 5389 5390 for (i = 0; i < n; i++) { 5391 unsigned int entry = (start + i) % NUM_TX_DESC; 5392 struct ring_info *tx_skb = tp->tx_skb + entry; 5393 unsigned int len = tx_skb->len; 5394 5395 if (len) { 5396 struct sk_buff *skb = tx_skb->skb; 5397 5398 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5399 tp->TxDescArray + entry); 5400 if (skb) { 5401 dev_consume_skb_any(skb); 5402 tx_skb->skb = NULL; 5403 } 5404 } 5405 } 5406 } 5407 5408 static void rtl8169_tx_clear(struct rtl8169_private *tp) 5409 { 5410 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 5411 tp->cur_tx = tp->dirty_tx = 0; 5412 netdev_reset_queue(tp->dev); 5413 } 5414 5415 static void rtl_reset_work(struct rtl8169_private *tp) 5416 { 5417 struct net_device *dev = tp->dev; 5418 int i; 5419 5420 napi_disable(&tp->napi); 5421 netif_stop_queue(dev); 5422 synchronize_rcu(); 5423 5424 rtl8169_hw_reset(tp); 5425 5426 for (i = 0; i < NUM_RX_DESC; i++) 5427 rtl8169_mark_to_asic(tp->RxDescArray + i); 5428 5429 rtl8169_tx_clear(tp); 5430 rtl8169_init_ring_indexes(tp); 5431 5432 napi_enable(&tp->napi); 5433 rtl_hw_start(tp); 5434 netif_wake_queue(dev); 5435 } 5436 5437 static void rtl8169_tx_timeout(struct net_device *dev) 5438 { 5439 struct rtl8169_private *tp = netdev_priv(dev); 5440 5441 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5442 } 5443 5444 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry) 5445 { 5446 u32 status = opts0 | len; 5447 5448 if (entry == NUM_TX_DESC - 1) 5449 status |= RingEnd; 5450 5451 return cpu_to_le32(status); 5452 } 5453 5454 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 5455 u32 *opts) 5456 { 5457 struct skb_shared_info *info = skb_shinfo(skb); 5458 unsigned int cur_frag, entry; 5459 struct TxDesc *uninitialized_var(txd); 5460 struct device *d = tp_to_dev(tp); 5461 5462 entry = tp->cur_tx; 5463 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 5464 const skb_frag_t *frag = info->frags + cur_frag; 5465 dma_addr_t mapping; 5466 u32 len; 5467 void *addr; 5468 5469 entry = (entry + 1) % NUM_TX_DESC; 5470 5471 txd = tp->TxDescArray + entry; 5472 len = skb_frag_size(frag); 5473 addr = skb_frag_address(frag); 5474 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 5475 if (unlikely(dma_mapping_error(d, mapping))) { 5476 if (net_ratelimit()) 5477 netif_err(tp, drv, tp->dev, 5478 "Failed to map TX fragments DMA!\n"); 5479 goto err_out; 5480 } 5481 5482 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5483 txd->opts2 = cpu_to_le32(opts[1]); 5484 txd->addr = cpu_to_le64(mapping); 5485 5486 tp->tx_skb[entry].len = len; 5487 } 5488 5489 if (cur_frag) { 5490 tp->tx_skb[entry].skb = skb; 5491 txd->opts1 |= cpu_to_le32(LastFrag); 5492 } 5493 5494 return cur_frag; 5495 5496 err_out: 5497 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 5498 return -EIO; 5499 } 5500 5501 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 5502 { 5503 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 5504 } 5505 5506 /* msdn_giant_send_check() 5507 * According to the document of microsoft, the TCP Pseudo Header excludes the 5508 * packet length for IPv6 TCP large packets. 5509 */ 5510 static int msdn_giant_send_check(struct sk_buff *skb) 5511 { 5512 const struct ipv6hdr *ipv6h; 5513 struct tcphdr *th; 5514 int ret; 5515 5516 ret = skb_cow_head(skb, 0); 5517 if (ret) 5518 return ret; 5519 5520 ipv6h = ipv6_hdr(skb); 5521 th = tcp_hdr(skb); 5522 5523 th->check = 0; 5524 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 5525 5526 return ret; 5527 } 5528 5529 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 5530 { 5531 u32 mss = skb_shinfo(skb)->gso_size; 5532 5533 if (mss) { 5534 opts[0] |= TD_LSO; 5535 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; 5536 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5537 const struct iphdr *ip = ip_hdr(skb); 5538 5539 if (ip->protocol == IPPROTO_TCP) 5540 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 5541 else if (ip->protocol == IPPROTO_UDP) 5542 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 5543 else 5544 WARN_ON_ONCE(1); 5545 } 5546 } 5547 5548 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 5549 struct sk_buff *skb, u32 *opts) 5550 { 5551 u32 transport_offset = (u32)skb_transport_offset(skb); 5552 u32 mss = skb_shinfo(skb)->gso_size; 5553 5554 if (mss) { 5555 switch (vlan_get_protocol(skb)) { 5556 case htons(ETH_P_IP): 5557 opts[0] |= TD1_GTSENV4; 5558 break; 5559 5560 case htons(ETH_P_IPV6): 5561 if (msdn_giant_send_check(skb)) 5562 return false; 5563 5564 opts[0] |= TD1_GTSENV6; 5565 break; 5566 5567 default: 5568 WARN_ON_ONCE(1); 5569 break; 5570 } 5571 5572 opts[0] |= transport_offset << GTTCPHO_SHIFT; 5573 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; 5574 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5575 u8 ip_protocol; 5576 5577 switch (vlan_get_protocol(skb)) { 5578 case htons(ETH_P_IP): 5579 opts[1] |= TD1_IPv4_CS; 5580 ip_protocol = ip_hdr(skb)->protocol; 5581 break; 5582 5583 case htons(ETH_P_IPV6): 5584 opts[1] |= TD1_IPv6_CS; 5585 ip_protocol = ipv6_hdr(skb)->nexthdr; 5586 break; 5587 5588 default: 5589 ip_protocol = IPPROTO_RAW; 5590 break; 5591 } 5592 5593 if (ip_protocol == IPPROTO_TCP) 5594 opts[1] |= TD1_TCP_CS; 5595 else if (ip_protocol == IPPROTO_UDP) 5596 opts[1] |= TD1_UDP_CS; 5597 else 5598 WARN_ON_ONCE(1); 5599 5600 opts[1] |= transport_offset << TCPHO_SHIFT; 5601 } else { 5602 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 5603 return !eth_skb_pad(skb); 5604 } 5605 5606 return true; 5607 } 5608 5609 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 5610 unsigned int nr_frags) 5611 { 5612 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 5613 5614 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 5615 return slots_avail > nr_frags; 5616 } 5617 5618 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 5619 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 5620 { 5621 switch (tp->mac_version) { 5622 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5623 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 5624 return false; 5625 default: 5626 return true; 5627 } 5628 } 5629 5630 static void rtl8169_doorbell(struct rtl8169_private *tp) 5631 { 5632 if (rtl_is_8125(tp)) 5633 RTL_W16(tp, TxPoll_8125, BIT(0)); 5634 else 5635 RTL_W8(tp, TxPoll, NPQ); 5636 } 5637 5638 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 5639 struct net_device *dev) 5640 { 5641 struct rtl8169_private *tp = netdev_priv(dev); 5642 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 5643 struct TxDesc *txd = tp->TxDescArray + entry; 5644 struct device *d = tp_to_dev(tp); 5645 dma_addr_t mapping; 5646 u32 opts[2], len; 5647 bool stop_queue; 5648 bool door_bell; 5649 int frags; 5650 5651 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) { 5652 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 5653 goto err_stop_0; 5654 } 5655 5656 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) 5657 goto err_stop_0; 5658 5659 opts[1] = rtl8169_tx_vlan_tag(skb); 5660 opts[0] = DescOwn; 5661 5662 if (rtl_chip_supports_csum_v2(tp)) { 5663 if (!rtl8169_tso_csum_v2(tp, skb, opts)) 5664 goto err_dma_0; 5665 } else { 5666 rtl8169_tso_csum_v1(skb, opts); 5667 } 5668 5669 len = skb_headlen(skb); 5670 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); 5671 if (unlikely(dma_mapping_error(d, mapping))) { 5672 if (net_ratelimit()) 5673 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); 5674 goto err_dma_0; 5675 } 5676 5677 tp->tx_skb[entry].len = len; 5678 txd->addr = cpu_to_le64(mapping); 5679 5680 frags = rtl8169_xmit_frags(tp, skb, opts); 5681 if (frags < 0) 5682 goto err_dma_1; 5683 else if (frags) 5684 opts[0] |= FirstFrag; 5685 else { 5686 opts[0] |= FirstFrag | LastFrag; 5687 tp->tx_skb[entry].skb = skb; 5688 } 5689 5690 txd->opts2 = cpu_to_le32(opts[1]); 5691 5692 skb_tx_timestamp(skb); 5693 5694 /* Force memory writes to complete before releasing descriptor */ 5695 dma_wmb(); 5696 5697 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 5698 5699 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5700 5701 /* Force all memory writes to complete before notifying device */ 5702 wmb(); 5703 5704 tp->cur_tx += frags + 1; 5705 5706 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 5707 if (unlikely(stop_queue)) { 5708 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 5709 * not miss a ring update when it notices a stopped queue. 5710 */ 5711 smp_wmb(); 5712 netif_stop_queue(dev); 5713 door_bell = true; 5714 } 5715 5716 if (door_bell) 5717 rtl8169_doorbell(tp); 5718 5719 if (unlikely(stop_queue)) { 5720 /* Sync with rtl_tx: 5721 * - publish queue status and cur_tx ring index (write barrier) 5722 * - refresh dirty_tx ring index (read barrier). 5723 * May the current thread have a pessimistic view of the ring 5724 * status and forget to wake up queue, a racing rtl_tx thread 5725 * can't. 5726 */ 5727 smp_mb(); 5728 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 5729 netif_start_queue(dev); 5730 } 5731 5732 return NETDEV_TX_OK; 5733 5734 err_dma_1: 5735 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); 5736 err_dma_0: 5737 dev_kfree_skb_any(skb); 5738 dev->stats.tx_dropped++; 5739 return NETDEV_TX_OK; 5740 5741 err_stop_0: 5742 netif_stop_queue(dev); 5743 dev->stats.tx_dropped++; 5744 return NETDEV_TX_BUSY; 5745 } 5746 5747 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 5748 struct net_device *dev, 5749 netdev_features_t features) 5750 { 5751 int transport_offset = skb_transport_offset(skb); 5752 struct rtl8169_private *tp = netdev_priv(dev); 5753 5754 if (skb_is_gso(skb)) { 5755 if (transport_offset > GTTCPHO_MAX && 5756 rtl_chip_supports_csum_v2(tp)) 5757 features &= ~NETIF_F_ALL_TSO; 5758 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5759 if (skb->len < ETH_ZLEN) { 5760 switch (tp->mac_version) { 5761 case RTL_GIGA_MAC_VER_11: 5762 case RTL_GIGA_MAC_VER_12: 5763 case RTL_GIGA_MAC_VER_17: 5764 case RTL_GIGA_MAC_VER_34: 5765 features &= ~NETIF_F_CSUM_MASK; 5766 break; 5767 default: 5768 break; 5769 } 5770 } 5771 5772 if (transport_offset > TCPHO_MAX && 5773 rtl_chip_supports_csum_v2(tp)) 5774 features &= ~NETIF_F_CSUM_MASK; 5775 } 5776 5777 return vlan_features_check(skb, features); 5778 } 5779 5780 static void rtl8169_pcierr_interrupt(struct net_device *dev) 5781 { 5782 struct rtl8169_private *tp = netdev_priv(dev); 5783 struct pci_dev *pdev = tp->pci_dev; 5784 u16 pci_status, pci_cmd; 5785 5786 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 5787 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 5788 5789 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", 5790 pci_cmd, pci_status); 5791 5792 /* 5793 * The recovery sequence below admits a very elaborated explanation: 5794 * - it seems to work; 5795 * - I did not see what else could be done; 5796 * - it makes iop3xx happy. 5797 * 5798 * Feel free to adjust to your needs. 5799 */ 5800 if (pdev->broken_parity_status) 5801 pci_cmd &= ~PCI_COMMAND_PARITY; 5802 else 5803 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 5804 5805 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 5806 5807 pci_write_config_word(pdev, PCI_STATUS, 5808 pci_status & (PCI_STATUS_DETECTED_PARITY | 5809 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | 5810 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); 5811 5812 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5813 } 5814 5815 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 5816 int budget) 5817 { 5818 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 5819 5820 dirty_tx = tp->dirty_tx; 5821 smp_rmb(); 5822 tx_left = tp->cur_tx - dirty_tx; 5823 5824 while (tx_left > 0) { 5825 unsigned int entry = dirty_tx % NUM_TX_DESC; 5826 struct ring_info *tx_skb = tp->tx_skb + entry; 5827 u32 status; 5828 5829 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 5830 if (status & DescOwn) 5831 break; 5832 5833 /* This barrier is needed to keep us from reading 5834 * any other fields out of the Tx descriptor until 5835 * we know the status of DescOwn 5836 */ 5837 dma_rmb(); 5838 5839 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5840 tp->TxDescArray + entry); 5841 if (tx_skb->skb) { 5842 pkts_compl++; 5843 bytes_compl += tx_skb->skb->len; 5844 napi_consume_skb(tx_skb->skb, budget); 5845 tx_skb->skb = NULL; 5846 } 5847 dirty_tx++; 5848 tx_left--; 5849 } 5850 5851 if (tp->dirty_tx != dirty_tx) { 5852 netdev_completed_queue(dev, pkts_compl, bytes_compl); 5853 5854 u64_stats_update_begin(&tp->tx_stats.syncp); 5855 tp->tx_stats.packets += pkts_compl; 5856 tp->tx_stats.bytes += bytes_compl; 5857 u64_stats_update_end(&tp->tx_stats.syncp); 5858 5859 tp->dirty_tx = dirty_tx; 5860 /* Sync with rtl8169_start_xmit: 5861 * - publish dirty_tx ring index (write barrier) 5862 * - refresh cur_tx ring index and queue status (read barrier) 5863 * May the current thread miss the stopped queue condition, 5864 * a racing xmit thread can only have a right view of the 5865 * ring status. 5866 */ 5867 smp_mb(); 5868 if (netif_queue_stopped(dev) && 5869 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 5870 netif_wake_queue(dev); 5871 } 5872 /* 5873 * 8168 hack: TxPoll requests are lost when the Tx packets are 5874 * too close. Let's kick an extra TxPoll request when a burst 5875 * of start_xmit activity is detected (if it is not detected, 5876 * it is slow enough). -- FR 5877 */ 5878 if (tp->cur_tx != dirty_tx) 5879 rtl8169_doorbell(tp); 5880 } 5881 } 5882 5883 static inline int rtl8169_fragmented_frame(u32 status) 5884 { 5885 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 5886 } 5887 5888 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 5889 { 5890 u32 status = opts1 & RxProtoMask; 5891 5892 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 5893 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 5894 skb->ip_summed = CHECKSUM_UNNECESSARY; 5895 else 5896 skb_checksum_none_assert(skb); 5897 } 5898 5899 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 5900 { 5901 unsigned int cur_rx, rx_left; 5902 unsigned int count; 5903 5904 cur_rx = tp->cur_rx; 5905 5906 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 5907 unsigned int entry = cur_rx % NUM_RX_DESC; 5908 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 5909 struct RxDesc *desc = tp->RxDescArray + entry; 5910 u32 status; 5911 5912 status = le32_to_cpu(desc->opts1); 5913 if (status & DescOwn) 5914 break; 5915 5916 /* This barrier is needed to keep us from reading 5917 * any other fields out of the Rx descriptor until 5918 * we know the status of DescOwn 5919 */ 5920 dma_rmb(); 5921 5922 if (unlikely(status & RxRES)) { 5923 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", 5924 status); 5925 dev->stats.rx_errors++; 5926 if (status & (RxRWT | RxRUNT)) 5927 dev->stats.rx_length_errors++; 5928 if (status & RxCRC) 5929 dev->stats.rx_crc_errors++; 5930 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 5931 dev->features & NETIF_F_RXALL) { 5932 goto process_pkt; 5933 } 5934 } else { 5935 unsigned int pkt_size; 5936 struct sk_buff *skb; 5937 5938 process_pkt: 5939 pkt_size = status & GENMASK(13, 0); 5940 if (likely(!(dev->features & NETIF_F_RXFCS))) 5941 pkt_size -= ETH_FCS_LEN; 5942 /* 5943 * The driver does not support incoming fragmented 5944 * frames. They are seen as a symptom of over-mtu 5945 * sized frames. 5946 */ 5947 if (unlikely(rtl8169_fragmented_frame(status))) { 5948 dev->stats.rx_dropped++; 5949 dev->stats.rx_length_errors++; 5950 goto release_descriptor; 5951 } 5952 5953 skb = napi_alloc_skb(&tp->napi, pkt_size); 5954 if (unlikely(!skb)) { 5955 dev->stats.rx_dropped++; 5956 goto release_descriptor; 5957 } 5958 5959 dma_sync_single_for_cpu(tp_to_dev(tp), 5960 le64_to_cpu(desc->addr), 5961 pkt_size, DMA_FROM_DEVICE); 5962 prefetch(rx_buf); 5963 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 5964 skb->tail += pkt_size; 5965 skb->len = pkt_size; 5966 5967 dma_sync_single_for_device(tp_to_dev(tp), 5968 le64_to_cpu(desc->addr), 5969 pkt_size, DMA_FROM_DEVICE); 5970 5971 rtl8169_rx_csum(skb, status); 5972 skb->protocol = eth_type_trans(skb, dev); 5973 5974 rtl8169_rx_vlan_tag(desc, skb); 5975 5976 if (skb->pkt_type == PACKET_MULTICAST) 5977 dev->stats.multicast++; 5978 5979 napi_gro_receive(&tp->napi, skb); 5980 5981 u64_stats_update_begin(&tp->rx_stats.syncp); 5982 tp->rx_stats.packets++; 5983 tp->rx_stats.bytes += pkt_size; 5984 u64_stats_update_end(&tp->rx_stats.syncp); 5985 } 5986 release_descriptor: 5987 desc->opts2 = 0; 5988 rtl8169_mark_to_asic(desc); 5989 } 5990 5991 count = cur_rx - tp->cur_rx; 5992 tp->cur_rx = cur_rx; 5993 5994 return count; 5995 } 5996 5997 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 5998 { 5999 struct rtl8169_private *tp = dev_instance; 6000 u32 status = rtl_get_events(tp); 6001 6002 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 6003 !(status & tp->irq_mask)) 6004 return IRQ_NONE; 6005 6006 if (unlikely(status & SYSErr)) { 6007 rtl8169_pcierr_interrupt(tp->dev); 6008 goto out; 6009 } 6010 6011 if (status & LinkChg) 6012 phy_mac_interrupt(tp->phydev); 6013 6014 if (unlikely(status & RxFIFOOver && 6015 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 6016 netif_stop_queue(tp->dev); 6017 /* XXX - Hack alert. See rtl_task(). */ 6018 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); 6019 } 6020 6021 rtl_irq_disable(tp); 6022 napi_schedule_irqoff(&tp->napi); 6023 out: 6024 rtl_ack_events(tp, status); 6025 6026 return IRQ_HANDLED; 6027 } 6028 6029 static void rtl_task(struct work_struct *work) 6030 { 6031 static const struct { 6032 int bitnr; 6033 void (*action)(struct rtl8169_private *); 6034 } rtl_work[] = { 6035 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, 6036 }; 6037 struct rtl8169_private *tp = 6038 container_of(work, struct rtl8169_private, wk.work); 6039 struct net_device *dev = tp->dev; 6040 int i; 6041 6042 rtl_lock_work(tp); 6043 6044 if (!netif_running(dev) || 6045 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 6046 goto out_unlock; 6047 6048 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { 6049 bool pending; 6050 6051 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); 6052 if (pending) 6053 rtl_work[i].action(tp); 6054 } 6055 6056 out_unlock: 6057 rtl_unlock_work(tp); 6058 } 6059 6060 static int rtl8169_poll(struct napi_struct *napi, int budget) 6061 { 6062 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 6063 struct net_device *dev = tp->dev; 6064 int work_done; 6065 6066 work_done = rtl_rx(dev, tp, (u32) budget); 6067 6068 rtl_tx(dev, tp, budget); 6069 6070 if (work_done < budget) { 6071 napi_complete_done(napi, work_done); 6072 rtl_irq_enable(tp); 6073 } 6074 6075 return work_done; 6076 } 6077 6078 static void rtl8169_rx_missed(struct net_device *dev) 6079 { 6080 struct rtl8169_private *tp = netdev_priv(dev); 6081 6082 if (tp->mac_version > RTL_GIGA_MAC_VER_06) 6083 return; 6084 6085 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff; 6086 RTL_W32(tp, RxMissed, 0); 6087 } 6088 6089 static void r8169_phylink_handler(struct net_device *ndev) 6090 { 6091 struct rtl8169_private *tp = netdev_priv(ndev); 6092 6093 if (netif_carrier_ok(ndev)) { 6094 rtl_link_chg_patch(tp); 6095 pm_request_resume(&tp->pci_dev->dev); 6096 } else { 6097 pm_runtime_idle(&tp->pci_dev->dev); 6098 } 6099 6100 if (net_ratelimit()) 6101 phy_print_status(tp->phydev); 6102 } 6103 6104 static int r8169_phy_connect(struct rtl8169_private *tp) 6105 { 6106 struct phy_device *phydev = tp->phydev; 6107 phy_interface_t phy_mode; 6108 int ret; 6109 6110 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 6111 PHY_INTERFACE_MODE_MII; 6112 6113 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 6114 phy_mode); 6115 if (ret) 6116 return ret; 6117 6118 if (!tp->supports_gmii) 6119 phy_set_max_speed(phydev, SPEED_100); 6120 6121 phy_support_asym_pause(phydev); 6122 6123 phy_attached_info(phydev); 6124 6125 return 0; 6126 } 6127 6128 static void rtl8169_down(struct net_device *dev) 6129 { 6130 struct rtl8169_private *tp = netdev_priv(dev); 6131 6132 phy_stop(tp->phydev); 6133 6134 napi_disable(&tp->napi); 6135 netif_stop_queue(dev); 6136 6137 rtl8169_hw_reset(tp); 6138 /* 6139 * At this point device interrupts can not be enabled in any function, 6140 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) 6141 * and napi is disabled (rtl8169_poll). 6142 */ 6143 rtl8169_rx_missed(dev); 6144 6145 /* Give a racing hard_start_xmit a few cycles to complete. */ 6146 synchronize_rcu(); 6147 6148 rtl8169_tx_clear(tp); 6149 6150 rtl8169_rx_clear(tp); 6151 6152 rtl_pll_power_down(tp); 6153 } 6154 6155 static int rtl8169_close(struct net_device *dev) 6156 { 6157 struct rtl8169_private *tp = netdev_priv(dev); 6158 struct pci_dev *pdev = tp->pci_dev; 6159 6160 pm_runtime_get_sync(&pdev->dev); 6161 6162 /* Update counters before going down */ 6163 rtl8169_update_counters(tp); 6164 6165 rtl_lock_work(tp); 6166 /* Clear all task flags */ 6167 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6168 6169 rtl8169_down(dev); 6170 rtl_unlock_work(tp); 6171 6172 cancel_work_sync(&tp->wk.work); 6173 6174 phy_disconnect(tp->phydev); 6175 6176 pci_free_irq(pdev, 0, tp); 6177 6178 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6179 tp->RxPhyAddr); 6180 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6181 tp->TxPhyAddr); 6182 tp->TxDescArray = NULL; 6183 tp->RxDescArray = NULL; 6184 6185 pm_runtime_put_sync(&pdev->dev); 6186 6187 return 0; 6188 } 6189 6190 #ifdef CONFIG_NET_POLL_CONTROLLER 6191 static void rtl8169_netpoll(struct net_device *dev) 6192 { 6193 struct rtl8169_private *tp = netdev_priv(dev); 6194 6195 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 6196 } 6197 #endif 6198 6199 static int rtl_open(struct net_device *dev) 6200 { 6201 struct rtl8169_private *tp = netdev_priv(dev); 6202 struct pci_dev *pdev = tp->pci_dev; 6203 int retval = -ENOMEM; 6204 6205 pm_runtime_get_sync(&pdev->dev); 6206 6207 /* 6208 * Rx and Tx descriptors needs 256 bytes alignment. 6209 * dma_alloc_coherent provides more. 6210 */ 6211 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 6212 &tp->TxPhyAddr, GFP_KERNEL); 6213 if (!tp->TxDescArray) 6214 goto err_pm_runtime_put; 6215 6216 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 6217 &tp->RxPhyAddr, GFP_KERNEL); 6218 if (!tp->RxDescArray) 6219 goto err_free_tx_0; 6220 6221 retval = rtl8169_init_ring(tp); 6222 if (retval < 0) 6223 goto err_free_rx_1; 6224 6225 rtl_request_firmware(tp); 6226 6227 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 6228 dev->name); 6229 if (retval < 0) 6230 goto err_release_fw_2; 6231 6232 retval = r8169_phy_connect(tp); 6233 if (retval) 6234 goto err_free_irq; 6235 6236 rtl_lock_work(tp); 6237 6238 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6239 6240 napi_enable(&tp->napi); 6241 6242 rtl8169_init_phy(dev, tp); 6243 6244 rtl_pll_power_up(tp); 6245 6246 rtl_hw_start(tp); 6247 6248 if (!rtl8169_init_counter_offsets(tp)) 6249 netif_warn(tp, hw, dev, "counter reset/update failed\n"); 6250 6251 phy_start(tp->phydev); 6252 netif_start_queue(dev); 6253 6254 rtl_unlock_work(tp); 6255 6256 pm_runtime_put_sync(&pdev->dev); 6257 out: 6258 return retval; 6259 6260 err_free_irq: 6261 pci_free_irq(pdev, 0, tp); 6262 err_release_fw_2: 6263 rtl_release_firmware(tp); 6264 rtl8169_rx_clear(tp); 6265 err_free_rx_1: 6266 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6267 tp->RxPhyAddr); 6268 tp->RxDescArray = NULL; 6269 err_free_tx_0: 6270 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6271 tp->TxPhyAddr); 6272 tp->TxDescArray = NULL; 6273 err_pm_runtime_put: 6274 pm_runtime_put_noidle(&pdev->dev); 6275 goto out; 6276 } 6277 6278 static void 6279 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6280 { 6281 struct rtl8169_private *tp = netdev_priv(dev); 6282 struct pci_dev *pdev = tp->pci_dev; 6283 struct rtl8169_counters *counters = tp->counters; 6284 unsigned int start; 6285 6286 pm_runtime_get_noresume(&pdev->dev); 6287 6288 if (netif_running(dev) && pm_runtime_active(&pdev->dev)) 6289 rtl8169_rx_missed(dev); 6290 6291 do { 6292 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 6293 stats->rx_packets = tp->rx_stats.packets; 6294 stats->rx_bytes = tp->rx_stats.bytes; 6295 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 6296 6297 do { 6298 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 6299 stats->tx_packets = tp->tx_stats.packets; 6300 stats->tx_bytes = tp->tx_stats.bytes; 6301 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 6302 6303 stats->rx_dropped = dev->stats.rx_dropped; 6304 stats->tx_dropped = dev->stats.tx_dropped; 6305 stats->rx_length_errors = dev->stats.rx_length_errors; 6306 stats->rx_errors = dev->stats.rx_errors; 6307 stats->rx_crc_errors = dev->stats.rx_crc_errors; 6308 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 6309 stats->rx_missed_errors = dev->stats.rx_missed_errors; 6310 stats->multicast = dev->stats.multicast; 6311 6312 /* 6313 * Fetch additional counter values missing in stats collected by driver 6314 * from tally counters. 6315 */ 6316 if (pm_runtime_active(&pdev->dev)) 6317 rtl8169_update_counters(tp); 6318 6319 /* 6320 * Subtract values fetched during initalization. 6321 * See rtl8169_init_counter_offsets for a description why we do that. 6322 */ 6323 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 6324 le64_to_cpu(tp->tc_offset.tx_errors); 6325 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 6326 le32_to_cpu(tp->tc_offset.tx_multi_collision); 6327 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 6328 le16_to_cpu(tp->tc_offset.tx_aborted); 6329 6330 pm_runtime_put_noidle(&pdev->dev); 6331 } 6332 6333 static void rtl8169_net_suspend(struct net_device *dev) 6334 { 6335 struct rtl8169_private *tp = netdev_priv(dev); 6336 6337 if (!netif_running(dev)) 6338 return; 6339 6340 phy_stop(tp->phydev); 6341 netif_device_detach(dev); 6342 6343 rtl_lock_work(tp); 6344 napi_disable(&tp->napi); 6345 /* Clear all task flags */ 6346 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6347 6348 rtl_unlock_work(tp); 6349 6350 rtl_pll_power_down(tp); 6351 } 6352 6353 #ifdef CONFIG_PM 6354 6355 static int rtl8169_suspend(struct device *device) 6356 { 6357 struct net_device *dev = dev_get_drvdata(device); 6358 struct rtl8169_private *tp = netdev_priv(dev); 6359 6360 rtl8169_net_suspend(dev); 6361 clk_disable_unprepare(tp->clk); 6362 6363 return 0; 6364 } 6365 6366 static void __rtl8169_resume(struct net_device *dev) 6367 { 6368 struct rtl8169_private *tp = netdev_priv(dev); 6369 6370 netif_device_attach(dev); 6371 6372 rtl_pll_power_up(tp); 6373 rtl8169_init_phy(dev, tp); 6374 6375 phy_start(tp->phydev); 6376 6377 rtl_lock_work(tp); 6378 napi_enable(&tp->napi); 6379 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6380 rtl_reset_work(tp); 6381 rtl_unlock_work(tp); 6382 } 6383 6384 static int rtl8169_resume(struct device *device) 6385 { 6386 struct net_device *dev = dev_get_drvdata(device); 6387 struct rtl8169_private *tp = netdev_priv(dev); 6388 6389 rtl_rar_set(tp, dev->dev_addr); 6390 6391 clk_prepare_enable(tp->clk); 6392 6393 if (netif_running(dev)) 6394 __rtl8169_resume(dev); 6395 6396 return 0; 6397 } 6398 6399 static int rtl8169_runtime_suspend(struct device *device) 6400 { 6401 struct net_device *dev = dev_get_drvdata(device); 6402 struct rtl8169_private *tp = netdev_priv(dev); 6403 6404 if (!tp->TxDescArray) 6405 return 0; 6406 6407 rtl_lock_work(tp); 6408 __rtl8169_set_wol(tp, WAKE_ANY); 6409 rtl_unlock_work(tp); 6410 6411 rtl8169_net_suspend(dev); 6412 6413 /* Update counters before going runtime suspend */ 6414 rtl8169_rx_missed(dev); 6415 rtl8169_update_counters(tp); 6416 6417 return 0; 6418 } 6419 6420 static int rtl8169_runtime_resume(struct device *device) 6421 { 6422 struct net_device *dev = dev_get_drvdata(device); 6423 struct rtl8169_private *tp = netdev_priv(dev); 6424 6425 rtl_rar_set(tp, dev->dev_addr); 6426 6427 if (!tp->TxDescArray) 6428 return 0; 6429 6430 rtl_lock_work(tp); 6431 __rtl8169_set_wol(tp, tp->saved_wolopts); 6432 rtl_unlock_work(tp); 6433 6434 __rtl8169_resume(dev); 6435 6436 return 0; 6437 } 6438 6439 static int rtl8169_runtime_idle(struct device *device) 6440 { 6441 struct net_device *dev = dev_get_drvdata(device); 6442 6443 if (!netif_running(dev) || !netif_carrier_ok(dev)) 6444 pm_schedule_suspend(device, 10000); 6445 6446 return -EBUSY; 6447 } 6448 6449 static const struct dev_pm_ops rtl8169_pm_ops = { 6450 .suspend = rtl8169_suspend, 6451 .resume = rtl8169_resume, 6452 .freeze = rtl8169_suspend, 6453 .thaw = rtl8169_resume, 6454 .poweroff = rtl8169_suspend, 6455 .restore = rtl8169_resume, 6456 .runtime_suspend = rtl8169_runtime_suspend, 6457 .runtime_resume = rtl8169_runtime_resume, 6458 .runtime_idle = rtl8169_runtime_idle, 6459 }; 6460 6461 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 6462 6463 #else /* !CONFIG_PM */ 6464 6465 #define RTL8169_PM_OPS NULL 6466 6467 #endif /* !CONFIG_PM */ 6468 6469 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 6470 { 6471 /* WoL fails with 8168b when the receiver is disabled. */ 6472 switch (tp->mac_version) { 6473 case RTL_GIGA_MAC_VER_11: 6474 case RTL_GIGA_MAC_VER_12: 6475 case RTL_GIGA_MAC_VER_17: 6476 pci_clear_master(tp->pci_dev); 6477 6478 RTL_W8(tp, ChipCmd, CmdRxEnb); 6479 /* PCI commit */ 6480 RTL_R8(tp, ChipCmd); 6481 break; 6482 default: 6483 break; 6484 } 6485 } 6486 6487 static void rtl_shutdown(struct pci_dev *pdev) 6488 { 6489 struct net_device *dev = pci_get_drvdata(pdev); 6490 struct rtl8169_private *tp = netdev_priv(dev); 6491 6492 rtl8169_net_suspend(dev); 6493 6494 /* Restore original MAC address */ 6495 rtl_rar_set(tp, dev->perm_addr); 6496 6497 rtl8169_hw_reset(tp); 6498 6499 if (system_state == SYSTEM_POWER_OFF) { 6500 if (tp->saved_wolopts) { 6501 rtl_wol_suspend_quirk(tp); 6502 rtl_wol_shutdown_quirk(tp); 6503 } 6504 6505 pci_wake_from_d3(pdev, true); 6506 pci_set_power_state(pdev, PCI_D3hot); 6507 } 6508 } 6509 6510 static void rtl_remove_one(struct pci_dev *pdev) 6511 { 6512 struct net_device *dev = pci_get_drvdata(pdev); 6513 struct rtl8169_private *tp = netdev_priv(dev); 6514 6515 if (r8168_check_dash(tp)) 6516 rtl8168_driver_stop(tp); 6517 6518 netif_napi_del(&tp->napi); 6519 6520 unregister_netdev(dev); 6521 mdiobus_unregister(tp->phydev->mdio.bus); 6522 6523 rtl_release_firmware(tp); 6524 6525 if (pci_dev_run_wake(pdev)) 6526 pm_runtime_get_noresume(&pdev->dev); 6527 6528 /* restore original MAC address */ 6529 rtl_rar_set(tp, dev->perm_addr); 6530 } 6531 6532 static const struct net_device_ops rtl_netdev_ops = { 6533 .ndo_open = rtl_open, 6534 .ndo_stop = rtl8169_close, 6535 .ndo_get_stats64 = rtl8169_get_stats64, 6536 .ndo_start_xmit = rtl8169_start_xmit, 6537 .ndo_features_check = rtl8169_features_check, 6538 .ndo_tx_timeout = rtl8169_tx_timeout, 6539 .ndo_validate_addr = eth_validate_addr, 6540 .ndo_change_mtu = rtl8169_change_mtu, 6541 .ndo_fix_features = rtl8169_fix_features, 6542 .ndo_set_features = rtl8169_set_features, 6543 .ndo_set_mac_address = rtl_set_mac_address, 6544 .ndo_do_ioctl = rtl8169_ioctl, 6545 .ndo_set_rx_mode = rtl_set_rx_mode, 6546 #ifdef CONFIG_NET_POLL_CONTROLLER 6547 .ndo_poll_controller = rtl8169_netpoll, 6548 #endif 6549 6550 }; 6551 6552 static void rtl_set_irq_mask(struct rtl8169_private *tp) 6553 { 6554 tp->irq_mask = RTL_EVENT_NAPI | LinkChg; 6555 6556 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 6557 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 6558 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 6559 /* special workaround needed */ 6560 tp->irq_mask |= RxFIFOOver; 6561 else 6562 tp->irq_mask |= RxOverflow; 6563 } 6564 6565 static int rtl_alloc_irq(struct rtl8169_private *tp) 6566 { 6567 unsigned int flags; 6568 6569 switch (tp->mac_version) { 6570 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6571 rtl_unlock_config_regs(tp); 6572 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 6573 rtl_lock_config_regs(tp); 6574 /* fall through */ 6575 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24: 6576 flags = PCI_IRQ_LEGACY; 6577 break; 6578 default: 6579 flags = PCI_IRQ_ALL_TYPES; 6580 break; 6581 } 6582 6583 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 6584 } 6585 6586 static void rtl_read_mac_address(struct rtl8169_private *tp, 6587 u8 mac_addr[ETH_ALEN]) 6588 { 6589 /* Get MAC address */ 6590 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 6591 u32 value = rtl_eri_read(tp, 0xe0); 6592 6593 mac_addr[0] = (value >> 0) & 0xff; 6594 mac_addr[1] = (value >> 8) & 0xff; 6595 mac_addr[2] = (value >> 16) & 0xff; 6596 mac_addr[3] = (value >> 24) & 0xff; 6597 6598 value = rtl_eri_read(tp, 0xe4); 6599 mac_addr[4] = (value >> 0) & 0xff; 6600 mac_addr[5] = (value >> 8) & 0xff; 6601 } else if (rtl_is_8125(tp)) { 6602 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 6603 } 6604 } 6605 6606 DECLARE_RTL_COND(rtl_link_list_ready_cond) 6607 { 6608 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 6609 } 6610 6611 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 6612 { 6613 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 6614 } 6615 6616 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 6617 { 6618 struct rtl8169_private *tp = mii_bus->priv; 6619 6620 if (phyaddr > 0) 6621 return -ENODEV; 6622 6623 return rtl_readphy(tp, phyreg); 6624 } 6625 6626 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 6627 int phyreg, u16 val) 6628 { 6629 struct rtl8169_private *tp = mii_bus->priv; 6630 6631 if (phyaddr > 0) 6632 return -ENODEV; 6633 6634 rtl_writephy(tp, phyreg, val); 6635 6636 return 0; 6637 } 6638 6639 static int r8169_mdio_register(struct rtl8169_private *tp) 6640 { 6641 struct pci_dev *pdev = tp->pci_dev; 6642 struct mii_bus *new_bus; 6643 int ret; 6644 6645 new_bus = devm_mdiobus_alloc(&pdev->dev); 6646 if (!new_bus) 6647 return -ENOMEM; 6648 6649 new_bus->name = "r8169"; 6650 new_bus->priv = tp; 6651 new_bus->parent = &pdev->dev; 6652 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 6653 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 6654 6655 new_bus->read = r8169_mdio_read_reg; 6656 new_bus->write = r8169_mdio_write_reg; 6657 6658 ret = mdiobus_register(new_bus); 6659 if (ret) 6660 return ret; 6661 6662 tp->phydev = mdiobus_get_phy(new_bus, 0); 6663 if (!tp->phydev) { 6664 mdiobus_unregister(new_bus); 6665 return -ENODEV; 6666 } 6667 6668 /* PHY will be woken up in rtl_open() */ 6669 phy_suspend(tp->phydev); 6670 6671 return 0; 6672 } 6673 6674 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 6675 { 6676 tp->ocp_base = OCP_STD_PHY_BASE; 6677 6678 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6679 6680 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 6681 return; 6682 6683 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6684 return; 6685 6686 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6687 msleep(1); 6688 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6689 6690 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6691 6692 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6693 return; 6694 6695 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 6696 6697 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6698 } 6699 6700 static void rtl_hw_init_8125(struct rtl8169_private *tp) 6701 { 6702 tp->ocp_base = OCP_STD_PHY_BASE; 6703 6704 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6705 6706 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6707 return; 6708 6709 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6710 msleep(1); 6711 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6712 6713 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6714 6715 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6716 return; 6717 6718 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 6719 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 6720 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 6721 6722 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6723 } 6724 6725 static void rtl_hw_initialize(struct rtl8169_private *tp) 6726 { 6727 switch (tp->mac_version) { 6728 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 6729 rtl8168ep_stop_cmac(tp); 6730 /* fall through */ 6731 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 6732 rtl_hw_init_8168g(tp); 6733 break; 6734 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 6735 rtl_hw_init_8125(tp); 6736 break; 6737 default: 6738 break; 6739 } 6740 } 6741 6742 static int rtl_jumbo_max(struct rtl8169_private *tp) 6743 { 6744 /* Non-GBit versions don't support jumbo frames */ 6745 if (!tp->supports_gmii) 6746 return JUMBO_1K; 6747 6748 switch (tp->mac_version) { 6749 /* RTL8169 */ 6750 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6751 return JUMBO_7K; 6752 /* RTL8168b */ 6753 case RTL_GIGA_MAC_VER_11: 6754 case RTL_GIGA_MAC_VER_12: 6755 case RTL_GIGA_MAC_VER_17: 6756 return JUMBO_4K; 6757 /* RTL8168c */ 6758 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 6759 return JUMBO_6K; 6760 default: 6761 return JUMBO_9K; 6762 } 6763 } 6764 6765 static void rtl_disable_clk(void *data) 6766 { 6767 clk_disable_unprepare(data); 6768 } 6769 6770 static int rtl_get_ether_clk(struct rtl8169_private *tp) 6771 { 6772 struct device *d = tp_to_dev(tp); 6773 struct clk *clk; 6774 int rc; 6775 6776 clk = devm_clk_get(d, "ether_clk"); 6777 if (IS_ERR(clk)) { 6778 rc = PTR_ERR(clk); 6779 if (rc == -ENOENT) 6780 /* clk-core allows NULL (for suspend / resume) */ 6781 rc = 0; 6782 else if (rc != -EPROBE_DEFER) 6783 dev_err(d, "failed to get clk: %d\n", rc); 6784 } else { 6785 tp->clk = clk; 6786 rc = clk_prepare_enable(clk); 6787 if (rc) 6788 dev_err(d, "failed to enable clk: %d\n", rc); 6789 else 6790 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 6791 } 6792 6793 return rc; 6794 } 6795 6796 static void rtl_init_mac_address(struct rtl8169_private *tp) 6797 { 6798 struct net_device *dev = tp->dev; 6799 u8 *mac_addr = dev->dev_addr; 6800 int rc; 6801 6802 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 6803 if (!rc) 6804 goto done; 6805 6806 rtl_read_mac_address(tp, mac_addr); 6807 if (is_valid_ether_addr(mac_addr)) 6808 goto done; 6809 6810 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 6811 if (is_valid_ether_addr(mac_addr)) 6812 goto done; 6813 6814 eth_hw_addr_random(dev); 6815 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 6816 done: 6817 rtl_rar_set(tp, mac_addr); 6818 } 6819 6820 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 6821 { 6822 struct rtl8169_private *tp; 6823 struct net_device *dev; 6824 int chipset, region; 6825 int jumbo_max, rc; 6826 6827 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 6828 if (!dev) 6829 return -ENOMEM; 6830 6831 SET_NETDEV_DEV(dev, &pdev->dev); 6832 dev->netdev_ops = &rtl_netdev_ops; 6833 tp = netdev_priv(dev); 6834 tp->dev = dev; 6835 tp->pci_dev = pdev; 6836 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 6837 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 6838 tp->eee_adv = -1; 6839 6840 /* Get the *optional* external "ether_clk" used on some boards */ 6841 rc = rtl_get_ether_clk(tp); 6842 if (rc) 6843 return rc; 6844 6845 /* Disable ASPM completely as that cause random device stop working 6846 * problems as well as full system hangs for some PCIe devices users. 6847 */ 6848 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 6849 PCIE_LINK_STATE_L1); 6850 tp->aspm_manageable = !rc; 6851 6852 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 6853 rc = pcim_enable_device(pdev); 6854 if (rc < 0) { 6855 dev_err(&pdev->dev, "enable failure\n"); 6856 return rc; 6857 } 6858 6859 if (pcim_set_mwi(pdev) < 0) 6860 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 6861 6862 /* use first MMIO region */ 6863 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 6864 if (region < 0) { 6865 dev_err(&pdev->dev, "no MMIO resource found\n"); 6866 return -ENODEV; 6867 } 6868 6869 /* check for weird/broken PCI region reporting */ 6870 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 6871 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 6872 return -ENODEV; 6873 } 6874 6875 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 6876 if (rc < 0) { 6877 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 6878 return rc; 6879 } 6880 6881 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 6882 6883 /* Identify chip attached to board */ 6884 rtl8169_get_mac_version(tp); 6885 if (tp->mac_version == RTL_GIGA_MAC_NONE) 6886 return -ENODEV; 6887 6888 tp->cp_cmd = RTL_R16(tp, CPlusCmd); 6889 6890 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 6891 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 6892 dev->features |= NETIF_F_HIGHDMA; 6893 6894 rtl_init_rxcfg(tp); 6895 6896 rtl8169_irq_mask_and_ack(tp); 6897 6898 rtl_hw_initialize(tp); 6899 6900 rtl_hw_reset(tp); 6901 6902 pci_set_master(pdev); 6903 6904 chipset = tp->mac_version; 6905 6906 rc = rtl_alloc_irq(tp); 6907 if (rc < 0) { 6908 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 6909 return rc; 6910 } 6911 6912 mutex_init(&tp->wk.mutex); 6913 INIT_WORK(&tp->wk.work, rtl_task); 6914 u64_stats_init(&tp->rx_stats.syncp); 6915 u64_stats_init(&tp->tx_stats.syncp); 6916 6917 rtl_init_mac_address(tp); 6918 6919 dev->ethtool_ops = &rtl8169_ethtool_ops; 6920 6921 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 6922 6923 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 6924 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 6925 NETIF_F_HW_VLAN_CTAG_RX; 6926 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 6927 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 6928 NETIF_F_HW_VLAN_CTAG_RX; 6929 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 6930 NETIF_F_HIGHDMA; 6931 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 6932 6933 tp->cp_cmd |= RxChkSum; 6934 /* RTL8125 uses register RxConfig for VLAN offloading config */ 6935 if (!rtl_is_8125(tp)) 6936 tp->cp_cmd |= RxVlan; 6937 /* 6938 * Pretend we are using VLANs; This bypasses a nasty bug where 6939 * Interrupts stop flowing on high load on 8110SCd controllers. 6940 */ 6941 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 6942 /* Disallow toggling */ 6943 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 6944 6945 if (rtl_chip_supports_csum_v2(tp)) { 6946 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 6947 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 6948 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 6949 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 6950 } else { 6951 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 6952 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 6953 } 6954 6955 /* RTL8168e-vl has a HW issue with TSO */ 6956 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { 6957 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 6958 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 6959 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 6960 } 6961 6962 dev->hw_features |= NETIF_F_RXALL; 6963 dev->hw_features |= NETIF_F_RXFCS; 6964 6965 /* MTU range: 60 - hw-specific max */ 6966 dev->min_mtu = ETH_ZLEN; 6967 jumbo_max = rtl_jumbo_max(tp); 6968 dev->max_mtu = jumbo_max; 6969 6970 rtl_set_irq_mask(tp); 6971 6972 tp->fw_name = rtl_chip_infos[chipset].fw_name; 6973 6974 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 6975 &tp->counters_phys_addr, 6976 GFP_KERNEL); 6977 if (!tp->counters) 6978 return -ENOMEM; 6979 6980 pci_set_drvdata(pdev, dev); 6981 6982 rc = r8169_mdio_register(tp); 6983 if (rc) 6984 return rc; 6985 6986 /* chip gets powered up in rtl_open() */ 6987 rtl_pll_power_down(tp); 6988 6989 rc = register_netdev(dev); 6990 if (rc) 6991 goto err_mdio_unregister; 6992 6993 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n", 6994 rtl_chip_infos[chipset].name, dev->dev_addr, 6995 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf, 6996 pci_irq_vector(pdev, 0)); 6997 6998 if (jumbo_max > JUMBO_1K) 6999 netif_info(tp, probe, dev, 7000 "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 7001 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 7002 "ok" : "ko"); 7003 7004 if (r8168_check_dash(tp)) 7005 rtl8168_driver_start(tp); 7006 7007 if (pci_dev_run_wake(pdev)) 7008 pm_runtime_put_sync(&pdev->dev); 7009 7010 return 0; 7011 7012 err_mdio_unregister: 7013 mdiobus_unregister(tp->phydev->mdio.bus); 7014 return rc; 7015 } 7016 7017 static struct pci_driver rtl8169_pci_driver = { 7018 .name = MODULENAME, 7019 .id_table = rtl8169_pci_tbl, 7020 .probe = rtl_init_one, 7021 .remove = rtl_remove_one, 7022 .shutdown = rtl_shutdown, 7023 .driver.pm = RTL8169_PM_OPS, 7024 }; 7025 7026 module_pci_driver(rtl8169_pci_driver); 7027