1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 59 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 60 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 61 62 #define R8169_REGS_SIZE 256 63 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 64 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 65 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 66 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 67 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 68 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 69 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 70 71 #define OCP_STD_PHY_BASE 0xa400 72 73 #define RTL_CFG_NO_GBIT 1 74 75 /* write/read MMIO register */ 76 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 77 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 78 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 79 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 80 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 81 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 82 83 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 84 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 88 static const struct { 89 const char *name; 90 const char *fw_name; 91 } rtl_chip_infos[] = { 92 /* PCI devices. */ 93 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 94 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 95 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 96 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 97 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 98 /* PCI-E devices. */ 99 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 100 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 102 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 103 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 104 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 105 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 106 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 107 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 108 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 109 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 112 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 114 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 115 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 116 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 117 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 118 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 119 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 120 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 121 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 122 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 123 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 124 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 125 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 126 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 127 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 128 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 129 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 130 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 131 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 132 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 133 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 134 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 135 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 136 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 137 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 138 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 139 }; 140 141 static const struct pci_device_id rtl8169_pci_tbl[] = { 142 { PCI_VDEVICE(REALTEK, 0x2502) }, 143 { PCI_VDEVICE(REALTEK, 0x2600) }, 144 { PCI_VDEVICE(REALTEK, 0x8129) }, 145 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 146 { PCI_VDEVICE(REALTEK, 0x8161) }, 147 { PCI_VDEVICE(REALTEK, 0x8162) }, 148 { PCI_VDEVICE(REALTEK, 0x8167) }, 149 { PCI_VDEVICE(REALTEK, 0x8168) }, 150 { PCI_VDEVICE(NCUBE, 0x8168) }, 151 { PCI_VDEVICE(REALTEK, 0x8169) }, 152 { PCI_VENDOR_ID_DLINK, 0x4300, 153 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 154 { PCI_VDEVICE(DLINK, 0x4300) }, 155 { PCI_VDEVICE(DLINK, 0x4302) }, 156 { PCI_VDEVICE(AT, 0xc107) }, 157 { PCI_VDEVICE(USR, 0x0116) }, 158 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 159 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 160 { PCI_VDEVICE(REALTEK, 0x8125) }, 161 { PCI_VDEVICE(REALTEK, 0x3000) }, 162 {} 163 }; 164 165 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 166 167 enum rtl_registers { 168 MAC0 = 0, /* Ethernet hardware address. */ 169 MAC4 = 4, 170 MAR0 = 8, /* Multicast filter. */ 171 CounterAddrLow = 0x10, 172 CounterAddrHigh = 0x14, 173 TxDescStartAddrLow = 0x20, 174 TxDescStartAddrHigh = 0x24, 175 TxHDescStartAddrLow = 0x28, 176 TxHDescStartAddrHigh = 0x2c, 177 FLASH = 0x30, 178 ERSR = 0x36, 179 ChipCmd = 0x37, 180 TxPoll = 0x38, 181 IntrMask = 0x3c, 182 IntrStatus = 0x3e, 183 184 TxConfig = 0x40, 185 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 186 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 187 188 RxConfig = 0x44, 189 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 190 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 191 #define RXCFG_FIFO_SHIFT 13 192 /* No threshold before first PCI xfer */ 193 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 194 #define RX_EARLY_OFF (1 << 11) 195 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 196 #define RXCFG_DMA_SHIFT 8 197 /* Unlimited maximum PCI burst. */ 198 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 199 200 Cfg9346 = 0x50, 201 Config0 = 0x51, 202 Config1 = 0x52, 203 Config2 = 0x53, 204 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 205 206 Config3 = 0x54, 207 Config4 = 0x55, 208 Config5 = 0x56, 209 PHYAR = 0x60, 210 PHYstatus = 0x6c, 211 RxMaxSize = 0xda, 212 CPlusCmd = 0xe0, 213 IntrMitigate = 0xe2, 214 215 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 216 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 217 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 218 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 219 220 #define RTL_COALESCE_T_MAX 0x0fU 221 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 222 223 RxDescAddrLow = 0xe4, 224 RxDescAddrHigh = 0xe8, 225 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 226 227 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 228 229 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 230 231 #define TxPacketMax (8064 >> 7) 232 #define EarlySize 0x27 233 234 FuncEvent = 0xf0, 235 FuncEventMask = 0xf4, 236 FuncPresetState = 0xf8, 237 IBCR0 = 0xf8, 238 IBCR2 = 0xf9, 239 IBIMR0 = 0xfa, 240 IBISR0 = 0xfb, 241 FuncForceEvent = 0xfc, 242 }; 243 244 enum rtl8168_8101_registers { 245 CSIDR = 0x64, 246 CSIAR = 0x68, 247 #define CSIAR_FLAG 0x80000000 248 #define CSIAR_WRITE_CMD 0x80000000 249 #define CSIAR_BYTE_ENABLE 0x0000f000 250 #define CSIAR_ADDR_MASK 0x00000fff 251 PMCH = 0x6f, 252 #define D3COLD_NO_PLL_DOWN BIT(7) 253 #define D3HOT_NO_PLL_DOWN BIT(6) 254 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 255 EPHYAR = 0x80, 256 #define EPHYAR_FLAG 0x80000000 257 #define EPHYAR_WRITE_CMD 0x80000000 258 #define EPHYAR_REG_MASK 0x1f 259 #define EPHYAR_REG_SHIFT 16 260 #define EPHYAR_DATA_MASK 0xffff 261 DLLPR = 0xd0, 262 #define PFM_EN (1 << 6) 263 #define TX_10M_PS_EN (1 << 7) 264 DBG_REG = 0xd1, 265 #define FIX_NAK_1 (1 << 4) 266 #define FIX_NAK_2 (1 << 3) 267 TWSI = 0xd2, 268 MCU = 0xd3, 269 #define NOW_IS_OOB (1 << 7) 270 #define TX_EMPTY (1 << 5) 271 #define RX_EMPTY (1 << 4) 272 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 273 #define EN_NDP (1 << 3) 274 #define EN_OOB_RESET (1 << 2) 275 #define LINK_LIST_RDY (1 << 1) 276 EFUSEAR = 0xdc, 277 #define EFUSEAR_FLAG 0x80000000 278 #define EFUSEAR_WRITE_CMD 0x80000000 279 #define EFUSEAR_READ_CMD 0x00000000 280 #define EFUSEAR_REG_MASK 0x03ff 281 #define EFUSEAR_REG_SHIFT 8 282 #define EFUSEAR_DATA_MASK 0xff 283 MISC_1 = 0xf2, 284 #define PFM_D3COLD_EN (1 << 6) 285 }; 286 287 enum rtl8168_registers { 288 LED_FREQ = 0x1a, 289 EEE_LED = 0x1b, 290 ERIDR = 0x70, 291 ERIAR = 0x74, 292 #define ERIAR_FLAG 0x80000000 293 #define ERIAR_WRITE_CMD 0x80000000 294 #define ERIAR_READ_CMD 0x00000000 295 #define ERIAR_ADDR_BYTE_ALIGN 4 296 #define ERIAR_TYPE_SHIFT 16 297 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 298 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 299 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 300 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 301 #define ERIAR_MASK_SHIFT 12 302 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 303 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 304 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 305 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 306 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 307 EPHY_RXER_NUM = 0x7c, 308 OCPDR = 0xb0, /* OCP GPHY access */ 309 #define OCPDR_WRITE_CMD 0x80000000 310 #define OCPDR_READ_CMD 0x00000000 311 #define OCPDR_REG_MASK 0x7f 312 #define OCPDR_GPHY_REG_SHIFT 16 313 #define OCPDR_DATA_MASK 0xffff 314 OCPAR = 0xb4, 315 #define OCPAR_FLAG 0x80000000 316 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 317 #define OCPAR_GPHY_READ_CMD 0x0000f060 318 GPHY_OCP = 0xb8, 319 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 320 MISC = 0xf0, /* 8168e only. */ 321 #define TXPLA_RST (1 << 29) 322 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 323 #define PWM_EN (1 << 22) 324 #define RXDV_GATED_EN (1 << 19) 325 #define EARLY_TALLY_EN (1 << 16) 326 }; 327 328 enum rtl8125_registers { 329 IntrMask_8125 = 0x38, 330 IntrStatus_8125 = 0x3c, 331 TxPoll_8125 = 0x90, 332 MAC0_BKP = 0x19e0, 333 EEE_TXIDLE_TIMER_8125 = 0x6048, 334 }; 335 336 #define RX_VLAN_INNER_8125 BIT(22) 337 #define RX_VLAN_OUTER_8125 BIT(23) 338 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 339 340 #define RX_FETCH_DFLT_8125 (8 << 27) 341 342 enum rtl_register_content { 343 /* InterruptStatusBits */ 344 SYSErr = 0x8000, 345 PCSTimeout = 0x4000, 346 SWInt = 0x0100, 347 TxDescUnavail = 0x0080, 348 RxFIFOOver = 0x0040, 349 LinkChg = 0x0020, 350 RxOverflow = 0x0010, 351 TxErr = 0x0008, 352 TxOK = 0x0004, 353 RxErr = 0x0002, 354 RxOK = 0x0001, 355 356 /* RxStatusDesc */ 357 RxRWT = (1 << 22), 358 RxRES = (1 << 21), 359 RxRUNT = (1 << 20), 360 RxCRC = (1 << 19), 361 362 /* ChipCmdBits */ 363 StopReq = 0x80, 364 CmdReset = 0x10, 365 CmdRxEnb = 0x08, 366 CmdTxEnb = 0x04, 367 RxBufEmpty = 0x01, 368 369 /* TXPoll register p.5 */ 370 HPQ = 0x80, /* Poll cmd on the high prio queue */ 371 NPQ = 0x40, /* Poll cmd on the low prio queue */ 372 FSWInt = 0x01, /* Forced software interrupt */ 373 374 /* Cfg9346Bits */ 375 Cfg9346_Lock = 0x00, 376 Cfg9346_Unlock = 0xc0, 377 378 /* rx_mode_bits */ 379 AcceptErr = 0x20, 380 AcceptRunt = 0x10, 381 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 382 AcceptBroadcast = 0x08, 383 AcceptMulticast = 0x04, 384 AcceptMyPhys = 0x02, 385 AcceptAllPhys = 0x01, 386 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 387 #define RX_CONFIG_ACCEPT_MASK 0x3f 388 389 /* TxConfigBits */ 390 TxInterFrameGapShift = 24, 391 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 392 393 /* Config1 register p.24 */ 394 LEDS1 = (1 << 7), 395 LEDS0 = (1 << 6), 396 Speed_down = (1 << 4), 397 MEMMAP = (1 << 3), 398 IOMAP = (1 << 2), 399 VPD = (1 << 1), 400 PMEnable = (1 << 0), /* Power Management Enable */ 401 402 /* Config2 register p. 25 */ 403 ClkReqEn = (1 << 7), /* Clock Request Enable */ 404 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 405 PCI_Clock_66MHz = 0x01, 406 PCI_Clock_33MHz = 0x00, 407 408 /* Config3 register p.25 */ 409 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 410 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 411 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 412 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 413 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 414 415 /* Config4 register */ 416 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 417 418 /* Config5 register p.27 */ 419 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 420 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 421 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 422 Spi_en = (1 << 3), 423 LanWake = (1 << 1), /* LanWake enable/disable */ 424 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 425 ASPM_en = (1 << 0), /* ASPM enable */ 426 427 /* CPlusCmd p.31 */ 428 EnableBist = (1 << 15), // 8168 8101 429 Mac_dbgo_oe = (1 << 14), // 8168 8101 430 EnAnaPLL = (1 << 14), // 8169 431 Normal_mode = (1 << 13), // unused 432 Force_half_dup = (1 << 12), // 8168 8101 433 Force_rxflow_en = (1 << 11), // 8168 8101 434 Force_txflow_en = (1 << 10), // 8168 8101 435 Cxpl_dbg_sel = (1 << 9), // 8168 8101 436 ASF = (1 << 8), // 8168 8101 437 PktCntrDisable = (1 << 7), // 8168 8101 438 Mac_dbgo_sel = 0x001c, // 8168 439 RxVlan = (1 << 6), 440 RxChkSum = (1 << 5), 441 PCIDAC = (1 << 4), 442 PCIMulRW = (1 << 3), 443 #define INTT_MASK GENMASK(1, 0) 444 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 445 446 /* rtl8169_PHYstatus */ 447 TBI_Enable = 0x80, 448 TxFlowCtrl = 0x40, 449 RxFlowCtrl = 0x20, 450 _1000bpsF = 0x10, 451 _100bps = 0x08, 452 _10bps = 0x04, 453 LinkStatus = 0x02, 454 FullDup = 0x01, 455 456 /* ResetCounterCommand */ 457 CounterReset = 0x1, 458 459 /* DumpCounterCommand */ 460 CounterDump = 0x8, 461 462 /* magic enable v2 */ 463 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 464 }; 465 466 enum rtl_desc_bit { 467 /* First doubleword. */ 468 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 469 RingEnd = (1 << 30), /* End of descriptor ring */ 470 FirstFrag = (1 << 29), /* First segment of a packet */ 471 LastFrag = (1 << 28), /* Final segment of a packet */ 472 }; 473 474 /* Generic case. */ 475 enum rtl_tx_desc_bit { 476 /* First doubleword. */ 477 TD_LSO = (1 << 27), /* Large Send Offload */ 478 #define TD_MSS_MAX 0x07ffu /* MSS value */ 479 480 /* Second doubleword. */ 481 TxVlanTag = (1 << 17), /* Add VLAN tag */ 482 }; 483 484 /* 8169, 8168b and 810x except 8102e. */ 485 enum rtl_tx_desc_bit_0 { 486 /* First doubleword. */ 487 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 488 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 489 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 490 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 491 }; 492 493 /* 8102e, 8168c and beyond. */ 494 enum rtl_tx_desc_bit_1 { 495 /* First doubleword. */ 496 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 497 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 498 #define GTTCPHO_SHIFT 18 499 #define GTTCPHO_MAX 0x7f 500 501 /* Second doubleword. */ 502 #define TCPHO_SHIFT 18 503 #define TCPHO_MAX 0x3ff 504 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 505 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 506 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 507 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 508 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 509 }; 510 511 enum rtl_rx_desc_bit { 512 /* Rx private */ 513 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 514 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 515 516 #define RxProtoUDP (PID1) 517 #define RxProtoTCP (PID0) 518 #define RxProtoIP (PID1 | PID0) 519 #define RxProtoMask RxProtoIP 520 521 IPFail = (1 << 16), /* IP checksum failed */ 522 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 523 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 524 525 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 526 527 RxVlanTag = (1 << 16), /* VLAN tag available */ 528 }; 529 530 #define RTL_GSO_MAX_SIZE_V1 32000 531 #define RTL_GSO_MAX_SEGS_V1 24 532 #define RTL_GSO_MAX_SIZE_V2 64000 533 #define RTL_GSO_MAX_SEGS_V2 64 534 535 struct TxDesc { 536 __le32 opts1; 537 __le32 opts2; 538 __le64 addr; 539 }; 540 541 struct RxDesc { 542 __le32 opts1; 543 __le32 opts2; 544 __le64 addr; 545 }; 546 547 struct ring_info { 548 struct sk_buff *skb; 549 u32 len; 550 }; 551 552 struct rtl8169_counters { 553 __le64 tx_packets; 554 __le64 rx_packets; 555 __le64 tx_errors; 556 __le32 rx_errors; 557 __le16 rx_missed; 558 __le16 align_errors; 559 __le32 tx_one_collision; 560 __le32 tx_multi_collision; 561 __le64 rx_unicast; 562 __le64 rx_broadcast; 563 __le32 rx_multicast; 564 __le16 tx_aborted; 565 __le16 tx_underun; 566 }; 567 568 struct rtl8169_tc_offsets { 569 bool inited; 570 __le64 tx_errors; 571 __le32 tx_multi_collision; 572 __le16 tx_aborted; 573 __le16 rx_missed; 574 }; 575 576 enum rtl_flag { 577 RTL_FLAG_TASK_ENABLED = 0, 578 RTL_FLAG_TASK_RESET_PENDING, 579 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 580 RTL_FLAG_TASK_TX_TIMEOUT, 581 RTL_FLAG_MAX 582 }; 583 584 enum rtl_dash_type { 585 RTL_DASH_NONE, 586 RTL_DASH_DP, 587 RTL_DASH_EP, 588 }; 589 590 struct rtl8169_private { 591 void __iomem *mmio_addr; /* memory map physical address */ 592 struct pci_dev *pci_dev; 593 struct net_device *dev; 594 struct phy_device *phydev; 595 struct napi_struct napi; 596 enum mac_version mac_version; 597 enum rtl_dash_type dash_type; 598 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 599 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 600 u32 dirty_tx; 601 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 602 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 603 dma_addr_t TxPhyAddr; 604 dma_addr_t RxPhyAddr; 605 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 606 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 607 u16 cp_cmd; 608 u32 irq_mask; 609 int irq; 610 struct clk *clk; 611 612 struct { 613 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 614 struct work_struct work; 615 } wk; 616 617 raw_spinlock_t config25_lock; 618 raw_spinlock_t mac_ocp_lock; 619 620 raw_spinlock_t cfg9346_usage_lock; 621 int cfg9346_usage_count; 622 623 unsigned supports_gmii:1; 624 unsigned aspm_manageable:1; 625 unsigned dash_enabled:1; 626 dma_addr_t counters_phys_addr; 627 struct rtl8169_counters *counters; 628 struct rtl8169_tc_offsets tc_offset; 629 u32 saved_wolopts; 630 int eee_adv; 631 632 const char *fw_name; 633 struct rtl_fw *rtl_fw; 634 635 u32 ocp_base; 636 }; 637 638 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 639 640 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 641 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 642 MODULE_SOFTDEP("pre: realtek"); 643 MODULE_LICENSE("GPL"); 644 MODULE_FIRMWARE(FIRMWARE_8168D_1); 645 MODULE_FIRMWARE(FIRMWARE_8168D_2); 646 MODULE_FIRMWARE(FIRMWARE_8168E_1); 647 MODULE_FIRMWARE(FIRMWARE_8168E_2); 648 MODULE_FIRMWARE(FIRMWARE_8168E_3); 649 MODULE_FIRMWARE(FIRMWARE_8105E_1); 650 MODULE_FIRMWARE(FIRMWARE_8168F_1); 651 MODULE_FIRMWARE(FIRMWARE_8168F_2); 652 MODULE_FIRMWARE(FIRMWARE_8402_1); 653 MODULE_FIRMWARE(FIRMWARE_8411_1); 654 MODULE_FIRMWARE(FIRMWARE_8411_2); 655 MODULE_FIRMWARE(FIRMWARE_8106E_1); 656 MODULE_FIRMWARE(FIRMWARE_8106E_2); 657 MODULE_FIRMWARE(FIRMWARE_8168G_2); 658 MODULE_FIRMWARE(FIRMWARE_8168G_3); 659 MODULE_FIRMWARE(FIRMWARE_8168H_2); 660 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 661 MODULE_FIRMWARE(FIRMWARE_8107E_2); 662 MODULE_FIRMWARE(FIRMWARE_8125A_3); 663 MODULE_FIRMWARE(FIRMWARE_8125B_2); 664 665 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 666 { 667 return &tp->pci_dev->dev; 668 } 669 670 static void rtl_lock_config_regs(struct rtl8169_private *tp) 671 { 672 unsigned long flags; 673 674 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 675 if (!--tp->cfg9346_usage_count) 676 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 677 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 678 } 679 680 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 681 { 682 unsigned long flags; 683 684 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 685 if (!tp->cfg9346_usage_count++) 686 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 687 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 688 } 689 690 static void rtl_pci_commit(struct rtl8169_private *tp) 691 { 692 /* Read an arbitrary register to commit a preceding PCI write */ 693 RTL_R8(tp, ChipCmd); 694 } 695 696 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 697 { 698 unsigned long flags; 699 u8 val; 700 701 raw_spin_lock_irqsave(&tp->config25_lock, flags); 702 val = RTL_R8(tp, Config2); 703 RTL_W8(tp, Config2, (val & ~clear) | set); 704 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 705 } 706 707 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 708 { 709 unsigned long flags; 710 u8 val; 711 712 raw_spin_lock_irqsave(&tp->config25_lock, flags); 713 val = RTL_R8(tp, Config5); 714 RTL_W8(tp, Config5, (val & ~clear) | set); 715 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 716 } 717 718 static bool rtl_is_8125(struct rtl8169_private *tp) 719 { 720 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 721 } 722 723 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 724 { 725 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 726 tp->mac_version != RTL_GIGA_MAC_VER_39 && 727 tp->mac_version <= RTL_GIGA_MAC_VER_53; 728 } 729 730 static bool rtl_supports_eee(struct rtl8169_private *tp) 731 { 732 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 733 tp->mac_version != RTL_GIGA_MAC_VER_37 && 734 tp->mac_version != RTL_GIGA_MAC_VER_39; 735 } 736 737 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 738 { 739 int i; 740 741 for (i = 0; i < ETH_ALEN; i++) 742 mac[i] = RTL_R8(tp, reg + i); 743 } 744 745 struct rtl_cond { 746 bool (*check)(struct rtl8169_private *); 747 const char *msg; 748 }; 749 750 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 751 unsigned long usecs, int n, bool high) 752 { 753 int i; 754 755 for (i = 0; i < n; i++) { 756 if (c->check(tp) == high) 757 return true; 758 fsleep(usecs); 759 } 760 761 if (net_ratelimit()) 762 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 763 c->msg, !high, n, usecs); 764 return false; 765 } 766 767 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 768 const struct rtl_cond *c, 769 unsigned long d, int n) 770 { 771 return rtl_loop_wait(tp, c, d, n, true); 772 } 773 774 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 775 const struct rtl_cond *c, 776 unsigned long d, int n) 777 { 778 return rtl_loop_wait(tp, c, d, n, false); 779 } 780 781 #define DECLARE_RTL_COND(name) \ 782 static bool name ## _check(struct rtl8169_private *); \ 783 \ 784 static const struct rtl_cond name = { \ 785 .check = name ## _check, \ 786 .msg = #name \ 787 }; \ 788 \ 789 static bool name ## _check(struct rtl8169_private *tp) 790 791 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 792 { 793 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 794 if (type == ERIAR_OOB && 795 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 796 tp->mac_version == RTL_GIGA_MAC_VER_53)) 797 *cmd |= 0xf70 << 18; 798 } 799 800 DECLARE_RTL_COND(rtl_eriar_cond) 801 { 802 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 803 } 804 805 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 806 u32 val, int type) 807 { 808 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 809 810 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 811 return; 812 813 RTL_W32(tp, ERIDR, val); 814 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 815 RTL_W32(tp, ERIAR, cmd); 816 817 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 818 } 819 820 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 821 u32 val) 822 { 823 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 824 } 825 826 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 827 { 828 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 829 830 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 831 RTL_W32(tp, ERIAR, cmd); 832 833 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 834 RTL_R32(tp, ERIDR) : ~0; 835 } 836 837 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 838 { 839 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 840 } 841 842 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 843 { 844 u32 val = rtl_eri_read(tp, addr); 845 846 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 847 } 848 849 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 850 { 851 rtl_w0w1_eri(tp, addr, p, 0); 852 } 853 854 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 855 { 856 rtl_w0w1_eri(tp, addr, 0, m); 857 } 858 859 static bool rtl_ocp_reg_failure(u32 reg) 860 { 861 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 862 } 863 864 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 865 { 866 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 867 } 868 869 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 870 { 871 if (rtl_ocp_reg_failure(reg)) 872 return; 873 874 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 875 876 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 877 } 878 879 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 880 { 881 if (rtl_ocp_reg_failure(reg)) 882 return 0; 883 884 RTL_W32(tp, GPHY_OCP, reg << 15); 885 886 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 887 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 888 } 889 890 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 891 { 892 if (rtl_ocp_reg_failure(reg)) 893 return; 894 895 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 896 } 897 898 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 899 { 900 unsigned long flags; 901 902 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 903 __r8168_mac_ocp_write(tp, reg, data); 904 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 905 } 906 907 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 908 { 909 if (rtl_ocp_reg_failure(reg)) 910 return 0; 911 912 RTL_W32(tp, OCPDR, reg << 15); 913 914 return RTL_R32(tp, OCPDR); 915 } 916 917 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 918 { 919 unsigned long flags; 920 u16 val; 921 922 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 923 val = __r8168_mac_ocp_read(tp, reg); 924 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 925 926 return val; 927 } 928 929 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 930 u16 set) 931 { 932 unsigned long flags; 933 u16 data; 934 935 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 936 data = __r8168_mac_ocp_read(tp, reg); 937 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 938 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 939 } 940 941 /* Work around a hw issue with RTL8168g PHY, the quirk disables 942 * PHY MCU interrupts before PHY power-down. 943 */ 944 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 945 { 946 switch (tp->mac_version) { 947 case RTL_GIGA_MAC_VER_40: 948 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 949 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 950 else 951 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 952 break; 953 default: 954 break; 955 } 956 }; 957 958 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 959 { 960 if (reg == 0x1f) { 961 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 962 return; 963 } 964 965 if (tp->ocp_base != OCP_STD_PHY_BASE) 966 reg -= 0x10; 967 968 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 969 rtl8168g_phy_suspend_quirk(tp, value); 970 971 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 972 } 973 974 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 975 { 976 if (reg == 0x1f) 977 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 978 979 if (tp->ocp_base != OCP_STD_PHY_BASE) 980 reg -= 0x10; 981 982 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 983 } 984 985 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 986 { 987 if (reg == 0x1f) { 988 tp->ocp_base = value << 4; 989 return; 990 } 991 992 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 993 } 994 995 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 996 { 997 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 998 } 999 1000 DECLARE_RTL_COND(rtl_phyar_cond) 1001 { 1002 return RTL_R32(tp, PHYAR) & 0x80000000; 1003 } 1004 1005 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1006 { 1007 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1008 1009 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1010 /* 1011 * According to hardware specs a 20us delay is required after write 1012 * complete indication, but before sending next command. 1013 */ 1014 udelay(20); 1015 } 1016 1017 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1018 { 1019 int value; 1020 1021 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1022 1023 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1024 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1025 1026 /* 1027 * According to hardware specs a 20us delay is required after read 1028 * complete indication, but before sending next command. 1029 */ 1030 udelay(20); 1031 1032 return value; 1033 } 1034 1035 DECLARE_RTL_COND(rtl_ocpar_cond) 1036 { 1037 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1038 } 1039 1040 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1041 1042 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1043 { 1044 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1045 } 1046 1047 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1048 { 1049 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1050 } 1051 1052 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1053 { 1054 r8168dp_2_mdio_start(tp); 1055 1056 r8169_mdio_write(tp, reg, value); 1057 1058 r8168dp_2_mdio_stop(tp); 1059 } 1060 1061 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1062 { 1063 int value; 1064 1065 /* Work around issue with chip reporting wrong PHY ID */ 1066 if (reg == MII_PHYSID2) 1067 return 0xc912; 1068 1069 r8168dp_2_mdio_start(tp); 1070 1071 value = r8169_mdio_read(tp, reg); 1072 1073 r8168dp_2_mdio_stop(tp); 1074 1075 return value; 1076 } 1077 1078 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1079 { 1080 switch (tp->mac_version) { 1081 case RTL_GIGA_MAC_VER_28: 1082 case RTL_GIGA_MAC_VER_31: 1083 r8168dp_2_mdio_write(tp, location, val); 1084 break; 1085 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1086 r8168g_mdio_write(tp, location, val); 1087 break; 1088 default: 1089 r8169_mdio_write(tp, location, val); 1090 break; 1091 } 1092 } 1093 1094 static int rtl_readphy(struct rtl8169_private *tp, int location) 1095 { 1096 switch (tp->mac_version) { 1097 case RTL_GIGA_MAC_VER_28: 1098 case RTL_GIGA_MAC_VER_31: 1099 return r8168dp_2_mdio_read(tp, location); 1100 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1101 return r8168g_mdio_read(tp, location); 1102 default: 1103 return r8169_mdio_read(tp, location); 1104 } 1105 } 1106 1107 DECLARE_RTL_COND(rtl_ephyar_cond) 1108 { 1109 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1110 } 1111 1112 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1113 { 1114 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1115 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1116 1117 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1118 1119 udelay(10); 1120 } 1121 1122 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1123 { 1124 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1125 1126 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1127 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1128 } 1129 1130 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1131 { 1132 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1133 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1134 RTL_R32(tp, OCPDR) : ~0; 1135 } 1136 1137 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1138 { 1139 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1140 } 1141 1142 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1143 u32 data) 1144 { 1145 RTL_W32(tp, OCPDR, data); 1146 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1147 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1148 } 1149 1150 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1151 u32 data) 1152 { 1153 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1154 data, ERIAR_OOB); 1155 } 1156 1157 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1158 { 1159 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1160 1161 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1162 } 1163 1164 #define OOB_CMD_RESET 0x00 1165 #define OOB_CMD_DRIVER_START 0x05 1166 #define OOB_CMD_DRIVER_STOP 0x06 1167 1168 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1169 { 1170 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1171 } 1172 1173 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1174 { 1175 u16 reg; 1176 1177 reg = rtl8168_get_ocp_reg(tp); 1178 1179 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1180 } 1181 1182 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1183 { 1184 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1185 } 1186 1187 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1188 { 1189 return RTL_R8(tp, IBISR0) & 0x20; 1190 } 1191 1192 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1193 { 1194 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1195 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1196 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1197 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1198 } 1199 1200 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1201 { 1202 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1203 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1204 } 1205 1206 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1207 { 1208 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1209 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1210 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1211 } 1212 1213 static void rtl8168_driver_start(struct rtl8169_private *tp) 1214 { 1215 if (tp->dash_type == RTL_DASH_DP) 1216 rtl8168dp_driver_start(tp); 1217 else 1218 rtl8168ep_driver_start(tp); 1219 } 1220 1221 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1222 { 1223 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1224 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1225 } 1226 1227 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1228 { 1229 rtl8168ep_stop_cmac(tp); 1230 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1231 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1232 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1233 } 1234 1235 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1236 { 1237 if (tp->dash_type == RTL_DASH_DP) 1238 rtl8168dp_driver_stop(tp); 1239 else 1240 rtl8168ep_driver_stop(tp); 1241 } 1242 1243 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1244 { 1245 u16 reg = rtl8168_get_ocp_reg(tp); 1246 1247 return r8168dp_ocp_read(tp, reg) & BIT(15); 1248 } 1249 1250 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1251 { 1252 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1253 } 1254 1255 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1256 { 1257 switch (tp->dash_type) { 1258 case RTL_DASH_DP: 1259 return r8168dp_check_dash(tp); 1260 case RTL_DASH_EP: 1261 return r8168ep_check_dash(tp); 1262 default: 1263 return false; 1264 } 1265 } 1266 1267 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1268 { 1269 switch (tp->mac_version) { 1270 case RTL_GIGA_MAC_VER_28: 1271 case RTL_GIGA_MAC_VER_31: 1272 return RTL_DASH_DP; 1273 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1274 return RTL_DASH_EP; 1275 default: 1276 return RTL_DASH_NONE; 1277 } 1278 } 1279 1280 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1281 { 1282 switch (tp->mac_version) { 1283 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1284 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1285 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1286 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1287 if (enable) 1288 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1289 else 1290 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1291 break; 1292 default: 1293 break; 1294 } 1295 } 1296 1297 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1298 { 1299 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1300 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1301 } 1302 1303 DECLARE_RTL_COND(rtl_efusear_cond) 1304 { 1305 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1306 } 1307 1308 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1309 { 1310 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1311 1312 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1313 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1314 } 1315 1316 static u32 rtl_get_events(struct rtl8169_private *tp) 1317 { 1318 if (rtl_is_8125(tp)) 1319 return RTL_R32(tp, IntrStatus_8125); 1320 else 1321 return RTL_R16(tp, IntrStatus); 1322 } 1323 1324 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1325 { 1326 if (rtl_is_8125(tp)) 1327 RTL_W32(tp, IntrStatus_8125, bits); 1328 else 1329 RTL_W16(tp, IntrStatus, bits); 1330 } 1331 1332 static void rtl_irq_disable(struct rtl8169_private *tp) 1333 { 1334 if (rtl_is_8125(tp)) 1335 RTL_W32(tp, IntrMask_8125, 0); 1336 else 1337 RTL_W16(tp, IntrMask, 0); 1338 } 1339 1340 static void rtl_irq_enable(struct rtl8169_private *tp) 1341 { 1342 if (rtl_is_8125(tp)) 1343 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1344 else 1345 RTL_W16(tp, IntrMask, tp->irq_mask); 1346 } 1347 1348 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1349 { 1350 rtl_irq_disable(tp); 1351 rtl_ack_events(tp, 0xffffffff); 1352 rtl_pci_commit(tp); 1353 } 1354 1355 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1356 { 1357 struct phy_device *phydev = tp->phydev; 1358 1359 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1360 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1361 if (phydev->speed == SPEED_1000) { 1362 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1363 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1364 } else if (phydev->speed == SPEED_100) { 1365 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1366 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1367 } else { 1368 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1369 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1370 } 1371 rtl_reset_packet_filter(tp); 1372 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1373 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1374 if (phydev->speed == SPEED_1000) { 1375 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1376 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1377 } else { 1378 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1379 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1380 } 1381 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1382 if (phydev->speed == SPEED_10) { 1383 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1384 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1385 } else { 1386 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1387 } 1388 } 1389 } 1390 1391 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1392 1393 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1394 { 1395 struct rtl8169_private *tp = netdev_priv(dev); 1396 1397 wol->supported = WAKE_ANY; 1398 wol->wolopts = tp->saved_wolopts; 1399 } 1400 1401 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1402 { 1403 static const struct { 1404 u32 opt; 1405 u16 reg; 1406 u8 mask; 1407 } cfg[] = { 1408 { WAKE_PHY, Config3, LinkUp }, 1409 { WAKE_UCAST, Config5, UWF }, 1410 { WAKE_BCAST, Config5, BWF }, 1411 { WAKE_MCAST, Config5, MWF }, 1412 { WAKE_ANY, Config5, LanWake }, 1413 { WAKE_MAGIC, Config3, MagicPacket } 1414 }; 1415 unsigned int i, tmp = ARRAY_SIZE(cfg); 1416 unsigned long flags; 1417 u8 options; 1418 1419 rtl_unlock_config_regs(tp); 1420 1421 if (rtl_is_8168evl_up(tp)) { 1422 tmp--; 1423 if (wolopts & WAKE_MAGIC) 1424 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1425 else 1426 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1427 } else if (rtl_is_8125(tp)) { 1428 tmp--; 1429 if (wolopts & WAKE_MAGIC) 1430 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1431 else 1432 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1433 } 1434 1435 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1436 for (i = 0; i < tmp; i++) { 1437 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1438 if (wolopts & cfg[i].opt) 1439 options |= cfg[i].mask; 1440 RTL_W8(tp, cfg[i].reg, options); 1441 } 1442 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1443 1444 switch (tp->mac_version) { 1445 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1446 options = RTL_R8(tp, Config1) & ~PMEnable; 1447 if (wolopts) 1448 options |= PMEnable; 1449 RTL_W8(tp, Config1, options); 1450 break; 1451 case RTL_GIGA_MAC_VER_34: 1452 case RTL_GIGA_MAC_VER_37: 1453 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1454 if (wolopts) 1455 rtl_mod_config2(tp, 0, PME_SIGNAL); 1456 else 1457 rtl_mod_config2(tp, PME_SIGNAL, 0); 1458 break; 1459 default: 1460 break; 1461 } 1462 1463 rtl_lock_config_regs(tp); 1464 1465 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1466 1467 if (!tp->dash_enabled) { 1468 rtl_set_d3_pll_down(tp, !wolopts); 1469 tp->dev->wol_enabled = wolopts ? 1 : 0; 1470 } 1471 } 1472 1473 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1474 { 1475 struct rtl8169_private *tp = netdev_priv(dev); 1476 1477 if (wol->wolopts & ~WAKE_ANY) 1478 return -EINVAL; 1479 1480 tp->saved_wolopts = wol->wolopts; 1481 __rtl8169_set_wol(tp, tp->saved_wolopts); 1482 1483 return 0; 1484 } 1485 1486 static void rtl8169_get_drvinfo(struct net_device *dev, 1487 struct ethtool_drvinfo *info) 1488 { 1489 struct rtl8169_private *tp = netdev_priv(dev); 1490 struct rtl_fw *rtl_fw = tp->rtl_fw; 1491 1492 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1493 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1494 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1495 if (rtl_fw) 1496 strscpy(info->fw_version, rtl_fw->version, 1497 sizeof(info->fw_version)); 1498 } 1499 1500 static int rtl8169_get_regs_len(struct net_device *dev) 1501 { 1502 return R8169_REGS_SIZE; 1503 } 1504 1505 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1506 netdev_features_t features) 1507 { 1508 struct rtl8169_private *tp = netdev_priv(dev); 1509 1510 if (dev->mtu > TD_MSS_MAX) 1511 features &= ~NETIF_F_ALL_TSO; 1512 1513 if (dev->mtu > ETH_DATA_LEN && 1514 tp->mac_version > RTL_GIGA_MAC_VER_06) 1515 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1516 1517 return features; 1518 } 1519 1520 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1521 netdev_features_t features) 1522 { 1523 u32 rx_config = RTL_R32(tp, RxConfig); 1524 1525 if (features & NETIF_F_RXALL) 1526 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1527 else 1528 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1529 1530 if (rtl_is_8125(tp)) { 1531 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1532 rx_config |= RX_VLAN_8125; 1533 else 1534 rx_config &= ~RX_VLAN_8125; 1535 } 1536 1537 RTL_W32(tp, RxConfig, rx_config); 1538 } 1539 1540 static int rtl8169_set_features(struct net_device *dev, 1541 netdev_features_t features) 1542 { 1543 struct rtl8169_private *tp = netdev_priv(dev); 1544 1545 rtl_set_rx_config_features(tp, features); 1546 1547 if (features & NETIF_F_RXCSUM) 1548 tp->cp_cmd |= RxChkSum; 1549 else 1550 tp->cp_cmd &= ~RxChkSum; 1551 1552 if (!rtl_is_8125(tp)) { 1553 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1554 tp->cp_cmd |= RxVlan; 1555 else 1556 tp->cp_cmd &= ~RxVlan; 1557 } 1558 1559 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1560 rtl_pci_commit(tp); 1561 1562 return 0; 1563 } 1564 1565 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1566 { 1567 return (skb_vlan_tag_present(skb)) ? 1568 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1569 } 1570 1571 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1572 { 1573 u32 opts2 = le32_to_cpu(desc->opts2); 1574 1575 if (opts2 & RxVlanTag) 1576 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1577 } 1578 1579 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1580 void *p) 1581 { 1582 struct rtl8169_private *tp = netdev_priv(dev); 1583 u32 __iomem *data = tp->mmio_addr; 1584 u32 *dw = p; 1585 int i; 1586 1587 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1588 memcpy_fromio(dw++, data++, 4); 1589 } 1590 1591 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1592 "tx_packets", 1593 "rx_packets", 1594 "tx_errors", 1595 "rx_errors", 1596 "rx_missed", 1597 "align_errors", 1598 "tx_single_collisions", 1599 "tx_multi_collisions", 1600 "unicast", 1601 "broadcast", 1602 "multicast", 1603 "tx_aborted", 1604 "tx_underrun", 1605 }; 1606 1607 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1608 { 1609 switch (sset) { 1610 case ETH_SS_STATS: 1611 return ARRAY_SIZE(rtl8169_gstrings); 1612 default: 1613 return -EOPNOTSUPP; 1614 } 1615 } 1616 1617 DECLARE_RTL_COND(rtl_counters_cond) 1618 { 1619 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1620 } 1621 1622 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1623 { 1624 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1625 1626 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1627 rtl_pci_commit(tp); 1628 RTL_W32(tp, CounterAddrLow, cmd); 1629 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1630 1631 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1632 } 1633 1634 static void rtl8169_update_counters(struct rtl8169_private *tp) 1635 { 1636 u8 val = RTL_R8(tp, ChipCmd); 1637 1638 /* 1639 * Some chips are unable to dump tally counters when the receiver 1640 * is disabled. If 0xff chip may be in a PCI power-save state. 1641 */ 1642 if (val & CmdRxEnb && val != 0xff) 1643 rtl8169_do_counters(tp, CounterDump); 1644 } 1645 1646 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1647 { 1648 struct rtl8169_counters *counters = tp->counters; 1649 1650 /* 1651 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1652 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1653 * reset by a power cycle, while the counter values collected by the 1654 * driver are reset at every driver unload/load cycle. 1655 * 1656 * To make sure the HW values returned by @get_stats64 match the SW 1657 * values, we collect the initial values at first open(*) and use them 1658 * as offsets to normalize the values returned by @get_stats64. 1659 * 1660 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1661 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1662 * set at open time by rtl_hw_start. 1663 */ 1664 1665 if (tp->tc_offset.inited) 1666 return; 1667 1668 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1669 rtl8169_do_counters(tp, CounterReset); 1670 } else { 1671 rtl8169_update_counters(tp); 1672 tp->tc_offset.tx_errors = counters->tx_errors; 1673 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1674 tp->tc_offset.tx_aborted = counters->tx_aborted; 1675 tp->tc_offset.rx_missed = counters->rx_missed; 1676 } 1677 1678 tp->tc_offset.inited = true; 1679 } 1680 1681 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1682 struct ethtool_stats *stats, u64 *data) 1683 { 1684 struct rtl8169_private *tp = netdev_priv(dev); 1685 struct rtl8169_counters *counters; 1686 1687 counters = tp->counters; 1688 rtl8169_update_counters(tp); 1689 1690 data[0] = le64_to_cpu(counters->tx_packets); 1691 data[1] = le64_to_cpu(counters->rx_packets); 1692 data[2] = le64_to_cpu(counters->tx_errors); 1693 data[3] = le32_to_cpu(counters->rx_errors); 1694 data[4] = le16_to_cpu(counters->rx_missed); 1695 data[5] = le16_to_cpu(counters->align_errors); 1696 data[6] = le32_to_cpu(counters->tx_one_collision); 1697 data[7] = le32_to_cpu(counters->tx_multi_collision); 1698 data[8] = le64_to_cpu(counters->rx_unicast); 1699 data[9] = le64_to_cpu(counters->rx_broadcast); 1700 data[10] = le32_to_cpu(counters->rx_multicast); 1701 data[11] = le16_to_cpu(counters->tx_aborted); 1702 data[12] = le16_to_cpu(counters->tx_underun); 1703 } 1704 1705 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1706 { 1707 switch(stringset) { 1708 case ETH_SS_STATS: 1709 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1710 break; 1711 } 1712 } 1713 1714 /* 1715 * Interrupt coalescing 1716 * 1717 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1718 * > 8169, 8168 and 810x line of chipsets 1719 * 1720 * 8169, 8168, and 8136(810x) serial chipsets support it. 1721 * 1722 * > 2 - the Tx timer unit at gigabit speed 1723 * 1724 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1725 * (0xe0) bit 1 and bit 0. 1726 * 1727 * For 8169 1728 * bit[1:0] \ speed 1000M 100M 10M 1729 * 0 0 320ns 2.56us 40.96us 1730 * 0 1 2.56us 20.48us 327.7us 1731 * 1 0 5.12us 40.96us 655.4us 1732 * 1 1 10.24us 81.92us 1.31ms 1733 * 1734 * For the other 1735 * bit[1:0] \ speed 1000M 100M 10M 1736 * 0 0 5us 2.56us 40.96us 1737 * 0 1 40us 20.48us 327.7us 1738 * 1 0 80us 40.96us 655.4us 1739 * 1 1 160us 81.92us 1.31ms 1740 */ 1741 1742 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1743 struct rtl_coalesce_info { 1744 u32 speed; 1745 u32 scale_nsecs[4]; 1746 }; 1747 1748 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1749 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1750 1751 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1752 { SPEED_1000, COALESCE_DELAY(320) }, 1753 { SPEED_100, COALESCE_DELAY(2560) }, 1754 { SPEED_10, COALESCE_DELAY(40960) }, 1755 { 0 }, 1756 }; 1757 1758 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1759 { SPEED_1000, COALESCE_DELAY(5000) }, 1760 { SPEED_100, COALESCE_DELAY(2560) }, 1761 { SPEED_10, COALESCE_DELAY(40960) }, 1762 { 0 }, 1763 }; 1764 #undef COALESCE_DELAY 1765 1766 /* get rx/tx scale vector corresponding to current speed */ 1767 static const struct rtl_coalesce_info * 1768 rtl_coalesce_info(struct rtl8169_private *tp) 1769 { 1770 const struct rtl_coalesce_info *ci; 1771 1772 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1773 ci = rtl_coalesce_info_8169; 1774 else 1775 ci = rtl_coalesce_info_8168_8136; 1776 1777 /* if speed is unknown assume highest one */ 1778 if (tp->phydev->speed == SPEED_UNKNOWN) 1779 return ci; 1780 1781 for (; ci->speed; ci++) { 1782 if (tp->phydev->speed == ci->speed) 1783 return ci; 1784 } 1785 1786 return ERR_PTR(-ELNRNG); 1787 } 1788 1789 static int rtl_get_coalesce(struct net_device *dev, 1790 struct ethtool_coalesce *ec, 1791 struct kernel_ethtool_coalesce *kernel_coal, 1792 struct netlink_ext_ack *extack) 1793 { 1794 struct rtl8169_private *tp = netdev_priv(dev); 1795 const struct rtl_coalesce_info *ci; 1796 u32 scale, c_us, c_fr; 1797 u16 intrmit; 1798 1799 if (rtl_is_8125(tp)) 1800 return -EOPNOTSUPP; 1801 1802 memset(ec, 0, sizeof(*ec)); 1803 1804 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1805 ci = rtl_coalesce_info(tp); 1806 if (IS_ERR(ci)) 1807 return PTR_ERR(ci); 1808 1809 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1810 1811 intrmit = RTL_R16(tp, IntrMitigate); 1812 1813 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1814 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1815 1816 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1817 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1818 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1819 1820 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1821 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1822 1823 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1824 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1825 1826 return 0; 1827 } 1828 1829 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1830 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1831 u16 *cp01) 1832 { 1833 const struct rtl_coalesce_info *ci; 1834 u16 i; 1835 1836 ci = rtl_coalesce_info(tp); 1837 if (IS_ERR(ci)) 1838 return PTR_ERR(ci); 1839 1840 for (i = 0; i < 4; i++) { 1841 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1842 *cp01 = i; 1843 return ci->scale_nsecs[i]; 1844 } 1845 } 1846 1847 return -ERANGE; 1848 } 1849 1850 static int rtl_set_coalesce(struct net_device *dev, 1851 struct ethtool_coalesce *ec, 1852 struct kernel_ethtool_coalesce *kernel_coal, 1853 struct netlink_ext_ack *extack) 1854 { 1855 struct rtl8169_private *tp = netdev_priv(dev); 1856 u32 tx_fr = ec->tx_max_coalesced_frames; 1857 u32 rx_fr = ec->rx_max_coalesced_frames; 1858 u32 coal_usec_max, units; 1859 u16 w = 0, cp01 = 0; 1860 int scale; 1861 1862 if (rtl_is_8125(tp)) 1863 return -EOPNOTSUPP; 1864 1865 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1866 return -ERANGE; 1867 1868 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1869 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1870 if (scale < 0) 1871 return scale; 1872 1873 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1874 * not only when usecs=0 because of e.g. the following scenario: 1875 * 1876 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1877 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1878 * - then user does `ethtool -C eth0 rx-usecs 100` 1879 * 1880 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1881 * if we want to ignore rx_frames then it has to be set to 0. 1882 */ 1883 if (rx_fr == 1) 1884 rx_fr = 0; 1885 if (tx_fr == 1) 1886 tx_fr = 0; 1887 1888 /* HW requires time limit to be set if frame limit is set */ 1889 if ((tx_fr && !ec->tx_coalesce_usecs) || 1890 (rx_fr && !ec->rx_coalesce_usecs)) 1891 return -EINVAL; 1892 1893 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1894 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1895 1896 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1897 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1898 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1899 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1900 1901 RTL_W16(tp, IntrMitigate, w); 1902 1903 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1904 if (rtl_is_8168evl_up(tp)) { 1905 if (!rx_fr && !tx_fr) 1906 /* disable packet counter */ 1907 tp->cp_cmd |= PktCntrDisable; 1908 else 1909 tp->cp_cmd &= ~PktCntrDisable; 1910 } 1911 1912 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1913 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1914 rtl_pci_commit(tp); 1915 1916 return 0; 1917 } 1918 1919 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1920 { 1921 struct rtl8169_private *tp = netdev_priv(dev); 1922 1923 if (!rtl_supports_eee(tp)) 1924 return -EOPNOTSUPP; 1925 1926 return phy_ethtool_get_eee(tp->phydev, data); 1927 } 1928 1929 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1930 { 1931 struct rtl8169_private *tp = netdev_priv(dev); 1932 int ret; 1933 1934 if (!rtl_supports_eee(tp)) 1935 return -EOPNOTSUPP; 1936 1937 ret = phy_ethtool_set_eee(tp->phydev, data); 1938 1939 if (!ret) 1940 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1941 MDIO_AN_EEE_ADV); 1942 return ret; 1943 } 1944 1945 static void rtl8169_get_ringparam(struct net_device *dev, 1946 struct ethtool_ringparam *data, 1947 struct kernel_ethtool_ringparam *kernel_data, 1948 struct netlink_ext_ack *extack) 1949 { 1950 data->rx_max_pending = NUM_RX_DESC; 1951 data->rx_pending = NUM_RX_DESC; 1952 data->tx_max_pending = NUM_TX_DESC; 1953 data->tx_pending = NUM_TX_DESC; 1954 } 1955 1956 static void rtl8169_get_pauseparam(struct net_device *dev, 1957 struct ethtool_pauseparam *data) 1958 { 1959 struct rtl8169_private *tp = netdev_priv(dev); 1960 bool tx_pause, rx_pause; 1961 1962 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1963 1964 data->autoneg = tp->phydev->autoneg; 1965 data->tx_pause = tx_pause ? 1 : 0; 1966 data->rx_pause = rx_pause ? 1 : 0; 1967 } 1968 1969 static int rtl8169_set_pauseparam(struct net_device *dev, 1970 struct ethtool_pauseparam *data) 1971 { 1972 struct rtl8169_private *tp = netdev_priv(dev); 1973 1974 if (dev->mtu > ETH_DATA_LEN) 1975 return -EOPNOTSUPP; 1976 1977 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1978 1979 return 0; 1980 } 1981 1982 static const struct ethtool_ops rtl8169_ethtool_ops = { 1983 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1984 ETHTOOL_COALESCE_MAX_FRAMES, 1985 .get_drvinfo = rtl8169_get_drvinfo, 1986 .get_regs_len = rtl8169_get_regs_len, 1987 .get_link = ethtool_op_get_link, 1988 .get_coalesce = rtl_get_coalesce, 1989 .set_coalesce = rtl_set_coalesce, 1990 .get_regs = rtl8169_get_regs, 1991 .get_wol = rtl8169_get_wol, 1992 .set_wol = rtl8169_set_wol, 1993 .get_strings = rtl8169_get_strings, 1994 .get_sset_count = rtl8169_get_sset_count, 1995 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1996 .get_ts_info = ethtool_op_get_ts_info, 1997 .nway_reset = phy_ethtool_nway_reset, 1998 .get_eee = rtl8169_get_eee, 1999 .set_eee = rtl8169_set_eee, 2000 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2001 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2002 .get_ringparam = rtl8169_get_ringparam, 2003 .get_pauseparam = rtl8169_get_pauseparam, 2004 .set_pauseparam = rtl8169_set_pauseparam, 2005 }; 2006 2007 static void rtl_enable_eee(struct rtl8169_private *tp) 2008 { 2009 struct phy_device *phydev = tp->phydev; 2010 int adv; 2011 2012 /* respect EEE advertisement the user may have set */ 2013 if (tp->eee_adv >= 0) 2014 adv = tp->eee_adv; 2015 else 2016 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2017 2018 if (adv >= 0) 2019 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2020 } 2021 2022 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2023 { 2024 /* 2025 * The driver currently handles the 8168Bf and the 8168Be identically 2026 * but they can be identified more specifically through the test below 2027 * if needed: 2028 * 2029 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2030 * 2031 * Same thing for the 8101Eb and the 8101Ec: 2032 * 2033 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2034 */ 2035 static const struct rtl_mac_info { 2036 u16 mask; 2037 u16 val; 2038 enum mac_version ver; 2039 } mac_info[] = { 2040 /* 8125B family. */ 2041 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2042 2043 /* 8125A family. */ 2044 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2045 /* It seems only XID 609 made it to the mass market. 2046 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2047 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2048 */ 2049 2050 /* RTL8117 */ 2051 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2052 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2053 2054 /* 8168EP family. */ 2055 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2056 /* It seems this chip version never made it to 2057 * the wild. Let's disable detection. 2058 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2059 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2060 */ 2061 2062 /* 8168H family. */ 2063 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2064 /* It seems this chip version never made it to 2065 * the wild. Let's disable detection. 2066 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2067 */ 2068 2069 /* 8168G family. */ 2070 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2071 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2072 /* It seems this chip version never made it to 2073 * the wild. Let's disable detection. 2074 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2075 */ 2076 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2077 2078 /* 8168F family. */ 2079 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2080 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2081 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2082 2083 /* 8168E family. */ 2084 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2085 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2086 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2087 2088 /* 8168D family. */ 2089 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2090 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2091 2092 /* 8168DP family. */ 2093 /* It seems this early RTL8168dp version never made it to 2094 * the wild. Support has been removed. 2095 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2096 */ 2097 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2098 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2099 2100 /* 8168C family. */ 2101 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2102 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2103 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2104 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2105 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2106 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2107 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2108 2109 /* 8168B family. */ 2110 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2111 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2112 2113 /* 8101 family. */ 2114 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2115 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2116 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2117 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2118 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2119 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2120 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2121 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2122 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2123 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2124 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2125 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2126 2127 /* 8110 family. */ 2128 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2129 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2130 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2131 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2132 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2133 2134 /* Catch-all */ 2135 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2136 }; 2137 const struct rtl_mac_info *p = mac_info; 2138 enum mac_version ver; 2139 2140 while ((xid & p->mask) != p->val) 2141 p++; 2142 ver = p->ver; 2143 2144 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2145 if (ver == RTL_GIGA_MAC_VER_42) 2146 ver = RTL_GIGA_MAC_VER_43; 2147 else if (ver == RTL_GIGA_MAC_VER_46) 2148 ver = RTL_GIGA_MAC_VER_48; 2149 } 2150 2151 return ver; 2152 } 2153 2154 static void rtl_release_firmware(struct rtl8169_private *tp) 2155 { 2156 if (tp->rtl_fw) { 2157 rtl_fw_release_firmware(tp->rtl_fw); 2158 kfree(tp->rtl_fw); 2159 tp->rtl_fw = NULL; 2160 } 2161 } 2162 2163 void r8169_apply_firmware(struct rtl8169_private *tp) 2164 { 2165 int val; 2166 2167 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2168 if (tp->rtl_fw) { 2169 rtl_fw_write_firmware(tp, tp->rtl_fw); 2170 /* At least one firmware doesn't reset tp->ocp_base. */ 2171 tp->ocp_base = OCP_STD_PHY_BASE; 2172 2173 /* PHY soft reset may still be in progress */ 2174 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2175 !(val & BMCR_RESET), 2176 50000, 600000, true); 2177 } 2178 } 2179 2180 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2181 { 2182 /* Adjust EEE LED frequency */ 2183 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2184 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2185 2186 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2187 } 2188 2189 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2190 { 2191 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2192 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2193 } 2194 2195 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2196 { 2197 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2198 } 2199 2200 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2201 { 2202 rtl8125_set_eee_txidle_timer(tp); 2203 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2204 } 2205 2206 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2207 { 2208 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2209 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2210 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2211 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2212 } 2213 2214 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2215 { 2216 u16 data1, data2, ioffset; 2217 2218 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2219 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2220 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2221 2222 ioffset = (data2 >> 1) & 0x7ff8; 2223 ioffset |= data2 & 0x0007; 2224 if (data1 & BIT(7)) 2225 ioffset |= BIT(15); 2226 2227 return ioffset; 2228 } 2229 2230 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2231 { 2232 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 2233 return; 2234 2235 set_bit(flag, tp->wk.flags); 2236 schedule_work(&tp->wk.work); 2237 } 2238 2239 static void rtl8169_init_phy(struct rtl8169_private *tp) 2240 { 2241 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2242 2243 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2244 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2245 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2246 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2247 RTL_W8(tp, 0x82, 0x01); 2248 } 2249 2250 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2251 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2252 tp->pci_dev->subsystem_device == 0xe000) 2253 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2254 2255 /* We may have called phy_speed_down before */ 2256 phy_speed_up(tp->phydev); 2257 2258 if (rtl_supports_eee(tp)) 2259 rtl_enable_eee(tp); 2260 2261 genphy_soft_reset(tp->phydev); 2262 } 2263 2264 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2265 { 2266 rtl_unlock_config_regs(tp); 2267 2268 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2269 rtl_pci_commit(tp); 2270 2271 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2272 rtl_pci_commit(tp); 2273 2274 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2275 rtl_rar_exgmac_set(tp, addr); 2276 2277 rtl_lock_config_regs(tp); 2278 } 2279 2280 static int rtl_set_mac_address(struct net_device *dev, void *p) 2281 { 2282 struct rtl8169_private *tp = netdev_priv(dev); 2283 int ret; 2284 2285 ret = eth_mac_addr(dev, p); 2286 if (ret) 2287 return ret; 2288 2289 rtl_rar_set(tp, dev->dev_addr); 2290 2291 return 0; 2292 } 2293 2294 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2295 { 2296 switch (tp->mac_version) { 2297 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2298 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2299 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2300 break; 2301 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2302 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2303 case RTL_GIGA_MAC_VER_38: 2304 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2305 break; 2306 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2307 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2308 break; 2309 case RTL_GIGA_MAC_VER_61: 2310 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2311 break; 2312 case RTL_GIGA_MAC_VER_63: 2313 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2314 RX_PAUSE_SLOT_ON); 2315 break; 2316 default: 2317 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2318 break; 2319 } 2320 } 2321 2322 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2323 { 2324 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2325 } 2326 2327 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2328 { 2329 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2330 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2331 } 2332 2333 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2334 { 2335 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2336 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2337 } 2338 2339 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2340 { 2341 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2342 } 2343 2344 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2345 { 2346 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2347 } 2348 2349 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2350 { 2351 RTL_W8(tp, MaxTxPacketSize, 0x24); 2352 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2353 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2354 } 2355 2356 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2357 { 2358 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2359 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2360 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2361 } 2362 2363 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2364 { 2365 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2366 } 2367 2368 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2369 { 2370 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2371 } 2372 2373 static void rtl_jumbo_config(struct rtl8169_private *tp) 2374 { 2375 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2376 int readrq = 4096; 2377 2378 rtl_unlock_config_regs(tp); 2379 switch (tp->mac_version) { 2380 case RTL_GIGA_MAC_VER_17: 2381 if (jumbo) { 2382 readrq = 512; 2383 r8168b_1_hw_jumbo_enable(tp); 2384 } else { 2385 r8168b_1_hw_jumbo_disable(tp); 2386 } 2387 break; 2388 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2389 if (jumbo) { 2390 readrq = 512; 2391 r8168c_hw_jumbo_enable(tp); 2392 } else { 2393 r8168c_hw_jumbo_disable(tp); 2394 } 2395 break; 2396 case RTL_GIGA_MAC_VER_28: 2397 if (jumbo) 2398 r8168dp_hw_jumbo_enable(tp); 2399 else 2400 r8168dp_hw_jumbo_disable(tp); 2401 break; 2402 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2403 if (jumbo) 2404 r8168e_hw_jumbo_enable(tp); 2405 else 2406 r8168e_hw_jumbo_disable(tp); 2407 break; 2408 default: 2409 break; 2410 } 2411 rtl_lock_config_regs(tp); 2412 2413 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2414 pcie_set_readrq(tp->pci_dev, readrq); 2415 2416 /* Chip doesn't support pause in jumbo mode */ 2417 if (jumbo) { 2418 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2419 tp->phydev->advertising); 2420 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2421 tp->phydev->advertising); 2422 phy_start_aneg(tp->phydev); 2423 } 2424 } 2425 2426 DECLARE_RTL_COND(rtl_chipcmd_cond) 2427 { 2428 return RTL_R8(tp, ChipCmd) & CmdReset; 2429 } 2430 2431 static void rtl_hw_reset(struct rtl8169_private *tp) 2432 { 2433 RTL_W8(tp, ChipCmd, CmdReset); 2434 2435 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2436 } 2437 2438 static void rtl_request_firmware(struct rtl8169_private *tp) 2439 { 2440 struct rtl_fw *rtl_fw; 2441 2442 /* firmware loaded already or no firmware available */ 2443 if (tp->rtl_fw || !tp->fw_name) 2444 return; 2445 2446 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2447 if (!rtl_fw) 2448 return; 2449 2450 rtl_fw->phy_write = rtl_writephy; 2451 rtl_fw->phy_read = rtl_readphy; 2452 rtl_fw->mac_mcu_write = mac_mcu_write; 2453 rtl_fw->mac_mcu_read = mac_mcu_read; 2454 rtl_fw->fw_name = tp->fw_name; 2455 rtl_fw->dev = tp_to_dev(tp); 2456 2457 if (rtl_fw_request_firmware(rtl_fw)) 2458 kfree(rtl_fw); 2459 else 2460 tp->rtl_fw = rtl_fw; 2461 } 2462 2463 static void rtl_rx_close(struct rtl8169_private *tp) 2464 { 2465 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2466 } 2467 2468 DECLARE_RTL_COND(rtl_npq_cond) 2469 { 2470 return RTL_R8(tp, TxPoll) & NPQ; 2471 } 2472 2473 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2474 { 2475 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2476 } 2477 2478 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2479 { 2480 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2481 } 2482 2483 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2484 { 2485 /* IntrMitigate has new functionality on RTL8125 */ 2486 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2487 } 2488 2489 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2490 { 2491 switch (tp->mac_version) { 2492 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2493 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2494 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2495 break; 2496 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2497 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2498 break; 2499 case RTL_GIGA_MAC_VER_63: 2500 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2501 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2502 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2503 break; 2504 default: 2505 break; 2506 } 2507 } 2508 2509 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2510 { 2511 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2512 } 2513 2514 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2515 { 2516 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2517 fsleep(2000); 2518 rtl_wait_txrx_fifo_empty(tp); 2519 } 2520 2521 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2522 { 2523 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2524 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2525 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2526 2527 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2528 rtl_disable_rxdvgate(tp); 2529 } 2530 2531 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2532 { 2533 if (tp->dash_enabled) 2534 return; 2535 2536 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2537 tp->mac_version == RTL_GIGA_MAC_VER_33) 2538 rtl_ephy_write(tp, 0x19, 0xff64); 2539 2540 if (device_may_wakeup(tp_to_dev(tp))) { 2541 phy_speed_down(tp->phydev, false); 2542 rtl_wol_enable_rx(tp); 2543 } 2544 } 2545 2546 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2547 { 2548 u32 val = TX_DMA_BURST << TxDMAShift | 2549 InterFrameGap << TxInterFrameGapShift; 2550 2551 if (rtl_is_8168evl_up(tp)) 2552 val |= TXCFG_AUTO_FIFO; 2553 2554 RTL_W32(tp, TxConfig, val); 2555 } 2556 2557 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2558 { 2559 /* Low hurts. Let's disable the filtering. */ 2560 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2561 } 2562 2563 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2564 { 2565 /* 2566 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2567 * register to be written before TxDescAddrLow to work. 2568 * Switching from MMIO to I/O access fixes the issue as well. 2569 */ 2570 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2571 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2572 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2573 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2574 } 2575 2576 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2577 { 2578 u32 val; 2579 2580 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2581 val = 0x000fff00; 2582 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2583 val = 0x00ffff00; 2584 else 2585 return; 2586 2587 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2588 val |= 0xff; 2589 2590 RTL_W32(tp, 0x7c, val); 2591 } 2592 2593 static void rtl_set_rx_mode(struct net_device *dev) 2594 { 2595 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2596 /* Multicast hash filter */ 2597 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2598 struct rtl8169_private *tp = netdev_priv(dev); 2599 u32 tmp; 2600 2601 if (dev->flags & IFF_PROMISC) { 2602 rx_mode |= AcceptAllPhys; 2603 } else if (!(dev->flags & IFF_MULTICAST)) { 2604 rx_mode &= ~AcceptMulticast; 2605 } else if (dev->flags & IFF_ALLMULTI || 2606 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2607 /* accept all multicasts */ 2608 } else if (netdev_mc_empty(dev)) { 2609 rx_mode &= ~AcceptMulticast; 2610 } else { 2611 struct netdev_hw_addr *ha; 2612 2613 mc_filter[1] = mc_filter[0] = 0; 2614 netdev_for_each_mc_addr(ha, dev) { 2615 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2616 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2617 } 2618 2619 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2620 tmp = mc_filter[0]; 2621 mc_filter[0] = swab32(mc_filter[1]); 2622 mc_filter[1] = swab32(tmp); 2623 } 2624 } 2625 2626 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2627 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2628 2629 tmp = RTL_R32(tp, RxConfig); 2630 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2631 } 2632 2633 DECLARE_RTL_COND(rtl_csiar_cond) 2634 { 2635 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2636 } 2637 2638 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2639 { 2640 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2641 2642 RTL_W32(tp, CSIDR, value); 2643 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2644 CSIAR_BYTE_ENABLE | func << 16); 2645 2646 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2647 } 2648 2649 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2650 { 2651 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2652 2653 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2654 CSIAR_BYTE_ENABLE); 2655 2656 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2657 RTL_R32(tp, CSIDR) : ~0; 2658 } 2659 2660 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2661 { 2662 struct pci_dev *pdev = tp->pci_dev; 2663 u32 csi; 2664 2665 /* According to Realtek the value at config space address 0x070f 2666 * controls the L0s/L1 entrance latency. We try standard ECAM access 2667 * first and if it fails fall back to CSI. 2668 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2669 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2670 */ 2671 if (pdev->cfg_size > 0x070f && 2672 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2673 return; 2674 2675 netdev_notice_once(tp->dev, 2676 "No native access to PCI extended config space, falling back to CSI\n"); 2677 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2678 rtl_csi_write(tp, 0x070c, csi | val << 24); 2679 } 2680 2681 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2682 { 2683 /* L0 7us, L1 16us */ 2684 rtl_set_aspm_entry_latency(tp, 0x27); 2685 } 2686 2687 struct ephy_info { 2688 unsigned int offset; 2689 u16 mask; 2690 u16 bits; 2691 }; 2692 2693 static void __rtl_ephy_init(struct rtl8169_private *tp, 2694 const struct ephy_info *e, int len) 2695 { 2696 u16 w; 2697 2698 while (len-- > 0) { 2699 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2700 rtl_ephy_write(tp, e->offset, w); 2701 e++; 2702 } 2703 } 2704 2705 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2706 2707 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2708 { 2709 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2710 PCI_EXP_LNKCTL_CLKREQ_EN); 2711 } 2712 2713 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2714 { 2715 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2716 PCI_EXP_LNKCTL_CLKREQ_EN); 2717 } 2718 2719 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2720 { 2721 /* work around an issue when PCI reset occurs during L2/L3 state */ 2722 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2723 } 2724 2725 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2726 { 2727 /* Bits control which events trigger ASPM L1 exit: 2728 * Bit 12: rxdv 2729 * Bit 11: ltr_msg 2730 * Bit 10: txdma_poll 2731 * Bit 9: xadm 2732 * Bit 8: pktavi 2733 * Bit 7: txpla 2734 */ 2735 switch (tp->mac_version) { 2736 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2737 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2738 break; 2739 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2740 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2741 break; 2742 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2743 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2744 break; 2745 default: 2746 break; 2747 } 2748 } 2749 2750 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2751 { 2752 switch (tp->mac_version) { 2753 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2754 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2755 break; 2756 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2757 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2758 break; 2759 default: 2760 break; 2761 } 2762 } 2763 2764 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2765 { 2766 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2767 return; 2768 2769 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2770 if (enable && tp->aspm_manageable) { 2771 /* On these chip versions ASPM can even harm 2772 * bus communication of other PCI devices. 2773 */ 2774 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2775 tp->mac_version == RTL_GIGA_MAC_VER_43) 2776 return; 2777 2778 rtl_mod_config5(tp, 0, ASPM_en); 2779 rtl_mod_config2(tp, 0, ClkReqEn); 2780 2781 switch (tp->mac_version) { 2782 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2783 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2784 /* reset ephy tx/rx disable timer */ 2785 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2786 /* chip can trigger L1.2 */ 2787 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2788 break; 2789 default: 2790 break; 2791 } 2792 } else { 2793 switch (tp->mac_version) { 2794 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2795 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2796 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2797 break; 2798 default: 2799 break; 2800 } 2801 2802 rtl_mod_config2(tp, ClkReqEn, 0); 2803 rtl_mod_config5(tp, ASPM_en, 0); 2804 } 2805 } 2806 2807 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2808 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2809 { 2810 /* Usage of dynamic vs. static FIFO is controlled by bit 2811 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2812 */ 2813 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2814 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2815 } 2816 2817 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2818 u8 low, u8 high) 2819 { 2820 /* FIFO thresholds for pause flow control */ 2821 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2822 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2823 } 2824 2825 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2826 { 2827 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2828 } 2829 2830 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2831 { 2832 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2833 2834 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2835 2836 rtl_disable_clock_request(tp); 2837 } 2838 2839 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2840 { 2841 static const struct ephy_info e_info_8168cp[] = { 2842 { 0x01, 0, 0x0001 }, 2843 { 0x02, 0x0800, 0x1000 }, 2844 { 0x03, 0, 0x0042 }, 2845 { 0x06, 0x0080, 0x0000 }, 2846 { 0x07, 0, 0x2000 } 2847 }; 2848 2849 rtl_set_def_aspm_entry_latency(tp); 2850 2851 rtl_ephy_init(tp, e_info_8168cp); 2852 2853 __rtl_hw_start_8168cp(tp); 2854 } 2855 2856 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2857 { 2858 rtl_set_def_aspm_entry_latency(tp); 2859 2860 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2861 } 2862 2863 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2864 { 2865 rtl_set_def_aspm_entry_latency(tp); 2866 2867 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2868 2869 /* Magic. */ 2870 RTL_W8(tp, DBG_REG, 0x20); 2871 } 2872 2873 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2874 { 2875 static const struct ephy_info e_info_8168c_1[] = { 2876 { 0x02, 0x0800, 0x1000 }, 2877 { 0x03, 0, 0x0002 }, 2878 { 0x06, 0x0080, 0x0000 } 2879 }; 2880 2881 rtl_set_def_aspm_entry_latency(tp); 2882 2883 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2884 2885 rtl_ephy_init(tp, e_info_8168c_1); 2886 2887 __rtl_hw_start_8168cp(tp); 2888 } 2889 2890 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2891 { 2892 static const struct ephy_info e_info_8168c_2[] = { 2893 { 0x01, 0, 0x0001 }, 2894 { 0x03, 0x0400, 0x0020 } 2895 }; 2896 2897 rtl_set_def_aspm_entry_latency(tp); 2898 2899 rtl_ephy_init(tp, e_info_8168c_2); 2900 2901 __rtl_hw_start_8168cp(tp); 2902 } 2903 2904 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2905 { 2906 rtl_set_def_aspm_entry_latency(tp); 2907 2908 __rtl_hw_start_8168cp(tp); 2909 } 2910 2911 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2912 { 2913 rtl_set_def_aspm_entry_latency(tp); 2914 2915 rtl_disable_clock_request(tp); 2916 } 2917 2918 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2919 { 2920 static const struct ephy_info e_info_8168d_4[] = { 2921 { 0x0b, 0x0000, 0x0048 }, 2922 { 0x19, 0x0020, 0x0050 }, 2923 { 0x0c, 0x0100, 0x0020 }, 2924 { 0x10, 0x0004, 0x0000 }, 2925 }; 2926 2927 rtl_set_def_aspm_entry_latency(tp); 2928 2929 rtl_ephy_init(tp, e_info_8168d_4); 2930 2931 rtl_enable_clock_request(tp); 2932 } 2933 2934 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2935 { 2936 static const struct ephy_info e_info_8168e_1[] = { 2937 { 0x00, 0x0200, 0x0100 }, 2938 { 0x00, 0x0000, 0x0004 }, 2939 { 0x06, 0x0002, 0x0001 }, 2940 { 0x06, 0x0000, 0x0030 }, 2941 { 0x07, 0x0000, 0x2000 }, 2942 { 0x00, 0x0000, 0x0020 }, 2943 { 0x03, 0x5800, 0x2000 }, 2944 { 0x03, 0x0000, 0x0001 }, 2945 { 0x01, 0x0800, 0x1000 }, 2946 { 0x07, 0x0000, 0x4000 }, 2947 { 0x1e, 0x0000, 0x2000 }, 2948 { 0x19, 0xffff, 0xfe6c }, 2949 { 0x0a, 0x0000, 0x0040 } 2950 }; 2951 2952 rtl_set_def_aspm_entry_latency(tp); 2953 2954 rtl_ephy_init(tp, e_info_8168e_1); 2955 2956 rtl_disable_clock_request(tp); 2957 2958 /* Reset tx FIFO pointer */ 2959 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2960 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2961 2962 rtl_mod_config5(tp, Spi_en, 0); 2963 } 2964 2965 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2966 { 2967 static const struct ephy_info e_info_8168e_2[] = { 2968 { 0x09, 0x0000, 0x0080 }, 2969 { 0x19, 0x0000, 0x0224 }, 2970 { 0x00, 0x0000, 0x0004 }, 2971 { 0x0c, 0x3df0, 0x0200 }, 2972 }; 2973 2974 rtl_set_def_aspm_entry_latency(tp); 2975 2976 rtl_ephy_init(tp, e_info_8168e_2); 2977 2978 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2979 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2980 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2981 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2982 rtl_reset_packet_filter(tp); 2983 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2984 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2985 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2986 2987 rtl_disable_clock_request(tp); 2988 2989 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2990 2991 rtl8168_config_eee_mac(tp); 2992 2993 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2994 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2995 rtl_mod_config5(tp, Spi_en, 0); 2996 } 2997 2998 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2999 { 3000 rtl_set_def_aspm_entry_latency(tp); 3001 3002 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3003 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3004 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3005 rtl_reset_packet_filter(tp); 3006 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3007 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3008 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3009 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3010 3011 rtl_disable_clock_request(tp); 3012 3013 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3014 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3015 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3016 rtl_mod_config5(tp, Spi_en, 0); 3017 3018 rtl8168_config_eee_mac(tp); 3019 } 3020 3021 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3022 { 3023 static const struct ephy_info e_info_8168f_1[] = { 3024 { 0x06, 0x00c0, 0x0020 }, 3025 { 0x08, 0x0001, 0x0002 }, 3026 { 0x09, 0x0000, 0x0080 }, 3027 { 0x19, 0x0000, 0x0224 }, 3028 { 0x00, 0x0000, 0x0008 }, 3029 { 0x0c, 0x3df0, 0x0200 }, 3030 }; 3031 3032 rtl_hw_start_8168f(tp); 3033 3034 rtl_ephy_init(tp, e_info_8168f_1); 3035 } 3036 3037 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3038 { 3039 static const struct ephy_info e_info_8168f_1[] = { 3040 { 0x06, 0x00c0, 0x0020 }, 3041 { 0x0f, 0xffff, 0x5200 }, 3042 { 0x19, 0x0000, 0x0224 }, 3043 { 0x00, 0x0000, 0x0008 }, 3044 { 0x0c, 0x3df0, 0x0200 }, 3045 }; 3046 3047 rtl_hw_start_8168f(tp); 3048 rtl_pcie_state_l2l3_disable(tp); 3049 3050 rtl_ephy_init(tp, e_info_8168f_1); 3051 } 3052 3053 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3054 { 3055 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3056 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3057 3058 rtl_set_def_aspm_entry_latency(tp); 3059 3060 rtl_reset_packet_filter(tp); 3061 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3062 3063 rtl_disable_rxdvgate(tp); 3064 3065 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3066 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3067 3068 rtl8168_config_eee_mac(tp); 3069 3070 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3071 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3072 3073 rtl_pcie_state_l2l3_disable(tp); 3074 } 3075 3076 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3077 { 3078 static const struct ephy_info e_info_8168g_1[] = { 3079 { 0x00, 0x0008, 0x0000 }, 3080 { 0x0c, 0x3ff0, 0x0820 }, 3081 { 0x1e, 0x0000, 0x0001 }, 3082 { 0x19, 0x8000, 0x0000 } 3083 }; 3084 3085 rtl_hw_start_8168g(tp); 3086 rtl_ephy_init(tp, e_info_8168g_1); 3087 } 3088 3089 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3090 { 3091 static const struct ephy_info e_info_8168g_2[] = { 3092 { 0x00, 0x0008, 0x0000 }, 3093 { 0x0c, 0x3ff0, 0x0820 }, 3094 { 0x19, 0xffff, 0x7c00 }, 3095 { 0x1e, 0xffff, 0x20eb }, 3096 { 0x0d, 0xffff, 0x1666 }, 3097 { 0x00, 0xffff, 0x10a3 }, 3098 { 0x06, 0xffff, 0xf050 }, 3099 { 0x04, 0x0000, 0x0010 }, 3100 { 0x1d, 0x4000, 0x0000 }, 3101 }; 3102 3103 rtl_hw_start_8168g(tp); 3104 rtl_ephy_init(tp, e_info_8168g_2); 3105 } 3106 3107 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3108 { 3109 static const u16 fix_data[] = { 3110 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3111 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3112 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3113 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3114 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3115 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3116 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3117 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3118 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3119 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3120 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3121 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3122 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3123 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3124 }; 3125 unsigned long flags; 3126 int i; 3127 3128 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3129 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3130 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3131 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3132 } 3133 3134 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3135 { 3136 static const struct ephy_info e_info_8411_2[] = { 3137 { 0x00, 0x0008, 0x0000 }, 3138 { 0x0c, 0x37d0, 0x0820 }, 3139 { 0x1e, 0x0000, 0x0001 }, 3140 { 0x19, 0x8021, 0x0000 }, 3141 { 0x1e, 0x0000, 0x2000 }, 3142 { 0x0d, 0x0100, 0x0200 }, 3143 { 0x00, 0x0000, 0x0080 }, 3144 { 0x06, 0x0000, 0x0010 }, 3145 { 0x04, 0x0000, 0x0010 }, 3146 { 0x1d, 0x0000, 0x4000 }, 3147 }; 3148 3149 rtl_hw_start_8168g(tp); 3150 3151 rtl_ephy_init(tp, e_info_8411_2); 3152 3153 /* The following Realtek-provided magic fixes an issue with the RX unit 3154 * getting confused after the PHY having been powered-down. 3155 */ 3156 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3157 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3158 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3159 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3160 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3161 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3162 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3163 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3164 mdelay(3); 3165 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3166 3167 rtl8411b_fix_phy_down(tp); 3168 3169 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3170 3171 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3172 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3173 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3174 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3175 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3176 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3177 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3178 } 3179 3180 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3181 { 3182 static const struct ephy_info e_info_8168h_1[] = { 3183 { 0x1e, 0x0800, 0x0001 }, 3184 { 0x1d, 0x0000, 0x0800 }, 3185 { 0x05, 0xffff, 0x2089 }, 3186 { 0x06, 0xffff, 0x5881 }, 3187 { 0x04, 0xffff, 0x854a }, 3188 { 0x01, 0xffff, 0x068b } 3189 }; 3190 int rg_saw_cnt; 3191 3192 rtl_ephy_init(tp, e_info_8168h_1); 3193 3194 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3195 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3196 3197 rtl_set_def_aspm_entry_latency(tp); 3198 3199 rtl_reset_packet_filter(tp); 3200 3201 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3202 3203 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3204 3205 rtl_disable_rxdvgate(tp); 3206 3207 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3208 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3209 3210 rtl8168_config_eee_mac(tp); 3211 3212 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3213 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3214 3215 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3216 3217 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3218 3219 rtl_pcie_state_l2l3_disable(tp); 3220 3221 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3222 if (rg_saw_cnt > 0) { 3223 u16 sw_cnt_1ms_ini; 3224 3225 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3226 sw_cnt_1ms_ini &= 0x0fff; 3227 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3228 } 3229 3230 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3231 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3232 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3233 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3234 3235 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3236 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3237 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3238 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3239 } 3240 3241 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3242 { 3243 rtl8168ep_stop_cmac(tp); 3244 3245 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3246 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3247 3248 rtl_set_def_aspm_entry_latency(tp); 3249 3250 rtl_reset_packet_filter(tp); 3251 3252 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3253 3254 rtl_disable_rxdvgate(tp); 3255 3256 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3257 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3258 3259 rtl8168_config_eee_mac(tp); 3260 3261 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3262 3263 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3264 3265 rtl_pcie_state_l2l3_disable(tp); 3266 } 3267 3268 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3269 { 3270 static const struct ephy_info e_info_8168ep_3[] = { 3271 { 0x00, 0x0000, 0x0080 }, 3272 { 0x0d, 0x0100, 0x0200 }, 3273 { 0x19, 0x8021, 0x0000 }, 3274 { 0x1e, 0x0000, 0x2000 }, 3275 }; 3276 3277 rtl_ephy_init(tp, e_info_8168ep_3); 3278 3279 rtl_hw_start_8168ep(tp); 3280 3281 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3282 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3283 3284 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3285 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3286 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3287 } 3288 3289 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3290 { 3291 static const struct ephy_info e_info_8117[] = { 3292 { 0x19, 0x0040, 0x1100 }, 3293 { 0x59, 0x0040, 0x1100 }, 3294 }; 3295 int rg_saw_cnt; 3296 3297 rtl8168ep_stop_cmac(tp); 3298 rtl_ephy_init(tp, e_info_8117); 3299 3300 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3301 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3302 3303 rtl_set_def_aspm_entry_latency(tp); 3304 3305 rtl_reset_packet_filter(tp); 3306 3307 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3308 3309 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3310 3311 rtl_disable_rxdvgate(tp); 3312 3313 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3314 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3315 3316 rtl8168_config_eee_mac(tp); 3317 3318 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3319 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3320 3321 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3322 3323 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3324 3325 rtl_pcie_state_l2l3_disable(tp); 3326 3327 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3328 if (rg_saw_cnt > 0) { 3329 u16 sw_cnt_1ms_ini; 3330 3331 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3332 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3333 } 3334 3335 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3336 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3337 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3338 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3339 3340 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3341 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3342 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3343 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3344 3345 /* firmware is for MAC only */ 3346 r8169_apply_firmware(tp); 3347 } 3348 3349 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3350 { 3351 static const struct ephy_info e_info_8102e_1[] = { 3352 { 0x01, 0, 0x6e65 }, 3353 { 0x02, 0, 0x091f }, 3354 { 0x03, 0, 0xc2f9 }, 3355 { 0x06, 0, 0xafb5 }, 3356 { 0x07, 0, 0x0e00 }, 3357 { 0x19, 0, 0xec80 }, 3358 { 0x01, 0, 0x2e65 }, 3359 { 0x01, 0, 0x6e65 } 3360 }; 3361 u8 cfg1; 3362 3363 rtl_set_def_aspm_entry_latency(tp); 3364 3365 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3366 3367 RTL_W8(tp, Config1, 3368 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3369 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3370 3371 cfg1 = RTL_R8(tp, Config1); 3372 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3373 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3374 3375 rtl_ephy_init(tp, e_info_8102e_1); 3376 } 3377 3378 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3379 { 3380 rtl_set_def_aspm_entry_latency(tp); 3381 3382 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3383 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3384 } 3385 3386 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3387 { 3388 rtl_hw_start_8102e_2(tp); 3389 3390 rtl_ephy_write(tp, 0x03, 0xc2f9); 3391 } 3392 3393 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3394 { 3395 static const struct ephy_info e_info_8401[] = { 3396 { 0x01, 0xffff, 0x6fe5 }, 3397 { 0x03, 0xffff, 0x0599 }, 3398 { 0x06, 0xffff, 0xaf25 }, 3399 { 0x07, 0xffff, 0x8e68 }, 3400 }; 3401 3402 rtl_ephy_init(tp, e_info_8401); 3403 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3404 } 3405 3406 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3407 { 3408 static const struct ephy_info e_info_8105e_1[] = { 3409 { 0x07, 0, 0x4000 }, 3410 { 0x19, 0, 0x0200 }, 3411 { 0x19, 0, 0x0020 }, 3412 { 0x1e, 0, 0x2000 }, 3413 { 0x03, 0, 0x0001 }, 3414 { 0x19, 0, 0x0100 }, 3415 { 0x19, 0, 0x0004 }, 3416 { 0x0a, 0, 0x0020 } 3417 }; 3418 3419 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3420 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3421 3422 /* Disable Early Tally Counter */ 3423 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3424 3425 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3426 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3427 3428 rtl_ephy_init(tp, e_info_8105e_1); 3429 3430 rtl_pcie_state_l2l3_disable(tp); 3431 } 3432 3433 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3434 { 3435 rtl_hw_start_8105e_1(tp); 3436 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3437 } 3438 3439 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3440 { 3441 static const struct ephy_info e_info_8402[] = { 3442 { 0x19, 0xffff, 0xff64 }, 3443 { 0x1e, 0, 0x4000 } 3444 }; 3445 3446 rtl_set_def_aspm_entry_latency(tp); 3447 3448 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3449 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3450 3451 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3452 3453 rtl_ephy_init(tp, e_info_8402); 3454 3455 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3456 rtl_reset_packet_filter(tp); 3457 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3458 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3459 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3460 3461 /* disable EEE */ 3462 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3463 3464 rtl_pcie_state_l2l3_disable(tp); 3465 } 3466 3467 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3468 { 3469 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3470 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3471 3472 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3473 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3474 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3475 3476 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3477 rtl_set_aspm_entry_latency(tp, 0x2f); 3478 3479 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3480 3481 /* disable EEE */ 3482 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3483 3484 rtl_pcie_state_l2l3_disable(tp); 3485 } 3486 3487 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3488 { 3489 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3490 } 3491 3492 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3493 { 3494 rtl_pcie_state_l2l3_disable(tp); 3495 3496 RTL_W16(tp, 0x382, 0x221b); 3497 RTL_W8(tp, 0x4500, 0); 3498 RTL_W16(tp, 0x4800, 0); 3499 3500 /* disable UPS */ 3501 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3502 3503 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3504 3505 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3506 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3507 3508 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3509 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3510 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3511 3512 /* disable new tx descriptor format */ 3513 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3514 3515 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3516 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3517 else 3518 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3519 3520 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3521 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3522 else 3523 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3524 3525 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3526 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3527 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3528 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3529 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3530 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3531 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3532 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3533 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3534 3535 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3536 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3537 udelay(1); 3538 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3539 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3540 3541 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3542 3543 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3544 3545 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3546 rtl8125b_config_eee_mac(tp); 3547 else 3548 rtl8125a_config_eee_mac(tp); 3549 3550 rtl_disable_rxdvgate(tp); 3551 } 3552 3553 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3554 { 3555 static const struct ephy_info e_info_8125a_2[] = { 3556 { 0x04, 0xffff, 0xd000 }, 3557 { 0x0a, 0xffff, 0x8653 }, 3558 { 0x23, 0xffff, 0xab66 }, 3559 { 0x20, 0xffff, 0x9455 }, 3560 { 0x21, 0xffff, 0x99ff }, 3561 { 0x29, 0xffff, 0xfe04 }, 3562 3563 { 0x44, 0xffff, 0xd000 }, 3564 { 0x4a, 0xffff, 0x8653 }, 3565 { 0x63, 0xffff, 0xab66 }, 3566 { 0x60, 0xffff, 0x9455 }, 3567 { 0x61, 0xffff, 0x99ff }, 3568 { 0x69, 0xffff, 0xfe04 }, 3569 }; 3570 3571 rtl_set_def_aspm_entry_latency(tp); 3572 rtl_ephy_init(tp, e_info_8125a_2); 3573 rtl_hw_start_8125_common(tp); 3574 } 3575 3576 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3577 { 3578 static const struct ephy_info e_info_8125b[] = { 3579 { 0x0b, 0xffff, 0xa908 }, 3580 { 0x1e, 0xffff, 0x20eb }, 3581 { 0x4b, 0xffff, 0xa908 }, 3582 { 0x5e, 0xffff, 0x20eb }, 3583 { 0x22, 0x0030, 0x0020 }, 3584 { 0x62, 0x0030, 0x0020 }, 3585 }; 3586 3587 rtl_set_def_aspm_entry_latency(tp); 3588 rtl_ephy_init(tp, e_info_8125b); 3589 rtl_hw_start_8125_common(tp); 3590 } 3591 3592 static void rtl_hw_config(struct rtl8169_private *tp) 3593 { 3594 static const rtl_generic_fct hw_configs[] = { 3595 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3596 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3597 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3598 [RTL_GIGA_MAC_VER_10] = NULL, 3599 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3600 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3601 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3602 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3603 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3604 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3605 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3606 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3607 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3608 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3609 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3610 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3611 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3612 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3613 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3614 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3615 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3616 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3617 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3618 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3619 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3620 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3621 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3622 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3623 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3624 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3625 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3626 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3627 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3628 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3629 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3630 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3631 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3632 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3633 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3634 }; 3635 3636 if (hw_configs[tp->mac_version]) 3637 hw_configs[tp->mac_version](tp); 3638 } 3639 3640 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3641 { 3642 int i; 3643 3644 /* disable interrupt coalescing */ 3645 for (i = 0xa00; i < 0xb00; i += 4) 3646 RTL_W32(tp, i, 0); 3647 3648 rtl_hw_config(tp); 3649 } 3650 3651 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3652 { 3653 if (rtl_is_8168evl_up(tp)) 3654 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3655 else 3656 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3657 3658 rtl_hw_config(tp); 3659 3660 /* disable interrupt coalescing */ 3661 RTL_W16(tp, IntrMitigate, 0x0000); 3662 } 3663 3664 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3665 { 3666 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3667 3668 tp->cp_cmd |= PCIMulRW; 3669 3670 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3671 tp->mac_version == RTL_GIGA_MAC_VER_03) 3672 tp->cp_cmd |= EnAnaPLL; 3673 3674 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3675 3676 rtl8169_set_magic_reg(tp); 3677 3678 /* disable interrupt coalescing */ 3679 RTL_W16(tp, IntrMitigate, 0x0000); 3680 } 3681 3682 static void rtl_hw_start(struct rtl8169_private *tp) 3683 { 3684 rtl_unlock_config_regs(tp); 3685 /* disable aspm and clock request before ephy access */ 3686 rtl_hw_aspm_clkreq_enable(tp, false); 3687 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3688 3689 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3690 rtl_hw_start_8169(tp); 3691 else if (rtl_is_8125(tp)) 3692 rtl_hw_start_8125(tp); 3693 else 3694 rtl_hw_start_8168(tp); 3695 3696 rtl_enable_exit_l1(tp); 3697 rtl_hw_aspm_clkreq_enable(tp, true); 3698 rtl_set_rx_max_size(tp); 3699 rtl_set_rx_tx_desc_registers(tp); 3700 rtl_lock_config_regs(tp); 3701 3702 rtl_jumbo_config(tp); 3703 3704 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3705 rtl_pci_commit(tp); 3706 3707 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3708 rtl_init_rxcfg(tp); 3709 rtl_set_tx_config_registers(tp); 3710 rtl_set_rx_config_features(tp, tp->dev->features); 3711 rtl_set_rx_mode(tp->dev); 3712 rtl_irq_enable(tp); 3713 } 3714 3715 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3716 { 3717 struct rtl8169_private *tp = netdev_priv(dev); 3718 3719 dev->mtu = new_mtu; 3720 netdev_update_features(dev); 3721 rtl_jumbo_config(tp); 3722 3723 switch (tp->mac_version) { 3724 case RTL_GIGA_MAC_VER_61: 3725 case RTL_GIGA_MAC_VER_63: 3726 rtl8125_set_eee_txidle_timer(tp); 3727 break; 3728 default: 3729 break; 3730 } 3731 3732 return 0; 3733 } 3734 3735 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3736 { 3737 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3738 3739 desc->opts2 = 0; 3740 /* Force memory writes to complete before releasing descriptor */ 3741 dma_wmb(); 3742 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3743 } 3744 3745 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3746 struct RxDesc *desc) 3747 { 3748 struct device *d = tp_to_dev(tp); 3749 int node = dev_to_node(d); 3750 dma_addr_t mapping; 3751 struct page *data; 3752 3753 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3754 if (!data) 3755 return NULL; 3756 3757 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3758 if (unlikely(dma_mapping_error(d, mapping))) { 3759 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3760 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3761 return NULL; 3762 } 3763 3764 desc->addr = cpu_to_le64(mapping); 3765 rtl8169_mark_to_asic(desc); 3766 3767 return data; 3768 } 3769 3770 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3771 { 3772 int i; 3773 3774 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3775 dma_unmap_page(tp_to_dev(tp), 3776 le64_to_cpu(tp->RxDescArray[i].addr), 3777 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3778 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3779 tp->Rx_databuff[i] = NULL; 3780 tp->RxDescArray[i].addr = 0; 3781 tp->RxDescArray[i].opts1 = 0; 3782 } 3783 } 3784 3785 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3786 { 3787 int i; 3788 3789 for (i = 0; i < NUM_RX_DESC; i++) { 3790 struct page *data; 3791 3792 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3793 if (!data) { 3794 rtl8169_rx_clear(tp); 3795 return -ENOMEM; 3796 } 3797 tp->Rx_databuff[i] = data; 3798 } 3799 3800 /* mark as last descriptor in the ring */ 3801 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3802 3803 return 0; 3804 } 3805 3806 static int rtl8169_init_ring(struct rtl8169_private *tp) 3807 { 3808 rtl8169_init_ring_indexes(tp); 3809 3810 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3811 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3812 3813 return rtl8169_rx_fill(tp); 3814 } 3815 3816 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3817 { 3818 struct ring_info *tx_skb = tp->tx_skb + entry; 3819 struct TxDesc *desc = tp->TxDescArray + entry; 3820 3821 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3822 DMA_TO_DEVICE); 3823 memset(desc, 0, sizeof(*desc)); 3824 memset(tx_skb, 0, sizeof(*tx_skb)); 3825 } 3826 3827 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3828 unsigned int n) 3829 { 3830 unsigned int i; 3831 3832 for (i = 0; i < n; i++) { 3833 unsigned int entry = (start + i) % NUM_TX_DESC; 3834 struct ring_info *tx_skb = tp->tx_skb + entry; 3835 unsigned int len = tx_skb->len; 3836 3837 if (len) { 3838 struct sk_buff *skb = tx_skb->skb; 3839 3840 rtl8169_unmap_tx_skb(tp, entry); 3841 if (skb) 3842 dev_consume_skb_any(skb); 3843 } 3844 } 3845 } 3846 3847 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3848 { 3849 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3850 netdev_reset_queue(tp->dev); 3851 } 3852 3853 static void rtl8169_cleanup(struct rtl8169_private *tp) 3854 { 3855 napi_disable(&tp->napi); 3856 3857 /* Give a racing hard_start_xmit a few cycles to complete. */ 3858 synchronize_net(); 3859 3860 /* Disable interrupts */ 3861 rtl8169_irq_mask_and_ack(tp); 3862 3863 rtl_rx_close(tp); 3864 3865 switch (tp->mac_version) { 3866 case RTL_GIGA_MAC_VER_28: 3867 case RTL_GIGA_MAC_VER_31: 3868 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3869 break; 3870 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3871 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3872 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3873 break; 3874 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3875 rtl_enable_rxdvgate(tp); 3876 fsleep(2000); 3877 break; 3878 default: 3879 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3880 fsleep(100); 3881 break; 3882 } 3883 3884 rtl_hw_reset(tp); 3885 3886 rtl8169_tx_clear(tp); 3887 rtl8169_init_ring_indexes(tp); 3888 } 3889 3890 static void rtl_reset_work(struct rtl8169_private *tp) 3891 { 3892 int i; 3893 3894 netif_stop_queue(tp->dev); 3895 3896 rtl8169_cleanup(tp); 3897 3898 for (i = 0; i < NUM_RX_DESC; i++) 3899 rtl8169_mark_to_asic(tp->RxDescArray + i); 3900 3901 napi_enable(&tp->napi); 3902 rtl_hw_start(tp); 3903 } 3904 3905 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3906 { 3907 struct rtl8169_private *tp = netdev_priv(dev); 3908 3909 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 3910 } 3911 3912 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3913 void *addr, unsigned int entry, bool desc_own) 3914 { 3915 struct TxDesc *txd = tp->TxDescArray + entry; 3916 struct device *d = tp_to_dev(tp); 3917 dma_addr_t mapping; 3918 u32 opts1; 3919 int ret; 3920 3921 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3922 ret = dma_mapping_error(d, mapping); 3923 if (unlikely(ret)) { 3924 if (net_ratelimit()) 3925 netdev_err(tp->dev, "Failed to map TX data!\n"); 3926 return ret; 3927 } 3928 3929 txd->addr = cpu_to_le64(mapping); 3930 txd->opts2 = cpu_to_le32(opts[1]); 3931 3932 opts1 = opts[0] | len; 3933 if (entry == NUM_TX_DESC - 1) 3934 opts1 |= RingEnd; 3935 if (desc_own) 3936 opts1 |= DescOwn; 3937 txd->opts1 = cpu_to_le32(opts1); 3938 3939 tp->tx_skb[entry].len = len; 3940 3941 return 0; 3942 } 3943 3944 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3945 const u32 *opts, unsigned int entry) 3946 { 3947 struct skb_shared_info *info = skb_shinfo(skb); 3948 unsigned int cur_frag; 3949 3950 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 3951 const skb_frag_t *frag = info->frags + cur_frag; 3952 void *addr = skb_frag_address(frag); 3953 u32 len = skb_frag_size(frag); 3954 3955 entry = (entry + 1) % NUM_TX_DESC; 3956 3957 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 3958 goto err_out; 3959 } 3960 3961 return 0; 3962 3963 err_out: 3964 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 3965 return -EIO; 3966 } 3967 3968 static bool rtl_skb_is_udp(struct sk_buff *skb) 3969 { 3970 int no = skb_network_offset(skb); 3971 struct ipv6hdr *i6h, _i6h; 3972 struct iphdr *ih, _ih; 3973 3974 switch (vlan_get_protocol(skb)) { 3975 case htons(ETH_P_IP): 3976 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 3977 return ih && ih->protocol == IPPROTO_UDP; 3978 case htons(ETH_P_IPV6): 3979 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 3980 return i6h && i6h->nexthdr == IPPROTO_UDP; 3981 default: 3982 return false; 3983 } 3984 } 3985 3986 #define RTL_MIN_PATCH_LEN 47 3987 3988 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 3989 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 3990 struct sk_buff *skb) 3991 { 3992 unsigned int padto = 0, len = skb->len; 3993 3994 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 3995 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 3996 unsigned int trans_data_len = skb_tail_pointer(skb) - 3997 skb_transport_header(skb); 3998 3999 if (trans_data_len >= offsetof(struct udphdr, len) && 4000 trans_data_len < RTL_MIN_PATCH_LEN) { 4001 u16 dest = ntohs(udp_hdr(skb)->dest); 4002 4003 /* dest is a standard PTP port */ 4004 if (dest == 319 || dest == 320) 4005 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4006 } 4007 4008 if (trans_data_len < sizeof(struct udphdr)) 4009 padto = max_t(unsigned int, padto, 4010 len + sizeof(struct udphdr) - trans_data_len); 4011 } 4012 4013 return padto; 4014 } 4015 4016 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4017 struct sk_buff *skb) 4018 { 4019 unsigned int padto; 4020 4021 padto = rtl8125_quirk_udp_padto(tp, skb); 4022 4023 switch (tp->mac_version) { 4024 case RTL_GIGA_MAC_VER_34: 4025 case RTL_GIGA_MAC_VER_61: 4026 case RTL_GIGA_MAC_VER_63: 4027 padto = max_t(unsigned int, padto, ETH_ZLEN); 4028 break; 4029 default: 4030 break; 4031 } 4032 4033 return padto; 4034 } 4035 4036 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4037 { 4038 u32 mss = skb_shinfo(skb)->gso_size; 4039 4040 if (mss) { 4041 opts[0] |= TD_LSO; 4042 opts[0] |= mss << TD0_MSS_SHIFT; 4043 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4044 const struct iphdr *ip = ip_hdr(skb); 4045 4046 if (ip->protocol == IPPROTO_TCP) 4047 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4048 else if (ip->protocol == IPPROTO_UDP) 4049 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4050 else 4051 WARN_ON_ONCE(1); 4052 } 4053 } 4054 4055 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4056 struct sk_buff *skb, u32 *opts) 4057 { 4058 struct skb_shared_info *shinfo = skb_shinfo(skb); 4059 u32 mss = shinfo->gso_size; 4060 4061 if (mss) { 4062 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4063 opts[0] |= TD1_GTSENV4; 4064 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4065 if (skb_cow_head(skb, 0)) 4066 return false; 4067 4068 tcp_v6_gso_csum_prep(skb); 4069 opts[0] |= TD1_GTSENV6; 4070 } else { 4071 WARN_ON_ONCE(1); 4072 } 4073 4074 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4075 opts[1] |= mss << TD1_MSS_SHIFT; 4076 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4077 u8 ip_protocol; 4078 4079 switch (vlan_get_protocol(skb)) { 4080 case htons(ETH_P_IP): 4081 opts[1] |= TD1_IPv4_CS; 4082 ip_protocol = ip_hdr(skb)->protocol; 4083 break; 4084 4085 case htons(ETH_P_IPV6): 4086 opts[1] |= TD1_IPv6_CS; 4087 ip_protocol = ipv6_hdr(skb)->nexthdr; 4088 break; 4089 4090 default: 4091 ip_protocol = IPPROTO_RAW; 4092 break; 4093 } 4094 4095 if (ip_protocol == IPPROTO_TCP) 4096 opts[1] |= TD1_TCP_CS; 4097 else if (ip_protocol == IPPROTO_UDP) 4098 opts[1] |= TD1_UDP_CS; 4099 else 4100 WARN_ON_ONCE(1); 4101 4102 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4103 } else { 4104 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4105 4106 /* skb_padto would free the skb on error */ 4107 return !__skb_put_padto(skb, padto, false); 4108 } 4109 4110 return true; 4111 } 4112 4113 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4114 { 4115 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4116 } 4117 4118 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4119 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4120 { 4121 switch (tp->mac_version) { 4122 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4123 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4124 return false; 4125 default: 4126 return true; 4127 } 4128 } 4129 4130 static void rtl8169_doorbell(struct rtl8169_private *tp) 4131 { 4132 if (rtl_is_8125(tp)) 4133 RTL_W16(tp, TxPoll_8125, BIT(0)); 4134 else 4135 RTL_W8(tp, TxPoll, NPQ); 4136 } 4137 4138 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4139 struct net_device *dev) 4140 { 4141 unsigned int frags = skb_shinfo(skb)->nr_frags; 4142 struct rtl8169_private *tp = netdev_priv(dev); 4143 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4144 struct TxDesc *txd_first, *txd_last; 4145 bool stop_queue, door_bell; 4146 u32 opts[2]; 4147 4148 if (unlikely(!rtl_tx_slots_avail(tp))) { 4149 if (net_ratelimit()) 4150 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4151 goto err_stop_0; 4152 } 4153 4154 opts[1] = rtl8169_tx_vlan_tag(skb); 4155 opts[0] = 0; 4156 4157 if (!rtl_chip_supports_csum_v2(tp)) 4158 rtl8169_tso_csum_v1(skb, opts); 4159 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4160 goto err_dma_0; 4161 4162 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4163 entry, false))) 4164 goto err_dma_0; 4165 4166 txd_first = tp->TxDescArray + entry; 4167 4168 if (frags) { 4169 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4170 goto err_dma_1; 4171 entry = (entry + frags) % NUM_TX_DESC; 4172 } 4173 4174 txd_last = tp->TxDescArray + entry; 4175 txd_last->opts1 |= cpu_to_le32(LastFrag); 4176 tp->tx_skb[entry].skb = skb; 4177 4178 skb_tx_timestamp(skb); 4179 4180 /* Force memory writes to complete before releasing descriptor */ 4181 dma_wmb(); 4182 4183 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4184 4185 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4186 4187 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4188 smp_wmb(); 4189 4190 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4191 4192 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4193 R8169_TX_STOP_THRS, 4194 R8169_TX_START_THRS); 4195 if (door_bell || stop_queue) 4196 rtl8169_doorbell(tp); 4197 4198 return NETDEV_TX_OK; 4199 4200 err_dma_1: 4201 rtl8169_unmap_tx_skb(tp, entry); 4202 err_dma_0: 4203 dev_kfree_skb_any(skb); 4204 dev->stats.tx_dropped++; 4205 return NETDEV_TX_OK; 4206 4207 err_stop_0: 4208 netif_stop_queue(dev); 4209 dev->stats.tx_dropped++; 4210 return NETDEV_TX_BUSY; 4211 } 4212 4213 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4214 { 4215 struct skb_shared_info *info = skb_shinfo(skb); 4216 unsigned int nr_frags = info->nr_frags; 4217 4218 if (!nr_frags) 4219 return UINT_MAX; 4220 4221 return skb_frag_size(info->frags + nr_frags - 1); 4222 } 4223 4224 /* Workaround for hw issues with TSO on RTL8168evl */ 4225 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4226 netdev_features_t features) 4227 { 4228 /* IPv4 header has options field */ 4229 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4230 ip_hdrlen(skb) > sizeof(struct iphdr)) 4231 features &= ~NETIF_F_ALL_TSO; 4232 4233 /* IPv4 TCP header has options field */ 4234 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4235 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4236 features &= ~NETIF_F_ALL_TSO; 4237 4238 else if (rtl_last_frag_len(skb) <= 6) 4239 features &= ~NETIF_F_ALL_TSO; 4240 4241 return features; 4242 } 4243 4244 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4245 struct net_device *dev, 4246 netdev_features_t features) 4247 { 4248 struct rtl8169_private *tp = netdev_priv(dev); 4249 4250 if (skb_is_gso(skb)) { 4251 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4252 features = rtl8168evl_fix_tso(skb, features); 4253 4254 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4255 rtl_chip_supports_csum_v2(tp)) 4256 features &= ~NETIF_F_ALL_TSO; 4257 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4258 /* work around hw bug on some chip versions */ 4259 if (skb->len < ETH_ZLEN) 4260 features &= ~NETIF_F_CSUM_MASK; 4261 4262 if (rtl_quirk_packet_padto(tp, skb)) 4263 features &= ~NETIF_F_CSUM_MASK; 4264 4265 if (skb_transport_offset(skb) > TCPHO_MAX && 4266 rtl_chip_supports_csum_v2(tp)) 4267 features &= ~NETIF_F_CSUM_MASK; 4268 } 4269 4270 return vlan_features_check(skb, features); 4271 } 4272 4273 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4274 { 4275 struct rtl8169_private *tp = netdev_priv(dev); 4276 struct pci_dev *pdev = tp->pci_dev; 4277 int pci_status_errs; 4278 u16 pci_cmd; 4279 4280 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4281 4282 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4283 4284 if (net_ratelimit()) 4285 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4286 pci_cmd, pci_status_errs); 4287 4288 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4289 } 4290 4291 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4292 int budget) 4293 { 4294 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4295 struct sk_buff *skb; 4296 4297 dirty_tx = tp->dirty_tx; 4298 4299 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4300 unsigned int entry = dirty_tx % NUM_TX_DESC; 4301 u32 status; 4302 4303 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4304 if (status & DescOwn) 4305 break; 4306 4307 skb = tp->tx_skb[entry].skb; 4308 rtl8169_unmap_tx_skb(tp, entry); 4309 4310 if (skb) { 4311 pkts_compl++; 4312 bytes_compl += skb->len; 4313 napi_consume_skb(skb, budget); 4314 } 4315 dirty_tx++; 4316 } 4317 4318 if (tp->dirty_tx != dirty_tx) { 4319 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4320 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4321 4322 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4323 rtl_tx_slots_avail(tp), 4324 R8169_TX_START_THRS); 4325 /* 4326 * 8168 hack: TxPoll requests are lost when the Tx packets are 4327 * too close. Let's kick an extra TxPoll request when a burst 4328 * of start_xmit activity is detected (if it is not detected, 4329 * it is slow enough). -- FR 4330 * If skb is NULL then we come here again once a tx irq is 4331 * triggered after the last fragment is marked transmitted. 4332 */ 4333 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4334 rtl8169_doorbell(tp); 4335 } 4336 } 4337 4338 static inline int rtl8169_fragmented_frame(u32 status) 4339 { 4340 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4341 } 4342 4343 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4344 { 4345 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4346 4347 if (status == RxProtoTCP || status == RxProtoUDP) 4348 skb->ip_summed = CHECKSUM_UNNECESSARY; 4349 else 4350 skb_checksum_none_assert(skb); 4351 } 4352 4353 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4354 { 4355 struct device *d = tp_to_dev(tp); 4356 int count; 4357 4358 for (count = 0; count < budget; count++, tp->cur_rx++) { 4359 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4360 struct RxDesc *desc = tp->RxDescArray + entry; 4361 struct sk_buff *skb; 4362 const void *rx_buf; 4363 dma_addr_t addr; 4364 u32 status; 4365 4366 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4367 if (status & DescOwn) 4368 break; 4369 4370 /* This barrier is needed to keep us from reading 4371 * any other fields out of the Rx descriptor until 4372 * we know the status of DescOwn 4373 */ 4374 dma_rmb(); 4375 4376 if (unlikely(status & RxRES)) { 4377 if (net_ratelimit()) 4378 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4379 status); 4380 dev->stats.rx_errors++; 4381 if (status & (RxRWT | RxRUNT)) 4382 dev->stats.rx_length_errors++; 4383 if (status & RxCRC) 4384 dev->stats.rx_crc_errors++; 4385 4386 if (!(dev->features & NETIF_F_RXALL)) 4387 goto release_descriptor; 4388 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4389 goto release_descriptor; 4390 } 4391 4392 pkt_size = status & GENMASK(13, 0); 4393 if (likely(!(dev->features & NETIF_F_RXFCS))) 4394 pkt_size -= ETH_FCS_LEN; 4395 4396 /* The driver does not support incoming fragmented frames. 4397 * They are seen as a symptom of over-mtu sized frames. 4398 */ 4399 if (unlikely(rtl8169_fragmented_frame(status))) { 4400 dev->stats.rx_dropped++; 4401 dev->stats.rx_length_errors++; 4402 goto release_descriptor; 4403 } 4404 4405 skb = napi_alloc_skb(&tp->napi, pkt_size); 4406 if (unlikely(!skb)) { 4407 dev->stats.rx_dropped++; 4408 goto release_descriptor; 4409 } 4410 4411 addr = le64_to_cpu(desc->addr); 4412 rx_buf = page_address(tp->Rx_databuff[entry]); 4413 4414 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4415 prefetch(rx_buf); 4416 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4417 skb->tail += pkt_size; 4418 skb->len = pkt_size; 4419 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4420 4421 rtl8169_rx_csum(skb, status); 4422 skb->protocol = eth_type_trans(skb, dev); 4423 4424 rtl8169_rx_vlan_tag(desc, skb); 4425 4426 if (skb->pkt_type == PACKET_MULTICAST) 4427 dev->stats.multicast++; 4428 4429 napi_gro_receive(&tp->napi, skb); 4430 4431 dev_sw_netstats_rx_add(dev, pkt_size); 4432 release_descriptor: 4433 rtl8169_mark_to_asic(desc); 4434 } 4435 4436 return count; 4437 } 4438 4439 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4440 { 4441 struct rtl8169_private *tp = dev_instance; 4442 u32 status = rtl_get_events(tp); 4443 4444 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4445 return IRQ_NONE; 4446 4447 if (unlikely(status & SYSErr)) { 4448 rtl8169_pcierr_interrupt(tp->dev); 4449 goto out; 4450 } 4451 4452 if (status & LinkChg) 4453 phy_mac_interrupt(tp->phydev); 4454 4455 if (unlikely(status & RxFIFOOver && 4456 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4457 netif_stop_queue(tp->dev); 4458 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4459 } 4460 4461 if (napi_schedule_prep(&tp->napi)) { 4462 rtl_irq_disable(tp); 4463 __napi_schedule(&tp->napi); 4464 } 4465 out: 4466 rtl_ack_events(tp, status); 4467 4468 return IRQ_HANDLED; 4469 } 4470 4471 static void rtl_task(struct work_struct *work) 4472 { 4473 struct rtl8169_private *tp = 4474 container_of(work, struct rtl8169_private, wk.work); 4475 int ret; 4476 4477 rtnl_lock(); 4478 4479 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4480 goto out_unlock; 4481 4482 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4483 /* if chip isn't accessible, reset bus to revive it */ 4484 if (RTL_R32(tp, TxConfig) == ~0) { 4485 ret = pci_reset_bus(tp->pci_dev); 4486 if (ret < 0) { 4487 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4488 netif_device_detach(tp->dev); 4489 goto out_unlock; 4490 } 4491 } 4492 4493 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4494 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4495 PCIE_LINK_STATE_L0S); 4496 if (!ret) 4497 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4498 goto reset; 4499 } 4500 4501 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4502 reset: 4503 rtl_reset_work(tp); 4504 netif_wake_queue(tp->dev); 4505 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4506 rtl_reset_work(tp); 4507 } 4508 out_unlock: 4509 rtnl_unlock(); 4510 } 4511 4512 static int rtl8169_poll(struct napi_struct *napi, int budget) 4513 { 4514 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4515 struct net_device *dev = tp->dev; 4516 int work_done; 4517 4518 rtl_tx(dev, tp, budget); 4519 4520 work_done = rtl_rx(dev, tp, budget); 4521 4522 if (work_done < budget && napi_complete_done(napi, work_done)) 4523 rtl_irq_enable(tp); 4524 4525 return work_done; 4526 } 4527 4528 static void r8169_phylink_handler(struct net_device *ndev) 4529 { 4530 struct rtl8169_private *tp = netdev_priv(ndev); 4531 struct device *d = tp_to_dev(tp); 4532 4533 if (netif_carrier_ok(ndev)) { 4534 rtl_link_chg_patch(tp); 4535 pm_request_resume(d); 4536 netif_wake_queue(tp->dev); 4537 } else { 4538 /* In few cases rx is broken after link-down otherwise */ 4539 if (rtl_is_8125(tp)) 4540 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4541 pm_runtime_idle(d); 4542 } 4543 4544 phy_print_status(tp->phydev); 4545 } 4546 4547 static int r8169_phy_connect(struct rtl8169_private *tp) 4548 { 4549 struct phy_device *phydev = tp->phydev; 4550 phy_interface_t phy_mode; 4551 int ret; 4552 4553 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4554 PHY_INTERFACE_MODE_MII; 4555 4556 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4557 phy_mode); 4558 if (ret) 4559 return ret; 4560 4561 if (!tp->supports_gmii) 4562 phy_set_max_speed(phydev, SPEED_100); 4563 4564 phy_attached_info(phydev); 4565 4566 return 0; 4567 } 4568 4569 static void rtl8169_down(struct rtl8169_private *tp) 4570 { 4571 /* Clear all task flags */ 4572 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4573 4574 phy_stop(tp->phydev); 4575 4576 rtl8169_update_counters(tp); 4577 4578 pci_clear_master(tp->pci_dev); 4579 rtl_pci_commit(tp); 4580 4581 rtl8169_cleanup(tp); 4582 rtl_disable_exit_l1(tp); 4583 rtl_prepare_power_down(tp); 4584 4585 if (tp->dash_type != RTL_DASH_NONE) 4586 rtl8168_driver_stop(tp); 4587 } 4588 4589 static void rtl8169_up(struct rtl8169_private *tp) 4590 { 4591 if (tp->dash_type != RTL_DASH_NONE) 4592 rtl8168_driver_start(tp); 4593 4594 pci_set_master(tp->pci_dev); 4595 phy_init_hw(tp->phydev); 4596 phy_resume(tp->phydev); 4597 rtl8169_init_phy(tp); 4598 napi_enable(&tp->napi); 4599 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4600 rtl_reset_work(tp); 4601 4602 phy_start(tp->phydev); 4603 } 4604 4605 static int rtl8169_close(struct net_device *dev) 4606 { 4607 struct rtl8169_private *tp = netdev_priv(dev); 4608 struct pci_dev *pdev = tp->pci_dev; 4609 4610 pm_runtime_get_sync(&pdev->dev); 4611 4612 netif_stop_queue(dev); 4613 rtl8169_down(tp); 4614 rtl8169_rx_clear(tp); 4615 4616 cancel_work(&tp->wk.work); 4617 4618 free_irq(tp->irq, tp); 4619 4620 phy_disconnect(tp->phydev); 4621 4622 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4623 tp->RxPhyAddr); 4624 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4625 tp->TxPhyAddr); 4626 tp->TxDescArray = NULL; 4627 tp->RxDescArray = NULL; 4628 4629 pm_runtime_put_sync(&pdev->dev); 4630 4631 return 0; 4632 } 4633 4634 #ifdef CONFIG_NET_POLL_CONTROLLER 4635 static void rtl8169_netpoll(struct net_device *dev) 4636 { 4637 struct rtl8169_private *tp = netdev_priv(dev); 4638 4639 rtl8169_interrupt(tp->irq, tp); 4640 } 4641 #endif 4642 4643 static int rtl_open(struct net_device *dev) 4644 { 4645 struct rtl8169_private *tp = netdev_priv(dev); 4646 struct pci_dev *pdev = tp->pci_dev; 4647 unsigned long irqflags; 4648 int retval = -ENOMEM; 4649 4650 pm_runtime_get_sync(&pdev->dev); 4651 4652 /* 4653 * Rx and Tx descriptors needs 256 bytes alignment. 4654 * dma_alloc_coherent provides more. 4655 */ 4656 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4657 &tp->TxPhyAddr, GFP_KERNEL); 4658 if (!tp->TxDescArray) 4659 goto out; 4660 4661 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4662 &tp->RxPhyAddr, GFP_KERNEL); 4663 if (!tp->RxDescArray) 4664 goto err_free_tx_0; 4665 4666 retval = rtl8169_init_ring(tp); 4667 if (retval < 0) 4668 goto err_free_rx_1; 4669 4670 rtl_request_firmware(tp); 4671 4672 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4673 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4674 if (retval < 0) 4675 goto err_release_fw_2; 4676 4677 retval = r8169_phy_connect(tp); 4678 if (retval) 4679 goto err_free_irq; 4680 4681 rtl8169_up(tp); 4682 rtl8169_init_counter_offsets(tp); 4683 netif_start_queue(dev); 4684 out: 4685 pm_runtime_put_sync(&pdev->dev); 4686 4687 return retval; 4688 4689 err_free_irq: 4690 free_irq(tp->irq, tp); 4691 err_release_fw_2: 4692 rtl_release_firmware(tp); 4693 rtl8169_rx_clear(tp); 4694 err_free_rx_1: 4695 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4696 tp->RxPhyAddr); 4697 tp->RxDescArray = NULL; 4698 err_free_tx_0: 4699 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4700 tp->TxPhyAddr); 4701 tp->TxDescArray = NULL; 4702 goto out; 4703 } 4704 4705 static void 4706 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4707 { 4708 struct rtl8169_private *tp = netdev_priv(dev); 4709 struct pci_dev *pdev = tp->pci_dev; 4710 struct rtl8169_counters *counters = tp->counters; 4711 4712 pm_runtime_get_noresume(&pdev->dev); 4713 4714 netdev_stats_to_stats64(stats, &dev->stats); 4715 dev_fetch_sw_netstats(stats, dev->tstats); 4716 4717 /* 4718 * Fetch additional counter values missing in stats collected by driver 4719 * from tally counters. 4720 */ 4721 if (pm_runtime_active(&pdev->dev)) 4722 rtl8169_update_counters(tp); 4723 4724 /* 4725 * Subtract values fetched during initalization. 4726 * See rtl8169_init_counter_offsets for a description why we do that. 4727 */ 4728 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4729 le64_to_cpu(tp->tc_offset.tx_errors); 4730 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4731 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4732 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4733 le16_to_cpu(tp->tc_offset.tx_aborted); 4734 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4735 le16_to_cpu(tp->tc_offset.rx_missed); 4736 4737 pm_runtime_put_noidle(&pdev->dev); 4738 } 4739 4740 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4741 { 4742 netif_device_detach(tp->dev); 4743 4744 if (netif_running(tp->dev)) 4745 rtl8169_down(tp); 4746 } 4747 4748 static int rtl8169_runtime_resume(struct device *dev) 4749 { 4750 struct rtl8169_private *tp = dev_get_drvdata(dev); 4751 4752 rtl_rar_set(tp, tp->dev->dev_addr); 4753 __rtl8169_set_wol(tp, tp->saved_wolopts); 4754 4755 if (tp->TxDescArray) 4756 rtl8169_up(tp); 4757 4758 netif_device_attach(tp->dev); 4759 4760 return 0; 4761 } 4762 4763 static int rtl8169_suspend(struct device *device) 4764 { 4765 struct rtl8169_private *tp = dev_get_drvdata(device); 4766 4767 rtnl_lock(); 4768 rtl8169_net_suspend(tp); 4769 if (!device_may_wakeup(tp_to_dev(tp))) 4770 clk_disable_unprepare(tp->clk); 4771 rtnl_unlock(); 4772 4773 return 0; 4774 } 4775 4776 static int rtl8169_resume(struct device *device) 4777 { 4778 struct rtl8169_private *tp = dev_get_drvdata(device); 4779 4780 if (!device_may_wakeup(tp_to_dev(tp))) 4781 clk_prepare_enable(tp->clk); 4782 4783 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4784 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4785 rtl_init_rxcfg(tp); 4786 4787 return rtl8169_runtime_resume(device); 4788 } 4789 4790 static int rtl8169_runtime_suspend(struct device *device) 4791 { 4792 struct rtl8169_private *tp = dev_get_drvdata(device); 4793 4794 if (!tp->TxDescArray) { 4795 netif_device_detach(tp->dev); 4796 return 0; 4797 } 4798 4799 rtnl_lock(); 4800 __rtl8169_set_wol(tp, WAKE_PHY); 4801 rtl8169_net_suspend(tp); 4802 rtnl_unlock(); 4803 4804 return 0; 4805 } 4806 4807 static int rtl8169_runtime_idle(struct device *device) 4808 { 4809 struct rtl8169_private *tp = dev_get_drvdata(device); 4810 4811 if (tp->dash_enabled) 4812 return -EBUSY; 4813 4814 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4815 pm_schedule_suspend(device, 10000); 4816 4817 return -EBUSY; 4818 } 4819 4820 static const struct dev_pm_ops rtl8169_pm_ops = { 4821 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4822 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4823 rtl8169_runtime_idle) 4824 }; 4825 4826 static void rtl_shutdown(struct pci_dev *pdev) 4827 { 4828 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4829 4830 rtnl_lock(); 4831 rtl8169_net_suspend(tp); 4832 rtnl_unlock(); 4833 4834 /* Restore original MAC address */ 4835 rtl_rar_set(tp, tp->dev->perm_addr); 4836 4837 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 4838 pci_wake_from_d3(pdev, tp->saved_wolopts); 4839 pci_set_power_state(pdev, PCI_D3hot); 4840 } 4841 } 4842 4843 static void rtl_remove_one(struct pci_dev *pdev) 4844 { 4845 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4846 4847 if (pci_dev_run_wake(pdev)) 4848 pm_runtime_get_noresume(&pdev->dev); 4849 4850 cancel_work_sync(&tp->wk.work); 4851 4852 unregister_netdev(tp->dev); 4853 4854 if (tp->dash_type != RTL_DASH_NONE) 4855 rtl8168_driver_stop(tp); 4856 4857 rtl_release_firmware(tp); 4858 4859 /* restore original MAC address */ 4860 rtl_rar_set(tp, tp->dev->perm_addr); 4861 } 4862 4863 static const struct net_device_ops rtl_netdev_ops = { 4864 .ndo_open = rtl_open, 4865 .ndo_stop = rtl8169_close, 4866 .ndo_get_stats64 = rtl8169_get_stats64, 4867 .ndo_start_xmit = rtl8169_start_xmit, 4868 .ndo_features_check = rtl8169_features_check, 4869 .ndo_tx_timeout = rtl8169_tx_timeout, 4870 .ndo_validate_addr = eth_validate_addr, 4871 .ndo_change_mtu = rtl8169_change_mtu, 4872 .ndo_fix_features = rtl8169_fix_features, 4873 .ndo_set_features = rtl8169_set_features, 4874 .ndo_set_mac_address = rtl_set_mac_address, 4875 .ndo_eth_ioctl = phy_do_ioctl_running, 4876 .ndo_set_rx_mode = rtl_set_rx_mode, 4877 #ifdef CONFIG_NET_POLL_CONTROLLER 4878 .ndo_poll_controller = rtl8169_netpoll, 4879 #endif 4880 4881 }; 4882 4883 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4884 { 4885 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4886 4887 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4888 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4889 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4890 /* special workaround needed */ 4891 tp->irq_mask |= RxFIFOOver; 4892 else 4893 tp->irq_mask |= RxOverflow; 4894 } 4895 4896 static int rtl_alloc_irq(struct rtl8169_private *tp) 4897 { 4898 unsigned int flags; 4899 4900 switch (tp->mac_version) { 4901 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4902 rtl_unlock_config_regs(tp); 4903 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4904 rtl_lock_config_regs(tp); 4905 fallthrough; 4906 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4907 flags = PCI_IRQ_LEGACY; 4908 break; 4909 default: 4910 flags = PCI_IRQ_ALL_TYPES; 4911 break; 4912 } 4913 4914 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4915 } 4916 4917 static void rtl_read_mac_address(struct rtl8169_private *tp, 4918 u8 mac_addr[ETH_ALEN]) 4919 { 4920 /* Get MAC address */ 4921 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 4922 u32 value; 4923 4924 value = rtl_eri_read(tp, 0xe0); 4925 put_unaligned_le32(value, mac_addr); 4926 value = rtl_eri_read(tp, 0xe4); 4927 put_unaligned_le16(value, mac_addr + 4); 4928 } else if (rtl_is_8125(tp)) { 4929 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 4930 } 4931 } 4932 4933 DECLARE_RTL_COND(rtl_link_list_ready_cond) 4934 { 4935 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 4936 } 4937 4938 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 4939 { 4940 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 4941 } 4942 4943 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 4944 { 4945 struct rtl8169_private *tp = mii_bus->priv; 4946 4947 if (phyaddr > 0) 4948 return -ENODEV; 4949 4950 return rtl_readphy(tp, phyreg); 4951 } 4952 4953 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 4954 int phyreg, u16 val) 4955 { 4956 struct rtl8169_private *tp = mii_bus->priv; 4957 4958 if (phyaddr > 0) 4959 return -ENODEV; 4960 4961 rtl_writephy(tp, phyreg, val); 4962 4963 return 0; 4964 } 4965 4966 static int r8169_mdio_register(struct rtl8169_private *tp) 4967 { 4968 struct pci_dev *pdev = tp->pci_dev; 4969 struct mii_bus *new_bus; 4970 int ret; 4971 4972 new_bus = devm_mdiobus_alloc(&pdev->dev); 4973 if (!new_bus) 4974 return -ENOMEM; 4975 4976 new_bus->name = "r8169"; 4977 new_bus->priv = tp; 4978 new_bus->parent = &pdev->dev; 4979 new_bus->irq[0] = PHY_MAC_INTERRUPT; 4980 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 4981 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 4982 4983 new_bus->read = r8169_mdio_read_reg; 4984 new_bus->write = r8169_mdio_write_reg; 4985 4986 ret = devm_mdiobus_register(&pdev->dev, new_bus); 4987 if (ret) 4988 return ret; 4989 4990 tp->phydev = mdiobus_get_phy(new_bus, 0); 4991 if (!tp->phydev) { 4992 return -ENODEV; 4993 } else if (!tp->phydev->drv) { 4994 /* Most chip versions fail with the genphy driver. 4995 * Therefore ensure that the dedicated PHY driver is loaded. 4996 */ 4997 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 4998 tp->phydev->phy_id); 4999 return -EUNATCH; 5000 } 5001 5002 tp->phydev->mac_managed_pm = true; 5003 5004 phy_support_asym_pause(tp->phydev); 5005 5006 /* PHY will be woken up in rtl_open() */ 5007 phy_suspend(tp->phydev); 5008 5009 return 0; 5010 } 5011 5012 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5013 { 5014 rtl_enable_rxdvgate(tp); 5015 5016 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5017 msleep(1); 5018 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5019 5020 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5021 r8168g_wait_ll_share_fifo_ready(tp); 5022 5023 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5024 r8168g_wait_ll_share_fifo_ready(tp); 5025 } 5026 5027 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5028 { 5029 rtl_enable_rxdvgate(tp); 5030 5031 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5032 msleep(1); 5033 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5034 5035 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5036 r8168g_wait_ll_share_fifo_ready(tp); 5037 5038 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5039 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5040 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5041 r8168g_wait_ll_share_fifo_ready(tp); 5042 } 5043 5044 static void rtl_hw_initialize(struct rtl8169_private *tp) 5045 { 5046 switch (tp->mac_version) { 5047 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5048 rtl8168ep_stop_cmac(tp); 5049 fallthrough; 5050 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5051 rtl_hw_init_8168g(tp); 5052 break; 5053 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5054 rtl_hw_init_8125(tp); 5055 break; 5056 default: 5057 break; 5058 } 5059 } 5060 5061 static int rtl_jumbo_max(struct rtl8169_private *tp) 5062 { 5063 /* Non-GBit versions don't support jumbo frames */ 5064 if (!tp->supports_gmii) 5065 return 0; 5066 5067 switch (tp->mac_version) { 5068 /* RTL8169 */ 5069 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5070 return JUMBO_7K; 5071 /* RTL8168b */ 5072 case RTL_GIGA_MAC_VER_11: 5073 case RTL_GIGA_MAC_VER_17: 5074 return JUMBO_4K; 5075 /* RTL8168c */ 5076 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5077 return JUMBO_6K; 5078 default: 5079 return JUMBO_9K; 5080 } 5081 } 5082 5083 static void rtl_init_mac_address(struct rtl8169_private *tp) 5084 { 5085 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5086 struct net_device *dev = tp->dev; 5087 int rc; 5088 5089 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5090 if (!rc) 5091 goto done; 5092 5093 rtl_read_mac_address(tp, mac_addr); 5094 if (is_valid_ether_addr(mac_addr)) 5095 goto done; 5096 5097 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5098 if (is_valid_ether_addr(mac_addr)) 5099 goto done; 5100 5101 eth_random_addr(mac_addr); 5102 dev->addr_assign_type = NET_ADDR_RANDOM; 5103 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5104 done: 5105 eth_hw_addr_set(dev, mac_addr); 5106 rtl_rar_set(tp, mac_addr); 5107 } 5108 5109 /* register is set if system vendor successfully tested ASPM 1.2 */ 5110 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5111 { 5112 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5113 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5114 return true; 5115 5116 return false; 5117 } 5118 5119 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5120 { 5121 struct rtl8169_private *tp; 5122 int jumbo_max, region, rc; 5123 enum mac_version chipset; 5124 struct net_device *dev; 5125 u32 txconfig; 5126 u16 xid; 5127 5128 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5129 if (!dev) 5130 return -ENOMEM; 5131 5132 SET_NETDEV_DEV(dev, &pdev->dev); 5133 dev->netdev_ops = &rtl_netdev_ops; 5134 tp = netdev_priv(dev); 5135 tp->dev = dev; 5136 tp->pci_dev = pdev; 5137 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5138 tp->eee_adv = -1; 5139 tp->ocp_base = OCP_STD_PHY_BASE; 5140 5141 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5142 raw_spin_lock_init(&tp->config25_lock); 5143 raw_spin_lock_init(&tp->mac_ocp_lock); 5144 5145 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5146 struct pcpu_sw_netstats); 5147 if (!dev->tstats) 5148 return -ENOMEM; 5149 5150 /* Get the *optional* external "ether_clk" used on some boards */ 5151 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5152 if (IS_ERR(tp->clk)) 5153 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5154 5155 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5156 rc = pcim_enable_device(pdev); 5157 if (rc < 0) 5158 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5159 5160 if (pcim_set_mwi(pdev) < 0) 5161 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5162 5163 /* use first MMIO region */ 5164 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5165 if (region < 0) 5166 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5167 5168 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5169 if (rc < 0) 5170 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5171 5172 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5173 5174 txconfig = RTL_R32(tp, TxConfig); 5175 if (txconfig == ~0U) 5176 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5177 5178 xid = (txconfig >> 20) & 0xfcf; 5179 5180 /* Identify chip attached to board */ 5181 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5182 if (chipset == RTL_GIGA_MAC_NONE) 5183 return dev_err_probe(&pdev->dev, -ENODEV, 5184 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5185 xid); 5186 tp->mac_version = chipset; 5187 5188 /* Disable ASPM L1 as that cause random device stop working 5189 * problems as well as full system hangs for some PCIe devices users. 5190 */ 5191 if (rtl_aspm_is_safe(tp)) 5192 rc = 0; 5193 else 5194 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5195 tp->aspm_manageable = !rc; 5196 5197 tp->dash_type = rtl_get_dash_type(tp); 5198 tp->dash_enabled = rtl_dash_is_enabled(tp); 5199 5200 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5201 5202 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5203 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5204 dev->features |= NETIF_F_HIGHDMA; 5205 5206 rtl_init_rxcfg(tp); 5207 5208 rtl8169_irq_mask_and_ack(tp); 5209 5210 rtl_hw_initialize(tp); 5211 5212 rtl_hw_reset(tp); 5213 5214 rc = rtl_alloc_irq(tp); 5215 if (rc < 0) 5216 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5217 5218 tp->irq = pci_irq_vector(pdev, 0); 5219 5220 INIT_WORK(&tp->wk.work, rtl_task); 5221 5222 rtl_init_mac_address(tp); 5223 5224 dev->ethtool_ops = &rtl8169_ethtool_ops; 5225 5226 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5227 5228 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5229 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5230 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5231 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5232 5233 /* 5234 * Pretend we are using VLANs; This bypasses a nasty bug where 5235 * Interrupts stop flowing on high load on 8110SCd controllers. 5236 */ 5237 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5238 /* Disallow toggling */ 5239 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5240 5241 if (rtl_chip_supports_csum_v2(tp)) 5242 dev->hw_features |= NETIF_F_IPV6_CSUM; 5243 5244 dev->features |= dev->hw_features; 5245 5246 /* There has been a number of reports that using SG/TSO results in 5247 * tx timeouts. However for a lot of people SG/TSO works fine. 5248 * Therefore disable both features by default, but allow users to 5249 * enable them. Use at own risk! 5250 */ 5251 if (rtl_chip_supports_csum_v2(tp)) { 5252 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5253 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5254 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5255 } else { 5256 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5257 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5258 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5259 } 5260 5261 dev->hw_features |= NETIF_F_RXALL; 5262 dev->hw_features |= NETIF_F_RXFCS; 5263 5264 netdev_sw_irq_coalesce_default_on(dev); 5265 5266 /* configure chip for default features */ 5267 rtl8169_set_features(dev, dev->features); 5268 5269 if (!tp->dash_enabled) { 5270 rtl_set_d3_pll_down(tp, true); 5271 } else { 5272 rtl_set_d3_pll_down(tp, false); 5273 dev->wol_enabled = 1; 5274 } 5275 5276 jumbo_max = rtl_jumbo_max(tp); 5277 if (jumbo_max) 5278 dev->max_mtu = jumbo_max; 5279 5280 rtl_set_irq_mask(tp); 5281 5282 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5283 5284 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5285 &tp->counters_phys_addr, 5286 GFP_KERNEL); 5287 if (!tp->counters) 5288 return -ENOMEM; 5289 5290 pci_set_drvdata(pdev, tp); 5291 5292 rc = r8169_mdio_register(tp); 5293 if (rc) 5294 return rc; 5295 5296 rc = register_netdev(dev); 5297 if (rc) 5298 return rc; 5299 5300 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5301 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5302 5303 if (jumbo_max) 5304 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5305 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5306 "ok" : "ko"); 5307 5308 if (tp->dash_type != RTL_DASH_NONE) { 5309 netdev_info(dev, "DASH %s\n", 5310 tp->dash_enabled ? "enabled" : "disabled"); 5311 rtl8168_driver_start(tp); 5312 } 5313 5314 if (pci_dev_run_wake(pdev)) 5315 pm_runtime_put_sync(&pdev->dev); 5316 5317 return 0; 5318 } 5319 5320 static struct pci_driver rtl8169_pci_driver = { 5321 .name = KBUILD_MODNAME, 5322 .id_table = rtl8169_pci_tbl, 5323 .probe = rtl_init_one, 5324 .remove = rtl_remove_one, 5325 .shutdown = rtl_shutdown, 5326 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5327 }; 5328 5329 module_pci_driver(rtl8169_pci_driver); 5330