1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 61 #define MC_FILTER_LIMIT 32 62 63 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 65 66 #define R8169_REGS_SIZE 256 67 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 68 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 69 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 70 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 71 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 72 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 73 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 74 75 #define OCP_STD_PHY_BASE 0xa400 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 92 static const struct { 93 const char *name; 94 const char *fw_name; 95 } rtl_chip_infos[] = { 96 /* PCI devices. */ 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 102 /* PCI-E devices. */ 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 107 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 109 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 111 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 117 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 118 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 119 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 122 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 124 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 125 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 126 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 127 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 128 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 129 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 130 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 131 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 132 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 133 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 134 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 135 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 136 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 137 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 138 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 139 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 140 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 141 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 142 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 143 }; 144 145 static const struct pci_device_id rtl8169_pci_tbl[] = { 146 { PCI_VDEVICE(REALTEK, 0x2502) }, 147 { PCI_VDEVICE(REALTEK, 0x2600) }, 148 { PCI_VDEVICE(REALTEK, 0x8129) }, 149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 150 { PCI_VDEVICE(REALTEK, 0x8161) }, 151 { PCI_VDEVICE(REALTEK, 0x8162) }, 152 { PCI_VDEVICE(REALTEK, 0x8167) }, 153 { PCI_VDEVICE(REALTEK, 0x8168) }, 154 { PCI_VDEVICE(NCUBE, 0x8168) }, 155 { PCI_VDEVICE(REALTEK, 0x8169) }, 156 { PCI_VENDOR_ID_DLINK, 0x4300, 157 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 158 { PCI_VDEVICE(DLINK, 0x4300) }, 159 { PCI_VDEVICE(DLINK, 0x4302) }, 160 { PCI_VDEVICE(AT, 0xc107) }, 161 { PCI_VDEVICE(USR, 0x0116) }, 162 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 163 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 164 { PCI_VDEVICE(REALTEK, 0x8125) }, 165 { PCI_VDEVICE(REALTEK, 0x3000) }, 166 {} 167 }; 168 169 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 170 171 enum rtl_registers { 172 MAC0 = 0, /* Ethernet hardware address. */ 173 MAC4 = 4, 174 MAR0 = 8, /* Multicast filter. */ 175 CounterAddrLow = 0x10, 176 CounterAddrHigh = 0x14, 177 TxDescStartAddrLow = 0x20, 178 TxDescStartAddrHigh = 0x24, 179 TxHDescStartAddrLow = 0x28, 180 TxHDescStartAddrHigh = 0x2c, 181 FLASH = 0x30, 182 ERSR = 0x36, 183 ChipCmd = 0x37, 184 TxPoll = 0x38, 185 IntrMask = 0x3c, 186 IntrStatus = 0x3e, 187 188 TxConfig = 0x40, 189 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 190 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 191 192 RxConfig = 0x44, 193 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 194 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 195 #define RXCFG_FIFO_SHIFT 13 196 /* No threshold before first PCI xfer */ 197 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 198 #define RX_EARLY_OFF (1 << 11) 199 #define RXCFG_DMA_SHIFT 8 200 /* Unlimited maximum PCI burst. */ 201 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 202 203 Cfg9346 = 0x50, 204 Config0 = 0x51, 205 Config1 = 0x52, 206 Config2 = 0x53, 207 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 208 209 Config3 = 0x54, 210 Config4 = 0x55, 211 Config5 = 0x56, 212 PHYAR = 0x60, 213 PHYstatus = 0x6c, 214 RxMaxSize = 0xda, 215 CPlusCmd = 0xe0, 216 IntrMitigate = 0xe2, 217 218 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 219 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 220 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 221 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 222 223 #define RTL_COALESCE_T_MAX 0x0fU 224 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 225 226 RxDescAddrLow = 0xe4, 227 RxDescAddrHigh = 0xe8, 228 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 229 230 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 231 232 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 233 234 #define TxPacketMax (8064 >> 7) 235 #define EarlySize 0x27 236 237 FuncEvent = 0xf0, 238 FuncEventMask = 0xf4, 239 FuncPresetState = 0xf8, 240 IBCR0 = 0xf8, 241 IBCR2 = 0xf9, 242 IBIMR0 = 0xfa, 243 IBISR0 = 0xfb, 244 FuncForceEvent = 0xfc, 245 }; 246 247 enum rtl8168_8101_registers { 248 CSIDR = 0x64, 249 CSIAR = 0x68, 250 #define CSIAR_FLAG 0x80000000 251 #define CSIAR_WRITE_CMD 0x80000000 252 #define CSIAR_BYTE_ENABLE 0x0000f000 253 #define CSIAR_ADDR_MASK 0x00000fff 254 PMCH = 0x6f, 255 #define D3COLD_NO_PLL_DOWN BIT(7) 256 #define D3HOT_NO_PLL_DOWN BIT(6) 257 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 258 EPHYAR = 0x80, 259 #define EPHYAR_FLAG 0x80000000 260 #define EPHYAR_WRITE_CMD 0x80000000 261 #define EPHYAR_REG_MASK 0x1f 262 #define EPHYAR_REG_SHIFT 16 263 #define EPHYAR_DATA_MASK 0xffff 264 DLLPR = 0xd0, 265 #define PFM_EN (1 << 6) 266 #define TX_10M_PS_EN (1 << 7) 267 DBG_REG = 0xd1, 268 #define FIX_NAK_1 (1 << 4) 269 #define FIX_NAK_2 (1 << 3) 270 TWSI = 0xd2, 271 MCU = 0xd3, 272 #define NOW_IS_OOB (1 << 7) 273 #define TX_EMPTY (1 << 5) 274 #define RX_EMPTY (1 << 4) 275 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 276 #define EN_NDP (1 << 3) 277 #define EN_OOB_RESET (1 << 2) 278 #define LINK_LIST_RDY (1 << 1) 279 EFUSEAR = 0xdc, 280 #define EFUSEAR_FLAG 0x80000000 281 #define EFUSEAR_WRITE_CMD 0x80000000 282 #define EFUSEAR_READ_CMD 0x00000000 283 #define EFUSEAR_REG_MASK 0x03ff 284 #define EFUSEAR_REG_SHIFT 8 285 #define EFUSEAR_DATA_MASK 0xff 286 MISC_1 = 0xf2, 287 #define PFM_D3COLD_EN (1 << 6) 288 }; 289 290 enum rtl8168_registers { 291 LED_FREQ = 0x1a, 292 EEE_LED = 0x1b, 293 ERIDR = 0x70, 294 ERIAR = 0x74, 295 #define ERIAR_FLAG 0x80000000 296 #define ERIAR_WRITE_CMD 0x80000000 297 #define ERIAR_READ_CMD 0x00000000 298 #define ERIAR_ADDR_BYTE_ALIGN 4 299 #define ERIAR_TYPE_SHIFT 16 300 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 301 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 303 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_MASK_SHIFT 12 305 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 306 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 308 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 310 EPHY_RXER_NUM = 0x7c, 311 OCPDR = 0xb0, /* OCP GPHY access */ 312 #define OCPDR_WRITE_CMD 0x80000000 313 #define OCPDR_READ_CMD 0x00000000 314 #define OCPDR_REG_MASK 0x7f 315 #define OCPDR_GPHY_REG_SHIFT 16 316 #define OCPDR_DATA_MASK 0xffff 317 OCPAR = 0xb4, 318 #define OCPAR_FLAG 0x80000000 319 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 320 #define OCPAR_GPHY_READ_CMD 0x0000f060 321 GPHY_OCP = 0xb8, 322 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 323 MISC = 0xf0, /* 8168e only. */ 324 #define TXPLA_RST (1 << 29) 325 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 326 #define PWM_EN (1 << 22) 327 #define RXDV_GATED_EN (1 << 19) 328 #define EARLY_TALLY_EN (1 << 16) 329 }; 330 331 enum rtl8125_registers { 332 IntrMask_8125 = 0x38, 333 IntrStatus_8125 = 0x3c, 334 TxPoll_8125 = 0x90, 335 MAC0_BKP = 0x19e0, 336 EEE_TXIDLE_TIMER_8125 = 0x6048, 337 }; 338 339 #define RX_VLAN_INNER_8125 BIT(22) 340 #define RX_VLAN_OUTER_8125 BIT(23) 341 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 342 343 #define RX_FETCH_DFLT_8125 (8 << 27) 344 345 enum rtl_register_content { 346 /* InterruptStatusBits */ 347 SYSErr = 0x8000, 348 PCSTimeout = 0x4000, 349 SWInt = 0x0100, 350 TxDescUnavail = 0x0080, 351 RxFIFOOver = 0x0040, 352 LinkChg = 0x0020, 353 RxOverflow = 0x0010, 354 TxErr = 0x0008, 355 TxOK = 0x0004, 356 RxErr = 0x0002, 357 RxOK = 0x0001, 358 359 /* RxStatusDesc */ 360 RxRWT = (1 << 22), 361 RxRES = (1 << 21), 362 RxRUNT = (1 << 20), 363 RxCRC = (1 << 19), 364 365 /* ChipCmdBits */ 366 StopReq = 0x80, 367 CmdReset = 0x10, 368 CmdRxEnb = 0x08, 369 CmdTxEnb = 0x04, 370 RxBufEmpty = 0x01, 371 372 /* TXPoll register p.5 */ 373 HPQ = 0x80, /* Poll cmd on the high prio queue */ 374 NPQ = 0x40, /* Poll cmd on the low prio queue */ 375 FSWInt = 0x01, /* Forced software interrupt */ 376 377 /* Cfg9346Bits */ 378 Cfg9346_Lock = 0x00, 379 Cfg9346_Unlock = 0xc0, 380 381 /* rx_mode_bits */ 382 AcceptErr = 0x20, 383 AcceptRunt = 0x10, 384 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 385 AcceptBroadcast = 0x08, 386 AcceptMulticast = 0x04, 387 AcceptMyPhys = 0x02, 388 AcceptAllPhys = 0x01, 389 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 390 #define RX_CONFIG_ACCEPT_MASK 0x3f 391 392 /* TxConfigBits */ 393 TxInterFrameGapShift = 24, 394 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 395 396 /* Config1 register p.24 */ 397 LEDS1 = (1 << 7), 398 LEDS0 = (1 << 6), 399 Speed_down = (1 << 4), 400 MEMMAP = (1 << 3), 401 IOMAP = (1 << 2), 402 VPD = (1 << 1), 403 PMEnable = (1 << 0), /* Power Management Enable */ 404 405 /* Config2 register p. 25 */ 406 ClkReqEn = (1 << 7), /* Clock Request Enable */ 407 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 408 PCI_Clock_66MHz = 0x01, 409 PCI_Clock_33MHz = 0x00, 410 411 /* Config3 register p.25 */ 412 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 413 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 414 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 415 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 416 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 417 418 /* Config4 register */ 419 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 420 421 /* Config5 register p.27 */ 422 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 423 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 424 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 425 Spi_en = (1 << 3), 426 LanWake = (1 << 1), /* LanWake enable/disable */ 427 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 428 ASPM_en = (1 << 0), /* ASPM enable */ 429 430 /* CPlusCmd p.31 */ 431 EnableBist = (1 << 15), // 8168 8101 432 Mac_dbgo_oe = (1 << 14), // 8168 8101 433 EnAnaPLL = (1 << 14), // 8169 434 Normal_mode = (1 << 13), // unused 435 Force_half_dup = (1 << 12), // 8168 8101 436 Force_rxflow_en = (1 << 11), // 8168 8101 437 Force_txflow_en = (1 << 10), // 8168 8101 438 Cxpl_dbg_sel = (1 << 9), // 8168 8101 439 ASF = (1 << 8), // 8168 8101 440 PktCntrDisable = (1 << 7), // 8168 8101 441 Mac_dbgo_sel = 0x001c, // 8168 442 RxVlan = (1 << 6), 443 RxChkSum = (1 << 5), 444 PCIDAC = (1 << 4), 445 PCIMulRW = (1 << 3), 446 #define INTT_MASK GENMASK(1, 0) 447 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 448 449 /* rtl8169_PHYstatus */ 450 TBI_Enable = 0x80, 451 TxFlowCtrl = 0x40, 452 RxFlowCtrl = 0x20, 453 _1000bpsF = 0x10, 454 _100bps = 0x08, 455 _10bps = 0x04, 456 LinkStatus = 0x02, 457 FullDup = 0x01, 458 459 /* ResetCounterCommand */ 460 CounterReset = 0x1, 461 462 /* DumpCounterCommand */ 463 CounterDump = 0x8, 464 465 /* magic enable v2 */ 466 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 467 }; 468 469 enum rtl_desc_bit { 470 /* First doubleword. */ 471 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 472 RingEnd = (1 << 30), /* End of descriptor ring */ 473 FirstFrag = (1 << 29), /* First segment of a packet */ 474 LastFrag = (1 << 28), /* Final segment of a packet */ 475 }; 476 477 /* Generic case. */ 478 enum rtl_tx_desc_bit { 479 /* First doubleword. */ 480 TD_LSO = (1 << 27), /* Large Send Offload */ 481 #define TD_MSS_MAX 0x07ffu /* MSS value */ 482 483 /* Second doubleword. */ 484 TxVlanTag = (1 << 17), /* Add VLAN tag */ 485 }; 486 487 /* 8169, 8168b and 810x except 8102e. */ 488 enum rtl_tx_desc_bit_0 { 489 /* First doubleword. */ 490 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 491 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 492 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 493 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 494 }; 495 496 /* 8102e, 8168c and beyond. */ 497 enum rtl_tx_desc_bit_1 { 498 /* First doubleword. */ 499 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 500 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 501 #define GTTCPHO_SHIFT 18 502 #define GTTCPHO_MAX 0x7f 503 504 /* Second doubleword. */ 505 #define TCPHO_SHIFT 18 506 #define TCPHO_MAX 0x3ff 507 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 508 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 509 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 510 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 511 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 512 }; 513 514 enum rtl_rx_desc_bit { 515 /* Rx private */ 516 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 517 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 518 519 #define RxProtoUDP (PID1) 520 #define RxProtoTCP (PID0) 521 #define RxProtoIP (PID1 | PID0) 522 #define RxProtoMask RxProtoIP 523 524 IPFail = (1 << 16), /* IP checksum failed */ 525 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 526 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 527 528 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 529 530 RxVlanTag = (1 << 16), /* VLAN tag available */ 531 }; 532 533 #define RTL_GSO_MAX_SIZE_V1 32000 534 #define RTL_GSO_MAX_SEGS_V1 24 535 #define RTL_GSO_MAX_SIZE_V2 64000 536 #define RTL_GSO_MAX_SEGS_V2 64 537 538 struct TxDesc { 539 __le32 opts1; 540 __le32 opts2; 541 __le64 addr; 542 }; 543 544 struct RxDesc { 545 __le32 opts1; 546 __le32 opts2; 547 __le64 addr; 548 }; 549 550 struct ring_info { 551 struct sk_buff *skb; 552 u32 len; 553 }; 554 555 struct rtl8169_counters { 556 __le64 tx_packets; 557 __le64 rx_packets; 558 __le64 tx_errors; 559 __le32 rx_errors; 560 __le16 rx_missed; 561 __le16 align_errors; 562 __le32 tx_one_collision; 563 __le32 tx_multi_collision; 564 __le64 rx_unicast; 565 __le64 rx_broadcast; 566 __le32 rx_multicast; 567 __le16 tx_aborted; 568 __le16 tx_underun; 569 }; 570 571 struct rtl8169_tc_offsets { 572 bool inited; 573 __le64 tx_errors; 574 __le32 tx_multi_collision; 575 __le16 tx_aborted; 576 __le16 rx_missed; 577 }; 578 579 enum rtl_flag { 580 RTL_FLAG_TASK_ENABLED = 0, 581 RTL_FLAG_TASK_RESET_PENDING, 582 RTL_FLAG_TASK_TX_TIMEOUT, 583 RTL_FLAG_MAX 584 }; 585 586 enum rtl_dash_type { 587 RTL_DASH_NONE, 588 RTL_DASH_DP, 589 RTL_DASH_EP, 590 }; 591 592 struct rtl8169_private { 593 void __iomem *mmio_addr; /* memory map physical address */ 594 struct pci_dev *pci_dev; 595 struct net_device *dev; 596 struct phy_device *phydev; 597 struct napi_struct napi; 598 enum mac_version mac_version; 599 enum rtl_dash_type dash_type; 600 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 601 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 602 u32 dirty_tx; 603 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 604 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 605 dma_addr_t TxPhyAddr; 606 dma_addr_t RxPhyAddr; 607 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 608 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 609 u16 cp_cmd; 610 u32 irq_mask; 611 int irq; 612 struct clk *clk; 613 614 struct { 615 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 616 struct work_struct work; 617 } wk; 618 619 raw_spinlock_t config25_lock; 620 raw_spinlock_t mac_ocp_lock; 621 622 raw_spinlock_t cfg9346_usage_lock; 623 int cfg9346_usage_count; 624 625 unsigned supports_gmii:1; 626 unsigned aspm_manageable:1; 627 unsigned dash_enabled:1; 628 dma_addr_t counters_phys_addr; 629 struct rtl8169_counters *counters; 630 struct rtl8169_tc_offsets tc_offset; 631 u32 saved_wolopts; 632 int eee_adv; 633 634 const char *fw_name; 635 struct rtl_fw *rtl_fw; 636 637 u32 ocp_base; 638 }; 639 640 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 641 642 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 643 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 644 MODULE_SOFTDEP("pre: realtek"); 645 MODULE_LICENSE("GPL"); 646 MODULE_FIRMWARE(FIRMWARE_8168D_1); 647 MODULE_FIRMWARE(FIRMWARE_8168D_2); 648 MODULE_FIRMWARE(FIRMWARE_8168E_1); 649 MODULE_FIRMWARE(FIRMWARE_8168E_2); 650 MODULE_FIRMWARE(FIRMWARE_8168E_3); 651 MODULE_FIRMWARE(FIRMWARE_8105E_1); 652 MODULE_FIRMWARE(FIRMWARE_8168F_1); 653 MODULE_FIRMWARE(FIRMWARE_8168F_2); 654 MODULE_FIRMWARE(FIRMWARE_8402_1); 655 MODULE_FIRMWARE(FIRMWARE_8411_1); 656 MODULE_FIRMWARE(FIRMWARE_8411_2); 657 MODULE_FIRMWARE(FIRMWARE_8106E_1); 658 MODULE_FIRMWARE(FIRMWARE_8106E_2); 659 MODULE_FIRMWARE(FIRMWARE_8168G_2); 660 MODULE_FIRMWARE(FIRMWARE_8168G_3); 661 MODULE_FIRMWARE(FIRMWARE_8168H_2); 662 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 663 MODULE_FIRMWARE(FIRMWARE_8107E_2); 664 MODULE_FIRMWARE(FIRMWARE_8125A_3); 665 MODULE_FIRMWARE(FIRMWARE_8125B_2); 666 667 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 668 { 669 return &tp->pci_dev->dev; 670 } 671 672 static void rtl_lock_config_regs(struct rtl8169_private *tp) 673 { 674 unsigned long flags; 675 676 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 677 if (!--tp->cfg9346_usage_count) 678 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 679 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 680 } 681 682 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 683 { 684 unsigned long flags; 685 686 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 687 if (!tp->cfg9346_usage_count++) 688 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 689 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 690 } 691 692 static void rtl_pci_commit(struct rtl8169_private *tp) 693 { 694 /* Read an arbitrary register to commit a preceding PCI write */ 695 RTL_R8(tp, ChipCmd); 696 } 697 698 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 699 { 700 unsigned long flags; 701 u8 val; 702 703 raw_spin_lock_irqsave(&tp->config25_lock, flags); 704 val = RTL_R8(tp, Config2); 705 RTL_W8(tp, Config2, (val & ~clear) | set); 706 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 707 } 708 709 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 710 { 711 unsigned long flags; 712 u8 val; 713 714 raw_spin_lock_irqsave(&tp->config25_lock, flags); 715 val = RTL_R8(tp, Config5); 716 RTL_W8(tp, Config5, (val & ~clear) | set); 717 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 718 } 719 720 static bool rtl_is_8125(struct rtl8169_private *tp) 721 { 722 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 723 } 724 725 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 726 { 727 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 728 tp->mac_version != RTL_GIGA_MAC_VER_39 && 729 tp->mac_version <= RTL_GIGA_MAC_VER_53; 730 } 731 732 static bool rtl_supports_eee(struct rtl8169_private *tp) 733 { 734 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 735 tp->mac_version != RTL_GIGA_MAC_VER_37 && 736 tp->mac_version != RTL_GIGA_MAC_VER_39; 737 } 738 739 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 740 { 741 int i; 742 743 for (i = 0; i < ETH_ALEN; i++) 744 mac[i] = RTL_R8(tp, reg + i); 745 } 746 747 struct rtl_cond { 748 bool (*check)(struct rtl8169_private *); 749 const char *msg; 750 }; 751 752 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 753 unsigned long usecs, int n, bool high) 754 { 755 int i; 756 757 for (i = 0; i < n; i++) { 758 if (c->check(tp) == high) 759 return true; 760 fsleep(usecs); 761 } 762 763 if (net_ratelimit()) 764 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 765 c->msg, !high, n, usecs); 766 return false; 767 } 768 769 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 770 const struct rtl_cond *c, 771 unsigned long d, int n) 772 { 773 return rtl_loop_wait(tp, c, d, n, true); 774 } 775 776 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 777 const struct rtl_cond *c, 778 unsigned long d, int n) 779 { 780 return rtl_loop_wait(tp, c, d, n, false); 781 } 782 783 #define DECLARE_RTL_COND(name) \ 784 static bool name ## _check(struct rtl8169_private *); \ 785 \ 786 static const struct rtl_cond name = { \ 787 .check = name ## _check, \ 788 .msg = #name \ 789 }; \ 790 \ 791 static bool name ## _check(struct rtl8169_private *tp) 792 793 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 794 { 795 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 796 if (type == ERIAR_OOB && 797 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 798 tp->mac_version == RTL_GIGA_MAC_VER_53)) 799 *cmd |= 0xf70 << 18; 800 } 801 802 DECLARE_RTL_COND(rtl_eriar_cond) 803 { 804 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 805 } 806 807 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 808 u32 val, int type) 809 { 810 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 811 812 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 813 return; 814 815 RTL_W32(tp, ERIDR, val); 816 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 817 RTL_W32(tp, ERIAR, cmd); 818 819 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 820 } 821 822 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 823 u32 val) 824 { 825 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 826 } 827 828 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 829 { 830 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 831 832 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 833 RTL_W32(tp, ERIAR, cmd); 834 835 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 836 RTL_R32(tp, ERIDR) : ~0; 837 } 838 839 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 840 { 841 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 842 } 843 844 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 845 { 846 u32 val = rtl_eri_read(tp, addr); 847 848 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 849 } 850 851 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 852 { 853 rtl_w0w1_eri(tp, addr, p, 0); 854 } 855 856 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 857 { 858 rtl_w0w1_eri(tp, addr, 0, m); 859 } 860 861 static bool rtl_ocp_reg_failure(u32 reg) 862 { 863 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 864 } 865 866 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 867 { 868 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 869 } 870 871 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 872 { 873 if (rtl_ocp_reg_failure(reg)) 874 return; 875 876 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 877 878 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 879 } 880 881 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 882 { 883 if (rtl_ocp_reg_failure(reg)) 884 return 0; 885 886 RTL_W32(tp, GPHY_OCP, reg << 15); 887 888 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 889 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 890 } 891 892 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 893 { 894 if (rtl_ocp_reg_failure(reg)) 895 return; 896 897 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 898 } 899 900 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 901 { 902 unsigned long flags; 903 904 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 905 __r8168_mac_ocp_write(tp, reg, data); 906 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 907 } 908 909 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 910 { 911 if (rtl_ocp_reg_failure(reg)) 912 return 0; 913 914 RTL_W32(tp, OCPDR, reg << 15); 915 916 return RTL_R32(tp, OCPDR); 917 } 918 919 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 920 { 921 unsigned long flags; 922 u16 val; 923 924 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 925 val = __r8168_mac_ocp_read(tp, reg); 926 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 927 928 return val; 929 } 930 931 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 932 u16 set) 933 { 934 unsigned long flags; 935 u16 data; 936 937 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 938 data = __r8168_mac_ocp_read(tp, reg); 939 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 940 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 941 } 942 943 /* Work around a hw issue with RTL8168g PHY, the quirk disables 944 * PHY MCU interrupts before PHY power-down. 945 */ 946 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 947 { 948 switch (tp->mac_version) { 949 case RTL_GIGA_MAC_VER_40: 950 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 951 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 952 else 953 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 954 break; 955 default: 956 break; 957 } 958 }; 959 960 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 961 { 962 if (reg == 0x1f) { 963 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 964 return; 965 } 966 967 if (tp->ocp_base != OCP_STD_PHY_BASE) 968 reg -= 0x10; 969 970 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 971 rtl8168g_phy_suspend_quirk(tp, value); 972 973 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 974 } 975 976 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 977 { 978 if (reg == 0x1f) 979 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 980 981 if (tp->ocp_base != OCP_STD_PHY_BASE) 982 reg -= 0x10; 983 984 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 985 } 986 987 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 988 { 989 if (reg == 0x1f) { 990 tp->ocp_base = value << 4; 991 return; 992 } 993 994 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 995 } 996 997 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 998 { 999 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1000 } 1001 1002 DECLARE_RTL_COND(rtl_phyar_cond) 1003 { 1004 return RTL_R32(tp, PHYAR) & 0x80000000; 1005 } 1006 1007 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1008 { 1009 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1010 1011 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1012 /* 1013 * According to hardware specs a 20us delay is required after write 1014 * complete indication, but before sending next command. 1015 */ 1016 udelay(20); 1017 } 1018 1019 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1020 { 1021 int value; 1022 1023 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1024 1025 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1026 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1027 1028 /* 1029 * According to hardware specs a 20us delay is required after read 1030 * complete indication, but before sending next command. 1031 */ 1032 udelay(20); 1033 1034 return value; 1035 } 1036 1037 DECLARE_RTL_COND(rtl_ocpar_cond) 1038 { 1039 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1040 } 1041 1042 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1043 1044 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1045 { 1046 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1047 } 1048 1049 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1050 { 1051 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1052 } 1053 1054 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1055 { 1056 r8168dp_2_mdio_start(tp); 1057 1058 r8169_mdio_write(tp, reg, value); 1059 1060 r8168dp_2_mdio_stop(tp); 1061 } 1062 1063 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1064 { 1065 int value; 1066 1067 /* Work around issue with chip reporting wrong PHY ID */ 1068 if (reg == MII_PHYSID2) 1069 return 0xc912; 1070 1071 r8168dp_2_mdio_start(tp); 1072 1073 value = r8169_mdio_read(tp, reg); 1074 1075 r8168dp_2_mdio_stop(tp); 1076 1077 return value; 1078 } 1079 1080 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1081 { 1082 switch (tp->mac_version) { 1083 case RTL_GIGA_MAC_VER_28: 1084 case RTL_GIGA_MAC_VER_31: 1085 r8168dp_2_mdio_write(tp, location, val); 1086 break; 1087 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1088 r8168g_mdio_write(tp, location, val); 1089 break; 1090 default: 1091 r8169_mdio_write(tp, location, val); 1092 break; 1093 } 1094 } 1095 1096 static int rtl_readphy(struct rtl8169_private *tp, int location) 1097 { 1098 switch (tp->mac_version) { 1099 case RTL_GIGA_MAC_VER_28: 1100 case RTL_GIGA_MAC_VER_31: 1101 return r8168dp_2_mdio_read(tp, location); 1102 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1103 return r8168g_mdio_read(tp, location); 1104 default: 1105 return r8169_mdio_read(tp, location); 1106 } 1107 } 1108 1109 DECLARE_RTL_COND(rtl_ephyar_cond) 1110 { 1111 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1112 } 1113 1114 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1115 { 1116 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1117 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1118 1119 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1120 1121 udelay(10); 1122 } 1123 1124 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1125 { 1126 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1127 1128 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1129 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1130 } 1131 1132 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1133 { 1134 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1135 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1136 RTL_R32(tp, OCPDR) : ~0; 1137 } 1138 1139 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1140 { 1141 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1142 } 1143 1144 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1145 u32 data) 1146 { 1147 RTL_W32(tp, OCPDR, data); 1148 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1149 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1150 } 1151 1152 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1153 u32 data) 1154 { 1155 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1156 data, ERIAR_OOB); 1157 } 1158 1159 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1160 { 1161 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1162 1163 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1164 } 1165 1166 #define OOB_CMD_RESET 0x00 1167 #define OOB_CMD_DRIVER_START 0x05 1168 #define OOB_CMD_DRIVER_STOP 0x06 1169 1170 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1171 { 1172 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1173 } 1174 1175 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1176 { 1177 u16 reg; 1178 1179 reg = rtl8168_get_ocp_reg(tp); 1180 1181 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1182 } 1183 1184 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1185 { 1186 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1187 } 1188 1189 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1190 { 1191 return RTL_R8(tp, IBISR0) & 0x20; 1192 } 1193 1194 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1195 { 1196 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1197 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1198 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1199 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1200 } 1201 1202 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1203 { 1204 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1205 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1206 } 1207 1208 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1209 { 1210 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1211 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1212 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1213 } 1214 1215 static void rtl8168_driver_start(struct rtl8169_private *tp) 1216 { 1217 if (tp->dash_type == RTL_DASH_DP) 1218 rtl8168dp_driver_start(tp); 1219 else 1220 rtl8168ep_driver_start(tp); 1221 } 1222 1223 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1224 { 1225 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1226 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1227 } 1228 1229 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1230 { 1231 rtl8168ep_stop_cmac(tp); 1232 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1233 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1234 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1235 } 1236 1237 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1238 { 1239 if (tp->dash_type == RTL_DASH_DP) 1240 rtl8168dp_driver_stop(tp); 1241 else 1242 rtl8168ep_driver_stop(tp); 1243 } 1244 1245 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1246 { 1247 u16 reg = rtl8168_get_ocp_reg(tp); 1248 1249 return r8168dp_ocp_read(tp, reg) & BIT(15); 1250 } 1251 1252 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1253 { 1254 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1255 } 1256 1257 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1258 { 1259 switch (tp->dash_type) { 1260 case RTL_DASH_DP: 1261 return r8168dp_check_dash(tp); 1262 case RTL_DASH_EP: 1263 return r8168ep_check_dash(tp); 1264 default: 1265 return false; 1266 } 1267 } 1268 1269 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1270 { 1271 switch (tp->mac_version) { 1272 case RTL_GIGA_MAC_VER_28: 1273 case RTL_GIGA_MAC_VER_31: 1274 return RTL_DASH_DP; 1275 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1276 return RTL_DASH_EP; 1277 default: 1278 return RTL_DASH_NONE; 1279 } 1280 } 1281 1282 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1283 { 1284 switch (tp->mac_version) { 1285 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1286 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1287 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1288 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1289 if (enable) 1290 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1291 else 1292 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1293 break; 1294 default: 1295 break; 1296 } 1297 } 1298 1299 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1300 { 1301 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1302 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1303 } 1304 1305 DECLARE_RTL_COND(rtl_efusear_cond) 1306 { 1307 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1308 } 1309 1310 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1311 { 1312 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1313 1314 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1315 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1316 } 1317 1318 static u32 rtl_get_events(struct rtl8169_private *tp) 1319 { 1320 if (rtl_is_8125(tp)) 1321 return RTL_R32(tp, IntrStatus_8125); 1322 else 1323 return RTL_R16(tp, IntrStatus); 1324 } 1325 1326 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1327 { 1328 if (rtl_is_8125(tp)) 1329 RTL_W32(tp, IntrStatus_8125, bits); 1330 else 1331 RTL_W16(tp, IntrStatus, bits); 1332 } 1333 1334 static void rtl_irq_disable(struct rtl8169_private *tp) 1335 { 1336 if (rtl_is_8125(tp)) 1337 RTL_W32(tp, IntrMask_8125, 0); 1338 else 1339 RTL_W16(tp, IntrMask, 0); 1340 } 1341 1342 static void rtl_irq_enable(struct rtl8169_private *tp) 1343 { 1344 if (rtl_is_8125(tp)) 1345 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1346 else 1347 RTL_W16(tp, IntrMask, tp->irq_mask); 1348 } 1349 1350 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1351 { 1352 rtl_irq_disable(tp); 1353 rtl_ack_events(tp, 0xffffffff); 1354 rtl_pci_commit(tp); 1355 } 1356 1357 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1358 { 1359 struct phy_device *phydev = tp->phydev; 1360 1361 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1362 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1363 if (phydev->speed == SPEED_1000) { 1364 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1365 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1366 } else if (phydev->speed == SPEED_100) { 1367 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1368 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1369 } else { 1370 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1371 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1372 } 1373 rtl_reset_packet_filter(tp); 1374 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1375 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1376 if (phydev->speed == SPEED_1000) { 1377 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1378 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1379 } else { 1380 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1381 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1382 } 1383 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1384 if (phydev->speed == SPEED_10) { 1385 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1386 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1387 } else { 1388 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1389 } 1390 } 1391 } 1392 1393 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1394 1395 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1396 { 1397 struct rtl8169_private *tp = netdev_priv(dev); 1398 1399 wol->supported = WAKE_ANY; 1400 wol->wolopts = tp->saved_wolopts; 1401 } 1402 1403 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1404 { 1405 static const struct { 1406 u32 opt; 1407 u16 reg; 1408 u8 mask; 1409 } cfg[] = { 1410 { WAKE_PHY, Config3, LinkUp }, 1411 { WAKE_UCAST, Config5, UWF }, 1412 { WAKE_BCAST, Config5, BWF }, 1413 { WAKE_MCAST, Config5, MWF }, 1414 { WAKE_ANY, Config5, LanWake }, 1415 { WAKE_MAGIC, Config3, MagicPacket } 1416 }; 1417 unsigned int i, tmp = ARRAY_SIZE(cfg); 1418 unsigned long flags; 1419 u8 options; 1420 1421 rtl_unlock_config_regs(tp); 1422 1423 if (rtl_is_8168evl_up(tp)) { 1424 tmp--; 1425 if (wolopts & WAKE_MAGIC) 1426 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1427 else 1428 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1429 } else if (rtl_is_8125(tp)) { 1430 tmp--; 1431 if (wolopts & WAKE_MAGIC) 1432 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1433 else 1434 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1435 } 1436 1437 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1438 for (i = 0; i < tmp; i++) { 1439 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1440 if (wolopts & cfg[i].opt) 1441 options |= cfg[i].mask; 1442 RTL_W8(tp, cfg[i].reg, options); 1443 } 1444 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1445 1446 switch (tp->mac_version) { 1447 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1448 options = RTL_R8(tp, Config1) & ~PMEnable; 1449 if (wolopts) 1450 options |= PMEnable; 1451 RTL_W8(tp, Config1, options); 1452 break; 1453 case RTL_GIGA_MAC_VER_34: 1454 case RTL_GIGA_MAC_VER_37: 1455 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1456 if (wolopts) 1457 rtl_mod_config2(tp, 0, PME_SIGNAL); 1458 else 1459 rtl_mod_config2(tp, PME_SIGNAL, 0); 1460 break; 1461 default: 1462 break; 1463 } 1464 1465 rtl_lock_config_regs(tp); 1466 1467 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1468 1469 if (!tp->dash_enabled) { 1470 rtl_set_d3_pll_down(tp, !wolopts); 1471 tp->dev->wol_enabled = wolopts ? 1 : 0; 1472 } 1473 } 1474 1475 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1476 { 1477 struct rtl8169_private *tp = netdev_priv(dev); 1478 1479 if (wol->wolopts & ~WAKE_ANY) 1480 return -EINVAL; 1481 1482 tp->saved_wolopts = wol->wolopts; 1483 __rtl8169_set_wol(tp, tp->saved_wolopts); 1484 1485 return 0; 1486 } 1487 1488 static void rtl8169_get_drvinfo(struct net_device *dev, 1489 struct ethtool_drvinfo *info) 1490 { 1491 struct rtl8169_private *tp = netdev_priv(dev); 1492 struct rtl_fw *rtl_fw = tp->rtl_fw; 1493 1494 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1495 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1496 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1497 if (rtl_fw) 1498 strscpy(info->fw_version, rtl_fw->version, 1499 sizeof(info->fw_version)); 1500 } 1501 1502 static int rtl8169_get_regs_len(struct net_device *dev) 1503 { 1504 return R8169_REGS_SIZE; 1505 } 1506 1507 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1508 netdev_features_t features) 1509 { 1510 struct rtl8169_private *tp = netdev_priv(dev); 1511 1512 if (dev->mtu > TD_MSS_MAX) 1513 features &= ~NETIF_F_ALL_TSO; 1514 1515 if (dev->mtu > ETH_DATA_LEN && 1516 tp->mac_version > RTL_GIGA_MAC_VER_06) 1517 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1518 1519 return features; 1520 } 1521 1522 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1523 netdev_features_t features) 1524 { 1525 u32 rx_config = RTL_R32(tp, RxConfig); 1526 1527 if (features & NETIF_F_RXALL) 1528 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1529 else 1530 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1531 1532 if (rtl_is_8125(tp)) { 1533 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1534 rx_config |= RX_VLAN_8125; 1535 else 1536 rx_config &= ~RX_VLAN_8125; 1537 } 1538 1539 RTL_W32(tp, RxConfig, rx_config); 1540 } 1541 1542 static int rtl8169_set_features(struct net_device *dev, 1543 netdev_features_t features) 1544 { 1545 struct rtl8169_private *tp = netdev_priv(dev); 1546 1547 rtl_set_rx_config_features(tp, features); 1548 1549 if (features & NETIF_F_RXCSUM) 1550 tp->cp_cmd |= RxChkSum; 1551 else 1552 tp->cp_cmd &= ~RxChkSum; 1553 1554 if (!rtl_is_8125(tp)) { 1555 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1556 tp->cp_cmd |= RxVlan; 1557 else 1558 tp->cp_cmd &= ~RxVlan; 1559 } 1560 1561 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1562 rtl_pci_commit(tp); 1563 1564 return 0; 1565 } 1566 1567 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1568 { 1569 return (skb_vlan_tag_present(skb)) ? 1570 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1571 } 1572 1573 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1574 { 1575 u32 opts2 = le32_to_cpu(desc->opts2); 1576 1577 if (opts2 & RxVlanTag) 1578 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1579 } 1580 1581 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1582 void *p) 1583 { 1584 struct rtl8169_private *tp = netdev_priv(dev); 1585 u32 __iomem *data = tp->mmio_addr; 1586 u32 *dw = p; 1587 int i; 1588 1589 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1590 memcpy_fromio(dw++, data++, 4); 1591 } 1592 1593 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1594 "tx_packets", 1595 "rx_packets", 1596 "tx_errors", 1597 "rx_errors", 1598 "rx_missed", 1599 "align_errors", 1600 "tx_single_collisions", 1601 "tx_multi_collisions", 1602 "unicast", 1603 "broadcast", 1604 "multicast", 1605 "tx_aborted", 1606 "tx_underrun", 1607 }; 1608 1609 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1610 { 1611 switch (sset) { 1612 case ETH_SS_STATS: 1613 return ARRAY_SIZE(rtl8169_gstrings); 1614 default: 1615 return -EOPNOTSUPP; 1616 } 1617 } 1618 1619 DECLARE_RTL_COND(rtl_counters_cond) 1620 { 1621 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1622 } 1623 1624 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1625 { 1626 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1627 1628 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1629 rtl_pci_commit(tp); 1630 RTL_W32(tp, CounterAddrLow, cmd); 1631 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1632 1633 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1634 } 1635 1636 static void rtl8169_update_counters(struct rtl8169_private *tp) 1637 { 1638 u8 val = RTL_R8(tp, ChipCmd); 1639 1640 /* 1641 * Some chips are unable to dump tally counters when the receiver 1642 * is disabled. If 0xff chip may be in a PCI power-save state. 1643 */ 1644 if (val & CmdRxEnb && val != 0xff) 1645 rtl8169_do_counters(tp, CounterDump); 1646 } 1647 1648 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1649 { 1650 struct rtl8169_counters *counters = tp->counters; 1651 1652 /* 1653 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1654 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1655 * reset by a power cycle, while the counter values collected by the 1656 * driver are reset at every driver unload/load cycle. 1657 * 1658 * To make sure the HW values returned by @get_stats64 match the SW 1659 * values, we collect the initial values at first open(*) and use them 1660 * as offsets to normalize the values returned by @get_stats64. 1661 * 1662 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1663 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1664 * set at open time by rtl_hw_start. 1665 */ 1666 1667 if (tp->tc_offset.inited) 1668 return; 1669 1670 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1671 rtl8169_do_counters(tp, CounterReset); 1672 } else { 1673 rtl8169_update_counters(tp); 1674 tp->tc_offset.tx_errors = counters->tx_errors; 1675 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1676 tp->tc_offset.tx_aborted = counters->tx_aborted; 1677 tp->tc_offset.rx_missed = counters->rx_missed; 1678 } 1679 1680 tp->tc_offset.inited = true; 1681 } 1682 1683 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1684 struct ethtool_stats *stats, u64 *data) 1685 { 1686 struct rtl8169_private *tp = netdev_priv(dev); 1687 struct rtl8169_counters *counters; 1688 1689 counters = tp->counters; 1690 rtl8169_update_counters(tp); 1691 1692 data[0] = le64_to_cpu(counters->tx_packets); 1693 data[1] = le64_to_cpu(counters->rx_packets); 1694 data[2] = le64_to_cpu(counters->tx_errors); 1695 data[3] = le32_to_cpu(counters->rx_errors); 1696 data[4] = le16_to_cpu(counters->rx_missed); 1697 data[5] = le16_to_cpu(counters->align_errors); 1698 data[6] = le32_to_cpu(counters->tx_one_collision); 1699 data[7] = le32_to_cpu(counters->tx_multi_collision); 1700 data[8] = le64_to_cpu(counters->rx_unicast); 1701 data[9] = le64_to_cpu(counters->rx_broadcast); 1702 data[10] = le32_to_cpu(counters->rx_multicast); 1703 data[11] = le16_to_cpu(counters->tx_aborted); 1704 data[12] = le16_to_cpu(counters->tx_underun); 1705 } 1706 1707 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1708 { 1709 switch(stringset) { 1710 case ETH_SS_STATS: 1711 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1712 break; 1713 } 1714 } 1715 1716 /* 1717 * Interrupt coalescing 1718 * 1719 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1720 * > 8169, 8168 and 810x line of chipsets 1721 * 1722 * 8169, 8168, and 8136(810x) serial chipsets support it. 1723 * 1724 * > 2 - the Tx timer unit at gigabit speed 1725 * 1726 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1727 * (0xe0) bit 1 and bit 0. 1728 * 1729 * For 8169 1730 * bit[1:0] \ speed 1000M 100M 10M 1731 * 0 0 320ns 2.56us 40.96us 1732 * 0 1 2.56us 20.48us 327.7us 1733 * 1 0 5.12us 40.96us 655.4us 1734 * 1 1 10.24us 81.92us 1.31ms 1735 * 1736 * For the other 1737 * bit[1:0] \ speed 1000M 100M 10M 1738 * 0 0 5us 2.56us 40.96us 1739 * 0 1 40us 20.48us 327.7us 1740 * 1 0 80us 40.96us 655.4us 1741 * 1 1 160us 81.92us 1.31ms 1742 */ 1743 1744 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1745 struct rtl_coalesce_info { 1746 u32 speed; 1747 u32 scale_nsecs[4]; 1748 }; 1749 1750 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1751 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1752 1753 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1754 { SPEED_1000, COALESCE_DELAY(320) }, 1755 { SPEED_100, COALESCE_DELAY(2560) }, 1756 { SPEED_10, COALESCE_DELAY(40960) }, 1757 { 0 }, 1758 }; 1759 1760 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1761 { SPEED_1000, COALESCE_DELAY(5000) }, 1762 { SPEED_100, COALESCE_DELAY(2560) }, 1763 { SPEED_10, COALESCE_DELAY(40960) }, 1764 { 0 }, 1765 }; 1766 #undef COALESCE_DELAY 1767 1768 /* get rx/tx scale vector corresponding to current speed */ 1769 static const struct rtl_coalesce_info * 1770 rtl_coalesce_info(struct rtl8169_private *tp) 1771 { 1772 const struct rtl_coalesce_info *ci; 1773 1774 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1775 ci = rtl_coalesce_info_8169; 1776 else 1777 ci = rtl_coalesce_info_8168_8136; 1778 1779 /* if speed is unknown assume highest one */ 1780 if (tp->phydev->speed == SPEED_UNKNOWN) 1781 return ci; 1782 1783 for (; ci->speed; ci++) { 1784 if (tp->phydev->speed == ci->speed) 1785 return ci; 1786 } 1787 1788 return ERR_PTR(-ELNRNG); 1789 } 1790 1791 static int rtl_get_coalesce(struct net_device *dev, 1792 struct ethtool_coalesce *ec, 1793 struct kernel_ethtool_coalesce *kernel_coal, 1794 struct netlink_ext_ack *extack) 1795 { 1796 struct rtl8169_private *tp = netdev_priv(dev); 1797 const struct rtl_coalesce_info *ci; 1798 u32 scale, c_us, c_fr; 1799 u16 intrmit; 1800 1801 if (rtl_is_8125(tp)) 1802 return -EOPNOTSUPP; 1803 1804 memset(ec, 0, sizeof(*ec)); 1805 1806 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1807 ci = rtl_coalesce_info(tp); 1808 if (IS_ERR(ci)) 1809 return PTR_ERR(ci); 1810 1811 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1812 1813 intrmit = RTL_R16(tp, IntrMitigate); 1814 1815 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1816 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1817 1818 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1819 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1820 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1821 1822 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1823 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1824 1825 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1826 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1827 1828 return 0; 1829 } 1830 1831 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1832 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1833 u16 *cp01) 1834 { 1835 const struct rtl_coalesce_info *ci; 1836 u16 i; 1837 1838 ci = rtl_coalesce_info(tp); 1839 if (IS_ERR(ci)) 1840 return PTR_ERR(ci); 1841 1842 for (i = 0; i < 4; i++) { 1843 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1844 *cp01 = i; 1845 return ci->scale_nsecs[i]; 1846 } 1847 } 1848 1849 return -ERANGE; 1850 } 1851 1852 static int rtl_set_coalesce(struct net_device *dev, 1853 struct ethtool_coalesce *ec, 1854 struct kernel_ethtool_coalesce *kernel_coal, 1855 struct netlink_ext_ack *extack) 1856 { 1857 struct rtl8169_private *tp = netdev_priv(dev); 1858 u32 tx_fr = ec->tx_max_coalesced_frames; 1859 u32 rx_fr = ec->rx_max_coalesced_frames; 1860 u32 coal_usec_max, units; 1861 u16 w = 0, cp01 = 0; 1862 int scale; 1863 1864 if (rtl_is_8125(tp)) 1865 return -EOPNOTSUPP; 1866 1867 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1868 return -ERANGE; 1869 1870 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1871 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1872 if (scale < 0) 1873 return scale; 1874 1875 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1876 * not only when usecs=0 because of e.g. the following scenario: 1877 * 1878 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1879 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1880 * - then user does `ethtool -C eth0 rx-usecs 100` 1881 * 1882 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1883 * if we want to ignore rx_frames then it has to be set to 0. 1884 */ 1885 if (rx_fr == 1) 1886 rx_fr = 0; 1887 if (tx_fr == 1) 1888 tx_fr = 0; 1889 1890 /* HW requires time limit to be set if frame limit is set */ 1891 if ((tx_fr && !ec->tx_coalesce_usecs) || 1892 (rx_fr && !ec->rx_coalesce_usecs)) 1893 return -EINVAL; 1894 1895 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1896 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1897 1898 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1899 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1900 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1901 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1902 1903 RTL_W16(tp, IntrMitigate, w); 1904 1905 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1906 if (rtl_is_8168evl_up(tp)) { 1907 if (!rx_fr && !tx_fr) 1908 /* disable packet counter */ 1909 tp->cp_cmd |= PktCntrDisable; 1910 else 1911 tp->cp_cmd &= ~PktCntrDisable; 1912 } 1913 1914 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1915 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1916 rtl_pci_commit(tp); 1917 1918 return 0; 1919 } 1920 1921 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1922 { 1923 struct rtl8169_private *tp = netdev_priv(dev); 1924 1925 if (!rtl_supports_eee(tp)) 1926 return -EOPNOTSUPP; 1927 1928 return phy_ethtool_get_eee(tp->phydev, data); 1929 } 1930 1931 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1932 { 1933 struct rtl8169_private *tp = netdev_priv(dev); 1934 int ret; 1935 1936 if (!rtl_supports_eee(tp)) 1937 return -EOPNOTSUPP; 1938 1939 ret = phy_ethtool_set_eee(tp->phydev, data); 1940 1941 if (!ret) 1942 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1943 MDIO_AN_EEE_ADV); 1944 return ret; 1945 } 1946 1947 static void rtl8169_get_ringparam(struct net_device *dev, 1948 struct ethtool_ringparam *data, 1949 struct kernel_ethtool_ringparam *kernel_data, 1950 struct netlink_ext_ack *extack) 1951 { 1952 data->rx_max_pending = NUM_RX_DESC; 1953 data->rx_pending = NUM_RX_DESC; 1954 data->tx_max_pending = NUM_TX_DESC; 1955 data->tx_pending = NUM_TX_DESC; 1956 } 1957 1958 static void rtl8169_get_pauseparam(struct net_device *dev, 1959 struct ethtool_pauseparam *data) 1960 { 1961 struct rtl8169_private *tp = netdev_priv(dev); 1962 bool tx_pause, rx_pause; 1963 1964 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1965 1966 data->autoneg = tp->phydev->autoneg; 1967 data->tx_pause = tx_pause ? 1 : 0; 1968 data->rx_pause = rx_pause ? 1 : 0; 1969 } 1970 1971 static int rtl8169_set_pauseparam(struct net_device *dev, 1972 struct ethtool_pauseparam *data) 1973 { 1974 struct rtl8169_private *tp = netdev_priv(dev); 1975 1976 if (dev->mtu > ETH_DATA_LEN) 1977 return -EOPNOTSUPP; 1978 1979 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1980 1981 return 0; 1982 } 1983 1984 static const struct ethtool_ops rtl8169_ethtool_ops = { 1985 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1986 ETHTOOL_COALESCE_MAX_FRAMES, 1987 .get_drvinfo = rtl8169_get_drvinfo, 1988 .get_regs_len = rtl8169_get_regs_len, 1989 .get_link = ethtool_op_get_link, 1990 .get_coalesce = rtl_get_coalesce, 1991 .set_coalesce = rtl_set_coalesce, 1992 .get_regs = rtl8169_get_regs, 1993 .get_wol = rtl8169_get_wol, 1994 .set_wol = rtl8169_set_wol, 1995 .get_strings = rtl8169_get_strings, 1996 .get_sset_count = rtl8169_get_sset_count, 1997 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1998 .get_ts_info = ethtool_op_get_ts_info, 1999 .nway_reset = phy_ethtool_nway_reset, 2000 .get_eee = rtl8169_get_eee, 2001 .set_eee = rtl8169_set_eee, 2002 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2003 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2004 .get_ringparam = rtl8169_get_ringparam, 2005 .get_pauseparam = rtl8169_get_pauseparam, 2006 .set_pauseparam = rtl8169_set_pauseparam, 2007 }; 2008 2009 static void rtl_enable_eee(struct rtl8169_private *tp) 2010 { 2011 struct phy_device *phydev = tp->phydev; 2012 int adv; 2013 2014 /* respect EEE advertisement the user may have set */ 2015 if (tp->eee_adv >= 0) 2016 adv = tp->eee_adv; 2017 else 2018 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2019 2020 if (adv >= 0) 2021 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2022 } 2023 2024 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2025 { 2026 /* 2027 * The driver currently handles the 8168Bf and the 8168Be identically 2028 * but they can be identified more specifically through the test below 2029 * if needed: 2030 * 2031 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2032 * 2033 * Same thing for the 8101Eb and the 8101Ec: 2034 * 2035 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2036 */ 2037 static const struct rtl_mac_info { 2038 u16 mask; 2039 u16 val; 2040 enum mac_version ver; 2041 } mac_info[] = { 2042 /* 8125B family. */ 2043 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2044 2045 /* 8125A family. */ 2046 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2047 /* It seems only XID 609 made it to the mass market. 2048 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2049 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2050 */ 2051 2052 /* RTL8117 */ 2053 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2054 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2055 2056 /* 8168EP family. */ 2057 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2058 /* It seems this chip version never made it to 2059 * the wild. Let's disable detection. 2060 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2061 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2062 */ 2063 2064 /* 8168H family. */ 2065 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2066 /* It seems this chip version never made it to 2067 * the wild. Let's disable detection. 2068 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2069 */ 2070 2071 /* 8168G family. */ 2072 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2073 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2074 /* It seems this chip version never made it to 2075 * the wild. Let's disable detection. 2076 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2077 */ 2078 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2079 2080 /* 8168F family. */ 2081 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2082 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2083 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2084 2085 /* 8168E family. */ 2086 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2087 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2088 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2089 2090 /* 8168D family. */ 2091 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2092 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2093 2094 /* 8168DP family. */ 2095 /* It seems this early RTL8168dp version never made it to 2096 * the wild. Support has been removed. 2097 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2098 */ 2099 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2100 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2101 2102 /* 8168C family. */ 2103 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2104 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2105 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2106 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2107 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2108 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2109 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2110 2111 /* 8168B family. */ 2112 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2113 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2114 2115 /* 8101 family. */ 2116 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2117 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2118 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2119 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2120 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2121 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2122 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2123 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2124 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2125 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2126 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2127 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2128 2129 /* 8110 family. */ 2130 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2131 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2132 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2133 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2134 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2135 2136 /* Catch-all */ 2137 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2138 }; 2139 const struct rtl_mac_info *p = mac_info; 2140 enum mac_version ver; 2141 2142 while ((xid & p->mask) != p->val) 2143 p++; 2144 ver = p->ver; 2145 2146 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2147 if (ver == RTL_GIGA_MAC_VER_42) 2148 ver = RTL_GIGA_MAC_VER_43; 2149 else if (ver == RTL_GIGA_MAC_VER_46) 2150 ver = RTL_GIGA_MAC_VER_48; 2151 } 2152 2153 return ver; 2154 } 2155 2156 static void rtl_release_firmware(struct rtl8169_private *tp) 2157 { 2158 if (tp->rtl_fw) { 2159 rtl_fw_release_firmware(tp->rtl_fw); 2160 kfree(tp->rtl_fw); 2161 tp->rtl_fw = NULL; 2162 } 2163 } 2164 2165 void r8169_apply_firmware(struct rtl8169_private *tp) 2166 { 2167 int val; 2168 2169 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2170 if (tp->rtl_fw) { 2171 rtl_fw_write_firmware(tp, tp->rtl_fw); 2172 /* At least one firmware doesn't reset tp->ocp_base. */ 2173 tp->ocp_base = OCP_STD_PHY_BASE; 2174 2175 /* PHY soft reset may still be in progress */ 2176 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2177 !(val & BMCR_RESET), 2178 50000, 600000, true); 2179 } 2180 } 2181 2182 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2183 { 2184 /* Adjust EEE LED frequency */ 2185 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2186 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2187 2188 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2189 } 2190 2191 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2192 { 2193 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2194 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2195 } 2196 2197 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2198 { 2199 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2200 } 2201 2202 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2203 { 2204 rtl8125_set_eee_txidle_timer(tp); 2205 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2206 } 2207 2208 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2209 { 2210 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2211 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2212 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2213 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2214 } 2215 2216 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2217 { 2218 u16 data1, data2, ioffset; 2219 2220 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2221 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2222 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2223 2224 ioffset = (data2 >> 1) & 0x7ff8; 2225 ioffset |= data2 & 0x0007; 2226 if (data1 & BIT(7)) 2227 ioffset |= BIT(15); 2228 2229 return ioffset; 2230 } 2231 2232 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2233 { 2234 set_bit(flag, tp->wk.flags); 2235 schedule_work(&tp->wk.work); 2236 } 2237 2238 static void rtl8169_init_phy(struct rtl8169_private *tp) 2239 { 2240 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2241 2242 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2243 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2244 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2245 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2246 RTL_W8(tp, 0x82, 0x01); 2247 } 2248 2249 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2250 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2251 tp->pci_dev->subsystem_device == 0xe000) 2252 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2253 2254 /* We may have called phy_speed_down before */ 2255 phy_speed_up(tp->phydev); 2256 2257 if (rtl_supports_eee(tp)) 2258 rtl_enable_eee(tp); 2259 2260 genphy_soft_reset(tp->phydev); 2261 } 2262 2263 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2264 { 2265 rtl_unlock_config_regs(tp); 2266 2267 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2268 rtl_pci_commit(tp); 2269 2270 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2271 rtl_pci_commit(tp); 2272 2273 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2274 rtl_rar_exgmac_set(tp, addr); 2275 2276 rtl_lock_config_regs(tp); 2277 } 2278 2279 static int rtl_set_mac_address(struct net_device *dev, void *p) 2280 { 2281 struct rtl8169_private *tp = netdev_priv(dev); 2282 int ret; 2283 2284 ret = eth_mac_addr(dev, p); 2285 if (ret) 2286 return ret; 2287 2288 rtl_rar_set(tp, dev->dev_addr); 2289 2290 return 0; 2291 } 2292 2293 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2294 { 2295 switch (tp->mac_version) { 2296 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2297 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2298 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2299 break; 2300 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2301 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2302 case RTL_GIGA_MAC_VER_38: 2303 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2304 break; 2305 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2306 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2307 break; 2308 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2309 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2310 break; 2311 default: 2312 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2313 break; 2314 } 2315 } 2316 2317 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2318 { 2319 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2320 } 2321 2322 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2323 { 2324 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2325 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2326 } 2327 2328 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2329 { 2330 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2331 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2332 } 2333 2334 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2335 { 2336 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2337 } 2338 2339 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2340 { 2341 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2342 } 2343 2344 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2345 { 2346 RTL_W8(tp, MaxTxPacketSize, 0x24); 2347 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2348 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2349 } 2350 2351 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2352 { 2353 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2354 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2355 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2356 } 2357 2358 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2359 { 2360 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2361 } 2362 2363 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2364 { 2365 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2366 } 2367 2368 static void rtl_jumbo_config(struct rtl8169_private *tp) 2369 { 2370 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2371 int readrq = 4096; 2372 2373 rtl_unlock_config_regs(tp); 2374 switch (tp->mac_version) { 2375 case RTL_GIGA_MAC_VER_17: 2376 if (jumbo) { 2377 readrq = 512; 2378 r8168b_1_hw_jumbo_enable(tp); 2379 } else { 2380 r8168b_1_hw_jumbo_disable(tp); 2381 } 2382 break; 2383 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2384 if (jumbo) { 2385 readrq = 512; 2386 r8168c_hw_jumbo_enable(tp); 2387 } else { 2388 r8168c_hw_jumbo_disable(tp); 2389 } 2390 break; 2391 case RTL_GIGA_MAC_VER_28: 2392 if (jumbo) 2393 r8168dp_hw_jumbo_enable(tp); 2394 else 2395 r8168dp_hw_jumbo_disable(tp); 2396 break; 2397 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2398 if (jumbo) 2399 r8168e_hw_jumbo_enable(tp); 2400 else 2401 r8168e_hw_jumbo_disable(tp); 2402 break; 2403 default: 2404 break; 2405 } 2406 rtl_lock_config_regs(tp); 2407 2408 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2409 pcie_set_readrq(tp->pci_dev, readrq); 2410 2411 /* Chip doesn't support pause in jumbo mode */ 2412 if (jumbo) { 2413 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2414 tp->phydev->advertising); 2415 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2416 tp->phydev->advertising); 2417 phy_start_aneg(tp->phydev); 2418 } 2419 } 2420 2421 DECLARE_RTL_COND(rtl_chipcmd_cond) 2422 { 2423 return RTL_R8(tp, ChipCmd) & CmdReset; 2424 } 2425 2426 static void rtl_hw_reset(struct rtl8169_private *tp) 2427 { 2428 RTL_W8(tp, ChipCmd, CmdReset); 2429 2430 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2431 } 2432 2433 static void rtl_request_firmware(struct rtl8169_private *tp) 2434 { 2435 struct rtl_fw *rtl_fw; 2436 2437 /* firmware loaded already or no firmware available */ 2438 if (tp->rtl_fw || !tp->fw_name) 2439 return; 2440 2441 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2442 if (!rtl_fw) 2443 return; 2444 2445 rtl_fw->phy_write = rtl_writephy; 2446 rtl_fw->phy_read = rtl_readphy; 2447 rtl_fw->mac_mcu_write = mac_mcu_write; 2448 rtl_fw->mac_mcu_read = mac_mcu_read; 2449 rtl_fw->fw_name = tp->fw_name; 2450 rtl_fw->dev = tp_to_dev(tp); 2451 2452 if (rtl_fw_request_firmware(rtl_fw)) 2453 kfree(rtl_fw); 2454 else 2455 tp->rtl_fw = rtl_fw; 2456 } 2457 2458 static void rtl_rx_close(struct rtl8169_private *tp) 2459 { 2460 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2461 } 2462 2463 DECLARE_RTL_COND(rtl_npq_cond) 2464 { 2465 return RTL_R8(tp, TxPoll) & NPQ; 2466 } 2467 2468 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2469 { 2470 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2471 } 2472 2473 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2474 { 2475 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2476 } 2477 2478 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2479 { 2480 /* IntrMitigate has new functionality on RTL8125 */ 2481 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2482 } 2483 2484 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2485 { 2486 switch (tp->mac_version) { 2487 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2488 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2489 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2490 break; 2491 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2492 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2493 break; 2494 case RTL_GIGA_MAC_VER_63: 2495 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2496 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2497 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2498 break; 2499 default: 2500 break; 2501 } 2502 } 2503 2504 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2505 { 2506 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2507 } 2508 2509 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2510 { 2511 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2512 fsleep(2000); 2513 rtl_wait_txrx_fifo_empty(tp); 2514 } 2515 2516 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2517 { 2518 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2519 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2520 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2521 2522 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2523 rtl_disable_rxdvgate(tp); 2524 } 2525 2526 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2527 { 2528 if (tp->dash_enabled) 2529 return; 2530 2531 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2532 tp->mac_version == RTL_GIGA_MAC_VER_33) 2533 rtl_ephy_write(tp, 0x19, 0xff64); 2534 2535 if (device_may_wakeup(tp_to_dev(tp))) { 2536 phy_speed_down(tp->phydev, false); 2537 rtl_wol_enable_rx(tp); 2538 } 2539 } 2540 2541 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2542 { 2543 u32 val = TX_DMA_BURST << TxDMAShift | 2544 InterFrameGap << TxInterFrameGapShift; 2545 2546 if (rtl_is_8168evl_up(tp)) 2547 val |= TXCFG_AUTO_FIFO; 2548 2549 RTL_W32(tp, TxConfig, val); 2550 } 2551 2552 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2553 { 2554 /* Low hurts. Let's disable the filtering. */ 2555 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2556 } 2557 2558 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2559 { 2560 /* 2561 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2562 * register to be written before TxDescAddrLow to work. 2563 * Switching from MMIO to I/O access fixes the issue as well. 2564 */ 2565 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2566 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2567 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2568 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2569 } 2570 2571 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2572 { 2573 u32 val; 2574 2575 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2576 val = 0x000fff00; 2577 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2578 val = 0x00ffff00; 2579 else 2580 return; 2581 2582 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2583 val |= 0xff; 2584 2585 RTL_W32(tp, 0x7c, val); 2586 } 2587 2588 static void rtl_set_rx_mode(struct net_device *dev) 2589 { 2590 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2591 /* Multicast hash filter */ 2592 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2593 struct rtl8169_private *tp = netdev_priv(dev); 2594 u32 tmp; 2595 2596 if (dev->flags & IFF_PROMISC) { 2597 rx_mode |= AcceptAllPhys; 2598 } else if (!(dev->flags & IFF_MULTICAST)) { 2599 rx_mode &= ~AcceptMulticast; 2600 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2601 dev->flags & IFF_ALLMULTI || 2602 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2603 /* accept all multicasts */ 2604 } else if (netdev_mc_empty(dev)) { 2605 rx_mode &= ~AcceptMulticast; 2606 } else { 2607 struct netdev_hw_addr *ha; 2608 2609 mc_filter[1] = mc_filter[0] = 0; 2610 netdev_for_each_mc_addr(ha, dev) { 2611 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2612 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2613 } 2614 2615 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2616 tmp = mc_filter[0]; 2617 mc_filter[0] = swab32(mc_filter[1]); 2618 mc_filter[1] = swab32(tmp); 2619 } 2620 } 2621 2622 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2623 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2624 2625 tmp = RTL_R32(tp, RxConfig); 2626 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2627 } 2628 2629 DECLARE_RTL_COND(rtl_csiar_cond) 2630 { 2631 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2632 } 2633 2634 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2635 { 2636 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2637 2638 RTL_W32(tp, CSIDR, value); 2639 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2640 CSIAR_BYTE_ENABLE | func << 16); 2641 2642 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2643 } 2644 2645 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2646 { 2647 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2648 2649 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2650 CSIAR_BYTE_ENABLE); 2651 2652 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2653 RTL_R32(tp, CSIDR) : ~0; 2654 } 2655 2656 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2657 { 2658 struct pci_dev *pdev = tp->pci_dev; 2659 u32 csi; 2660 2661 /* According to Realtek the value at config space address 0x070f 2662 * controls the L0s/L1 entrance latency. We try standard ECAM access 2663 * first and if it fails fall back to CSI. 2664 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2665 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2666 */ 2667 if (pdev->cfg_size > 0x070f && 2668 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2669 return; 2670 2671 netdev_notice_once(tp->dev, 2672 "No native access to PCI extended config space, falling back to CSI\n"); 2673 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2674 rtl_csi_write(tp, 0x070c, csi | val << 24); 2675 } 2676 2677 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2678 { 2679 /* L0 7us, L1 16us */ 2680 rtl_set_aspm_entry_latency(tp, 0x27); 2681 } 2682 2683 struct ephy_info { 2684 unsigned int offset; 2685 u16 mask; 2686 u16 bits; 2687 }; 2688 2689 static void __rtl_ephy_init(struct rtl8169_private *tp, 2690 const struct ephy_info *e, int len) 2691 { 2692 u16 w; 2693 2694 while (len-- > 0) { 2695 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2696 rtl_ephy_write(tp, e->offset, w); 2697 e++; 2698 } 2699 } 2700 2701 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2702 2703 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2704 { 2705 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2706 PCI_EXP_LNKCTL_CLKREQ_EN); 2707 } 2708 2709 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2710 { 2711 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2712 PCI_EXP_LNKCTL_CLKREQ_EN); 2713 } 2714 2715 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2716 { 2717 /* work around an issue when PCI reset occurs during L2/L3 state */ 2718 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2719 } 2720 2721 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2722 { 2723 /* Bits control which events trigger ASPM L1 exit: 2724 * Bit 12: rxdv 2725 * Bit 11: ltr_msg 2726 * Bit 10: txdma_poll 2727 * Bit 9: xadm 2728 * Bit 8: pktavi 2729 * Bit 7: txpla 2730 */ 2731 switch (tp->mac_version) { 2732 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2733 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2734 break; 2735 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2736 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2737 break; 2738 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2739 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2740 break; 2741 default: 2742 break; 2743 } 2744 } 2745 2746 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2747 { 2748 switch (tp->mac_version) { 2749 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2750 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2751 break; 2752 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2753 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2754 break; 2755 default: 2756 break; 2757 } 2758 } 2759 2760 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2761 { 2762 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2763 return; 2764 2765 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2766 if (enable && tp->aspm_manageable) { 2767 /* On these chip versions ASPM can even harm 2768 * bus communication of other PCI devices. 2769 */ 2770 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2771 tp->mac_version == RTL_GIGA_MAC_VER_43) 2772 return; 2773 2774 rtl_mod_config5(tp, 0, ASPM_en); 2775 rtl_mod_config2(tp, 0, ClkReqEn); 2776 2777 switch (tp->mac_version) { 2778 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2779 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2780 /* reset ephy tx/rx disable timer */ 2781 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2782 /* chip can trigger L1.2 */ 2783 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2784 break; 2785 default: 2786 break; 2787 } 2788 } else { 2789 switch (tp->mac_version) { 2790 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2791 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2792 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2793 break; 2794 default: 2795 break; 2796 } 2797 2798 rtl_mod_config2(tp, ClkReqEn, 0); 2799 rtl_mod_config5(tp, ASPM_en, 0); 2800 } 2801 } 2802 2803 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2804 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2805 { 2806 /* Usage of dynamic vs. static FIFO is controlled by bit 2807 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2808 */ 2809 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2810 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2811 } 2812 2813 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2814 u8 low, u8 high) 2815 { 2816 /* FIFO thresholds for pause flow control */ 2817 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2818 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2819 } 2820 2821 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2822 { 2823 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2824 } 2825 2826 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2827 { 2828 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2829 2830 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2831 2832 rtl_disable_clock_request(tp); 2833 } 2834 2835 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2836 { 2837 static const struct ephy_info e_info_8168cp[] = { 2838 { 0x01, 0, 0x0001 }, 2839 { 0x02, 0x0800, 0x1000 }, 2840 { 0x03, 0, 0x0042 }, 2841 { 0x06, 0x0080, 0x0000 }, 2842 { 0x07, 0, 0x2000 } 2843 }; 2844 2845 rtl_set_def_aspm_entry_latency(tp); 2846 2847 rtl_ephy_init(tp, e_info_8168cp); 2848 2849 __rtl_hw_start_8168cp(tp); 2850 } 2851 2852 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2853 { 2854 rtl_set_def_aspm_entry_latency(tp); 2855 2856 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2857 } 2858 2859 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2860 { 2861 rtl_set_def_aspm_entry_latency(tp); 2862 2863 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2864 2865 /* Magic. */ 2866 RTL_W8(tp, DBG_REG, 0x20); 2867 } 2868 2869 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2870 { 2871 static const struct ephy_info e_info_8168c_1[] = { 2872 { 0x02, 0x0800, 0x1000 }, 2873 { 0x03, 0, 0x0002 }, 2874 { 0x06, 0x0080, 0x0000 } 2875 }; 2876 2877 rtl_set_def_aspm_entry_latency(tp); 2878 2879 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2880 2881 rtl_ephy_init(tp, e_info_8168c_1); 2882 2883 __rtl_hw_start_8168cp(tp); 2884 } 2885 2886 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2887 { 2888 static const struct ephy_info e_info_8168c_2[] = { 2889 { 0x01, 0, 0x0001 }, 2890 { 0x03, 0x0400, 0x0020 } 2891 }; 2892 2893 rtl_set_def_aspm_entry_latency(tp); 2894 2895 rtl_ephy_init(tp, e_info_8168c_2); 2896 2897 __rtl_hw_start_8168cp(tp); 2898 } 2899 2900 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2901 { 2902 rtl_set_def_aspm_entry_latency(tp); 2903 2904 __rtl_hw_start_8168cp(tp); 2905 } 2906 2907 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2908 { 2909 rtl_set_def_aspm_entry_latency(tp); 2910 2911 rtl_disable_clock_request(tp); 2912 } 2913 2914 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2915 { 2916 static const struct ephy_info e_info_8168d_4[] = { 2917 { 0x0b, 0x0000, 0x0048 }, 2918 { 0x19, 0x0020, 0x0050 }, 2919 { 0x0c, 0x0100, 0x0020 }, 2920 { 0x10, 0x0004, 0x0000 }, 2921 }; 2922 2923 rtl_set_def_aspm_entry_latency(tp); 2924 2925 rtl_ephy_init(tp, e_info_8168d_4); 2926 2927 rtl_enable_clock_request(tp); 2928 } 2929 2930 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2931 { 2932 static const struct ephy_info e_info_8168e_1[] = { 2933 { 0x00, 0x0200, 0x0100 }, 2934 { 0x00, 0x0000, 0x0004 }, 2935 { 0x06, 0x0002, 0x0001 }, 2936 { 0x06, 0x0000, 0x0030 }, 2937 { 0x07, 0x0000, 0x2000 }, 2938 { 0x00, 0x0000, 0x0020 }, 2939 { 0x03, 0x5800, 0x2000 }, 2940 { 0x03, 0x0000, 0x0001 }, 2941 { 0x01, 0x0800, 0x1000 }, 2942 { 0x07, 0x0000, 0x4000 }, 2943 { 0x1e, 0x0000, 0x2000 }, 2944 { 0x19, 0xffff, 0xfe6c }, 2945 { 0x0a, 0x0000, 0x0040 } 2946 }; 2947 2948 rtl_set_def_aspm_entry_latency(tp); 2949 2950 rtl_ephy_init(tp, e_info_8168e_1); 2951 2952 rtl_disable_clock_request(tp); 2953 2954 /* Reset tx FIFO pointer */ 2955 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2956 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2957 2958 rtl_mod_config5(tp, Spi_en, 0); 2959 } 2960 2961 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2962 { 2963 static const struct ephy_info e_info_8168e_2[] = { 2964 { 0x09, 0x0000, 0x0080 }, 2965 { 0x19, 0x0000, 0x0224 }, 2966 { 0x00, 0x0000, 0x0004 }, 2967 { 0x0c, 0x3df0, 0x0200 }, 2968 }; 2969 2970 rtl_set_def_aspm_entry_latency(tp); 2971 2972 rtl_ephy_init(tp, e_info_8168e_2); 2973 2974 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2975 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2976 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2977 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2978 rtl_reset_packet_filter(tp); 2979 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2980 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2981 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2982 2983 rtl_disable_clock_request(tp); 2984 2985 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2986 2987 rtl8168_config_eee_mac(tp); 2988 2989 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2990 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2991 rtl_mod_config5(tp, Spi_en, 0); 2992 } 2993 2994 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2995 { 2996 rtl_set_def_aspm_entry_latency(tp); 2997 2998 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2999 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3000 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3001 rtl_reset_packet_filter(tp); 3002 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3003 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3004 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3005 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3006 3007 rtl_disable_clock_request(tp); 3008 3009 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3010 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3011 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3012 rtl_mod_config5(tp, Spi_en, 0); 3013 3014 rtl8168_config_eee_mac(tp); 3015 } 3016 3017 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3018 { 3019 static const struct ephy_info e_info_8168f_1[] = { 3020 { 0x06, 0x00c0, 0x0020 }, 3021 { 0x08, 0x0001, 0x0002 }, 3022 { 0x09, 0x0000, 0x0080 }, 3023 { 0x19, 0x0000, 0x0224 }, 3024 { 0x00, 0x0000, 0x0008 }, 3025 { 0x0c, 0x3df0, 0x0200 }, 3026 }; 3027 3028 rtl_hw_start_8168f(tp); 3029 3030 rtl_ephy_init(tp, e_info_8168f_1); 3031 } 3032 3033 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3034 { 3035 static const struct ephy_info e_info_8168f_1[] = { 3036 { 0x06, 0x00c0, 0x0020 }, 3037 { 0x0f, 0xffff, 0x5200 }, 3038 { 0x19, 0x0000, 0x0224 }, 3039 { 0x00, 0x0000, 0x0008 }, 3040 { 0x0c, 0x3df0, 0x0200 }, 3041 }; 3042 3043 rtl_hw_start_8168f(tp); 3044 rtl_pcie_state_l2l3_disable(tp); 3045 3046 rtl_ephy_init(tp, e_info_8168f_1); 3047 } 3048 3049 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3050 { 3051 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3052 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3053 3054 rtl_set_def_aspm_entry_latency(tp); 3055 3056 rtl_reset_packet_filter(tp); 3057 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3058 3059 rtl_disable_rxdvgate(tp); 3060 3061 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3062 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3063 3064 rtl8168_config_eee_mac(tp); 3065 3066 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3067 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3068 3069 rtl_pcie_state_l2l3_disable(tp); 3070 } 3071 3072 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3073 { 3074 static const struct ephy_info e_info_8168g_1[] = { 3075 { 0x00, 0x0008, 0x0000 }, 3076 { 0x0c, 0x3ff0, 0x0820 }, 3077 { 0x1e, 0x0000, 0x0001 }, 3078 { 0x19, 0x8000, 0x0000 } 3079 }; 3080 3081 rtl_hw_start_8168g(tp); 3082 rtl_ephy_init(tp, e_info_8168g_1); 3083 } 3084 3085 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3086 { 3087 static const struct ephy_info e_info_8168g_2[] = { 3088 { 0x00, 0x0008, 0x0000 }, 3089 { 0x0c, 0x3ff0, 0x0820 }, 3090 { 0x19, 0xffff, 0x7c00 }, 3091 { 0x1e, 0xffff, 0x20eb }, 3092 { 0x0d, 0xffff, 0x1666 }, 3093 { 0x00, 0xffff, 0x10a3 }, 3094 { 0x06, 0xffff, 0xf050 }, 3095 { 0x04, 0x0000, 0x0010 }, 3096 { 0x1d, 0x4000, 0x0000 }, 3097 }; 3098 3099 rtl_hw_start_8168g(tp); 3100 rtl_ephy_init(tp, e_info_8168g_2); 3101 } 3102 3103 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3104 { 3105 static const u16 fix_data[] = { 3106 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3107 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3108 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3109 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3110 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3111 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3112 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3113 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3114 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3115 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3116 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3117 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3118 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3119 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3120 }; 3121 unsigned long flags; 3122 int i; 3123 3124 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3125 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3126 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3127 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3128 } 3129 3130 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3131 { 3132 static const struct ephy_info e_info_8411_2[] = { 3133 { 0x00, 0x0008, 0x0000 }, 3134 { 0x0c, 0x37d0, 0x0820 }, 3135 { 0x1e, 0x0000, 0x0001 }, 3136 { 0x19, 0x8021, 0x0000 }, 3137 { 0x1e, 0x0000, 0x2000 }, 3138 { 0x0d, 0x0100, 0x0200 }, 3139 { 0x00, 0x0000, 0x0080 }, 3140 { 0x06, 0x0000, 0x0010 }, 3141 { 0x04, 0x0000, 0x0010 }, 3142 { 0x1d, 0x0000, 0x4000 }, 3143 }; 3144 3145 rtl_hw_start_8168g(tp); 3146 3147 rtl_ephy_init(tp, e_info_8411_2); 3148 3149 /* The following Realtek-provided magic fixes an issue with the RX unit 3150 * getting confused after the PHY having been powered-down. 3151 */ 3152 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3153 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3154 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3155 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3156 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3157 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3158 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3159 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3160 mdelay(3); 3161 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3162 3163 rtl8411b_fix_phy_down(tp); 3164 3165 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3166 3167 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3168 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3169 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3170 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3171 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3172 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3173 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3174 } 3175 3176 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3177 { 3178 static const struct ephy_info e_info_8168h_1[] = { 3179 { 0x1e, 0x0800, 0x0001 }, 3180 { 0x1d, 0x0000, 0x0800 }, 3181 { 0x05, 0xffff, 0x2089 }, 3182 { 0x06, 0xffff, 0x5881 }, 3183 { 0x04, 0xffff, 0x854a }, 3184 { 0x01, 0xffff, 0x068b } 3185 }; 3186 int rg_saw_cnt; 3187 3188 rtl_ephy_init(tp, e_info_8168h_1); 3189 3190 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3191 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3192 3193 rtl_set_def_aspm_entry_latency(tp); 3194 3195 rtl_reset_packet_filter(tp); 3196 3197 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3198 3199 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3200 3201 rtl_disable_rxdvgate(tp); 3202 3203 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3204 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3205 3206 rtl8168_config_eee_mac(tp); 3207 3208 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3209 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3210 3211 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3212 3213 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3214 3215 rtl_pcie_state_l2l3_disable(tp); 3216 3217 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3218 if (rg_saw_cnt > 0) { 3219 u16 sw_cnt_1ms_ini; 3220 3221 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3222 sw_cnt_1ms_ini &= 0x0fff; 3223 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3224 } 3225 3226 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3227 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3228 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3229 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3230 3231 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3232 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3233 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3234 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3235 } 3236 3237 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3238 { 3239 rtl8168ep_stop_cmac(tp); 3240 3241 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3242 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3243 3244 rtl_set_def_aspm_entry_latency(tp); 3245 3246 rtl_reset_packet_filter(tp); 3247 3248 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3249 3250 rtl_disable_rxdvgate(tp); 3251 3252 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3253 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3254 3255 rtl8168_config_eee_mac(tp); 3256 3257 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3258 3259 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3260 3261 rtl_pcie_state_l2l3_disable(tp); 3262 } 3263 3264 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3265 { 3266 static const struct ephy_info e_info_8168ep_3[] = { 3267 { 0x00, 0x0000, 0x0080 }, 3268 { 0x0d, 0x0100, 0x0200 }, 3269 { 0x19, 0x8021, 0x0000 }, 3270 { 0x1e, 0x0000, 0x2000 }, 3271 }; 3272 3273 rtl_ephy_init(tp, e_info_8168ep_3); 3274 3275 rtl_hw_start_8168ep(tp); 3276 3277 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3278 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3279 3280 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3281 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3282 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3283 } 3284 3285 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3286 { 3287 static const struct ephy_info e_info_8117[] = { 3288 { 0x19, 0x0040, 0x1100 }, 3289 { 0x59, 0x0040, 0x1100 }, 3290 }; 3291 int rg_saw_cnt; 3292 3293 rtl8168ep_stop_cmac(tp); 3294 rtl_ephy_init(tp, e_info_8117); 3295 3296 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3297 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3298 3299 rtl_set_def_aspm_entry_latency(tp); 3300 3301 rtl_reset_packet_filter(tp); 3302 3303 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3304 3305 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3306 3307 rtl_disable_rxdvgate(tp); 3308 3309 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3310 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3311 3312 rtl8168_config_eee_mac(tp); 3313 3314 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3315 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3316 3317 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3318 3319 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3320 3321 rtl_pcie_state_l2l3_disable(tp); 3322 3323 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3324 if (rg_saw_cnt > 0) { 3325 u16 sw_cnt_1ms_ini; 3326 3327 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3328 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3329 } 3330 3331 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3332 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3333 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3334 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3335 3336 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3337 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3338 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3339 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3340 3341 /* firmware is for MAC only */ 3342 r8169_apply_firmware(tp); 3343 } 3344 3345 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3346 { 3347 static const struct ephy_info e_info_8102e_1[] = { 3348 { 0x01, 0, 0x6e65 }, 3349 { 0x02, 0, 0x091f }, 3350 { 0x03, 0, 0xc2f9 }, 3351 { 0x06, 0, 0xafb5 }, 3352 { 0x07, 0, 0x0e00 }, 3353 { 0x19, 0, 0xec80 }, 3354 { 0x01, 0, 0x2e65 }, 3355 { 0x01, 0, 0x6e65 } 3356 }; 3357 u8 cfg1; 3358 3359 rtl_set_def_aspm_entry_latency(tp); 3360 3361 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3362 3363 RTL_W8(tp, Config1, 3364 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3365 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3366 3367 cfg1 = RTL_R8(tp, Config1); 3368 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3369 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3370 3371 rtl_ephy_init(tp, e_info_8102e_1); 3372 } 3373 3374 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3375 { 3376 rtl_set_def_aspm_entry_latency(tp); 3377 3378 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3379 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3380 } 3381 3382 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3383 { 3384 rtl_hw_start_8102e_2(tp); 3385 3386 rtl_ephy_write(tp, 0x03, 0xc2f9); 3387 } 3388 3389 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3390 { 3391 static const struct ephy_info e_info_8401[] = { 3392 { 0x01, 0xffff, 0x6fe5 }, 3393 { 0x03, 0xffff, 0x0599 }, 3394 { 0x06, 0xffff, 0xaf25 }, 3395 { 0x07, 0xffff, 0x8e68 }, 3396 }; 3397 3398 rtl_ephy_init(tp, e_info_8401); 3399 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3400 } 3401 3402 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3403 { 3404 static const struct ephy_info e_info_8105e_1[] = { 3405 { 0x07, 0, 0x4000 }, 3406 { 0x19, 0, 0x0200 }, 3407 { 0x19, 0, 0x0020 }, 3408 { 0x1e, 0, 0x2000 }, 3409 { 0x03, 0, 0x0001 }, 3410 { 0x19, 0, 0x0100 }, 3411 { 0x19, 0, 0x0004 }, 3412 { 0x0a, 0, 0x0020 } 3413 }; 3414 3415 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3416 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3417 3418 /* Disable Early Tally Counter */ 3419 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3420 3421 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3422 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3423 3424 rtl_ephy_init(tp, e_info_8105e_1); 3425 3426 rtl_pcie_state_l2l3_disable(tp); 3427 } 3428 3429 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3430 { 3431 rtl_hw_start_8105e_1(tp); 3432 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3433 } 3434 3435 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3436 { 3437 static const struct ephy_info e_info_8402[] = { 3438 { 0x19, 0xffff, 0xff64 }, 3439 { 0x1e, 0, 0x4000 } 3440 }; 3441 3442 rtl_set_def_aspm_entry_latency(tp); 3443 3444 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3445 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3446 3447 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3448 3449 rtl_ephy_init(tp, e_info_8402); 3450 3451 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3452 rtl_reset_packet_filter(tp); 3453 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3454 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3455 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3456 3457 /* disable EEE */ 3458 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3459 3460 rtl_pcie_state_l2l3_disable(tp); 3461 } 3462 3463 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3464 { 3465 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3466 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3467 3468 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3469 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3470 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3471 3472 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3473 rtl_set_aspm_entry_latency(tp, 0x2f); 3474 3475 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3476 3477 /* disable EEE */ 3478 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3479 3480 rtl_pcie_state_l2l3_disable(tp); 3481 } 3482 3483 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3484 { 3485 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3486 } 3487 3488 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3489 { 3490 rtl_pcie_state_l2l3_disable(tp); 3491 3492 RTL_W16(tp, 0x382, 0x221b); 3493 RTL_W8(tp, 0x4500, 0); 3494 RTL_W16(tp, 0x4800, 0); 3495 3496 /* disable UPS */ 3497 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3498 3499 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3500 3501 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3502 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3503 3504 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3505 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3506 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3507 3508 /* disable new tx descriptor format */ 3509 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3510 3511 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3512 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3513 else 3514 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3515 3516 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3517 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3518 else 3519 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3520 3521 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3522 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3523 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3524 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3525 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3526 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3527 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3528 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3529 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3530 3531 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3532 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3533 udelay(1); 3534 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3535 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3536 3537 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3538 3539 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3540 3541 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3542 rtl8125b_config_eee_mac(tp); 3543 else 3544 rtl8125a_config_eee_mac(tp); 3545 3546 rtl_disable_rxdvgate(tp); 3547 } 3548 3549 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3550 { 3551 static const struct ephy_info e_info_8125a_2[] = { 3552 { 0x04, 0xffff, 0xd000 }, 3553 { 0x0a, 0xffff, 0x8653 }, 3554 { 0x23, 0xffff, 0xab66 }, 3555 { 0x20, 0xffff, 0x9455 }, 3556 { 0x21, 0xffff, 0x99ff }, 3557 { 0x29, 0xffff, 0xfe04 }, 3558 3559 { 0x44, 0xffff, 0xd000 }, 3560 { 0x4a, 0xffff, 0x8653 }, 3561 { 0x63, 0xffff, 0xab66 }, 3562 { 0x60, 0xffff, 0x9455 }, 3563 { 0x61, 0xffff, 0x99ff }, 3564 { 0x69, 0xffff, 0xfe04 }, 3565 }; 3566 3567 rtl_set_def_aspm_entry_latency(tp); 3568 rtl_ephy_init(tp, e_info_8125a_2); 3569 rtl_hw_start_8125_common(tp); 3570 } 3571 3572 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3573 { 3574 static const struct ephy_info e_info_8125b[] = { 3575 { 0x0b, 0xffff, 0xa908 }, 3576 { 0x1e, 0xffff, 0x20eb }, 3577 { 0x4b, 0xffff, 0xa908 }, 3578 { 0x5e, 0xffff, 0x20eb }, 3579 { 0x22, 0x0030, 0x0020 }, 3580 { 0x62, 0x0030, 0x0020 }, 3581 }; 3582 3583 rtl_set_def_aspm_entry_latency(tp); 3584 rtl_ephy_init(tp, e_info_8125b); 3585 rtl_hw_start_8125_common(tp); 3586 } 3587 3588 static void rtl_hw_config(struct rtl8169_private *tp) 3589 { 3590 static const rtl_generic_fct hw_configs[] = { 3591 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3592 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3593 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3594 [RTL_GIGA_MAC_VER_10] = NULL, 3595 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3596 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3597 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3598 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3599 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3600 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3601 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3602 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3603 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3604 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3605 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3606 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3607 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3608 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3609 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3610 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3611 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3612 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3613 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3614 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3615 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3616 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3617 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3618 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3619 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3620 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3621 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3622 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3623 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3624 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3625 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3626 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3627 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3628 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3629 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3630 }; 3631 3632 if (hw_configs[tp->mac_version]) 3633 hw_configs[tp->mac_version](tp); 3634 } 3635 3636 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3637 { 3638 int i; 3639 3640 /* disable interrupt coalescing */ 3641 for (i = 0xa00; i < 0xb00; i += 4) 3642 RTL_W32(tp, i, 0); 3643 3644 rtl_hw_config(tp); 3645 } 3646 3647 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3648 { 3649 if (rtl_is_8168evl_up(tp)) 3650 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3651 else 3652 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3653 3654 rtl_hw_config(tp); 3655 3656 /* disable interrupt coalescing */ 3657 RTL_W16(tp, IntrMitigate, 0x0000); 3658 } 3659 3660 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3661 { 3662 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3663 3664 tp->cp_cmd |= PCIMulRW; 3665 3666 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3667 tp->mac_version == RTL_GIGA_MAC_VER_03) 3668 tp->cp_cmd |= EnAnaPLL; 3669 3670 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3671 3672 rtl8169_set_magic_reg(tp); 3673 3674 /* disable interrupt coalescing */ 3675 RTL_W16(tp, IntrMitigate, 0x0000); 3676 } 3677 3678 static void rtl_hw_start(struct rtl8169_private *tp) 3679 { 3680 rtl_unlock_config_regs(tp); 3681 /* disable aspm and clock request before ephy access */ 3682 rtl_hw_aspm_clkreq_enable(tp, false); 3683 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3684 3685 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3686 rtl_hw_start_8169(tp); 3687 else if (rtl_is_8125(tp)) 3688 rtl_hw_start_8125(tp); 3689 else 3690 rtl_hw_start_8168(tp); 3691 3692 rtl_enable_exit_l1(tp); 3693 rtl_hw_aspm_clkreq_enable(tp, true); 3694 rtl_set_rx_max_size(tp); 3695 rtl_set_rx_tx_desc_registers(tp); 3696 rtl_lock_config_regs(tp); 3697 3698 rtl_jumbo_config(tp); 3699 3700 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3701 rtl_pci_commit(tp); 3702 3703 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3704 rtl_init_rxcfg(tp); 3705 rtl_set_tx_config_registers(tp); 3706 rtl_set_rx_config_features(tp, tp->dev->features); 3707 rtl_set_rx_mode(tp->dev); 3708 rtl_irq_enable(tp); 3709 } 3710 3711 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3712 { 3713 struct rtl8169_private *tp = netdev_priv(dev); 3714 3715 dev->mtu = new_mtu; 3716 netdev_update_features(dev); 3717 rtl_jumbo_config(tp); 3718 3719 switch (tp->mac_version) { 3720 case RTL_GIGA_MAC_VER_61: 3721 case RTL_GIGA_MAC_VER_63: 3722 rtl8125_set_eee_txidle_timer(tp); 3723 break; 3724 default: 3725 break; 3726 } 3727 3728 return 0; 3729 } 3730 3731 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3732 { 3733 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3734 3735 desc->opts2 = 0; 3736 /* Force memory writes to complete before releasing descriptor */ 3737 dma_wmb(); 3738 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3739 } 3740 3741 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3742 struct RxDesc *desc) 3743 { 3744 struct device *d = tp_to_dev(tp); 3745 int node = dev_to_node(d); 3746 dma_addr_t mapping; 3747 struct page *data; 3748 3749 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3750 if (!data) 3751 return NULL; 3752 3753 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3754 if (unlikely(dma_mapping_error(d, mapping))) { 3755 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3756 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3757 return NULL; 3758 } 3759 3760 desc->addr = cpu_to_le64(mapping); 3761 rtl8169_mark_to_asic(desc); 3762 3763 return data; 3764 } 3765 3766 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3767 { 3768 int i; 3769 3770 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3771 dma_unmap_page(tp_to_dev(tp), 3772 le64_to_cpu(tp->RxDescArray[i].addr), 3773 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3774 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3775 tp->Rx_databuff[i] = NULL; 3776 tp->RxDescArray[i].addr = 0; 3777 tp->RxDescArray[i].opts1 = 0; 3778 } 3779 } 3780 3781 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3782 { 3783 int i; 3784 3785 for (i = 0; i < NUM_RX_DESC; i++) { 3786 struct page *data; 3787 3788 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3789 if (!data) { 3790 rtl8169_rx_clear(tp); 3791 return -ENOMEM; 3792 } 3793 tp->Rx_databuff[i] = data; 3794 } 3795 3796 /* mark as last descriptor in the ring */ 3797 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3798 3799 return 0; 3800 } 3801 3802 static int rtl8169_init_ring(struct rtl8169_private *tp) 3803 { 3804 rtl8169_init_ring_indexes(tp); 3805 3806 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3807 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3808 3809 return rtl8169_rx_fill(tp); 3810 } 3811 3812 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3813 { 3814 struct ring_info *tx_skb = tp->tx_skb + entry; 3815 struct TxDesc *desc = tp->TxDescArray + entry; 3816 3817 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3818 DMA_TO_DEVICE); 3819 memset(desc, 0, sizeof(*desc)); 3820 memset(tx_skb, 0, sizeof(*tx_skb)); 3821 } 3822 3823 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3824 unsigned int n) 3825 { 3826 unsigned int i; 3827 3828 for (i = 0; i < n; i++) { 3829 unsigned int entry = (start + i) % NUM_TX_DESC; 3830 struct ring_info *tx_skb = tp->tx_skb + entry; 3831 unsigned int len = tx_skb->len; 3832 3833 if (len) { 3834 struct sk_buff *skb = tx_skb->skb; 3835 3836 rtl8169_unmap_tx_skb(tp, entry); 3837 if (skb) 3838 dev_consume_skb_any(skb); 3839 } 3840 } 3841 } 3842 3843 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3844 { 3845 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3846 netdev_reset_queue(tp->dev); 3847 } 3848 3849 static void rtl8169_cleanup(struct rtl8169_private *tp) 3850 { 3851 napi_disable(&tp->napi); 3852 3853 /* Give a racing hard_start_xmit a few cycles to complete. */ 3854 synchronize_net(); 3855 3856 /* Disable interrupts */ 3857 rtl8169_irq_mask_and_ack(tp); 3858 3859 rtl_rx_close(tp); 3860 3861 switch (tp->mac_version) { 3862 case RTL_GIGA_MAC_VER_28: 3863 case RTL_GIGA_MAC_VER_31: 3864 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3865 break; 3866 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3867 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3868 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3869 break; 3870 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3871 rtl_enable_rxdvgate(tp); 3872 fsleep(2000); 3873 break; 3874 default: 3875 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3876 fsleep(100); 3877 break; 3878 } 3879 3880 rtl_hw_reset(tp); 3881 3882 rtl8169_tx_clear(tp); 3883 rtl8169_init_ring_indexes(tp); 3884 } 3885 3886 static void rtl_reset_work(struct rtl8169_private *tp) 3887 { 3888 int i; 3889 3890 netif_stop_queue(tp->dev); 3891 3892 rtl8169_cleanup(tp); 3893 3894 for (i = 0; i < NUM_RX_DESC; i++) 3895 rtl8169_mark_to_asic(tp->RxDescArray + i); 3896 3897 napi_enable(&tp->napi); 3898 rtl_hw_start(tp); 3899 } 3900 3901 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3902 { 3903 struct rtl8169_private *tp = netdev_priv(dev); 3904 3905 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 3906 } 3907 3908 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3909 void *addr, unsigned int entry, bool desc_own) 3910 { 3911 struct TxDesc *txd = tp->TxDescArray + entry; 3912 struct device *d = tp_to_dev(tp); 3913 dma_addr_t mapping; 3914 u32 opts1; 3915 int ret; 3916 3917 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3918 ret = dma_mapping_error(d, mapping); 3919 if (unlikely(ret)) { 3920 if (net_ratelimit()) 3921 netdev_err(tp->dev, "Failed to map TX data!\n"); 3922 return ret; 3923 } 3924 3925 txd->addr = cpu_to_le64(mapping); 3926 txd->opts2 = cpu_to_le32(opts[1]); 3927 3928 opts1 = opts[0] | len; 3929 if (entry == NUM_TX_DESC - 1) 3930 opts1 |= RingEnd; 3931 if (desc_own) 3932 opts1 |= DescOwn; 3933 txd->opts1 = cpu_to_le32(opts1); 3934 3935 tp->tx_skb[entry].len = len; 3936 3937 return 0; 3938 } 3939 3940 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3941 const u32 *opts, unsigned int entry) 3942 { 3943 struct skb_shared_info *info = skb_shinfo(skb); 3944 unsigned int cur_frag; 3945 3946 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 3947 const skb_frag_t *frag = info->frags + cur_frag; 3948 void *addr = skb_frag_address(frag); 3949 u32 len = skb_frag_size(frag); 3950 3951 entry = (entry + 1) % NUM_TX_DESC; 3952 3953 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 3954 goto err_out; 3955 } 3956 3957 return 0; 3958 3959 err_out: 3960 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 3961 return -EIO; 3962 } 3963 3964 static bool rtl_skb_is_udp(struct sk_buff *skb) 3965 { 3966 int no = skb_network_offset(skb); 3967 struct ipv6hdr *i6h, _i6h; 3968 struct iphdr *ih, _ih; 3969 3970 switch (vlan_get_protocol(skb)) { 3971 case htons(ETH_P_IP): 3972 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 3973 return ih && ih->protocol == IPPROTO_UDP; 3974 case htons(ETH_P_IPV6): 3975 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 3976 return i6h && i6h->nexthdr == IPPROTO_UDP; 3977 default: 3978 return false; 3979 } 3980 } 3981 3982 #define RTL_MIN_PATCH_LEN 47 3983 3984 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 3985 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 3986 struct sk_buff *skb) 3987 { 3988 unsigned int padto = 0, len = skb->len; 3989 3990 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 3991 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 3992 unsigned int trans_data_len = skb_tail_pointer(skb) - 3993 skb_transport_header(skb); 3994 3995 if (trans_data_len >= offsetof(struct udphdr, len) && 3996 trans_data_len < RTL_MIN_PATCH_LEN) { 3997 u16 dest = ntohs(udp_hdr(skb)->dest); 3998 3999 /* dest is a standard PTP port */ 4000 if (dest == 319 || dest == 320) 4001 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4002 } 4003 4004 if (trans_data_len < sizeof(struct udphdr)) 4005 padto = max_t(unsigned int, padto, 4006 len + sizeof(struct udphdr) - trans_data_len); 4007 } 4008 4009 return padto; 4010 } 4011 4012 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4013 struct sk_buff *skb) 4014 { 4015 unsigned int padto; 4016 4017 padto = rtl8125_quirk_udp_padto(tp, skb); 4018 4019 switch (tp->mac_version) { 4020 case RTL_GIGA_MAC_VER_34: 4021 case RTL_GIGA_MAC_VER_61: 4022 case RTL_GIGA_MAC_VER_63: 4023 padto = max_t(unsigned int, padto, ETH_ZLEN); 4024 break; 4025 default: 4026 break; 4027 } 4028 4029 return padto; 4030 } 4031 4032 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4033 { 4034 u32 mss = skb_shinfo(skb)->gso_size; 4035 4036 if (mss) { 4037 opts[0] |= TD_LSO; 4038 opts[0] |= mss << TD0_MSS_SHIFT; 4039 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4040 const struct iphdr *ip = ip_hdr(skb); 4041 4042 if (ip->protocol == IPPROTO_TCP) 4043 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4044 else if (ip->protocol == IPPROTO_UDP) 4045 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4046 else 4047 WARN_ON_ONCE(1); 4048 } 4049 } 4050 4051 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4052 struct sk_buff *skb, u32 *opts) 4053 { 4054 struct skb_shared_info *shinfo = skb_shinfo(skb); 4055 u32 mss = shinfo->gso_size; 4056 4057 if (mss) { 4058 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4059 opts[0] |= TD1_GTSENV4; 4060 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4061 if (skb_cow_head(skb, 0)) 4062 return false; 4063 4064 tcp_v6_gso_csum_prep(skb); 4065 opts[0] |= TD1_GTSENV6; 4066 } else { 4067 WARN_ON_ONCE(1); 4068 } 4069 4070 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4071 opts[1] |= mss << TD1_MSS_SHIFT; 4072 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4073 u8 ip_protocol; 4074 4075 switch (vlan_get_protocol(skb)) { 4076 case htons(ETH_P_IP): 4077 opts[1] |= TD1_IPv4_CS; 4078 ip_protocol = ip_hdr(skb)->protocol; 4079 break; 4080 4081 case htons(ETH_P_IPV6): 4082 opts[1] |= TD1_IPv6_CS; 4083 ip_protocol = ipv6_hdr(skb)->nexthdr; 4084 break; 4085 4086 default: 4087 ip_protocol = IPPROTO_RAW; 4088 break; 4089 } 4090 4091 if (ip_protocol == IPPROTO_TCP) 4092 opts[1] |= TD1_TCP_CS; 4093 else if (ip_protocol == IPPROTO_UDP) 4094 opts[1] |= TD1_UDP_CS; 4095 else 4096 WARN_ON_ONCE(1); 4097 4098 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4099 } else { 4100 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4101 4102 /* skb_padto would free the skb on error */ 4103 return !__skb_put_padto(skb, padto, false); 4104 } 4105 4106 return true; 4107 } 4108 4109 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4110 { 4111 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4112 } 4113 4114 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4115 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4116 { 4117 switch (tp->mac_version) { 4118 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4119 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4120 return false; 4121 default: 4122 return true; 4123 } 4124 } 4125 4126 static void rtl8169_doorbell(struct rtl8169_private *tp) 4127 { 4128 if (rtl_is_8125(tp)) 4129 RTL_W16(tp, TxPoll_8125, BIT(0)); 4130 else 4131 RTL_W8(tp, TxPoll, NPQ); 4132 } 4133 4134 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4135 struct net_device *dev) 4136 { 4137 unsigned int frags = skb_shinfo(skb)->nr_frags; 4138 struct rtl8169_private *tp = netdev_priv(dev); 4139 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4140 struct TxDesc *txd_first, *txd_last; 4141 bool stop_queue, door_bell; 4142 u32 opts[2]; 4143 4144 if (unlikely(!rtl_tx_slots_avail(tp))) { 4145 if (net_ratelimit()) 4146 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4147 goto err_stop_0; 4148 } 4149 4150 opts[1] = rtl8169_tx_vlan_tag(skb); 4151 opts[0] = 0; 4152 4153 if (!rtl_chip_supports_csum_v2(tp)) 4154 rtl8169_tso_csum_v1(skb, opts); 4155 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4156 goto err_dma_0; 4157 4158 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4159 entry, false))) 4160 goto err_dma_0; 4161 4162 txd_first = tp->TxDescArray + entry; 4163 4164 if (frags) { 4165 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4166 goto err_dma_1; 4167 entry = (entry + frags) % NUM_TX_DESC; 4168 } 4169 4170 txd_last = tp->TxDescArray + entry; 4171 txd_last->opts1 |= cpu_to_le32(LastFrag); 4172 tp->tx_skb[entry].skb = skb; 4173 4174 skb_tx_timestamp(skb); 4175 4176 /* Force memory writes to complete before releasing descriptor */ 4177 dma_wmb(); 4178 4179 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4180 4181 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4182 4183 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4184 smp_wmb(); 4185 4186 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4187 4188 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4189 R8169_TX_STOP_THRS, 4190 R8169_TX_START_THRS); 4191 if (door_bell || stop_queue) 4192 rtl8169_doorbell(tp); 4193 4194 return NETDEV_TX_OK; 4195 4196 err_dma_1: 4197 rtl8169_unmap_tx_skb(tp, entry); 4198 err_dma_0: 4199 dev_kfree_skb_any(skb); 4200 dev->stats.tx_dropped++; 4201 return NETDEV_TX_OK; 4202 4203 err_stop_0: 4204 netif_stop_queue(dev); 4205 dev->stats.tx_dropped++; 4206 return NETDEV_TX_BUSY; 4207 } 4208 4209 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4210 { 4211 struct skb_shared_info *info = skb_shinfo(skb); 4212 unsigned int nr_frags = info->nr_frags; 4213 4214 if (!nr_frags) 4215 return UINT_MAX; 4216 4217 return skb_frag_size(info->frags + nr_frags - 1); 4218 } 4219 4220 /* Workaround for hw issues with TSO on RTL8168evl */ 4221 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4222 netdev_features_t features) 4223 { 4224 /* IPv4 header has options field */ 4225 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4226 ip_hdrlen(skb) > sizeof(struct iphdr)) 4227 features &= ~NETIF_F_ALL_TSO; 4228 4229 /* IPv4 TCP header has options field */ 4230 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4231 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4232 features &= ~NETIF_F_ALL_TSO; 4233 4234 else if (rtl_last_frag_len(skb) <= 6) 4235 features &= ~NETIF_F_ALL_TSO; 4236 4237 return features; 4238 } 4239 4240 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4241 struct net_device *dev, 4242 netdev_features_t features) 4243 { 4244 struct rtl8169_private *tp = netdev_priv(dev); 4245 4246 if (skb_is_gso(skb)) { 4247 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4248 features = rtl8168evl_fix_tso(skb, features); 4249 4250 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4251 rtl_chip_supports_csum_v2(tp)) 4252 features &= ~NETIF_F_ALL_TSO; 4253 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4254 /* work around hw bug on some chip versions */ 4255 if (skb->len < ETH_ZLEN) 4256 features &= ~NETIF_F_CSUM_MASK; 4257 4258 if (rtl_quirk_packet_padto(tp, skb)) 4259 features &= ~NETIF_F_CSUM_MASK; 4260 4261 if (skb_transport_offset(skb) > TCPHO_MAX && 4262 rtl_chip_supports_csum_v2(tp)) 4263 features &= ~NETIF_F_CSUM_MASK; 4264 } 4265 4266 return vlan_features_check(skb, features); 4267 } 4268 4269 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4270 { 4271 struct rtl8169_private *tp = netdev_priv(dev); 4272 struct pci_dev *pdev = tp->pci_dev; 4273 int pci_status_errs; 4274 u16 pci_cmd; 4275 4276 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4277 4278 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4279 4280 if (net_ratelimit()) 4281 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4282 pci_cmd, pci_status_errs); 4283 4284 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4285 } 4286 4287 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4288 int budget) 4289 { 4290 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4291 struct sk_buff *skb; 4292 4293 dirty_tx = tp->dirty_tx; 4294 4295 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4296 unsigned int entry = dirty_tx % NUM_TX_DESC; 4297 u32 status; 4298 4299 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4300 if (status & DescOwn) 4301 break; 4302 4303 skb = tp->tx_skb[entry].skb; 4304 rtl8169_unmap_tx_skb(tp, entry); 4305 4306 if (skb) { 4307 pkts_compl++; 4308 bytes_compl += skb->len; 4309 napi_consume_skb(skb, budget); 4310 } 4311 dirty_tx++; 4312 } 4313 4314 if (tp->dirty_tx != dirty_tx) { 4315 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4316 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4317 4318 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4319 rtl_tx_slots_avail(tp), 4320 R8169_TX_START_THRS); 4321 /* 4322 * 8168 hack: TxPoll requests are lost when the Tx packets are 4323 * too close. Let's kick an extra TxPoll request when a burst 4324 * of start_xmit activity is detected (if it is not detected, 4325 * it is slow enough). -- FR 4326 * If skb is NULL then we come here again once a tx irq is 4327 * triggered after the last fragment is marked transmitted. 4328 */ 4329 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4330 rtl8169_doorbell(tp); 4331 } 4332 } 4333 4334 static inline int rtl8169_fragmented_frame(u32 status) 4335 { 4336 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4337 } 4338 4339 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4340 { 4341 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4342 4343 if (status == RxProtoTCP || status == RxProtoUDP) 4344 skb->ip_summed = CHECKSUM_UNNECESSARY; 4345 else 4346 skb_checksum_none_assert(skb); 4347 } 4348 4349 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4350 { 4351 struct device *d = tp_to_dev(tp); 4352 int count; 4353 4354 for (count = 0; count < budget; count++, tp->cur_rx++) { 4355 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4356 struct RxDesc *desc = tp->RxDescArray + entry; 4357 struct sk_buff *skb; 4358 const void *rx_buf; 4359 dma_addr_t addr; 4360 u32 status; 4361 4362 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4363 if (status & DescOwn) 4364 break; 4365 4366 /* This barrier is needed to keep us from reading 4367 * any other fields out of the Rx descriptor until 4368 * we know the status of DescOwn 4369 */ 4370 dma_rmb(); 4371 4372 if (unlikely(status & RxRES)) { 4373 if (net_ratelimit()) 4374 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4375 status); 4376 dev->stats.rx_errors++; 4377 if (status & (RxRWT | RxRUNT)) 4378 dev->stats.rx_length_errors++; 4379 if (status & RxCRC) 4380 dev->stats.rx_crc_errors++; 4381 4382 if (!(dev->features & NETIF_F_RXALL)) 4383 goto release_descriptor; 4384 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4385 goto release_descriptor; 4386 } 4387 4388 pkt_size = status & GENMASK(13, 0); 4389 if (likely(!(dev->features & NETIF_F_RXFCS))) 4390 pkt_size -= ETH_FCS_LEN; 4391 4392 /* The driver does not support incoming fragmented frames. 4393 * They are seen as a symptom of over-mtu sized frames. 4394 */ 4395 if (unlikely(rtl8169_fragmented_frame(status))) { 4396 dev->stats.rx_dropped++; 4397 dev->stats.rx_length_errors++; 4398 goto release_descriptor; 4399 } 4400 4401 skb = napi_alloc_skb(&tp->napi, pkt_size); 4402 if (unlikely(!skb)) { 4403 dev->stats.rx_dropped++; 4404 goto release_descriptor; 4405 } 4406 4407 addr = le64_to_cpu(desc->addr); 4408 rx_buf = page_address(tp->Rx_databuff[entry]); 4409 4410 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4411 prefetch(rx_buf); 4412 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4413 skb->tail += pkt_size; 4414 skb->len = pkt_size; 4415 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4416 4417 rtl8169_rx_csum(skb, status); 4418 skb->protocol = eth_type_trans(skb, dev); 4419 4420 rtl8169_rx_vlan_tag(desc, skb); 4421 4422 if (skb->pkt_type == PACKET_MULTICAST) 4423 dev->stats.multicast++; 4424 4425 napi_gro_receive(&tp->napi, skb); 4426 4427 dev_sw_netstats_rx_add(dev, pkt_size); 4428 release_descriptor: 4429 rtl8169_mark_to_asic(desc); 4430 } 4431 4432 return count; 4433 } 4434 4435 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4436 { 4437 struct rtl8169_private *tp = dev_instance; 4438 u32 status = rtl_get_events(tp); 4439 4440 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4441 return IRQ_NONE; 4442 4443 if (unlikely(status & SYSErr)) { 4444 rtl8169_pcierr_interrupt(tp->dev); 4445 goto out; 4446 } 4447 4448 if (status & LinkChg) 4449 phy_mac_interrupt(tp->phydev); 4450 4451 if (unlikely(status & RxFIFOOver && 4452 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4453 netif_stop_queue(tp->dev); 4454 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4455 } 4456 4457 if (napi_schedule_prep(&tp->napi)) { 4458 rtl_irq_disable(tp); 4459 __napi_schedule(&tp->napi); 4460 } 4461 out: 4462 rtl_ack_events(tp, status); 4463 4464 return IRQ_HANDLED; 4465 } 4466 4467 static void rtl_task(struct work_struct *work) 4468 { 4469 struct rtl8169_private *tp = 4470 container_of(work, struct rtl8169_private, wk.work); 4471 int ret; 4472 4473 rtnl_lock(); 4474 4475 if (!netif_running(tp->dev) || 4476 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4477 goto out_unlock; 4478 4479 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4480 /* if chip isn't accessible, reset bus to revive it */ 4481 if (RTL_R32(tp, TxConfig) == ~0) { 4482 ret = pci_reset_bus(tp->pci_dev); 4483 if (ret < 0) { 4484 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4485 netif_device_detach(tp->dev); 4486 goto out_unlock; 4487 } 4488 } 4489 4490 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4491 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4492 PCIE_LINK_STATE_L0S); 4493 if (!ret) 4494 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4495 goto reset; 4496 } 4497 4498 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4499 reset: 4500 rtl_reset_work(tp); 4501 netif_wake_queue(tp->dev); 4502 } 4503 out_unlock: 4504 rtnl_unlock(); 4505 } 4506 4507 static int rtl8169_poll(struct napi_struct *napi, int budget) 4508 { 4509 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4510 struct net_device *dev = tp->dev; 4511 int work_done; 4512 4513 rtl_tx(dev, tp, budget); 4514 4515 work_done = rtl_rx(dev, tp, budget); 4516 4517 if (work_done < budget && napi_complete_done(napi, work_done)) 4518 rtl_irq_enable(tp); 4519 4520 return work_done; 4521 } 4522 4523 static void r8169_phylink_handler(struct net_device *ndev) 4524 { 4525 struct rtl8169_private *tp = netdev_priv(ndev); 4526 struct device *d = tp_to_dev(tp); 4527 4528 if (netif_carrier_ok(ndev)) { 4529 rtl_link_chg_patch(tp); 4530 pm_request_resume(d); 4531 netif_wake_queue(tp->dev); 4532 } else { 4533 /* In few cases rx is broken after link-down otherwise */ 4534 if (rtl_is_8125(tp)) 4535 rtl_reset_work(tp); 4536 pm_runtime_idle(d); 4537 } 4538 4539 phy_print_status(tp->phydev); 4540 } 4541 4542 static int r8169_phy_connect(struct rtl8169_private *tp) 4543 { 4544 struct phy_device *phydev = tp->phydev; 4545 phy_interface_t phy_mode; 4546 int ret; 4547 4548 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4549 PHY_INTERFACE_MODE_MII; 4550 4551 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4552 phy_mode); 4553 if (ret) 4554 return ret; 4555 4556 if (!tp->supports_gmii) 4557 phy_set_max_speed(phydev, SPEED_100); 4558 4559 phy_attached_info(phydev); 4560 4561 return 0; 4562 } 4563 4564 static void rtl8169_down(struct rtl8169_private *tp) 4565 { 4566 /* Clear all task flags */ 4567 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4568 4569 phy_stop(tp->phydev); 4570 4571 rtl8169_update_counters(tp); 4572 4573 pci_clear_master(tp->pci_dev); 4574 rtl_pci_commit(tp); 4575 4576 rtl8169_cleanup(tp); 4577 rtl_disable_exit_l1(tp); 4578 rtl_prepare_power_down(tp); 4579 4580 if (tp->dash_type != RTL_DASH_NONE) 4581 rtl8168_driver_stop(tp); 4582 } 4583 4584 static void rtl8169_up(struct rtl8169_private *tp) 4585 { 4586 if (tp->dash_type != RTL_DASH_NONE) 4587 rtl8168_driver_start(tp); 4588 4589 pci_set_master(tp->pci_dev); 4590 phy_init_hw(tp->phydev); 4591 phy_resume(tp->phydev); 4592 rtl8169_init_phy(tp); 4593 napi_enable(&tp->napi); 4594 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4595 rtl_reset_work(tp); 4596 4597 phy_start(tp->phydev); 4598 } 4599 4600 static int rtl8169_close(struct net_device *dev) 4601 { 4602 struct rtl8169_private *tp = netdev_priv(dev); 4603 struct pci_dev *pdev = tp->pci_dev; 4604 4605 pm_runtime_get_sync(&pdev->dev); 4606 4607 netif_stop_queue(dev); 4608 rtl8169_down(tp); 4609 rtl8169_rx_clear(tp); 4610 4611 cancel_work_sync(&tp->wk.work); 4612 4613 free_irq(tp->irq, tp); 4614 4615 phy_disconnect(tp->phydev); 4616 4617 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4618 tp->RxPhyAddr); 4619 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4620 tp->TxPhyAddr); 4621 tp->TxDescArray = NULL; 4622 tp->RxDescArray = NULL; 4623 4624 pm_runtime_put_sync(&pdev->dev); 4625 4626 return 0; 4627 } 4628 4629 #ifdef CONFIG_NET_POLL_CONTROLLER 4630 static void rtl8169_netpoll(struct net_device *dev) 4631 { 4632 struct rtl8169_private *tp = netdev_priv(dev); 4633 4634 rtl8169_interrupt(tp->irq, tp); 4635 } 4636 #endif 4637 4638 static int rtl_open(struct net_device *dev) 4639 { 4640 struct rtl8169_private *tp = netdev_priv(dev); 4641 struct pci_dev *pdev = tp->pci_dev; 4642 unsigned long irqflags; 4643 int retval = -ENOMEM; 4644 4645 pm_runtime_get_sync(&pdev->dev); 4646 4647 /* 4648 * Rx and Tx descriptors needs 256 bytes alignment. 4649 * dma_alloc_coherent provides more. 4650 */ 4651 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4652 &tp->TxPhyAddr, GFP_KERNEL); 4653 if (!tp->TxDescArray) 4654 goto out; 4655 4656 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4657 &tp->RxPhyAddr, GFP_KERNEL); 4658 if (!tp->RxDescArray) 4659 goto err_free_tx_0; 4660 4661 retval = rtl8169_init_ring(tp); 4662 if (retval < 0) 4663 goto err_free_rx_1; 4664 4665 rtl_request_firmware(tp); 4666 4667 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4668 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4669 if (retval < 0) 4670 goto err_release_fw_2; 4671 4672 retval = r8169_phy_connect(tp); 4673 if (retval) 4674 goto err_free_irq; 4675 4676 rtl8169_up(tp); 4677 rtl8169_init_counter_offsets(tp); 4678 netif_start_queue(dev); 4679 out: 4680 pm_runtime_put_sync(&pdev->dev); 4681 4682 return retval; 4683 4684 err_free_irq: 4685 free_irq(tp->irq, tp); 4686 err_release_fw_2: 4687 rtl_release_firmware(tp); 4688 rtl8169_rx_clear(tp); 4689 err_free_rx_1: 4690 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4691 tp->RxPhyAddr); 4692 tp->RxDescArray = NULL; 4693 err_free_tx_0: 4694 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4695 tp->TxPhyAddr); 4696 tp->TxDescArray = NULL; 4697 goto out; 4698 } 4699 4700 static void 4701 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4702 { 4703 struct rtl8169_private *tp = netdev_priv(dev); 4704 struct pci_dev *pdev = tp->pci_dev; 4705 struct rtl8169_counters *counters = tp->counters; 4706 4707 pm_runtime_get_noresume(&pdev->dev); 4708 4709 netdev_stats_to_stats64(stats, &dev->stats); 4710 dev_fetch_sw_netstats(stats, dev->tstats); 4711 4712 /* 4713 * Fetch additional counter values missing in stats collected by driver 4714 * from tally counters. 4715 */ 4716 if (pm_runtime_active(&pdev->dev)) 4717 rtl8169_update_counters(tp); 4718 4719 /* 4720 * Subtract values fetched during initalization. 4721 * See rtl8169_init_counter_offsets for a description why we do that. 4722 */ 4723 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4724 le64_to_cpu(tp->tc_offset.tx_errors); 4725 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4726 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4727 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4728 le16_to_cpu(tp->tc_offset.tx_aborted); 4729 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4730 le16_to_cpu(tp->tc_offset.rx_missed); 4731 4732 pm_runtime_put_noidle(&pdev->dev); 4733 } 4734 4735 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4736 { 4737 netif_device_detach(tp->dev); 4738 4739 if (netif_running(tp->dev)) 4740 rtl8169_down(tp); 4741 } 4742 4743 static int rtl8169_runtime_resume(struct device *dev) 4744 { 4745 struct rtl8169_private *tp = dev_get_drvdata(dev); 4746 4747 rtl_rar_set(tp, tp->dev->dev_addr); 4748 __rtl8169_set_wol(tp, tp->saved_wolopts); 4749 4750 if (tp->TxDescArray) 4751 rtl8169_up(tp); 4752 4753 netif_device_attach(tp->dev); 4754 4755 return 0; 4756 } 4757 4758 static int rtl8169_suspend(struct device *device) 4759 { 4760 struct rtl8169_private *tp = dev_get_drvdata(device); 4761 4762 rtnl_lock(); 4763 rtl8169_net_suspend(tp); 4764 if (!device_may_wakeup(tp_to_dev(tp))) 4765 clk_disable_unprepare(tp->clk); 4766 rtnl_unlock(); 4767 4768 return 0; 4769 } 4770 4771 static int rtl8169_resume(struct device *device) 4772 { 4773 struct rtl8169_private *tp = dev_get_drvdata(device); 4774 4775 if (!device_may_wakeup(tp_to_dev(tp))) 4776 clk_prepare_enable(tp->clk); 4777 4778 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4779 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4780 rtl_init_rxcfg(tp); 4781 4782 return rtl8169_runtime_resume(device); 4783 } 4784 4785 static int rtl8169_runtime_suspend(struct device *device) 4786 { 4787 struct rtl8169_private *tp = dev_get_drvdata(device); 4788 4789 if (!tp->TxDescArray) { 4790 netif_device_detach(tp->dev); 4791 return 0; 4792 } 4793 4794 rtnl_lock(); 4795 __rtl8169_set_wol(tp, WAKE_PHY); 4796 rtl8169_net_suspend(tp); 4797 rtnl_unlock(); 4798 4799 return 0; 4800 } 4801 4802 static int rtl8169_runtime_idle(struct device *device) 4803 { 4804 struct rtl8169_private *tp = dev_get_drvdata(device); 4805 4806 if (tp->dash_enabled) 4807 return -EBUSY; 4808 4809 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4810 pm_schedule_suspend(device, 10000); 4811 4812 return -EBUSY; 4813 } 4814 4815 static const struct dev_pm_ops rtl8169_pm_ops = { 4816 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4817 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4818 rtl8169_runtime_idle) 4819 }; 4820 4821 static void rtl_shutdown(struct pci_dev *pdev) 4822 { 4823 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4824 4825 rtnl_lock(); 4826 rtl8169_net_suspend(tp); 4827 rtnl_unlock(); 4828 4829 /* Restore original MAC address */ 4830 rtl_rar_set(tp, tp->dev->perm_addr); 4831 4832 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 4833 pci_wake_from_d3(pdev, tp->saved_wolopts); 4834 pci_set_power_state(pdev, PCI_D3hot); 4835 } 4836 } 4837 4838 static void rtl_remove_one(struct pci_dev *pdev) 4839 { 4840 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4841 4842 if (pci_dev_run_wake(pdev)) 4843 pm_runtime_get_noresume(&pdev->dev); 4844 4845 unregister_netdev(tp->dev); 4846 4847 if (tp->dash_type != RTL_DASH_NONE) 4848 rtl8168_driver_stop(tp); 4849 4850 rtl_release_firmware(tp); 4851 4852 /* restore original MAC address */ 4853 rtl_rar_set(tp, tp->dev->perm_addr); 4854 } 4855 4856 static const struct net_device_ops rtl_netdev_ops = { 4857 .ndo_open = rtl_open, 4858 .ndo_stop = rtl8169_close, 4859 .ndo_get_stats64 = rtl8169_get_stats64, 4860 .ndo_start_xmit = rtl8169_start_xmit, 4861 .ndo_features_check = rtl8169_features_check, 4862 .ndo_tx_timeout = rtl8169_tx_timeout, 4863 .ndo_validate_addr = eth_validate_addr, 4864 .ndo_change_mtu = rtl8169_change_mtu, 4865 .ndo_fix_features = rtl8169_fix_features, 4866 .ndo_set_features = rtl8169_set_features, 4867 .ndo_set_mac_address = rtl_set_mac_address, 4868 .ndo_eth_ioctl = phy_do_ioctl_running, 4869 .ndo_set_rx_mode = rtl_set_rx_mode, 4870 #ifdef CONFIG_NET_POLL_CONTROLLER 4871 .ndo_poll_controller = rtl8169_netpoll, 4872 #endif 4873 4874 }; 4875 4876 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4877 { 4878 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4879 4880 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4881 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4882 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4883 /* special workaround needed */ 4884 tp->irq_mask |= RxFIFOOver; 4885 else 4886 tp->irq_mask |= RxOverflow; 4887 } 4888 4889 static int rtl_alloc_irq(struct rtl8169_private *tp) 4890 { 4891 unsigned int flags; 4892 4893 switch (tp->mac_version) { 4894 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4895 rtl_unlock_config_regs(tp); 4896 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4897 rtl_lock_config_regs(tp); 4898 fallthrough; 4899 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4900 flags = PCI_IRQ_LEGACY; 4901 break; 4902 default: 4903 flags = PCI_IRQ_ALL_TYPES; 4904 break; 4905 } 4906 4907 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4908 } 4909 4910 static void rtl_read_mac_address(struct rtl8169_private *tp, 4911 u8 mac_addr[ETH_ALEN]) 4912 { 4913 /* Get MAC address */ 4914 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 4915 u32 value; 4916 4917 value = rtl_eri_read(tp, 0xe0); 4918 put_unaligned_le32(value, mac_addr); 4919 value = rtl_eri_read(tp, 0xe4); 4920 put_unaligned_le16(value, mac_addr + 4); 4921 } else if (rtl_is_8125(tp)) { 4922 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 4923 } 4924 } 4925 4926 DECLARE_RTL_COND(rtl_link_list_ready_cond) 4927 { 4928 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 4929 } 4930 4931 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 4932 { 4933 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 4934 } 4935 4936 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 4937 { 4938 struct rtl8169_private *tp = mii_bus->priv; 4939 4940 if (phyaddr > 0) 4941 return -ENODEV; 4942 4943 return rtl_readphy(tp, phyreg); 4944 } 4945 4946 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 4947 int phyreg, u16 val) 4948 { 4949 struct rtl8169_private *tp = mii_bus->priv; 4950 4951 if (phyaddr > 0) 4952 return -ENODEV; 4953 4954 rtl_writephy(tp, phyreg, val); 4955 4956 return 0; 4957 } 4958 4959 static int r8169_mdio_register(struct rtl8169_private *tp) 4960 { 4961 struct pci_dev *pdev = tp->pci_dev; 4962 struct mii_bus *new_bus; 4963 int ret; 4964 4965 new_bus = devm_mdiobus_alloc(&pdev->dev); 4966 if (!new_bus) 4967 return -ENOMEM; 4968 4969 new_bus->name = "r8169"; 4970 new_bus->priv = tp; 4971 new_bus->parent = &pdev->dev; 4972 new_bus->irq[0] = PHY_MAC_INTERRUPT; 4973 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 4974 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 4975 4976 new_bus->read = r8169_mdio_read_reg; 4977 new_bus->write = r8169_mdio_write_reg; 4978 4979 ret = devm_mdiobus_register(&pdev->dev, new_bus); 4980 if (ret) 4981 return ret; 4982 4983 tp->phydev = mdiobus_get_phy(new_bus, 0); 4984 if (!tp->phydev) { 4985 return -ENODEV; 4986 } else if (!tp->phydev->drv) { 4987 /* Most chip versions fail with the genphy driver. 4988 * Therefore ensure that the dedicated PHY driver is loaded. 4989 */ 4990 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 4991 tp->phydev->phy_id); 4992 return -EUNATCH; 4993 } 4994 4995 tp->phydev->mac_managed_pm = true; 4996 4997 phy_support_asym_pause(tp->phydev); 4998 4999 /* PHY will be woken up in rtl_open() */ 5000 phy_suspend(tp->phydev); 5001 5002 return 0; 5003 } 5004 5005 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5006 { 5007 rtl_enable_rxdvgate(tp); 5008 5009 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5010 msleep(1); 5011 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5012 5013 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5014 r8168g_wait_ll_share_fifo_ready(tp); 5015 5016 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5017 r8168g_wait_ll_share_fifo_ready(tp); 5018 } 5019 5020 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5021 { 5022 rtl_enable_rxdvgate(tp); 5023 5024 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5025 msleep(1); 5026 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5027 5028 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5029 r8168g_wait_ll_share_fifo_ready(tp); 5030 5031 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5032 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5033 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5034 r8168g_wait_ll_share_fifo_ready(tp); 5035 } 5036 5037 static void rtl_hw_initialize(struct rtl8169_private *tp) 5038 { 5039 switch (tp->mac_version) { 5040 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5041 rtl8168ep_stop_cmac(tp); 5042 fallthrough; 5043 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5044 rtl_hw_init_8168g(tp); 5045 break; 5046 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5047 rtl_hw_init_8125(tp); 5048 break; 5049 default: 5050 break; 5051 } 5052 } 5053 5054 static int rtl_jumbo_max(struct rtl8169_private *tp) 5055 { 5056 /* Non-GBit versions don't support jumbo frames */ 5057 if (!tp->supports_gmii) 5058 return 0; 5059 5060 switch (tp->mac_version) { 5061 /* RTL8169 */ 5062 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5063 return JUMBO_7K; 5064 /* RTL8168b */ 5065 case RTL_GIGA_MAC_VER_11: 5066 case RTL_GIGA_MAC_VER_17: 5067 return JUMBO_4K; 5068 /* RTL8168c */ 5069 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5070 return JUMBO_6K; 5071 default: 5072 return JUMBO_9K; 5073 } 5074 } 5075 5076 static void rtl_init_mac_address(struct rtl8169_private *tp) 5077 { 5078 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5079 struct net_device *dev = tp->dev; 5080 int rc; 5081 5082 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5083 if (!rc) 5084 goto done; 5085 5086 rtl_read_mac_address(tp, mac_addr); 5087 if (is_valid_ether_addr(mac_addr)) 5088 goto done; 5089 5090 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5091 if (is_valid_ether_addr(mac_addr)) 5092 goto done; 5093 5094 eth_random_addr(mac_addr); 5095 dev->addr_assign_type = NET_ADDR_RANDOM; 5096 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5097 done: 5098 eth_hw_addr_set(dev, mac_addr); 5099 rtl_rar_set(tp, mac_addr); 5100 } 5101 5102 /* register is set if system vendor successfully tested ASPM 1.2 */ 5103 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5104 { 5105 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5106 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5107 return true; 5108 5109 return false; 5110 } 5111 5112 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5113 { 5114 struct rtl8169_private *tp; 5115 int jumbo_max, region, rc; 5116 enum mac_version chipset; 5117 struct net_device *dev; 5118 u32 txconfig; 5119 u16 xid; 5120 5121 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5122 if (!dev) 5123 return -ENOMEM; 5124 5125 SET_NETDEV_DEV(dev, &pdev->dev); 5126 dev->netdev_ops = &rtl_netdev_ops; 5127 tp = netdev_priv(dev); 5128 tp->dev = dev; 5129 tp->pci_dev = pdev; 5130 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5131 tp->eee_adv = -1; 5132 tp->ocp_base = OCP_STD_PHY_BASE; 5133 5134 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5135 raw_spin_lock_init(&tp->config25_lock); 5136 raw_spin_lock_init(&tp->mac_ocp_lock); 5137 5138 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5139 struct pcpu_sw_netstats); 5140 if (!dev->tstats) 5141 return -ENOMEM; 5142 5143 /* Get the *optional* external "ether_clk" used on some boards */ 5144 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5145 if (IS_ERR(tp->clk)) 5146 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5147 5148 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5149 rc = pcim_enable_device(pdev); 5150 if (rc < 0) 5151 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5152 5153 if (pcim_set_mwi(pdev) < 0) 5154 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5155 5156 /* use first MMIO region */ 5157 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5158 if (region < 0) 5159 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5160 5161 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5162 if (rc < 0) 5163 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5164 5165 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5166 5167 txconfig = RTL_R32(tp, TxConfig); 5168 if (txconfig == ~0U) 5169 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5170 5171 xid = (txconfig >> 20) & 0xfcf; 5172 5173 /* Identify chip attached to board */ 5174 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5175 if (chipset == RTL_GIGA_MAC_NONE) 5176 return dev_err_probe(&pdev->dev, -ENODEV, 5177 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5178 xid); 5179 tp->mac_version = chipset; 5180 5181 /* Disable ASPM L1 as that cause random device stop working 5182 * problems as well as full system hangs for some PCIe devices users. 5183 */ 5184 if (rtl_aspm_is_safe(tp)) 5185 rc = 0; 5186 else 5187 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5188 tp->aspm_manageable = !rc; 5189 5190 tp->dash_type = rtl_get_dash_type(tp); 5191 tp->dash_enabled = rtl_dash_is_enabled(tp); 5192 5193 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5194 5195 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5196 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5197 dev->features |= NETIF_F_HIGHDMA; 5198 5199 rtl_init_rxcfg(tp); 5200 5201 rtl8169_irq_mask_and_ack(tp); 5202 5203 rtl_hw_initialize(tp); 5204 5205 rtl_hw_reset(tp); 5206 5207 rc = rtl_alloc_irq(tp); 5208 if (rc < 0) 5209 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5210 5211 tp->irq = pci_irq_vector(pdev, 0); 5212 5213 INIT_WORK(&tp->wk.work, rtl_task); 5214 5215 rtl_init_mac_address(tp); 5216 5217 dev->ethtool_ops = &rtl8169_ethtool_ops; 5218 5219 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5220 5221 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5222 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5223 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5224 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5225 5226 /* 5227 * Pretend we are using VLANs; This bypasses a nasty bug where 5228 * Interrupts stop flowing on high load on 8110SCd controllers. 5229 */ 5230 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5231 /* Disallow toggling */ 5232 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5233 5234 if (rtl_chip_supports_csum_v2(tp)) 5235 dev->hw_features |= NETIF_F_IPV6_CSUM; 5236 5237 dev->features |= dev->hw_features; 5238 5239 /* There has been a number of reports that using SG/TSO results in 5240 * tx timeouts. However for a lot of people SG/TSO works fine. 5241 * Therefore disable both features by default, but allow users to 5242 * enable them. Use at own risk! 5243 */ 5244 if (rtl_chip_supports_csum_v2(tp)) { 5245 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5246 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5247 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5248 } else { 5249 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5250 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5251 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5252 } 5253 5254 dev->hw_features |= NETIF_F_RXALL; 5255 dev->hw_features |= NETIF_F_RXFCS; 5256 5257 netdev_sw_irq_coalesce_default_on(dev); 5258 5259 /* configure chip for default features */ 5260 rtl8169_set_features(dev, dev->features); 5261 5262 if (!tp->dash_enabled) { 5263 rtl_set_d3_pll_down(tp, true); 5264 } else { 5265 rtl_set_d3_pll_down(tp, false); 5266 dev->wol_enabled = 1; 5267 } 5268 5269 jumbo_max = rtl_jumbo_max(tp); 5270 if (jumbo_max) 5271 dev->max_mtu = jumbo_max; 5272 5273 rtl_set_irq_mask(tp); 5274 5275 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5276 5277 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5278 &tp->counters_phys_addr, 5279 GFP_KERNEL); 5280 if (!tp->counters) 5281 return -ENOMEM; 5282 5283 pci_set_drvdata(pdev, tp); 5284 5285 rc = r8169_mdio_register(tp); 5286 if (rc) 5287 return rc; 5288 5289 rc = register_netdev(dev); 5290 if (rc) 5291 return rc; 5292 5293 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5294 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5295 5296 if (jumbo_max) 5297 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5298 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5299 "ok" : "ko"); 5300 5301 if (tp->dash_type != RTL_DASH_NONE) { 5302 netdev_info(dev, "DASH %s\n", 5303 tp->dash_enabled ? "enabled" : "disabled"); 5304 rtl8168_driver_start(tp); 5305 } 5306 5307 if (pci_dev_run_wake(pdev)) 5308 pm_runtime_put_sync(&pdev->dev); 5309 5310 return 0; 5311 } 5312 5313 static struct pci_driver rtl8169_pci_driver = { 5314 .name = KBUILD_MODNAME, 5315 .id_table = rtl8169_pci_tbl, 5316 .probe = rtl_init_one, 5317 .remove = rtl_remove_one, 5318 .shutdown = rtl_shutdown, 5319 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5320 }; 5321 5322 module_pci_driver(rtl8169_pci_driver); 5323