1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define MODULENAME "r8169" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 56 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 59 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 60 61 #define R8169_MSG_DEFAULT \ 62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 63 64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 65 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 66 #define MC_FILTER_LIMIT 32 67 68 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 69 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 70 71 #define R8169_REGS_SIZE 256 72 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 73 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 74 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 77 78 #define OCP_STD_PHY_BASE 0xa400 79 80 #define RTL_CFG_NO_GBIT 1 81 82 /* write/read MMIO register */ 83 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 84 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 85 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 86 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 87 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 88 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 89 90 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) 91 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) 92 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) 93 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) 94 95 static const struct { 96 const char *name; 97 const char *fw_name; 98 } rtl_chip_infos[] = { 99 /* PCI devices. */ 100 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 101 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 102 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 103 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 104 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 105 /* PCI-E devices. */ 106 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 107 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 108 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 109 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 110 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 111 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 112 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 113 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 114 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 115 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 116 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 117 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 118 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 119 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 120 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 121 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 122 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 123 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 124 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 125 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 126 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 127 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 128 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 129 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 130 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 131 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 132 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 133 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 134 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 135 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 136 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 137 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 138 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 139 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 140 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 141 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 142 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 143 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 144 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 145 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 146 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 147 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 148 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 149 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 150 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 151 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 152 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 153 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 154 }; 155 156 static const struct pci_device_id rtl8169_pci_tbl[] = { 157 { PCI_VDEVICE(REALTEK, 0x2502) }, 158 { PCI_VDEVICE(REALTEK, 0x2600) }, 159 { PCI_VDEVICE(REALTEK, 0x8129) }, 160 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 161 { PCI_VDEVICE(REALTEK, 0x8161) }, 162 { PCI_VDEVICE(REALTEK, 0x8167) }, 163 { PCI_VDEVICE(REALTEK, 0x8168) }, 164 { PCI_VDEVICE(NCUBE, 0x8168) }, 165 { PCI_VDEVICE(REALTEK, 0x8169) }, 166 { PCI_VENDOR_ID_DLINK, 0x4300, 167 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 168 { PCI_VDEVICE(DLINK, 0x4300) }, 169 { PCI_VDEVICE(DLINK, 0x4302) }, 170 { PCI_VDEVICE(AT, 0xc107) }, 171 { PCI_VDEVICE(USR, 0x0116) }, 172 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 173 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 174 { PCI_VDEVICE(REALTEK, 0x8125) }, 175 { PCI_VDEVICE(REALTEK, 0x3000) }, 176 {} 177 }; 178 179 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 180 181 static struct { 182 u32 msg_enable; 183 } debug = { -1 }; 184 185 enum rtl_registers { 186 MAC0 = 0, /* Ethernet hardware address. */ 187 MAC4 = 4, 188 MAR0 = 8, /* Multicast filter. */ 189 CounterAddrLow = 0x10, 190 CounterAddrHigh = 0x14, 191 TxDescStartAddrLow = 0x20, 192 TxDescStartAddrHigh = 0x24, 193 TxHDescStartAddrLow = 0x28, 194 TxHDescStartAddrHigh = 0x2c, 195 FLASH = 0x30, 196 ERSR = 0x36, 197 ChipCmd = 0x37, 198 TxPoll = 0x38, 199 IntrMask = 0x3c, 200 IntrStatus = 0x3e, 201 202 TxConfig = 0x40, 203 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 204 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 205 206 RxConfig = 0x44, 207 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 208 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 209 #define RXCFG_FIFO_SHIFT 13 210 /* No threshold before first PCI xfer */ 211 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 212 #define RX_EARLY_OFF (1 << 11) 213 #define RXCFG_DMA_SHIFT 8 214 /* Unlimited maximum PCI burst. */ 215 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 216 217 Cfg9346 = 0x50, 218 Config0 = 0x51, 219 Config1 = 0x52, 220 Config2 = 0x53, 221 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 222 223 Config3 = 0x54, 224 Config4 = 0x55, 225 Config5 = 0x56, 226 PHYAR = 0x60, 227 PHYstatus = 0x6c, 228 RxMaxSize = 0xda, 229 CPlusCmd = 0xe0, 230 IntrMitigate = 0xe2, 231 232 #define RTL_COALESCE_MASK 0x0f 233 #define RTL_COALESCE_SHIFT 4 234 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) 235 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) 236 237 RxDescAddrLow = 0xe4, 238 RxDescAddrHigh = 0xe8, 239 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 240 241 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 242 243 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 244 245 #define TxPacketMax (8064 >> 7) 246 #define EarlySize 0x27 247 248 FuncEvent = 0xf0, 249 FuncEventMask = 0xf4, 250 FuncPresetState = 0xf8, 251 IBCR0 = 0xf8, 252 IBCR2 = 0xf9, 253 IBIMR0 = 0xfa, 254 IBISR0 = 0xfb, 255 FuncForceEvent = 0xfc, 256 }; 257 258 enum rtl8168_8101_registers { 259 CSIDR = 0x64, 260 CSIAR = 0x68, 261 #define CSIAR_FLAG 0x80000000 262 #define CSIAR_WRITE_CMD 0x80000000 263 #define CSIAR_BYTE_ENABLE 0x0000f000 264 #define CSIAR_ADDR_MASK 0x00000fff 265 PMCH = 0x6f, 266 EPHYAR = 0x80, 267 #define EPHYAR_FLAG 0x80000000 268 #define EPHYAR_WRITE_CMD 0x80000000 269 #define EPHYAR_REG_MASK 0x1f 270 #define EPHYAR_REG_SHIFT 16 271 #define EPHYAR_DATA_MASK 0xffff 272 DLLPR = 0xd0, 273 #define PFM_EN (1 << 6) 274 #define TX_10M_PS_EN (1 << 7) 275 DBG_REG = 0xd1, 276 #define FIX_NAK_1 (1 << 4) 277 #define FIX_NAK_2 (1 << 3) 278 TWSI = 0xd2, 279 MCU = 0xd3, 280 #define NOW_IS_OOB (1 << 7) 281 #define TX_EMPTY (1 << 5) 282 #define RX_EMPTY (1 << 4) 283 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 284 #define EN_NDP (1 << 3) 285 #define EN_OOB_RESET (1 << 2) 286 #define LINK_LIST_RDY (1 << 1) 287 EFUSEAR = 0xdc, 288 #define EFUSEAR_FLAG 0x80000000 289 #define EFUSEAR_WRITE_CMD 0x80000000 290 #define EFUSEAR_READ_CMD 0x00000000 291 #define EFUSEAR_REG_MASK 0x03ff 292 #define EFUSEAR_REG_SHIFT 8 293 #define EFUSEAR_DATA_MASK 0xff 294 MISC_1 = 0xf2, 295 #define PFM_D3COLD_EN (1 << 6) 296 }; 297 298 enum rtl8168_registers { 299 LED_FREQ = 0x1a, 300 EEE_LED = 0x1b, 301 ERIDR = 0x70, 302 ERIAR = 0x74, 303 #define ERIAR_FLAG 0x80000000 304 #define ERIAR_WRITE_CMD 0x80000000 305 #define ERIAR_READ_CMD 0x00000000 306 #define ERIAR_ADDR_BYTE_ALIGN 4 307 #define ERIAR_TYPE_SHIFT 16 308 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 310 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 312 #define ERIAR_MASK_SHIFT 12 313 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 315 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 317 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 318 EPHY_RXER_NUM = 0x7c, 319 OCPDR = 0xb0, /* OCP GPHY access */ 320 #define OCPDR_WRITE_CMD 0x80000000 321 #define OCPDR_READ_CMD 0x00000000 322 #define OCPDR_REG_MASK 0x7f 323 #define OCPDR_GPHY_REG_SHIFT 16 324 #define OCPDR_DATA_MASK 0xffff 325 OCPAR = 0xb4, 326 #define OCPAR_FLAG 0x80000000 327 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 328 #define OCPAR_GPHY_READ_CMD 0x0000f060 329 GPHY_OCP = 0xb8, 330 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 331 MISC = 0xf0, /* 8168e only. */ 332 #define TXPLA_RST (1 << 29) 333 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 334 #define PWM_EN (1 << 22) 335 #define RXDV_GATED_EN (1 << 19) 336 #define EARLY_TALLY_EN (1 << 16) 337 }; 338 339 enum rtl8125_registers { 340 IntrMask_8125 = 0x38, 341 IntrStatus_8125 = 0x3c, 342 TxPoll_8125 = 0x90, 343 MAC0_BKP = 0x19e0, 344 }; 345 346 #define RX_VLAN_INNER_8125 BIT(22) 347 #define RX_VLAN_OUTER_8125 BIT(23) 348 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 349 350 #define RX_FETCH_DFLT_8125 (8 << 27) 351 352 enum rtl_register_content { 353 /* InterruptStatusBits */ 354 SYSErr = 0x8000, 355 PCSTimeout = 0x4000, 356 SWInt = 0x0100, 357 TxDescUnavail = 0x0080, 358 RxFIFOOver = 0x0040, 359 LinkChg = 0x0020, 360 RxOverflow = 0x0010, 361 TxErr = 0x0008, 362 TxOK = 0x0004, 363 RxErr = 0x0002, 364 RxOK = 0x0001, 365 366 /* RxStatusDesc */ 367 RxRWT = (1 << 22), 368 RxRES = (1 << 21), 369 RxRUNT = (1 << 20), 370 RxCRC = (1 << 19), 371 372 /* ChipCmdBits */ 373 StopReq = 0x80, 374 CmdReset = 0x10, 375 CmdRxEnb = 0x08, 376 CmdTxEnb = 0x04, 377 RxBufEmpty = 0x01, 378 379 /* TXPoll register p.5 */ 380 HPQ = 0x80, /* Poll cmd on the high prio queue */ 381 NPQ = 0x40, /* Poll cmd on the low prio queue */ 382 FSWInt = 0x01, /* Forced software interrupt */ 383 384 /* Cfg9346Bits */ 385 Cfg9346_Lock = 0x00, 386 Cfg9346_Unlock = 0xc0, 387 388 /* rx_mode_bits */ 389 AcceptErr = 0x20, 390 AcceptRunt = 0x10, 391 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 392 AcceptBroadcast = 0x08, 393 AcceptMulticast = 0x04, 394 AcceptMyPhys = 0x02, 395 AcceptAllPhys = 0x01, 396 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 397 #define RX_CONFIG_ACCEPT_MASK 0x3f 398 399 /* TxConfigBits */ 400 TxInterFrameGapShift = 24, 401 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 402 403 /* Config1 register p.24 */ 404 LEDS1 = (1 << 7), 405 LEDS0 = (1 << 6), 406 Speed_down = (1 << 4), 407 MEMMAP = (1 << 3), 408 IOMAP = (1 << 2), 409 VPD = (1 << 1), 410 PMEnable = (1 << 0), /* Power Management Enable */ 411 412 /* Config2 register p. 25 */ 413 ClkReqEn = (1 << 7), /* Clock Request Enable */ 414 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 415 PCI_Clock_66MHz = 0x01, 416 PCI_Clock_33MHz = 0x00, 417 418 /* Config3 register p.25 */ 419 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 420 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 421 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 422 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 423 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 424 425 /* Config4 register */ 426 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 427 428 /* Config5 register p.27 */ 429 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 430 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 431 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 432 Spi_en = (1 << 3), 433 LanWake = (1 << 1), /* LanWake enable/disable */ 434 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 435 ASPM_en = (1 << 0), /* ASPM enable */ 436 437 /* CPlusCmd p.31 */ 438 EnableBist = (1 << 15), // 8168 8101 439 Mac_dbgo_oe = (1 << 14), // 8168 8101 440 EnAnaPLL = (1 << 14), // 8169 441 Normal_mode = (1 << 13), // unused 442 Force_half_dup = (1 << 12), // 8168 8101 443 Force_rxflow_en = (1 << 11), // 8168 8101 444 Force_txflow_en = (1 << 10), // 8168 8101 445 Cxpl_dbg_sel = (1 << 9), // 8168 8101 446 ASF = (1 << 8), // 8168 8101 447 PktCntrDisable = (1 << 7), // 8168 8101 448 Mac_dbgo_sel = 0x001c, // 8168 449 RxVlan = (1 << 6), 450 RxChkSum = (1 << 5), 451 PCIDAC = (1 << 4), 452 PCIMulRW = (1 << 3), 453 #define INTT_MASK GENMASK(1, 0) 454 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 455 456 /* rtl8169_PHYstatus */ 457 TBI_Enable = 0x80, 458 TxFlowCtrl = 0x40, 459 RxFlowCtrl = 0x20, 460 _1000bpsF = 0x10, 461 _100bps = 0x08, 462 _10bps = 0x04, 463 LinkStatus = 0x02, 464 FullDup = 0x01, 465 466 /* ResetCounterCommand */ 467 CounterReset = 0x1, 468 469 /* DumpCounterCommand */ 470 CounterDump = 0x8, 471 472 /* magic enable v2 */ 473 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 474 }; 475 476 enum rtl_desc_bit { 477 /* First doubleword. */ 478 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 479 RingEnd = (1 << 30), /* End of descriptor ring */ 480 FirstFrag = (1 << 29), /* First segment of a packet */ 481 LastFrag = (1 << 28), /* Final segment of a packet */ 482 }; 483 484 /* Generic case. */ 485 enum rtl_tx_desc_bit { 486 /* First doubleword. */ 487 TD_LSO = (1 << 27), /* Large Send Offload */ 488 #define TD_MSS_MAX 0x07ffu /* MSS value */ 489 490 /* Second doubleword. */ 491 TxVlanTag = (1 << 17), /* Add VLAN tag */ 492 }; 493 494 /* 8169, 8168b and 810x except 8102e. */ 495 enum rtl_tx_desc_bit_0 { 496 /* First doubleword. */ 497 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 498 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 499 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 500 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 501 }; 502 503 /* 8102e, 8168c and beyond. */ 504 enum rtl_tx_desc_bit_1 { 505 /* First doubleword. */ 506 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 507 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 508 #define GTTCPHO_SHIFT 18 509 #define GTTCPHO_MAX 0x7f 510 511 /* Second doubleword. */ 512 #define TCPHO_SHIFT 18 513 #define TCPHO_MAX 0x3ff 514 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 515 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 516 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 517 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 518 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 519 }; 520 521 enum rtl_rx_desc_bit { 522 /* Rx private */ 523 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 524 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 525 526 #define RxProtoUDP (PID1) 527 #define RxProtoTCP (PID0) 528 #define RxProtoIP (PID1 | PID0) 529 #define RxProtoMask RxProtoIP 530 531 IPFail = (1 << 16), /* IP checksum failed */ 532 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 533 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 534 RxVlanTag = (1 << 16), /* VLAN tag available */ 535 }; 536 537 #define RsvdMask 0x3fffc000 538 539 #define RTL_GSO_MAX_SIZE_V1 32000 540 #define RTL_GSO_MAX_SEGS_V1 24 541 #define RTL_GSO_MAX_SIZE_V2 64000 542 #define RTL_GSO_MAX_SEGS_V2 64 543 544 struct TxDesc { 545 __le32 opts1; 546 __le32 opts2; 547 __le64 addr; 548 }; 549 550 struct RxDesc { 551 __le32 opts1; 552 __le32 opts2; 553 __le64 addr; 554 }; 555 556 struct ring_info { 557 struct sk_buff *skb; 558 u32 len; 559 }; 560 561 struct rtl8169_counters { 562 __le64 tx_packets; 563 __le64 rx_packets; 564 __le64 tx_errors; 565 __le32 rx_errors; 566 __le16 rx_missed; 567 __le16 align_errors; 568 __le32 tx_one_collision; 569 __le32 tx_multi_collision; 570 __le64 rx_unicast; 571 __le64 rx_broadcast; 572 __le32 rx_multicast; 573 __le16 tx_aborted; 574 __le16 tx_underun; 575 }; 576 577 struct rtl8169_tc_offsets { 578 bool inited; 579 __le64 tx_errors; 580 __le32 tx_multi_collision; 581 __le16 tx_aborted; 582 __le16 rx_missed; 583 }; 584 585 enum rtl_flag { 586 RTL_FLAG_TASK_ENABLED = 0, 587 RTL_FLAG_TASK_RESET_PENDING, 588 RTL_FLAG_MAX 589 }; 590 591 struct rtl8169_stats { 592 u64 packets; 593 u64 bytes; 594 struct u64_stats_sync syncp; 595 }; 596 597 struct rtl8169_private { 598 void __iomem *mmio_addr; /* memory map physical address */ 599 struct pci_dev *pci_dev; 600 struct net_device *dev; 601 struct phy_device *phydev; 602 struct napi_struct napi; 603 u32 msg_enable; 604 enum mac_version mac_version; 605 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 606 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 607 u32 dirty_tx; 608 struct rtl8169_stats rx_stats; 609 struct rtl8169_stats tx_stats; 610 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 611 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 612 dma_addr_t TxPhyAddr; 613 dma_addr_t RxPhyAddr; 614 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 615 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 616 u16 cp_cmd; 617 u32 irq_mask; 618 struct clk *clk; 619 620 struct { 621 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 622 struct mutex mutex; 623 struct work_struct work; 624 } wk; 625 626 unsigned irq_enabled:1; 627 unsigned supports_gmii:1; 628 unsigned aspm_manageable:1; 629 dma_addr_t counters_phys_addr; 630 struct rtl8169_counters *counters; 631 struct rtl8169_tc_offsets tc_offset; 632 u32 saved_wolopts; 633 int eee_adv; 634 635 const char *fw_name; 636 struct rtl_fw *rtl_fw; 637 638 u32 ocp_base; 639 }; 640 641 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 642 643 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 644 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 645 module_param_named(debug, debug.msg_enable, int, 0); 646 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 647 MODULE_SOFTDEP("pre: realtek"); 648 MODULE_LICENSE("GPL"); 649 MODULE_FIRMWARE(FIRMWARE_8168D_1); 650 MODULE_FIRMWARE(FIRMWARE_8168D_2); 651 MODULE_FIRMWARE(FIRMWARE_8168E_1); 652 MODULE_FIRMWARE(FIRMWARE_8168E_2); 653 MODULE_FIRMWARE(FIRMWARE_8168E_3); 654 MODULE_FIRMWARE(FIRMWARE_8105E_1); 655 MODULE_FIRMWARE(FIRMWARE_8168F_1); 656 MODULE_FIRMWARE(FIRMWARE_8168F_2); 657 MODULE_FIRMWARE(FIRMWARE_8402_1); 658 MODULE_FIRMWARE(FIRMWARE_8411_1); 659 MODULE_FIRMWARE(FIRMWARE_8411_2); 660 MODULE_FIRMWARE(FIRMWARE_8106E_1); 661 MODULE_FIRMWARE(FIRMWARE_8106E_2); 662 MODULE_FIRMWARE(FIRMWARE_8168G_2); 663 MODULE_FIRMWARE(FIRMWARE_8168G_3); 664 MODULE_FIRMWARE(FIRMWARE_8168H_1); 665 MODULE_FIRMWARE(FIRMWARE_8168H_2); 666 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 667 MODULE_FIRMWARE(FIRMWARE_8107E_1); 668 MODULE_FIRMWARE(FIRMWARE_8107E_2); 669 MODULE_FIRMWARE(FIRMWARE_8125A_3); 670 671 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 672 { 673 return &tp->pci_dev->dev; 674 } 675 676 static void rtl_lock_work(struct rtl8169_private *tp) 677 { 678 mutex_lock(&tp->wk.mutex); 679 } 680 681 static void rtl_unlock_work(struct rtl8169_private *tp) 682 { 683 mutex_unlock(&tp->wk.mutex); 684 } 685 686 static void rtl_lock_config_regs(struct rtl8169_private *tp) 687 { 688 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 689 } 690 691 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 692 { 693 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 694 } 695 696 static void rtl_pci_commit(struct rtl8169_private *tp) 697 { 698 /* Read an arbitrary register to commit a preceding PCI write */ 699 RTL_R8(tp, ChipCmd); 700 } 701 702 static bool rtl_is_8125(struct rtl8169_private *tp) 703 { 704 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 705 } 706 707 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 708 { 709 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 710 tp->mac_version != RTL_GIGA_MAC_VER_39 && 711 tp->mac_version <= RTL_GIGA_MAC_VER_52; 712 } 713 714 static bool rtl_supports_eee(struct rtl8169_private *tp) 715 { 716 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 717 tp->mac_version != RTL_GIGA_MAC_VER_37 && 718 tp->mac_version != RTL_GIGA_MAC_VER_39; 719 } 720 721 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 722 { 723 int i; 724 725 for (i = 0; i < ETH_ALEN; i++) 726 mac[i] = RTL_R8(tp, reg + i); 727 } 728 729 struct rtl_cond { 730 bool (*check)(struct rtl8169_private *); 731 const char *msg; 732 }; 733 734 static void rtl_udelay(unsigned int d) 735 { 736 udelay(d); 737 } 738 739 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 740 void (*delay)(unsigned int), unsigned int d, int n, 741 bool high) 742 { 743 int i; 744 745 for (i = 0; i < n; i++) { 746 if (c->check(tp) == high) 747 return true; 748 delay(d); 749 } 750 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", 751 c->msg, !high, n, d); 752 return false; 753 } 754 755 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 756 const struct rtl_cond *c, 757 unsigned int d, int n) 758 { 759 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 760 } 761 762 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 763 const struct rtl_cond *c, 764 unsigned int d, int n) 765 { 766 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 767 } 768 769 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 770 const struct rtl_cond *c, 771 unsigned int d, int n) 772 { 773 return rtl_loop_wait(tp, c, msleep, d, n, true); 774 } 775 776 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 777 const struct rtl_cond *c, 778 unsigned int d, int n) 779 { 780 return rtl_loop_wait(tp, c, msleep, d, n, false); 781 } 782 783 #define DECLARE_RTL_COND(name) \ 784 static bool name ## _check(struct rtl8169_private *); \ 785 \ 786 static const struct rtl_cond name = { \ 787 .check = name ## _check, \ 788 .msg = #name \ 789 }; \ 790 \ 791 static bool name ## _check(struct rtl8169_private *tp) 792 793 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 794 { 795 if (reg & 0xffff0001) { 796 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); 797 return true; 798 } 799 return false; 800 } 801 802 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 803 { 804 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 805 } 806 807 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 808 { 809 if (rtl_ocp_reg_failure(tp, reg)) 810 return; 811 812 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 813 814 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 815 } 816 817 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 818 { 819 if (rtl_ocp_reg_failure(tp, reg)) 820 return 0; 821 822 RTL_W32(tp, GPHY_OCP, reg << 15); 823 824 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 825 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 826 } 827 828 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 829 { 830 if (rtl_ocp_reg_failure(tp, reg)) 831 return; 832 833 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 834 } 835 836 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 837 { 838 if (rtl_ocp_reg_failure(tp, reg)) 839 return 0; 840 841 RTL_W32(tp, OCPDR, reg << 15); 842 843 return RTL_R32(tp, OCPDR); 844 } 845 846 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 847 u16 set) 848 { 849 u16 data = r8168_mac_ocp_read(tp, reg); 850 851 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 852 } 853 854 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 855 { 856 if (reg == 0x1f) { 857 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 858 return; 859 } 860 861 if (tp->ocp_base != OCP_STD_PHY_BASE) 862 reg -= 0x10; 863 864 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 865 } 866 867 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 868 { 869 if (reg == 0x1f) 870 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 871 872 if (tp->ocp_base != OCP_STD_PHY_BASE) 873 reg -= 0x10; 874 875 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 876 } 877 878 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 879 { 880 if (reg == 0x1f) { 881 tp->ocp_base = value << 4; 882 return; 883 } 884 885 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 886 } 887 888 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 889 { 890 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 891 } 892 893 DECLARE_RTL_COND(rtl_phyar_cond) 894 { 895 return RTL_R32(tp, PHYAR) & 0x80000000; 896 } 897 898 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 899 { 900 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 901 902 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 903 /* 904 * According to hardware specs a 20us delay is required after write 905 * complete indication, but before sending next command. 906 */ 907 udelay(20); 908 } 909 910 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 911 { 912 int value; 913 914 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 915 916 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 917 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 918 919 /* 920 * According to hardware specs a 20us delay is required after read 921 * complete indication, but before sending next command. 922 */ 923 udelay(20); 924 925 return value; 926 } 927 928 DECLARE_RTL_COND(rtl_ocpar_cond) 929 { 930 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 931 } 932 933 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 934 { 935 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 936 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 937 RTL_W32(tp, EPHY_RXER_NUM, 0); 938 939 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 940 } 941 942 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 943 { 944 r8168dp_1_mdio_access(tp, reg, 945 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 946 } 947 948 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 949 { 950 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 951 952 mdelay(1); 953 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 954 RTL_W32(tp, EPHY_RXER_NUM, 0); 955 956 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 957 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 958 } 959 960 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 961 962 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 963 { 964 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 965 } 966 967 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 968 { 969 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 970 } 971 972 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 973 { 974 r8168dp_2_mdio_start(tp); 975 976 r8169_mdio_write(tp, reg, value); 977 978 r8168dp_2_mdio_stop(tp); 979 } 980 981 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 982 { 983 int value; 984 985 /* Work around issue with chip reporting wrong PHY ID */ 986 if (reg == MII_PHYSID2) 987 return 0xc912; 988 989 r8168dp_2_mdio_start(tp); 990 991 value = r8169_mdio_read(tp, reg); 992 993 r8168dp_2_mdio_stop(tp); 994 995 return value; 996 } 997 998 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 999 { 1000 switch (tp->mac_version) { 1001 case RTL_GIGA_MAC_VER_27: 1002 r8168dp_1_mdio_write(tp, location, val); 1003 break; 1004 case RTL_GIGA_MAC_VER_28: 1005 case RTL_GIGA_MAC_VER_31: 1006 r8168dp_2_mdio_write(tp, location, val); 1007 break; 1008 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1009 r8168g_mdio_write(tp, location, val); 1010 break; 1011 default: 1012 r8169_mdio_write(tp, location, val); 1013 break; 1014 } 1015 } 1016 1017 static int rtl_readphy(struct rtl8169_private *tp, int location) 1018 { 1019 switch (tp->mac_version) { 1020 case RTL_GIGA_MAC_VER_27: 1021 return r8168dp_1_mdio_read(tp, location); 1022 case RTL_GIGA_MAC_VER_28: 1023 case RTL_GIGA_MAC_VER_31: 1024 return r8168dp_2_mdio_read(tp, location); 1025 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1026 return r8168g_mdio_read(tp, location); 1027 default: 1028 return r8169_mdio_read(tp, location); 1029 } 1030 } 1031 1032 DECLARE_RTL_COND(rtl_ephyar_cond) 1033 { 1034 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1035 } 1036 1037 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1038 { 1039 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1040 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1041 1042 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1043 1044 udelay(10); 1045 } 1046 1047 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1048 { 1049 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1050 1051 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1052 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1053 } 1054 1055 DECLARE_RTL_COND(rtl_eriar_cond) 1056 { 1057 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1058 } 1059 1060 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1061 u32 val, int type) 1062 { 1063 BUG_ON((addr & 3) || (mask == 0)); 1064 RTL_W32(tp, ERIDR, val); 1065 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1066 1067 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1068 } 1069 1070 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1071 u32 val) 1072 { 1073 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1074 } 1075 1076 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1077 { 1078 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1079 1080 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1081 RTL_R32(tp, ERIDR) : ~0; 1082 } 1083 1084 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1085 { 1086 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1087 } 1088 1089 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1090 u32 m) 1091 { 1092 u32 val; 1093 1094 val = rtl_eri_read(tp, addr); 1095 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1096 } 1097 1098 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1099 u32 p) 1100 { 1101 rtl_w0w1_eri(tp, addr, mask, p, 0); 1102 } 1103 1104 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1105 u32 m) 1106 { 1107 rtl_w0w1_eri(tp, addr, mask, 0, m); 1108 } 1109 1110 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1111 { 1112 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1113 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1114 RTL_R32(tp, OCPDR) : ~0; 1115 } 1116 1117 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1118 { 1119 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1120 } 1121 1122 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1123 u32 data) 1124 { 1125 RTL_W32(tp, OCPDR, data); 1126 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1127 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1128 } 1129 1130 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1131 u32 data) 1132 { 1133 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1134 data, ERIAR_OOB); 1135 } 1136 1137 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1138 { 1139 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1140 1141 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1142 } 1143 1144 #define OOB_CMD_RESET 0x00 1145 #define OOB_CMD_DRIVER_START 0x05 1146 #define OOB_CMD_DRIVER_STOP 0x06 1147 1148 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1149 { 1150 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1151 } 1152 1153 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1154 { 1155 u16 reg; 1156 1157 reg = rtl8168_get_ocp_reg(tp); 1158 1159 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1160 } 1161 1162 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1163 { 1164 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1165 } 1166 1167 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1168 { 1169 return RTL_R8(tp, IBISR0) & 0x20; 1170 } 1171 1172 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1173 { 1174 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1175 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1176 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1177 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1178 } 1179 1180 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1181 { 1182 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1183 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1184 } 1185 1186 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1187 { 1188 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1189 r8168ep_ocp_write(tp, 0x01, 0x30, 1190 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1191 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1192 } 1193 1194 static void rtl8168_driver_start(struct rtl8169_private *tp) 1195 { 1196 switch (tp->mac_version) { 1197 case RTL_GIGA_MAC_VER_27: 1198 case RTL_GIGA_MAC_VER_28: 1199 case RTL_GIGA_MAC_VER_31: 1200 rtl8168dp_driver_start(tp); 1201 break; 1202 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1203 rtl8168ep_driver_start(tp); 1204 break; 1205 default: 1206 BUG(); 1207 break; 1208 } 1209 } 1210 1211 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1212 { 1213 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1214 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1215 } 1216 1217 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1218 { 1219 rtl8168ep_stop_cmac(tp); 1220 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1221 r8168ep_ocp_write(tp, 0x01, 0x30, 1222 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1223 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1224 } 1225 1226 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1227 { 1228 switch (tp->mac_version) { 1229 case RTL_GIGA_MAC_VER_27: 1230 case RTL_GIGA_MAC_VER_28: 1231 case RTL_GIGA_MAC_VER_31: 1232 rtl8168dp_driver_stop(tp); 1233 break; 1234 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1235 rtl8168ep_driver_stop(tp); 1236 break; 1237 default: 1238 BUG(); 1239 break; 1240 } 1241 } 1242 1243 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1244 { 1245 u16 reg = rtl8168_get_ocp_reg(tp); 1246 1247 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1248 } 1249 1250 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1251 { 1252 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1253 } 1254 1255 static bool r8168_check_dash(struct rtl8169_private *tp) 1256 { 1257 switch (tp->mac_version) { 1258 case RTL_GIGA_MAC_VER_27: 1259 case RTL_GIGA_MAC_VER_28: 1260 case RTL_GIGA_MAC_VER_31: 1261 return r8168dp_check_dash(tp); 1262 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1263 return r8168ep_check_dash(tp); 1264 default: 1265 return false; 1266 } 1267 } 1268 1269 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1270 { 1271 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1272 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1273 } 1274 1275 DECLARE_RTL_COND(rtl_efusear_cond) 1276 { 1277 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1278 } 1279 1280 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1281 { 1282 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1283 1284 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1285 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1286 } 1287 1288 static u32 rtl_get_events(struct rtl8169_private *tp) 1289 { 1290 if (rtl_is_8125(tp)) 1291 return RTL_R32(tp, IntrStatus_8125); 1292 else 1293 return RTL_R16(tp, IntrStatus); 1294 } 1295 1296 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1297 { 1298 if (rtl_is_8125(tp)) 1299 RTL_W32(tp, IntrStatus_8125, bits); 1300 else 1301 RTL_W16(tp, IntrStatus, bits); 1302 } 1303 1304 static void rtl_irq_disable(struct rtl8169_private *tp) 1305 { 1306 if (rtl_is_8125(tp)) 1307 RTL_W32(tp, IntrMask_8125, 0); 1308 else 1309 RTL_W16(tp, IntrMask, 0); 1310 tp->irq_enabled = 0; 1311 } 1312 1313 static void rtl_irq_enable(struct rtl8169_private *tp) 1314 { 1315 tp->irq_enabled = 1; 1316 if (rtl_is_8125(tp)) 1317 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1318 else 1319 RTL_W16(tp, IntrMask, tp->irq_mask); 1320 } 1321 1322 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1323 { 1324 rtl_irq_disable(tp); 1325 rtl_ack_events(tp, 0xffffffff); 1326 rtl_pci_commit(tp); 1327 } 1328 1329 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1330 { 1331 struct phy_device *phydev = tp->phydev; 1332 1333 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1334 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1335 if (phydev->speed == SPEED_1000) { 1336 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1337 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1338 } else if (phydev->speed == SPEED_100) { 1339 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1340 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1341 } else { 1342 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1343 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1344 } 1345 rtl_reset_packet_filter(tp); 1346 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1347 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1348 if (phydev->speed == SPEED_1000) { 1349 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1350 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1351 } else { 1352 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1353 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1354 } 1355 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1356 if (phydev->speed == SPEED_10) { 1357 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1358 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1359 } else { 1360 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1361 } 1362 } 1363 } 1364 1365 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1366 1367 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1368 { 1369 struct rtl8169_private *tp = netdev_priv(dev); 1370 1371 rtl_lock_work(tp); 1372 wol->supported = WAKE_ANY; 1373 wol->wolopts = tp->saved_wolopts; 1374 rtl_unlock_work(tp); 1375 } 1376 1377 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1378 { 1379 static const struct { 1380 u32 opt; 1381 u16 reg; 1382 u8 mask; 1383 } cfg[] = { 1384 { WAKE_PHY, Config3, LinkUp }, 1385 { WAKE_UCAST, Config5, UWF }, 1386 { WAKE_BCAST, Config5, BWF }, 1387 { WAKE_MCAST, Config5, MWF }, 1388 { WAKE_ANY, Config5, LanWake }, 1389 { WAKE_MAGIC, Config3, MagicPacket } 1390 }; 1391 unsigned int i, tmp = ARRAY_SIZE(cfg); 1392 u8 options; 1393 1394 rtl_unlock_config_regs(tp); 1395 1396 if (rtl_is_8168evl_up(tp)) { 1397 tmp--; 1398 if (wolopts & WAKE_MAGIC) 1399 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1400 MagicPacket_v2); 1401 else 1402 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1403 MagicPacket_v2); 1404 } else if (rtl_is_8125(tp)) { 1405 tmp--; 1406 if (wolopts & WAKE_MAGIC) 1407 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1408 else 1409 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1410 } 1411 1412 for (i = 0; i < tmp; i++) { 1413 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1414 if (wolopts & cfg[i].opt) 1415 options |= cfg[i].mask; 1416 RTL_W8(tp, cfg[i].reg, options); 1417 } 1418 1419 switch (tp->mac_version) { 1420 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1421 options = RTL_R8(tp, Config1) & ~PMEnable; 1422 if (wolopts) 1423 options |= PMEnable; 1424 RTL_W8(tp, Config1, options); 1425 break; 1426 case RTL_GIGA_MAC_VER_34: 1427 case RTL_GIGA_MAC_VER_37: 1428 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52: 1429 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1430 if (wolopts) 1431 options |= PME_SIGNAL; 1432 RTL_W8(tp, Config2, options); 1433 break; 1434 default: 1435 break; 1436 } 1437 1438 rtl_lock_config_regs(tp); 1439 1440 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1441 tp->dev->wol_enabled = wolopts ? 1 : 0; 1442 } 1443 1444 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1445 { 1446 struct rtl8169_private *tp = netdev_priv(dev); 1447 struct device *d = tp_to_dev(tp); 1448 1449 if (wol->wolopts & ~WAKE_ANY) 1450 return -EINVAL; 1451 1452 pm_runtime_get_noresume(d); 1453 1454 rtl_lock_work(tp); 1455 1456 tp->saved_wolopts = wol->wolopts; 1457 1458 if (pm_runtime_active(d)) 1459 __rtl8169_set_wol(tp, tp->saved_wolopts); 1460 1461 rtl_unlock_work(tp); 1462 1463 pm_runtime_put_noidle(d); 1464 1465 return 0; 1466 } 1467 1468 static void rtl8169_get_drvinfo(struct net_device *dev, 1469 struct ethtool_drvinfo *info) 1470 { 1471 struct rtl8169_private *tp = netdev_priv(dev); 1472 struct rtl_fw *rtl_fw = tp->rtl_fw; 1473 1474 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1475 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1476 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1477 if (rtl_fw) 1478 strlcpy(info->fw_version, rtl_fw->version, 1479 sizeof(info->fw_version)); 1480 } 1481 1482 static int rtl8169_get_regs_len(struct net_device *dev) 1483 { 1484 return R8169_REGS_SIZE; 1485 } 1486 1487 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1488 netdev_features_t features) 1489 { 1490 struct rtl8169_private *tp = netdev_priv(dev); 1491 1492 if (dev->mtu > TD_MSS_MAX) 1493 features &= ~NETIF_F_ALL_TSO; 1494 1495 if (dev->mtu > ETH_DATA_LEN && 1496 tp->mac_version > RTL_GIGA_MAC_VER_06) 1497 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1498 1499 return features; 1500 } 1501 1502 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1503 netdev_features_t features) 1504 { 1505 u32 rx_config = RTL_R32(tp, RxConfig); 1506 1507 if (features & NETIF_F_RXALL) 1508 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1509 else 1510 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1511 1512 if (rtl_is_8125(tp)) { 1513 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1514 rx_config |= RX_VLAN_8125; 1515 else 1516 rx_config &= ~RX_VLAN_8125; 1517 } 1518 1519 RTL_W32(tp, RxConfig, rx_config); 1520 } 1521 1522 static int rtl8169_set_features(struct net_device *dev, 1523 netdev_features_t features) 1524 { 1525 struct rtl8169_private *tp = netdev_priv(dev); 1526 1527 rtl_lock_work(tp); 1528 1529 rtl_set_rx_config_features(tp, features); 1530 1531 if (features & NETIF_F_RXCSUM) 1532 tp->cp_cmd |= RxChkSum; 1533 else 1534 tp->cp_cmd &= ~RxChkSum; 1535 1536 if (!rtl_is_8125(tp)) { 1537 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1538 tp->cp_cmd |= RxVlan; 1539 else 1540 tp->cp_cmd &= ~RxVlan; 1541 } 1542 1543 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1544 rtl_pci_commit(tp); 1545 1546 rtl_unlock_work(tp); 1547 1548 return 0; 1549 } 1550 1551 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1552 { 1553 return (skb_vlan_tag_present(skb)) ? 1554 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1555 } 1556 1557 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1558 { 1559 u32 opts2 = le32_to_cpu(desc->opts2); 1560 1561 if (opts2 & RxVlanTag) 1562 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1563 } 1564 1565 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1566 void *p) 1567 { 1568 struct rtl8169_private *tp = netdev_priv(dev); 1569 u32 __iomem *data = tp->mmio_addr; 1570 u32 *dw = p; 1571 int i; 1572 1573 rtl_lock_work(tp); 1574 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1575 memcpy_fromio(dw++, data++, 4); 1576 rtl_unlock_work(tp); 1577 } 1578 1579 static u32 rtl8169_get_msglevel(struct net_device *dev) 1580 { 1581 struct rtl8169_private *tp = netdev_priv(dev); 1582 1583 return tp->msg_enable; 1584 } 1585 1586 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1587 { 1588 struct rtl8169_private *tp = netdev_priv(dev); 1589 1590 tp->msg_enable = value; 1591 } 1592 1593 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1594 "tx_packets", 1595 "rx_packets", 1596 "tx_errors", 1597 "rx_errors", 1598 "rx_missed", 1599 "align_errors", 1600 "tx_single_collisions", 1601 "tx_multi_collisions", 1602 "unicast", 1603 "broadcast", 1604 "multicast", 1605 "tx_aborted", 1606 "tx_underrun", 1607 }; 1608 1609 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1610 { 1611 switch (sset) { 1612 case ETH_SS_STATS: 1613 return ARRAY_SIZE(rtl8169_gstrings); 1614 default: 1615 return -EOPNOTSUPP; 1616 } 1617 } 1618 1619 DECLARE_RTL_COND(rtl_counters_cond) 1620 { 1621 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1622 } 1623 1624 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1625 { 1626 dma_addr_t paddr = tp->counters_phys_addr; 1627 u32 cmd; 1628 1629 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1630 rtl_pci_commit(tp); 1631 cmd = (u64)paddr & DMA_BIT_MASK(32); 1632 RTL_W32(tp, CounterAddrLow, cmd); 1633 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1634 1635 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1636 } 1637 1638 static bool rtl8169_reset_counters(struct rtl8169_private *tp) 1639 { 1640 /* 1641 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1642 * tally counters. 1643 */ 1644 if (tp->mac_version < RTL_GIGA_MAC_VER_19) 1645 return true; 1646 1647 return rtl8169_do_counters(tp, CounterReset); 1648 } 1649 1650 static bool rtl8169_update_counters(struct rtl8169_private *tp) 1651 { 1652 u8 val = RTL_R8(tp, ChipCmd); 1653 1654 /* 1655 * Some chips are unable to dump tally counters when the receiver 1656 * is disabled. If 0xff chip may be in a PCI power-save state. 1657 */ 1658 if (!(val & CmdRxEnb) || val == 0xff) 1659 return true; 1660 1661 return rtl8169_do_counters(tp, CounterDump); 1662 } 1663 1664 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1665 { 1666 struct rtl8169_counters *counters = tp->counters; 1667 bool ret = false; 1668 1669 /* 1670 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1671 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1672 * reset by a power cycle, while the counter values collected by the 1673 * driver are reset at every driver unload/load cycle. 1674 * 1675 * To make sure the HW values returned by @get_stats64 match the SW 1676 * values, we collect the initial values at first open(*) and use them 1677 * as offsets to normalize the values returned by @get_stats64. 1678 * 1679 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1680 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1681 * set at open time by rtl_hw_start. 1682 */ 1683 1684 if (tp->tc_offset.inited) 1685 return true; 1686 1687 /* If both, reset and update fail, propagate to caller. */ 1688 if (rtl8169_reset_counters(tp)) 1689 ret = true; 1690 1691 if (rtl8169_update_counters(tp)) 1692 ret = true; 1693 1694 tp->tc_offset.tx_errors = counters->tx_errors; 1695 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1696 tp->tc_offset.tx_aborted = counters->tx_aborted; 1697 tp->tc_offset.rx_missed = counters->rx_missed; 1698 tp->tc_offset.inited = true; 1699 1700 return ret; 1701 } 1702 1703 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1704 struct ethtool_stats *stats, u64 *data) 1705 { 1706 struct rtl8169_private *tp = netdev_priv(dev); 1707 struct device *d = tp_to_dev(tp); 1708 struct rtl8169_counters *counters = tp->counters; 1709 1710 ASSERT_RTNL(); 1711 1712 pm_runtime_get_noresume(d); 1713 1714 if (pm_runtime_active(d)) 1715 rtl8169_update_counters(tp); 1716 1717 pm_runtime_put_noidle(d); 1718 1719 data[0] = le64_to_cpu(counters->tx_packets); 1720 data[1] = le64_to_cpu(counters->rx_packets); 1721 data[2] = le64_to_cpu(counters->tx_errors); 1722 data[3] = le32_to_cpu(counters->rx_errors); 1723 data[4] = le16_to_cpu(counters->rx_missed); 1724 data[5] = le16_to_cpu(counters->align_errors); 1725 data[6] = le32_to_cpu(counters->tx_one_collision); 1726 data[7] = le32_to_cpu(counters->tx_multi_collision); 1727 data[8] = le64_to_cpu(counters->rx_unicast); 1728 data[9] = le64_to_cpu(counters->rx_broadcast); 1729 data[10] = le32_to_cpu(counters->rx_multicast); 1730 data[11] = le16_to_cpu(counters->tx_aborted); 1731 data[12] = le16_to_cpu(counters->tx_underun); 1732 } 1733 1734 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1735 { 1736 switch(stringset) { 1737 case ETH_SS_STATS: 1738 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1739 break; 1740 } 1741 } 1742 1743 /* 1744 * Interrupt coalescing 1745 * 1746 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1747 * > 8169, 8168 and 810x line of chipsets 1748 * 1749 * 8169, 8168, and 8136(810x) serial chipsets support it. 1750 * 1751 * > 2 - the Tx timer unit at gigabit speed 1752 * 1753 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1754 * (0xe0) bit 1 and bit 0. 1755 * 1756 * For 8169 1757 * bit[1:0] \ speed 1000M 100M 10M 1758 * 0 0 320ns 2.56us 40.96us 1759 * 0 1 2.56us 20.48us 327.7us 1760 * 1 0 5.12us 40.96us 655.4us 1761 * 1 1 10.24us 81.92us 1.31ms 1762 * 1763 * For the other 1764 * bit[1:0] \ speed 1000M 100M 10M 1765 * 0 0 5us 2.56us 40.96us 1766 * 0 1 40us 20.48us 327.7us 1767 * 1 0 80us 40.96us 655.4us 1768 * 1 1 160us 81.92us 1.31ms 1769 */ 1770 1771 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ 1772 struct rtl_coalesce_scale { 1773 /* Rx / Tx */ 1774 u32 nsecs[2]; 1775 }; 1776 1777 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1778 struct rtl_coalesce_info { 1779 u32 speed; 1780 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ 1781 }; 1782 1783 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ 1784 #define rxtx_x1822(r, t) { \ 1785 {{(r), (t)}}, \ 1786 {{(r)*8, (t)*8}}, \ 1787 {{(r)*8*2, (t)*8*2}}, \ 1788 {{(r)*8*2*2, (t)*8*2*2}}, \ 1789 } 1790 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1791 /* speed delays: rx00 tx00 */ 1792 { SPEED_10, rxtx_x1822(40960, 40960) }, 1793 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1794 { SPEED_1000, rxtx_x1822( 320, 320) }, 1795 { 0 }, 1796 }; 1797 1798 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1799 /* speed delays: rx00 tx00 */ 1800 { SPEED_10, rxtx_x1822(40960, 40960) }, 1801 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1802 { SPEED_1000, rxtx_x1822( 5000, 5000) }, 1803 { 0 }, 1804 }; 1805 #undef rxtx_x1822 1806 1807 /* get rx/tx scale vector corresponding to current speed */ 1808 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) 1809 { 1810 struct rtl8169_private *tp = netdev_priv(dev); 1811 const struct rtl_coalesce_info *ci; 1812 1813 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1814 ci = rtl_coalesce_info_8169; 1815 else 1816 ci = rtl_coalesce_info_8168_8136; 1817 1818 for (; ci->speed; ci++) { 1819 if (tp->phydev->speed == ci->speed) 1820 return ci; 1821 } 1822 1823 return ERR_PTR(-ELNRNG); 1824 } 1825 1826 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1827 { 1828 struct rtl8169_private *tp = netdev_priv(dev); 1829 const struct rtl_coalesce_info *ci; 1830 const struct rtl_coalesce_scale *scale; 1831 struct { 1832 u32 *max_frames; 1833 u32 *usecs; 1834 } coal_settings [] = { 1835 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, 1836 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } 1837 }, *p = coal_settings; 1838 int i; 1839 u16 w; 1840 1841 if (rtl_is_8125(tp)) 1842 return -EOPNOTSUPP; 1843 1844 memset(ec, 0, sizeof(*ec)); 1845 1846 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1847 ci = rtl_coalesce_info(dev); 1848 if (IS_ERR(ci)) 1849 return PTR_ERR(ci); 1850 1851 scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; 1852 1853 /* read IntrMitigate and adjust according to scale */ 1854 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { 1855 *p->max_frames = (w & RTL_COALESCE_MASK) << 2; 1856 w >>= RTL_COALESCE_SHIFT; 1857 *p->usecs = w & RTL_COALESCE_MASK; 1858 } 1859 1860 for (i = 0; i < 2; i++) { 1861 p = coal_settings + i; 1862 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; 1863 1864 /* 1865 * ethtool_coalesce says it is illegal to set both usecs and 1866 * max_frames to 0. 1867 */ 1868 if (!*p->usecs && !*p->max_frames) 1869 *p->max_frames = 1; 1870 } 1871 1872 return 0; 1873 } 1874 1875 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ 1876 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( 1877 struct net_device *dev, u32 nsec, u16 *cp01) 1878 { 1879 const struct rtl_coalesce_info *ci; 1880 u16 i; 1881 1882 ci = rtl_coalesce_info(dev); 1883 if (IS_ERR(ci)) 1884 return ERR_CAST(ci); 1885 1886 for (i = 0; i < 4; i++) { 1887 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], 1888 ci->scalev[i].nsecs[1]); 1889 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { 1890 *cp01 = i; 1891 return &ci->scalev[i]; 1892 } 1893 } 1894 1895 return ERR_PTR(-EINVAL); 1896 } 1897 1898 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1899 { 1900 struct rtl8169_private *tp = netdev_priv(dev); 1901 const struct rtl_coalesce_scale *scale; 1902 struct { 1903 u32 frames; 1904 u32 usecs; 1905 } coal_settings [] = { 1906 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, 1907 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } 1908 }, *p = coal_settings; 1909 u16 w = 0, cp01; 1910 int i; 1911 1912 if (rtl_is_8125(tp)) 1913 return -EOPNOTSUPP; 1914 1915 scale = rtl_coalesce_choose_scale(dev, 1916 max(p[0].usecs, p[1].usecs) * 1000, &cp01); 1917 if (IS_ERR(scale)) 1918 return PTR_ERR(scale); 1919 1920 for (i = 0; i < 2; i++, p++) { 1921 u32 units; 1922 1923 /* 1924 * accept max_frames=1 we returned in rtl_get_coalesce. 1925 * accept it not only when usecs=0 because of e.g. the following scenario: 1926 * 1927 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1928 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1929 * - then user does `ethtool -C eth0 rx-usecs 100` 1930 * 1931 * since ethtool sends to kernel whole ethtool_coalesce 1932 * settings, if we do not handle rx_usecs=!0, rx_frames=1 1933 * we'll reject it below in `frames % 4 != 0`. 1934 */ 1935 if (p->frames == 1) { 1936 p->frames = 0; 1937 } 1938 1939 units = p->usecs * 1000 / scale->nsecs[i]; 1940 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) 1941 return -EINVAL; 1942 1943 w <<= RTL_COALESCE_SHIFT; 1944 w |= units; 1945 w <<= RTL_COALESCE_SHIFT; 1946 w |= p->frames >> 2; 1947 } 1948 1949 rtl_lock_work(tp); 1950 1951 RTL_W16(tp, IntrMitigate, swab16(w)); 1952 1953 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1954 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1955 rtl_pci_commit(tp); 1956 1957 rtl_unlock_work(tp); 1958 1959 return 0; 1960 } 1961 1962 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1963 { 1964 struct rtl8169_private *tp = netdev_priv(dev); 1965 struct device *d = tp_to_dev(tp); 1966 int ret; 1967 1968 if (!rtl_supports_eee(tp)) 1969 return -EOPNOTSUPP; 1970 1971 pm_runtime_get_noresume(d); 1972 1973 if (!pm_runtime_active(d)) { 1974 ret = -EOPNOTSUPP; 1975 } else { 1976 ret = phy_ethtool_get_eee(tp->phydev, data); 1977 } 1978 1979 pm_runtime_put_noidle(d); 1980 1981 return ret; 1982 } 1983 1984 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1985 { 1986 struct rtl8169_private *tp = netdev_priv(dev); 1987 struct device *d = tp_to_dev(tp); 1988 int ret; 1989 1990 if (!rtl_supports_eee(tp)) 1991 return -EOPNOTSUPP; 1992 1993 pm_runtime_get_noresume(d); 1994 1995 if (!pm_runtime_active(d)) { 1996 ret = -EOPNOTSUPP; 1997 goto out; 1998 } 1999 2000 if (dev->phydev->autoneg == AUTONEG_DISABLE || 2001 dev->phydev->duplex != DUPLEX_FULL) { 2002 ret = -EPROTONOSUPPORT; 2003 goto out; 2004 } 2005 2006 ret = phy_ethtool_set_eee(tp->phydev, data); 2007 2008 if (!ret) 2009 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 2010 MDIO_AN_EEE_ADV); 2011 out: 2012 pm_runtime_put_noidle(d); 2013 return ret; 2014 } 2015 2016 static const struct ethtool_ops rtl8169_ethtool_ops = { 2017 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2018 ETHTOOL_COALESCE_MAX_FRAMES, 2019 .get_drvinfo = rtl8169_get_drvinfo, 2020 .get_regs_len = rtl8169_get_regs_len, 2021 .get_link = ethtool_op_get_link, 2022 .get_coalesce = rtl_get_coalesce, 2023 .set_coalesce = rtl_set_coalesce, 2024 .get_msglevel = rtl8169_get_msglevel, 2025 .set_msglevel = rtl8169_set_msglevel, 2026 .get_regs = rtl8169_get_regs, 2027 .get_wol = rtl8169_get_wol, 2028 .set_wol = rtl8169_set_wol, 2029 .get_strings = rtl8169_get_strings, 2030 .get_sset_count = rtl8169_get_sset_count, 2031 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2032 .get_ts_info = ethtool_op_get_ts_info, 2033 .nway_reset = phy_ethtool_nway_reset, 2034 .get_eee = rtl8169_get_eee, 2035 .set_eee = rtl8169_set_eee, 2036 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2037 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2038 }; 2039 2040 static void rtl_enable_eee(struct rtl8169_private *tp) 2041 { 2042 struct phy_device *phydev = tp->phydev; 2043 int adv; 2044 2045 /* respect EEE advertisement the user may have set */ 2046 if (tp->eee_adv >= 0) 2047 adv = tp->eee_adv; 2048 else 2049 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2050 2051 if (adv >= 0) 2052 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 2053 } 2054 2055 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2056 { 2057 /* 2058 * The driver currently handles the 8168Bf and the 8168Be identically 2059 * but they can be identified more specifically through the test below 2060 * if needed: 2061 * 2062 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2063 * 2064 * Same thing for the 8101Eb and the 8101Ec: 2065 * 2066 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2067 */ 2068 static const struct rtl_mac_info { 2069 u16 mask; 2070 u16 val; 2071 enum mac_version ver; 2072 } mac_info[] = { 2073 /* 8125 family. */ 2074 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2075 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2076 2077 /* RTL8117 */ 2078 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2079 2080 /* 8168EP family. */ 2081 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2082 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2083 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2084 2085 /* 8168H family. */ 2086 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2087 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2088 2089 /* 8168G family. */ 2090 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2091 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2092 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2093 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2094 2095 /* 8168F family. */ 2096 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2097 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2098 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2099 2100 /* 8168E family. */ 2101 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2102 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2103 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2104 2105 /* 8168D family. */ 2106 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2107 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2108 2109 /* 8168DP family. */ 2110 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2111 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2112 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2113 2114 /* 8168C family. */ 2115 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2116 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2117 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2118 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2119 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2120 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2121 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2122 2123 /* 8168B family. */ 2124 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2125 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2126 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2127 2128 /* 8101 family. */ 2129 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2130 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2131 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2132 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2133 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2134 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2135 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2136 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2137 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2138 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2139 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2140 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2141 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2142 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2143 /* FIXME: where did these entries come from ? -- FR */ 2144 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2145 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2146 2147 /* 8110 family. */ 2148 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2149 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2150 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2151 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2152 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2153 2154 /* Catch-all */ 2155 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2156 }; 2157 const struct rtl_mac_info *p = mac_info; 2158 enum mac_version ver; 2159 2160 while ((xid & p->mask) != p->val) 2161 p++; 2162 ver = p->ver; 2163 2164 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2165 if (ver == RTL_GIGA_MAC_VER_42) 2166 ver = RTL_GIGA_MAC_VER_43; 2167 else if (ver == RTL_GIGA_MAC_VER_45) 2168 ver = RTL_GIGA_MAC_VER_47; 2169 else if (ver == RTL_GIGA_MAC_VER_46) 2170 ver = RTL_GIGA_MAC_VER_48; 2171 } 2172 2173 return ver; 2174 } 2175 2176 static void rtl_release_firmware(struct rtl8169_private *tp) 2177 { 2178 if (tp->rtl_fw) { 2179 rtl_fw_release_firmware(tp->rtl_fw); 2180 kfree(tp->rtl_fw); 2181 tp->rtl_fw = NULL; 2182 } 2183 } 2184 2185 void r8169_apply_firmware(struct rtl8169_private *tp) 2186 { 2187 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2188 if (tp->rtl_fw) 2189 rtl_fw_write_firmware(tp, tp->rtl_fw); 2190 } 2191 2192 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2193 { 2194 /* Adjust EEE LED frequency */ 2195 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2196 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2197 2198 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2199 } 2200 2201 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2202 { 2203 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2204 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2205 } 2206 2207 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2208 { 2209 const u16 w[] = { 2210 addr[0] | (addr[1] << 8), 2211 addr[2] | (addr[3] << 8), 2212 addr[4] | (addr[5] << 8) 2213 }; 2214 2215 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2216 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2217 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2218 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2219 } 2220 2221 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2222 { 2223 u16 data1, data2, ioffset; 2224 2225 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2226 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2227 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2228 2229 ioffset = (data2 >> 1) & 0x7ff8; 2230 ioffset |= data2 & 0x0007; 2231 if (data1 & BIT(7)) 2232 ioffset |= BIT(15); 2233 2234 return ioffset; 2235 } 2236 2237 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2238 { 2239 set_bit(flag, tp->wk.flags); 2240 schedule_work(&tp->wk.work); 2241 } 2242 2243 static void rtl8169_init_phy(struct rtl8169_private *tp) 2244 { 2245 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2246 2247 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2248 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2249 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2250 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2251 RTL_W8(tp, 0x82, 0x01); 2252 } 2253 2254 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2255 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2256 tp->pci_dev->subsystem_device == 0xe000) 2257 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2258 2259 /* We may have called phy_speed_down before */ 2260 phy_speed_up(tp->phydev); 2261 2262 if (rtl_supports_eee(tp)) 2263 rtl_enable_eee(tp); 2264 2265 genphy_soft_reset(tp->phydev); 2266 } 2267 2268 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 2269 { 2270 rtl_lock_work(tp); 2271 2272 rtl_unlock_config_regs(tp); 2273 2274 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 2275 rtl_pci_commit(tp); 2276 2277 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2278 rtl_pci_commit(tp); 2279 2280 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2281 rtl_rar_exgmac_set(tp, addr); 2282 2283 rtl_lock_config_regs(tp); 2284 2285 rtl_unlock_work(tp); 2286 } 2287 2288 static int rtl_set_mac_address(struct net_device *dev, void *p) 2289 { 2290 struct rtl8169_private *tp = netdev_priv(dev); 2291 struct device *d = tp_to_dev(tp); 2292 int ret; 2293 2294 ret = eth_mac_addr(dev, p); 2295 if (ret) 2296 return ret; 2297 2298 pm_runtime_get_noresume(d); 2299 2300 if (pm_runtime_active(d)) 2301 rtl_rar_set(tp, dev->dev_addr); 2302 2303 pm_runtime_put_noidle(d); 2304 2305 return 0; 2306 } 2307 2308 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 2309 { 2310 switch (tp->mac_version) { 2311 case RTL_GIGA_MAC_VER_25: 2312 case RTL_GIGA_MAC_VER_26: 2313 case RTL_GIGA_MAC_VER_29: 2314 case RTL_GIGA_MAC_VER_30: 2315 case RTL_GIGA_MAC_VER_32: 2316 case RTL_GIGA_MAC_VER_33: 2317 case RTL_GIGA_MAC_VER_34: 2318 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61: 2319 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2320 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2321 break; 2322 default: 2323 break; 2324 } 2325 } 2326 2327 static void rtl_pll_power_down(struct rtl8169_private *tp) 2328 { 2329 if (r8168_check_dash(tp)) 2330 return; 2331 2332 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2333 tp->mac_version == RTL_GIGA_MAC_VER_33) 2334 rtl_ephy_write(tp, 0x19, 0xff64); 2335 2336 if (device_may_wakeup(tp_to_dev(tp))) { 2337 phy_speed_down(tp->phydev, false); 2338 rtl_wol_suspend_quirk(tp); 2339 return; 2340 } 2341 2342 switch (tp->mac_version) { 2343 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2344 case RTL_GIGA_MAC_VER_37: 2345 case RTL_GIGA_MAC_VER_39: 2346 case RTL_GIGA_MAC_VER_43: 2347 case RTL_GIGA_MAC_VER_44: 2348 case RTL_GIGA_MAC_VER_45: 2349 case RTL_GIGA_MAC_VER_46: 2350 case RTL_GIGA_MAC_VER_47: 2351 case RTL_GIGA_MAC_VER_48: 2352 case RTL_GIGA_MAC_VER_50: 2353 case RTL_GIGA_MAC_VER_51: 2354 case RTL_GIGA_MAC_VER_52: 2355 case RTL_GIGA_MAC_VER_60: 2356 case RTL_GIGA_MAC_VER_61: 2357 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2358 break; 2359 case RTL_GIGA_MAC_VER_40: 2360 case RTL_GIGA_MAC_VER_41: 2361 case RTL_GIGA_MAC_VER_49: 2362 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 2363 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2364 break; 2365 default: 2366 break; 2367 } 2368 } 2369 2370 static void rtl_pll_power_up(struct rtl8169_private *tp) 2371 { 2372 switch (tp->mac_version) { 2373 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2374 case RTL_GIGA_MAC_VER_37: 2375 case RTL_GIGA_MAC_VER_39: 2376 case RTL_GIGA_MAC_VER_43: 2377 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 2378 break; 2379 case RTL_GIGA_MAC_VER_44: 2380 case RTL_GIGA_MAC_VER_45: 2381 case RTL_GIGA_MAC_VER_46: 2382 case RTL_GIGA_MAC_VER_47: 2383 case RTL_GIGA_MAC_VER_48: 2384 case RTL_GIGA_MAC_VER_50: 2385 case RTL_GIGA_MAC_VER_51: 2386 case RTL_GIGA_MAC_VER_52: 2387 case RTL_GIGA_MAC_VER_60: 2388 case RTL_GIGA_MAC_VER_61: 2389 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2390 break; 2391 case RTL_GIGA_MAC_VER_40: 2392 case RTL_GIGA_MAC_VER_41: 2393 case RTL_GIGA_MAC_VER_49: 2394 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2395 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 2396 break; 2397 default: 2398 break; 2399 } 2400 2401 phy_resume(tp->phydev); 2402 } 2403 2404 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2405 { 2406 switch (tp->mac_version) { 2407 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2408 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2409 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2410 break; 2411 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2412 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2413 case RTL_GIGA_MAC_VER_38: 2414 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2415 break; 2416 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2417 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2418 break; 2419 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2420 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2421 break; 2422 default: 2423 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2424 break; 2425 } 2426 } 2427 2428 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2429 { 2430 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2431 } 2432 2433 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2434 { 2435 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2436 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2437 } 2438 2439 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2440 { 2441 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2442 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2443 } 2444 2445 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2446 { 2447 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2448 } 2449 2450 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2451 { 2452 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2453 } 2454 2455 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2456 { 2457 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2458 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2459 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2460 } 2461 2462 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2463 { 2464 RTL_W8(tp, MaxTxPacketSize, 0x0c); 2465 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2466 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2467 } 2468 2469 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2470 { 2471 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2472 } 2473 2474 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2475 { 2476 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2477 } 2478 2479 static void rtl_jumbo_config(struct rtl8169_private *tp) 2480 { 2481 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2482 2483 rtl_unlock_config_regs(tp); 2484 switch (tp->mac_version) { 2485 case RTL_GIGA_MAC_VER_12: 2486 case RTL_GIGA_MAC_VER_17: 2487 if (jumbo) { 2488 pcie_set_readrq(tp->pci_dev, 512); 2489 r8168b_1_hw_jumbo_enable(tp); 2490 } else { 2491 r8168b_1_hw_jumbo_disable(tp); 2492 } 2493 break; 2494 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2495 if (jumbo) { 2496 pcie_set_readrq(tp->pci_dev, 512); 2497 r8168c_hw_jumbo_enable(tp); 2498 } else { 2499 r8168c_hw_jumbo_disable(tp); 2500 } 2501 break; 2502 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2503 if (jumbo) 2504 r8168dp_hw_jumbo_enable(tp); 2505 else 2506 r8168dp_hw_jumbo_disable(tp); 2507 break; 2508 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2509 if (jumbo) { 2510 pcie_set_readrq(tp->pci_dev, 512); 2511 r8168e_hw_jumbo_enable(tp); 2512 } else { 2513 r8168e_hw_jumbo_disable(tp); 2514 } 2515 break; 2516 default: 2517 break; 2518 } 2519 rtl_lock_config_regs(tp); 2520 2521 if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2522 pcie_set_readrq(tp->pci_dev, 4096); 2523 } 2524 2525 DECLARE_RTL_COND(rtl_chipcmd_cond) 2526 { 2527 return RTL_R8(tp, ChipCmd) & CmdReset; 2528 } 2529 2530 static void rtl_hw_reset(struct rtl8169_private *tp) 2531 { 2532 RTL_W8(tp, ChipCmd, CmdReset); 2533 2534 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2535 } 2536 2537 static void rtl_request_firmware(struct rtl8169_private *tp) 2538 { 2539 struct rtl_fw *rtl_fw; 2540 2541 /* firmware loaded already or no firmware available */ 2542 if (tp->rtl_fw || !tp->fw_name) 2543 return; 2544 2545 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2546 if (!rtl_fw) { 2547 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n"); 2548 return; 2549 } 2550 2551 rtl_fw->phy_write = rtl_writephy; 2552 rtl_fw->phy_read = rtl_readphy; 2553 rtl_fw->mac_mcu_write = mac_mcu_write; 2554 rtl_fw->mac_mcu_read = mac_mcu_read; 2555 rtl_fw->fw_name = tp->fw_name; 2556 rtl_fw->dev = tp_to_dev(tp); 2557 2558 if (rtl_fw_request_firmware(rtl_fw)) 2559 kfree(rtl_fw); 2560 else 2561 tp->rtl_fw = rtl_fw; 2562 } 2563 2564 static void rtl_rx_close(struct rtl8169_private *tp) 2565 { 2566 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2567 } 2568 2569 DECLARE_RTL_COND(rtl_npq_cond) 2570 { 2571 return RTL_R8(tp, TxPoll) & NPQ; 2572 } 2573 2574 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2575 { 2576 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2577 } 2578 2579 static void rtl8169_hw_reset(struct rtl8169_private *tp) 2580 { 2581 /* Disable interrupts */ 2582 rtl8169_irq_mask_and_ack(tp); 2583 2584 rtl_rx_close(tp); 2585 2586 switch (tp->mac_version) { 2587 case RTL_GIGA_MAC_VER_27: 2588 case RTL_GIGA_MAC_VER_28: 2589 case RTL_GIGA_MAC_VER_31: 2590 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 2591 break; 2592 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2593 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2594 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2595 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 2596 break; 2597 default: 2598 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2599 udelay(100); 2600 break; 2601 } 2602 2603 rtl_hw_reset(tp); 2604 } 2605 2606 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2607 { 2608 u32 val = TX_DMA_BURST << TxDMAShift | 2609 InterFrameGap << TxInterFrameGapShift; 2610 2611 if (rtl_is_8168evl_up(tp)) 2612 val |= TXCFG_AUTO_FIFO; 2613 2614 RTL_W32(tp, TxConfig, val); 2615 } 2616 2617 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2618 { 2619 /* Low hurts. Let's disable the filtering. */ 2620 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2621 } 2622 2623 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2624 { 2625 /* 2626 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2627 * register to be written before TxDescAddrLow to work. 2628 * Switching from MMIO to I/O access fixes the issue as well. 2629 */ 2630 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2631 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2632 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2633 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2634 } 2635 2636 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) 2637 { 2638 u32 val; 2639 2640 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2641 val = 0x000fff00; 2642 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2643 val = 0x00ffff00; 2644 else 2645 return; 2646 2647 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2648 val |= 0xff; 2649 2650 RTL_W32(tp, 0x7c, val); 2651 } 2652 2653 static void rtl_set_rx_mode(struct net_device *dev) 2654 { 2655 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2656 /* Multicast hash filter */ 2657 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2658 struct rtl8169_private *tp = netdev_priv(dev); 2659 u32 tmp; 2660 2661 if (dev->flags & IFF_PROMISC) { 2662 /* Unconditionally log net taps. */ 2663 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); 2664 rx_mode |= AcceptAllPhys; 2665 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2666 dev->flags & IFF_ALLMULTI || 2667 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2668 /* accept all multicasts */ 2669 } else if (netdev_mc_empty(dev)) { 2670 rx_mode &= ~AcceptMulticast; 2671 } else { 2672 struct netdev_hw_addr *ha; 2673 2674 mc_filter[1] = mc_filter[0] = 0; 2675 netdev_for_each_mc_addr(ha, dev) { 2676 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2677 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2678 } 2679 2680 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2681 tmp = mc_filter[0]; 2682 mc_filter[0] = swab32(mc_filter[1]); 2683 mc_filter[1] = swab32(tmp); 2684 } 2685 } 2686 2687 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2688 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2689 2690 tmp = RTL_R32(tp, RxConfig); 2691 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2692 } 2693 2694 DECLARE_RTL_COND(rtl_csiar_cond) 2695 { 2696 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2697 } 2698 2699 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2700 { 2701 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2702 2703 RTL_W32(tp, CSIDR, value); 2704 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2705 CSIAR_BYTE_ENABLE | func << 16); 2706 2707 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2708 } 2709 2710 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2711 { 2712 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2713 2714 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2715 CSIAR_BYTE_ENABLE); 2716 2717 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2718 RTL_R32(tp, CSIDR) : ~0; 2719 } 2720 2721 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2722 { 2723 struct pci_dev *pdev = tp->pci_dev; 2724 u32 csi; 2725 2726 /* According to Realtek the value at config space address 0x070f 2727 * controls the L0s/L1 entrance latency. We try standard ECAM access 2728 * first and if it fails fall back to CSI. 2729 */ 2730 if (pdev->cfg_size > 0x070f && 2731 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2732 return; 2733 2734 netdev_notice_once(tp->dev, 2735 "No native access to PCI extended config space, falling back to CSI\n"); 2736 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2737 rtl_csi_write(tp, 0x070c, csi | val << 24); 2738 } 2739 2740 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2741 { 2742 rtl_csi_access_enable(tp, 0x27); 2743 } 2744 2745 struct ephy_info { 2746 unsigned int offset; 2747 u16 mask; 2748 u16 bits; 2749 }; 2750 2751 static void __rtl_ephy_init(struct rtl8169_private *tp, 2752 const struct ephy_info *e, int len) 2753 { 2754 u16 w; 2755 2756 while (len-- > 0) { 2757 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2758 rtl_ephy_write(tp, e->offset, w); 2759 e++; 2760 } 2761 } 2762 2763 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2764 2765 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2766 { 2767 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2768 PCI_EXP_LNKCTL_CLKREQ_EN); 2769 } 2770 2771 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2772 { 2773 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2774 PCI_EXP_LNKCTL_CLKREQ_EN); 2775 } 2776 2777 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2778 { 2779 /* work around an issue when PCI reset occurs during L2/L3 state */ 2780 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2781 } 2782 2783 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2784 { 2785 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2786 if (enable && tp->aspm_manageable) { 2787 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2788 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2789 } else { 2790 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2791 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2792 } 2793 2794 udelay(10); 2795 } 2796 2797 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2798 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2799 { 2800 /* Usage of dynamic vs. static FIFO is controlled by bit 2801 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2802 */ 2803 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2804 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2805 } 2806 2807 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2808 u8 low, u8 high) 2809 { 2810 /* FIFO thresholds for pause flow control */ 2811 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2812 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2813 } 2814 2815 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2816 { 2817 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2818 } 2819 2820 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2821 { 2822 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2823 2824 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2825 2826 rtl_disable_clock_request(tp); 2827 } 2828 2829 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2830 { 2831 static const struct ephy_info e_info_8168cp[] = { 2832 { 0x01, 0, 0x0001 }, 2833 { 0x02, 0x0800, 0x1000 }, 2834 { 0x03, 0, 0x0042 }, 2835 { 0x06, 0x0080, 0x0000 }, 2836 { 0x07, 0, 0x2000 } 2837 }; 2838 2839 rtl_set_def_aspm_entry_latency(tp); 2840 2841 rtl_ephy_init(tp, e_info_8168cp); 2842 2843 __rtl_hw_start_8168cp(tp); 2844 } 2845 2846 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2847 { 2848 rtl_set_def_aspm_entry_latency(tp); 2849 2850 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2851 } 2852 2853 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2854 { 2855 rtl_set_def_aspm_entry_latency(tp); 2856 2857 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2858 2859 /* Magic. */ 2860 RTL_W8(tp, DBG_REG, 0x20); 2861 } 2862 2863 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2864 { 2865 static const struct ephy_info e_info_8168c_1[] = { 2866 { 0x02, 0x0800, 0x1000 }, 2867 { 0x03, 0, 0x0002 }, 2868 { 0x06, 0x0080, 0x0000 } 2869 }; 2870 2871 rtl_set_def_aspm_entry_latency(tp); 2872 2873 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2874 2875 rtl_ephy_init(tp, e_info_8168c_1); 2876 2877 __rtl_hw_start_8168cp(tp); 2878 } 2879 2880 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2881 { 2882 static const struct ephy_info e_info_8168c_2[] = { 2883 { 0x01, 0, 0x0001 }, 2884 { 0x03, 0x0400, 0x0020 } 2885 }; 2886 2887 rtl_set_def_aspm_entry_latency(tp); 2888 2889 rtl_ephy_init(tp, e_info_8168c_2); 2890 2891 __rtl_hw_start_8168cp(tp); 2892 } 2893 2894 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2895 { 2896 rtl_hw_start_8168c_2(tp); 2897 } 2898 2899 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2900 { 2901 rtl_set_def_aspm_entry_latency(tp); 2902 2903 __rtl_hw_start_8168cp(tp); 2904 } 2905 2906 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2907 { 2908 rtl_set_def_aspm_entry_latency(tp); 2909 2910 rtl_disable_clock_request(tp); 2911 } 2912 2913 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2914 { 2915 static const struct ephy_info e_info_8168d_4[] = { 2916 { 0x0b, 0x0000, 0x0048 }, 2917 { 0x19, 0x0020, 0x0050 }, 2918 { 0x0c, 0x0100, 0x0020 }, 2919 { 0x10, 0x0004, 0x0000 }, 2920 }; 2921 2922 rtl_set_def_aspm_entry_latency(tp); 2923 2924 rtl_ephy_init(tp, e_info_8168d_4); 2925 2926 rtl_enable_clock_request(tp); 2927 } 2928 2929 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2930 { 2931 static const struct ephy_info e_info_8168e_1[] = { 2932 { 0x00, 0x0200, 0x0100 }, 2933 { 0x00, 0x0000, 0x0004 }, 2934 { 0x06, 0x0002, 0x0001 }, 2935 { 0x06, 0x0000, 0x0030 }, 2936 { 0x07, 0x0000, 0x2000 }, 2937 { 0x00, 0x0000, 0x0020 }, 2938 { 0x03, 0x5800, 0x2000 }, 2939 { 0x03, 0x0000, 0x0001 }, 2940 { 0x01, 0x0800, 0x1000 }, 2941 { 0x07, 0x0000, 0x4000 }, 2942 { 0x1e, 0x0000, 0x2000 }, 2943 { 0x19, 0xffff, 0xfe6c }, 2944 { 0x0a, 0x0000, 0x0040 } 2945 }; 2946 2947 rtl_set_def_aspm_entry_latency(tp); 2948 2949 rtl_ephy_init(tp, e_info_8168e_1); 2950 2951 rtl_disable_clock_request(tp); 2952 2953 /* Reset tx FIFO pointer */ 2954 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2955 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2956 2957 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2958 } 2959 2960 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2961 { 2962 static const struct ephy_info e_info_8168e_2[] = { 2963 { 0x09, 0x0000, 0x0080 }, 2964 { 0x19, 0x0000, 0x0224 }, 2965 { 0x00, 0x0000, 0x0004 }, 2966 { 0x0c, 0x3df0, 0x0200 }, 2967 }; 2968 2969 rtl_set_def_aspm_entry_latency(tp); 2970 2971 rtl_ephy_init(tp, e_info_8168e_2); 2972 2973 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2974 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2975 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2976 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2977 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2978 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 2979 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 2980 2981 rtl_disable_clock_request(tp); 2982 2983 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2984 2985 rtl8168_config_eee_mac(tp); 2986 2987 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2988 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2989 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2990 2991 rtl_hw_aspm_clkreq_enable(tp, true); 2992 } 2993 2994 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2995 { 2996 rtl_set_def_aspm_entry_latency(tp); 2997 2998 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2999 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3000 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3001 rtl_reset_packet_filter(tp); 3002 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 3003 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 3004 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3005 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3006 3007 rtl_disable_clock_request(tp); 3008 3009 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3010 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3011 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3012 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 3013 3014 rtl8168_config_eee_mac(tp); 3015 } 3016 3017 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3018 { 3019 static const struct ephy_info e_info_8168f_1[] = { 3020 { 0x06, 0x00c0, 0x0020 }, 3021 { 0x08, 0x0001, 0x0002 }, 3022 { 0x09, 0x0000, 0x0080 }, 3023 { 0x19, 0x0000, 0x0224 }, 3024 { 0x00, 0x0000, 0x0004 }, 3025 { 0x0c, 0x3df0, 0x0200 }, 3026 }; 3027 3028 rtl_hw_start_8168f(tp); 3029 3030 rtl_ephy_init(tp, e_info_8168f_1); 3031 3032 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 3033 } 3034 3035 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3036 { 3037 static const struct ephy_info e_info_8168f_1[] = { 3038 { 0x06, 0x00c0, 0x0020 }, 3039 { 0x0f, 0xffff, 0x5200 }, 3040 { 0x19, 0x0000, 0x0224 }, 3041 { 0x00, 0x0000, 0x0004 }, 3042 { 0x0c, 0x3df0, 0x0200 }, 3043 }; 3044 3045 rtl_hw_start_8168f(tp); 3046 rtl_pcie_state_l2l3_disable(tp); 3047 3048 rtl_ephy_init(tp, e_info_8168f_1); 3049 3050 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 3051 } 3052 3053 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3054 { 3055 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3056 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3057 3058 rtl_set_def_aspm_entry_latency(tp); 3059 3060 rtl_reset_packet_filter(tp); 3061 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3062 3063 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3064 3065 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3066 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3067 3068 rtl8168_config_eee_mac(tp); 3069 3070 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 3071 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3072 3073 rtl_pcie_state_l2l3_disable(tp); 3074 } 3075 3076 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3077 { 3078 static const struct ephy_info e_info_8168g_1[] = { 3079 { 0x00, 0x0008, 0x0000 }, 3080 { 0x0c, 0x3ff0, 0x0820 }, 3081 { 0x1e, 0x0000, 0x0001 }, 3082 { 0x19, 0x8000, 0x0000 } 3083 }; 3084 3085 rtl_hw_start_8168g(tp); 3086 3087 /* disable aspm and clock request before access ephy */ 3088 rtl_hw_aspm_clkreq_enable(tp, false); 3089 rtl_ephy_init(tp, e_info_8168g_1); 3090 rtl_hw_aspm_clkreq_enable(tp, true); 3091 } 3092 3093 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3094 { 3095 static const struct ephy_info e_info_8168g_2[] = { 3096 { 0x00, 0x0008, 0x0000 }, 3097 { 0x0c, 0x3ff0, 0x0820 }, 3098 { 0x19, 0xffff, 0x7c00 }, 3099 { 0x1e, 0xffff, 0x20eb }, 3100 { 0x0d, 0xffff, 0x1666 }, 3101 { 0x00, 0xffff, 0x10a3 }, 3102 { 0x06, 0xffff, 0xf050 }, 3103 { 0x04, 0x0000, 0x0010 }, 3104 { 0x1d, 0x4000, 0x0000 }, 3105 }; 3106 3107 rtl_hw_start_8168g(tp); 3108 3109 /* disable aspm and clock request before access ephy */ 3110 rtl_hw_aspm_clkreq_enable(tp, false); 3111 rtl_ephy_init(tp, e_info_8168g_2); 3112 } 3113 3114 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3115 { 3116 static const struct ephy_info e_info_8411_2[] = { 3117 { 0x00, 0x0008, 0x0000 }, 3118 { 0x0c, 0x37d0, 0x0820 }, 3119 { 0x1e, 0x0000, 0x0001 }, 3120 { 0x19, 0x8021, 0x0000 }, 3121 { 0x1e, 0x0000, 0x2000 }, 3122 { 0x0d, 0x0100, 0x0200 }, 3123 { 0x00, 0x0000, 0x0080 }, 3124 { 0x06, 0x0000, 0x0010 }, 3125 { 0x04, 0x0000, 0x0010 }, 3126 { 0x1d, 0x0000, 0x4000 }, 3127 }; 3128 3129 rtl_hw_start_8168g(tp); 3130 3131 /* disable aspm and clock request before access ephy */ 3132 rtl_hw_aspm_clkreq_enable(tp, false); 3133 rtl_ephy_init(tp, e_info_8411_2); 3134 3135 /* The following Realtek-provided magic fixes an issue with the RX unit 3136 * getting confused after the PHY having been powered-down. 3137 */ 3138 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3139 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3140 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3141 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3142 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3143 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3144 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3145 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3146 mdelay(3); 3147 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3148 3149 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3150 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3151 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3152 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3153 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3154 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3155 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3156 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3157 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3158 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3159 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3160 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3161 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3162 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3163 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3164 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3165 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3166 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3167 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3168 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3169 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3170 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3171 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3172 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3173 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3174 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3175 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3176 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3177 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3178 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3179 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3180 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3181 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3182 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3183 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3184 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3185 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3186 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3187 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3188 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3189 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3190 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3191 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3192 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3193 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3194 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3195 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3196 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3197 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3198 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3199 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3200 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3201 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3202 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3203 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3204 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3205 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3206 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3207 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3208 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3209 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3210 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3211 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3212 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3213 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3214 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3215 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3216 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3217 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3218 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3219 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3220 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3221 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3222 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3223 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3224 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3225 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3226 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3227 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3228 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3229 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3230 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3231 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3232 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3233 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3234 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3235 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3236 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3237 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3238 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3239 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3240 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3241 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3242 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3243 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3244 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3245 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3246 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3247 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3248 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3249 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3250 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3251 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3252 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3253 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3254 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3255 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3256 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3257 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3258 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3259 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3260 3261 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3262 3263 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3264 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3265 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3266 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3267 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3268 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3269 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3270 3271 rtl_hw_aspm_clkreq_enable(tp, true); 3272 } 3273 3274 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3275 { 3276 static const struct ephy_info e_info_8168h_1[] = { 3277 { 0x1e, 0x0800, 0x0001 }, 3278 { 0x1d, 0x0000, 0x0800 }, 3279 { 0x05, 0xffff, 0x2089 }, 3280 { 0x06, 0xffff, 0x5881 }, 3281 { 0x04, 0xffff, 0x854a }, 3282 { 0x01, 0xffff, 0x068b } 3283 }; 3284 int rg_saw_cnt; 3285 3286 /* disable aspm and clock request before access ephy */ 3287 rtl_hw_aspm_clkreq_enable(tp, false); 3288 rtl_ephy_init(tp, e_info_8168h_1); 3289 3290 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3291 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3292 3293 rtl_set_def_aspm_entry_latency(tp); 3294 3295 rtl_reset_packet_filter(tp); 3296 3297 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 3298 3299 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 3300 3301 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3302 3303 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3304 3305 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3306 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3307 3308 rtl8168_config_eee_mac(tp); 3309 3310 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3311 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3312 3313 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3314 3315 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3316 3317 rtl_pcie_state_l2l3_disable(tp); 3318 3319 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3320 if (rg_saw_cnt > 0) { 3321 u16 sw_cnt_1ms_ini; 3322 3323 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3324 sw_cnt_1ms_ini &= 0x0fff; 3325 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3326 } 3327 3328 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3329 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3330 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3331 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3332 3333 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3334 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3335 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3336 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3337 3338 rtl_hw_aspm_clkreq_enable(tp, true); 3339 } 3340 3341 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3342 { 3343 rtl8168ep_stop_cmac(tp); 3344 3345 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3346 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3347 3348 rtl_set_def_aspm_entry_latency(tp); 3349 3350 rtl_reset_packet_filter(tp); 3351 3352 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 3353 3354 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3355 3356 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3357 3358 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3359 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3360 3361 rtl8168_config_eee_mac(tp); 3362 3363 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 3364 3365 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3366 3367 rtl_pcie_state_l2l3_disable(tp); 3368 } 3369 3370 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3371 { 3372 static const struct ephy_info e_info_8168ep_1[] = { 3373 { 0x00, 0xffff, 0x10ab }, 3374 { 0x06, 0xffff, 0xf030 }, 3375 { 0x08, 0xffff, 0x2006 }, 3376 { 0x0d, 0xffff, 0x1666 }, 3377 { 0x0c, 0x3ff0, 0x0000 } 3378 }; 3379 3380 /* disable aspm and clock request before access ephy */ 3381 rtl_hw_aspm_clkreq_enable(tp, false); 3382 rtl_ephy_init(tp, e_info_8168ep_1); 3383 3384 rtl_hw_start_8168ep(tp); 3385 3386 rtl_hw_aspm_clkreq_enable(tp, true); 3387 } 3388 3389 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3390 { 3391 static const struct ephy_info e_info_8168ep_2[] = { 3392 { 0x00, 0xffff, 0x10a3 }, 3393 { 0x19, 0xffff, 0xfc00 }, 3394 { 0x1e, 0xffff, 0x20ea } 3395 }; 3396 3397 /* disable aspm and clock request before access ephy */ 3398 rtl_hw_aspm_clkreq_enable(tp, false); 3399 rtl_ephy_init(tp, e_info_8168ep_2); 3400 3401 rtl_hw_start_8168ep(tp); 3402 3403 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3404 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3405 3406 rtl_hw_aspm_clkreq_enable(tp, true); 3407 } 3408 3409 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3410 { 3411 static const struct ephy_info e_info_8168ep_3[] = { 3412 { 0x00, 0x0000, 0x0080 }, 3413 { 0x0d, 0x0100, 0x0200 }, 3414 { 0x19, 0x8021, 0x0000 }, 3415 { 0x1e, 0x0000, 0x2000 }, 3416 }; 3417 3418 /* disable aspm and clock request before access ephy */ 3419 rtl_hw_aspm_clkreq_enable(tp, false); 3420 rtl_ephy_init(tp, e_info_8168ep_3); 3421 3422 rtl_hw_start_8168ep(tp); 3423 3424 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3425 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3426 3427 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3428 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3429 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3430 3431 rtl_hw_aspm_clkreq_enable(tp, true); 3432 } 3433 3434 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3435 { 3436 static const struct ephy_info e_info_8117[] = { 3437 { 0x19, 0x0040, 0x1100 }, 3438 { 0x59, 0x0040, 0x1100 }, 3439 }; 3440 int rg_saw_cnt; 3441 3442 rtl8168ep_stop_cmac(tp); 3443 3444 /* disable aspm and clock request before access ephy */ 3445 rtl_hw_aspm_clkreq_enable(tp, false); 3446 rtl_ephy_init(tp, e_info_8117); 3447 3448 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3449 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3450 3451 rtl_set_def_aspm_entry_latency(tp); 3452 3453 rtl_reset_packet_filter(tp); 3454 3455 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90); 3456 3457 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3458 3459 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3460 3461 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3462 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3463 3464 rtl8168_config_eee_mac(tp); 3465 3466 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3467 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3468 3469 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3470 3471 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3472 3473 rtl_pcie_state_l2l3_disable(tp); 3474 3475 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3476 if (rg_saw_cnt > 0) { 3477 u16 sw_cnt_1ms_ini; 3478 3479 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3480 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3481 } 3482 3483 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3484 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3485 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3486 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3487 3488 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3489 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3490 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3491 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3492 3493 /* firmware is for MAC only */ 3494 r8169_apply_firmware(tp); 3495 3496 rtl_hw_aspm_clkreq_enable(tp, true); 3497 } 3498 3499 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3500 { 3501 static const struct ephy_info e_info_8102e_1[] = { 3502 { 0x01, 0, 0x6e65 }, 3503 { 0x02, 0, 0x091f }, 3504 { 0x03, 0, 0xc2f9 }, 3505 { 0x06, 0, 0xafb5 }, 3506 { 0x07, 0, 0x0e00 }, 3507 { 0x19, 0, 0xec80 }, 3508 { 0x01, 0, 0x2e65 }, 3509 { 0x01, 0, 0x6e65 } 3510 }; 3511 u8 cfg1; 3512 3513 rtl_set_def_aspm_entry_latency(tp); 3514 3515 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3516 3517 RTL_W8(tp, Config1, 3518 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3519 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3520 3521 cfg1 = RTL_R8(tp, Config1); 3522 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3523 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3524 3525 rtl_ephy_init(tp, e_info_8102e_1); 3526 } 3527 3528 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3529 { 3530 rtl_set_def_aspm_entry_latency(tp); 3531 3532 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3533 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3534 } 3535 3536 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3537 { 3538 rtl_hw_start_8102e_2(tp); 3539 3540 rtl_ephy_write(tp, 0x03, 0xc2f9); 3541 } 3542 3543 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3544 { 3545 static const struct ephy_info e_info_8105e_1[] = { 3546 { 0x07, 0, 0x4000 }, 3547 { 0x19, 0, 0x0200 }, 3548 { 0x19, 0, 0x0020 }, 3549 { 0x1e, 0, 0x2000 }, 3550 { 0x03, 0, 0x0001 }, 3551 { 0x19, 0, 0x0100 }, 3552 { 0x19, 0, 0x0004 }, 3553 { 0x0a, 0, 0x0020 } 3554 }; 3555 3556 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3557 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3558 3559 /* Disable Early Tally Counter */ 3560 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3561 3562 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3563 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3564 3565 rtl_ephy_init(tp, e_info_8105e_1); 3566 3567 rtl_pcie_state_l2l3_disable(tp); 3568 } 3569 3570 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3571 { 3572 rtl_hw_start_8105e_1(tp); 3573 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3574 } 3575 3576 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3577 { 3578 static const struct ephy_info e_info_8402[] = { 3579 { 0x19, 0xffff, 0xff64 }, 3580 { 0x1e, 0, 0x4000 } 3581 }; 3582 3583 rtl_set_def_aspm_entry_latency(tp); 3584 3585 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3586 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3587 3588 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3589 3590 rtl_ephy_init(tp, e_info_8402); 3591 3592 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3593 rtl_reset_packet_filter(tp); 3594 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3595 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3596 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 3597 3598 /* disable EEE */ 3599 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3600 3601 rtl_pcie_state_l2l3_disable(tp); 3602 } 3603 3604 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3605 { 3606 rtl_hw_aspm_clkreq_enable(tp, false); 3607 3608 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3609 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3610 3611 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3612 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3613 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3614 3615 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3616 3617 /* disable EEE */ 3618 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3619 3620 rtl_pcie_state_l2l3_disable(tp); 3621 rtl_hw_aspm_clkreq_enable(tp, true); 3622 } 3623 3624 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3625 { 3626 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3627 } 3628 3629 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3630 { 3631 rtl_pcie_state_l2l3_disable(tp); 3632 3633 RTL_W16(tp, 0x382, 0x221b); 3634 RTL_W8(tp, 0x4500, 0); 3635 RTL_W16(tp, 0x4800, 0); 3636 3637 /* disable UPS */ 3638 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3639 3640 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3641 3642 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3643 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3644 3645 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3646 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3647 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3648 3649 /* disable new tx descriptor format */ 3650 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3651 3652 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3653 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3654 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3655 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3656 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3657 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3658 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3659 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3660 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 3661 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3662 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3663 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 3664 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3665 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3666 udelay(1); 3667 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3668 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3669 3670 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3671 3672 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3673 3674 rtl8125_config_eee_mac(tp); 3675 3676 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3677 udelay(10); 3678 } 3679 3680 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 3681 { 3682 static const struct ephy_info e_info_8125_1[] = { 3683 { 0x01, 0xffff, 0xa812 }, 3684 { 0x09, 0xffff, 0x520c }, 3685 { 0x04, 0xffff, 0xd000 }, 3686 { 0x0d, 0xffff, 0xf702 }, 3687 { 0x0a, 0xffff, 0x8653 }, 3688 { 0x06, 0xffff, 0x001e }, 3689 { 0x08, 0xffff, 0x3595 }, 3690 { 0x20, 0xffff, 0x9455 }, 3691 { 0x21, 0xffff, 0x99ff }, 3692 { 0x02, 0xffff, 0x6046 }, 3693 { 0x29, 0xffff, 0xfe00 }, 3694 { 0x23, 0xffff, 0xab62 }, 3695 3696 { 0x41, 0xffff, 0xa80c }, 3697 { 0x49, 0xffff, 0x520c }, 3698 { 0x44, 0xffff, 0xd000 }, 3699 { 0x4d, 0xffff, 0xf702 }, 3700 { 0x4a, 0xffff, 0x8653 }, 3701 { 0x46, 0xffff, 0x001e }, 3702 { 0x48, 0xffff, 0x3595 }, 3703 { 0x60, 0xffff, 0x9455 }, 3704 { 0x61, 0xffff, 0x99ff }, 3705 { 0x42, 0xffff, 0x6046 }, 3706 { 0x69, 0xffff, 0xfe00 }, 3707 { 0x63, 0xffff, 0xab62 }, 3708 }; 3709 3710 rtl_set_def_aspm_entry_latency(tp); 3711 3712 /* disable aspm and clock request before access ephy */ 3713 rtl_hw_aspm_clkreq_enable(tp, false); 3714 rtl_ephy_init(tp, e_info_8125_1); 3715 3716 rtl_hw_start_8125_common(tp); 3717 } 3718 3719 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 3720 { 3721 static const struct ephy_info e_info_8125_2[] = { 3722 { 0x04, 0xffff, 0xd000 }, 3723 { 0x0a, 0xffff, 0x8653 }, 3724 { 0x23, 0xffff, 0xab66 }, 3725 { 0x20, 0xffff, 0x9455 }, 3726 { 0x21, 0xffff, 0x99ff }, 3727 { 0x29, 0xffff, 0xfe04 }, 3728 3729 { 0x44, 0xffff, 0xd000 }, 3730 { 0x4a, 0xffff, 0x8653 }, 3731 { 0x63, 0xffff, 0xab66 }, 3732 { 0x60, 0xffff, 0x9455 }, 3733 { 0x61, 0xffff, 0x99ff }, 3734 { 0x69, 0xffff, 0xfe04 }, 3735 }; 3736 3737 rtl_set_def_aspm_entry_latency(tp); 3738 3739 /* disable aspm and clock request before access ephy */ 3740 rtl_hw_aspm_clkreq_enable(tp, false); 3741 rtl_ephy_init(tp, e_info_8125_2); 3742 3743 rtl_hw_start_8125_common(tp); 3744 } 3745 3746 static void rtl_hw_config(struct rtl8169_private *tp) 3747 { 3748 static const rtl_generic_fct hw_configs[] = { 3749 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3750 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3751 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3752 [RTL_GIGA_MAC_VER_10] = NULL, 3753 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3754 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3755 [RTL_GIGA_MAC_VER_13] = NULL, 3756 [RTL_GIGA_MAC_VER_14] = NULL, 3757 [RTL_GIGA_MAC_VER_15] = NULL, 3758 [RTL_GIGA_MAC_VER_16] = NULL, 3759 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3760 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3761 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3762 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3763 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3764 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3765 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3766 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3767 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3768 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3769 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3770 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3771 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3772 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3773 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3774 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3775 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3776 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3777 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3778 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3779 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3780 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3781 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3782 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3783 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3784 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3785 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3786 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3787 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3788 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3789 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3790 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3791 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3792 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3793 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3794 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3795 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 3796 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 3797 }; 3798 3799 if (hw_configs[tp->mac_version]) 3800 hw_configs[tp->mac_version](tp); 3801 } 3802 3803 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3804 { 3805 int i; 3806 3807 /* disable interrupt coalescing */ 3808 for (i = 0xa00; i < 0xb00; i += 4) 3809 RTL_W32(tp, i, 0); 3810 3811 rtl_hw_config(tp); 3812 } 3813 3814 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3815 { 3816 if (rtl_is_8168evl_up(tp)) 3817 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3818 else 3819 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3820 3821 rtl_hw_config(tp); 3822 3823 /* disable interrupt coalescing */ 3824 RTL_W16(tp, IntrMitigate, 0x0000); 3825 } 3826 3827 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3828 { 3829 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3830 3831 tp->cp_cmd |= PCIMulRW; 3832 3833 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3834 tp->mac_version == RTL_GIGA_MAC_VER_03) 3835 tp->cp_cmd |= EnAnaPLL; 3836 3837 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3838 3839 rtl8169_set_magic_reg(tp, tp->mac_version); 3840 3841 /* disable interrupt coalescing */ 3842 RTL_W16(tp, IntrMitigate, 0x0000); 3843 } 3844 3845 static void rtl_hw_start(struct rtl8169_private *tp) 3846 { 3847 rtl_unlock_config_regs(tp); 3848 3849 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3850 3851 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3852 rtl_hw_start_8169(tp); 3853 else if (rtl_is_8125(tp)) 3854 rtl_hw_start_8125(tp); 3855 else 3856 rtl_hw_start_8168(tp); 3857 3858 rtl_set_rx_max_size(tp); 3859 rtl_set_rx_tx_desc_registers(tp); 3860 rtl_lock_config_regs(tp); 3861 3862 rtl_jumbo_config(tp); 3863 3864 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3865 rtl_pci_commit(tp); 3866 3867 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3868 rtl_init_rxcfg(tp); 3869 rtl_set_tx_config_registers(tp); 3870 rtl_set_rx_config_features(tp, tp->dev->features); 3871 rtl_set_rx_mode(tp->dev); 3872 rtl_irq_enable(tp); 3873 } 3874 3875 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3876 { 3877 struct rtl8169_private *tp = netdev_priv(dev); 3878 3879 dev->mtu = new_mtu; 3880 netdev_update_features(dev); 3881 rtl_jumbo_config(tp); 3882 3883 return 0; 3884 } 3885 3886 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 3887 { 3888 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3889 3890 desc->opts2 = 0; 3891 /* Force memory writes to complete before releasing descriptor */ 3892 dma_wmb(); 3893 3894 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 3895 } 3896 3897 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3898 struct RxDesc *desc) 3899 { 3900 struct device *d = tp_to_dev(tp); 3901 int node = dev_to_node(d); 3902 dma_addr_t mapping; 3903 struct page *data; 3904 3905 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3906 if (!data) 3907 return NULL; 3908 3909 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3910 if (unlikely(dma_mapping_error(d, mapping))) { 3911 if (net_ratelimit()) 3912 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); 3913 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3914 return NULL; 3915 } 3916 3917 desc->addr = cpu_to_le64(mapping); 3918 rtl8169_mark_to_asic(desc); 3919 3920 return data; 3921 } 3922 3923 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3924 { 3925 unsigned int i; 3926 3927 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3928 dma_unmap_page(tp_to_dev(tp), 3929 le64_to_cpu(tp->RxDescArray[i].addr), 3930 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3931 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3932 tp->Rx_databuff[i] = NULL; 3933 tp->RxDescArray[i].addr = 0; 3934 tp->RxDescArray[i].opts1 = 0; 3935 } 3936 } 3937 3938 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3939 { 3940 unsigned int i; 3941 3942 for (i = 0; i < NUM_RX_DESC; i++) { 3943 struct page *data; 3944 3945 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3946 if (!data) { 3947 rtl8169_rx_clear(tp); 3948 return -ENOMEM; 3949 } 3950 tp->Rx_databuff[i] = data; 3951 } 3952 3953 /* mark as last descriptor in the ring */ 3954 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3955 3956 return 0; 3957 } 3958 3959 static int rtl8169_init_ring(struct rtl8169_private *tp) 3960 { 3961 rtl8169_init_ring_indexes(tp); 3962 3963 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3964 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3965 3966 return rtl8169_rx_fill(tp); 3967 } 3968 3969 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3970 { 3971 struct ring_info *tx_skb = tp->tx_skb + entry; 3972 struct TxDesc *desc = tp->TxDescArray + entry; 3973 3974 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3975 DMA_TO_DEVICE); 3976 memset(desc, 0, sizeof(*desc)); 3977 memset(tx_skb, 0, sizeof(*tx_skb)); 3978 } 3979 3980 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3981 unsigned int n) 3982 { 3983 unsigned int i; 3984 3985 for (i = 0; i < n; i++) { 3986 unsigned int entry = (start + i) % NUM_TX_DESC; 3987 struct ring_info *tx_skb = tp->tx_skb + entry; 3988 unsigned int len = tx_skb->len; 3989 3990 if (len) { 3991 struct sk_buff *skb = tx_skb->skb; 3992 3993 rtl8169_unmap_tx_skb(tp, entry); 3994 if (skb) 3995 dev_consume_skb_any(skb); 3996 } 3997 } 3998 } 3999 4000 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4001 { 4002 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4003 tp->cur_tx = tp->dirty_tx = 0; 4004 netdev_reset_queue(tp->dev); 4005 } 4006 4007 static void rtl_reset_work(struct rtl8169_private *tp) 4008 { 4009 struct net_device *dev = tp->dev; 4010 int i; 4011 4012 napi_disable(&tp->napi); 4013 netif_stop_queue(dev); 4014 synchronize_rcu(); 4015 4016 rtl8169_hw_reset(tp); 4017 4018 for (i = 0; i < NUM_RX_DESC; i++) 4019 rtl8169_mark_to_asic(tp->RxDescArray + i); 4020 4021 rtl8169_tx_clear(tp); 4022 rtl8169_init_ring_indexes(tp); 4023 4024 napi_enable(&tp->napi); 4025 rtl_hw_start(tp); 4026 netif_wake_queue(dev); 4027 } 4028 4029 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4030 { 4031 struct rtl8169_private *tp = netdev_priv(dev); 4032 4033 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4034 } 4035 4036 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4037 void *addr, unsigned int entry, bool desc_own) 4038 { 4039 struct TxDesc *txd = tp->TxDescArray + entry; 4040 struct device *d = tp_to_dev(tp); 4041 dma_addr_t mapping; 4042 u32 opts1; 4043 int ret; 4044 4045 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4046 ret = dma_mapping_error(d, mapping); 4047 if (unlikely(ret)) { 4048 if (net_ratelimit()) 4049 netif_err(tp, drv, tp->dev, "Failed to map TX data!\n"); 4050 return ret; 4051 } 4052 4053 txd->addr = cpu_to_le64(mapping); 4054 txd->opts2 = cpu_to_le32(opts[1]); 4055 4056 opts1 = opts[0] | len; 4057 if (entry == NUM_TX_DESC - 1) 4058 opts1 |= RingEnd; 4059 if (desc_own) 4060 opts1 |= DescOwn; 4061 txd->opts1 = cpu_to_le32(opts1); 4062 4063 tp->tx_skb[entry].len = len; 4064 4065 return 0; 4066 } 4067 4068 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4069 const u32 *opts, unsigned int entry) 4070 { 4071 struct skb_shared_info *info = skb_shinfo(skb); 4072 unsigned int cur_frag; 4073 4074 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4075 const skb_frag_t *frag = info->frags + cur_frag; 4076 void *addr = skb_frag_address(frag); 4077 u32 len = skb_frag_size(frag); 4078 4079 entry = (entry + 1) % NUM_TX_DESC; 4080 4081 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4082 goto err_out; 4083 } 4084 4085 return 0; 4086 4087 err_out: 4088 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4089 return -EIO; 4090 } 4091 4092 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 4093 { 4094 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 4095 } 4096 4097 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4098 { 4099 u32 mss = skb_shinfo(skb)->gso_size; 4100 4101 if (mss) { 4102 opts[0] |= TD_LSO; 4103 opts[0] |= mss << TD0_MSS_SHIFT; 4104 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4105 const struct iphdr *ip = ip_hdr(skb); 4106 4107 if (ip->protocol == IPPROTO_TCP) 4108 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4109 else if (ip->protocol == IPPROTO_UDP) 4110 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4111 else 4112 WARN_ON_ONCE(1); 4113 } 4114 } 4115 4116 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4117 struct sk_buff *skb, u32 *opts) 4118 { 4119 u32 transport_offset = (u32)skb_transport_offset(skb); 4120 struct skb_shared_info *shinfo = skb_shinfo(skb); 4121 u32 mss = shinfo->gso_size; 4122 4123 if (mss) { 4124 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4125 opts[0] |= TD1_GTSENV4; 4126 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4127 if (skb_cow_head(skb, 0)) 4128 return false; 4129 4130 tcp_v6_gso_csum_prep(skb); 4131 opts[0] |= TD1_GTSENV6; 4132 } else { 4133 WARN_ON_ONCE(1); 4134 } 4135 4136 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4137 opts[1] |= mss << TD1_MSS_SHIFT; 4138 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4139 u8 ip_protocol; 4140 4141 switch (vlan_get_protocol(skb)) { 4142 case htons(ETH_P_IP): 4143 opts[1] |= TD1_IPv4_CS; 4144 ip_protocol = ip_hdr(skb)->protocol; 4145 break; 4146 4147 case htons(ETH_P_IPV6): 4148 opts[1] |= TD1_IPv6_CS; 4149 ip_protocol = ipv6_hdr(skb)->nexthdr; 4150 break; 4151 4152 default: 4153 ip_protocol = IPPROTO_RAW; 4154 break; 4155 } 4156 4157 if (ip_protocol == IPPROTO_TCP) 4158 opts[1] |= TD1_TCP_CS; 4159 else if (ip_protocol == IPPROTO_UDP) 4160 opts[1] |= TD1_UDP_CS; 4161 else 4162 WARN_ON_ONCE(1); 4163 4164 opts[1] |= transport_offset << TCPHO_SHIFT; 4165 } else { 4166 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 4167 return !eth_skb_pad(skb); 4168 } 4169 4170 return true; 4171 } 4172 4173 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 4174 unsigned int nr_frags) 4175 { 4176 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 4177 4178 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4179 return slots_avail > nr_frags; 4180 } 4181 4182 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4183 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4184 { 4185 switch (tp->mac_version) { 4186 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4187 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4188 return false; 4189 default: 4190 return true; 4191 } 4192 } 4193 4194 static void rtl8169_doorbell(struct rtl8169_private *tp) 4195 { 4196 if (rtl_is_8125(tp)) 4197 RTL_W16(tp, TxPoll_8125, BIT(0)); 4198 else 4199 RTL_W8(tp, TxPoll, NPQ); 4200 } 4201 4202 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4203 struct net_device *dev) 4204 { 4205 unsigned int frags = skb_shinfo(skb)->nr_frags; 4206 struct rtl8169_private *tp = netdev_priv(dev); 4207 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4208 struct TxDesc *txd_first, *txd_last; 4209 bool stop_queue, door_bell; 4210 u32 opts[2]; 4211 4212 txd_first = tp->TxDescArray + entry; 4213 4214 if (unlikely(!rtl_tx_slots_avail(tp, frags))) { 4215 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 4216 goto err_stop_0; 4217 } 4218 4219 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn)) 4220 goto err_stop_0; 4221 4222 opts[1] = rtl8169_tx_vlan_tag(skb); 4223 opts[0] = 0; 4224 4225 if (!rtl_chip_supports_csum_v2(tp)) 4226 rtl8169_tso_csum_v1(skb, opts); 4227 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4228 goto err_dma_0; 4229 4230 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4231 entry, false))) 4232 goto err_dma_0; 4233 4234 if (frags) { 4235 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4236 goto err_dma_1; 4237 entry = (entry + frags) % NUM_TX_DESC; 4238 } 4239 4240 txd_last = tp->TxDescArray + entry; 4241 txd_last->opts1 |= cpu_to_le32(LastFrag); 4242 tp->tx_skb[entry].skb = skb; 4243 4244 skb_tx_timestamp(skb); 4245 4246 /* Force memory writes to complete before releasing descriptor */ 4247 dma_wmb(); 4248 4249 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4250 4251 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4252 4253 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4254 smp_wmb(); 4255 4256 tp->cur_tx += frags + 1; 4257 4258 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 4259 if (unlikely(stop_queue)) { 4260 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4261 * not miss a ring update when it notices a stopped queue. 4262 */ 4263 smp_wmb(); 4264 netif_stop_queue(dev); 4265 door_bell = true; 4266 } 4267 4268 if (door_bell) 4269 rtl8169_doorbell(tp); 4270 4271 if (unlikely(stop_queue)) { 4272 /* Sync with rtl_tx: 4273 * - publish queue status and cur_tx ring index (write barrier) 4274 * - refresh dirty_tx ring index (read barrier). 4275 * May the current thread have a pessimistic view of the ring 4276 * status and forget to wake up queue, a racing rtl_tx thread 4277 * can't. 4278 */ 4279 smp_mb(); 4280 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 4281 netif_start_queue(dev); 4282 } 4283 4284 return NETDEV_TX_OK; 4285 4286 err_dma_1: 4287 rtl8169_unmap_tx_skb(tp, entry); 4288 err_dma_0: 4289 dev_kfree_skb_any(skb); 4290 dev->stats.tx_dropped++; 4291 return NETDEV_TX_OK; 4292 4293 err_stop_0: 4294 netif_stop_queue(dev); 4295 dev->stats.tx_dropped++; 4296 return NETDEV_TX_BUSY; 4297 } 4298 4299 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4300 { 4301 struct skb_shared_info *info = skb_shinfo(skb); 4302 unsigned int nr_frags = info->nr_frags; 4303 4304 if (!nr_frags) 4305 return UINT_MAX; 4306 4307 return skb_frag_size(info->frags + nr_frags - 1); 4308 } 4309 4310 /* Workaround for hw issues with TSO on RTL8168evl */ 4311 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4312 netdev_features_t features) 4313 { 4314 /* IPv4 header has options field */ 4315 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4316 ip_hdrlen(skb) > sizeof(struct iphdr)) 4317 features &= ~NETIF_F_ALL_TSO; 4318 4319 /* IPv4 TCP header has options field */ 4320 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4321 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4322 features &= ~NETIF_F_ALL_TSO; 4323 4324 else if (rtl_last_frag_len(skb) <= 6) 4325 features &= ~NETIF_F_ALL_TSO; 4326 4327 return features; 4328 } 4329 4330 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4331 struct net_device *dev, 4332 netdev_features_t features) 4333 { 4334 int transport_offset = skb_transport_offset(skb); 4335 struct rtl8169_private *tp = netdev_priv(dev); 4336 4337 if (skb_is_gso(skb)) { 4338 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4339 features = rtl8168evl_fix_tso(skb, features); 4340 4341 if (transport_offset > GTTCPHO_MAX && 4342 rtl_chip_supports_csum_v2(tp)) 4343 features &= ~NETIF_F_ALL_TSO; 4344 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4345 if (skb->len < ETH_ZLEN) { 4346 switch (tp->mac_version) { 4347 case RTL_GIGA_MAC_VER_11: 4348 case RTL_GIGA_MAC_VER_12: 4349 case RTL_GIGA_MAC_VER_17: 4350 case RTL_GIGA_MAC_VER_34: 4351 features &= ~NETIF_F_CSUM_MASK; 4352 break; 4353 default: 4354 break; 4355 } 4356 } 4357 4358 if (transport_offset > TCPHO_MAX && 4359 rtl_chip_supports_csum_v2(tp)) 4360 features &= ~NETIF_F_CSUM_MASK; 4361 } 4362 4363 return vlan_features_check(skb, features); 4364 } 4365 4366 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4367 { 4368 struct rtl8169_private *tp = netdev_priv(dev); 4369 struct pci_dev *pdev = tp->pci_dev; 4370 int pci_status_errs; 4371 u16 pci_cmd; 4372 4373 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4374 4375 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4376 4377 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4378 pci_cmd, pci_status_errs); 4379 4380 /* 4381 * The recovery sequence below admits a very elaborated explanation: 4382 * - it seems to work; 4383 * - I did not see what else could be done; 4384 * - it makes iop3xx happy. 4385 * 4386 * Feel free to adjust to your needs. 4387 */ 4388 if (pdev->broken_parity_status) 4389 pci_cmd &= ~PCI_COMMAND_PARITY; 4390 else 4391 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4392 4393 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4394 4395 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4396 } 4397 4398 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4399 int budget) 4400 { 4401 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 4402 4403 dirty_tx = tp->dirty_tx; 4404 smp_rmb(); 4405 4406 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) { 4407 unsigned int entry = dirty_tx % NUM_TX_DESC; 4408 struct sk_buff *skb = tp->tx_skb[entry].skb; 4409 u32 status; 4410 4411 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4412 if (status & DescOwn) 4413 break; 4414 4415 rtl8169_unmap_tx_skb(tp, entry); 4416 4417 if (skb) { 4418 pkts_compl++; 4419 bytes_compl += skb->len; 4420 napi_consume_skb(skb, budget); 4421 } 4422 dirty_tx++; 4423 } 4424 4425 if (tp->dirty_tx != dirty_tx) { 4426 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4427 4428 u64_stats_update_begin(&tp->tx_stats.syncp); 4429 tp->tx_stats.packets += pkts_compl; 4430 tp->tx_stats.bytes += bytes_compl; 4431 u64_stats_update_end(&tp->tx_stats.syncp); 4432 4433 tp->dirty_tx = dirty_tx; 4434 /* Sync with rtl8169_start_xmit: 4435 * - publish dirty_tx ring index (write barrier) 4436 * - refresh cur_tx ring index and queue status (read barrier) 4437 * May the current thread miss the stopped queue condition, 4438 * a racing xmit thread can only have a right view of the 4439 * ring status. 4440 */ 4441 smp_mb(); 4442 if (netif_queue_stopped(dev) && 4443 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 4444 netif_wake_queue(dev); 4445 } 4446 /* 4447 * 8168 hack: TxPoll requests are lost when the Tx packets are 4448 * too close. Let's kick an extra TxPoll request when a burst 4449 * of start_xmit activity is detected (if it is not detected, 4450 * it is slow enough). -- FR 4451 */ 4452 if (tp->cur_tx != dirty_tx) 4453 rtl8169_doorbell(tp); 4454 } 4455 } 4456 4457 static inline int rtl8169_fragmented_frame(u32 status) 4458 { 4459 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4460 } 4461 4462 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4463 { 4464 u32 status = opts1 & RxProtoMask; 4465 4466 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4467 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 4468 skb->ip_summed = CHECKSUM_UNNECESSARY; 4469 else 4470 skb_checksum_none_assert(skb); 4471 } 4472 4473 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 4474 { 4475 unsigned int cur_rx, rx_left; 4476 unsigned int count; 4477 4478 cur_rx = tp->cur_rx; 4479 4480 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 4481 unsigned int entry = cur_rx % NUM_RX_DESC; 4482 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 4483 struct RxDesc *desc = tp->RxDescArray + entry; 4484 u32 status; 4485 4486 status = le32_to_cpu(desc->opts1); 4487 if (status & DescOwn) 4488 break; 4489 4490 /* This barrier is needed to keep us from reading 4491 * any other fields out of the Rx descriptor until 4492 * we know the status of DescOwn 4493 */ 4494 dma_rmb(); 4495 4496 if (unlikely(status & RxRES)) { 4497 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", 4498 status); 4499 dev->stats.rx_errors++; 4500 if (status & (RxRWT | RxRUNT)) 4501 dev->stats.rx_length_errors++; 4502 if (status & RxCRC) 4503 dev->stats.rx_crc_errors++; 4504 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 4505 dev->features & NETIF_F_RXALL) { 4506 goto process_pkt; 4507 } 4508 } else { 4509 unsigned int pkt_size; 4510 struct sk_buff *skb; 4511 4512 process_pkt: 4513 pkt_size = status & GENMASK(13, 0); 4514 if (likely(!(dev->features & NETIF_F_RXFCS))) 4515 pkt_size -= ETH_FCS_LEN; 4516 /* 4517 * The driver does not support incoming fragmented 4518 * frames. They are seen as a symptom of over-mtu 4519 * sized frames. 4520 */ 4521 if (unlikely(rtl8169_fragmented_frame(status))) { 4522 dev->stats.rx_dropped++; 4523 dev->stats.rx_length_errors++; 4524 goto release_descriptor; 4525 } 4526 4527 skb = napi_alloc_skb(&tp->napi, pkt_size); 4528 if (unlikely(!skb)) { 4529 dev->stats.rx_dropped++; 4530 goto release_descriptor; 4531 } 4532 4533 dma_sync_single_for_cpu(tp_to_dev(tp), 4534 le64_to_cpu(desc->addr), 4535 pkt_size, DMA_FROM_DEVICE); 4536 prefetch(rx_buf); 4537 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4538 skb->tail += pkt_size; 4539 skb->len = pkt_size; 4540 4541 dma_sync_single_for_device(tp_to_dev(tp), 4542 le64_to_cpu(desc->addr), 4543 pkt_size, DMA_FROM_DEVICE); 4544 4545 rtl8169_rx_csum(skb, status); 4546 skb->protocol = eth_type_trans(skb, dev); 4547 4548 rtl8169_rx_vlan_tag(desc, skb); 4549 4550 if (skb->pkt_type == PACKET_MULTICAST) 4551 dev->stats.multicast++; 4552 4553 napi_gro_receive(&tp->napi, skb); 4554 4555 u64_stats_update_begin(&tp->rx_stats.syncp); 4556 tp->rx_stats.packets++; 4557 tp->rx_stats.bytes += pkt_size; 4558 u64_stats_update_end(&tp->rx_stats.syncp); 4559 } 4560 release_descriptor: 4561 rtl8169_mark_to_asic(desc); 4562 } 4563 4564 count = cur_rx - tp->cur_rx; 4565 tp->cur_rx = cur_rx; 4566 4567 return count; 4568 } 4569 4570 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4571 { 4572 struct rtl8169_private *tp = dev_instance; 4573 u32 status = rtl_get_events(tp); 4574 4575 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 4576 !(status & tp->irq_mask)) 4577 return IRQ_NONE; 4578 4579 if (unlikely(status & SYSErr)) { 4580 rtl8169_pcierr_interrupt(tp->dev); 4581 goto out; 4582 } 4583 4584 if (status & LinkChg) 4585 phy_mac_interrupt(tp->phydev); 4586 4587 if (unlikely(status & RxFIFOOver && 4588 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4589 netif_stop_queue(tp->dev); 4590 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4591 } 4592 4593 rtl_irq_disable(tp); 4594 napi_schedule_irqoff(&tp->napi); 4595 out: 4596 rtl_ack_events(tp, status); 4597 4598 return IRQ_HANDLED; 4599 } 4600 4601 static void rtl_task(struct work_struct *work) 4602 { 4603 struct rtl8169_private *tp = 4604 container_of(work, struct rtl8169_private, wk.work); 4605 4606 rtl_lock_work(tp); 4607 4608 if (!netif_running(tp->dev) || 4609 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4610 goto out_unlock; 4611 4612 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) 4613 rtl_reset_work(tp); 4614 out_unlock: 4615 rtl_unlock_work(tp); 4616 } 4617 4618 static int rtl8169_poll(struct napi_struct *napi, int budget) 4619 { 4620 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4621 struct net_device *dev = tp->dev; 4622 int work_done; 4623 4624 work_done = rtl_rx(dev, tp, (u32) budget); 4625 4626 rtl_tx(dev, tp, budget); 4627 4628 if (work_done < budget) { 4629 napi_complete_done(napi, work_done); 4630 rtl_irq_enable(tp); 4631 } 4632 4633 return work_done; 4634 } 4635 4636 static void r8169_phylink_handler(struct net_device *ndev) 4637 { 4638 struct rtl8169_private *tp = netdev_priv(ndev); 4639 4640 if (netif_carrier_ok(ndev)) { 4641 rtl_link_chg_patch(tp); 4642 pm_request_resume(&tp->pci_dev->dev); 4643 } else { 4644 pm_runtime_idle(&tp->pci_dev->dev); 4645 } 4646 4647 if (net_ratelimit()) 4648 phy_print_status(tp->phydev); 4649 } 4650 4651 static int r8169_phy_connect(struct rtl8169_private *tp) 4652 { 4653 struct phy_device *phydev = tp->phydev; 4654 phy_interface_t phy_mode; 4655 int ret; 4656 4657 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4658 PHY_INTERFACE_MODE_MII; 4659 4660 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4661 phy_mode); 4662 if (ret) 4663 return ret; 4664 4665 if (!tp->supports_gmii) 4666 phy_set_max_speed(phydev, SPEED_100); 4667 4668 phy_support_asym_pause(phydev); 4669 4670 phy_attached_info(phydev); 4671 4672 return 0; 4673 } 4674 4675 static void rtl8169_down(struct net_device *dev) 4676 { 4677 struct rtl8169_private *tp = netdev_priv(dev); 4678 4679 phy_stop(tp->phydev); 4680 4681 napi_disable(&tp->napi); 4682 netif_stop_queue(dev); 4683 4684 rtl8169_hw_reset(tp); 4685 4686 /* Give a racing hard_start_xmit a few cycles to complete. */ 4687 synchronize_rcu(); 4688 4689 rtl8169_tx_clear(tp); 4690 4691 rtl8169_rx_clear(tp); 4692 4693 rtl_pll_power_down(tp); 4694 } 4695 4696 static int rtl8169_close(struct net_device *dev) 4697 { 4698 struct rtl8169_private *tp = netdev_priv(dev); 4699 struct pci_dev *pdev = tp->pci_dev; 4700 4701 pm_runtime_get_sync(&pdev->dev); 4702 4703 /* Update counters before going down */ 4704 rtl8169_update_counters(tp); 4705 4706 rtl_lock_work(tp); 4707 /* Clear all task flags */ 4708 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4709 4710 rtl8169_down(dev); 4711 rtl_unlock_work(tp); 4712 4713 cancel_work_sync(&tp->wk.work); 4714 4715 phy_disconnect(tp->phydev); 4716 4717 pci_free_irq(pdev, 0, tp); 4718 4719 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4720 tp->RxPhyAddr); 4721 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4722 tp->TxPhyAddr); 4723 tp->TxDescArray = NULL; 4724 tp->RxDescArray = NULL; 4725 4726 pm_runtime_put_sync(&pdev->dev); 4727 4728 return 0; 4729 } 4730 4731 #ifdef CONFIG_NET_POLL_CONTROLLER 4732 static void rtl8169_netpoll(struct net_device *dev) 4733 { 4734 struct rtl8169_private *tp = netdev_priv(dev); 4735 4736 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4737 } 4738 #endif 4739 4740 static int rtl_open(struct net_device *dev) 4741 { 4742 struct rtl8169_private *tp = netdev_priv(dev); 4743 struct pci_dev *pdev = tp->pci_dev; 4744 int retval = -ENOMEM; 4745 4746 pm_runtime_get_sync(&pdev->dev); 4747 4748 /* 4749 * Rx and Tx descriptors needs 256 bytes alignment. 4750 * dma_alloc_coherent provides more. 4751 */ 4752 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4753 &tp->TxPhyAddr, GFP_KERNEL); 4754 if (!tp->TxDescArray) 4755 goto err_pm_runtime_put; 4756 4757 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4758 &tp->RxPhyAddr, GFP_KERNEL); 4759 if (!tp->RxDescArray) 4760 goto err_free_tx_0; 4761 4762 retval = rtl8169_init_ring(tp); 4763 if (retval < 0) 4764 goto err_free_rx_1; 4765 4766 rtl_request_firmware(tp); 4767 4768 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 4769 dev->name); 4770 if (retval < 0) 4771 goto err_release_fw_2; 4772 4773 retval = r8169_phy_connect(tp); 4774 if (retval) 4775 goto err_free_irq; 4776 4777 rtl_lock_work(tp); 4778 4779 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4780 4781 napi_enable(&tp->napi); 4782 4783 rtl8169_init_phy(tp); 4784 4785 rtl_pll_power_up(tp); 4786 4787 rtl_hw_start(tp); 4788 4789 if (!rtl8169_init_counter_offsets(tp)) 4790 netif_warn(tp, hw, dev, "counter reset/update failed\n"); 4791 4792 phy_start(tp->phydev); 4793 netif_start_queue(dev); 4794 4795 rtl_unlock_work(tp); 4796 4797 pm_runtime_put_sync(&pdev->dev); 4798 out: 4799 return retval; 4800 4801 err_free_irq: 4802 pci_free_irq(pdev, 0, tp); 4803 err_release_fw_2: 4804 rtl_release_firmware(tp); 4805 rtl8169_rx_clear(tp); 4806 err_free_rx_1: 4807 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4808 tp->RxPhyAddr); 4809 tp->RxDescArray = NULL; 4810 err_free_tx_0: 4811 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4812 tp->TxPhyAddr); 4813 tp->TxDescArray = NULL; 4814 err_pm_runtime_put: 4815 pm_runtime_put_noidle(&pdev->dev); 4816 goto out; 4817 } 4818 4819 static void 4820 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4821 { 4822 struct rtl8169_private *tp = netdev_priv(dev); 4823 struct pci_dev *pdev = tp->pci_dev; 4824 struct rtl8169_counters *counters = tp->counters; 4825 unsigned int start; 4826 4827 pm_runtime_get_noresume(&pdev->dev); 4828 4829 netdev_stats_to_stats64(stats, &dev->stats); 4830 4831 do { 4832 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 4833 stats->rx_packets = tp->rx_stats.packets; 4834 stats->rx_bytes = tp->rx_stats.bytes; 4835 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 4836 4837 do { 4838 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 4839 stats->tx_packets = tp->tx_stats.packets; 4840 stats->tx_bytes = tp->tx_stats.bytes; 4841 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 4842 4843 /* 4844 * Fetch additional counter values missing in stats collected by driver 4845 * from tally counters. 4846 */ 4847 if (pm_runtime_active(&pdev->dev)) 4848 rtl8169_update_counters(tp); 4849 4850 /* 4851 * Subtract values fetched during initalization. 4852 * See rtl8169_init_counter_offsets for a description why we do that. 4853 */ 4854 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4855 le64_to_cpu(tp->tc_offset.tx_errors); 4856 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4857 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4858 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4859 le16_to_cpu(tp->tc_offset.tx_aborted); 4860 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4861 le16_to_cpu(tp->tc_offset.rx_missed); 4862 4863 pm_runtime_put_noidle(&pdev->dev); 4864 } 4865 4866 static void rtl8169_net_suspend(struct net_device *dev) 4867 { 4868 struct rtl8169_private *tp = netdev_priv(dev); 4869 4870 if (!netif_running(dev)) 4871 return; 4872 4873 phy_stop(tp->phydev); 4874 netif_device_detach(dev); 4875 4876 rtl_lock_work(tp); 4877 napi_disable(&tp->napi); 4878 /* Clear all task flags */ 4879 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4880 4881 rtl_unlock_work(tp); 4882 4883 rtl_pll_power_down(tp); 4884 } 4885 4886 #ifdef CONFIG_PM 4887 4888 static int rtl8169_suspend(struct device *device) 4889 { 4890 struct net_device *dev = dev_get_drvdata(device); 4891 struct rtl8169_private *tp = netdev_priv(dev); 4892 4893 rtl8169_net_suspend(dev); 4894 clk_disable_unprepare(tp->clk); 4895 4896 return 0; 4897 } 4898 4899 static void __rtl8169_resume(struct net_device *dev) 4900 { 4901 struct rtl8169_private *tp = netdev_priv(dev); 4902 4903 netif_device_attach(dev); 4904 4905 rtl_pll_power_up(tp); 4906 rtl8169_init_phy(tp); 4907 4908 phy_start(tp->phydev); 4909 4910 rtl_lock_work(tp); 4911 napi_enable(&tp->napi); 4912 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4913 rtl_reset_work(tp); 4914 rtl_unlock_work(tp); 4915 } 4916 4917 static int rtl8169_resume(struct device *device) 4918 { 4919 struct net_device *dev = dev_get_drvdata(device); 4920 struct rtl8169_private *tp = netdev_priv(dev); 4921 4922 rtl_rar_set(tp, dev->dev_addr); 4923 4924 clk_prepare_enable(tp->clk); 4925 4926 if (netif_running(dev)) 4927 __rtl8169_resume(dev); 4928 4929 return 0; 4930 } 4931 4932 static int rtl8169_runtime_suspend(struct device *device) 4933 { 4934 struct net_device *dev = dev_get_drvdata(device); 4935 struct rtl8169_private *tp = netdev_priv(dev); 4936 4937 if (!tp->TxDescArray) 4938 return 0; 4939 4940 rtl_lock_work(tp); 4941 __rtl8169_set_wol(tp, WAKE_ANY); 4942 rtl_unlock_work(tp); 4943 4944 rtl8169_net_suspend(dev); 4945 4946 /* Update counters before going runtime suspend */ 4947 rtl8169_update_counters(tp); 4948 4949 return 0; 4950 } 4951 4952 static int rtl8169_runtime_resume(struct device *device) 4953 { 4954 struct net_device *dev = dev_get_drvdata(device); 4955 struct rtl8169_private *tp = netdev_priv(dev); 4956 4957 rtl_rar_set(tp, dev->dev_addr); 4958 4959 if (!tp->TxDescArray) 4960 return 0; 4961 4962 rtl_lock_work(tp); 4963 __rtl8169_set_wol(tp, tp->saved_wolopts); 4964 rtl_unlock_work(tp); 4965 4966 __rtl8169_resume(dev); 4967 4968 return 0; 4969 } 4970 4971 static int rtl8169_runtime_idle(struct device *device) 4972 { 4973 struct net_device *dev = dev_get_drvdata(device); 4974 4975 if (!netif_running(dev) || !netif_carrier_ok(dev)) 4976 pm_schedule_suspend(device, 10000); 4977 4978 return -EBUSY; 4979 } 4980 4981 static const struct dev_pm_ops rtl8169_pm_ops = { 4982 .suspend = rtl8169_suspend, 4983 .resume = rtl8169_resume, 4984 .freeze = rtl8169_suspend, 4985 .thaw = rtl8169_resume, 4986 .poweroff = rtl8169_suspend, 4987 .restore = rtl8169_resume, 4988 .runtime_suspend = rtl8169_runtime_suspend, 4989 .runtime_resume = rtl8169_runtime_resume, 4990 .runtime_idle = rtl8169_runtime_idle, 4991 }; 4992 4993 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 4994 4995 #else /* !CONFIG_PM */ 4996 4997 #define RTL8169_PM_OPS NULL 4998 4999 #endif /* !CONFIG_PM */ 5000 5001 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 5002 { 5003 /* WoL fails with 8168b when the receiver is disabled. */ 5004 switch (tp->mac_version) { 5005 case RTL_GIGA_MAC_VER_11: 5006 case RTL_GIGA_MAC_VER_12: 5007 case RTL_GIGA_MAC_VER_17: 5008 pci_clear_master(tp->pci_dev); 5009 5010 RTL_W8(tp, ChipCmd, CmdRxEnb); 5011 rtl_pci_commit(tp); 5012 break; 5013 default: 5014 break; 5015 } 5016 } 5017 5018 static void rtl_shutdown(struct pci_dev *pdev) 5019 { 5020 struct net_device *dev = pci_get_drvdata(pdev); 5021 struct rtl8169_private *tp = netdev_priv(dev); 5022 5023 rtl8169_net_suspend(dev); 5024 5025 /* Restore original MAC address */ 5026 rtl_rar_set(tp, dev->perm_addr); 5027 5028 rtl8169_hw_reset(tp); 5029 5030 if (system_state == SYSTEM_POWER_OFF) { 5031 if (tp->saved_wolopts) { 5032 rtl_wol_suspend_quirk(tp); 5033 rtl_wol_shutdown_quirk(tp); 5034 } 5035 5036 pci_wake_from_d3(pdev, true); 5037 pci_set_power_state(pdev, PCI_D3hot); 5038 } 5039 } 5040 5041 static void rtl_remove_one(struct pci_dev *pdev) 5042 { 5043 struct net_device *dev = pci_get_drvdata(pdev); 5044 struct rtl8169_private *tp = netdev_priv(dev); 5045 5046 if (r8168_check_dash(tp)) 5047 rtl8168_driver_stop(tp); 5048 5049 netif_napi_del(&tp->napi); 5050 5051 unregister_netdev(dev); 5052 mdiobus_unregister(tp->phydev->mdio.bus); 5053 5054 rtl_release_firmware(tp); 5055 5056 if (pci_dev_run_wake(pdev)) 5057 pm_runtime_get_noresume(&pdev->dev); 5058 5059 /* restore original MAC address */ 5060 rtl_rar_set(tp, dev->perm_addr); 5061 } 5062 5063 static const struct net_device_ops rtl_netdev_ops = { 5064 .ndo_open = rtl_open, 5065 .ndo_stop = rtl8169_close, 5066 .ndo_get_stats64 = rtl8169_get_stats64, 5067 .ndo_start_xmit = rtl8169_start_xmit, 5068 .ndo_features_check = rtl8169_features_check, 5069 .ndo_tx_timeout = rtl8169_tx_timeout, 5070 .ndo_validate_addr = eth_validate_addr, 5071 .ndo_change_mtu = rtl8169_change_mtu, 5072 .ndo_fix_features = rtl8169_fix_features, 5073 .ndo_set_features = rtl8169_set_features, 5074 .ndo_set_mac_address = rtl_set_mac_address, 5075 .ndo_do_ioctl = phy_do_ioctl_running, 5076 .ndo_set_rx_mode = rtl_set_rx_mode, 5077 #ifdef CONFIG_NET_POLL_CONTROLLER 5078 .ndo_poll_controller = rtl8169_netpoll, 5079 #endif 5080 5081 }; 5082 5083 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5084 { 5085 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5086 5087 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5088 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5089 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5090 /* special workaround needed */ 5091 tp->irq_mask |= RxFIFOOver; 5092 else 5093 tp->irq_mask |= RxOverflow; 5094 } 5095 5096 static int rtl_alloc_irq(struct rtl8169_private *tp) 5097 { 5098 unsigned int flags; 5099 5100 switch (tp->mac_version) { 5101 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5102 rtl_unlock_config_regs(tp); 5103 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5104 rtl_lock_config_regs(tp); 5105 /* fall through */ 5106 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5107 flags = PCI_IRQ_LEGACY; 5108 break; 5109 default: 5110 flags = PCI_IRQ_ALL_TYPES; 5111 break; 5112 } 5113 5114 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5115 } 5116 5117 static void rtl_read_mac_address(struct rtl8169_private *tp, 5118 u8 mac_addr[ETH_ALEN]) 5119 { 5120 /* Get MAC address */ 5121 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5122 u32 value = rtl_eri_read(tp, 0xe0); 5123 5124 mac_addr[0] = (value >> 0) & 0xff; 5125 mac_addr[1] = (value >> 8) & 0xff; 5126 mac_addr[2] = (value >> 16) & 0xff; 5127 mac_addr[3] = (value >> 24) & 0xff; 5128 5129 value = rtl_eri_read(tp, 0xe4); 5130 mac_addr[4] = (value >> 0) & 0xff; 5131 mac_addr[5] = (value >> 8) & 0xff; 5132 } else if (rtl_is_8125(tp)) { 5133 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5134 } 5135 } 5136 5137 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5138 { 5139 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5140 } 5141 5142 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 5143 { 5144 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 5145 } 5146 5147 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5148 { 5149 struct rtl8169_private *tp = mii_bus->priv; 5150 5151 if (phyaddr > 0) 5152 return -ENODEV; 5153 5154 return rtl_readphy(tp, phyreg); 5155 } 5156 5157 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5158 int phyreg, u16 val) 5159 { 5160 struct rtl8169_private *tp = mii_bus->priv; 5161 5162 if (phyaddr > 0) 5163 return -ENODEV; 5164 5165 rtl_writephy(tp, phyreg, val); 5166 5167 return 0; 5168 } 5169 5170 static int r8169_mdio_register(struct rtl8169_private *tp) 5171 { 5172 struct pci_dev *pdev = tp->pci_dev; 5173 struct mii_bus *new_bus; 5174 int ret; 5175 5176 new_bus = devm_mdiobus_alloc(&pdev->dev); 5177 if (!new_bus) 5178 return -ENOMEM; 5179 5180 new_bus->name = "r8169"; 5181 new_bus->priv = tp; 5182 new_bus->parent = &pdev->dev; 5183 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5184 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5185 5186 new_bus->read = r8169_mdio_read_reg; 5187 new_bus->write = r8169_mdio_write_reg; 5188 5189 ret = devm_mdiobus_register(new_bus); 5190 if (ret) 5191 return ret; 5192 5193 tp->phydev = mdiobus_get_phy(new_bus, 0); 5194 if (!tp->phydev) { 5195 return -ENODEV; 5196 } else if (!tp->phydev->drv) { 5197 /* Most chip versions fail with the genphy driver. 5198 * Therefore ensure that the dedicated PHY driver is loaded. 5199 */ 5200 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5201 tp->phydev->phy_id); 5202 return -EUNATCH; 5203 } 5204 5205 /* PHY will be woken up in rtl_open() */ 5206 phy_suspend(tp->phydev); 5207 5208 return 0; 5209 } 5210 5211 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5212 { 5213 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 5214 5215 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 5216 return; 5217 5218 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 5219 return; 5220 5221 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5222 msleep(1); 5223 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5224 5225 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5226 5227 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 5228 return; 5229 5230 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5231 5232 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5233 } 5234 5235 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5236 { 5237 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 5238 5239 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 5240 return; 5241 5242 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5243 msleep(1); 5244 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5245 5246 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5247 5248 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 5249 return; 5250 5251 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5252 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5253 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5254 5255 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5256 } 5257 5258 static void rtl_hw_initialize(struct rtl8169_private *tp) 5259 { 5260 switch (tp->mac_version) { 5261 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 5262 rtl8168ep_stop_cmac(tp); 5263 /* fall through */ 5264 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5265 rtl_hw_init_8168g(tp); 5266 break; 5267 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 5268 rtl_hw_init_8125(tp); 5269 break; 5270 default: 5271 break; 5272 } 5273 } 5274 5275 static int rtl_jumbo_max(struct rtl8169_private *tp) 5276 { 5277 /* Non-GBit versions don't support jumbo frames */ 5278 if (!tp->supports_gmii) 5279 return 0; 5280 5281 switch (tp->mac_version) { 5282 /* RTL8169 */ 5283 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5284 return JUMBO_7K; 5285 /* RTL8168b */ 5286 case RTL_GIGA_MAC_VER_11: 5287 case RTL_GIGA_MAC_VER_12: 5288 case RTL_GIGA_MAC_VER_17: 5289 return JUMBO_4K; 5290 /* RTL8168c */ 5291 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5292 return JUMBO_6K; 5293 default: 5294 return JUMBO_9K; 5295 } 5296 } 5297 5298 static void rtl_disable_clk(void *data) 5299 { 5300 clk_disable_unprepare(data); 5301 } 5302 5303 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5304 { 5305 struct device *d = tp_to_dev(tp); 5306 struct clk *clk; 5307 int rc; 5308 5309 clk = devm_clk_get(d, "ether_clk"); 5310 if (IS_ERR(clk)) { 5311 rc = PTR_ERR(clk); 5312 if (rc == -ENOENT) 5313 /* clk-core allows NULL (for suspend / resume) */ 5314 rc = 0; 5315 else if (rc != -EPROBE_DEFER) 5316 dev_err(d, "failed to get clk: %d\n", rc); 5317 } else { 5318 tp->clk = clk; 5319 rc = clk_prepare_enable(clk); 5320 if (rc) 5321 dev_err(d, "failed to enable clk: %d\n", rc); 5322 else 5323 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5324 } 5325 5326 return rc; 5327 } 5328 5329 static void rtl_init_mac_address(struct rtl8169_private *tp) 5330 { 5331 struct net_device *dev = tp->dev; 5332 u8 *mac_addr = dev->dev_addr; 5333 int rc; 5334 5335 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5336 if (!rc) 5337 goto done; 5338 5339 rtl_read_mac_address(tp, mac_addr); 5340 if (is_valid_ether_addr(mac_addr)) 5341 goto done; 5342 5343 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5344 if (is_valid_ether_addr(mac_addr)) 5345 goto done; 5346 5347 eth_hw_addr_random(dev); 5348 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5349 done: 5350 rtl_rar_set(tp, mac_addr); 5351 } 5352 5353 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5354 { 5355 struct rtl8169_private *tp; 5356 int jumbo_max, region, rc; 5357 enum mac_version chipset; 5358 struct net_device *dev; 5359 u16 xid; 5360 5361 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5362 if (!dev) 5363 return -ENOMEM; 5364 5365 SET_NETDEV_DEV(dev, &pdev->dev); 5366 dev->netdev_ops = &rtl_netdev_ops; 5367 tp = netdev_priv(dev); 5368 tp->dev = dev; 5369 tp->pci_dev = pdev; 5370 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 5371 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5372 tp->eee_adv = -1; 5373 tp->ocp_base = OCP_STD_PHY_BASE; 5374 5375 /* Get the *optional* external "ether_clk" used on some boards */ 5376 rc = rtl_get_ether_clk(tp); 5377 if (rc) 5378 return rc; 5379 5380 /* Disable ASPM completely as that cause random device stop working 5381 * problems as well as full system hangs for some PCIe devices users. 5382 */ 5383 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5384 PCIE_LINK_STATE_L1); 5385 tp->aspm_manageable = !rc; 5386 5387 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5388 rc = pcim_enable_device(pdev); 5389 if (rc < 0) { 5390 dev_err(&pdev->dev, "enable failure\n"); 5391 return rc; 5392 } 5393 5394 if (pcim_set_mwi(pdev) < 0) 5395 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5396 5397 /* use first MMIO region */ 5398 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5399 if (region < 0) { 5400 dev_err(&pdev->dev, "no MMIO resource found\n"); 5401 return -ENODEV; 5402 } 5403 5404 /* check for weird/broken PCI region reporting */ 5405 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5406 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5407 return -ENODEV; 5408 } 5409 5410 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5411 if (rc < 0) { 5412 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5413 return rc; 5414 } 5415 5416 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5417 5418 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5419 5420 /* Identify chip attached to board */ 5421 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5422 if (chipset == RTL_GIGA_MAC_NONE) { 5423 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid); 5424 return -ENODEV; 5425 } 5426 5427 tp->mac_version = chipset; 5428 5429 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5430 5431 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5432 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5433 dev->features |= NETIF_F_HIGHDMA; 5434 5435 rtl_init_rxcfg(tp); 5436 5437 rtl8169_irq_mask_and_ack(tp); 5438 5439 rtl_hw_initialize(tp); 5440 5441 rtl_hw_reset(tp); 5442 5443 pci_set_master(pdev); 5444 5445 rc = rtl_alloc_irq(tp); 5446 if (rc < 0) { 5447 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5448 return rc; 5449 } 5450 5451 mutex_init(&tp->wk.mutex); 5452 INIT_WORK(&tp->wk.work, rtl_task); 5453 u64_stats_init(&tp->rx_stats.syncp); 5454 u64_stats_init(&tp->tx_stats.syncp); 5455 5456 rtl_init_mac_address(tp); 5457 5458 dev->ethtool_ops = &rtl8169_ethtool_ops; 5459 5460 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5461 5462 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5463 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5464 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5465 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5466 5467 /* 5468 * Pretend we are using VLANs; This bypasses a nasty bug where 5469 * Interrupts stop flowing on high load on 8110SCd controllers. 5470 */ 5471 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5472 /* Disallow toggling */ 5473 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5474 5475 if (rtl_chip_supports_csum_v2(tp)) 5476 dev->hw_features |= NETIF_F_IPV6_CSUM; 5477 5478 dev->features |= dev->hw_features; 5479 5480 /* There has been a number of reports that using SG/TSO results in 5481 * tx timeouts. However for a lot of people SG/TSO works fine. 5482 * Therefore disable both features by default, but allow users to 5483 * enable them. Use at own risk! 5484 */ 5485 if (rtl_chip_supports_csum_v2(tp)) { 5486 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5487 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5488 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5489 } else { 5490 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5491 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5492 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5493 } 5494 5495 dev->hw_features |= NETIF_F_RXALL; 5496 dev->hw_features |= NETIF_F_RXFCS; 5497 5498 /* configure chip for default features */ 5499 rtl8169_set_features(dev, dev->features); 5500 5501 jumbo_max = rtl_jumbo_max(tp); 5502 if (jumbo_max) 5503 dev->max_mtu = jumbo_max; 5504 5505 rtl_set_irq_mask(tp); 5506 5507 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5508 5509 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5510 &tp->counters_phys_addr, 5511 GFP_KERNEL); 5512 if (!tp->counters) 5513 return -ENOMEM; 5514 5515 pci_set_drvdata(pdev, dev); 5516 5517 rc = r8169_mdio_register(tp); 5518 if (rc) 5519 return rc; 5520 5521 /* chip gets powered up in rtl_open() */ 5522 rtl_pll_power_down(tp); 5523 5524 rc = register_netdev(dev); 5525 if (rc) 5526 return rc; 5527 5528 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n", 5529 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5530 pci_irq_vector(pdev, 0)); 5531 5532 if (jumbo_max) 5533 netif_info(tp, probe, dev, 5534 "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5535 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5536 "ok" : "ko"); 5537 5538 if (r8168_check_dash(tp)) 5539 rtl8168_driver_start(tp); 5540 5541 if (pci_dev_run_wake(pdev)) 5542 pm_runtime_put_sync(&pdev->dev); 5543 5544 return 0; 5545 } 5546 5547 static struct pci_driver rtl8169_pci_driver = { 5548 .name = MODULENAME, 5549 .id_table = rtl8169_pci_tbl, 5550 .probe = rtl_init_one, 5551 .remove = rtl_remove_one, 5552 .shutdown = rtl_shutdown, 5553 .driver.pm = RTL8169_PM_OPS, 5554 }; 5555 5556 module_pci_driver(rtl8169_pci_driver); 5557