1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 59 60 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 61 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 62 63 #define R8169_REGS_SIZE 256 64 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 65 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 66 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 67 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 68 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 69 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 70 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 71 72 #define OCP_STD_PHY_BASE 0xa400 73 74 #define RTL_CFG_NO_GBIT 1 75 76 /* write/read MMIO register */ 77 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 81 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 82 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 83 84 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 89 static const struct { 90 const char *name; 91 const char *fw_name; 92 } rtl_chip_infos[] = { 93 /* PCI devices. */ 94 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 95 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 96 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 97 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 98 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 99 /* PCI-E devices. */ 100 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 102 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 103 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 104 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 105 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 106 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 108 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 109 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 113 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 115 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 116 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 117 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 118 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 119 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 120 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 121 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 122 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 123 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 124 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 125 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 126 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 127 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 128 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 129 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 130 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 131 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 132 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 133 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 134 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 135 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 136 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 137 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 138 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 139 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 140 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 141 }; 142 143 static const struct pci_device_id rtl8169_pci_tbl[] = { 144 { PCI_VDEVICE(REALTEK, 0x2502) }, 145 { PCI_VDEVICE(REALTEK, 0x2600) }, 146 { PCI_VDEVICE(REALTEK, 0x8129) }, 147 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 148 { PCI_VDEVICE(REALTEK, 0x8161) }, 149 { PCI_VDEVICE(REALTEK, 0x8162) }, 150 { PCI_VDEVICE(REALTEK, 0x8167) }, 151 { PCI_VDEVICE(REALTEK, 0x8168) }, 152 { PCI_VDEVICE(NCUBE, 0x8168) }, 153 { PCI_VDEVICE(REALTEK, 0x8169) }, 154 { PCI_VENDOR_ID_DLINK, 0x4300, 155 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 156 { PCI_VDEVICE(DLINK, 0x4300) }, 157 { PCI_VDEVICE(DLINK, 0x4302) }, 158 { PCI_VDEVICE(AT, 0xc107) }, 159 { PCI_VDEVICE(USR, 0x0116) }, 160 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 161 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 162 { PCI_VDEVICE(REALTEK, 0x8125) }, 163 { PCI_VDEVICE(REALTEK, 0x8126) }, 164 { PCI_VDEVICE(REALTEK, 0x3000) }, 165 {} 166 }; 167 168 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 169 170 enum rtl_registers { 171 MAC0 = 0, /* Ethernet hardware address. */ 172 MAC4 = 4, 173 MAR0 = 8, /* Multicast filter. */ 174 CounterAddrLow = 0x10, 175 CounterAddrHigh = 0x14, 176 TxDescStartAddrLow = 0x20, 177 TxDescStartAddrHigh = 0x24, 178 TxHDescStartAddrLow = 0x28, 179 TxHDescStartAddrHigh = 0x2c, 180 FLASH = 0x30, 181 ERSR = 0x36, 182 ChipCmd = 0x37, 183 TxPoll = 0x38, 184 IntrMask = 0x3c, 185 IntrStatus = 0x3e, 186 187 TxConfig = 0x40, 188 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 189 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 190 191 RxConfig = 0x44, 192 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 193 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 194 #define RXCFG_FIFO_SHIFT 13 195 /* No threshold before first PCI xfer */ 196 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 197 #define RX_EARLY_OFF (1 << 11) 198 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 199 #define RXCFG_DMA_SHIFT 8 200 /* Unlimited maximum PCI burst. */ 201 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 202 203 Cfg9346 = 0x50, 204 Config0 = 0x51, 205 Config1 = 0x52, 206 Config2 = 0x53, 207 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 208 209 Config3 = 0x54, 210 Config4 = 0x55, 211 Config5 = 0x56, 212 PHYAR = 0x60, 213 PHYstatus = 0x6c, 214 RxMaxSize = 0xda, 215 CPlusCmd = 0xe0, 216 IntrMitigate = 0xe2, 217 218 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 219 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 220 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 221 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 222 223 #define RTL_COALESCE_T_MAX 0x0fU 224 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 225 226 RxDescAddrLow = 0xe4, 227 RxDescAddrHigh = 0xe8, 228 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 229 230 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 231 232 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 233 234 #define TxPacketMax (8064 >> 7) 235 #define EarlySize 0x27 236 237 FuncEvent = 0xf0, 238 FuncEventMask = 0xf4, 239 FuncPresetState = 0xf8, 240 IBCR0 = 0xf8, 241 IBCR2 = 0xf9, 242 IBIMR0 = 0xfa, 243 IBISR0 = 0xfb, 244 FuncForceEvent = 0xfc, 245 }; 246 247 enum rtl8168_8101_registers { 248 CSIDR = 0x64, 249 CSIAR = 0x68, 250 #define CSIAR_FLAG 0x80000000 251 #define CSIAR_WRITE_CMD 0x80000000 252 #define CSIAR_BYTE_ENABLE 0x0000f000 253 #define CSIAR_ADDR_MASK 0x00000fff 254 PMCH = 0x6f, 255 #define D3COLD_NO_PLL_DOWN BIT(7) 256 #define D3HOT_NO_PLL_DOWN BIT(6) 257 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 258 EPHYAR = 0x80, 259 #define EPHYAR_FLAG 0x80000000 260 #define EPHYAR_WRITE_CMD 0x80000000 261 #define EPHYAR_REG_MASK 0x1f 262 #define EPHYAR_REG_SHIFT 16 263 #define EPHYAR_DATA_MASK 0xffff 264 DLLPR = 0xd0, 265 #define PFM_EN (1 << 6) 266 #define TX_10M_PS_EN (1 << 7) 267 DBG_REG = 0xd1, 268 #define FIX_NAK_1 (1 << 4) 269 #define FIX_NAK_2 (1 << 3) 270 TWSI = 0xd2, 271 MCU = 0xd3, 272 #define NOW_IS_OOB (1 << 7) 273 #define TX_EMPTY (1 << 5) 274 #define RX_EMPTY (1 << 4) 275 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 276 #define EN_NDP (1 << 3) 277 #define EN_OOB_RESET (1 << 2) 278 #define LINK_LIST_RDY (1 << 1) 279 EFUSEAR = 0xdc, 280 #define EFUSEAR_FLAG 0x80000000 281 #define EFUSEAR_WRITE_CMD 0x80000000 282 #define EFUSEAR_READ_CMD 0x00000000 283 #define EFUSEAR_REG_MASK 0x03ff 284 #define EFUSEAR_REG_SHIFT 8 285 #define EFUSEAR_DATA_MASK 0xff 286 MISC_1 = 0xf2, 287 #define PFM_D3COLD_EN (1 << 6) 288 }; 289 290 enum rtl8168_registers { 291 LED_CTRL = 0x18, 292 LED_FREQ = 0x1a, 293 EEE_LED = 0x1b, 294 ERIDR = 0x70, 295 ERIAR = 0x74, 296 #define ERIAR_FLAG 0x80000000 297 #define ERIAR_WRITE_CMD 0x80000000 298 #define ERIAR_READ_CMD 0x00000000 299 #define ERIAR_ADDR_BYTE_ALIGN 4 300 #define ERIAR_TYPE_SHIFT 16 301 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 303 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_MASK_SHIFT 12 306 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 308 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 311 EPHY_RXER_NUM = 0x7c, 312 OCPDR = 0xb0, /* OCP GPHY access */ 313 #define OCPDR_WRITE_CMD 0x80000000 314 #define OCPDR_READ_CMD 0x00000000 315 #define OCPDR_REG_MASK 0x7f 316 #define OCPDR_GPHY_REG_SHIFT 16 317 #define OCPDR_DATA_MASK 0xffff 318 OCPAR = 0xb4, 319 #define OCPAR_FLAG 0x80000000 320 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 321 #define OCPAR_GPHY_READ_CMD 0x0000f060 322 GPHY_OCP = 0xb8, 323 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 324 MISC = 0xf0, /* 8168e only. */ 325 #define TXPLA_RST (1 << 29) 326 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 327 #define PWM_EN (1 << 22) 328 #define RXDV_GATED_EN (1 << 19) 329 #define EARLY_TALLY_EN (1 << 16) 330 }; 331 332 enum rtl8125_registers { 333 INT_CFG0_8125 = 0x34, 334 #define INT_CFG0_ENABLE_8125 BIT(0) 335 #define INT_CFG0_CLKREQEN BIT(3) 336 IntrMask_8125 = 0x38, 337 IntrStatus_8125 = 0x3c, 338 INT_CFG1_8125 = 0x7a, 339 TxPoll_8125 = 0x90, 340 MAC0_BKP = 0x19e0, 341 EEE_TXIDLE_TIMER_8125 = 0x6048, 342 }; 343 344 #define RX_VLAN_INNER_8125 BIT(22) 345 #define RX_VLAN_OUTER_8125 BIT(23) 346 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 347 348 #define RX_FETCH_DFLT_8125 (8 << 27) 349 350 enum rtl_register_content { 351 /* InterruptStatusBits */ 352 SYSErr = 0x8000, 353 PCSTimeout = 0x4000, 354 SWInt = 0x0100, 355 TxDescUnavail = 0x0080, 356 RxFIFOOver = 0x0040, 357 LinkChg = 0x0020, 358 RxOverflow = 0x0010, 359 TxErr = 0x0008, 360 TxOK = 0x0004, 361 RxErr = 0x0002, 362 RxOK = 0x0001, 363 364 /* RxStatusDesc */ 365 RxRWT = (1 << 22), 366 RxRES = (1 << 21), 367 RxRUNT = (1 << 20), 368 RxCRC = (1 << 19), 369 370 /* ChipCmdBits */ 371 StopReq = 0x80, 372 CmdReset = 0x10, 373 CmdRxEnb = 0x08, 374 CmdTxEnb = 0x04, 375 RxBufEmpty = 0x01, 376 377 /* TXPoll register p.5 */ 378 HPQ = 0x80, /* Poll cmd on the high prio queue */ 379 NPQ = 0x40, /* Poll cmd on the low prio queue */ 380 FSWInt = 0x01, /* Forced software interrupt */ 381 382 /* Cfg9346Bits */ 383 Cfg9346_Lock = 0x00, 384 Cfg9346_Unlock = 0xc0, 385 386 /* rx_mode_bits */ 387 AcceptErr = 0x20, 388 AcceptRunt = 0x10, 389 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 390 AcceptBroadcast = 0x08, 391 AcceptMulticast = 0x04, 392 AcceptMyPhys = 0x02, 393 AcceptAllPhys = 0x01, 394 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 395 #define RX_CONFIG_ACCEPT_MASK 0x3f 396 397 /* TxConfigBits */ 398 TxInterFrameGapShift = 24, 399 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 400 401 /* Config1 register p.24 */ 402 LEDS1 = (1 << 7), 403 LEDS0 = (1 << 6), 404 Speed_down = (1 << 4), 405 MEMMAP = (1 << 3), 406 IOMAP = (1 << 2), 407 VPD = (1 << 1), 408 PMEnable = (1 << 0), /* Power Management Enable */ 409 410 /* Config2 register p. 25 */ 411 ClkReqEn = (1 << 7), /* Clock Request Enable */ 412 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 413 PCI_Clock_66MHz = 0x01, 414 PCI_Clock_33MHz = 0x00, 415 416 /* Config3 register p.25 */ 417 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 418 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 419 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 420 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 421 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 422 423 /* Config4 register */ 424 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 425 426 /* Config5 register p.27 */ 427 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 428 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 429 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 430 Spi_en = (1 << 3), 431 LanWake = (1 << 1), /* LanWake enable/disable */ 432 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 433 ASPM_en = (1 << 0), /* ASPM enable */ 434 435 /* CPlusCmd p.31 */ 436 EnableBist = (1 << 15), // 8168 8101 437 Mac_dbgo_oe = (1 << 14), // 8168 8101 438 EnAnaPLL = (1 << 14), // 8169 439 Normal_mode = (1 << 13), // unused 440 Force_half_dup = (1 << 12), // 8168 8101 441 Force_rxflow_en = (1 << 11), // 8168 8101 442 Force_txflow_en = (1 << 10), // 8168 8101 443 Cxpl_dbg_sel = (1 << 9), // 8168 8101 444 ASF = (1 << 8), // 8168 8101 445 PktCntrDisable = (1 << 7), // 8168 8101 446 Mac_dbgo_sel = 0x001c, // 8168 447 RxVlan = (1 << 6), 448 RxChkSum = (1 << 5), 449 PCIDAC = (1 << 4), 450 PCIMulRW = (1 << 3), 451 #define INTT_MASK GENMASK(1, 0) 452 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 453 454 /* rtl8169_PHYstatus */ 455 TBI_Enable = 0x80, 456 TxFlowCtrl = 0x40, 457 RxFlowCtrl = 0x20, 458 _1000bpsF = 0x10, 459 _100bps = 0x08, 460 _10bps = 0x04, 461 LinkStatus = 0x02, 462 FullDup = 0x01, 463 464 /* ResetCounterCommand */ 465 CounterReset = 0x1, 466 467 /* DumpCounterCommand */ 468 CounterDump = 0x8, 469 470 /* magic enable v2 */ 471 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 472 }; 473 474 enum rtl_desc_bit { 475 /* First doubleword. */ 476 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 477 RingEnd = (1 << 30), /* End of descriptor ring */ 478 FirstFrag = (1 << 29), /* First segment of a packet */ 479 LastFrag = (1 << 28), /* Final segment of a packet */ 480 }; 481 482 /* Generic case. */ 483 enum rtl_tx_desc_bit { 484 /* First doubleword. */ 485 TD_LSO = (1 << 27), /* Large Send Offload */ 486 #define TD_MSS_MAX 0x07ffu /* MSS value */ 487 488 /* Second doubleword. */ 489 TxVlanTag = (1 << 17), /* Add VLAN tag */ 490 }; 491 492 /* 8169, 8168b and 810x except 8102e. */ 493 enum rtl_tx_desc_bit_0 { 494 /* First doubleword. */ 495 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 496 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 497 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 498 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 499 }; 500 501 /* 8102e, 8168c and beyond. */ 502 enum rtl_tx_desc_bit_1 { 503 /* First doubleword. */ 504 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 505 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 506 #define GTTCPHO_SHIFT 18 507 #define GTTCPHO_MAX 0x7f 508 509 /* Second doubleword. */ 510 #define TCPHO_SHIFT 18 511 #define TCPHO_MAX 0x3ff 512 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 513 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 514 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 515 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 516 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 517 }; 518 519 enum rtl_rx_desc_bit { 520 /* Rx private */ 521 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 522 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 523 524 #define RxProtoUDP (PID1) 525 #define RxProtoTCP (PID0) 526 #define RxProtoIP (PID1 | PID0) 527 #define RxProtoMask RxProtoIP 528 529 IPFail = (1 << 16), /* IP checksum failed */ 530 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 531 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 532 533 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 534 535 RxVlanTag = (1 << 16), /* VLAN tag available */ 536 }; 537 538 #define RTL_GSO_MAX_SIZE_V1 32000 539 #define RTL_GSO_MAX_SEGS_V1 24 540 #define RTL_GSO_MAX_SIZE_V2 64000 541 #define RTL_GSO_MAX_SEGS_V2 64 542 543 struct TxDesc { 544 __le32 opts1; 545 __le32 opts2; 546 __le64 addr; 547 }; 548 549 struct RxDesc { 550 __le32 opts1; 551 __le32 opts2; 552 __le64 addr; 553 }; 554 555 struct ring_info { 556 struct sk_buff *skb; 557 u32 len; 558 }; 559 560 struct rtl8169_counters { 561 __le64 tx_packets; 562 __le64 rx_packets; 563 __le64 tx_errors; 564 __le32 rx_errors; 565 __le16 rx_missed; 566 __le16 align_errors; 567 __le32 tx_one_collision; 568 __le32 tx_multi_collision; 569 __le64 rx_unicast; 570 __le64 rx_broadcast; 571 __le32 rx_multicast; 572 __le16 tx_aborted; 573 __le16 tx_underun; 574 }; 575 576 struct rtl8169_tc_offsets { 577 bool inited; 578 __le64 tx_errors; 579 __le32 tx_multi_collision; 580 __le16 tx_aborted; 581 __le16 rx_missed; 582 }; 583 584 enum rtl_flag { 585 RTL_FLAG_TASK_ENABLED = 0, 586 RTL_FLAG_TASK_RESET_PENDING, 587 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 588 RTL_FLAG_TASK_TX_TIMEOUT, 589 RTL_FLAG_MAX 590 }; 591 592 enum rtl_dash_type { 593 RTL_DASH_NONE, 594 RTL_DASH_DP, 595 RTL_DASH_EP, 596 }; 597 598 struct rtl8169_private { 599 void __iomem *mmio_addr; /* memory map physical address */ 600 struct pci_dev *pci_dev; 601 struct net_device *dev; 602 struct phy_device *phydev; 603 struct napi_struct napi; 604 enum mac_version mac_version; 605 enum rtl_dash_type dash_type; 606 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 607 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 608 u32 dirty_tx; 609 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 610 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 611 dma_addr_t TxPhyAddr; 612 dma_addr_t RxPhyAddr; 613 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 614 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 615 u16 cp_cmd; 616 u32 irq_mask; 617 int irq; 618 struct clk *clk; 619 620 struct { 621 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 622 struct work_struct work; 623 } wk; 624 625 raw_spinlock_t config25_lock; 626 raw_spinlock_t mac_ocp_lock; 627 struct mutex led_lock; /* serialize LED ctrl RMW access */ 628 629 raw_spinlock_t cfg9346_usage_lock; 630 int cfg9346_usage_count; 631 632 unsigned supports_gmii:1; 633 unsigned aspm_manageable:1; 634 unsigned dash_enabled:1; 635 dma_addr_t counters_phys_addr; 636 struct rtl8169_counters *counters; 637 struct rtl8169_tc_offsets tc_offset; 638 u32 saved_wolopts; 639 640 const char *fw_name; 641 struct rtl_fw *rtl_fw; 642 643 u32 ocp_base; 644 }; 645 646 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 647 648 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 649 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 650 MODULE_SOFTDEP("pre: realtek"); 651 MODULE_LICENSE("GPL"); 652 MODULE_FIRMWARE(FIRMWARE_8168D_1); 653 MODULE_FIRMWARE(FIRMWARE_8168D_2); 654 MODULE_FIRMWARE(FIRMWARE_8168E_1); 655 MODULE_FIRMWARE(FIRMWARE_8168E_2); 656 MODULE_FIRMWARE(FIRMWARE_8168E_3); 657 MODULE_FIRMWARE(FIRMWARE_8105E_1); 658 MODULE_FIRMWARE(FIRMWARE_8168F_1); 659 MODULE_FIRMWARE(FIRMWARE_8168F_2); 660 MODULE_FIRMWARE(FIRMWARE_8402_1); 661 MODULE_FIRMWARE(FIRMWARE_8411_1); 662 MODULE_FIRMWARE(FIRMWARE_8411_2); 663 MODULE_FIRMWARE(FIRMWARE_8106E_1); 664 MODULE_FIRMWARE(FIRMWARE_8106E_2); 665 MODULE_FIRMWARE(FIRMWARE_8168G_2); 666 MODULE_FIRMWARE(FIRMWARE_8168G_3); 667 MODULE_FIRMWARE(FIRMWARE_8168H_2); 668 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 669 MODULE_FIRMWARE(FIRMWARE_8107E_2); 670 MODULE_FIRMWARE(FIRMWARE_8125A_3); 671 MODULE_FIRMWARE(FIRMWARE_8125B_2); 672 673 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 674 { 675 return &tp->pci_dev->dev; 676 } 677 678 static void rtl_lock_config_regs(struct rtl8169_private *tp) 679 { 680 unsigned long flags; 681 682 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 683 if (!--tp->cfg9346_usage_count) 684 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 685 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 686 } 687 688 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 689 { 690 unsigned long flags; 691 692 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 693 if (!tp->cfg9346_usage_count++) 694 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 695 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 696 } 697 698 static void rtl_pci_commit(struct rtl8169_private *tp) 699 { 700 /* Read an arbitrary register to commit a preceding PCI write */ 701 RTL_R8(tp, ChipCmd); 702 } 703 704 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 705 { 706 unsigned long flags; 707 u8 val; 708 709 raw_spin_lock_irqsave(&tp->config25_lock, flags); 710 val = RTL_R8(tp, Config2); 711 RTL_W8(tp, Config2, (val & ~clear) | set); 712 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 713 } 714 715 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 716 { 717 unsigned long flags; 718 u8 val; 719 720 raw_spin_lock_irqsave(&tp->config25_lock, flags); 721 val = RTL_R8(tp, Config5); 722 RTL_W8(tp, Config5, (val & ~clear) | set); 723 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 724 } 725 726 static bool rtl_is_8125(struct rtl8169_private *tp) 727 { 728 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 729 } 730 731 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 732 { 733 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 734 tp->mac_version != RTL_GIGA_MAC_VER_39 && 735 tp->mac_version <= RTL_GIGA_MAC_VER_53; 736 } 737 738 static bool rtl_supports_eee(struct rtl8169_private *tp) 739 { 740 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 741 tp->mac_version != RTL_GIGA_MAC_VER_37 && 742 tp->mac_version != RTL_GIGA_MAC_VER_39; 743 } 744 745 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 746 { 747 int i; 748 749 for (i = 0; i < ETH_ALEN; i++) 750 mac[i] = RTL_R8(tp, reg + i); 751 } 752 753 struct rtl_cond { 754 bool (*check)(struct rtl8169_private *); 755 const char *msg; 756 }; 757 758 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 759 unsigned long usecs, int n, bool high) 760 { 761 int i; 762 763 for (i = 0; i < n; i++) { 764 if (c->check(tp) == high) 765 return true; 766 fsleep(usecs); 767 } 768 769 if (net_ratelimit()) 770 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 771 c->msg, !high, n, usecs); 772 return false; 773 } 774 775 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 776 const struct rtl_cond *c, 777 unsigned long d, int n) 778 { 779 return rtl_loop_wait(tp, c, d, n, true); 780 } 781 782 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 783 const struct rtl_cond *c, 784 unsigned long d, int n) 785 { 786 return rtl_loop_wait(tp, c, d, n, false); 787 } 788 789 #define DECLARE_RTL_COND(name) \ 790 static bool name ## _check(struct rtl8169_private *); \ 791 \ 792 static const struct rtl_cond name = { \ 793 .check = name ## _check, \ 794 .msg = #name \ 795 }; \ 796 \ 797 static bool name ## _check(struct rtl8169_private *tp) 798 799 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 800 { 801 struct device *dev = tp_to_dev(tp); 802 int ret; 803 804 ret = pm_runtime_resume_and_get(dev); 805 if (ret < 0) 806 return ret; 807 808 mutex_lock(&tp->led_lock); 809 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 810 mutex_unlock(&tp->led_lock); 811 812 pm_runtime_put_sync(dev); 813 814 return 0; 815 } 816 817 int rtl8168_get_led_mode(struct rtl8169_private *tp) 818 { 819 struct device *dev = tp_to_dev(tp); 820 int ret; 821 822 ret = pm_runtime_resume_and_get(dev); 823 if (ret < 0) 824 return ret; 825 826 ret = RTL_R16(tp, LED_CTRL); 827 828 pm_runtime_put_sync(dev); 829 830 return ret; 831 } 832 833 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 834 char *buf, int buf_len) 835 { 836 struct pci_dev *pdev = tp->pci_dev; 837 char pdom[8], pfun[8]; 838 int domain; 839 840 domain = pci_domain_nr(pdev->bus); 841 if (domain) 842 snprintf(pdom, sizeof(pdom), "P%d", domain); 843 else 844 pdom[0] = '\0'; 845 846 if (pdev->multifunction) 847 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 848 else 849 pfun[0] = '\0'; 850 851 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 852 PCI_SLOT(pdev->devfn), pfun, idx); 853 } 854 855 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 856 { 857 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 858 if (type == ERIAR_OOB && 859 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 860 tp->mac_version == RTL_GIGA_MAC_VER_53)) 861 *cmd |= 0xf70 << 18; 862 } 863 864 DECLARE_RTL_COND(rtl_eriar_cond) 865 { 866 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 867 } 868 869 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 870 u32 val, int type) 871 { 872 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 873 874 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 875 return; 876 877 RTL_W32(tp, ERIDR, val); 878 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 879 RTL_W32(tp, ERIAR, cmd); 880 881 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 882 } 883 884 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 885 u32 val) 886 { 887 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 888 } 889 890 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 891 { 892 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 893 894 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 895 RTL_W32(tp, ERIAR, cmd); 896 897 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 898 RTL_R32(tp, ERIDR) : ~0; 899 } 900 901 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 902 { 903 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 904 } 905 906 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 907 { 908 u32 val = rtl_eri_read(tp, addr); 909 910 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 911 } 912 913 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 914 { 915 rtl_w0w1_eri(tp, addr, p, 0); 916 } 917 918 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 919 { 920 rtl_w0w1_eri(tp, addr, 0, m); 921 } 922 923 static bool rtl_ocp_reg_failure(u32 reg) 924 { 925 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 926 } 927 928 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 929 { 930 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 931 } 932 933 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 934 { 935 if (rtl_ocp_reg_failure(reg)) 936 return; 937 938 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 939 940 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 941 } 942 943 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 944 { 945 if (rtl_ocp_reg_failure(reg)) 946 return 0; 947 948 RTL_W32(tp, GPHY_OCP, reg << 15); 949 950 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 951 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 952 } 953 954 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 955 { 956 if (rtl_ocp_reg_failure(reg)) 957 return; 958 959 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 960 } 961 962 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 963 { 964 unsigned long flags; 965 966 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 967 __r8168_mac_ocp_write(tp, reg, data); 968 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 969 } 970 971 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 972 { 973 if (rtl_ocp_reg_failure(reg)) 974 return 0; 975 976 RTL_W32(tp, OCPDR, reg << 15); 977 978 return RTL_R32(tp, OCPDR); 979 } 980 981 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 982 { 983 unsigned long flags; 984 u16 val; 985 986 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 987 val = __r8168_mac_ocp_read(tp, reg); 988 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 989 990 return val; 991 } 992 993 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 994 u16 set) 995 { 996 unsigned long flags; 997 u16 data; 998 999 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1000 data = __r8168_mac_ocp_read(tp, reg); 1001 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1002 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1003 } 1004 1005 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1006 * PHY MCU interrupts before PHY power-down. 1007 */ 1008 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1009 { 1010 switch (tp->mac_version) { 1011 case RTL_GIGA_MAC_VER_40: 1012 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1013 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1014 else 1015 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1016 break; 1017 default: 1018 break; 1019 } 1020 }; 1021 1022 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1023 { 1024 if (reg == 0x1f) { 1025 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1026 return; 1027 } 1028 1029 if (tp->ocp_base != OCP_STD_PHY_BASE) 1030 reg -= 0x10; 1031 1032 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1033 rtl8168g_phy_suspend_quirk(tp, value); 1034 1035 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1036 } 1037 1038 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1039 { 1040 if (reg == 0x1f) 1041 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1042 1043 if (tp->ocp_base != OCP_STD_PHY_BASE) 1044 reg -= 0x10; 1045 1046 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1047 } 1048 1049 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1050 { 1051 if (reg == 0x1f) { 1052 tp->ocp_base = value << 4; 1053 return; 1054 } 1055 1056 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1057 } 1058 1059 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1060 { 1061 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1062 } 1063 1064 DECLARE_RTL_COND(rtl_phyar_cond) 1065 { 1066 return RTL_R32(tp, PHYAR) & 0x80000000; 1067 } 1068 1069 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1070 { 1071 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1072 1073 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1074 /* 1075 * According to hardware specs a 20us delay is required after write 1076 * complete indication, but before sending next command. 1077 */ 1078 udelay(20); 1079 } 1080 1081 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1082 { 1083 int value; 1084 1085 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1086 1087 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1088 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1089 1090 /* 1091 * According to hardware specs a 20us delay is required after read 1092 * complete indication, but before sending next command. 1093 */ 1094 udelay(20); 1095 1096 return value; 1097 } 1098 1099 DECLARE_RTL_COND(rtl_ocpar_cond) 1100 { 1101 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1102 } 1103 1104 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1105 1106 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1107 { 1108 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1109 } 1110 1111 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1112 { 1113 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1114 } 1115 1116 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1117 { 1118 r8168dp_2_mdio_start(tp); 1119 1120 r8169_mdio_write(tp, reg, value); 1121 1122 r8168dp_2_mdio_stop(tp); 1123 } 1124 1125 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1126 { 1127 int value; 1128 1129 /* Work around issue with chip reporting wrong PHY ID */ 1130 if (reg == MII_PHYSID2) 1131 return 0xc912; 1132 1133 r8168dp_2_mdio_start(tp); 1134 1135 value = r8169_mdio_read(tp, reg); 1136 1137 r8168dp_2_mdio_stop(tp); 1138 1139 return value; 1140 } 1141 1142 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1143 { 1144 switch (tp->mac_version) { 1145 case RTL_GIGA_MAC_VER_28: 1146 case RTL_GIGA_MAC_VER_31: 1147 r8168dp_2_mdio_write(tp, location, val); 1148 break; 1149 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 1150 r8168g_mdio_write(tp, location, val); 1151 break; 1152 default: 1153 r8169_mdio_write(tp, location, val); 1154 break; 1155 } 1156 } 1157 1158 static int rtl_readphy(struct rtl8169_private *tp, int location) 1159 { 1160 switch (tp->mac_version) { 1161 case RTL_GIGA_MAC_VER_28: 1162 case RTL_GIGA_MAC_VER_31: 1163 return r8168dp_2_mdio_read(tp, location); 1164 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 1165 return r8168g_mdio_read(tp, location); 1166 default: 1167 return r8169_mdio_read(tp, location); 1168 } 1169 } 1170 1171 DECLARE_RTL_COND(rtl_ephyar_cond) 1172 { 1173 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1174 } 1175 1176 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1177 { 1178 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1179 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1180 1181 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1182 1183 udelay(10); 1184 } 1185 1186 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1187 { 1188 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1189 1190 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1191 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1192 } 1193 1194 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1195 { 1196 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1197 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1198 RTL_R32(tp, OCPDR) : ~0; 1199 } 1200 1201 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1202 { 1203 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1204 } 1205 1206 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1207 u32 data) 1208 { 1209 RTL_W32(tp, OCPDR, data); 1210 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1211 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1212 } 1213 1214 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1215 u32 data) 1216 { 1217 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1218 data, ERIAR_OOB); 1219 } 1220 1221 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1222 { 1223 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1224 1225 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1226 } 1227 1228 #define OOB_CMD_RESET 0x00 1229 #define OOB_CMD_DRIVER_START 0x05 1230 #define OOB_CMD_DRIVER_STOP 0x06 1231 1232 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1233 { 1234 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1235 } 1236 1237 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1238 { 1239 u16 reg; 1240 1241 reg = rtl8168_get_ocp_reg(tp); 1242 1243 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1244 } 1245 1246 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1247 { 1248 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1249 } 1250 1251 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1252 { 1253 return RTL_R8(tp, IBISR0) & 0x20; 1254 } 1255 1256 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1257 { 1258 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1259 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1260 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1261 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1262 } 1263 1264 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1265 { 1266 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1267 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1268 } 1269 1270 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1271 { 1272 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1273 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1274 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1275 } 1276 1277 static void rtl8168_driver_start(struct rtl8169_private *tp) 1278 { 1279 if (tp->dash_type == RTL_DASH_DP) 1280 rtl8168dp_driver_start(tp); 1281 else 1282 rtl8168ep_driver_start(tp); 1283 } 1284 1285 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1286 { 1287 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1288 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1289 } 1290 1291 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1292 { 1293 rtl8168ep_stop_cmac(tp); 1294 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1295 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1296 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1297 } 1298 1299 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1300 { 1301 if (tp->dash_type == RTL_DASH_DP) 1302 rtl8168dp_driver_stop(tp); 1303 else 1304 rtl8168ep_driver_stop(tp); 1305 } 1306 1307 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1308 { 1309 u16 reg = rtl8168_get_ocp_reg(tp); 1310 1311 return r8168dp_ocp_read(tp, reg) & BIT(15); 1312 } 1313 1314 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1315 { 1316 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1317 } 1318 1319 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1320 { 1321 switch (tp->dash_type) { 1322 case RTL_DASH_DP: 1323 return r8168dp_check_dash(tp); 1324 case RTL_DASH_EP: 1325 return r8168ep_check_dash(tp); 1326 default: 1327 return false; 1328 } 1329 } 1330 1331 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1332 { 1333 switch (tp->mac_version) { 1334 case RTL_GIGA_MAC_VER_28: 1335 case RTL_GIGA_MAC_VER_31: 1336 return RTL_DASH_DP; 1337 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1338 return RTL_DASH_EP; 1339 default: 1340 return RTL_DASH_NONE; 1341 } 1342 } 1343 1344 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1345 { 1346 switch (tp->mac_version) { 1347 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1348 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1349 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1350 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65: 1351 if (enable) 1352 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1353 else 1354 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1355 break; 1356 default: 1357 break; 1358 } 1359 } 1360 1361 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1362 { 1363 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1364 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1365 } 1366 1367 DECLARE_RTL_COND(rtl_efusear_cond) 1368 { 1369 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1370 } 1371 1372 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1373 { 1374 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1375 1376 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1377 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1378 } 1379 1380 static u32 rtl_get_events(struct rtl8169_private *tp) 1381 { 1382 if (rtl_is_8125(tp)) 1383 return RTL_R32(tp, IntrStatus_8125); 1384 else 1385 return RTL_R16(tp, IntrStatus); 1386 } 1387 1388 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1389 { 1390 if (rtl_is_8125(tp)) 1391 RTL_W32(tp, IntrStatus_8125, bits); 1392 else 1393 RTL_W16(tp, IntrStatus, bits); 1394 } 1395 1396 static void rtl_irq_disable(struct rtl8169_private *tp) 1397 { 1398 if (rtl_is_8125(tp)) 1399 RTL_W32(tp, IntrMask_8125, 0); 1400 else 1401 RTL_W16(tp, IntrMask, 0); 1402 } 1403 1404 static void rtl_irq_enable(struct rtl8169_private *tp) 1405 { 1406 if (rtl_is_8125(tp)) 1407 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1408 else 1409 RTL_W16(tp, IntrMask, tp->irq_mask); 1410 } 1411 1412 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1413 { 1414 rtl_irq_disable(tp); 1415 rtl_ack_events(tp, 0xffffffff); 1416 rtl_pci_commit(tp); 1417 } 1418 1419 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1420 { 1421 struct phy_device *phydev = tp->phydev; 1422 1423 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1424 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1425 if (phydev->speed == SPEED_1000) { 1426 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1427 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1428 } else if (phydev->speed == SPEED_100) { 1429 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1430 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1431 } else { 1432 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1433 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1434 } 1435 rtl_reset_packet_filter(tp); 1436 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1437 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1438 if (phydev->speed == SPEED_1000) { 1439 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1440 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1441 } else { 1442 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1443 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1444 } 1445 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1446 if (phydev->speed == SPEED_10) { 1447 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1448 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1449 } else { 1450 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1451 } 1452 } 1453 } 1454 1455 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1456 1457 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1458 { 1459 struct rtl8169_private *tp = netdev_priv(dev); 1460 1461 wol->supported = WAKE_ANY; 1462 wol->wolopts = tp->saved_wolopts; 1463 } 1464 1465 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1466 { 1467 static const struct { 1468 u32 opt; 1469 u16 reg; 1470 u8 mask; 1471 } cfg[] = { 1472 { WAKE_PHY, Config3, LinkUp }, 1473 { WAKE_UCAST, Config5, UWF }, 1474 { WAKE_BCAST, Config5, BWF }, 1475 { WAKE_MCAST, Config5, MWF }, 1476 { WAKE_ANY, Config5, LanWake }, 1477 { WAKE_MAGIC, Config3, MagicPacket } 1478 }; 1479 unsigned int i, tmp = ARRAY_SIZE(cfg); 1480 unsigned long flags; 1481 u8 options; 1482 1483 rtl_unlock_config_regs(tp); 1484 1485 if (rtl_is_8168evl_up(tp)) { 1486 tmp--; 1487 if (wolopts & WAKE_MAGIC) 1488 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1489 else 1490 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1491 } else if (rtl_is_8125(tp)) { 1492 tmp--; 1493 if (wolopts & WAKE_MAGIC) 1494 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1495 else 1496 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1497 } 1498 1499 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1500 for (i = 0; i < tmp; i++) { 1501 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1502 if (wolopts & cfg[i].opt) 1503 options |= cfg[i].mask; 1504 RTL_W8(tp, cfg[i].reg, options); 1505 } 1506 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1507 1508 switch (tp->mac_version) { 1509 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1510 options = RTL_R8(tp, Config1) & ~PMEnable; 1511 if (wolopts) 1512 options |= PMEnable; 1513 RTL_W8(tp, Config1, options); 1514 break; 1515 case RTL_GIGA_MAC_VER_34: 1516 case RTL_GIGA_MAC_VER_37: 1517 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_65: 1518 if (wolopts) 1519 rtl_mod_config2(tp, 0, PME_SIGNAL); 1520 else 1521 rtl_mod_config2(tp, PME_SIGNAL, 0); 1522 break; 1523 default: 1524 break; 1525 } 1526 1527 rtl_lock_config_regs(tp); 1528 1529 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1530 1531 if (!tp->dash_enabled) { 1532 rtl_set_d3_pll_down(tp, !wolopts); 1533 tp->dev->wol_enabled = wolopts ? 1 : 0; 1534 } 1535 } 1536 1537 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1538 { 1539 struct rtl8169_private *tp = netdev_priv(dev); 1540 1541 if (wol->wolopts & ~WAKE_ANY) 1542 return -EINVAL; 1543 1544 tp->saved_wolopts = wol->wolopts; 1545 __rtl8169_set_wol(tp, tp->saved_wolopts); 1546 1547 return 0; 1548 } 1549 1550 static void rtl8169_get_drvinfo(struct net_device *dev, 1551 struct ethtool_drvinfo *info) 1552 { 1553 struct rtl8169_private *tp = netdev_priv(dev); 1554 struct rtl_fw *rtl_fw = tp->rtl_fw; 1555 1556 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1557 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1558 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1559 if (rtl_fw) 1560 strscpy(info->fw_version, rtl_fw->version, 1561 sizeof(info->fw_version)); 1562 } 1563 1564 static int rtl8169_get_regs_len(struct net_device *dev) 1565 { 1566 return R8169_REGS_SIZE; 1567 } 1568 1569 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1570 netdev_features_t features) 1571 { 1572 struct rtl8169_private *tp = netdev_priv(dev); 1573 1574 if (dev->mtu > TD_MSS_MAX) 1575 features &= ~NETIF_F_ALL_TSO; 1576 1577 if (dev->mtu > ETH_DATA_LEN && 1578 tp->mac_version > RTL_GIGA_MAC_VER_06) 1579 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1580 1581 return features; 1582 } 1583 1584 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1585 netdev_features_t features) 1586 { 1587 u32 rx_config = RTL_R32(tp, RxConfig); 1588 1589 if (features & NETIF_F_RXALL) 1590 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1591 else 1592 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1593 1594 if (rtl_is_8125(tp)) { 1595 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1596 rx_config |= RX_VLAN_8125; 1597 else 1598 rx_config &= ~RX_VLAN_8125; 1599 } 1600 1601 RTL_W32(tp, RxConfig, rx_config); 1602 } 1603 1604 static int rtl8169_set_features(struct net_device *dev, 1605 netdev_features_t features) 1606 { 1607 struct rtl8169_private *tp = netdev_priv(dev); 1608 1609 rtl_set_rx_config_features(tp, features); 1610 1611 if (features & NETIF_F_RXCSUM) 1612 tp->cp_cmd |= RxChkSum; 1613 else 1614 tp->cp_cmd &= ~RxChkSum; 1615 1616 if (!rtl_is_8125(tp)) { 1617 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1618 tp->cp_cmd |= RxVlan; 1619 else 1620 tp->cp_cmd &= ~RxVlan; 1621 } 1622 1623 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1624 rtl_pci_commit(tp); 1625 1626 return 0; 1627 } 1628 1629 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1630 { 1631 return (skb_vlan_tag_present(skb)) ? 1632 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1633 } 1634 1635 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1636 { 1637 u32 opts2 = le32_to_cpu(desc->opts2); 1638 1639 if (opts2 & RxVlanTag) 1640 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1641 } 1642 1643 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1644 void *p) 1645 { 1646 struct rtl8169_private *tp = netdev_priv(dev); 1647 u32 __iomem *data = tp->mmio_addr; 1648 u32 *dw = p; 1649 int i; 1650 1651 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1652 memcpy_fromio(dw++, data++, 4); 1653 } 1654 1655 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1656 "tx_packets", 1657 "rx_packets", 1658 "tx_errors", 1659 "rx_errors", 1660 "rx_missed", 1661 "align_errors", 1662 "tx_single_collisions", 1663 "tx_multi_collisions", 1664 "unicast", 1665 "broadcast", 1666 "multicast", 1667 "tx_aborted", 1668 "tx_underrun", 1669 }; 1670 1671 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1672 { 1673 switch (sset) { 1674 case ETH_SS_STATS: 1675 return ARRAY_SIZE(rtl8169_gstrings); 1676 default: 1677 return -EOPNOTSUPP; 1678 } 1679 } 1680 1681 DECLARE_RTL_COND(rtl_counters_cond) 1682 { 1683 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1684 } 1685 1686 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1687 { 1688 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1689 1690 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1691 rtl_pci_commit(tp); 1692 RTL_W32(tp, CounterAddrLow, cmd); 1693 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1694 1695 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1696 } 1697 1698 static void rtl8169_update_counters(struct rtl8169_private *tp) 1699 { 1700 u8 val = RTL_R8(tp, ChipCmd); 1701 1702 /* 1703 * Some chips are unable to dump tally counters when the receiver 1704 * is disabled. If 0xff chip may be in a PCI power-save state. 1705 */ 1706 if (val & CmdRxEnb && val != 0xff) 1707 rtl8169_do_counters(tp, CounterDump); 1708 } 1709 1710 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1711 { 1712 struct rtl8169_counters *counters = tp->counters; 1713 1714 /* 1715 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1716 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1717 * reset by a power cycle, while the counter values collected by the 1718 * driver are reset at every driver unload/load cycle. 1719 * 1720 * To make sure the HW values returned by @get_stats64 match the SW 1721 * values, we collect the initial values at first open(*) and use them 1722 * as offsets to normalize the values returned by @get_stats64. 1723 * 1724 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1725 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1726 * set at open time by rtl_hw_start. 1727 */ 1728 1729 if (tp->tc_offset.inited) 1730 return; 1731 1732 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1733 rtl8169_do_counters(tp, CounterReset); 1734 } else { 1735 rtl8169_update_counters(tp); 1736 tp->tc_offset.tx_errors = counters->tx_errors; 1737 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1738 tp->tc_offset.tx_aborted = counters->tx_aborted; 1739 tp->tc_offset.rx_missed = counters->rx_missed; 1740 } 1741 1742 tp->tc_offset.inited = true; 1743 } 1744 1745 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1746 struct ethtool_stats *stats, u64 *data) 1747 { 1748 struct rtl8169_private *tp = netdev_priv(dev); 1749 struct rtl8169_counters *counters; 1750 1751 counters = tp->counters; 1752 rtl8169_update_counters(tp); 1753 1754 data[0] = le64_to_cpu(counters->tx_packets); 1755 data[1] = le64_to_cpu(counters->rx_packets); 1756 data[2] = le64_to_cpu(counters->tx_errors); 1757 data[3] = le32_to_cpu(counters->rx_errors); 1758 data[4] = le16_to_cpu(counters->rx_missed); 1759 data[5] = le16_to_cpu(counters->align_errors); 1760 data[6] = le32_to_cpu(counters->tx_one_collision); 1761 data[7] = le32_to_cpu(counters->tx_multi_collision); 1762 data[8] = le64_to_cpu(counters->rx_unicast); 1763 data[9] = le64_to_cpu(counters->rx_broadcast); 1764 data[10] = le32_to_cpu(counters->rx_multicast); 1765 data[11] = le16_to_cpu(counters->tx_aborted); 1766 data[12] = le16_to_cpu(counters->tx_underun); 1767 } 1768 1769 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1770 { 1771 switch(stringset) { 1772 case ETH_SS_STATS: 1773 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1774 break; 1775 } 1776 } 1777 1778 /* 1779 * Interrupt coalescing 1780 * 1781 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1782 * > 8169, 8168 and 810x line of chipsets 1783 * 1784 * 8169, 8168, and 8136(810x) serial chipsets support it. 1785 * 1786 * > 2 - the Tx timer unit at gigabit speed 1787 * 1788 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1789 * (0xe0) bit 1 and bit 0. 1790 * 1791 * For 8169 1792 * bit[1:0] \ speed 1000M 100M 10M 1793 * 0 0 320ns 2.56us 40.96us 1794 * 0 1 2.56us 20.48us 327.7us 1795 * 1 0 5.12us 40.96us 655.4us 1796 * 1 1 10.24us 81.92us 1.31ms 1797 * 1798 * For the other 1799 * bit[1:0] \ speed 1000M 100M 10M 1800 * 0 0 5us 2.56us 40.96us 1801 * 0 1 40us 20.48us 327.7us 1802 * 1 0 80us 40.96us 655.4us 1803 * 1 1 160us 81.92us 1.31ms 1804 */ 1805 1806 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1807 struct rtl_coalesce_info { 1808 u32 speed; 1809 u32 scale_nsecs[4]; 1810 }; 1811 1812 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1813 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1814 1815 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1816 { SPEED_1000, COALESCE_DELAY(320) }, 1817 { SPEED_100, COALESCE_DELAY(2560) }, 1818 { SPEED_10, COALESCE_DELAY(40960) }, 1819 { 0 }, 1820 }; 1821 1822 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1823 { SPEED_1000, COALESCE_DELAY(5000) }, 1824 { SPEED_100, COALESCE_DELAY(2560) }, 1825 { SPEED_10, COALESCE_DELAY(40960) }, 1826 { 0 }, 1827 }; 1828 #undef COALESCE_DELAY 1829 1830 /* get rx/tx scale vector corresponding to current speed */ 1831 static const struct rtl_coalesce_info * 1832 rtl_coalesce_info(struct rtl8169_private *tp) 1833 { 1834 const struct rtl_coalesce_info *ci; 1835 1836 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1837 ci = rtl_coalesce_info_8169; 1838 else 1839 ci = rtl_coalesce_info_8168_8136; 1840 1841 /* if speed is unknown assume highest one */ 1842 if (tp->phydev->speed == SPEED_UNKNOWN) 1843 return ci; 1844 1845 for (; ci->speed; ci++) { 1846 if (tp->phydev->speed == ci->speed) 1847 return ci; 1848 } 1849 1850 return ERR_PTR(-ELNRNG); 1851 } 1852 1853 static int rtl_get_coalesce(struct net_device *dev, 1854 struct ethtool_coalesce *ec, 1855 struct kernel_ethtool_coalesce *kernel_coal, 1856 struct netlink_ext_ack *extack) 1857 { 1858 struct rtl8169_private *tp = netdev_priv(dev); 1859 const struct rtl_coalesce_info *ci; 1860 u32 scale, c_us, c_fr; 1861 u16 intrmit; 1862 1863 if (rtl_is_8125(tp)) 1864 return -EOPNOTSUPP; 1865 1866 memset(ec, 0, sizeof(*ec)); 1867 1868 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1869 ci = rtl_coalesce_info(tp); 1870 if (IS_ERR(ci)) 1871 return PTR_ERR(ci); 1872 1873 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1874 1875 intrmit = RTL_R16(tp, IntrMitigate); 1876 1877 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1878 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1879 1880 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1881 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1882 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1883 1884 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1885 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1886 1887 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1888 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1889 1890 return 0; 1891 } 1892 1893 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1894 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1895 u16 *cp01) 1896 { 1897 const struct rtl_coalesce_info *ci; 1898 u16 i; 1899 1900 ci = rtl_coalesce_info(tp); 1901 if (IS_ERR(ci)) 1902 return PTR_ERR(ci); 1903 1904 for (i = 0; i < 4; i++) { 1905 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1906 *cp01 = i; 1907 return ci->scale_nsecs[i]; 1908 } 1909 } 1910 1911 return -ERANGE; 1912 } 1913 1914 static int rtl_set_coalesce(struct net_device *dev, 1915 struct ethtool_coalesce *ec, 1916 struct kernel_ethtool_coalesce *kernel_coal, 1917 struct netlink_ext_ack *extack) 1918 { 1919 struct rtl8169_private *tp = netdev_priv(dev); 1920 u32 tx_fr = ec->tx_max_coalesced_frames; 1921 u32 rx_fr = ec->rx_max_coalesced_frames; 1922 u32 coal_usec_max, units; 1923 u16 w = 0, cp01 = 0; 1924 int scale; 1925 1926 if (rtl_is_8125(tp)) 1927 return -EOPNOTSUPP; 1928 1929 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1930 return -ERANGE; 1931 1932 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1933 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1934 if (scale < 0) 1935 return scale; 1936 1937 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1938 * not only when usecs=0 because of e.g. the following scenario: 1939 * 1940 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1941 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1942 * - then user does `ethtool -C eth0 rx-usecs 100` 1943 * 1944 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1945 * if we want to ignore rx_frames then it has to be set to 0. 1946 */ 1947 if (rx_fr == 1) 1948 rx_fr = 0; 1949 if (tx_fr == 1) 1950 tx_fr = 0; 1951 1952 /* HW requires time limit to be set if frame limit is set */ 1953 if ((tx_fr && !ec->tx_coalesce_usecs) || 1954 (rx_fr && !ec->rx_coalesce_usecs)) 1955 return -EINVAL; 1956 1957 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1958 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1959 1960 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1961 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1962 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1963 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1964 1965 RTL_W16(tp, IntrMitigate, w); 1966 1967 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1968 if (rtl_is_8168evl_up(tp)) { 1969 if (!rx_fr && !tx_fr) 1970 /* disable packet counter */ 1971 tp->cp_cmd |= PktCntrDisable; 1972 else 1973 tp->cp_cmd &= ~PktCntrDisable; 1974 } 1975 1976 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1977 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1978 rtl_pci_commit(tp); 1979 1980 return 0; 1981 } 1982 1983 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 1984 { 1985 struct rtl8169_private *tp = netdev_priv(dev); 1986 1987 if (!rtl_supports_eee(tp)) 1988 return -EOPNOTSUPP; 1989 1990 return phy_ethtool_get_eee(tp->phydev, data); 1991 } 1992 1993 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 1994 { 1995 struct rtl8169_private *tp = netdev_priv(dev); 1996 1997 if (!rtl_supports_eee(tp)) 1998 return -EOPNOTSUPP; 1999 2000 return phy_ethtool_set_eee(tp->phydev, data); 2001 } 2002 2003 static void rtl8169_get_ringparam(struct net_device *dev, 2004 struct ethtool_ringparam *data, 2005 struct kernel_ethtool_ringparam *kernel_data, 2006 struct netlink_ext_ack *extack) 2007 { 2008 data->rx_max_pending = NUM_RX_DESC; 2009 data->rx_pending = NUM_RX_DESC; 2010 data->tx_max_pending = NUM_TX_DESC; 2011 data->tx_pending = NUM_TX_DESC; 2012 } 2013 2014 static void rtl8169_get_pauseparam(struct net_device *dev, 2015 struct ethtool_pauseparam *data) 2016 { 2017 struct rtl8169_private *tp = netdev_priv(dev); 2018 bool tx_pause, rx_pause; 2019 2020 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2021 2022 data->autoneg = tp->phydev->autoneg; 2023 data->tx_pause = tx_pause ? 1 : 0; 2024 data->rx_pause = rx_pause ? 1 : 0; 2025 } 2026 2027 static int rtl8169_set_pauseparam(struct net_device *dev, 2028 struct ethtool_pauseparam *data) 2029 { 2030 struct rtl8169_private *tp = netdev_priv(dev); 2031 2032 if (dev->mtu > ETH_DATA_LEN) 2033 return -EOPNOTSUPP; 2034 2035 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2036 2037 return 0; 2038 } 2039 2040 static const struct ethtool_ops rtl8169_ethtool_ops = { 2041 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2042 ETHTOOL_COALESCE_MAX_FRAMES, 2043 .get_drvinfo = rtl8169_get_drvinfo, 2044 .get_regs_len = rtl8169_get_regs_len, 2045 .get_link = ethtool_op_get_link, 2046 .get_coalesce = rtl_get_coalesce, 2047 .set_coalesce = rtl_set_coalesce, 2048 .get_regs = rtl8169_get_regs, 2049 .get_wol = rtl8169_get_wol, 2050 .set_wol = rtl8169_set_wol, 2051 .get_strings = rtl8169_get_strings, 2052 .get_sset_count = rtl8169_get_sset_count, 2053 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2054 .get_ts_info = ethtool_op_get_ts_info, 2055 .nway_reset = phy_ethtool_nway_reset, 2056 .get_eee = rtl8169_get_eee, 2057 .set_eee = rtl8169_set_eee, 2058 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2059 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2060 .get_ringparam = rtl8169_get_ringparam, 2061 .get_pauseparam = rtl8169_get_pauseparam, 2062 .set_pauseparam = rtl8169_set_pauseparam, 2063 }; 2064 2065 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2066 { 2067 /* 2068 * The driver currently handles the 8168Bf and the 8168Be identically 2069 * but they can be identified more specifically through the test below 2070 * if needed: 2071 * 2072 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2073 * 2074 * Same thing for the 8101Eb and the 8101Ec: 2075 * 2076 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2077 */ 2078 static const struct rtl_mac_info { 2079 u16 mask; 2080 u16 val; 2081 enum mac_version ver; 2082 } mac_info[] = { 2083 /* 8126A family. */ 2084 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2085 2086 /* 8125B family. */ 2087 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2088 2089 /* 8125A family. */ 2090 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2091 /* It seems only XID 609 made it to the mass market. 2092 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2093 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2094 */ 2095 2096 /* RTL8117 */ 2097 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2098 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2099 2100 /* 8168EP family. */ 2101 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2102 /* It seems this chip version never made it to 2103 * the wild. Let's disable detection. 2104 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2105 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2106 */ 2107 2108 /* 8168H family. */ 2109 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2110 /* It seems this chip version never made it to 2111 * the wild. Let's disable detection. 2112 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2113 */ 2114 2115 /* 8168G family. */ 2116 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2117 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2118 /* It seems this chip version never made it to 2119 * the wild. Let's disable detection. 2120 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2121 */ 2122 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2123 2124 /* 8168F family. */ 2125 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2126 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2127 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2128 2129 /* 8168E family. */ 2130 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2131 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2132 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2133 2134 /* 8168D family. */ 2135 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2136 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2137 2138 /* 8168DP family. */ 2139 /* It seems this early RTL8168dp version never made it to 2140 * the wild. Support has been removed. 2141 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2142 */ 2143 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2144 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2145 2146 /* 8168C family. */ 2147 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2148 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2149 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2150 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2151 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2152 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2153 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2154 2155 /* 8168B family. */ 2156 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2157 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2158 2159 /* 8101 family. */ 2160 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2161 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2162 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2163 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2164 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2165 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2166 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2167 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2168 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2169 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2170 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2171 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2172 2173 /* 8110 family. */ 2174 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2175 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2176 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2177 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2178 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2179 2180 /* Catch-all */ 2181 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2182 }; 2183 const struct rtl_mac_info *p = mac_info; 2184 enum mac_version ver; 2185 2186 while ((xid & p->mask) != p->val) 2187 p++; 2188 ver = p->ver; 2189 2190 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2191 if (ver == RTL_GIGA_MAC_VER_42) 2192 ver = RTL_GIGA_MAC_VER_43; 2193 else if (ver == RTL_GIGA_MAC_VER_46) 2194 ver = RTL_GIGA_MAC_VER_48; 2195 } 2196 2197 return ver; 2198 } 2199 2200 static void rtl_release_firmware(struct rtl8169_private *tp) 2201 { 2202 if (tp->rtl_fw) { 2203 rtl_fw_release_firmware(tp->rtl_fw); 2204 kfree(tp->rtl_fw); 2205 tp->rtl_fw = NULL; 2206 } 2207 } 2208 2209 void r8169_apply_firmware(struct rtl8169_private *tp) 2210 { 2211 int val; 2212 2213 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2214 if (tp->rtl_fw) { 2215 rtl_fw_write_firmware(tp, tp->rtl_fw); 2216 /* At least one firmware doesn't reset tp->ocp_base. */ 2217 tp->ocp_base = OCP_STD_PHY_BASE; 2218 2219 /* PHY soft reset may still be in progress */ 2220 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2221 !(val & BMCR_RESET), 2222 50000, 600000, true); 2223 } 2224 } 2225 2226 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2227 { 2228 /* Adjust EEE LED frequency */ 2229 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2230 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2231 2232 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2233 } 2234 2235 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2236 { 2237 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2238 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2239 } 2240 2241 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2242 { 2243 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2244 } 2245 2246 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2247 { 2248 rtl8125_set_eee_txidle_timer(tp); 2249 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2250 } 2251 2252 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2253 { 2254 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2255 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2256 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2257 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2258 } 2259 2260 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2261 { 2262 u16 data1, data2, ioffset; 2263 2264 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2265 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2266 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2267 2268 ioffset = (data2 >> 1) & 0x7ff8; 2269 ioffset |= data2 & 0x0007; 2270 if (data1 & BIT(7)) 2271 ioffset |= BIT(15); 2272 2273 return ioffset; 2274 } 2275 2276 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2277 { 2278 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 2279 return; 2280 2281 set_bit(flag, tp->wk.flags); 2282 schedule_work(&tp->wk.work); 2283 } 2284 2285 static void rtl8169_init_phy(struct rtl8169_private *tp) 2286 { 2287 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2288 2289 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2290 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2291 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2292 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2293 RTL_W8(tp, 0x82, 0x01); 2294 } 2295 2296 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2297 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2298 tp->pci_dev->subsystem_device == 0xe000) 2299 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2300 2301 /* We may have called phy_speed_down before */ 2302 phy_speed_up(tp->phydev); 2303 2304 genphy_soft_reset(tp->phydev); 2305 } 2306 2307 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2308 { 2309 rtl_unlock_config_regs(tp); 2310 2311 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2312 rtl_pci_commit(tp); 2313 2314 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2315 rtl_pci_commit(tp); 2316 2317 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2318 rtl_rar_exgmac_set(tp, addr); 2319 2320 rtl_lock_config_regs(tp); 2321 } 2322 2323 static int rtl_set_mac_address(struct net_device *dev, void *p) 2324 { 2325 struct rtl8169_private *tp = netdev_priv(dev); 2326 int ret; 2327 2328 ret = eth_mac_addr(dev, p); 2329 if (ret) 2330 return ret; 2331 2332 rtl_rar_set(tp, dev->dev_addr); 2333 2334 return 0; 2335 } 2336 2337 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2338 { 2339 switch (tp->mac_version) { 2340 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2341 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2342 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2343 break; 2344 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2345 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2346 case RTL_GIGA_MAC_VER_38: 2347 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2348 break; 2349 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2350 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2351 break; 2352 case RTL_GIGA_MAC_VER_61: 2353 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2354 break; 2355 case RTL_GIGA_MAC_VER_63: 2356 case RTL_GIGA_MAC_VER_65: 2357 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2358 RX_PAUSE_SLOT_ON); 2359 break; 2360 default: 2361 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2362 break; 2363 } 2364 } 2365 2366 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2367 { 2368 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2369 } 2370 2371 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2372 { 2373 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2374 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2375 } 2376 2377 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2378 { 2379 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2380 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2381 } 2382 2383 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2384 { 2385 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2386 } 2387 2388 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2389 { 2390 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2391 } 2392 2393 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2394 { 2395 RTL_W8(tp, MaxTxPacketSize, 0x24); 2396 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2397 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2398 } 2399 2400 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2401 { 2402 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2403 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2404 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2405 } 2406 2407 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2408 { 2409 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2410 } 2411 2412 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2413 { 2414 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2415 } 2416 2417 static void rtl_jumbo_config(struct rtl8169_private *tp) 2418 { 2419 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2420 int readrq = 4096; 2421 2422 rtl_unlock_config_regs(tp); 2423 switch (tp->mac_version) { 2424 case RTL_GIGA_MAC_VER_17: 2425 if (jumbo) { 2426 readrq = 512; 2427 r8168b_1_hw_jumbo_enable(tp); 2428 } else { 2429 r8168b_1_hw_jumbo_disable(tp); 2430 } 2431 break; 2432 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2433 if (jumbo) { 2434 readrq = 512; 2435 r8168c_hw_jumbo_enable(tp); 2436 } else { 2437 r8168c_hw_jumbo_disable(tp); 2438 } 2439 break; 2440 case RTL_GIGA_MAC_VER_28: 2441 if (jumbo) 2442 r8168dp_hw_jumbo_enable(tp); 2443 else 2444 r8168dp_hw_jumbo_disable(tp); 2445 break; 2446 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2447 if (jumbo) 2448 r8168e_hw_jumbo_enable(tp); 2449 else 2450 r8168e_hw_jumbo_disable(tp); 2451 break; 2452 default: 2453 break; 2454 } 2455 rtl_lock_config_regs(tp); 2456 2457 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2458 pcie_set_readrq(tp->pci_dev, readrq); 2459 2460 /* Chip doesn't support pause in jumbo mode */ 2461 if (jumbo) { 2462 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2463 tp->phydev->advertising); 2464 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2465 tp->phydev->advertising); 2466 phy_start_aneg(tp->phydev); 2467 } 2468 } 2469 2470 DECLARE_RTL_COND(rtl_chipcmd_cond) 2471 { 2472 return RTL_R8(tp, ChipCmd) & CmdReset; 2473 } 2474 2475 static void rtl_hw_reset(struct rtl8169_private *tp) 2476 { 2477 RTL_W8(tp, ChipCmd, CmdReset); 2478 2479 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2480 } 2481 2482 static void rtl_request_firmware(struct rtl8169_private *tp) 2483 { 2484 struct rtl_fw *rtl_fw; 2485 2486 /* firmware loaded already or no firmware available */ 2487 if (tp->rtl_fw || !tp->fw_name) 2488 return; 2489 2490 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2491 if (!rtl_fw) 2492 return; 2493 2494 rtl_fw->phy_write = rtl_writephy; 2495 rtl_fw->phy_read = rtl_readphy; 2496 rtl_fw->mac_mcu_write = mac_mcu_write; 2497 rtl_fw->mac_mcu_read = mac_mcu_read; 2498 rtl_fw->fw_name = tp->fw_name; 2499 rtl_fw->dev = tp_to_dev(tp); 2500 2501 if (rtl_fw_request_firmware(rtl_fw)) 2502 kfree(rtl_fw); 2503 else 2504 tp->rtl_fw = rtl_fw; 2505 } 2506 2507 static void rtl_rx_close(struct rtl8169_private *tp) 2508 { 2509 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2510 } 2511 2512 DECLARE_RTL_COND(rtl_npq_cond) 2513 { 2514 return RTL_R8(tp, TxPoll) & NPQ; 2515 } 2516 2517 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2518 { 2519 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2520 } 2521 2522 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2523 { 2524 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2525 } 2526 2527 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2528 { 2529 /* IntrMitigate has new functionality on RTL8125 */ 2530 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2531 } 2532 2533 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2534 { 2535 switch (tp->mac_version) { 2536 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2537 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2538 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2539 break; 2540 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2541 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2542 break; 2543 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_65: 2544 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2545 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2546 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2547 break; 2548 default: 2549 break; 2550 } 2551 } 2552 2553 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2554 { 2555 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2556 } 2557 2558 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2559 { 2560 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2561 fsleep(2000); 2562 rtl_wait_txrx_fifo_empty(tp); 2563 } 2564 2565 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2566 { 2567 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2568 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2569 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2570 2571 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2572 rtl_disable_rxdvgate(tp); 2573 } 2574 2575 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2576 { 2577 if (tp->dash_enabled) 2578 return; 2579 2580 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2581 tp->mac_version == RTL_GIGA_MAC_VER_33) 2582 rtl_ephy_write(tp, 0x19, 0xff64); 2583 2584 if (device_may_wakeup(tp_to_dev(tp))) { 2585 phy_speed_down(tp->phydev, false); 2586 rtl_wol_enable_rx(tp); 2587 } 2588 } 2589 2590 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2591 { 2592 u32 val = TX_DMA_BURST << TxDMAShift | 2593 InterFrameGap << TxInterFrameGapShift; 2594 2595 if (rtl_is_8168evl_up(tp)) 2596 val |= TXCFG_AUTO_FIFO; 2597 2598 RTL_W32(tp, TxConfig, val); 2599 } 2600 2601 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2602 { 2603 /* Low hurts. Let's disable the filtering. */ 2604 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2605 } 2606 2607 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2608 { 2609 /* 2610 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2611 * register to be written before TxDescAddrLow to work. 2612 * Switching from MMIO to I/O access fixes the issue as well. 2613 */ 2614 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2615 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2616 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2617 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2618 } 2619 2620 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2621 { 2622 u32 val; 2623 2624 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2625 val = 0x000fff00; 2626 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2627 val = 0x00ffff00; 2628 else 2629 return; 2630 2631 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2632 val |= 0xff; 2633 2634 RTL_W32(tp, 0x7c, val); 2635 } 2636 2637 static void rtl_set_rx_mode(struct net_device *dev) 2638 { 2639 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2640 /* Multicast hash filter */ 2641 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2642 struct rtl8169_private *tp = netdev_priv(dev); 2643 u32 tmp; 2644 2645 if (dev->flags & IFF_PROMISC) { 2646 rx_mode |= AcceptAllPhys; 2647 } else if (!(dev->flags & IFF_MULTICAST)) { 2648 rx_mode &= ~AcceptMulticast; 2649 } else if (dev->flags & IFF_ALLMULTI || 2650 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2651 /* accept all multicasts */ 2652 } else if (netdev_mc_empty(dev)) { 2653 rx_mode &= ~AcceptMulticast; 2654 } else { 2655 struct netdev_hw_addr *ha; 2656 2657 mc_filter[1] = mc_filter[0] = 0; 2658 netdev_for_each_mc_addr(ha, dev) { 2659 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2660 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2661 } 2662 2663 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2664 tmp = mc_filter[0]; 2665 mc_filter[0] = swab32(mc_filter[1]); 2666 mc_filter[1] = swab32(tmp); 2667 } 2668 } 2669 2670 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2671 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2672 2673 tmp = RTL_R32(tp, RxConfig); 2674 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2675 } 2676 2677 DECLARE_RTL_COND(rtl_csiar_cond) 2678 { 2679 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2680 } 2681 2682 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2683 { 2684 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2685 2686 RTL_W32(tp, CSIDR, value); 2687 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2688 CSIAR_BYTE_ENABLE | func << 16); 2689 2690 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2691 } 2692 2693 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2694 { 2695 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2696 2697 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2698 CSIAR_BYTE_ENABLE); 2699 2700 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2701 RTL_R32(tp, CSIDR) : ~0; 2702 } 2703 2704 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2705 { 2706 struct pci_dev *pdev = tp->pci_dev; 2707 u32 csi; 2708 2709 /* According to Realtek the value at config space address 0x070f 2710 * controls the L0s/L1 entrance latency. We try standard ECAM access 2711 * first and if it fails fall back to CSI. 2712 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2713 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2714 */ 2715 if (pdev->cfg_size > 0x070f && 2716 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2717 return; 2718 2719 netdev_notice_once(tp->dev, 2720 "No native access to PCI extended config space, falling back to CSI\n"); 2721 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2722 rtl_csi_write(tp, 0x070c, csi | val << 24); 2723 } 2724 2725 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2726 { 2727 /* L0 7us, L1 16us */ 2728 rtl_set_aspm_entry_latency(tp, 0x27); 2729 } 2730 2731 struct ephy_info { 2732 unsigned int offset; 2733 u16 mask; 2734 u16 bits; 2735 }; 2736 2737 static void __rtl_ephy_init(struct rtl8169_private *tp, 2738 const struct ephy_info *e, int len) 2739 { 2740 u16 w; 2741 2742 while (len-- > 0) { 2743 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2744 rtl_ephy_write(tp, e->offset, w); 2745 e++; 2746 } 2747 } 2748 2749 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2750 2751 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2752 { 2753 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2754 PCI_EXP_LNKCTL_CLKREQ_EN); 2755 } 2756 2757 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2758 { 2759 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2760 PCI_EXP_LNKCTL_CLKREQ_EN); 2761 } 2762 2763 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2764 { 2765 /* work around an issue when PCI reset occurs during L2/L3 state */ 2766 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2767 } 2768 2769 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2770 { 2771 /* Bits control which events trigger ASPM L1 exit: 2772 * Bit 12: rxdv 2773 * Bit 11: ltr_msg 2774 * Bit 10: txdma_poll 2775 * Bit 9: xadm 2776 * Bit 8: pktavi 2777 * Bit 7: txpla 2778 */ 2779 switch (tp->mac_version) { 2780 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2781 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2782 break; 2783 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2784 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2785 break; 2786 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 2787 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2788 break; 2789 default: 2790 break; 2791 } 2792 } 2793 2794 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2795 { 2796 switch (tp->mac_version) { 2797 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2798 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2799 break; 2800 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 2801 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2802 break; 2803 default: 2804 break; 2805 } 2806 } 2807 2808 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2809 { 2810 u8 val8; 2811 2812 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2813 return; 2814 2815 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2816 if (enable && tp->aspm_manageable) { 2817 /* On these chip versions ASPM can even harm 2818 * bus communication of other PCI devices. 2819 */ 2820 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2821 tp->mac_version == RTL_GIGA_MAC_VER_43) 2822 return; 2823 2824 rtl_mod_config5(tp, 0, ASPM_en); 2825 switch (tp->mac_version) { 2826 case RTL_GIGA_MAC_VER_65: 2827 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2828 RTL_W8(tp, INT_CFG0_8125, val8); 2829 break; 2830 default: 2831 rtl_mod_config2(tp, 0, ClkReqEn); 2832 break; 2833 } 2834 2835 switch (tp->mac_version) { 2836 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2837 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 2838 /* reset ephy tx/rx disable timer */ 2839 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2840 /* chip can trigger L1.2 */ 2841 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2842 break; 2843 default: 2844 break; 2845 } 2846 } else { 2847 switch (tp->mac_version) { 2848 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2849 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 2850 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2851 break; 2852 default: 2853 break; 2854 } 2855 2856 switch (tp->mac_version) { 2857 case RTL_GIGA_MAC_VER_65: 2858 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2859 RTL_W8(tp, INT_CFG0_8125, val8); 2860 break; 2861 default: 2862 rtl_mod_config2(tp, ClkReqEn, 0); 2863 break; 2864 } 2865 rtl_mod_config5(tp, ASPM_en, 0); 2866 } 2867 } 2868 2869 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2870 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2871 { 2872 /* Usage of dynamic vs. static FIFO is controlled by bit 2873 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2874 */ 2875 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2876 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2877 } 2878 2879 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2880 u8 low, u8 high) 2881 { 2882 /* FIFO thresholds for pause flow control */ 2883 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2884 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2885 } 2886 2887 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2888 { 2889 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2890 } 2891 2892 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2893 { 2894 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2895 2896 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2897 2898 rtl_disable_clock_request(tp); 2899 } 2900 2901 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2902 { 2903 static const struct ephy_info e_info_8168cp[] = { 2904 { 0x01, 0, 0x0001 }, 2905 { 0x02, 0x0800, 0x1000 }, 2906 { 0x03, 0, 0x0042 }, 2907 { 0x06, 0x0080, 0x0000 }, 2908 { 0x07, 0, 0x2000 } 2909 }; 2910 2911 rtl_set_def_aspm_entry_latency(tp); 2912 2913 rtl_ephy_init(tp, e_info_8168cp); 2914 2915 __rtl_hw_start_8168cp(tp); 2916 } 2917 2918 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2919 { 2920 rtl_set_def_aspm_entry_latency(tp); 2921 2922 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2923 } 2924 2925 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2926 { 2927 rtl_set_def_aspm_entry_latency(tp); 2928 2929 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2930 2931 /* Magic. */ 2932 RTL_W8(tp, DBG_REG, 0x20); 2933 } 2934 2935 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2936 { 2937 static const struct ephy_info e_info_8168c_1[] = { 2938 { 0x02, 0x0800, 0x1000 }, 2939 { 0x03, 0, 0x0002 }, 2940 { 0x06, 0x0080, 0x0000 } 2941 }; 2942 2943 rtl_set_def_aspm_entry_latency(tp); 2944 2945 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2946 2947 rtl_ephy_init(tp, e_info_8168c_1); 2948 2949 __rtl_hw_start_8168cp(tp); 2950 } 2951 2952 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2953 { 2954 static const struct ephy_info e_info_8168c_2[] = { 2955 { 0x01, 0, 0x0001 }, 2956 { 0x03, 0x0400, 0x0020 } 2957 }; 2958 2959 rtl_set_def_aspm_entry_latency(tp); 2960 2961 rtl_ephy_init(tp, e_info_8168c_2); 2962 2963 __rtl_hw_start_8168cp(tp); 2964 } 2965 2966 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2967 { 2968 rtl_set_def_aspm_entry_latency(tp); 2969 2970 __rtl_hw_start_8168cp(tp); 2971 } 2972 2973 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2974 { 2975 rtl_set_def_aspm_entry_latency(tp); 2976 2977 rtl_disable_clock_request(tp); 2978 } 2979 2980 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2981 { 2982 static const struct ephy_info e_info_8168d_4[] = { 2983 { 0x0b, 0x0000, 0x0048 }, 2984 { 0x19, 0x0020, 0x0050 }, 2985 { 0x0c, 0x0100, 0x0020 }, 2986 { 0x10, 0x0004, 0x0000 }, 2987 }; 2988 2989 rtl_set_def_aspm_entry_latency(tp); 2990 2991 rtl_ephy_init(tp, e_info_8168d_4); 2992 2993 rtl_enable_clock_request(tp); 2994 } 2995 2996 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2997 { 2998 static const struct ephy_info e_info_8168e_1[] = { 2999 { 0x00, 0x0200, 0x0100 }, 3000 { 0x00, 0x0000, 0x0004 }, 3001 { 0x06, 0x0002, 0x0001 }, 3002 { 0x06, 0x0000, 0x0030 }, 3003 { 0x07, 0x0000, 0x2000 }, 3004 { 0x00, 0x0000, 0x0020 }, 3005 { 0x03, 0x5800, 0x2000 }, 3006 { 0x03, 0x0000, 0x0001 }, 3007 { 0x01, 0x0800, 0x1000 }, 3008 { 0x07, 0x0000, 0x4000 }, 3009 { 0x1e, 0x0000, 0x2000 }, 3010 { 0x19, 0xffff, 0xfe6c }, 3011 { 0x0a, 0x0000, 0x0040 } 3012 }; 3013 3014 rtl_set_def_aspm_entry_latency(tp); 3015 3016 rtl_ephy_init(tp, e_info_8168e_1); 3017 3018 rtl_disable_clock_request(tp); 3019 3020 /* Reset tx FIFO pointer */ 3021 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3022 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3023 3024 rtl_mod_config5(tp, Spi_en, 0); 3025 } 3026 3027 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3028 { 3029 static const struct ephy_info e_info_8168e_2[] = { 3030 { 0x09, 0x0000, 0x0080 }, 3031 { 0x19, 0x0000, 0x0224 }, 3032 { 0x00, 0x0000, 0x0004 }, 3033 { 0x0c, 0x3df0, 0x0200 }, 3034 }; 3035 3036 rtl_set_def_aspm_entry_latency(tp); 3037 3038 rtl_ephy_init(tp, e_info_8168e_2); 3039 3040 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3041 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3042 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3043 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3044 rtl_reset_packet_filter(tp); 3045 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3046 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3047 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3048 3049 rtl_disable_clock_request(tp); 3050 3051 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3052 3053 rtl8168_config_eee_mac(tp); 3054 3055 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3056 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3057 rtl_mod_config5(tp, Spi_en, 0); 3058 } 3059 3060 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3061 { 3062 rtl_set_def_aspm_entry_latency(tp); 3063 3064 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3065 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3066 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3067 rtl_reset_packet_filter(tp); 3068 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3069 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3070 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3071 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3072 3073 rtl_disable_clock_request(tp); 3074 3075 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3076 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3077 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3078 rtl_mod_config5(tp, Spi_en, 0); 3079 3080 rtl8168_config_eee_mac(tp); 3081 } 3082 3083 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3084 { 3085 static const struct ephy_info e_info_8168f_1[] = { 3086 { 0x06, 0x00c0, 0x0020 }, 3087 { 0x08, 0x0001, 0x0002 }, 3088 { 0x09, 0x0000, 0x0080 }, 3089 { 0x19, 0x0000, 0x0224 }, 3090 { 0x00, 0x0000, 0x0008 }, 3091 { 0x0c, 0x3df0, 0x0200 }, 3092 }; 3093 3094 rtl_hw_start_8168f(tp); 3095 3096 rtl_ephy_init(tp, e_info_8168f_1); 3097 } 3098 3099 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3100 { 3101 static const struct ephy_info e_info_8168f_1[] = { 3102 { 0x06, 0x00c0, 0x0020 }, 3103 { 0x0f, 0xffff, 0x5200 }, 3104 { 0x19, 0x0000, 0x0224 }, 3105 { 0x00, 0x0000, 0x0008 }, 3106 { 0x0c, 0x3df0, 0x0200 }, 3107 }; 3108 3109 rtl_hw_start_8168f(tp); 3110 rtl_pcie_state_l2l3_disable(tp); 3111 3112 rtl_ephy_init(tp, e_info_8168f_1); 3113 } 3114 3115 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3116 { 3117 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3118 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3119 3120 rtl_set_def_aspm_entry_latency(tp); 3121 3122 rtl_reset_packet_filter(tp); 3123 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3124 3125 rtl_disable_rxdvgate(tp); 3126 3127 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3128 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3129 3130 rtl8168_config_eee_mac(tp); 3131 3132 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3133 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3134 3135 rtl_pcie_state_l2l3_disable(tp); 3136 } 3137 3138 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3139 { 3140 static const struct ephy_info e_info_8168g_1[] = { 3141 { 0x00, 0x0008, 0x0000 }, 3142 { 0x0c, 0x3ff0, 0x0820 }, 3143 { 0x1e, 0x0000, 0x0001 }, 3144 { 0x19, 0x8000, 0x0000 } 3145 }; 3146 3147 rtl_hw_start_8168g(tp); 3148 rtl_ephy_init(tp, e_info_8168g_1); 3149 } 3150 3151 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3152 { 3153 static const struct ephy_info e_info_8168g_2[] = { 3154 { 0x00, 0x0008, 0x0000 }, 3155 { 0x0c, 0x3ff0, 0x0820 }, 3156 { 0x19, 0xffff, 0x7c00 }, 3157 { 0x1e, 0xffff, 0x20eb }, 3158 { 0x0d, 0xffff, 0x1666 }, 3159 { 0x00, 0xffff, 0x10a3 }, 3160 { 0x06, 0xffff, 0xf050 }, 3161 { 0x04, 0x0000, 0x0010 }, 3162 { 0x1d, 0x4000, 0x0000 }, 3163 }; 3164 3165 rtl_hw_start_8168g(tp); 3166 rtl_ephy_init(tp, e_info_8168g_2); 3167 } 3168 3169 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3170 { 3171 static const u16 fix_data[] = { 3172 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3173 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3174 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3175 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3176 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3177 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3178 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3179 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3180 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3181 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3182 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3183 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3184 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3185 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3186 }; 3187 unsigned long flags; 3188 int i; 3189 3190 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3191 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3192 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3193 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3194 } 3195 3196 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3197 { 3198 static const struct ephy_info e_info_8411_2[] = { 3199 { 0x00, 0x0008, 0x0000 }, 3200 { 0x0c, 0x37d0, 0x0820 }, 3201 { 0x1e, 0x0000, 0x0001 }, 3202 { 0x19, 0x8021, 0x0000 }, 3203 { 0x1e, 0x0000, 0x2000 }, 3204 { 0x0d, 0x0100, 0x0200 }, 3205 { 0x00, 0x0000, 0x0080 }, 3206 { 0x06, 0x0000, 0x0010 }, 3207 { 0x04, 0x0000, 0x0010 }, 3208 { 0x1d, 0x0000, 0x4000 }, 3209 }; 3210 3211 rtl_hw_start_8168g(tp); 3212 3213 rtl_ephy_init(tp, e_info_8411_2); 3214 3215 /* The following Realtek-provided magic fixes an issue with the RX unit 3216 * getting confused after the PHY having been powered-down. 3217 */ 3218 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3219 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3220 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3221 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3222 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3223 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3224 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3225 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3226 mdelay(3); 3227 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3228 3229 rtl8411b_fix_phy_down(tp); 3230 3231 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3232 3233 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3234 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3235 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3236 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3237 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3238 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3239 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3240 } 3241 3242 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3243 { 3244 static const struct ephy_info e_info_8168h_1[] = { 3245 { 0x1e, 0x0800, 0x0001 }, 3246 { 0x1d, 0x0000, 0x0800 }, 3247 { 0x05, 0xffff, 0x2089 }, 3248 { 0x06, 0xffff, 0x5881 }, 3249 { 0x04, 0xffff, 0x854a }, 3250 { 0x01, 0xffff, 0x068b } 3251 }; 3252 int rg_saw_cnt; 3253 3254 rtl_ephy_init(tp, e_info_8168h_1); 3255 3256 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3257 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3258 3259 rtl_set_def_aspm_entry_latency(tp); 3260 3261 rtl_reset_packet_filter(tp); 3262 3263 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3264 3265 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3266 3267 rtl_disable_rxdvgate(tp); 3268 3269 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3270 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3271 3272 rtl8168_config_eee_mac(tp); 3273 3274 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3275 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3276 3277 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3278 3279 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3280 3281 rtl_pcie_state_l2l3_disable(tp); 3282 3283 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3284 if (rg_saw_cnt > 0) { 3285 u16 sw_cnt_1ms_ini; 3286 3287 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3288 sw_cnt_1ms_ini &= 0x0fff; 3289 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3290 } 3291 3292 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3293 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3294 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3295 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3296 3297 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3298 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3299 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3300 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3301 } 3302 3303 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3304 { 3305 rtl8168ep_stop_cmac(tp); 3306 3307 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3308 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3309 3310 rtl_set_def_aspm_entry_latency(tp); 3311 3312 rtl_reset_packet_filter(tp); 3313 3314 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3315 3316 rtl_disable_rxdvgate(tp); 3317 3318 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3319 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3320 3321 rtl8168_config_eee_mac(tp); 3322 3323 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3324 3325 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3326 3327 rtl_pcie_state_l2l3_disable(tp); 3328 } 3329 3330 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3331 { 3332 static const struct ephy_info e_info_8168ep_3[] = { 3333 { 0x00, 0x0000, 0x0080 }, 3334 { 0x0d, 0x0100, 0x0200 }, 3335 { 0x19, 0x8021, 0x0000 }, 3336 { 0x1e, 0x0000, 0x2000 }, 3337 }; 3338 3339 rtl_ephy_init(tp, e_info_8168ep_3); 3340 3341 rtl_hw_start_8168ep(tp); 3342 3343 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3344 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3345 3346 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3347 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3348 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3349 } 3350 3351 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3352 { 3353 static const struct ephy_info e_info_8117[] = { 3354 { 0x19, 0x0040, 0x1100 }, 3355 { 0x59, 0x0040, 0x1100 }, 3356 }; 3357 int rg_saw_cnt; 3358 3359 rtl8168ep_stop_cmac(tp); 3360 rtl_ephy_init(tp, e_info_8117); 3361 3362 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3363 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3364 3365 rtl_set_def_aspm_entry_latency(tp); 3366 3367 rtl_reset_packet_filter(tp); 3368 3369 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3370 3371 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3372 3373 rtl_disable_rxdvgate(tp); 3374 3375 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3376 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3377 3378 rtl8168_config_eee_mac(tp); 3379 3380 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3381 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3382 3383 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3384 3385 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3386 3387 rtl_pcie_state_l2l3_disable(tp); 3388 3389 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3390 if (rg_saw_cnt > 0) { 3391 u16 sw_cnt_1ms_ini; 3392 3393 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3394 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3395 } 3396 3397 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3398 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3399 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3400 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3401 3402 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3403 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3404 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3405 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3406 3407 /* firmware is for MAC only */ 3408 r8169_apply_firmware(tp); 3409 } 3410 3411 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3412 { 3413 static const struct ephy_info e_info_8102e_1[] = { 3414 { 0x01, 0, 0x6e65 }, 3415 { 0x02, 0, 0x091f }, 3416 { 0x03, 0, 0xc2f9 }, 3417 { 0x06, 0, 0xafb5 }, 3418 { 0x07, 0, 0x0e00 }, 3419 { 0x19, 0, 0xec80 }, 3420 { 0x01, 0, 0x2e65 }, 3421 { 0x01, 0, 0x6e65 } 3422 }; 3423 u8 cfg1; 3424 3425 rtl_set_def_aspm_entry_latency(tp); 3426 3427 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3428 3429 RTL_W8(tp, Config1, 3430 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3431 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3432 3433 cfg1 = RTL_R8(tp, Config1); 3434 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3435 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3436 3437 rtl_ephy_init(tp, e_info_8102e_1); 3438 } 3439 3440 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3441 { 3442 rtl_set_def_aspm_entry_latency(tp); 3443 3444 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3445 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3446 } 3447 3448 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3449 { 3450 rtl_hw_start_8102e_2(tp); 3451 3452 rtl_ephy_write(tp, 0x03, 0xc2f9); 3453 } 3454 3455 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3456 { 3457 static const struct ephy_info e_info_8401[] = { 3458 { 0x01, 0xffff, 0x6fe5 }, 3459 { 0x03, 0xffff, 0x0599 }, 3460 { 0x06, 0xffff, 0xaf25 }, 3461 { 0x07, 0xffff, 0x8e68 }, 3462 }; 3463 3464 rtl_ephy_init(tp, e_info_8401); 3465 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3466 } 3467 3468 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3469 { 3470 static const struct ephy_info e_info_8105e_1[] = { 3471 { 0x07, 0, 0x4000 }, 3472 { 0x19, 0, 0x0200 }, 3473 { 0x19, 0, 0x0020 }, 3474 { 0x1e, 0, 0x2000 }, 3475 { 0x03, 0, 0x0001 }, 3476 { 0x19, 0, 0x0100 }, 3477 { 0x19, 0, 0x0004 }, 3478 { 0x0a, 0, 0x0020 } 3479 }; 3480 3481 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3482 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3483 3484 /* Disable Early Tally Counter */ 3485 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3486 3487 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3488 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3489 3490 rtl_ephy_init(tp, e_info_8105e_1); 3491 3492 rtl_pcie_state_l2l3_disable(tp); 3493 } 3494 3495 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3496 { 3497 rtl_hw_start_8105e_1(tp); 3498 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3499 } 3500 3501 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3502 { 3503 static const struct ephy_info e_info_8402[] = { 3504 { 0x19, 0xffff, 0xff64 }, 3505 { 0x1e, 0, 0x4000 } 3506 }; 3507 3508 rtl_set_def_aspm_entry_latency(tp); 3509 3510 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3511 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3512 3513 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3514 3515 rtl_ephy_init(tp, e_info_8402); 3516 3517 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3518 rtl_reset_packet_filter(tp); 3519 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3520 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3521 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3522 3523 /* disable EEE */ 3524 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3525 3526 rtl_pcie_state_l2l3_disable(tp); 3527 } 3528 3529 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3530 { 3531 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3532 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3533 3534 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3535 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3536 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3537 3538 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3539 rtl_set_aspm_entry_latency(tp, 0x2f); 3540 3541 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3542 3543 /* disable EEE */ 3544 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3545 3546 rtl_pcie_state_l2l3_disable(tp); 3547 } 3548 3549 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3550 { 3551 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3552 } 3553 3554 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3555 { 3556 rtl_pcie_state_l2l3_disable(tp); 3557 3558 RTL_W16(tp, 0x382, 0x221b); 3559 RTL_W8(tp, 0x4500, 0); 3560 RTL_W16(tp, 0x4800, 0); 3561 3562 /* disable UPS */ 3563 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3564 3565 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3566 3567 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3568 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3569 3570 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3571 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3572 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3573 3574 /* disable new tx descriptor format */ 3575 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3576 3577 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3578 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3579 3580 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3581 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3582 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3583 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3584 else 3585 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3586 3587 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3588 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3589 else 3590 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3591 3592 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3593 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3594 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3595 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3596 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3597 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3598 if (tp->mac_version == RTL_GIGA_MAC_VER_65) 3599 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3600 else 3601 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3602 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3603 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3604 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3605 3606 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3607 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3608 udelay(1); 3609 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3610 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3611 3612 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3613 3614 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3615 3616 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3617 rtl8125a_config_eee_mac(tp); 3618 else 3619 rtl8125b_config_eee_mac(tp); 3620 3621 rtl_disable_rxdvgate(tp); 3622 } 3623 3624 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3625 { 3626 static const struct ephy_info e_info_8125a_2[] = { 3627 { 0x04, 0xffff, 0xd000 }, 3628 { 0x0a, 0xffff, 0x8653 }, 3629 { 0x23, 0xffff, 0xab66 }, 3630 { 0x20, 0xffff, 0x9455 }, 3631 { 0x21, 0xffff, 0x99ff }, 3632 { 0x29, 0xffff, 0xfe04 }, 3633 3634 { 0x44, 0xffff, 0xd000 }, 3635 { 0x4a, 0xffff, 0x8653 }, 3636 { 0x63, 0xffff, 0xab66 }, 3637 { 0x60, 0xffff, 0x9455 }, 3638 { 0x61, 0xffff, 0x99ff }, 3639 { 0x69, 0xffff, 0xfe04 }, 3640 }; 3641 3642 rtl_set_def_aspm_entry_latency(tp); 3643 rtl_ephy_init(tp, e_info_8125a_2); 3644 rtl_hw_start_8125_common(tp); 3645 } 3646 3647 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3648 { 3649 static const struct ephy_info e_info_8125b[] = { 3650 { 0x0b, 0xffff, 0xa908 }, 3651 { 0x1e, 0xffff, 0x20eb }, 3652 { 0x4b, 0xffff, 0xa908 }, 3653 { 0x5e, 0xffff, 0x20eb }, 3654 { 0x22, 0x0030, 0x0020 }, 3655 { 0x62, 0x0030, 0x0020 }, 3656 }; 3657 3658 rtl_set_def_aspm_entry_latency(tp); 3659 rtl_ephy_init(tp, e_info_8125b); 3660 rtl_hw_start_8125_common(tp); 3661 } 3662 3663 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3664 { 3665 rtl_set_def_aspm_entry_latency(tp); 3666 rtl_hw_start_8125_common(tp); 3667 } 3668 3669 static void rtl_hw_config(struct rtl8169_private *tp) 3670 { 3671 static const rtl_generic_fct hw_configs[] = { 3672 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3673 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3674 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3675 [RTL_GIGA_MAC_VER_10] = NULL, 3676 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3677 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3678 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3679 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3680 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3681 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3682 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3683 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3684 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3685 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3686 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3687 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3688 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3689 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3690 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3691 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3692 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3693 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3694 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3695 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3696 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3697 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3698 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3699 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3700 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3701 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3702 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3703 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3704 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3705 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3706 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3707 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3708 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3709 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3710 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3711 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3712 }; 3713 3714 if (hw_configs[tp->mac_version]) 3715 hw_configs[tp->mac_version](tp); 3716 } 3717 3718 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3719 { 3720 int i; 3721 3722 RTL_W8(tp, INT_CFG0_8125, 0x00); 3723 3724 /* disable interrupt coalescing */ 3725 switch (tp->mac_version) { 3726 case RTL_GIGA_MAC_VER_61: 3727 for (i = 0xa00; i < 0xb00; i += 4) 3728 RTL_W32(tp, i, 0); 3729 break; 3730 case RTL_GIGA_MAC_VER_63: 3731 case RTL_GIGA_MAC_VER_65: 3732 for (i = 0xa00; i < 0xa80; i += 4) 3733 RTL_W32(tp, i, 0); 3734 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3735 break; 3736 default: 3737 break; 3738 } 3739 3740 rtl_hw_config(tp); 3741 } 3742 3743 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3744 { 3745 if (rtl_is_8168evl_up(tp)) 3746 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3747 else 3748 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3749 3750 rtl_hw_config(tp); 3751 3752 /* disable interrupt coalescing */ 3753 RTL_W16(tp, IntrMitigate, 0x0000); 3754 } 3755 3756 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3757 { 3758 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3759 3760 tp->cp_cmd |= PCIMulRW; 3761 3762 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3763 tp->mac_version == RTL_GIGA_MAC_VER_03) 3764 tp->cp_cmd |= EnAnaPLL; 3765 3766 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3767 3768 rtl8169_set_magic_reg(tp); 3769 3770 /* disable interrupt coalescing */ 3771 RTL_W16(tp, IntrMitigate, 0x0000); 3772 } 3773 3774 static void rtl_hw_start(struct rtl8169_private *tp) 3775 { 3776 rtl_unlock_config_regs(tp); 3777 /* disable aspm and clock request before ephy access */ 3778 rtl_hw_aspm_clkreq_enable(tp, false); 3779 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3780 3781 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3782 rtl_hw_start_8169(tp); 3783 else if (rtl_is_8125(tp)) 3784 rtl_hw_start_8125(tp); 3785 else 3786 rtl_hw_start_8168(tp); 3787 3788 rtl_enable_exit_l1(tp); 3789 rtl_hw_aspm_clkreq_enable(tp, true); 3790 rtl_set_rx_max_size(tp); 3791 rtl_set_rx_tx_desc_registers(tp); 3792 rtl_lock_config_regs(tp); 3793 3794 rtl_jumbo_config(tp); 3795 3796 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3797 rtl_pci_commit(tp); 3798 3799 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3800 rtl_init_rxcfg(tp); 3801 rtl_set_tx_config_registers(tp); 3802 rtl_set_rx_config_features(tp, tp->dev->features); 3803 rtl_set_rx_mode(tp->dev); 3804 rtl_irq_enable(tp); 3805 } 3806 3807 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3808 { 3809 struct rtl8169_private *tp = netdev_priv(dev); 3810 3811 dev->mtu = new_mtu; 3812 netdev_update_features(dev); 3813 rtl_jumbo_config(tp); 3814 3815 switch (tp->mac_version) { 3816 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 3817 rtl8125_set_eee_txidle_timer(tp); 3818 break; 3819 default: 3820 break; 3821 } 3822 3823 return 0; 3824 } 3825 3826 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3827 { 3828 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3829 3830 desc->opts2 = 0; 3831 /* Force memory writes to complete before releasing descriptor */ 3832 dma_wmb(); 3833 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3834 } 3835 3836 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3837 struct RxDesc *desc) 3838 { 3839 struct device *d = tp_to_dev(tp); 3840 int node = dev_to_node(d); 3841 dma_addr_t mapping; 3842 struct page *data; 3843 3844 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3845 if (!data) 3846 return NULL; 3847 3848 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3849 if (unlikely(dma_mapping_error(d, mapping))) { 3850 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3851 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3852 return NULL; 3853 } 3854 3855 desc->addr = cpu_to_le64(mapping); 3856 rtl8169_mark_to_asic(desc); 3857 3858 return data; 3859 } 3860 3861 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3862 { 3863 int i; 3864 3865 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3866 dma_unmap_page(tp_to_dev(tp), 3867 le64_to_cpu(tp->RxDescArray[i].addr), 3868 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3869 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3870 tp->Rx_databuff[i] = NULL; 3871 tp->RxDescArray[i].addr = 0; 3872 tp->RxDescArray[i].opts1 = 0; 3873 } 3874 } 3875 3876 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3877 { 3878 int i; 3879 3880 for (i = 0; i < NUM_RX_DESC; i++) { 3881 struct page *data; 3882 3883 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3884 if (!data) { 3885 rtl8169_rx_clear(tp); 3886 return -ENOMEM; 3887 } 3888 tp->Rx_databuff[i] = data; 3889 } 3890 3891 /* mark as last descriptor in the ring */ 3892 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3893 3894 return 0; 3895 } 3896 3897 static int rtl8169_init_ring(struct rtl8169_private *tp) 3898 { 3899 rtl8169_init_ring_indexes(tp); 3900 3901 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3902 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3903 3904 return rtl8169_rx_fill(tp); 3905 } 3906 3907 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3908 { 3909 struct ring_info *tx_skb = tp->tx_skb + entry; 3910 struct TxDesc *desc = tp->TxDescArray + entry; 3911 3912 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3913 DMA_TO_DEVICE); 3914 memset(desc, 0, sizeof(*desc)); 3915 memset(tx_skb, 0, sizeof(*tx_skb)); 3916 } 3917 3918 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3919 unsigned int n) 3920 { 3921 unsigned int i; 3922 3923 for (i = 0; i < n; i++) { 3924 unsigned int entry = (start + i) % NUM_TX_DESC; 3925 struct ring_info *tx_skb = tp->tx_skb + entry; 3926 unsigned int len = tx_skb->len; 3927 3928 if (len) { 3929 struct sk_buff *skb = tx_skb->skb; 3930 3931 rtl8169_unmap_tx_skb(tp, entry); 3932 if (skb) 3933 dev_consume_skb_any(skb); 3934 } 3935 } 3936 } 3937 3938 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3939 { 3940 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3941 netdev_reset_queue(tp->dev); 3942 } 3943 3944 static void rtl8169_cleanup(struct rtl8169_private *tp) 3945 { 3946 napi_disable(&tp->napi); 3947 3948 /* Give a racing hard_start_xmit a few cycles to complete. */ 3949 synchronize_net(); 3950 3951 /* Disable interrupts */ 3952 rtl8169_irq_mask_and_ack(tp); 3953 3954 rtl_rx_close(tp); 3955 3956 switch (tp->mac_version) { 3957 case RTL_GIGA_MAC_VER_28: 3958 case RTL_GIGA_MAC_VER_31: 3959 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3960 break; 3961 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3962 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3963 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3964 break; 3965 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_65: 3966 rtl_enable_rxdvgate(tp); 3967 fsleep(2000); 3968 break; 3969 default: 3970 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3971 fsleep(100); 3972 break; 3973 } 3974 3975 rtl_hw_reset(tp); 3976 3977 rtl8169_tx_clear(tp); 3978 rtl8169_init_ring_indexes(tp); 3979 } 3980 3981 static void rtl_reset_work(struct rtl8169_private *tp) 3982 { 3983 int i; 3984 3985 netif_stop_queue(tp->dev); 3986 3987 rtl8169_cleanup(tp); 3988 3989 for (i = 0; i < NUM_RX_DESC; i++) 3990 rtl8169_mark_to_asic(tp->RxDescArray + i); 3991 3992 napi_enable(&tp->napi); 3993 rtl_hw_start(tp); 3994 } 3995 3996 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3997 { 3998 struct rtl8169_private *tp = netdev_priv(dev); 3999 4000 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4001 } 4002 4003 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4004 void *addr, unsigned int entry, bool desc_own) 4005 { 4006 struct TxDesc *txd = tp->TxDescArray + entry; 4007 struct device *d = tp_to_dev(tp); 4008 dma_addr_t mapping; 4009 u32 opts1; 4010 int ret; 4011 4012 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4013 ret = dma_mapping_error(d, mapping); 4014 if (unlikely(ret)) { 4015 if (net_ratelimit()) 4016 netdev_err(tp->dev, "Failed to map TX data!\n"); 4017 return ret; 4018 } 4019 4020 txd->addr = cpu_to_le64(mapping); 4021 txd->opts2 = cpu_to_le32(opts[1]); 4022 4023 opts1 = opts[0] | len; 4024 if (entry == NUM_TX_DESC - 1) 4025 opts1 |= RingEnd; 4026 if (desc_own) 4027 opts1 |= DescOwn; 4028 txd->opts1 = cpu_to_le32(opts1); 4029 4030 tp->tx_skb[entry].len = len; 4031 4032 return 0; 4033 } 4034 4035 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4036 const u32 *opts, unsigned int entry) 4037 { 4038 struct skb_shared_info *info = skb_shinfo(skb); 4039 unsigned int cur_frag; 4040 4041 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4042 const skb_frag_t *frag = info->frags + cur_frag; 4043 void *addr = skb_frag_address(frag); 4044 u32 len = skb_frag_size(frag); 4045 4046 entry = (entry + 1) % NUM_TX_DESC; 4047 4048 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4049 goto err_out; 4050 } 4051 4052 return 0; 4053 4054 err_out: 4055 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4056 return -EIO; 4057 } 4058 4059 static bool rtl_skb_is_udp(struct sk_buff *skb) 4060 { 4061 int no = skb_network_offset(skb); 4062 struct ipv6hdr *i6h, _i6h; 4063 struct iphdr *ih, _ih; 4064 4065 switch (vlan_get_protocol(skb)) { 4066 case htons(ETH_P_IP): 4067 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4068 return ih && ih->protocol == IPPROTO_UDP; 4069 case htons(ETH_P_IPV6): 4070 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4071 return i6h && i6h->nexthdr == IPPROTO_UDP; 4072 default: 4073 return false; 4074 } 4075 } 4076 4077 #define RTL_MIN_PATCH_LEN 47 4078 4079 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4080 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4081 struct sk_buff *skb) 4082 { 4083 unsigned int padto = 0, len = skb->len; 4084 4085 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4086 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4087 unsigned int trans_data_len = skb_tail_pointer(skb) - 4088 skb_transport_header(skb); 4089 4090 if (trans_data_len >= offsetof(struct udphdr, len) && 4091 trans_data_len < RTL_MIN_PATCH_LEN) { 4092 u16 dest = ntohs(udp_hdr(skb)->dest); 4093 4094 /* dest is a standard PTP port */ 4095 if (dest == 319 || dest == 320) 4096 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4097 } 4098 4099 if (trans_data_len < sizeof(struct udphdr)) 4100 padto = max_t(unsigned int, padto, 4101 len + sizeof(struct udphdr) - trans_data_len); 4102 } 4103 4104 return padto; 4105 } 4106 4107 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4108 struct sk_buff *skb) 4109 { 4110 unsigned int padto; 4111 4112 padto = rtl8125_quirk_udp_padto(tp, skb); 4113 4114 switch (tp->mac_version) { 4115 case RTL_GIGA_MAC_VER_34: 4116 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 4117 padto = max_t(unsigned int, padto, ETH_ZLEN); 4118 break; 4119 default: 4120 break; 4121 } 4122 4123 return padto; 4124 } 4125 4126 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4127 { 4128 u32 mss = skb_shinfo(skb)->gso_size; 4129 4130 if (mss) { 4131 opts[0] |= TD_LSO; 4132 opts[0] |= mss << TD0_MSS_SHIFT; 4133 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4134 const struct iphdr *ip = ip_hdr(skb); 4135 4136 if (ip->protocol == IPPROTO_TCP) 4137 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4138 else if (ip->protocol == IPPROTO_UDP) 4139 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4140 else 4141 WARN_ON_ONCE(1); 4142 } 4143 } 4144 4145 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4146 struct sk_buff *skb, u32 *opts) 4147 { 4148 struct skb_shared_info *shinfo = skb_shinfo(skb); 4149 u32 mss = shinfo->gso_size; 4150 4151 if (mss) { 4152 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4153 opts[0] |= TD1_GTSENV4; 4154 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4155 if (skb_cow_head(skb, 0)) 4156 return false; 4157 4158 tcp_v6_gso_csum_prep(skb); 4159 opts[0] |= TD1_GTSENV6; 4160 } else { 4161 WARN_ON_ONCE(1); 4162 } 4163 4164 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4165 opts[1] |= mss << TD1_MSS_SHIFT; 4166 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4167 u8 ip_protocol; 4168 4169 switch (vlan_get_protocol(skb)) { 4170 case htons(ETH_P_IP): 4171 opts[1] |= TD1_IPv4_CS; 4172 ip_protocol = ip_hdr(skb)->protocol; 4173 break; 4174 4175 case htons(ETH_P_IPV6): 4176 opts[1] |= TD1_IPv6_CS; 4177 ip_protocol = ipv6_hdr(skb)->nexthdr; 4178 break; 4179 4180 default: 4181 ip_protocol = IPPROTO_RAW; 4182 break; 4183 } 4184 4185 if (ip_protocol == IPPROTO_TCP) 4186 opts[1] |= TD1_TCP_CS; 4187 else if (ip_protocol == IPPROTO_UDP) 4188 opts[1] |= TD1_UDP_CS; 4189 else 4190 WARN_ON_ONCE(1); 4191 4192 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4193 } else { 4194 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4195 4196 /* skb_padto would free the skb on error */ 4197 return !__skb_put_padto(skb, padto, false); 4198 } 4199 4200 return true; 4201 } 4202 4203 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4204 { 4205 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4206 } 4207 4208 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4209 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4210 { 4211 switch (tp->mac_version) { 4212 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4213 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4214 return false; 4215 default: 4216 return true; 4217 } 4218 } 4219 4220 static void rtl8169_doorbell(struct rtl8169_private *tp) 4221 { 4222 if (rtl_is_8125(tp)) 4223 RTL_W16(tp, TxPoll_8125, BIT(0)); 4224 else 4225 RTL_W8(tp, TxPoll, NPQ); 4226 } 4227 4228 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4229 struct net_device *dev) 4230 { 4231 unsigned int frags = skb_shinfo(skb)->nr_frags; 4232 struct rtl8169_private *tp = netdev_priv(dev); 4233 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4234 struct TxDesc *txd_first, *txd_last; 4235 bool stop_queue, door_bell; 4236 u32 opts[2]; 4237 4238 if (unlikely(!rtl_tx_slots_avail(tp))) { 4239 if (net_ratelimit()) 4240 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4241 goto err_stop_0; 4242 } 4243 4244 opts[1] = rtl8169_tx_vlan_tag(skb); 4245 opts[0] = 0; 4246 4247 if (!rtl_chip_supports_csum_v2(tp)) 4248 rtl8169_tso_csum_v1(skb, opts); 4249 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4250 goto err_dma_0; 4251 4252 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4253 entry, false))) 4254 goto err_dma_0; 4255 4256 txd_first = tp->TxDescArray + entry; 4257 4258 if (frags) { 4259 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4260 goto err_dma_1; 4261 entry = (entry + frags) % NUM_TX_DESC; 4262 } 4263 4264 txd_last = tp->TxDescArray + entry; 4265 txd_last->opts1 |= cpu_to_le32(LastFrag); 4266 tp->tx_skb[entry].skb = skb; 4267 4268 skb_tx_timestamp(skb); 4269 4270 /* Force memory writes to complete before releasing descriptor */ 4271 dma_wmb(); 4272 4273 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4274 4275 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4276 4277 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4278 smp_wmb(); 4279 4280 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4281 4282 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4283 R8169_TX_STOP_THRS, 4284 R8169_TX_START_THRS); 4285 if (door_bell || stop_queue) 4286 rtl8169_doorbell(tp); 4287 4288 return NETDEV_TX_OK; 4289 4290 err_dma_1: 4291 rtl8169_unmap_tx_skb(tp, entry); 4292 err_dma_0: 4293 dev_kfree_skb_any(skb); 4294 dev->stats.tx_dropped++; 4295 return NETDEV_TX_OK; 4296 4297 err_stop_0: 4298 netif_stop_queue(dev); 4299 dev->stats.tx_dropped++; 4300 return NETDEV_TX_BUSY; 4301 } 4302 4303 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4304 { 4305 struct skb_shared_info *info = skb_shinfo(skb); 4306 unsigned int nr_frags = info->nr_frags; 4307 4308 if (!nr_frags) 4309 return UINT_MAX; 4310 4311 return skb_frag_size(info->frags + nr_frags - 1); 4312 } 4313 4314 /* Workaround for hw issues with TSO on RTL8168evl */ 4315 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4316 netdev_features_t features) 4317 { 4318 /* IPv4 header has options field */ 4319 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4320 ip_hdrlen(skb) > sizeof(struct iphdr)) 4321 features &= ~NETIF_F_ALL_TSO; 4322 4323 /* IPv4 TCP header has options field */ 4324 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4325 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4326 features &= ~NETIF_F_ALL_TSO; 4327 4328 else if (rtl_last_frag_len(skb) <= 6) 4329 features &= ~NETIF_F_ALL_TSO; 4330 4331 return features; 4332 } 4333 4334 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4335 struct net_device *dev, 4336 netdev_features_t features) 4337 { 4338 struct rtl8169_private *tp = netdev_priv(dev); 4339 4340 if (skb_is_gso(skb)) { 4341 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4342 features = rtl8168evl_fix_tso(skb, features); 4343 4344 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4345 rtl_chip_supports_csum_v2(tp)) 4346 features &= ~NETIF_F_ALL_TSO; 4347 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4348 /* work around hw bug on some chip versions */ 4349 if (skb->len < ETH_ZLEN) 4350 features &= ~NETIF_F_CSUM_MASK; 4351 4352 if (rtl_quirk_packet_padto(tp, skb)) 4353 features &= ~NETIF_F_CSUM_MASK; 4354 4355 if (skb_transport_offset(skb) > TCPHO_MAX && 4356 rtl_chip_supports_csum_v2(tp)) 4357 features &= ~NETIF_F_CSUM_MASK; 4358 } 4359 4360 return vlan_features_check(skb, features); 4361 } 4362 4363 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4364 { 4365 struct rtl8169_private *tp = netdev_priv(dev); 4366 struct pci_dev *pdev = tp->pci_dev; 4367 int pci_status_errs; 4368 u16 pci_cmd; 4369 4370 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4371 4372 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4373 4374 if (net_ratelimit()) 4375 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4376 pci_cmd, pci_status_errs); 4377 4378 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4379 } 4380 4381 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4382 int budget) 4383 { 4384 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4385 struct sk_buff *skb; 4386 4387 dirty_tx = tp->dirty_tx; 4388 4389 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4390 unsigned int entry = dirty_tx % NUM_TX_DESC; 4391 u32 status; 4392 4393 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4394 if (status & DescOwn) 4395 break; 4396 4397 skb = tp->tx_skb[entry].skb; 4398 rtl8169_unmap_tx_skb(tp, entry); 4399 4400 if (skb) { 4401 pkts_compl++; 4402 bytes_compl += skb->len; 4403 napi_consume_skb(skb, budget); 4404 } 4405 dirty_tx++; 4406 } 4407 4408 if (tp->dirty_tx != dirty_tx) { 4409 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4410 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4411 4412 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4413 rtl_tx_slots_avail(tp), 4414 R8169_TX_START_THRS); 4415 /* 4416 * 8168 hack: TxPoll requests are lost when the Tx packets are 4417 * too close. Let's kick an extra TxPoll request when a burst 4418 * of start_xmit activity is detected (if it is not detected, 4419 * it is slow enough). -- FR 4420 * If skb is NULL then we come here again once a tx irq is 4421 * triggered after the last fragment is marked transmitted. 4422 */ 4423 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4424 rtl8169_doorbell(tp); 4425 } 4426 } 4427 4428 static inline int rtl8169_fragmented_frame(u32 status) 4429 { 4430 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4431 } 4432 4433 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4434 { 4435 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4436 4437 if (status == RxProtoTCP || status == RxProtoUDP) 4438 skb->ip_summed = CHECKSUM_UNNECESSARY; 4439 else 4440 skb_checksum_none_assert(skb); 4441 } 4442 4443 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4444 { 4445 struct device *d = tp_to_dev(tp); 4446 int count; 4447 4448 for (count = 0; count < budget; count++, tp->cur_rx++) { 4449 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4450 struct RxDesc *desc = tp->RxDescArray + entry; 4451 struct sk_buff *skb; 4452 const void *rx_buf; 4453 dma_addr_t addr; 4454 u32 status; 4455 4456 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4457 if (status & DescOwn) 4458 break; 4459 4460 /* This barrier is needed to keep us from reading 4461 * any other fields out of the Rx descriptor until 4462 * we know the status of DescOwn 4463 */ 4464 dma_rmb(); 4465 4466 if (unlikely(status & RxRES)) { 4467 if (net_ratelimit()) 4468 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4469 status); 4470 dev->stats.rx_errors++; 4471 if (status & (RxRWT | RxRUNT)) 4472 dev->stats.rx_length_errors++; 4473 if (status & RxCRC) 4474 dev->stats.rx_crc_errors++; 4475 4476 if (!(dev->features & NETIF_F_RXALL)) 4477 goto release_descriptor; 4478 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4479 goto release_descriptor; 4480 } 4481 4482 pkt_size = status & GENMASK(13, 0); 4483 if (likely(!(dev->features & NETIF_F_RXFCS))) 4484 pkt_size -= ETH_FCS_LEN; 4485 4486 /* The driver does not support incoming fragmented frames. 4487 * They are seen as a symptom of over-mtu sized frames. 4488 */ 4489 if (unlikely(rtl8169_fragmented_frame(status))) { 4490 dev->stats.rx_dropped++; 4491 dev->stats.rx_length_errors++; 4492 goto release_descriptor; 4493 } 4494 4495 skb = napi_alloc_skb(&tp->napi, pkt_size); 4496 if (unlikely(!skb)) { 4497 dev->stats.rx_dropped++; 4498 goto release_descriptor; 4499 } 4500 4501 addr = le64_to_cpu(desc->addr); 4502 rx_buf = page_address(tp->Rx_databuff[entry]); 4503 4504 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4505 prefetch(rx_buf); 4506 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4507 skb->tail += pkt_size; 4508 skb->len = pkt_size; 4509 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4510 4511 rtl8169_rx_csum(skb, status); 4512 skb->protocol = eth_type_trans(skb, dev); 4513 4514 rtl8169_rx_vlan_tag(desc, skb); 4515 4516 if (skb->pkt_type == PACKET_MULTICAST) 4517 dev->stats.multicast++; 4518 4519 napi_gro_receive(&tp->napi, skb); 4520 4521 dev_sw_netstats_rx_add(dev, pkt_size); 4522 release_descriptor: 4523 rtl8169_mark_to_asic(desc); 4524 } 4525 4526 return count; 4527 } 4528 4529 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4530 { 4531 struct rtl8169_private *tp = dev_instance; 4532 u32 status = rtl_get_events(tp); 4533 4534 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4535 return IRQ_NONE; 4536 4537 if (unlikely(status & SYSErr)) { 4538 rtl8169_pcierr_interrupt(tp->dev); 4539 goto out; 4540 } 4541 4542 if (status & LinkChg) 4543 phy_mac_interrupt(tp->phydev); 4544 4545 if (unlikely(status & RxFIFOOver && 4546 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4547 netif_stop_queue(tp->dev); 4548 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4549 } 4550 4551 if (napi_schedule_prep(&tp->napi)) { 4552 rtl_irq_disable(tp); 4553 __napi_schedule(&tp->napi); 4554 } 4555 out: 4556 rtl_ack_events(tp, status); 4557 4558 return IRQ_HANDLED; 4559 } 4560 4561 static void rtl_task(struct work_struct *work) 4562 { 4563 struct rtl8169_private *tp = 4564 container_of(work, struct rtl8169_private, wk.work); 4565 int ret; 4566 4567 rtnl_lock(); 4568 4569 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4570 goto out_unlock; 4571 4572 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4573 /* if chip isn't accessible, reset bus to revive it */ 4574 if (RTL_R32(tp, TxConfig) == ~0) { 4575 ret = pci_reset_bus(tp->pci_dev); 4576 if (ret < 0) { 4577 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4578 netif_device_detach(tp->dev); 4579 goto out_unlock; 4580 } 4581 } 4582 4583 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4584 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4585 PCIE_LINK_STATE_L0S); 4586 if (!ret) 4587 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4588 goto reset; 4589 } 4590 4591 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4592 reset: 4593 rtl_reset_work(tp); 4594 netif_wake_queue(tp->dev); 4595 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4596 rtl_reset_work(tp); 4597 } 4598 out_unlock: 4599 rtnl_unlock(); 4600 } 4601 4602 static int rtl8169_poll(struct napi_struct *napi, int budget) 4603 { 4604 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4605 struct net_device *dev = tp->dev; 4606 int work_done; 4607 4608 rtl_tx(dev, tp, budget); 4609 4610 work_done = rtl_rx(dev, tp, budget); 4611 4612 if (work_done < budget && napi_complete_done(napi, work_done)) 4613 rtl_irq_enable(tp); 4614 4615 return work_done; 4616 } 4617 4618 static void r8169_phylink_handler(struct net_device *ndev) 4619 { 4620 struct rtl8169_private *tp = netdev_priv(ndev); 4621 struct device *d = tp_to_dev(tp); 4622 4623 if (netif_carrier_ok(ndev)) { 4624 rtl_link_chg_patch(tp); 4625 pm_request_resume(d); 4626 netif_wake_queue(tp->dev); 4627 } else { 4628 /* In few cases rx is broken after link-down otherwise */ 4629 if (rtl_is_8125(tp)) 4630 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4631 pm_runtime_idle(d); 4632 } 4633 4634 phy_print_status(tp->phydev); 4635 } 4636 4637 static int r8169_phy_connect(struct rtl8169_private *tp) 4638 { 4639 struct phy_device *phydev = tp->phydev; 4640 phy_interface_t phy_mode; 4641 int ret; 4642 4643 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4644 PHY_INTERFACE_MODE_MII; 4645 4646 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4647 phy_mode); 4648 if (ret) 4649 return ret; 4650 4651 if (!tp->supports_gmii) 4652 phy_set_max_speed(phydev, SPEED_100); 4653 4654 phy_attached_info(phydev); 4655 4656 return 0; 4657 } 4658 4659 static void rtl8169_down(struct rtl8169_private *tp) 4660 { 4661 /* Clear all task flags */ 4662 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4663 4664 phy_stop(tp->phydev); 4665 4666 rtl8169_update_counters(tp); 4667 4668 pci_clear_master(tp->pci_dev); 4669 rtl_pci_commit(tp); 4670 4671 rtl8169_cleanup(tp); 4672 rtl_disable_exit_l1(tp); 4673 rtl_prepare_power_down(tp); 4674 4675 if (tp->dash_type != RTL_DASH_NONE) 4676 rtl8168_driver_stop(tp); 4677 } 4678 4679 static void rtl8169_up(struct rtl8169_private *tp) 4680 { 4681 if (tp->dash_type != RTL_DASH_NONE) 4682 rtl8168_driver_start(tp); 4683 4684 pci_set_master(tp->pci_dev); 4685 phy_init_hw(tp->phydev); 4686 phy_resume(tp->phydev); 4687 rtl8169_init_phy(tp); 4688 napi_enable(&tp->napi); 4689 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4690 rtl_reset_work(tp); 4691 4692 phy_start(tp->phydev); 4693 } 4694 4695 static int rtl8169_close(struct net_device *dev) 4696 { 4697 struct rtl8169_private *tp = netdev_priv(dev); 4698 struct pci_dev *pdev = tp->pci_dev; 4699 4700 pm_runtime_get_sync(&pdev->dev); 4701 4702 netif_stop_queue(dev); 4703 rtl8169_down(tp); 4704 rtl8169_rx_clear(tp); 4705 4706 cancel_work(&tp->wk.work); 4707 4708 free_irq(tp->irq, tp); 4709 4710 phy_disconnect(tp->phydev); 4711 4712 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4713 tp->RxPhyAddr); 4714 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4715 tp->TxPhyAddr); 4716 tp->TxDescArray = NULL; 4717 tp->RxDescArray = NULL; 4718 4719 pm_runtime_put_sync(&pdev->dev); 4720 4721 return 0; 4722 } 4723 4724 #ifdef CONFIG_NET_POLL_CONTROLLER 4725 static void rtl8169_netpoll(struct net_device *dev) 4726 { 4727 struct rtl8169_private *tp = netdev_priv(dev); 4728 4729 rtl8169_interrupt(tp->irq, tp); 4730 } 4731 #endif 4732 4733 static int rtl_open(struct net_device *dev) 4734 { 4735 struct rtl8169_private *tp = netdev_priv(dev); 4736 struct pci_dev *pdev = tp->pci_dev; 4737 unsigned long irqflags; 4738 int retval = -ENOMEM; 4739 4740 pm_runtime_get_sync(&pdev->dev); 4741 4742 /* 4743 * Rx and Tx descriptors needs 256 bytes alignment. 4744 * dma_alloc_coherent provides more. 4745 */ 4746 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4747 &tp->TxPhyAddr, GFP_KERNEL); 4748 if (!tp->TxDescArray) 4749 goto out; 4750 4751 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4752 &tp->RxPhyAddr, GFP_KERNEL); 4753 if (!tp->RxDescArray) 4754 goto err_free_tx_0; 4755 4756 retval = rtl8169_init_ring(tp); 4757 if (retval < 0) 4758 goto err_free_rx_1; 4759 4760 rtl_request_firmware(tp); 4761 4762 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4763 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4764 if (retval < 0) 4765 goto err_release_fw_2; 4766 4767 retval = r8169_phy_connect(tp); 4768 if (retval) 4769 goto err_free_irq; 4770 4771 rtl8169_up(tp); 4772 rtl8169_init_counter_offsets(tp); 4773 netif_start_queue(dev); 4774 out: 4775 pm_runtime_put_sync(&pdev->dev); 4776 4777 return retval; 4778 4779 err_free_irq: 4780 free_irq(tp->irq, tp); 4781 err_release_fw_2: 4782 rtl_release_firmware(tp); 4783 rtl8169_rx_clear(tp); 4784 err_free_rx_1: 4785 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4786 tp->RxPhyAddr); 4787 tp->RxDescArray = NULL; 4788 err_free_tx_0: 4789 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4790 tp->TxPhyAddr); 4791 tp->TxDescArray = NULL; 4792 goto out; 4793 } 4794 4795 static void 4796 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4797 { 4798 struct rtl8169_private *tp = netdev_priv(dev); 4799 struct pci_dev *pdev = tp->pci_dev; 4800 struct rtl8169_counters *counters = tp->counters; 4801 4802 pm_runtime_get_noresume(&pdev->dev); 4803 4804 netdev_stats_to_stats64(stats, &dev->stats); 4805 dev_fetch_sw_netstats(stats, dev->tstats); 4806 4807 /* 4808 * Fetch additional counter values missing in stats collected by driver 4809 * from tally counters. 4810 */ 4811 if (pm_runtime_active(&pdev->dev)) 4812 rtl8169_update_counters(tp); 4813 4814 /* 4815 * Subtract values fetched during initalization. 4816 * See rtl8169_init_counter_offsets for a description why we do that. 4817 */ 4818 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4819 le64_to_cpu(tp->tc_offset.tx_errors); 4820 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4821 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4822 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4823 le16_to_cpu(tp->tc_offset.tx_aborted); 4824 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4825 le16_to_cpu(tp->tc_offset.rx_missed); 4826 4827 pm_runtime_put_noidle(&pdev->dev); 4828 } 4829 4830 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4831 { 4832 netif_device_detach(tp->dev); 4833 4834 if (netif_running(tp->dev)) 4835 rtl8169_down(tp); 4836 } 4837 4838 static int rtl8169_runtime_resume(struct device *dev) 4839 { 4840 struct rtl8169_private *tp = dev_get_drvdata(dev); 4841 4842 rtl_rar_set(tp, tp->dev->dev_addr); 4843 __rtl8169_set_wol(tp, tp->saved_wolopts); 4844 4845 if (tp->TxDescArray) 4846 rtl8169_up(tp); 4847 4848 netif_device_attach(tp->dev); 4849 4850 return 0; 4851 } 4852 4853 static int rtl8169_suspend(struct device *device) 4854 { 4855 struct rtl8169_private *tp = dev_get_drvdata(device); 4856 4857 rtnl_lock(); 4858 rtl8169_net_suspend(tp); 4859 if (!device_may_wakeup(tp_to_dev(tp))) 4860 clk_disable_unprepare(tp->clk); 4861 rtnl_unlock(); 4862 4863 return 0; 4864 } 4865 4866 static int rtl8169_resume(struct device *device) 4867 { 4868 struct rtl8169_private *tp = dev_get_drvdata(device); 4869 4870 if (!device_may_wakeup(tp_to_dev(tp))) 4871 clk_prepare_enable(tp->clk); 4872 4873 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4874 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4875 rtl_init_rxcfg(tp); 4876 4877 return rtl8169_runtime_resume(device); 4878 } 4879 4880 static int rtl8169_runtime_suspend(struct device *device) 4881 { 4882 struct rtl8169_private *tp = dev_get_drvdata(device); 4883 4884 if (!tp->TxDescArray) { 4885 netif_device_detach(tp->dev); 4886 return 0; 4887 } 4888 4889 rtnl_lock(); 4890 __rtl8169_set_wol(tp, WAKE_PHY); 4891 rtl8169_net_suspend(tp); 4892 rtnl_unlock(); 4893 4894 return 0; 4895 } 4896 4897 static int rtl8169_runtime_idle(struct device *device) 4898 { 4899 struct rtl8169_private *tp = dev_get_drvdata(device); 4900 4901 if (tp->dash_enabled) 4902 return -EBUSY; 4903 4904 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4905 pm_schedule_suspend(device, 10000); 4906 4907 return -EBUSY; 4908 } 4909 4910 static const struct dev_pm_ops rtl8169_pm_ops = { 4911 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4912 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4913 rtl8169_runtime_idle) 4914 }; 4915 4916 static void rtl_shutdown(struct pci_dev *pdev) 4917 { 4918 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4919 4920 rtnl_lock(); 4921 rtl8169_net_suspend(tp); 4922 rtnl_unlock(); 4923 4924 /* Restore original MAC address */ 4925 rtl_rar_set(tp, tp->dev->perm_addr); 4926 4927 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 4928 pci_wake_from_d3(pdev, tp->saved_wolopts); 4929 pci_set_power_state(pdev, PCI_D3hot); 4930 } 4931 } 4932 4933 static void rtl_remove_one(struct pci_dev *pdev) 4934 { 4935 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4936 4937 if (pci_dev_run_wake(pdev)) 4938 pm_runtime_get_noresume(&pdev->dev); 4939 4940 cancel_work_sync(&tp->wk.work); 4941 4942 unregister_netdev(tp->dev); 4943 4944 if (tp->dash_type != RTL_DASH_NONE) 4945 rtl8168_driver_stop(tp); 4946 4947 rtl_release_firmware(tp); 4948 4949 /* restore original MAC address */ 4950 rtl_rar_set(tp, tp->dev->perm_addr); 4951 } 4952 4953 static const struct net_device_ops rtl_netdev_ops = { 4954 .ndo_open = rtl_open, 4955 .ndo_stop = rtl8169_close, 4956 .ndo_get_stats64 = rtl8169_get_stats64, 4957 .ndo_start_xmit = rtl8169_start_xmit, 4958 .ndo_features_check = rtl8169_features_check, 4959 .ndo_tx_timeout = rtl8169_tx_timeout, 4960 .ndo_validate_addr = eth_validate_addr, 4961 .ndo_change_mtu = rtl8169_change_mtu, 4962 .ndo_fix_features = rtl8169_fix_features, 4963 .ndo_set_features = rtl8169_set_features, 4964 .ndo_set_mac_address = rtl_set_mac_address, 4965 .ndo_eth_ioctl = phy_do_ioctl_running, 4966 .ndo_set_rx_mode = rtl_set_rx_mode, 4967 #ifdef CONFIG_NET_POLL_CONTROLLER 4968 .ndo_poll_controller = rtl8169_netpoll, 4969 #endif 4970 4971 }; 4972 4973 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4974 { 4975 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4976 4977 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4978 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4979 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4980 /* special workaround needed */ 4981 tp->irq_mask |= RxFIFOOver; 4982 else 4983 tp->irq_mask |= RxOverflow; 4984 } 4985 4986 static int rtl_alloc_irq(struct rtl8169_private *tp) 4987 { 4988 unsigned int flags; 4989 4990 switch (tp->mac_version) { 4991 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4992 rtl_unlock_config_regs(tp); 4993 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4994 rtl_lock_config_regs(tp); 4995 fallthrough; 4996 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4997 flags = PCI_IRQ_LEGACY; 4998 break; 4999 default: 5000 flags = PCI_IRQ_ALL_TYPES; 5001 break; 5002 } 5003 5004 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5005 } 5006 5007 static void rtl_read_mac_address(struct rtl8169_private *tp, 5008 u8 mac_addr[ETH_ALEN]) 5009 { 5010 /* Get MAC address */ 5011 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5012 u32 value; 5013 5014 value = rtl_eri_read(tp, 0xe0); 5015 put_unaligned_le32(value, mac_addr); 5016 value = rtl_eri_read(tp, 0xe4); 5017 put_unaligned_le16(value, mac_addr + 4); 5018 } else if (rtl_is_8125(tp)) { 5019 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5020 } 5021 } 5022 5023 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5024 { 5025 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5026 } 5027 5028 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5029 { 5030 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5031 } 5032 5033 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5034 { 5035 struct rtl8169_private *tp = mii_bus->priv; 5036 5037 if (phyaddr > 0) 5038 return -ENODEV; 5039 5040 return rtl_readphy(tp, phyreg); 5041 } 5042 5043 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5044 int phyreg, u16 val) 5045 { 5046 struct rtl8169_private *tp = mii_bus->priv; 5047 5048 if (phyaddr > 0) 5049 return -ENODEV; 5050 5051 rtl_writephy(tp, phyreg, val); 5052 5053 return 0; 5054 } 5055 5056 static int r8169_mdio_register(struct rtl8169_private *tp) 5057 { 5058 struct pci_dev *pdev = tp->pci_dev; 5059 struct mii_bus *new_bus; 5060 int ret; 5061 5062 new_bus = devm_mdiobus_alloc(&pdev->dev); 5063 if (!new_bus) 5064 return -ENOMEM; 5065 5066 new_bus->name = "r8169"; 5067 new_bus->priv = tp; 5068 new_bus->parent = &pdev->dev; 5069 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5070 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5071 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5072 5073 new_bus->read = r8169_mdio_read_reg; 5074 new_bus->write = r8169_mdio_write_reg; 5075 5076 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5077 if (ret) 5078 return ret; 5079 5080 tp->phydev = mdiobus_get_phy(new_bus, 0); 5081 if (!tp->phydev) { 5082 return -ENODEV; 5083 } else if (!tp->phydev->drv) { 5084 /* Most chip versions fail with the genphy driver. 5085 * Therefore ensure that the dedicated PHY driver is loaded. 5086 */ 5087 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5088 tp->phydev->phy_id); 5089 return -EUNATCH; 5090 } 5091 5092 tp->phydev->mac_managed_pm = true; 5093 if (rtl_supports_eee(tp)) 5094 phy_advertise_eee_all(tp->phydev); 5095 phy_support_asym_pause(tp->phydev); 5096 5097 /* PHY will be woken up in rtl_open() */ 5098 phy_suspend(tp->phydev); 5099 5100 return 0; 5101 } 5102 5103 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5104 { 5105 rtl_enable_rxdvgate(tp); 5106 5107 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5108 msleep(1); 5109 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5110 5111 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5112 r8168g_wait_ll_share_fifo_ready(tp); 5113 5114 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5115 r8168g_wait_ll_share_fifo_ready(tp); 5116 } 5117 5118 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5119 { 5120 rtl_enable_rxdvgate(tp); 5121 5122 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5123 msleep(1); 5124 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5125 5126 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5127 r8168g_wait_ll_share_fifo_ready(tp); 5128 5129 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5130 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5131 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5132 r8168g_wait_ll_share_fifo_ready(tp); 5133 } 5134 5135 static void rtl_hw_initialize(struct rtl8169_private *tp) 5136 { 5137 switch (tp->mac_version) { 5138 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5139 rtl8168ep_stop_cmac(tp); 5140 fallthrough; 5141 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5142 rtl_hw_init_8168g(tp); 5143 break; 5144 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_65: 5145 rtl_hw_init_8125(tp); 5146 break; 5147 default: 5148 break; 5149 } 5150 } 5151 5152 static int rtl_jumbo_max(struct rtl8169_private *tp) 5153 { 5154 /* Non-GBit versions don't support jumbo frames */ 5155 if (!tp->supports_gmii) 5156 return 0; 5157 5158 switch (tp->mac_version) { 5159 /* RTL8169 */ 5160 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5161 return JUMBO_7K; 5162 /* RTL8168b */ 5163 case RTL_GIGA_MAC_VER_11: 5164 case RTL_GIGA_MAC_VER_17: 5165 return JUMBO_4K; 5166 /* RTL8168c */ 5167 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5168 return JUMBO_6K; 5169 default: 5170 return JUMBO_9K; 5171 } 5172 } 5173 5174 static void rtl_init_mac_address(struct rtl8169_private *tp) 5175 { 5176 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5177 struct net_device *dev = tp->dev; 5178 int rc; 5179 5180 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5181 if (!rc) 5182 goto done; 5183 5184 rtl_read_mac_address(tp, mac_addr); 5185 if (is_valid_ether_addr(mac_addr)) 5186 goto done; 5187 5188 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5189 if (is_valid_ether_addr(mac_addr)) 5190 goto done; 5191 5192 eth_random_addr(mac_addr); 5193 dev->addr_assign_type = NET_ADDR_RANDOM; 5194 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5195 done: 5196 eth_hw_addr_set(dev, mac_addr); 5197 rtl_rar_set(tp, mac_addr); 5198 } 5199 5200 /* register is set if system vendor successfully tested ASPM 1.2 */ 5201 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5202 { 5203 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5204 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5205 return true; 5206 5207 return false; 5208 } 5209 5210 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5211 { 5212 struct rtl8169_private *tp; 5213 int jumbo_max, region, rc; 5214 enum mac_version chipset; 5215 struct net_device *dev; 5216 u32 txconfig; 5217 u16 xid; 5218 5219 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5220 if (!dev) 5221 return -ENOMEM; 5222 5223 SET_NETDEV_DEV(dev, &pdev->dev); 5224 dev->netdev_ops = &rtl_netdev_ops; 5225 tp = netdev_priv(dev); 5226 tp->dev = dev; 5227 tp->pci_dev = pdev; 5228 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5229 tp->ocp_base = OCP_STD_PHY_BASE; 5230 5231 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5232 raw_spin_lock_init(&tp->config25_lock); 5233 raw_spin_lock_init(&tp->mac_ocp_lock); 5234 mutex_init(&tp->led_lock); 5235 5236 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5237 struct pcpu_sw_netstats); 5238 if (!dev->tstats) 5239 return -ENOMEM; 5240 5241 /* Get the *optional* external "ether_clk" used on some boards */ 5242 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5243 if (IS_ERR(tp->clk)) 5244 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5245 5246 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5247 rc = pcim_enable_device(pdev); 5248 if (rc < 0) 5249 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5250 5251 if (pcim_set_mwi(pdev) < 0) 5252 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5253 5254 /* use first MMIO region */ 5255 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5256 if (region < 0) 5257 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5258 5259 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5260 if (rc < 0) 5261 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5262 5263 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5264 5265 txconfig = RTL_R32(tp, TxConfig); 5266 if (txconfig == ~0U) 5267 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5268 5269 xid = (txconfig >> 20) & 0xfcf; 5270 5271 /* Identify chip attached to board */ 5272 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5273 if (chipset == RTL_GIGA_MAC_NONE) 5274 return dev_err_probe(&pdev->dev, -ENODEV, 5275 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5276 xid); 5277 tp->mac_version = chipset; 5278 5279 /* Disable ASPM L1 as that cause random device stop working 5280 * problems as well as full system hangs for some PCIe devices users. 5281 */ 5282 if (rtl_aspm_is_safe(tp)) 5283 rc = 0; 5284 else 5285 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5286 tp->aspm_manageable = !rc; 5287 5288 tp->dash_type = rtl_get_dash_type(tp); 5289 tp->dash_enabled = rtl_dash_is_enabled(tp); 5290 5291 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5292 5293 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5294 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5295 dev->features |= NETIF_F_HIGHDMA; 5296 5297 rtl_init_rxcfg(tp); 5298 5299 rtl8169_irq_mask_and_ack(tp); 5300 5301 rtl_hw_initialize(tp); 5302 5303 rtl_hw_reset(tp); 5304 5305 rc = rtl_alloc_irq(tp); 5306 if (rc < 0) 5307 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5308 5309 tp->irq = pci_irq_vector(pdev, 0); 5310 5311 INIT_WORK(&tp->wk.work, rtl_task); 5312 5313 rtl_init_mac_address(tp); 5314 5315 dev->ethtool_ops = &rtl8169_ethtool_ops; 5316 5317 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5318 5319 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5320 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5321 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5322 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5323 5324 /* 5325 * Pretend we are using VLANs; This bypasses a nasty bug where 5326 * Interrupts stop flowing on high load on 8110SCd controllers. 5327 */ 5328 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5329 /* Disallow toggling */ 5330 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5331 5332 if (rtl_chip_supports_csum_v2(tp)) 5333 dev->hw_features |= NETIF_F_IPV6_CSUM; 5334 5335 dev->features |= dev->hw_features; 5336 5337 /* There has been a number of reports that using SG/TSO results in 5338 * tx timeouts. However for a lot of people SG/TSO works fine. 5339 * Therefore disable both features by default, but allow users to 5340 * enable them. Use at own risk! 5341 */ 5342 if (rtl_chip_supports_csum_v2(tp)) { 5343 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5344 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5345 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5346 } else { 5347 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5348 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5349 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5350 } 5351 5352 dev->hw_features |= NETIF_F_RXALL; 5353 dev->hw_features |= NETIF_F_RXFCS; 5354 5355 netdev_sw_irq_coalesce_default_on(dev); 5356 5357 /* configure chip for default features */ 5358 rtl8169_set_features(dev, dev->features); 5359 5360 if (!tp->dash_enabled) { 5361 rtl_set_d3_pll_down(tp, true); 5362 } else { 5363 rtl_set_d3_pll_down(tp, false); 5364 dev->wol_enabled = 1; 5365 } 5366 5367 jumbo_max = rtl_jumbo_max(tp); 5368 if (jumbo_max) 5369 dev->max_mtu = jumbo_max; 5370 5371 rtl_set_irq_mask(tp); 5372 5373 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5374 5375 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5376 &tp->counters_phys_addr, 5377 GFP_KERNEL); 5378 if (!tp->counters) 5379 return -ENOMEM; 5380 5381 pci_set_drvdata(pdev, tp); 5382 5383 rc = r8169_mdio_register(tp); 5384 if (rc) 5385 return rc; 5386 5387 rc = register_netdev(dev); 5388 if (rc) 5389 return rc; 5390 5391 if (IS_ENABLED(CONFIG_R8169_LEDS) && 5392 tp->mac_version > RTL_GIGA_MAC_VER_06 && 5393 tp->mac_version < RTL_GIGA_MAC_VER_61) 5394 rtl8168_init_leds(dev); 5395 5396 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5397 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5398 5399 if (jumbo_max) 5400 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5401 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5402 "ok" : "ko"); 5403 5404 if (tp->dash_type != RTL_DASH_NONE) { 5405 netdev_info(dev, "DASH %s\n", 5406 tp->dash_enabled ? "enabled" : "disabled"); 5407 rtl8168_driver_start(tp); 5408 } 5409 5410 if (pci_dev_run_wake(pdev)) 5411 pm_runtime_put_sync(&pdev->dev); 5412 5413 return 0; 5414 } 5415 5416 static struct pci_driver rtl8169_pci_driver = { 5417 .name = KBUILD_MODNAME, 5418 .id_table = rtl8169_pci_tbl, 5419 .probe = rtl_init_one, 5420 .remove = rtl_remove_one, 5421 .shutdown = rtl_shutdown, 5422 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5423 }; 5424 5425 module_pci_driver(rtl8169_pci_driver); 5426