1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169_firmware.h" 35 36 #define MODULENAME "r8169" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 59 #define R8169_MSG_DEFAULT \ 60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 61 62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 64 #define MC_FILTER_LIMIT 32 65 66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 68 69 #define R8169_REGS_SIZE 256 70 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 enum mac_version { 87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */ 88 RTL_GIGA_MAC_VER_02, 89 RTL_GIGA_MAC_VER_03, 90 RTL_GIGA_MAC_VER_04, 91 RTL_GIGA_MAC_VER_05, 92 RTL_GIGA_MAC_VER_06, 93 RTL_GIGA_MAC_VER_07, 94 RTL_GIGA_MAC_VER_08, 95 RTL_GIGA_MAC_VER_09, 96 RTL_GIGA_MAC_VER_10, 97 RTL_GIGA_MAC_VER_11, 98 RTL_GIGA_MAC_VER_12, 99 RTL_GIGA_MAC_VER_13, 100 RTL_GIGA_MAC_VER_14, 101 RTL_GIGA_MAC_VER_15, 102 RTL_GIGA_MAC_VER_16, 103 RTL_GIGA_MAC_VER_17, 104 RTL_GIGA_MAC_VER_18, 105 RTL_GIGA_MAC_VER_19, 106 RTL_GIGA_MAC_VER_20, 107 RTL_GIGA_MAC_VER_21, 108 RTL_GIGA_MAC_VER_22, 109 RTL_GIGA_MAC_VER_23, 110 RTL_GIGA_MAC_VER_24, 111 RTL_GIGA_MAC_VER_25, 112 RTL_GIGA_MAC_VER_26, 113 RTL_GIGA_MAC_VER_27, 114 RTL_GIGA_MAC_VER_28, 115 RTL_GIGA_MAC_VER_29, 116 RTL_GIGA_MAC_VER_30, 117 RTL_GIGA_MAC_VER_31, 118 RTL_GIGA_MAC_VER_32, 119 RTL_GIGA_MAC_VER_33, 120 RTL_GIGA_MAC_VER_34, 121 RTL_GIGA_MAC_VER_35, 122 RTL_GIGA_MAC_VER_36, 123 RTL_GIGA_MAC_VER_37, 124 RTL_GIGA_MAC_VER_38, 125 RTL_GIGA_MAC_VER_39, 126 RTL_GIGA_MAC_VER_40, 127 RTL_GIGA_MAC_VER_41, 128 RTL_GIGA_MAC_VER_42, 129 RTL_GIGA_MAC_VER_43, 130 RTL_GIGA_MAC_VER_44, 131 RTL_GIGA_MAC_VER_45, 132 RTL_GIGA_MAC_VER_46, 133 RTL_GIGA_MAC_VER_47, 134 RTL_GIGA_MAC_VER_48, 135 RTL_GIGA_MAC_VER_49, 136 RTL_GIGA_MAC_VER_50, 137 RTL_GIGA_MAC_VER_51, 138 RTL_GIGA_MAC_VER_60, 139 RTL_GIGA_MAC_VER_61, 140 RTL_GIGA_MAC_NONE 141 }; 142 143 #define JUMBO_1K ETH_DATA_LEN 144 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) 145 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) 146 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) 147 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) 148 149 static const struct { 150 const char *name; 151 const char *fw_name; 152 } rtl_chip_infos[] = { 153 /* PCI devices. */ 154 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 155 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 156 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 157 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 158 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 159 /* PCI-E devices. */ 160 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 161 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 162 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 163 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 164 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 165 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 166 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 167 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 168 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 169 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 170 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 171 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 172 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 173 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 174 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 175 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 176 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 177 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 178 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 179 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 180 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 181 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 182 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 183 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 184 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 185 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 186 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 187 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 188 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 189 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 190 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 191 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 192 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 193 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 194 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 195 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 196 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 197 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 198 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 199 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 200 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 201 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 202 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 203 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 204 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 205 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 206 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 207 }; 208 209 static const struct pci_device_id rtl8169_pci_tbl[] = { 210 { PCI_VDEVICE(REALTEK, 0x2502) }, 211 { PCI_VDEVICE(REALTEK, 0x2600) }, 212 { PCI_VDEVICE(REALTEK, 0x8129) }, 213 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 214 { PCI_VDEVICE(REALTEK, 0x8161) }, 215 { PCI_VDEVICE(REALTEK, 0x8167) }, 216 { PCI_VDEVICE(REALTEK, 0x8168) }, 217 { PCI_VDEVICE(NCUBE, 0x8168) }, 218 { PCI_VDEVICE(REALTEK, 0x8169) }, 219 { PCI_VENDOR_ID_DLINK, 0x4300, 220 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 221 { PCI_VDEVICE(DLINK, 0x4300) }, 222 { PCI_VDEVICE(DLINK, 0x4302) }, 223 { PCI_VDEVICE(AT, 0xc107) }, 224 { PCI_VDEVICE(USR, 0x0116) }, 225 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 226 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 227 { PCI_VDEVICE(REALTEK, 0x8125) }, 228 { PCI_VDEVICE(REALTEK, 0x3000) }, 229 {} 230 }; 231 232 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 233 234 static struct { 235 u32 msg_enable; 236 } debug = { -1 }; 237 238 enum rtl_registers { 239 MAC0 = 0, /* Ethernet hardware address. */ 240 MAC4 = 4, 241 MAR0 = 8, /* Multicast filter. */ 242 CounterAddrLow = 0x10, 243 CounterAddrHigh = 0x14, 244 TxDescStartAddrLow = 0x20, 245 TxDescStartAddrHigh = 0x24, 246 TxHDescStartAddrLow = 0x28, 247 TxHDescStartAddrHigh = 0x2c, 248 FLASH = 0x30, 249 ERSR = 0x36, 250 ChipCmd = 0x37, 251 TxPoll = 0x38, 252 IntrMask = 0x3c, 253 IntrStatus = 0x3e, 254 255 TxConfig = 0x40, 256 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 257 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 258 259 RxConfig = 0x44, 260 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 261 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 262 #define RXCFG_FIFO_SHIFT 13 263 /* No threshold before first PCI xfer */ 264 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 265 #define RX_EARLY_OFF (1 << 11) 266 #define RXCFG_DMA_SHIFT 8 267 /* Unlimited maximum PCI burst. */ 268 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 269 270 RxMissed = 0x4c, 271 Cfg9346 = 0x50, 272 Config0 = 0x51, 273 Config1 = 0x52, 274 Config2 = 0x53, 275 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 276 277 Config3 = 0x54, 278 Config4 = 0x55, 279 Config5 = 0x56, 280 PHYAR = 0x60, 281 PHYstatus = 0x6c, 282 RxMaxSize = 0xda, 283 CPlusCmd = 0xe0, 284 IntrMitigate = 0xe2, 285 286 #define RTL_COALESCE_MASK 0x0f 287 #define RTL_COALESCE_SHIFT 4 288 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) 289 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) 290 291 RxDescAddrLow = 0xe4, 292 RxDescAddrHigh = 0xe8, 293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 294 295 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 296 297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 298 299 #define TxPacketMax (8064 >> 7) 300 #define EarlySize 0x27 301 302 FuncEvent = 0xf0, 303 FuncEventMask = 0xf4, 304 FuncPresetState = 0xf8, 305 IBCR0 = 0xf8, 306 IBCR2 = 0xf9, 307 IBIMR0 = 0xfa, 308 IBISR0 = 0xfb, 309 FuncForceEvent = 0xfc, 310 }; 311 312 enum rtl8168_8101_registers { 313 CSIDR = 0x64, 314 CSIAR = 0x68, 315 #define CSIAR_FLAG 0x80000000 316 #define CSIAR_WRITE_CMD 0x80000000 317 #define CSIAR_BYTE_ENABLE 0x0000f000 318 #define CSIAR_ADDR_MASK 0x00000fff 319 PMCH = 0x6f, 320 EPHYAR = 0x80, 321 #define EPHYAR_FLAG 0x80000000 322 #define EPHYAR_WRITE_CMD 0x80000000 323 #define EPHYAR_REG_MASK 0x1f 324 #define EPHYAR_REG_SHIFT 16 325 #define EPHYAR_DATA_MASK 0xffff 326 DLLPR = 0xd0, 327 #define PFM_EN (1 << 6) 328 #define TX_10M_PS_EN (1 << 7) 329 DBG_REG = 0xd1, 330 #define FIX_NAK_1 (1 << 4) 331 #define FIX_NAK_2 (1 << 3) 332 TWSI = 0xd2, 333 MCU = 0xd3, 334 #define NOW_IS_OOB (1 << 7) 335 #define TX_EMPTY (1 << 5) 336 #define RX_EMPTY (1 << 4) 337 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 338 #define EN_NDP (1 << 3) 339 #define EN_OOB_RESET (1 << 2) 340 #define LINK_LIST_RDY (1 << 1) 341 EFUSEAR = 0xdc, 342 #define EFUSEAR_FLAG 0x80000000 343 #define EFUSEAR_WRITE_CMD 0x80000000 344 #define EFUSEAR_READ_CMD 0x00000000 345 #define EFUSEAR_REG_MASK 0x03ff 346 #define EFUSEAR_REG_SHIFT 8 347 #define EFUSEAR_DATA_MASK 0xff 348 MISC_1 = 0xf2, 349 #define PFM_D3COLD_EN (1 << 6) 350 }; 351 352 enum rtl8168_registers { 353 LED_FREQ = 0x1a, 354 EEE_LED = 0x1b, 355 ERIDR = 0x70, 356 ERIAR = 0x74, 357 #define ERIAR_FLAG 0x80000000 358 #define ERIAR_WRITE_CMD 0x80000000 359 #define ERIAR_READ_CMD 0x00000000 360 #define ERIAR_ADDR_BYTE_ALIGN 4 361 #define ERIAR_TYPE_SHIFT 16 362 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 363 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 364 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 365 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 366 #define ERIAR_MASK_SHIFT 12 367 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 368 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 369 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 370 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 371 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 372 EPHY_RXER_NUM = 0x7c, 373 OCPDR = 0xb0, /* OCP GPHY access */ 374 #define OCPDR_WRITE_CMD 0x80000000 375 #define OCPDR_READ_CMD 0x00000000 376 #define OCPDR_REG_MASK 0x7f 377 #define OCPDR_GPHY_REG_SHIFT 16 378 #define OCPDR_DATA_MASK 0xffff 379 OCPAR = 0xb4, 380 #define OCPAR_FLAG 0x80000000 381 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 382 #define OCPAR_GPHY_READ_CMD 0x0000f060 383 GPHY_OCP = 0xb8, 384 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 385 MISC = 0xf0, /* 8168e only. */ 386 #define TXPLA_RST (1 << 29) 387 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 388 #define PWM_EN (1 << 22) 389 #define RXDV_GATED_EN (1 << 19) 390 #define EARLY_TALLY_EN (1 << 16) 391 }; 392 393 enum rtl8125_registers { 394 IntrMask_8125 = 0x38, 395 IntrStatus_8125 = 0x3c, 396 TxPoll_8125 = 0x90, 397 MAC0_BKP = 0x19e0, 398 }; 399 400 #define RX_VLAN_INNER_8125 BIT(22) 401 #define RX_VLAN_OUTER_8125 BIT(23) 402 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 403 404 #define RX_FETCH_DFLT_8125 (8 << 27) 405 406 enum rtl_register_content { 407 /* InterruptStatusBits */ 408 SYSErr = 0x8000, 409 PCSTimeout = 0x4000, 410 SWInt = 0x0100, 411 TxDescUnavail = 0x0080, 412 RxFIFOOver = 0x0040, 413 LinkChg = 0x0020, 414 RxOverflow = 0x0010, 415 TxErr = 0x0008, 416 TxOK = 0x0004, 417 RxErr = 0x0002, 418 RxOK = 0x0001, 419 420 /* RxStatusDesc */ 421 RxRWT = (1 << 22), 422 RxRES = (1 << 21), 423 RxRUNT = (1 << 20), 424 RxCRC = (1 << 19), 425 426 /* ChipCmdBits */ 427 StopReq = 0x80, 428 CmdReset = 0x10, 429 CmdRxEnb = 0x08, 430 CmdTxEnb = 0x04, 431 RxBufEmpty = 0x01, 432 433 /* TXPoll register p.5 */ 434 HPQ = 0x80, /* Poll cmd on the high prio queue */ 435 NPQ = 0x40, /* Poll cmd on the low prio queue */ 436 FSWInt = 0x01, /* Forced software interrupt */ 437 438 /* Cfg9346Bits */ 439 Cfg9346_Lock = 0x00, 440 Cfg9346_Unlock = 0xc0, 441 442 /* rx_mode_bits */ 443 AcceptErr = 0x20, 444 AcceptRunt = 0x10, 445 AcceptBroadcast = 0x08, 446 AcceptMulticast = 0x04, 447 AcceptMyPhys = 0x02, 448 AcceptAllPhys = 0x01, 449 #define RX_CONFIG_ACCEPT_MASK 0x3f 450 451 /* TxConfigBits */ 452 TxInterFrameGapShift = 24, 453 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 454 455 /* Config1 register p.24 */ 456 LEDS1 = (1 << 7), 457 LEDS0 = (1 << 6), 458 Speed_down = (1 << 4), 459 MEMMAP = (1 << 3), 460 IOMAP = (1 << 2), 461 VPD = (1 << 1), 462 PMEnable = (1 << 0), /* Power Management Enable */ 463 464 /* Config2 register p. 25 */ 465 ClkReqEn = (1 << 7), /* Clock Request Enable */ 466 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 467 PCI_Clock_66MHz = 0x01, 468 PCI_Clock_33MHz = 0x00, 469 470 /* Config3 register p.25 */ 471 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 472 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 473 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 474 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 475 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 476 477 /* Config4 register */ 478 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 479 480 /* Config5 register p.27 */ 481 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 482 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 483 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 484 Spi_en = (1 << 3), 485 LanWake = (1 << 1), /* LanWake enable/disable */ 486 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 487 ASPM_en = (1 << 0), /* ASPM enable */ 488 489 /* CPlusCmd p.31 */ 490 EnableBist = (1 << 15), // 8168 8101 491 Mac_dbgo_oe = (1 << 14), // 8168 8101 492 Normal_mode = (1 << 13), // unused 493 Force_half_dup = (1 << 12), // 8168 8101 494 Force_rxflow_en = (1 << 11), // 8168 8101 495 Force_txflow_en = (1 << 10), // 8168 8101 496 Cxpl_dbg_sel = (1 << 9), // 8168 8101 497 ASF = (1 << 8), // 8168 8101 498 PktCntrDisable = (1 << 7), // 8168 8101 499 Mac_dbgo_sel = 0x001c, // 8168 500 RxVlan = (1 << 6), 501 RxChkSum = (1 << 5), 502 PCIDAC = (1 << 4), 503 PCIMulRW = (1 << 3), 504 #define INTT_MASK GENMASK(1, 0) 505 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 506 507 /* rtl8169_PHYstatus */ 508 TBI_Enable = 0x80, 509 TxFlowCtrl = 0x40, 510 RxFlowCtrl = 0x20, 511 _1000bpsF = 0x10, 512 _100bps = 0x08, 513 _10bps = 0x04, 514 LinkStatus = 0x02, 515 FullDup = 0x01, 516 517 /* ResetCounterCommand */ 518 CounterReset = 0x1, 519 520 /* DumpCounterCommand */ 521 CounterDump = 0x8, 522 523 /* magic enable v2 */ 524 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 525 }; 526 527 enum rtl_desc_bit { 528 /* First doubleword. */ 529 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 530 RingEnd = (1 << 30), /* End of descriptor ring */ 531 FirstFrag = (1 << 29), /* First segment of a packet */ 532 LastFrag = (1 << 28), /* Final segment of a packet */ 533 }; 534 535 /* Generic case. */ 536 enum rtl_tx_desc_bit { 537 /* First doubleword. */ 538 TD_LSO = (1 << 27), /* Large Send Offload */ 539 #define TD_MSS_MAX 0x07ffu /* MSS value */ 540 541 /* Second doubleword. */ 542 TxVlanTag = (1 << 17), /* Add VLAN tag */ 543 }; 544 545 /* 8169, 8168b and 810x except 8102e. */ 546 enum rtl_tx_desc_bit_0 { 547 /* First doubleword. */ 548 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 549 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 550 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 551 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 552 }; 553 554 /* 8102e, 8168c and beyond. */ 555 enum rtl_tx_desc_bit_1 { 556 /* First doubleword. */ 557 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 558 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 559 #define GTTCPHO_SHIFT 18 560 #define GTTCPHO_MAX 0x7f 561 562 /* Second doubleword. */ 563 #define TCPHO_SHIFT 18 564 #define TCPHO_MAX 0x3ff 565 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 566 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 567 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 568 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 569 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 570 }; 571 572 enum rtl_rx_desc_bit { 573 /* Rx private */ 574 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 575 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 576 577 #define RxProtoUDP (PID1) 578 #define RxProtoTCP (PID0) 579 #define RxProtoIP (PID1 | PID0) 580 #define RxProtoMask RxProtoIP 581 582 IPFail = (1 << 16), /* IP checksum failed */ 583 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 584 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 585 RxVlanTag = (1 << 16), /* VLAN tag available */ 586 }; 587 588 #define RsvdMask 0x3fffc000 589 590 #define RTL_GSO_MAX_SIZE_V1 32000 591 #define RTL_GSO_MAX_SEGS_V1 24 592 #define RTL_GSO_MAX_SIZE_V2 64000 593 #define RTL_GSO_MAX_SEGS_V2 64 594 595 struct TxDesc { 596 __le32 opts1; 597 __le32 opts2; 598 __le64 addr; 599 }; 600 601 struct RxDesc { 602 __le32 opts1; 603 __le32 opts2; 604 __le64 addr; 605 }; 606 607 struct ring_info { 608 struct sk_buff *skb; 609 u32 len; 610 }; 611 612 struct rtl8169_counters { 613 __le64 tx_packets; 614 __le64 rx_packets; 615 __le64 tx_errors; 616 __le32 rx_errors; 617 __le16 rx_missed; 618 __le16 align_errors; 619 __le32 tx_one_collision; 620 __le32 tx_multi_collision; 621 __le64 rx_unicast; 622 __le64 rx_broadcast; 623 __le32 rx_multicast; 624 __le16 tx_aborted; 625 __le16 tx_underun; 626 }; 627 628 struct rtl8169_tc_offsets { 629 bool inited; 630 __le64 tx_errors; 631 __le32 tx_multi_collision; 632 __le16 tx_aborted; 633 }; 634 635 enum rtl_flag { 636 RTL_FLAG_TASK_ENABLED = 0, 637 RTL_FLAG_TASK_RESET_PENDING, 638 RTL_FLAG_MAX 639 }; 640 641 struct rtl8169_stats { 642 u64 packets; 643 u64 bytes; 644 struct u64_stats_sync syncp; 645 }; 646 647 struct rtl8169_private { 648 void __iomem *mmio_addr; /* memory map physical address */ 649 struct pci_dev *pci_dev; 650 struct net_device *dev; 651 struct phy_device *phydev; 652 struct napi_struct napi; 653 u32 msg_enable; 654 enum mac_version mac_version; 655 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 656 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 657 u32 dirty_tx; 658 struct rtl8169_stats rx_stats; 659 struct rtl8169_stats tx_stats; 660 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 661 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 662 dma_addr_t TxPhyAddr; 663 dma_addr_t RxPhyAddr; 664 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 665 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 666 u16 cp_cmd; 667 u32 irq_mask; 668 struct clk *clk; 669 670 struct { 671 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 672 struct mutex mutex; 673 struct work_struct work; 674 } wk; 675 676 unsigned irq_enabled:1; 677 unsigned supports_gmii:1; 678 unsigned aspm_manageable:1; 679 dma_addr_t counters_phys_addr; 680 struct rtl8169_counters *counters; 681 struct rtl8169_tc_offsets tc_offset; 682 u32 saved_wolopts; 683 684 const char *fw_name; 685 struct rtl_fw *rtl_fw; 686 687 u32 ocp_base; 688 }; 689 690 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 691 692 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 693 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 694 module_param_named(debug, debug.msg_enable, int, 0); 695 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 696 MODULE_SOFTDEP("pre: realtek"); 697 MODULE_LICENSE("GPL"); 698 MODULE_FIRMWARE(FIRMWARE_8168D_1); 699 MODULE_FIRMWARE(FIRMWARE_8168D_2); 700 MODULE_FIRMWARE(FIRMWARE_8168E_1); 701 MODULE_FIRMWARE(FIRMWARE_8168E_2); 702 MODULE_FIRMWARE(FIRMWARE_8168E_3); 703 MODULE_FIRMWARE(FIRMWARE_8105E_1); 704 MODULE_FIRMWARE(FIRMWARE_8168F_1); 705 MODULE_FIRMWARE(FIRMWARE_8168F_2); 706 MODULE_FIRMWARE(FIRMWARE_8402_1); 707 MODULE_FIRMWARE(FIRMWARE_8411_1); 708 MODULE_FIRMWARE(FIRMWARE_8411_2); 709 MODULE_FIRMWARE(FIRMWARE_8106E_1); 710 MODULE_FIRMWARE(FIRMWARE_8106E_2); 711 MODULE_FIRMWARE(FIRMWARE_8168G_2); 712 MODULE_FIRMWARE(FIRMWARE_8168G_3); 713 MODULE_FIRMWARE(FIRMWARE_8168H_1); 714 MODULE_FIRMWARE(FIRMWARE_8168H_2); 715 MODULE_FIRMWARE(FIRMWARE_8107E_1); 716 MODULE_FIRMWARE(FIRMWARE_8107E_2); 717 MODULE_FIRMWARE(FIRMWARE_8125A_3); 718 719 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 720 { 721 return &tp->pci_dev->dev; 722 } 723 724 static void rtl_lock_work(struct rtl8169_private *tp) 725 { 726 mutex_lock(&tp->wk.mutex); 727 } 728 729 static void rtl_unlock_work(struct rtl8169_private *tp) 730 { 731 mutex_unlock(&tp->wk.mutex); 732 } 733 734 static void rtl_lock_config_regs(struct rtl8169_private *tp) 735 { 736 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 737 } 738 739 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 740 { 741 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 742 } 743 744 static bool rtl_is_8125(struct rtl8169_private *tp) 745 { 746 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 747 } 748 749 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 750 { 751 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 752 tp->mac_version != RTL_GIGA_MAC_VER_39 && 753 tp->mac_version <= RTL_GIGA_MAC_VER_51; 754 } 755 756 static bool rtl_supports_eee(struct rtl8169_private *tp) 757 { 758 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 759 tp->mac_version != RTL_GIGA_MAC_VER_37 && 760 tp->mac_version != RTL_GIGA_MAC_VER_39; 761 } 762 763 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 764 { 765 int i; 766 767 for (i = 0; i < ETH_ALEN; i++) 768 mac[i] = RTL_R8(tp, reg + i); 769 } 770 771 struct rtl_cond { 772 bool (*check)(struct rtl8169_private *); 773 const char *msg; 774 }; 775 776 static void rtl_udelay(unsigned int d) 777 { 778 udelay(d); 779 } 780 781 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 782 void (*delay)(unsigned int), unsigned int d, int n, 783 bool high) 784 { 785 int i; 786 787 for (i = 0; i < n; i++) { 788 if (c->check(tp) == high) 789 return true; 790 delay(d); 791 } 792 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", 793 c->msg, !high, n, d); 794 return false; 795 } 796 797 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 798 const struct rtl_cond *c, 799 unsigned int d, int n) 800 { 801 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 802 } 803 804 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 805 const struct rtl_cond *c, 806 unsigned int d, int n) 807 { 808 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 809 } 810 811 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 812 const struct rtl_cond *c, 813 unsigned int d, int n) 814 { 815 return rtl_loop_wait(tp, c, msleep, d, n, true); 816 } 817 818 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 819 const struct rtl_cond *c, 820 unsigned int d, int n) 821 { 822 return rtl_loop_wait(tp, c, msleep, d, n, false); 823 } 824 825 #define DECLARE_RTL_COND(name) \ 826 static bool name ## _check(struct rtl8169_private *); \ 827 \ 828 static const struct rtl_cond name = { \ 829 .check = name ## _check, \ 830 .msg = #name \ 831 }; \ 832 \ 833 static bool name ## _check(struct rtl8169_private *tp) 834 835 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 836 { 837 if (reg & 0xffff0001) { 838 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); 839 return true; 840 } 841 return false; 842 } 843 844 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 845 { 846 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 847 } 848 849 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 850 { 851 if (rtl_ocp_reg_failure(tp, reg)) 852 return; 853 854 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 855 856 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 857 } 858 859 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 860 { 861 if (rtl_ocp_reg_failure(tp, reg)) 862 return 0; 863 864 RTL_W32(tp, GPHY_OCP, reg << 15); 865 866 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 867 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 868 } 869 870 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 871 { 872 if (rtl_ocp_reg_failure(tp, reg)) 873 return; 874 875 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 876 } 877 878 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 879 { 880 if (rtl_ocp_reg_failure(tp, reg)) 881 return 0; 882 883 RTL_W32(tp, OCPDR, reg << 15); 884 885 return RTL_R32(tp, OCPDR); 886 } 887 888 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 889 u16 set) 890 { 891 u16 data = r8168_mac_ocp_read(tp, reg); 892 893 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 894 } 895 896 #define OCP_STD_PHY_BASE 0xa400 897 898 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 899 { 900 if (reg == 0x1f) { 901 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 902 return; 903 } 904 905 if (tp->ocp_base != OCP_STD_PHY_BASE) 906 reg -= 0x10; 907 908 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 909 } 910 911 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 912 { 913 if (tp->ocp_base != OCP_STD_PHY_BASE) 914 reg -= 0x10; 915 916 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 917 } 918 919 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 920 { 921 if (reg == 0x1f) { 922 tp->ocp_base = value << 4; 923 return; 924 } 925 926 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 927 } 928 929 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 930 { 931 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 932 } 933 934 DECLARE_RTL_COND(rtl_phyar_cond) 935 { 936 return RTL_R32(tp, PHYAR) & 0x80000000; 937 } 938 939 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 940 { 941 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 942 943 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 944 /* 945 * According to hardware specs a 20us delay is required after write 946 * complete indication, but before sending next command. 947 */ 948 udelay(20); 949 } 950 951 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 952 { 953 int value; 954 955 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 956 957 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 958 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 959 960 /* 961 * According to hardware specs a 20us delay is required after read 962 * complete indication, but before sending next command. 963 */ 964 udelay(20); 965 966 return value; 967 } 968 969 DECLARE_RTL_COND(rtl_ocpar_cond) 970 { 971 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 972 } 973 974 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 975 { 976 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 977 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 978 RTL_W32(tp, EPHY_RXER_NUM, 0); 979 980 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 981 } 982 983 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 984 { 985 r8168dp_1_mdio_access(tp, reg, 986 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 987 } 988 989 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 990 { 991 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 992 993 mdelay(1); 994 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 995 RTL_W32(tp, EPHY_RXER_NUM, 0); 996 997 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 998 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 999 } 1000 1001 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1002 1003 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1004 { 1005 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1006 } 1007 1008 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1009 { 1010 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1011 } 1012 1013 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1014 { 1015 r8168dp_2_mdio_start(tp); 1016 1017 r8169_mdio_write(tp, reg, value); 1018 1019 r8168dp_2_mdio_stop(tp); 1020 } 1021 1022 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1023 { 1024 int value; 1025 1026 /* Work around issue with chip reporting wrong PHY ID */ 1027 if (reg == MII_PHYSID2) 1028 return 0xc912; 1029 1030 r8168dp_2_mdio_start(tp); 1031 1032 value = r8169_mdio_read(tp, reg); 1033 1034 r8168dp_2_mdio_stop(tp); 1035 1036 return value; 1037 } 1038 1039 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1040 { 1041 switch (tp->mac_version) { 1042 case RTL_GIGA_MAC_VER_27: 1043 r8168dp_1_mdio_write(tp, location, val); 1044 break; 1045 case RTL_GIGA_MAC_VER_28: 1046 case RTL_GIGA_MAC_VER_31: 1047 r8168dp_2_mdio_write(tp, location, val); 1048 break; 1049 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1050 r8168g_mdio_write(tp, location, val); 1051 break; 1052 default: 1053 r8169_mdio_write(tp, location, val); 1054 break; 1055 } 1056 } 1057 1058 static int rtl_readphy(struct rtl8169_private *tp, int location) 1059 { 1060 switch (tp->mac_version) { 1061 case RTL_GIGA_MAC_VER_27: 1062 return r8168dp_1_mdio_read(tp, location); 1063 case RTL_GIGA_MAC_VER_28: 1064 case RTL_GIGA_MAC_VER_31: 1065 return r8168dp_2_mdio_read(tp, location); 1066 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1067 return r8168g_mdio_read(tp, location); 1068 default: 1069 return r8169_mdio_read(tp, location); 1070 } 1071 } 1072 1073 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) 1074 { 1075 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); 1076 } 1077 1078 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) 1079 { 1080 int val; 1081 1082 val = rtl_readphy(tp, reg_addr); 1083 rtl_writephy(tp, reg_addr, (val & ~m) | p); 1084 } 1085 1086 DECLARE_RTL_COND(rtl_ephyar_cond) 1087 { 1088 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1089 } 1090 1091 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1092 { 1093 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1094 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1095 1096 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1097 1098 udelay(10); 1099 } 1100 1101 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1102 { 1103 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1104 1105 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1106 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1107 } 1108 1109 DECLARE_RTL_COND(rtl_eriar_cond) 1110 { 1111 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1112 } 1113 1114 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1115 u32 val, int type) 1116 { 1117 BUG_ON((addr & 3) || (mask == 0)); 1118 RTL_W32(tp, ERIDR, val); 1119 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1120 1121 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1122 } 1123 1124 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1125 u32 val) 1126 { 1127 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1128 } 1129 1130 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1131 { 1132 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1133 1134 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1135 RTL_R32(tp, ERIDR) : ~0; 1136 } 1137 1138 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1139 { 1140 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1141 } 1142 1143 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1144 u32 m) 1145 { 1146 u32 val; 1147 1148 val = rtl_eri_read(tp, addr); 1149 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1150 } 1151 1152 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1153 u32 p) 1154 { 1155 rtl_w0w1_eri(tp, addr, mask, p, 0); 1156 } 1157 1158 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1159 u32 m) 1160 { 1161 rtl_w0w1_eri(tp, addr, mask, 0, m); 1162 } 1163 1164 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1165 { 1166 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1167 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1168 RTL_R32(tp, OCPDR) : ~0; 1169 } 1170 1171 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1172 { 1173 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1174 } 1175 1176 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1177 u32 data) 1178 { 1179 RTL_W32(tp, OCPDR, data); 1180 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1181 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1182 } 1183 1184 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1185 u32 data) 1186 { 1187 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1188 data, ERIAR_OOB); 1189 } 1190 1191 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1192 { 1193 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1194 1195 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1196 } 1197 1198 #define OOB_CMD_RESET 0x00 1199 #define OOB_CMD_DRIVER_START 0x05 1200 #define OOB_CMD_DRIVER_STOP 0x06 1201 1202 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1203 { 1204 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1205 } 1206 1207 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1208 { 1209 u16 reg; 1210 1211 reg = rtl8168_get_ocp_reg(tp); 1212 1213 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1214 } 1215 1216 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1217 { 1218 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1219 } 1220 1221 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1222 { 1223 return RTL_R8(tp, IBISR0) & 0x20; 1224 } 1225 1226 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1227 { 1228 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1229 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1230 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1231 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1232 } 1233 1234 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1235 { 1236 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1237 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1238 } 1239 1240 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1241 { 1242 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1243 r8168ep_ocp_write(tp, 0x01, 0x30, 1244 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1245 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1246 } 1247 1248 static void rtl8168_driver_start(struct rtl8169_private *tp) 1249 { 1250 switch (tp->mac_version) { 1251 case RTL_GIGA_MAC_VER_27: 1252 case RTL_GIGA_MAC_VER_28: 1253 case RTL_GIGA_MAC_VER_31: 1254 rtl8168dp_driver_start(tp); 1255 break; 1256 case RTL_GIGA_MAC_VER_49: 1257 case RTL_GIGA_MAC_VER_50: 1258 case RTL_GIGA_MAC_VER_51: 1259 rtl8168ep_driver_start(tp); 1260 break; 1261 default: 1262 BUG(); 1263 break; 1264 } 1265 } 1266 1267 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1268 { 1269 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1270 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1271 } 1272 1273 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1274 { 1275 rtl8168ep_stop_cmac(tp); 1276 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1277 r8168ep_ocp_write(tp, 0x01, 0x30, 1278 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1279 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1280 } 1281 1282 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1283 { 1284 switch (tp->mac_version) { 1285 case RTL_GIGA_MAC_VER_27: 1286 case RTL_GIGA_MAC_VER_28: 1287 case RTL_GIGA_MAC_VER_31: 1288 rtl8168dp_driver_stop(tp); 1289 break; 1290 case RTL_GIGA_MAC_VER_49: 1291 case RTL_GIGA_MAC_VER_50: 1292 case RTL_GIGA_MAC_VER_51: 1293 rtl8168ep_driver_stop(tp); 1294 break; 1295 default: 1296 BUG(); 1297 break; 1298 } 1299 } 1300 1301 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1302 { 1303 u16 reg = rtl8168_get_ocp_reg(tp); 1304 1305 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1306 } 1307 1308 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1309 { 1310 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1311 } 1312 1313 static bool r8168_check_dash(struct rtl8169_private *tp) 1314 { 1315 switch (tp->mac_version) { 1316 case RTL_GIGA_MAC_VER_27: 1317 case RTL_GIGA_MAC_VER_28: 1318 case RTL_GIGA_MAC_VER_31: 1319 return r8168dp_check_dash(tp); 1320 case RTL_GIGA_MAC_VER_49: 1321 case RTL_GIGA_MAC_VER_50: 1322 case RTL_GIGA_MAC_VER_51: 1323 return r8168ep_check_dash(tp); 1324 default: 1325 return false; 1326 } 1327 } 1328 1329 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1330 { 1331 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1332 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1333 } 1334 1335 DECLARE_RTL_COND(rtl_efusear_cond) 1336 { 1337 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1338 } 1339 1340 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1341 { 1342 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1343 1344 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1345 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1346 } 1347 1348 static u32 rtl_get_events(struct rtl8169_private *tp) 1349 { 1350 if (rtl_is_8125(tp)) 1351 return RTL_R32(tp, IntrStatus_8125); 1352 else 1353 return RTL_R16(tp, IntrStatus); 1354 } 1355 1356 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1357 { 1358 if (rtl_is_8125(tp)) 1359 RTL_W32(tp, IntrStatus_8125, bits); 1360 else 1361 RTL_W16(tp, IntrStatus, bits); 1362 } 1363 1364 static void rtl_irq_disable(struct rtl8169_private *tp) 1365 { 1366 if (rtl_is_8125(tp)) 1367 RTL_W32(tp, IntrMask_8125, 0); 1368 else 1369 RTL_W16(tp, IntrMask, 0); 1370 tp->irq_enabled = 0; 1371 } 1372 1373 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) 1374 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) 1375 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) 1376 1377 static void rtl_irq_enable(struct rtl8169_private *tp) 1378 { 1379 tp->irq_enabled = 1; 1380 if (rtl_is_8125(tp)) 1381 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1382 else 1383 RTL_W16(tp, IntrMask, tp->irq_mask); 1384 } 1385 1386 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1387 { 1388 rtl_irq_disable(tp); 1389 rtl_ack_events(tp, 0xffffffff); 1390 /* PCI commit */ 1391 RTL_R8(tp, ChipCmd); 1392 } 1393 1394 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1395 { 1396 struct net_device *dev = tp->dev; 1397 struct phy_device *phydev = tp->phydev; 1398 1399 if (!netif_running(dev)) 1400 return; 1401 1402 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1403 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1404 if (phydev->speed == SPEED_1000) { 1405 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1406 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1407 } else if (phydev->speed == SPEED_100) { 1408 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1409 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1410 } else { 1411 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1412 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1413 } 1414 rtl_reset_packet_filter(tp); 1415 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1416 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1417 if (phydev->speed == SPEED_1000) { 1418 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1419 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1420 } else { 1421 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1422 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1423 } 1424 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1425 if (phydev->speed == SPEED_10) { 1426 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1427 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1428 } else { 1429 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1430 } 1431 } 1432 } 1433 1434 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1435 1436 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1437 { 1438 struct rtl8169_private *tp = netdev_priv(dev); 1439 1440 rtl_lock_work(tp); 1441 wol->supported = WAKE_ANY; 1442 wol->wolopts = tp->saved_wolopts; 1443 rtl_unlock_work(tp); 1444 } 1445 1446 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1447 { 1448 static const struct { 1449 u32 opt; 1450 u16 reg; 1451 u8 mask; 1452 } cfg[] = { 1453 { WAKE_PHY, Config3, LinkUp }, 1454 { WAKE_UCAST, Config5, UWF }, 1455 { WAKE_BCAST, Config5, BWF }, 1456 { WAKE_MCAST, Config5, MWF }, 1457 { WAKE_ANY, Config5, LanWake }, 1458 { WAKE_MAGIC, Config3, MagicPacket } 1459 }; 1460 unsigned int i, tmp = ARRAY_SIZE(cfg); 1461 u8 options; 1462 1463 rtl_unlock_config_regs(tp); 1464 1465 if (rtl_is_8168evl_up(tp)) { 1466 tmp--; 1467 if (wolopts & WAKE_MAGIC) 1468 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1469 MagicPacket_v2); 1470 else 1471 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1472 MagicPacket_v2); 1473 } else if (rtl_is_8125(tp)) { 1474 tmp--; 1475 if (wolopts & WAKE_MAGIC) 1476 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1477 else 1478 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1479 } 1480 1481 for (i = 0; i < tmp; i++) { 1482 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1483 if (wolopts & cfg[i].opt) 1484 options |= cfg[i].mask; 1485 RTL_W8(tp, cfg[i].reg, options); 1486 } 1487 1488 switch (tp->mac_version) { 1489 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1490 options = RTL_R8(tp, Config1) & ~PMEnable; 1491 if (wolopts) 1492 options |= PMEnable; 1493 RTL_W8(tp, Config1, options); 1494 break; 1495 case RTL_GIGA_MAC_VER_34: 1496 case RTL_GIGA_MAC_VER_37: 1497 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51: 1498 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1499 if (wolopts) 1500 options |= PME_SIGNAL; 1501 RTL_W8(tp, Config2, options); 1502 break; 1503 default: 1504 break; 1505 } 1506 1507 rtl_lock_config_regs(tp); 1508 1509 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1510 } 1511 1512 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1513 { 1514 struct rtl8169_private *tp = netdev_priv(dev); 1515 struct device *d = tp_to_dev(tp); 1516 1517 if (wol->wolopts & ~WAKE_ANY) 1518 return -EINVAL; 1519 1520 pm_runtime_get_noresume(d); 1521 1522 rtl_lock_work(tp); 1523 1524 tp->saved_wolopts = wol->wolopts; 1525 1526 if (pm_runtime_active(d)) 1527 __rtl8169_set_wol(tp, tp->saved_wolopts); 1528 1529 rtl_unlock_work(tp); 1530 1531 pm_runtime_put_noidle(d); 1532 1533 return 0; 1534 } 1535 1536 static void rtl8169_get_drvinfo(struct net_device *dev, 1537 struct ethtool_drvinfo *info) 1538 { 1539 struct rtl8169_private *tp = netdev_priv(dev); 1540 struct rtl_fw *rtl_fw = tp->rtl_fw; 1541 1542 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1543 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1544 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1545 if (rtl_fw) 1546 strlcpy(info->fw_version, rtl_fw->version, 1547 sizeof(info->fw_version)); 1548 } 1549 1550 static int rtl8169_get_regs_len(struct net_device *dev) 1551 { 1552 return R8169_REGS_SIZE; 1553 } 1554 1555 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1556 netdev_features_t features) 1557 { 1558 struct rtl8169_private *tp = netdev_priv(dev); 1559 1560 if (dev->mtu > TD_MSS_MAX) 1561 features &= ~NETIF_F_ALL_TSO; 1562 1563 if (dev->mtu > JUMBO_1K && 1564 tp->mac_version > RTL_GIGA_MAC_VER_06) 1565 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1566 1567 return features; 1568 } 1569 1570 static int rtl8169_set_features(struct net_device *dev, 1571 netdev_features_t features) 1572 { 1573 struct rtl8169_private *tp = netdev_priv(dev); 1574 u32 rx_config; 1575 1576 rtl_lock_work(tp); 1577 1578 rx_config = RTL_R32(tp, RxConfig); 1579 if (features & NETIF_F_RXALL) 1580 rx_config |= (AcceptErr | AcceptRunt); 1581 else 1582 rx_config &= ~(AcceptErr | AcceptRunt); 1583 1584 if (rtl_is_8125(tp)) { 1585 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1586 rx_config |= RX_VLAN_8125; 1587 else 1588 rx_config &= ~RX_VLAN_8125; 1589 } 1590 1591 RTL_W32(tp, RxConfig, rx_config); 1592 1593 if (features & NETIF_F_RXCSUM) 1594 tp->cp_cmd |= RxChkSum; 1595 else 1596 tp->cp_cmd &= ~RxChkSum; 1597 1598 if (!rtl_is_8125(tp)) { 1599 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1600 tp->cp_cmd |= RxVlan; 1601 else 1602 tp->cp_cmd &= ~RxVlan; 1603 } 1604 1605 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1606 RTL_R16(tp, CPlusCmd); 1607 1608 rtl_unlock_work(tp); 1609 1610 return 0; 1611 } 1612 1613 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1614 { 1615 return (skb_vlan_tag_present(skb)) ? 1616 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1617 } 1618 1619 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1620 { 1621 u32 opts2 = le32_to_cpu(desc->opts2); 1622 1623 if (opts2 & RxVlanTag) 1624 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1625 } 1626 1627 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1628 void *p) 1629 { 1630 struct rtl8169_private *tp = netdev_priv(dev); 1631 u32 __iomem *data = tp->mmio_addr; 1632 u32 *dw = p; 1633 int i; 1634 1635 rtl_lock_work(tp); 1636 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1637 memcpy_fromio(dw++, data++, 4); 1638 rtl_unlock_work(tp); 1639 } 1640 1641 static u32 rtl8169_get_msglevel(struct net_device *dev) 1642 { 1643 struct rtl8169_private *tp = netdev_priv(dev); 1644 1645 return tp->msg_enable; 1646 } 1647 1648 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1649 { 1650 struct rtl8169_private *tp = netdev_priv(dev); 1651 1652 tp->msg_enable = value; 1653 } 1654 1655 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1656 "tx_packets", 1657 "rx_packets", 1658 "tx_errors", 1659 "rx_errors", 1660 "rx_missed", 1661 "align_errors", 1662 "tx_single_collisions", 1663 "tx_multi_collisions", 1664 "unicast", 1665 "broadcast", 1666 "multicast", 1667 "tx_aborted", 1668 "tx_underrun", 1669 }; 1670 1671 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1672 { 1673 switch (sset) { 1674 case ETH_SS_STATS: 1675 return ARRAY_SIZE(rtl8169_gstrings); 1676 default: 1677 return -EOPNOTSUPP; 1678 } 1679 } 1680 1681 DECLARE_RTL_COND(rtl_counters_cond) 1682 { 1683 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1684 } 1685 1686 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1687 { 1688 dma_addr_t paddr = tp->counters_phys_addr; 1689 u32 cmd; 1690 1691 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1692 RTL_R32(tp, CounterAddrHigh); 1693 cmd = (u64)paddr & DMA_BIT_MASK(32); 1694 RTL_W32(tp, CounterAddrLow, cmd); 1695 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1696 1697 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1698 } 1699 1700 static bool rtl8169_reset_counters(struct rtl8169_private *tp) 1701 { 1702 /* 1703 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1704 * tally counters. 1705 */ 1706 if (tp->mac_version < RTL_GIGA_MAC_VER_19) 1707 return true; 1708 1709 return rtl8169_do_counters(tp, CounterReset); 1710 } 1711 1712 static bool rtl8169_update_counters(struct rtl8169_private *tp) 1713 { 1714 u8 val = RTL_R8(tp, ChipCmd); 1715 1716 /* 1717 * Some chips are unable to dump tally counters when the receiver 1718 * is disabled. If 0xff chip may be in a PCI power-save state. 1719 */ 1720 if (!(val & CmdRxEnb) || val == 0xff) 1721 return true; 1722 1723 return rtl8169_do_counters(tp, CounterDump); 1724 } 1725 1726 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1727 { 1728 struct rtl8169_counters *counters = tp->counters; 1729 bool ret = false; 1730 1731 /* 1732 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1733 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1734 * reset by a power cycle, while the counter values collected by the 1735 * driver are reset at every driver unload/load cycle. 1736 * 1737 * To make sure the HW values returned by @get_stats64 match the SW 1738 * values, we collect the initial values at first open(*) and use them 1739 * as offsets to normalize the values returned by @get_stats64. 1740 * 1741 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1742 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1743 * set at open time by rtl_hw_start. 1744 */ 1745 1746 if (tp->tc_offset.inited) 1747 return true; 1748 1749 /* If both, reset and update fail, propagate to caller. */ 1750 if (rtl8169_reset_counters(tp)) 1751 ret = true; 1752 1753 if (rtl8169_update_counters(tp)) 1754 ret = true; 1755 1756 tp->tc_offset.tx_errors = counters->tx_errors; 1757 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1758 tp->tc_offset.tx_aborted = counters->tx_aborted; 1759 tp->tc_offset.inited = true; 1760 1761 return ret; 1762 } 1763 1764 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1765 struct ethtool_stats *stats, u64 *data) 1766 { 1767 struct rtl8169_private *tp = netdev_priv(dev); 1768 struct device *d = tp_to_dev(tp); 1769 struct rtl8169_counters *counters = tp->counters; 1770 1771 ASSERT_RTNL(); 1772 1773 pm_runtime_get_noresume(d); 1774 1775 if (pm_runtime_active(d)) 1776 rtl8169_update_counters(tp); 1777 1778 pm_runtime_put_noidle(d); 1779 1780 data[0] = le64_to_cpu(counters->tx_packets); 1781 data[1] = le64_to_cpu(counters->rx_packets); 1782 data[2] = le64_to_cpu(counters->tx_errors); 1783 data[3] = le32_to_cpu(counters->rx_errors); 1784 data[4] = le16_to_cpu(counters->rx_missed); 1785 data[5] = le16_to_cpu(counters->align_errors); 1786 data[6] = le32_to_cpu(counters->tx_one_collision); 1787 data[7] = le32_to_cpu(counters->tx_multi_collision); 1788 data[8] = le64_to_cpu(counters->rx_unicast); 1789 data[9] = le64_to_cpu(counters->rx_broadcast); 1790 data[10] = le32_to_cpu(counters->rx_multicast); 1791 data[11] = le16_to_cpu(counters->tx_aborted); 1792 data[12] = le16_to_cpu(counters->tx_underun); 1793 } 1794 1795 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1796 { 1797 switch(stringset) { 1798 case ETH_SS_STATS: 1799 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1800 break; 1801 } 1802 } 1803 1804 /* 1805 * Interrupt coalescing 1806 * 1807 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1808 * > 8169, 8168 and 810x line of chipsets 1809 * 1810 * 8169, 8168, and 8136(810x) serial chipsets support it. 1811 * 1812 * > 2 - the Tx timer unit at gigabit speed 1813 * 1814 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1815 * (0xe0) bit 1 and bit 0. 1816 * 1817 * For 8169 1818 * bit[1:0] \ speed 1000M 100M 10M 1819 * 0 0 320ns 2.56us 40.96us 1820 * 0 1 2.56us 20.48us 327.7us 1821 * 1 0 5.12us 40.96us 655.4us 1822 * 1 1 10.24us 81.92us 1.31ms 1823 * 1824 * For the other 1825 * bit[1:0] \ speed 1000M 100M 10M 1826 * 0 0 5us 2.56us 40.96us 1827 * 0 1 40us 20.48us 327.7us 1828 * 1 0 80us 40.96us 655.4us 1829 * 1 1 160us 81.92us 1.31ms 1830 */ 1831 1832 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ 1833 struct rtl_coalesce_scale { 1834 /* Rx / Tx */ 1835 u32 nsecs[2]; 1836 }; 1837 1838 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1839 struct rtl_coalesce_info { 1840 u32 speed; 1841 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ 1842 }; 1843 1844 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ 1845 #define rxtx_x1822(r, t) { \ 1846 {{(r), (t)}}, \ 1847 {{(r)*8, (t)*8}}, \ 1848 {{(r)*8*2, (t)*8*2}}, \ 1849 {{(r)*8*2*2, (t)*8*2*2}}, \ 1850 } 1851 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1852 /* speed delays: rx00 tx00 */ 1853 { SPEED_10, rxtx_x1822(40960, 40960) }, 1854 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1855 { SPEED_1000, rxtx_x1822( 320, 320) }, 1856 { 0 }, 1857 }; 1858 1859 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1860 /* speed delays: rx00 tx00 */ 1861 { SPEED_10, rxtx_x1822(40960, 40960) }, 1862 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1863 { SPEED_1000, rxtx_x1822( 5000, 5000) }, 1864 { 0 }, 1865 }; 1866 #undef rxtx_x1822 1867 1868 /* get rx/tx scale vector corresponding to current speed */ 1869 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) 1870 { 1871 struct rtl8169_private *tp = netdev_priv(dev); 1872 const struct rtl_coalesce_info *ci; 1873 1874 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1875 ci = rtl_coalesce_info_8169; 1876 else 1877 ci = rtl_coalesce_info_8168_8136; 1878 1879 for (; ci->speed; ci++) { 1880 if (tp->phydev->speed == ci->speed) 1881 return ci; 1882 } 1883 1884 return ERR_PTR(-ELNRNG); 1885 } 1886 1887 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1888 { 1889 struct rtl8169_private *tp = netdev_priv(dev); 1890 const struct rtl_coalesce_info *ci; 1891 const struct rtl_coalesce_scale *scale; 1892 struct { 1893 u32 *max_frames; 1894 u32 *usecs; 1895 } coal_settings [] = { 1896 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, 1897 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } 1898 }, *p = coal_settings; 1899 int i; 1900 u16 w; 1901 1902 if (rtl_is_8125(tp)) 1903 return -EOPNOTSUPP; 1904 1905 memset(ec, 0, sizeof(*ec)); 1906 1907 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1908 ci = rtl_coalesce_info(dev); 1909 if (IS_ERR(ci)) 1910 return PTR_ERR(ci); 1911 1912 scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; 1913 1914 /* read IntrMitigate and adjust according to scale */ 1915 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { 1916 *p->max_frames = (w & RTL_COALESCE_MASK) << 2; 1917 w >>= RTL_COALESCE_SHIFT; 1918 *p->usecs = w & RTL_COALESCE_MASK; 1919 } 1920 1921 for (i = 0; i < 2; i++) { 1922 p = coal_settings + i; 1923 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; 1924 1925 /* 1926 * ethtool_coalesce says it is illegal to set both usecs and 1927 * max_frames to 0. 1928 */ 1929 if (!*p->usecs && !*p->max_frames) 1930 *p->max_frames = 1; 1931 } 1932 1933 return 0; 1934 } 1935 1936 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ 1937 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( 1938 struct net_device *dev, u32 nsec, u16 *cp01) 1939 { 1940 const struct rtl_coalesce_info *ci; 1941 u16 i; 1942 1943 ci = rtl_coalesce_info(dev); 1944 if (IS_ERR(ci)) 1945 return ERR_CAST(ci); 1946 1947 for (i = 0; i < 4; i++) { 1948 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], 1949 ci->scalev[i].nsecs[1]); 1950 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { 1951 *cp01 = i; 1952 return &ci->scalev[i]; 1953 } 1954 } 1955 1956 return ERR_PTR(-EINVAL); 1957 } 1958 1959 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1960 { 1961 struct rtl8169_private *tp = netdev_priv(dev); 1962 const struct rtl_coalesce_scale *scale; 1963 struct { 1964 u32 frames; 1965 u32 usecs; 1966 } coal_settings [] = { 1967 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, 1968 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } 1969 }, *p = coal_settings; 1970 u16 w = 0, cp01; 1971 int i; 1972 1973 if (rtl_is_8125(tp)) 1974 return -EOPNOTSUPP; 1975 1976 scale = rtl_coalesce_choose_scale(dev, 1977 max(p[0].usecs, p[1].usecs) * 1000, &cp01); 1978 if (IS_ERR(scale)) 1979 return PTR_ERR(scale); 1980 1981 for (i = 0; i < 2; i++, p++) { 1982 u32 units; 1983 1984 /* 1985 * accept max_frames=1 we returned in rtl_get_coalesce. 1986 * accept it not only when usecs=0 because of e.g. the following scenario: 1987 * 1988 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1989 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1990 * - then user does `ethtool -C eth0 rx-usecs 100` 1991 * 1992 * since ethtool sends to kernel whole ethtool_coalesce 1993 * settings, if we do not handle rx_usecs=!0, rx_frames=1 1994 * we'll reject it below in `frames % 4 != 0`. 1995 */ 1996 if (p->frames == 1) { 1997 p->frames = 0; 1998 } 1999 2000 units = p->usecs * 1000 / scale->nsecs[i]; 2001 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) 2002 return -EINVAL; 2003 2004 w <<= RTL_COALESCE_SHIFT; 2005 w |= units; 2006 w <<= RTL_COALESCE_SHIFT; 2007 w |= p->frames >> 2; 2008 } 2009 2010 rtl_lock_work(tp); 2011 2012 RTL_W16(tp, IntrMitigate, swab16(w)); 2013 2014 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2015 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2016 RTL_R16(tp, CPlusCmd); 2017 2018 rtl_unlock_work(tp); 2019 2020 return 0; 2021 } 2022 2023 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 2024 { 2025 struct rtl8169_private *tp = netdev_priv(dev); 2026 struct device *d = tp_to_dev(tp); 2027 int ret; 2028 2029 if (!rtl_supports_eee(tp)) 2030 return -EOPNOTSUPP; 2031 2032 pm_runtime_get_noresume(d); 2033 2034 if (!pm_runtime_active(d)) { 2035 ret = -EOPNOTSUPP; 2036 } else { 2037 ret = phy_ethtool_get_eee(tp->phydev, data); 2038 } 2039 2040 pm_runtime_put_noidle(d); 2041 2042 return ret; 2043 } 2044 2045 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 2046 { 2047 struct rtl8169_private *tp = netdev_priv(dev); 2048 struct device *d = tp_to_dev(tp); 2049 int ret; 2050 2051 if (!rtl_supports_eee(tp)) 2052 return -EOPNOTSUPP; 2053 2054 pm_runtime_get_noresume(d); 2055 2056 if (!pm_runtime_active(d)) { 2057 ret = -EOPNOTSUPP; 2058 goto out; 2059 } 2060 2061 if (dev->phydev->autoneg == AUTONEG_DISABLE || 2062 dev->phydev->duplex != DUPLEX_FULL) { 2063 ret = -EPROTONOSUPPORT; 2064 goto out; 2065 } 2066 2067 ret = phy_ethtool_set_eee(tp->phydev, data); 2068 out: 2069 pm_runtime_put_noidle(d); 2070 return ret; 2071 } 2072 2073 static const struct ethtool_ops rtl8169_ethtool_ops = { 2074 .get_drvinfo = rtl8169_get_drvinfo, 2075 .get_regs_len = rtl8169_get_regs_len, 2076 .get_link = ethtool_op_get_link, 2077 .get_coalesce = rtl_get_coalesce, 2078 .set_coalesce = rtl_set_coalesce, 2079 .get_msglevel = rtl8169_get_msglevel, 2080 .set_msglevel = rtl8169_set_msglevel, 2081 .get_regs = rtl8169_get_regs, 2082 .get_wol = rtl8169_get_wol, 2083 .set_wol = rtl8169_set_wol, 2084 .get_strings = rtl8169_get_strings, 2085 .get_sset_count = rtl8169_get_sset_count, 2086 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2087 .get_ts_info = ethtool_op_get_ts_info, 2088 .nway_reset = phy_ethtool_nway_reset, 2089 .get_eee = rtl8169_get_eee, 2090 .set_eee = rtl8169_set_eee, 2091 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2092 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2093 }; 2094 2095 static void rtl_enable_eee(struct rtl8169_private *tp) 2096 { 2097 struct phy_device *phydev = tp->phydev; 2098 int supported = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 2099 2100 if (supported > 0) 2101 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, supported); 2102 } 2103 2104 static void rtl8169_get_mac_version(struct rtl8169_private *tp) 2105 { 2106 /* 2107 * The driver currently handles the 8168Bf and the 8168Be identically 2108 * but they can be identified more specifically through the test below 2109 * if needed: 2110 * 2111 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2112 * 2113 * Same thing for the 8101Eb and the 8101Ec: 2114 * 2115 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2116 */ 2117 static const struct rtl_mac_info { 2118 u16 mask; 2119 u16 val; 2120 u16 mac_version; 2121 } mac_info[] = { 2122 /* 8125 family. */ 2123 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2124 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2125 2126 /* 8168EP family. */ 2127 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2128 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2129 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2130 2131 /* 8168H family. */ 2132 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2133 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2134 2135 /* 8168G family. */ 2136 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2137 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2138 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2139 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2140 2141 /* 8168F family. */ 2142 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2143 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2144 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2145 2146 /* 8168E family. */ 2147 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2148 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2149 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2150 2151 /* 8168D family. */ 2152 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2153 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2154 2155 /* 8168DP family. */ 2156 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2157 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2158 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2159 2160 /* 8168C family. */ 2161 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2162 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2163 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2164 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2165 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2166 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2167 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2168 2169 /* 8168B family. */ 2170 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2171 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2172 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2173 2174 /* 8101 family. */ 2175 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2176 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2177 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2178 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2179 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2180 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2181 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2182 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2183 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2184 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2185 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2186 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2187 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2188 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2189 /* FIXME: where did these entries come from ? -- FR */ 2190 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2191 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2192 2193 /* 8110 family. */ 2194 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2195 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2196 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2197 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2198 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2199 2200 /* Catch-all */ 2201 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2202 }; 2203 const struct rtl_mac_info *p = mac_info; 2204 u16 reg = RTL_R32(tp, TxConfig) >> 20; 2205 2206 while ((reg & p->mask) != p->val) 2207 p++; 2208 tp->mac_version = p->mac_version; 2209 2210 if (tp->mac_version == RTL_GIGA_MAC_NONE) { 2211 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf); 2212 } else if (!tp->supports_gmii) { 2213 if (tp->mac_version == RTL_GIGA_MAC_VER_42) 2214 tp->mac_version = RTL_GIGA_MAC_VER_43; 2215 else if (tp->mac_version == RTL_GIGA_MAC_VER_45) 2216 tp->mac_version = RTL_GIGA_MAC_VER_47; 2217 else if (tp->mac_version == RTL_GIGA_MAC_VER_46) 2218 tp->mac_version = RTL_GIGA_MAC_VER_48; 2219 } 2220 } 2221 2222 struct phy_reg { 2223 u16 reg; 2224 u16 val; 2225 }; 2226 2227 static void __rtl_writephy_batch(struct rtl8169_private *tp, 2228 const struct phy_reg *regs, int len) 2229 { 2230 while (len-- > 0) { 2231 rtl_writephy(tp, regs->reg, regs->val); 2232 regs++; 2233 } 2234 } 2235 2236 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a)) 2237 2238 static void rtl_release_firmware(struct rtl8169_private *tp) 2239 { 2240 if (tp->rtl_fw) { 2241 rtl_fw_release_firmware(tp->rtl_fw); 2242 kfree(tp->rtl_fw); 2243 tp->rtl_fw = NULL; 2244 } 2245 } 2246 2247 static void rtl_apply_firmware(struct rtl8169_private *tp) 2248 { 2249 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2250 if (tp->rtl_fw) 2251 rtl_fw_write_firmware(tp, tp->rtl_fw); 2252 } 2253 2254 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) 2255 { 2256 if (rtl_readphy(tp, reg) != val) 2257 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); 2258 else 2259 rtl_apply_firmware(tp); 2260 } 2261 2262 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2263 { 2264 /* Adjust EEE LED frequency */ 2265 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2266 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2267 2268 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2269 } 2270 2271 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2272 { 2273 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2274 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2275 } 2276 2277 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp) 2278 { 2279 struct phy_device *phydev = tp->phydev; 2280 2281 phy_write(phydev, 0x1f, 0x0007); 2282 phy_write(phydev, 0x1e, 0x0020); 2283 phy_set_bits(phydev, 0x15, BIT(8)); 2284 2285 phy_write(phydev, 0x1f, 0x0005); 2286 phy_write(phydev, 0x05, 0x8b85); 2287 phy_set_bits(phydev, 0x06, BIT(13)); 2288 2289 phy_write(phydev, 0x1f, 0x0000); 2290 } 2291 2292 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp) 2293 { 2294 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4)); 2295 } 2296 2297 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp) 2298 { 2299 struct phy_device *phydev = tp->phydev; 2300 2301 rtl8168g_config_eee_phy(tp); 2302 2303 phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200); 2304 phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080); 2305 } 2306 2307 static void rtl8125_config_eee_phy(struct rtl8169_private *tp) 2308 { 2309 struct phy_device *phydev = tp->phydev; 2310 2311 rtl8168h_config_eee_phy(tp); 2312 2313 phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000); 2314 phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000); 2315 } 2316 2317 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) 2318 { 2319 static const struct phy_reg phy_reg_init[] = { 2320 { 0x1f, 0x0001 }, 2321 { 0x06, 0x006e }, 2322 { 0x08, 0x0708 }, 2323 { 0x15, 0x4000 }, 2324 { 0x18, 0x65c7 }, 2325 2326 { 0x1f, 0x0001 }, 2327 { 0x03, 0x00a1 }, 2328 { 0x02, 0x0008 }, 2329 { 0x01, 0x0120 }, 2330 { 0x00, 0x1000 }, 2331 { 0x04, 0x0800 }, 2332 { 0x04, 0x0000 }, 2333 2334 { 0x03, 0xff41 }, 2335 { 0x02, 0xdf60 }, 2336 { 0x01, 0x0140 }, 2337 { 0x00, 0x0077 }, 2338 { 0x04, 0x7800 }, 2339 { 0x04, 0x7000 }, 2340 2341 { 0x03, 0x802f }, 2342 { 0x02, 0x4f02 }, 2343 { 0x01, 0x0409 }, 2344 { 0x00, 0xf0f9 }, 2345 { 0x04, 0x9800 }, 2346 { 0x04, 0x9000 }, 2347 2348 { 0x03, 0xdf01 }, 2349 { 0x02, 0xdf20 }, 2350 { 0x01, 0xff95 }, 2351 { 0x00, 0xba00 }, 2352 { 0x04, 0xa800 }, 2353 { 0x04, 0xa000 }, 2354 2355 { 0x03, 0xff41 }, 2356 { 0x02, 0xdf20 }, 2357 { 0x01, 0x0140 }, 2358 { 0x00, 0x00bb }, 2359 { 0x04, 0xb800 }, 2360 { 0x04, 0xb000 }, 2361 2362 { 0x03, 0xdf41 }, 2363 { 0x02, 0xdc60 }, 2364 { 0x01, 0x6340 }, 2365 { 0x00, 0x007d }, 2366 { 0x04, 0xd800 }, 2367 { 0x04, 0xd000 }, 2368 2369 { 0x03, 0xdf01 }, 2370 { 0x02, 0xdf20 }, 2371 { 0x01, 0x100a }, 2372 { 0x00, 0xa0ff }, 2373 { 0x04, 0xf800 }, 2374 { 0x04, 0xf000 }, 2375 2376 { 0x1f, 0x0000 }, 2377 { 0x0b, 0x0000 }, 2378 { 0x00, 0x9200 } 2379 }; 2380 2381 rtl_writephy_batch(tp, phy_reg_init); 2382 } 2383 2384 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) 2385 { 2386 static const struct phy_reg phy_reg_init[] = { 2387 { 0x1f, 0x0002 }, 2388 { 0x01, 0x90d0 }, 2389 { 0x1f, 0x0000 } 2390 }; 2391 2392 rtl_writephy_batch(tp, phy_reg_init); 2393 } 2394 2395 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) 2396 { 2397 struct pci_dev *pdev = tp->pci_dev; 2398 2399 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || 2400 (pdev->subsystem_device != 0xe000)) 2401 return; 2402 2403 rtl_writephy(tp, 0x1f, 0x0001); 2404 rtl_writephy(tp, 0x10, 0xf01b); 2405 rtl_writephy(tp, 0x1f, 0x0000); 2406 } 2407 2408 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) 2409 { 2410 static const struct phy_reg phy_reg_init[] = { 2411 { 0x1f, 0x0001 }, 2412 { 0x04, 0x0000 }, 2413 { 0x03, 0x00a1 }, 2414 { 0x02, 0x0008 }, 2415 { 0x01, 0x0120 }, 2416 { 0x00, 0x1000 }, 2417 { 0x04, 0x0800 }, 2418 { 0x04, 0x9000 }, 2419 { 0x03, 0x802f }, 2420 { 0x02, 0x4f02 }, 2421 { 0x01, 0x0409 }, 2422 { 0x00, 0xf099 }, 2423 { 0x04, 0x9800 }, 2424 { 0x04, 0xa000 }, 2425 { 0x03, 0xdf01 }, 2426 { 0x02, 0xdf20 }, 2427 { 0x01, 0xff95 }, 2428 { 0x00, 0xba00 }, 2429 { 0x04, 0xa800 }, 2430 { 0x04, 0xf000 }, 2431 { 0x03, 0xdf01 }, 2432 { 0x02, 0xdf20 }, 2433 { 0x01, 0x101a }, 2434 { 0x00, 0xa0ff }, 2435 { 0x04, 0xf800 }, 2436 { 0x04, 0x0000 }, 2437 { 0x1f, 0x0000 }, 2438 2439 { 0x1f, 0x0001 }, 2440 { 0x10, 0xf41b }, 2441 { 0x14, 0xfb54 }, 2442 { 0x18, 0xf5c7 }, 2443 { 0x1f, 0x0000 }, 2444 2445 { 0x1f, 0x0001 }, 2446 { 0x17, 0x0cc0 }, 2447 { 0x1f, 0x0000 } 2448 }; 2449 2450 rtl_writephy_batch(tp, phy_reg_init); 2451 2452 rtl8169scd_hw_phy_config_quirk(tp); 2453 } 2454 2455 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) 2456 { 2457 static const struct phy_reg phy_reg_init[] = { 2458 { 0x1f, 0x0001 }, 2459 { 0x04, 0x0000 }, 2460 { 0x03, 0x00a1 }, 2461 { 0x02, 0x0008 }, 2462 { 0x01, 0x0120 }, 2463 { 0x00, 0x1000 }, 2464 { 0x04, 0x0800 }, 2465 { 0x04, 0x9000 }, 2466 { 0x03, 0x802f }, 2467 { 0x02, 0x4f02 }, 2468 { 0x01, 0x0409 }, 2469 { 0x00, 0xf099 }, 2470 { 0x04, 0x9800 }, 2471 { 0x04, 0xa000 }, 2472 { 0x03, 0xdf01 }, 2473 { 0x02, 0xdf20 }, 2474 { 0x01, 0xff95 }, 2475 { 0x00, 0xba00 }, 2476 { 0x04, 0xa800 }, 2477 { 0x04, 0xf000 }, 2478 { 0x03, 0xdf01 }, 2479 { 0x02, 0xdf20 }, 2480 { 0x01, 0x101a }, 2481 { 0x00, 0xa0ff }, 2482 { 0x04, 0xf800 }, 2483 { 0x04, 0x0000 }, 2484 { 0x1f, 0x0000 }, 2485 2486 { 0x1f, 0x0001 }, 2487 { 0x0b, 0x8480 }, 2488 { 0x1f, 0x0000 }, 2489 2490 { 0x1f, 0x0001 }, 2491 { 0x18, 0x67c7 }, 2492 { 0x04, 0x2000 }, 2493 { 0x03, 0x002f }, 2494 { 0x02, 0x4360 }, 2495 { 0x01, 0x0109 }, 2496 { 0x00, 0x3022 }, 2497 { 0x04, 0x2800 }, 2498 { 0x1f, 0x0000 }, 2499 2500 { 0x1f, 0x0001 }, 2501 { 0x17, 0x0cc0 }, 2502 { 0x1f, 0x0000 } 2503 }; 2504 2505 rtl_writephy_batch(tp, phy_reg_init); 2506 } 2507 2508 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) 2509 { 2510 static const struct phy_reg phy_reg_init[] = { 2511 { 0x10, 0xf41b }, 2512 { 0x1f, 0x0000 } 2513 }; 2514 2515 rtl_writephy(tp, 0x1f, 0x0001); 2516 rtl_patchphy(tp, 0x16, 1 << 0); 2517 2518 rtl_writephy_batch(tp, phy_reg_init); 2519 } 2520 2521 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) 2522 { 2523 static const struct phy_reg phy_reg_init[] = { 2524 { 0x1f, 0x0001 }, 2525 { 0x10, 0xf41b }, 2526 { 0x1f, 0x0000 } 2527 }; 2528 2529 rtl_writephy_batch(tp, phy_reg_init); 2530 } 2531 2532 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) 2533 { 2534 static const struct phy_reg phy_reg_init[] = { 2535 { 0x1f, 0x0000 }, 2536 { 0x1d, 0x0f00 }, 2537 { 0x1f, 0x0002 }, 2538 { 0x0c, 0x1ec8 }, 2539 { 0x1f, 0x0000 } 2540 }; 2541 2542 rtl_writephy_batch(tp, phy_reg_init); 2543 } 2544 2545 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) 2546 { 2547 static const struct phy_reg phy_reg_init[] = { 2548 { 0x1f, 0x0001 }, 2549 { 0x1d, 0x3d98 }, 2550 { 0x1f, 0x0000 } 2551 }; 2552 2553 rtl_writephy(tp, 0x1f, 0x0000); 2554 rtl_patchphy(tp, 0x14, 1 << 5); 2555 rtl_patchphy(tp, 0x0d, 1 << 5); 2556 2557 rtl_writephy_batch(tp, phy_reg_init); 2558 } 2559 2560 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) 2561 { 2562 static const struct phy_reg phy_reg_init[] = { 2563 { 0x1f, 0x0001 }, 2564 { 0x12, 0x2300 }, 2565 { 0x1f, 0x0002 }, 2566 { 0x00, 0x88d4 }, 2567 { 0x01, 0x82b1 }, 2568 { 0x03, 0x7002 }, 2569 { 0x08, 0x9e30 }, 2570 { 0x09, 0x01f0 }, 2571 { 0x0a, 0x5500 }, 2572 { 0x0c, 0x00c8 }, 2573 { 0x1f, 0x0003 }, 2574 { 0x12, 0xc096 }, 2575 { 0x16, 0x000a }, 2576 { 0x1f, 0x0000 }, 2577 { 0x1f, 0x0000 }, 2578 { 0x09, 0x2000 }, 2579 { 0x09, 0x0000 } 2580 }; 2581 2582 rtl_writephy_batch(tp, phy_reg_init); 2583 2584 rtl_patchphy(tp, 0x14, 1 << 5); 2585 rtl_patchphy(tp, 0x0d, 1 << 5); 2586 rtl_writephy(tp, 0x1f, 0x0000); 2587 } 2588 2589 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) 2590 { 2591 static const struct phy_reg phy_reg_init[] = { 2592 { 0x1f, 0x0001 }, 2593 { 0x12, 0x2300 }, 2594 { 0x03, 0x802f }, 2595 { 0x02, 0x4f02 }, 2596 { 0x01, 0x0409 }, 2597 { 0x00, 0xf099 }, 2598 { 0x04, 0x9800 }, 2599 { 0x04, 0x9000 }, 2600 { 0x1d, 0x3d98 }, 2601 { 0x1f, 0x0002 }, 2602 { 0x0c, 0x7eb8 }, 2603 { 0x06, 0x0761 }, 2604 { 0x1f, 0x0003 }, 2605 { 0x16, 0x0f0a }, 2606 { 0x1f, 0x0000 } 2607 }; 2608 2609 rtl_writephy_batch(tp, phy_reg_init); 2610 2611 rtl_patchphy(tp, 0x16, 1 << 0); 2612 rtl_patchphy(tp, 0x14, 1 << 5); 2613 rtl_patchphy(tp, 0x0d, 1 << 5); 2614 rtl_writephy(tp, 0x1f, 0x0000); 2615 } 2616 2617 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) 2618 { 2619 static const struct phy_reg phy_reg_init[] = { 2620 { 0x1f, 0x0001 }, 2621 { 0x12, 0x2300 }, 2622 { 0x1d, 0x3d98 }, 2623 { 0x1f, 0x0002 }, 2624 { 0x0c, 0x7eb8 }, 2625 { 0x06, 0x5461 }, 2626 { 0x1f, 0x0003 }, 2627 { 0x16, 0x0f0a }, 2628 { 0x1f, 0x0000 } 2629 }; 2630 2631 rtl_writephy_batch(tp, phy_reg_init); 2632 2633 rtl_patchphy(tp, 0x16, 1 << 0); 2634 rtl_patchphy(tp, 0x14, 1 << 5); 2635 rtl_patchphy(tp, 0x0d, 1 << 5); 2636 rtl_writephy(tp, 0x1f, 0x0000); 2637 } 2638 2639 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) 2640 { 2641 rtl8168c_3_hw_phy_config(tp); 2642 } 2643 2644 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 2645 /* Channel Estimation */ 2646 { 0x1f, 0x0001 }, 2647 { 0x06, 0x4064 }, 2648 { 0x07, 0x2863 }, 2649 { 0x08, 0x059c }, 2650 { 0x09, 0x26b4 }, 2651 { 0x0a, 0x6a19 }, 2652 { 0x0b, 0xdcc8 }, 2653 { 0x10, 0xf06d }, 2654 { 0x14, 0x7f68 }, 2655 { 0x18, 0x7fd9 }, 2656 { 0x1c, 0xf0ff }, 2657 { 0x1d, 0x3d9c }, 2658 { 0x1f, 0x0003 }, 2659 { 0x12, 0xf49f }, 2660 { 0x13, 0x070b }, 2661 { 0x1a, 0x05ad }, 2662 { 0x14, 0x94c0 }, 2663 2664 /* 2665 * Tx Error Issue 2666 * Enhance line driver power 2667 */ 2668 { 0x1f, 0x0002 }, 2669 { 0x06, 0x5561 }, 2670 { 0x1f, 0x0005 }, 2671 { 0x05, 0x8332 }, 2672 { 0x06, 0x5561 }, 2673 2674 /* 2675 * Can not link to 1Gbps with bad cable 2676 * Decrease SNR threshold form 21.07dB to 19.04dB 2677 */ 2678 { 0x1f, 0x0001 }, 2679 { 0x17, 0x0cc0 }, 2680 2681 { 0x1f, 0x0000 }, 2682 { 0x0d, 0xf880 } 2683 }; 2684 2685 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = { 2686 { 0x1f, 0x0002 }, 2687 { 0x05, 0x669a }, 2688 { 0x1f, 0x0005 }, 2689 { 0x05, 0x8330 }, 2690 { 0x06, 0x669a }, 2691 { 0x1f, 0x0002 } 2692 }; 2693 2694 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) 2695 { 2696 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2697 2698 /* 2699 * Rx Error Issue 2700 * Fine Tune Switching regulator parameter 2701 */ 2702 rtl_writephy(tp, 0x1f, 0x0002); 2703 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef); 2704 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00); 2705 2706 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2707 int val; 2708 2709 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2710 2711 val = rtl_readphy(tp, 0x0d); 2712 2713 if ((val & 0x00ff) != 0x006c) { 2714 static const u32 set[] = { 2715 0x0065, 0x0066, 0x0067, 0x0068, 2716 0x0069, 0x006a, 0x006b, 0x006c 2717 }; 2718 int i; 2719 2720 rtl_writephy(tp, 0x1f, 0x0002); 2721 2722 val &= 0xff00; 2723 for (i = 0; i < ARRAY_SIZE(set); i++) 2724 rtl_writephy(tp, 0x0d, val | set[i]); 2725 } 2726 } else { 2727 static const struct phy_reg phy_reg_init[] = { 2728 { 0x1f, 0x0002 }, 2729 { 0x05, 0x6662 }, 2730 { 0x1f, 0x0005 }, 2731 { 0x05, 0x8330 }, 2732 { 0x06, 0x6662 } 2733 }; 2734 2735 rtl_writephy_batch(tp, phy_reg_init); 2736 } 2737 2738 /* RSET couple improve */ 2739 rtl_writephy(tp, 0x1f, 0x0002); 2740 rtl_patchphy(tp, 0x0d, 0x0300); 2741 rtl_patchphy(tp, 0x0f, 0x0010); 2742 2743 /* Fine tune PLL performance */ 2744 rtl_writephy(tp, 0x1f, 0x0002); 2745 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2746 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2747 2748 rtl_writephy(tp, 0x1f, 0x0005); 2749 rtl_writephy(tp, 0x05, 0x001b); 2750 2751 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); 2752 2753 rtl_writephy(tp, 0x1f, 0x0000); 2754 } 2755 2756 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) 2757 { 2758 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2759 2760 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2761 int val; 2762 2763 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2764 2765 val = rtl_readphy(tp, 0x0d); 2766 if ((val & 0x00ff) != 0x006c) { 2767 static const u32 set[] = { 2768 0x0065, 0x0066, 0x0067, 0x0068, 2769 0x0069, 0x006a, 0x006b, 0x006c 2770 }; 2771 int i; 2772 2773 rtl_writephy(tp, 0x1f, 0x0002); 2774 2775 val &= 0xff00; 2776 for (i = 0; i < ARRAY_SIZE(set); i++) 2777 rtl_writephy(tp, 0x0d, val | set[i]); 2778 } 2779 } else { 2780 static const struct phy_reg phy_reg_init[] = { 2781 { 0x1f, 0x0002 }, 2782 { 0x05, 0x2642 }, 2783 { 0x1f, 0x0005 }, 2784 { 0x05, 0x8330 }, 2785 { 0x06, 0x2642 } 2786 }; 2787 2788 rtl_writephy_batch(tp, phy_reg_init); 2789 } 2790 2791 /* Fine tune PLL performance */ 2792 rtl_writephy(tp, 0x1f, 0x0002); 2793 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2794 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2795 2796 /* Switching regulator Slew rate */ 2797 rtl_writephy(tp, 0x1f, 0x0002); 2798 rtl_patchphy(tp, 0x0f, 0x0017); 2799 2800 rtl_writephy(tp, 0x1f, 0x0005); 2801 rtl_writephy(tp, 0x05, 0x001b); 2802 2803 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); 2804 2805 rtl_writephy(tp, 0x1f, 0x0000); 2806 } 2807 2808 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) 2809 { 2810 static const struct phy_reg phy_reg_init[] = { 2811 { 0x1f, 0x0002 }, 2812 { 0x10, 0x0008 }, 2813 { 0x0d, 0x006c }, 2814 2815 { 0x1f, 0x0000 }, 2816 { 0x0d, 0xf880 }, 2817 2818 { 0x1f, 0x0001 }, 2819 { 0x17, 0x0cc0 }, 2820 2821 { 0x1f, 0x0001 }, 2822 { 0x0b, 0xa4d8 }, 2823 { 0x09, 0x281c }, 2824 { 0x07, 0x2883 }, 2825 { 0x0a, 0x6b35 }, 2826 { 0x1d, 0x3da4 }, 2827 { 0x1c, 0xeffd }, 2828 { 0x14, 0x7f52 }, 2829 { 0x18, 0x7fc6 }, 2830 { 0x08, 0x0601 }, 2831 { 0x06, 0x4063 }, 2832 { 0x10, 0xf074 }, 2833 { 0x1f, 0x0003 }, 2834 { 0x13, 0x0789 }, 2835 { 0x12, 0xf4bd }, 2836 { 0x1a, 0x04fd }, 2837 { 0x14, 0x84b0 }, 2838 { 0x1f, 0x0000 }, 2839 { 0x00, 0x9200 }, 2840 2841 { 0x1f, 0x0005 }, 2842 { 0x01, 0x0340 }, 2843 { 0x1f, 0x0001 }, 2844 { 0x04, 0x4000 }, 2845 { 0x03, 0x1d21 }, 2846 { 0x02, 0x0c32 }, 2847 { 0x01, 0x0200 }, 2848 { 0x00, 0x5554 }, 2849 { 0x04, 0x4800 }, 2850 { 0x04, 0x4000 }, 2851 { 0x04, 0xf000 }, 2852 { 0x03, 0xdf01 }, 2853 { 0x02, 0xdf20 }, 2854 { 0x01, 0x101a }, 2855 { 0x00, 0xa0ff }, 2856 { 0x04, 0xf800 }, 2857 { 0x04, 0xf000 }, 2858 { 0x1f, 0x0000 }, 2859 2860 { 0x1f, 0x0007 }, 2861 { 0x1e, 0x0023 }, 2862 { 0x16, 0x0000 }, 2863 { 0x1f, 0x0000 } 2864 }; 2865 2866 rtl_writephy_batch(tp, phy_reg_init); 2867 } 2868 2869 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) 2870 { 2871 static const struct phy_reg phy_reg_init[] = { 2872 { 0x1f, 0x0001 }, 2873 { 0x17, 0x0cc0 }, 2874 2875 { 0x1f, 0x0007 }, 2876 { 0x1e, 0x002d }, 2877 { 0x18, 0x0040 }, 2878 { 0x1f, 0x0000 } 2879 }; 2880 2881 rtl_writephy_batch(tp, phy_reg_init); 2882 rtl_patchphy(tp, 0x0d, 1 << 5); 2883 } 2884 2885 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) 2886 { 2887 static const struct phy_reg phy_reg_init[] = { 2888 /* Enable Delay cap */ 2889 { 0x1f, 0x0005 }, 2890 { 0x05, 0x8b80 }, 2891 { 0x06, 0xc896 }, 2892 { 0x1f, 0x0000 }, 2893 2894 /* Channel estimation fine tune */ 2895 { 0x1f, 0x0001 }, 2896 { 0x0b, 0x6c20 }, 2897 { 0x07, 0x2872 }, 2898 { 0x1c, 0xefff }, 2899 { 0x1f, 0x0003 }, 2900 { 0x14, 0x6420 }, 2901 { 0x1f, 0x0000 }, 2902 2903 /* Update PFM & 10M TX idle timer */ 2904 { 0x1f, 0x0007 }, 2905 { 0x1e, 0x002f }, 2906 { 0x15, 0x1919 }, 2907 { 0x1f, 0x0000 }, 2908 2909 { 0x1f, 0x0007 }, 2910 { 0x1e, 0x00ac }, 2911 { 0x18, 0x0006 }, 2912 { 0x1f, 0x0000 } 2913 }; 2914 2915 rtl_apply_firmware(tp); 2916 2917 rtl_writephy_batch(tp, phy_reg_init); 2918 2919 /* DCO enable for 10M IDLE Power */ 2920 rtl_writephy(tp, 0x1f, 0x0007); 2921 rtl_writephy(tp, 0x1e, 0x0023); 2922 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 2923 rtl_writephy(tp, 0x1f, 0x0000); 2924 2925 /* For impedance matching */ 2926 rtl_writephy(tp, 0x1f, 0x0002); 2927 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00); 2928 rtl_writephy(tp, 0x1f, 0x0000); 2929 2930 /* PHY auto speed down */ 2931 rtl_writephy(tp, 0x1f, 0x0007); 2932 rtl_writephy(tp, 0x1e, 0x002d); 2933 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000); 2934 rtl_writephy(tp, 0x1f, 0x0000); 2935 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 2936 2937 rtl_writephy(tp, 0x1f, 0x0005); 2938 rtl_writephy(tp, 0x05, 0x8b86); 2939 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 2940 rtl_writephy(tp, 0x1f, 0x0000); 2941 2942 rtl_writephy(tp, 0x1f, 0x0005); 2943 rtl_writephy(tp, 0x05, 0x8b85); 2944 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); 2945 rtl_writephy(tp, 0x1f, 0x0007); 2946 rtl_writephy(tp, 0x1e, 0x0020); 2947 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100); 2948 rtl_writephy(tp, 0x1f, 0x0006); 2949 rtl_writephy(tp, 0x00, 0x5a00); 2950 rtl_writephy(tp, 0x1f, 0x0000); 2951 rtl_writephy(tp, 0x0d, 0x0007); 2952 rtl_writephy(tp, 0x0e, 0x003c); 2953 rtl_writephy(tp, 0x0d, 0x4007); 2954 rtl_writephy(tp, 0x0e, 0x0000); 2955 rtl_writephy(tp, 0x0d, 0x0000); 2956 } 2957 2958 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2959 { 2960 const u16 w[] = { 2961 addr[0] | (addr[1] << 8), 2962 addr[2] | (addr[3] << 8), 2963 addr[4] | (addr[5] << 8) 2964 }; 2965 2966 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2967 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2968 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2969 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2970 } 2971 2972 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) 2973 { 2974 static const struct phy_reg phy_reg_init[] = { 2975 /* Enable Delay cap */ 2976 { 0x1f, 0x0004 }, 2977 { 0x1f, 0x0007 }, 2978 { 0x1e, 0x00ac }, 2979 { 0x18, 0x0006 }, 2980 { 0x1f, 0x0002 }, 2981 { 0x1f, 0x0000 }, 2982 { 0x1f, 0x0000 }, 2983 2984 /* Channel estimation fine tune */ 2985 { 0x1f, 0x0003 }, 2986 { 0x09, 0xa20f }, 2987 { 0x1f, 0x0000 }, 2988 { 0x1f, 0x0000 }, 2989 2990 /* Green Setting */ 2991 { 0x1f, 0x0005 }, 2992 { 0x05, 0x8b5b }, 2993 { 0x06, 0x9222 }, 2994 { 0x05, 0x8b6d }, 2995 { 0x06, 0x8000 }, 2996 { 0x05, 0x8b76 }, 2997 { 0x06, 0x8000 }, 2998 { 0x1f, 0x0000 } 2999 }; 3000 3001 rtl_apply_firmware(tp); 3002 3003 rtl_writephy_batch(tp, phy_reg_init); 3004 3005 /* For 4-corner performance improve */ 3006 rtl_writephy(tp, 0x1f, 0x0005); 3007 rtl_writephy(tp, 0x05, 0x8b80); 3008 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 3009 rtl_writephy(tp, 0x1f, 0x0000); 3010 3011 /* PHY auto speed down */ 3012 rtl_writephy(tp, 0x1f, 0x0004); 3013 rtl_writephy(tp, 0x1f, 0x0007); 3014 rtl_writephy(tp, 0x1e, 0x002d); 3015 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); 3016 rtl_writephy(tp, 0x1f, 0x0002); 3017 rtl_writephy(tp, 0x1f, 0x0000); 3018 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3019 3020 /* improve 10M EEE waveform */ 3021 rtl_writephy(tp, 0x1f, 0x0005); 3022 rtl_writephy(tp, 0x05, 0x8b86); 3023 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 3024 rtl_writephy(tp, 0x1f, 0x0000); 3025 3026 /* Improve 2-pair detection performance */ 3027 rtl_writephy(tp, 0x1f, 0x0005); 3028 rtl_writephy(tp, 0x05, 0x8b85); 3029 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3030 rtl_writephy(tp, 0x1f, 0x0000); 3031 3032 rtl8168f_config_eee_phy(tp); 3033 rtl_enable_eee(tp); 3034 3035 /* Green feature */ 3036 rtl_writephy(tp, 0x1f, 0x0003); 3037 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000); 3038 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000); 3039 rtl_writephy(tp, 0x1f, 0x0000); 3040 rtl_writephy(tp, 0x1f, 0x0005); 3041 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000); 3042 rtl_writephy(tp, 0x1f, 0x0000); 3043 3044 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ 3045 rtl_rar_exgmac_set(tp, tp->dev->dev_addr); 3046 } 3047 3048 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) 3049 { 3050 /* For 4-corner performance improve */ 3051 rtl_writephy(tp, 0x1f, 0x0005); 3052 rtl_writephy(tp, 0x05, 0x8b80); 3053 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000); 3054 rtl_writephy(tp, 0x1f, 0x0000); 3055 3056 /* PHY auto speed down */ 3057 rtl_writephy(tp, 0x1f, 0x0007); 3058 rtl_writephy(tp, 0x1e, 0x002d); 3059 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); 3060 rtl_writephy(tp, 0x1f, 0x0000); 3061 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3062 3063 /* Improve 10M EEE waveform */ 3064 rtl_writephy(tp, 0x1f, 0x0005); 3065 rtl_writephy(tp, 0x05, 0x8b86); 3066 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 3067 rtl_writephy(tp, 0x1f, 0x0000); 3068 3069 rtl8168f_config_eee_phy(tp); 3070 rtl_enable_eee(tp); 3071 } 3072 3073 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) 3074 { 3075 static const struct phy_reg phy_reg_init[] = { 3076 /* Channel estimation fine tune */ 3077 { 0x1f, 0x0003 }, 3078 { 0x09, 0xa20f }, 3079 { 0x1f, 0x0000 }, 3080 3081 /* Modify green table for giga & fnet */ 3082 { 0x1f, 0x0005 }, 3083 { 0x05, 0x8b55 }, 3084 { 0x06, 0x0000 }, 3085 { 0x05, 0x8b5e }, 3086 { 0x06, 0x0000 }, 3087 { 0x05, 0x8b67 }, 3088 { 0x06, 0x0000 }, 3089 { 0x05, 0x8b70 }, 3090 { 0x06, 0x0000 }, 3091 { 0x1f, 0x0000 }, 3092 { 0x1f, 0x0007 }, 3093 { 0x1e, 0x0078 }, 3094 { 0x17, 0x0000 }, 3095 { 0x19, 0x00fb }, 3096 { 0x1f, 0x0000 }, 3097 3098 /* Modify green table for 10M */ 3099 { 0x1f, 0x0005 }, 3100 { 0x05, 0x8b79 }, 3101 { 0x06, 0xaa00 }, 3102 { 0x1f, 0x0000 }, 3103 3104 /* Disable hiimpedance detection (RTCT) */ 3105 { 0x1f, 0x0003 }, 3106 { 0x01, 0x328a }, 3107 { 0x1f, 0x0000 } 3108 }; 3109 3110 rtl_apply_firmware(tp); 3111 3112 rtl_writephy_batch(tp, phy_reg_init); 3113 3114 rtl8168f_hw_phy_config(tp); 3115 3116 /* Improve 2-pair detection performance */ 3117 rtl_writephy(tp, 0x1f, 0x0005); 3118 rtl_writephy(tp, 0x05, 0x8b85); 3119 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3120 rtl_writephy(tp, 0x1f, 0x0000); 3121 } 3122 3123 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) 3124 { 3125 rtl_apply_firmware(tp); 3126 3127 rtl8168f_hw_phy_config(tp); 3128 } 3129 3130 static void rtl8411_hw_phy_config(struct rtl8169_private *tp) 3131 { 3132 static const struct phy_reg phy_reg_init[] = { 3133 /* Channel estimation fine tune */ 3134 { 0x1f, 0x0003 }, 3135 { 0x09, 0xa20f }, 3136 { 0x1f, 0x0000 }, 3137 3138 /* Modify green table for giga & fnet */ 3139 { 0x1f, 0x0005 }, 3140 { 0x05, 0x8b55 }, 3141 { 0x06, 0x0000 }, 3142 { 0x05, 0x8b5e }, 3143 { 0x06, 0x0000 }, 3144 { 0x05, 0x8b67 }, 3145 { 0x06, 0x0000 }, 3146 { 0x05, 0x8b70 }, 3147 { 0x06, 0x0000 }, 3148 { 0x1f, 0x0000 }, 3149 { 0x1f, 0x0007 }, 3150 { 0x1e, 0x0078 }, 3151 { 0x17, 0x0000 }, 3152 { 0x19, 0x00aa }, 3153 { 0x1f, 0x0000 }, 3154 3155 /* Modify green table for 10M */ 3156 { 0x1f, 0x0005 }, 3157 { 0x05, 0x8b79 }, 3158 { 0x06, 0xaa00 }, 3159 { 0x1f, 0x0000 }, 3160 3161 /* Disable hiimpedance detection (RTCT) */ 3162 { 0x1f, 0x0003 }, 3163 { 0x01, 0x328a }, 3164 { 0x1f, 0x0000 } 3165 }; 3166 3167 3168 rtl_apply_firmware(tp); 3169 3170 rtl8168f_hw_phy_config(tp); 3171 3172 /* Improve 2-pair detection performance */ 3173 rtl_writephy(tp, 0x1f, 0x0005); 3174 rtl_writephy(tp, 0x05, 0x8b85); 3175 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3176 rtl_writephy(tp, 0x1f, 0x0000); 3177 3178 rtl_writephy_batch(tp, phy_reg_init); 3179 3180 /* Modify green table for giga */ 3181 rtl_writephy(tp, 0x1f, 0x0005); 3182 rtl_writephy(tp, 0x05, 0x8b54); 3183 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); 3184 rtl_writephy(tp, 0x05, 0x8b5d); 3185 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); 3186 rtl_writephy(tp, 0x05, 0x8a7c); 3187 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3188 rtl_writephy(tp, 0x05, 0x8a7f); 3189 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000); 3190 rtl_writephy(tp, 0x05, 0x8a82); 3191 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3192 rtl_writephy(tp, 0x05, 0x8a85); 3193 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3194 rtl_writephy(tp, 0x05, 0x8a88); 3195 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3196 rtl_writephy(tp, 0x1f, 0x0000); 3197 3198 /* uc same-seed solution */ 3199 rtl_writephy(tp, 0x1f, 0x0005); 3200 rtl_writephy(tp, 0x05, 0x8b85); 3201 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000); 3202 rtl_writephy(tp, 0x1f, 0x0000); 3203 3204 /* Green feature */ 3205 rtl_writephy(tp, 0x1f, 0x0003); 3206 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); 3207 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); 3208 rtl_writephy(tp, 0x1f, 0x0000); 3209 } 3210 3211 static void rtl8168g_disable_aldps(struct rtl8169_private *tp) 3212 { 3213 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0); 3214 } 3215 3216 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp) 3217 { 3218 struct phy_device *phydev = tp->phydev; 3219 3220 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 3221 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 3222 phy_write(phydev, 0x1f, 0x0a43); 3223 phy_write(phydev, 0x13, 0x8084); 3224 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13)); 3225 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0)); 3226 3227 phy_write(phydev, 0x1f, 0x0000); 3228 } 3229 3230 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) 3231 { 3232 int ret; 3233 3234 rtl_apply_firmware(tp); 3235 3236 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10); 3237 if (ret & BIT(8)) 3238 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0); 3239 else 3240 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15)); 3241 3242 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13); 3243 if (ret & BIT(8)) 3244 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1)); 3245 else 3246 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0); 3247 3248 /* Enable PHY auto speed down */ 3249 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3250 3251 rtl8168g_phy_adjust_10m_aldps(tp); 3252 3253 /* EEE auto-fallback function */ 3254 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3255 3256 /* Enable UC LPF tune function */ 3257 rtl_writephy(tp, 0x1f, 0x0a43); 3258 rtl_writephy(tp, 0x13, 0x8012); 3259 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3260 3261 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3262 3263 /* Improve SWR Efficiency */ 3264 rtl_writephy(tp, 0x1f, 0x0bcd); 3265 rtl_writephy(tp, 0x14, 0x5065); 3266 rtl_writephy(tp, 0x14, 0xd065); 3267 rtl_writephy(tp, 0x1f, 0x0bc8); 3268 rtl_writephy(tp, 0x11, 0x5655); 3269 rtl_writephy(tp, 0x1f, 0x0bcd); 3270 rtl_writephy(tp, 0x14, 0x1065); 3271 rtl_writephy(tp, 0x14, 0x9065); 3272 rtl_writephy(tp, 0x14, 0x1065); 3273 rtl_writephy(tp, 0x1f, 0x0000); 3274 3275 rtl8168g_disable_aldps(tp); 3276 rtl8168g_config_eee_phy(tp); 3277 rtl_enable_eee(tp); 3278 } 3279 3280 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) 3281 { 3282 rtl_apply_firmware(tp); 3283 rtl8168g_config_eee_phy(tp); 3284 rtl_enable_eee(tp); 3285 } 3286 3287 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) 3288 { 3289 u16 dout_tapbin; 3290 u32 data; 3291 3292 rtl_apply_firmware(tp); 3293 3294 /* CHN EST parameters adjust - giga master */ 3295 rtl_writephy(tp, 0x1f, 0x0a43); 3296 rtl_writephy(tp, 0x13, 0x809b); 3297 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800); 3298 rtl_writephy(tp, 0x13, 0x80a2); 3299 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00); 3300 rtl_writephy(tp, 0x13, 0x80a4); 3301 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00); 3302 rtl_writephy(tp, 0x13, 0x809c); 3303 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00); 3304 rtl_writephy(tp, 0x1f, 0x0000); 3305 3306 /* CHN EST parameters adjust - giga slave */ 3307 rtl_writephy(tp, 0x1f, 0x0a43); 3308 rtl_writephy(tp, 0x13, 0x80ad); 3309 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800); 3310 rtl_writephy(tp, 0x13, 0x80b4); 3311 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00); 3312 rtl_writephy(tp, 0x13, 0x80ac); 3313 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00); 3314 rtl_writephy(tp, 0x1f, 0x0000); 3315 3316 /* CHN EST parameters adjust - fnet */ 3317 rtl_writephy(tp, 0x1f, 0x0a43); 3318 rtl_writephy(tp, 0x13, 0x808e); 3319 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00); 3320 rtl_writephy(tp, 0x13, 0x8090); 3321 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00); 3322 rtl_writephy(tp, 0x13, 0x8092); 3323 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00); 3324 rtl_writephy(tp, 0x1f, 0x0000); 3325 3326 /* enable R-tune & PGA-retune function */ 3327 dout_tapbin = 0; 3328 rtl_writephy(tp, 0x1f, 0x0a46); 3329 data = rtl_readphy(tp, 0x13); 3330 data &= 3; 3331 data <<= 2; 3332 dout_tapbin |= data; 3333 data = rtl_readphy(tp, 0x12); 3334 data &= 0xc000; 3335 data >>= 14; 3336 dout_tapbin |= data; 3337 dout_tapbin = ~(dout_tapbin^0x08); 3338 dout_tapbin <<= 12; 3339 dout_tapbin &= 0xf000; 3340 rtl_writephy(tp, 0x1f, 0x0a43); 3341 rtl_writephy(tp, 0x13, 0x827a); 3342 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3343 rtl_writephy(tp, 0x13, 0x827b); 3344 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3345 rtl_writephy(tp, 0x13, 0x827c); 3346 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3347 rtl_writephy(tp, 0x13, 0x827d); 3348 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3349 3350 rtl_writephy(tp, 0x1f, 0x0a43); 3351 rtl_writephy(tp, 0x13, 0x0811); 3352 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); 3353 rtl_writephy(tp, 0x1f, 0x0a42); 3354 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); 3355 rtl_writephy(tp, 0x1f, 0x0000); 3356 3357 /* enable GPHY 10M */ 3358 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3359 3360 /* SAR ADC performance */ 3361 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); 3362 3363 rtl_writephy(tp, 0x1f, 0x0a43); 3364 rtl_writephy(tp, 0x13, 0x803f); 3365 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3366 rtl_writephy(tp, 0x13, 0x8047); 3367 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3368 rtl_writephy(tp, 0x13, 0x804f); 3369 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3370 rtl_writephy(tp, 0x13, 0x8057); 3371 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3372 rtl_writephy(tp, 0x13, 0x805f); 3373 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3374 rtl_writephy(tp, 0x13, 0x8067); 3375 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3376 rtl_writephy(tp, 0x13, 0x806f); 3377 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3378 rtl_writephy(tp, 0x1f, 0x0000); 3379 3380 /* disable phy pfm mode */ 3381 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3382 3383 rtl8168g_disable_aldps(tp); 3384 rtl8168h_config_eee_phy(tp); 3385 rtl_enable_eee(tp); 3386 } 3387 3388 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) 3389 { 3390 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; 3391 u16 rlen; 3392 u32 data; 3393 3394 rtl_apply_firmware(tp); 3395 3396 /* CHIN EST parameter update */ 3397 rtl_writephy(tp, 0x1f, 0x0a43); 3398 rtl_writephy(tp, 0x13, 0x808a); 3399 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f); 3400 rtl_writephy(tp, 0x1f, 0x0000); 3401 3402 /* enable R-tune & PGA-retune function */ 3403 rtl_writephy(tp, 0x1f, 0x0a43); 3404 rtl_writephy(tp, 0x13, 0x0811); 3405 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); 3406 rtl_writephy(tp, 0x1f, 0x0a42); 3407 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); 3408 rtl_writephy(tp, 0x1f, 0x0000); 3409 3410 /* enable GPHY 10M */ 3411 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3412 3413 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 3414 data = r8168_mac_ocp_read(tp, 0xdd02); 3415 ioffset_p3 = ((data & 0x80)>>7); 3416 ioffset_p3 <<= 3; 3417 3418 data = r8168_mac_ocp_read(tp, 0xdd00); 3419 ioffset_p3 |= ((data & (0xe000))>>13); 3420 ioffset_p2 = ((data & (0x1e00))>>9); 3421 ioffset_p1 = ((data & (0x01e0))>>5); 3422 ioffset_p0 = ((data & 0x0010)>>4); 3423 ioffset_p0 <<= 3; 3424 ioffset_p0 |= (data & (0x07)); 3425 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); 3426 3427 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) || 3428 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) { 3429 rtl_writephy(tp, 0x1f, 0x0bcf); 3430 rtl_writephy(tp, 0x16, data); 3431 rtl_writephy(tp, 0x1f, 0x0000); 3432 } 3433 3434 /* Modify rlen (TX LPF corner frequency) level */ 3435 rtl_writephy(tp, 0x1f, 0x0bcd); 3436 data = rtl_readphy(tp, 0x16); 3437 data &= 0x000f; 3438 rlen = 0; 3439 if (data > 3) 3440 rlen = data - 3; 3441 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); 3442 rtl_writephy(tp, 0x17, data); 3443 rtl_writephy(tp, 0x1f, 0x0bcd); 3444 rtl_writephy(tp, 0x1f, 0x0000); 3445 3446 /* disable phy pfm mode */ 3447 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3448 3449 rtl8168g_disable_aldps(tp); 3450 rtl8168g_config_eee_phy(tp); 3451 rtl_enable_eee(tp); 3452 } 3453 3454 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp) 3455 { 3456 /* Enable PHY auto speed down */ 3457 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3458 3459 rtl8168g_phy_adjust_10m_aldps(tp); 3460 3461 /* Enable EEE auto-fallback function */ 3462 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3463 3464 /* Enable UC LPF tune function */ 3465 rtl_writephy(tp, 0x1f, 0x0a43); 3466 rtl_writephy(tp, 0x13, 0x8012); 3467 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3468 rtl_writephy(tp, 0x1f, 0x0000); 3469 3470 /* set rg_sel_sdm_rate */ 3471 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3472 3473 rtl8168g_disable_aldps(tp); 3474 rtl8168g_config_eee_phy(tp); 3475 rtl_enable_eee(tp); 3476 } 3477 3478 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp) 3479 { 3480 rtl8168g_phy_adjust_10m_aldps(tp); 3481 3482 /* Enable UC LPF tune function */ 3483 rtl_writephy(tp, 0x1f, 0x0a43); 3484 rtl_writephy(tp, 0x13, 0x8012); 3485 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3486 rtl_writephy(tp, 0x1f, 0x0000); 3487 3488 /* Set rg_sel_sdm_rate */ 3489 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3490 3491 /* Channel estimation parameters */ 3492 rtl_writephy(tp, 0x1f, 0x0a43); 3493 rtl_writephy(tp, 0x13, 0x80f3); 3494 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff); 3495 rtl_writephy(tp, 0x13, 0x80f0); 3496 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff); 3497 rtl_writephy(tp, 0x13, 0x80ef); 3498 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff); 3499 rtl_writephy(tp, 0x13, 0x80f6); 3500 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff); 3501 rtl_writephy(tp, 0x13, 0x80ec); 3502 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff); 3503 rtl_writephy(tp, 0x13, 0x80ed); 3504 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); 3505 rtl_writephy(tp, 0x13, 0x80f2); 3506 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff); 3507 rtl_writephy(tp, 0x13, 0x80f4); 3508 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff); 3509 rtl_writephy(tp, 0x1f, 0x0a43); 3510 rtl_writephy(tp, 0x13, 0x8110); 3511 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff); 3512 rtl_writephy(tp, 0x13, 0x810f); 3513 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff); 3514 rtl_writephy(tp, 0x13, 0x8111); 3515 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff); 3516 rtl_writephy(tp, 0x13, 0x8113); 3517 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff); 3518 rtl_writephy(tp, 0x13, 0x8115); 3519 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff); 3520 rtl_writephy(tp, 0x13, 0x810e); 3521 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff); 3522 rtl_writephy(tp, 0x13, 0x810c); 3523 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); 3524 rtl_writephy(tp, 0x13, 0x810b); 3525 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff); 3526 rtl_writephy(tp, 0x1f, 0x0a43); 3527 rtl_writephy(tp, 0x13, 0x80d1); 3528 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff); 3529 rtl_writephy(tp, 0x13, 0x80cd); 3530 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff); 3531 rtl_writephy(tp, 0x13, 0x80d3); 3532 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff); 3533 rtl_writephy(tp, 0x13, 0x80d5); 3534 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff); 3535 rtl_writephy(tp, 0x13, 0x80d7); 3536 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff); 3537 3538 /* Force PWM-mode */ 3539 rtl_writephy(tp, 0x1f, 0x0bcd); 3540 rtl_writephy(tp, 0x14, 0x5065); 3541 rtl_writephy(tp, 0x14, 0xd065); 3542 rtl_writephy(tp, 0x1f, 0x0bc8); 3543 rtl_writephy(tp, 0x12, 0x00ed); 3544 rtl_writephy(tp, 0x1f, 0x0bcd); 3545 rtl_writephy(tp, 0x14, 0x1065); 3546 rtl_writephy(tp, 0x14, 0x9065); 3547 rtl_writephy(tp, 0x14, 0x1065); 3548 rtl_writephy(tp, 0x1f, 0x0000); 3549 3550 rtl8168g_disable_aldps(tp); 3551 rtl8168g_config_eee_phy(tp); 3552 rtl_enable_eee(tp); 3553 } 3554 3555 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) 3556 { 3557 static const struct phy_reg phy_reg_init[] = { 3558 { 0x1f, 0x0003 }, 3559 { 0x08, 0x441d }, 3560 { 0x01, 0x9100 }, 3561 { 0x1f, 0x0000 } 3562 }; 3563 3564 rtl_writephy(tp, 0x1f, 0x0000); 3565 rtl_patchphy(tp, 0x11, 1 << 12); 3566 rtl_patchphy(tp, 0x19, 1 << 13); 3567 rtl_patchphy(tp, 0x10, 1 << 15); 3568 3569 rtl_writephy_batch(tp, phy_reg_init); 3570 } 3571 3572 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) 3573 { 3574 static const struct phy_reg phy_reg_init[] = { 3575 { 0x1f, 0x0005 }, 3576 { 0x1a, 0x0000 }, 3577 { 0x1f, 0x0000 }, 3578 3579 { 0x1f, 0x0004 }, 3580 { 0x1c, 0x0000 }, 3581 { 0x1f, 0x0000 }, 3582 3583 { 0x1f, 0x0001 }, 3584 { 0x15, 0x7701 }, 3585 { 0x1f, 0x0000 } 3586 }; 3587 3588 /* Disable ALDPS before ram code */ 3589 rtl_writephy(tp, 0x1f, 0x0000); 3590 rtl_writephy(tp, 0x18, 0x0310); 3591 msleep(100); 3592 3593 rtl_apply_firmware(tp); 3594 3595 rtl_writephy_batch(tp, phy_reg_init); 3596 } 3597 3598 static void rtl8402_hw_phy_config(struct rtl8169_private *tp) 3599 { 3600 /* Disable ALDPS before setting firmware */ 3601 rtl_writephy(tp, 0x1f, 0x0000); 3602 rtl_writephy(tp, 0x18, 0x0310); 3603 msleep(20); 3604 3605 rtl_apply_firmware(tp); 3606 3607 /* EEE setting */ 3608 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3609 rtl_writephy(tp, 0x1f, 0x0004); 3610 rtl_writephy(tp, 0x10, 0x401f); 3611 rtl_writephy(tp, 0x19, 0x7030); 3612 rtl_writephy(tp, 0x1f, 0x0000); 3613 } 3614 3615 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) 3616 { 3617 static const struct phy_reg phy_reg_init[] = { 3618 { 0x1f, 0x0004 }, 3619 { 0x10, 0xc07f }, 3620 { 0x19, 0x7030 }, 3621 { 0x1f, 0x0000 } 3622 }; 3623 3624 /* Disable ALDPS before ram code */ 3625 rtl_writephy(tp, 0x1f, 0x0000); 3626 rtl_writephy(tp, 0x18, 0x0310); 3627 msleep(100); 3628 3629 rtl_apply_firmware(tp); 3630 3631 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3632 rtl_writephy_batch(tp, phy_reg_init); 3633 3634 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3635 } 3636 3637 static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp) 3638 { 3639 struct phy_device *phydev = tp->phydev; 3640 3641 phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084); 3642 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3643 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006); 3644 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3645 phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100); 3646 phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000); 3647 phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400); 3648 phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff); 3649 phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff); 3650 3651 phy_write(phydev, 0x1f, 0x0a43); 3652 phy_write(phydev, 0x13, 0x80ea); 3653 phy_modify(phydev, 0x14, 0xff00, 0xc400); 3654 phy_write(phydev, 0x13, 0x80eb); 3655 phy_modify(phydev, 0x14, 0x0700, 0x0300); 3656 phy_write(phydev, 0x13, 0x80f8); 3657 phy_modify(phydev, 0x14, 0xff00, 0x1c00); 3658 phy_write(phydev, 0x13, 0x80f1); 3659 phy_modify(phydev, 0x14, 0xff00, 0x3000); 3660 phy_write(phydev, 0x13, 0x80fe); 3661 phy_modify(phydev, 0x14, 0xff00, 0xa500); 3662 phy_write(phydev, 0x13, 0x8102); 3663 phy_modify(phydev, 0x14, 0xff00, 0x5000); 3664 phy_write(phydev, 0x13, 0x8105); 3665 phy_modify(phydev, 0x14, 0xff00, 0x3300); 3666 phy_write(phydev, 0x13, 0x8100); 3667 phy_modify(phydev, 0x14, 0xff00, 0x7000); 3668 phy_write(phydev, 0x13, 0x8104); 3669 phy_modify(phydev, 0x14, 0xff00, 0xf000); 3670 phy_write(phydev, 0x13, 0x8106); 3671 phy_modify(phydev, 0x14, 0xff00, 0x6500); 3672 phy_write(phydev, 0x13, 0x80dc); 3673 phy_modify(phydev, 0x14, 0xff00, 0xed00); 3674 phy_write(phydev, 0x13, 0x80df); 3675 phy_set_bits(phydev, 0x14, BIT(8)); 3676 phy_write(phydev, 0x13, 0x80e1); 3677 phy_clear_bits(phydev, 0x14, BIT(8)); 3678 phy_write(phydev, 0x1f, 0x0000); 3679 3680 phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038); 3681 phy_write_paged(phydev, 0xa43, 0x13, 0x819f); 3682 phy_write_paged(phydev, 0xa43, 0x14, 0xd0b6); 3683 3684 phy_write_paged(phydev, 0xbc3, 0x12, 0x5555); 3685 phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00); 3686 phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000); 3687 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3688 3689 rtl8125_config_eee_phy(tp); 3690 rtl_enable_eee(tp); 3691 } 3692 3693 static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp) 3694 { 3695 struct phy_device *phydev = tp->phydev; 3696 int i; 3697 3698 phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010); 3699 phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff); 3700 phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006); 3701 phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000); 3702 phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002); 3703 phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044); 3704 phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000); 3705 phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000); 3706 phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002); 3707 phy_write_paged(phydev, 0xad4, 0x16, 0x00a8); 3708 phy_write_paged(phydev, 0xac5, 0x16, 0x01ff); 3709 phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030); 3710 3711 phy_write(phydev, 0x1f, 0x0b87); 3712 phy_write(phydev, 0x16, 0x80a2); 3713 phy_write(phydev, 0x17, 0x0153); 3714 phy_write(phydev, 0x16, 0x809c); 3715 phy_write(phydev, 0x17, 0x0153); 3716 phy_write(phydev, 0x1f, 0x0000); 3717 3718 phy_write(phydev, 0x1f, 0x0a43); 3719 phy_write(phydev, 0x13, 0x81B3); 3720 phy_write(phydev, 0x14, 0x0043); 3721 phy_write(phydev, 0x14, 0x00A7); 3722 phy_write(phydev, 0x14, 0x00D6); 3723 phy_write(phydev, 0x14, 0x00EC); 3724 phy_write(phydev, 0x14, 0x00F6); 3725 phy_write(phydev, 0x14, 0x00FB); 3726 phy_write(phydev, 0x14, 0x00FD); 3727 phy_write(phydev, 0x14, 0x00FF); 3728 phy_write(phydev, 0x14, 0x00BB); 3729 phy_write(phydev, 0x14, 0x0058); 3730 phy_write(phydev, 0x14, 0x0029); 3731 phy_write(phydev, 0x14, 0x0013); 3732 phy_write(phydev, 0x14, 0x0009); 3733 phy_write(phydev, 0x14, 0x0004); 3734 phy_write(phydev, 0x14, 0x0002); 3735 for (i = 0; i < 25; i++) 3736 phy_write(phydev, 0x14, 0x0000); 3737 3738 phy_write(phydev, 0x13, 0x8257); 3739 phy_write(phydev, 0x14, 0x020F); 3740 3741 phy_write(phydev, 0x13, 0x80EA); 3742 phy_write(phydev, 0x14, 0x7843); 3743 phy_write(phydev, 0x1f, 0x0000); 3744 3745 rtl_apply_firmware(tp); 3746 3747 phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000); 3748 3749 phy_write(phydev, 0x1f, 0x0a43); 3750 phy_write(phydev, 0x13, 0x81a2); 3751 phy_set_bits(phydev, 0x14, BIT(8)); 3752 phy_write(phydev, 0x1f, 0x0000); 3753 3754 phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00); 3755 phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000); 3756 phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020); 3757 phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000); 3758 phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000); 3759 phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800); 3760 3761 rtl8125_config_eee_phy(tp); 3762 rtl_enable_eee(tp); 3763 } 3764 3765 static void rtl_hw_phy_config(struct net_device *dev) 3766 { 3767 static const rtl_generic_fct phy_configs[] = { 3768 /* PCI devices. */ 3769 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 3770 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 3771 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 3772 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 3773 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 3774 /* PCI-E devices. */ 3775 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 3776 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 3777 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 3778 [RTL_GIGA_MAC_VER_10] = NULL, 3779 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 3780 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config, 3781 [RTL_GIGA_MAC_VER_13] = NULL, 3782 [RTL_GIGA_MAC_VER_14] = NULL, 3783 [RTL_GIGA_MAC_VER_15] = NULL, 3784 [RTL_GIGA_MAC_VER_16] = NULL, 3785 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 3786 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 3787 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 3788 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 3789 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 3790 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config, 3791 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 3792 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 3793 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 3794 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 3795 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config, 3796 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 3797 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 3798 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 3799 [RTL_GIGA_MAC_VER_31] = NULL, 3800 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 3801 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 3802 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 3803 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 3804 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 3805 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 3806 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 3807 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 3808 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 3809 [RTL_GIGA_MAC_VER_41] = NULL, 3810 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 3811 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 3812 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 3813 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config, 3814 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 3815 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config, 3816 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 3817 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config, 3818 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config, 3819 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 3820 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config, 3821 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config, 3822 }; 3823 struct rtl8169_private *tp = netdev_priv(dev); 3824 3825 if (phy_configs[tp->mac_version]) 3826 phy_configs[tp->mac_version](tp); 3827 } 3828 3829 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 3830 { 3831 if (!test_and_set_bit(flag, tp->wk.flags)) 3832 schedule_work(&tp->wk.work); 3833 } 3834 3835 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 3836 { 3837 rtl_hw_phy_config(dev); 3838 3839 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 3840 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 3841 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 3842 netif_dbg(tp, drv, dev, 3843 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 3844 RTL_W8(tp, 0x82, 0x01); 3845 } 3846 3847 /* We may have called phy_speed_down before */ 3848 phy_speed_up(tp->phydev); 3849 3850 genphy_soft_reset(tp->phydev); 3851 } 3852 3853 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 3854 { 3855 rtl_lock_work(tp); 3856 3857 rtl_unlock_config_regs(tp); 3858 3859 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 3860 RTL_R32(tp, MAC4); 3861 3862 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3863 RTL_R32(tp, MAC0); 3864 3865 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 3866 rtl_rar_exgmac_set(tp, addr); 3867 3868 rtl_lock_config_regs(tp); 3869 3870 rtl_unlock_work(tp); 3871 } 3872 3873 static int rtl_set_mac_address(struct net_device *dev, void *p) 3874 { 3875 struct rtl8169_private *tp = netdev_priv(dev); 3876 struct device *d = tp_to_dev(tp); 3877 int ret; 3878 3879 ret = eth_mac_addr(dev, p); 3880 if (ret) 3881 return ret; 3882 3883 pm_runtime_get_noresume(d); 3884 3885 if (pm_runtime_active(d)) 3886 rtl_rar_set(tp, dev->dev_addr); 3887 3888 pm_runtime_put_noidle(d); 3889 3890 return 0; 3891 } 3892 3893 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3894 { 3895 struct rtl8169_private *tp = netdev_priv(dev); 3896 3897 if (!netif_running(dev)) 3898 return -ENODEV; 3899 3900 return phy_mii_ioctl(tp->phydev, ifr, cmd); 3901 } 3902 3903 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 3904 { 3905 switch (tp->mac_version) { 3906 case RTL_GIGA_MAC_VER_25: 3907 case RTL_GIGA_MAC_VER_26: 3908 case RTL_GIGA_MAC_VER_29: 3909 case RTL_GIGA_MAC_VER_30: 3910 case RTL_GIGA_MAC_VER_32: 3911 case RTL_GIGA_MAC_VER_33: 3912 case RTL_GIGA_MAC_VER_34: 3913 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51: 3914 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 3915 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 3916 break; 3917 default: 3918 break; 3919 } 3920 } 3921 3922 static void rtl_pll_power_down(struct rtl8169_private *tp) 3923 { 3924 if (r8168_check_dash(tp)) 3925 return; 3926 3927 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 3928 tp->mac_version == RTL_GIGA_MAC_VER_33) 3929 rtl_ephy_write(tp, 0x19, 0xff64); 3930 3931 if (device_may_wakeup(tp_to_dev(tp))) { 3932 phy_speed_down(tp->phydev, false); 3933 rtl_wol_suspend_quirk(tp); 3934 return; 3935 } 3936 3937 switch (tp->mac_version) { 3938 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3939 case RTL_GIGA_MAC_VER_37: 3940 case RTL_GIGA_MAC_VER_39: 3941 case RTL_GIGA_MAC_VER_43: 3942 case RTL_GIGA_MAC_VER_44: 3943 case RTL_GIGA_MAC_VER_45: 3944 case RTL_GIGA_MAC_VER_46: 3945 case RTL_GIGA_MAC_VER_47: 3946 case RTL_GIGA_MAC_VER_48: 3947 case RTL_GIGA_MAC_VER_50: 3948 case RTL_GIGA_MAC_VER_51: 3949 case RTL_GIGA_MAC_VER_60: 3950 case RTL_GIGA_MAC_VER_61: 3951 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3952 break; 3953 case RTL_GIGA_MAC_VER_40: 3954 case RTL_GIGA_MAC_VER_41: 3955 case RTL_GIGA_MAC_VER_49: 3956 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3957 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3958 break; 3959 default: 3960 break; 3961 } 3962 } 3963 3964 static void rtl_pll_power_up(struct rtl8169_private *tp) 3965 { 3966 switch (tp->mac_version) { 3967 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3968 case RTL_GIGA_MAC_VER_37: 3969 case RTL_GIGA_MAC_VER_39: 3970 case RTL_GIGA_MAC_VER_43: 3971 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 3972 break; 3973 case RTL_GIGA_MAC_VER_44: 3974 case RTL_GIGA_MAC_VER_45: 3975 case RTL_GIGA_MAC_VER_46: 3976 case RTL_GIGA_MAC_VER_47: 3977 case RTL_GIGA_MAC_VER_48: 3978 case RTL_GIGA_MAC_VER_50: 3979 case RTL_GIGA_MAC_VER_51: 3980 case RTL_GIGA_MAC_VER_60: 3981 case RTL_GIGA_MAC_VER_61: 3982 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3983 break; 3984 case RTL_GIGA_MAC_VER_40: 3985 case RTL_GIGA_MAC_VER_41: 3986 case RTL_GIGA_MAC_VER_49: 3987 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3988 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3989 break; 3990 default: 3991 break; 3992 } 3993 3994 phy_resume(tp->phydev); 3995 /* give MAC/PHY some time to resume */ 3996 msleep(20); 3997 } 3998 3999 static void rtl_init_rxcfg(struct rtl8169_private *tp) 4000 { 4001 switch (tp->mac_version) { 4002 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4003 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4004 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 4005 break; 4006 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 4007 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 4008 case RTL_GIGA_MAC_VER_38: 4009 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 4010 break; 4011 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 4012 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 4013 break; 4014 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 4015 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 | 4016 RX_DMA_BURST); 4017 break; 4018 default: 4019 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 4020 break; 4021 } 4022 } 4023 4024 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 4025 { 4026 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 4027 } 4028 4029 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 4030 { 4031 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4032 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 4033 } 4034 4035 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 4036 { 4037 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4038 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 4039 } 4040 4041 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 4042 { 4043 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4044 } 4045 4046 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 4047 { 4048 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4049 } 4050 4051 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 4052 { 4053 RTL_W8(tp, MaxTxPacketSize, 0x3f); 4054 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 4055 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 4056 } 4057 4058 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 4059 { 4060 RTL_W8(tp, MaxTxPacketSize, 0x0c); 4061 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 4062 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 4063 } 4064 4065 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 4066 { 4067 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 4068 } 4069 4070 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 4071 { 4072 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 4073 } 4074 4075 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) 4076 { 4077 rtl_unlock_config_regs(tp); 4078 switch (tp->mac_version) { 4079 case RTL_GIGA_MAC_VER_12: 4080 case RTL_GIGA_MAC_VER_17: 4081 r8168b_1_hw_jumbo_enable(tp); 4082 break; 4083 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 4084 r8168c_hw_jumbo_enable(tp); 4085 break; 4086 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 4087 r8168dp_hw_jumbo_enable(tp); 4088 break; 4089 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 4090 r8168e_hw_jumbo_enable(tp); 4091 break; 4092 default: 4093 break; 4094 } 4095 rtl_lock_config_regs(tp); 4096 } 4097 4098 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) 4099 { 4100 rtl_unlock_config_regs(tp); 4101 switch (tp->mac_version) { 4102 case RTL_GIGA_MAC_VER_12: 4103 case RTL_GIGA_MAC_VER_17: 4104 r8168b_1_hw_jumbo_disable(tp); 4105 break; 4106 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 4107 r8168c_hw_jumbo_disable(tp); 4108 break; 4109 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 4110 r8168dp_hw_jumbo_disable(tp); 4111 break; 4112 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 4113 r8168e_hw_jumbo_disable(tp); 4114 break; 4115 default: 4116 break; 4117 } 4118 rtl_lock_config_regs(tp); 4119 } 4120 4121 static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu) 4122 { 4123 if (mtu > ETH_DATA_LEN) 4124 rtl_hw_jumbo_enable(tp); 4125 else 4126 rtl_hw_jumbo_disable(tp); 4127 } 4128 4129 DECLARE_RTL_COND(rtl_chipcmd_cond) 4130 { 4131 return RTL_R8(tp, ChipCmd) & CmdReset; 4132 } 4133 4134 static void rtl_hw_reset(struct rtl8169_private *tp) 4135 { 4136 RTL_W8(tp, ChipCmd, CmdReset); 4137 4138 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 4139 } 4140 4141 static void rtl_request_firmware(struct rtl8169_private *tp) 4142 { 4143 struct rtl_fw *rtl_fw; 4144 4145 /* firmware loaded already or no firmware available */ 4146 if (tp->rtl_fw || !tp->fw_name) 4147 return; 4148 4149 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 4150 if (!rtl_fw) { 4151 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n"); 4152 return; 4153 } 4154 4155 rtl_fw->phy_write = rtl_writephy; 4156 rtl_fw->phy_read = rtl_readphy; 4157 rtl_fw->mac_mcu_write = mac_mcu_write; 4158 rtl_fw->mac_mcu_read = mac_mcu_read; 4159 rtl_fw->fw_name = tp->fw_name; 4160 rtl_fw->dev = tp_to_dev(tp); 4161 4162 if (rtl_fw_request_firmware(rtl_fw)) 4163 kfree(rtl_fw); 4164 else 4165 tp->rtl_fw = rtl_fw; 4166 } 4167 4168 static void rtl_rx_close(struct rtl8169_private *tp) 4169 { 4170 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 4171 } 4172 4173 DECLARE_RTL_COND(rtl_npq_cond) 4174 { 4175 return RTL_R8(tp, TxPoll) & NPQ; 4176 } 4177 4178 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 4179 { 4180 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 4181 } 4182 4183 static void rtl8169_hw_reset(struct rtl8169_private *tp) 4184 { 4185 /* Disable interrupts */ 4186 rtl8169_irq_mask_and_ack(tp); 4187 4188 rtl_rx_close(tp); 4189 4190 switch (tp->mac_version) { 4191 case RTL_GIGA_MAC_VER_27: 4192 case RTL_GIGA_MAC_VER_28: 4193 case RTL_GIGA_MAC_VER_31: 4194 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 4195 break; 4196 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4197 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 4198 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4199 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4200 break; 4201 default: 4202 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4203 udelay(100); 4204 break; 4205 } 4206 4207 rtl_hw_reset(tp); 4208 } 4209 4210 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 4211 { 4212 u32 val = TX_DMA_BURST << TxDMAShift | 4213 InterFrameGap << TxInterFrameGapShift; 4214 4215 if (rtl_is_8168evl_up(tp)) 4216 val |= TXCFG_AUTO_FIFO; 4217 4218 RTL_W32(tp, TxConfig, val); 4219 } 4220 4221 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 4222 { 4223 /* Low hurts. Let's disable the filtering. */ 4224 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 4225 } 4226 4227 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 4228 { 4229 /* 4230 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 4231 * register to be written before TxDescAddrLow to work. 4232 * Switching from MMIO to I/O access fixes the issue as well. 4233 */ 4234 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 4235 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 4236 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 4237 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 4238 } 4239 4240 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) 4241 { 4242 u32 val; 4243 4244 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 4245 val = 0x000fff00; 4246 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 4247 val = 0x00ffff00; 4248 else 4249 return; 4250 4251 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 4252 val |= 0xff; 4253 4254 RTL_W32(tp, 0x7c, val); 4255 } 4256 4257 static void rtl_set_rx_mode(struct net_device *dev) 4258 { 4259 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 4260 /* Multicast hash filter */ 4261 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 4262 struct rtl8169_private *tp = netdev_priv(dev); 4263 u32 tmp; 4264 4265 if (dev->flags & IFF_PROMISC) { 4266 /* Unconditionally log net taps. */ 4267 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); 4268 rx_mode |= AcceptAllPhys; 4269 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 4270 dev->flags & IFF_ALLMULTI || 4271 tp->mac_version == RTL_GIGA_MAC_VER_35) { 4272 /* accept all multicasts */ 4273 } else if (netdev_mc_empty(dev)) { 4274 rx_mode &= ~AcceptMulticast; 4275 } else { 4276 struct netdev_hw_addr *ha; 4277 4278 mc_filter[1] = mc_filter[0] = 0; 4279 netdev_for_each_mc_addr(ha, dev) { 4280 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 4281 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 4282 } 4283 4284 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 4285 tmp = mc_filter[0]; 4286 mc_filter[0] = swab32(mc_filter[1]); 4287 mc_filter[1] = swab32(tmp); 4288 } 4289 } 4290 4291 if (dev->features & NETIF_F_RXALL) 4292 rx_mode |= (AcceptErr | AcceptRunt); 4293 4294 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 4295 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 4296 4297 tmp = RTL_R32(tp, RxConfig); 4298 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); 4299 } 4300 4301 DECLARE_RTL_COND(rtl_csiar_cond) 4302 { 4303 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 4304 } 4305 4306 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 4307 { 4308 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4309 4310 RTL_W32(tp, CSIDR, value); 4311 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 4312 CSIAR_BYTE_ENABLE | func << 16); 4313 4314 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 4315 } 4316 4317 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 4318 { 4319 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4320 4321 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 4322 CSIAR_BYTE_ENABLE); 4323 4324 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 4325 RTL_R32(tp, CSIDR) : ~0; 4326 } 4327 4328 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 4329 { 4330 struct pci_dev *pdev = tp->pci_dev; 4331 u32 csi; 4332 4333 /* According to Realtek the value at config space address 0x070f 4334 * controls the L0s/L1 entrance latency. We try standard ECAM access 4335 * first and if it fails fall back to CSI. 4336 */ 4337 if (pdev->cfg_size > 0x070f && 4338 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 4339 return; 4340 4341 netdev_notice_once(tp->dev, 4342 "No native access to PCI extended config space, falling back to CSI\n"); 4343 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 4344 rtl_csi_write(tp, 0x070c, csi | val << 24); 4345 } 4346 4347 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 4348 { 4349 rtl_csi_access_enable(tp, 0x27); 4350 } 4351 4352 struct ephy_info { 4353 unsigned int offset; 4354 u16 mask; 4355 u16 bits; 4356 }; 4357 4358 static void __rtl_ephy_init(struct rtl8169_private *tp, 4359 const struct ephy_info *e, int len) 4360 { 4361 u16 w; 4362 4363 while (len-- > 0) { 4364 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 4365 rtl_ephy_write(tp, e->offset, w); 4366 e++; 4367 } 4368 } 4369 4370 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 4371 4372 static void rtl_disable_clock_request(struct rtl8169_private *tp) 4373 { 4374 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 4375 PCI_EXP_LNKCTL_CLKREQ_EN); 4376 } 4377 4378 static void rtl_enable_clock_request(struct rtl8169_private *tp) 4379 { 4380 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 4381 PCI_EXP_LNKCTL_CLKREQ_EN); 4382 } 4383 4384 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 4385 { 4386 /* work around an issue when PCI reset occurs during L2/L3 state */ 4387 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 4388 } 4389 4390 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 4391 { 4392 /* Don't enable ASPM in the chip if OS can't control ASPM */ 4393 if (enable && tp->aspm_manageable) { 4394 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 4395 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 4396 } else { 4397 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4398 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4399 } 4400 4401 udelay(10); 4402 } 4403 4404 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 4405 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 4406 { 4407 /* Usage of dynamic vs. static FIFO is controlled by bit 4408 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 4409 */ 4410 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 4411 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 4412 } 4413 4414 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 4415 u8 low, u8 high) 4416 { 4417 /* FIFO thresholds for pause flow control */ 4418 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 4419 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 4420 } 4421 4422 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 4423 { 4424 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4425 } 4426 4427 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 4428 { 4429 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 4430 4431 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4432 4433 rtl_disable_clock_request(tp); 4434 } 4435 4436 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 4437 { 4438 static const struct ephy_info e_info_8168cp[] = { 4439 { 0x01, 0, 0x0001 }, 4440 { 0x02, 0x0800, 0x1000 }, 4441 { 0x03, 0, 0x0042 }, 4442 { 0x06, 0x0080, 0x0000 }, 4443 { 0x07, 0, 0x2000 } 4444 }; 4445 4446 rtl_set_def_aspm_entry_latency(tp); 4447 4448 rtl_ephy_init(tp, e_info_8168cp); 4449 4450 __rtl_hw_start_8168cp(tp); 4451 } 4452 4453 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 4454 { 4455 rtl_set_def_aspm_entry_latency(tp); 4456 4457 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4458 } 4459 4460 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 4461 { 4462 rtl_set_def_aspm_entry_latency(tp); 4463 4464 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4465 4466 /* Magic. */ 4467 RTL_W8(tp, DBG_REG, 0x20); 4468 } 4469 4470 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 4471 { 4472 static const struct ephy_info e_info_8168c_1[] = { 4473 { 0x02, 0x0800, 0x1000 }, 4474 { 0x03, 0, 0x0002 }, 4475 { 0x06, 0x0080, 0x0000 } 4476 }; 4477 4478 rtl_set_def_aspm_entry_latency(tp); 4479 4480 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 4481 4482 rtl_ephy_init(tp, e_info_8168c_1); 4483 4484 __rtl_hw_start_8168cp(tp); 4485 } 4486 4487 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 4488 { 4489 static const struct ephy_info e_info_8168c_2[] = { 4490 { 0x01, 0, 0x0001 }, 4491 { 0x03, 0x0400, 0x0020 } 4492 }; 4493 4494 rtl_set_def_aspm_entry_latency(tp); 4495 4496 rtl_ephy_init(tp, e_info_8168c_2); 4497 4498 __rtl_hw_start_8168cp(tp); 4499 } 4500 4501 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 4502 { 4503 rtl_hw_start_8168c_2(tp); 4504 } 4505 4506 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 4507 { 4508 rtl_set_def_aspm_entry_latency(tp); 4509 4510 __rtl_hw_start_8168cp(tp); 4511 } 4512 4513 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 4514 { 4515 rtl_set_def_aspm_entry_latency(tp); 4516 4517 rtl_disable_clock_request(tp); 4518 } 4519 4520 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 4521 { 4522 static const struct ephy_info e_info_8168d_4[] = { 4523 { 0x0b, 0x0000, 0x0048 }, 4524 { 0x19, 0x0020, 0x0050 }, 4525 { 0x0c, 0x0100, 0x0020 }, 4526 { 0x10, 0x0004, 0x0000 }, 4527 }; 4528 4529 rtl_set_def_aspm_entry_latency(tp); 4530 4531 rtl_ephy_init(tp, e_info_8168d_4); 4532 4533 rtl_enable_clock_request(tp); 4534 } 4535 4536 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 4537 { 4538 static const struct ephy_info e_info_8168e_1[] = { 4539 { 0x00, 0x0200, 0x0100 }, 4540 { 0x00, 0x0000, 0x0004 }, 4541 { 0x06, 0x0002, 0x0001 }, 4542 { 0x06, 0x0000, 0x0030 }, 4543 { 0x07, 0x0000, 0x2000 }, 4544 { 0x00, 0x0000, 0x0020 }, 4545 { 0x03, 0x5800, 0x2000 }, 4546 { 0x03, 0x0000, 0x0001 }, 4547 { 0x01, 0x0800, 0x1000 }, 4548 { 0x07, 0x0000, 0x4000 }, 4549 { 0x1e, 0x0000, 0x2000 }, 4550 { 0x19, 0xffff, 0xfe6c }, 4551 { 0x0a, 0x0000, 0x0040 } 4552 }; 4553 4554 rtl_set_def_aspm_entry_latency(tp); 4555 4556 rtl_ephy_init(tp, e_info_8168e_1); 4557 4558 rtl_disable_clock_request(tp); 4559 4560 /* Reset tx FIFO pointer */ 4561 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 4562 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 4563 4564 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4565 } 4566 4567 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 4568 { 4569 static const struct ephy_info e_info_8168e_2[] = { 4570 { 0x09, 0x0000, 0x0080 }, 4571 { 0x19, 0x0000, 0x0224 }, 4572 { 0x00, 0x0000, 0x0004 }, 4573 { 0x0c, 0x3df0, 0x0200 }, 4574 }; 4575 4576 rtl_set_def_aspm_entry_latency(tp); 4577 4578 rtl_ephy_init(tp, e_info_8168e_2); 4579 4580 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4581 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4582 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4583 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4584 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 4585 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4586 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4587 4588 rtl_disable_clock_request(tp); 4589 4590 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4591 4592 rtl8168_config_eee_mac(tp); 4593 4594 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4595 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4596 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4597 4598 rtl_hw_aspm_clkreq_enable(tp, true); 4599 } 4600 4601 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 4602 { 4603 rtl_set_def_aspm_entry_latency(tp); 4604 4605 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4606 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4607 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4608 rtl_reset_packet_filter(tp); 4609 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4610 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 4611 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4612 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 4613 4614 rtl_disable_clock_request(tp); 4615 4616 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4617 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4618 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4619 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4620 4621 rtl8168_config_eee_mac(tp); 4622 } 4623 4624 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 4625 { 4626 static const struct ephy_info e_info_8168f_1[] = { 4627 { 0x06, 0x00c0, 0x0020 }, 4628 { 0x08, 0x0001, 0x0002 }, 4629 { 0x09, 0x0000, 0x0080 }, 4630 { 0x19, 0x0000, 0x0224 }, 4631 { 0x00, 0x0000, 0x0004 }, 4632 { 0x0c, 0x3df0, 0x0200 }, 4633 }; 4634 4635 rtl_hw_start_8168f(tp); 4636 4637 rtl_ephy_init(tp, e_info_8168f_1); 4638 4639 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4640 } 4641 4642 static void rtl_hw_start_8411(struct rtl8169_private *tp) 4643 { 4644 static const struct ephy_info e_info_8168f_1[] = { 4645 { 0x06, 0x00c0, 0x0020 }, 4646 { 0x0f, 0xffff, 0x5200 }, 4647 { 0x19, 0x0000, 0x0224 }, 4648 { 0x00, 0x0000, 0x0004 }, 4649 { 0x0c, 0x3df0, 0x0200 }, 4650 }; 4651 4652 rtl_hw_start_8168f(tp); 4653 rtl_pcie_state_l2l3_disable(tp); 4654 4655 rtl_ephy_init(tp, e_info_8168f_1); 4656 4657 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 4658 } 4659 4660 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 4661 { 4662 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4663 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4664 4665 rtl_set_def_aspm_entry_latency(tp); 4666 4667 rtl_reset_packet_filter(tp); 4668 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 4669 4670 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4671 4672 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4673 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4674 4675 rtl8168_config_eee_mac(tp); 4676 4677 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4678 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4679 4680 rtl_pcie_state_l2l3_disable(tp); 4681 } 4682 4683 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 4684 { 4685 static const struct ephy_info e_info_8168g_1[] = { 4686 { 0x00, 0x0008, 0x0000 }, 4687 { 0x0c, 0x3ff0, 0x0820 }, 4688 { 0x1e, 0x0000, 0x0001 }, 4689 { 0x19, 0x8000, 0x0000 } 4690 }; 4691 4692 rtl_hw_start_8168g(tp); 4693 4694 /* disable aspm and clock request before access ephy */ 4695 rtl_hw_aspm_clkreq_enable(tp, false); 4696 rtl_ephy_init(tp, e_info_8168g_1); 4697 rtl_hw_aspm_clkreq_enable(tp, true); 4698 } 4699 4700 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 4701 { 4702 static const struct ephy_info e_info_8168g_2[] = { 4703 { 0x00, 0x0008, 0x0000 }, 4704 { 0x0c, 0x3ff0, 0x0820 }, 4705 { 0x19, 0xffff, 0x7c00 }, 4706 { 0x1e, 0xffff, 0x20eb }, 4707 { 0x0d, 0xffff, 0x1666 }, 4708 { 0x00, 0xffff, 0x10a3 }, 4709 { 0x06, 0xffff, 0xf050 }, 4710 { 0x04, 0x0000, 0x0010 }, 4711 { 0x1d, 0x4000, 0x0000 }, 4712 }; 4713 4714 rtl_hw_start_8168g(tp); 4715 4716 /* disable aspm and clock request before access ephy */ 4717 rtl_hw_aspm_clkreq_enable(tp, false); 4718 rtl_ephy_init(tp, e_info_8168g_2); 4719 } 4720 4721 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 4722 { 4723 static const struct ephy_info e_info_8411_2[] = { 4724 { 0x00, 0x0008, 0x0000 }, 4725 { 0x0c, 0x37d0, 0x0820 }, 4726 { 0x1e, 0x0000, 0x0001 }, 4727 { 0x19, 0x8021, 0x0000 }, 4728 { 0x1e, 0x0000, 0x2000 }, 4729 { 0x0d, 0x0100, 0x0200 }, 4730 { 0x00, 0x0000, 0x0080 }, 4731 { 0x06, 0x0000, 0x0010 }, 4732 { 0x04, 0x0000, 0x0010 }, 4733 { 0x1d, 0x0000, 0x4000 }, 4734 }; 4735 4736 rtl_hw_start_8168g(tp); 4737 4738 /* disable aspm and clock request before access ephy */ 4739 rtl_hw_aspm_clkreq_enable(tp, false); 4740 rtl_ephy_init(tp, e_info_8411_2); 4741 4742 /* The following Realtek-provided magic fixes an issue with the RX unit 4743 * getting confused after the PHY having been powered-down. 4744 */ 4745 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 4746 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 4747 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 4748 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 4749 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 4750 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 4751 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 4752 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 4753 mdelay(3); 4754 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 4755 4756 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 4757 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 4758 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 4759 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 4760 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 4761 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 4762 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 4763 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 4764 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 4765 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 4766 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 4767 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 4768 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 4769 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 4770 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 4771 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 4772 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 4773 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 4774 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 4775 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 4776 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 4777 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 4778 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 4779 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 4780 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 4781 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 4782 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 4783 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 4784 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 4785 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 4786 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 4787 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 4788 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 4789 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 4790 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 4791 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 4792 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 4793 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 4794 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 4795 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 4796 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 4797 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 4798 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 4799 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 4800 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 4801 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 4802 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 4803 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 4804 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 4805 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 4806 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 4807 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 4808 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 4809 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 4810 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 4811 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 4812 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 4813 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 4814 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 4815 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 4816 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 4817 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 4818 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 4819 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 4820 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 4821 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 4822 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 4823 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 4824 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 4825 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 4826 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 4827 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 4828 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 4829 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 4830 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 4831 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 4832 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 4833 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 4834 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 4835 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 4836 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 4837 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 4838 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 4839 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 4840 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 4841 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 4842 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 4843 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 4844 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 4845 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 4846 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 4847 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 4848 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 4849 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 4850 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 4851 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 4852 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 4853 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 4854 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 4855 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 4856 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 4857 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 4858 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 4859 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 4860 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 4861 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 4862 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 4863 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 4864 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 4865 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 4866 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 4867 4868 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 4869 4870 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 4871 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 4872 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 4873 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 4874 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 4875 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 4876 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 4877 4878 rtl_hw_aspm_clkreq_enable(tp, true); 4879 } 4880 4881 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 4882 { 4883 static const struct ephy_info e_info_8168h_1[] = { 4884 { 0x1e, 0x0800, 0x0001 }, 4885 { 0x1d, 0x0000, 0x0800 }, 4886 { 0x05, 0xffff, 0x2089 }, 4887 { 0x06, 0xffff, 0x5881 }, 4888 { 0x04, 0xffff, 0x854a }, 4889 { 0x01, 0xffff, 0x068b } 4890 }; 4891 int rg_saw_cnt; 4892 4893 /* disable aspm and clock request before access ephy */ 4894 rtl_hw_aspm_clkreq_enable(tp, false); 4895 rtl_ephy_init(tp, e_info_8168h_1); 4896 4897 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4898 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4899 4900 rtl_set_def_aspm_entry_latency(tp); 4901 4902 rtl_reset_packet_filter(tp); 4903 4904 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 4905 4906 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 4907 4908 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4909 4910 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4911 4912 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4913 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4914 4915 rtl8168_config_eee_mac(tp); 4916 4917 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4918 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4919 4920 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4921 4922 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4923 4924 rtl_pcie_state_l2l3_disable(tp); 4925 4926 rtl_writephy(tp, 0x1f, 0x0c42); 4927 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff); 4928 rtl_writephy(tp, 0x1f, 0x0000); 4929 if (rg_saw_cnt > 0) { 4930 u16 sw_cnt_1ms_ini; 4931 4932 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 4933 sw_cnt_1ms_ini &= 0x0fff; 4934 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 4935 } 4936 4937 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 4938 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 4939 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 4940 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 4941 4942 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 4943 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 4944 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 4945 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 4946 4947 rtl_hw_aspm_clkreq_enable(tp, true); 4948 } 4949 4950 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 4951 { 4952 rtl8168ep_stop_cmac(tp); 4953 4954 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4955 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 4956 4957 rtl_set_def_aspm_entry_latency(tp); 4958 4959 rtl_reset_packet_filter(tp); 4960 4961 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 4962 4963 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4964 4965 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4966 4967 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4968 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4969 4970 rtl8168_config_eee_mac(tp); 4971 4972 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4973 4974 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4975 4976 rtl_pcie_state_l2l3_disable(tp); 4977 } 4978 4979 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 4980 { 4981 static const struct ephy_info e_info_8168ep_1[] = { 4982 { 0x00, 0xffff, 0x10ab }, 4983 { 0x06, 0xffff, 0xf030 }, 4984 { 0x08, 0xffff, 0x2006 }, 4985 { 0x0d, 0xffff, 0x1666 }, 4986 { 0x0c, 0x3ff0, 0x0000 } 4987 }; 4988 4989 /* disable aspm and clock request before access ephy */ 4990 rtl_hw_aspm_clkreq_enable(tp, false); 4991 rtl_ephy_init(tp, e_info_8168ep_1); 4992 4993 rtl_hw_start_8168ep(tp); 4994 4995 rtl_hw_aspm_clkreq_enable(tp, true); 4996 } 4997 4998 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 4999 { 5000 static const struct ephy_info e_info_8168ep_2[] = { 5001 { 0x00, 0xffff, 0x10a3 }, 5002 { 0x19, 0xffff, 0xfc00 }, 5003 { 0x1e, 0xffff, 0x20ea } 5004 }; 5005 5006 /* disable aspm and clock request before access ephy */ 5007 rtl_hw_aspm_clkreq_enable(tp, false); 5008 rtl_ephy_init(tp, e_info_8168ep_2); 5009 5010 rtl_hw_start_8168ep(tp); 5011 5012 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5013 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 5014 5015 rtl_hw_aspm_clkreq_enable(tp, true); 5016 } 5017 5018 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 5019 { 5020 static const struct ephy_info e_info_8168ep_3[] = { 5021 { 0x00, 0x0000, 0x0080 }, 5022 { 0x0d, 0x0100, 0x0200 }, 5023 { 0x19, 0x8021, 0x0000 }, 5024 { 0x1e, 0x0000, 0x2000 }, 5025 }; 5026 5027 /* disable aspm and clock request before access ephy */ 5028 rtl_hw_aspm_clkreq_enable(tp, false); 5029 rtl_ephy_init(tp, e_info_8168ep_3); 5030 5031 rtl_hw_start_8168ep(tp); 5032 5033 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5034 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 5035 5036 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 5037 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 5038 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 5039 5040 rtl_hw_aspm_clkreq_enable(tp, true); 5041 } 5042 5043 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 5044 { 5045 static const struct ephy_info e_info_8102e_1[] = { 5046 { 0x01, 0, 0x6e65 }, 5047 { 0x02, 0, 0x091f }, 5048 { 0x03, 0, 0xc2f9 }, 5049 { 0x06, 0, 0xafb5 }, 5050 { 0x07, 0, 0x0e00 }, 5051 { 0x19, 0, 0xec80 }, 5052 { 0x01, 0, 0x2e65 }, 5053 { 0x01, 0, 0x6e65 } 5054 }; 5055 u8 cfg1; 5056 5057 rtl_set_def_aspm_entry_latency(tp); 5058 5059 RTL_W8(tp, DBG_REG, FIX_NAK_1); 5060 5061 RTL_W8(tp, Config1, 5062 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 5063 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5064 5065 cfg1 = RTL_R8(tp, Config1); 5066 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 5067 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 5068 5069 rtl_ephy_init(tp, e_info_8102e_1); 5070 } 5071 5072 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 5073 { 5074 rtl_set_def_aspm_entry_latency(tp); 5075 5076 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 5077 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5078 } 5079 5080 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 5081 { 5082 rtl_hw_start_8102e_2(tp); 5083 5084 rtl_ephy_write(tp, 0x03, 0xc2f9); 5085 } 5086 5087 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 5088 { 5089 static const struct ephy_info e_info_8105e_1[] = { 5090 { 0x07, 0, 0x4000 }, 5091 { 0x19, 0, 0x0200 }, 5092 { 0x19, 0, 0x0020 }, 5093 { 0x1e, 0, 0x2000 }, 5094 { 0x03, 0, 0x0001 }, 5095 { 0x19, 0, 0x0100 }, 5096 { 0x19, 0, 0x0004 }, 5097 { 0x0a, 0, 0x0020 } 5098 }; 5099 5100 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5101 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5102 5103 /* Disable Early Tally Counter */ 5104 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 5105 5106 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5107 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 5108 5109 rtl_ephy_init(tp, e_info_8105e_1); 5110 5111 rtl_pcie_state_l2l3_disable(tp); 5112 } 5113 5114 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 5115 { 5116 rtl_hw_start_8105e_1(tp); 5117 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 5118 } 5119 5120 static void rtl_hw_start_8402(struct rtl8169_private *tp) 5121 { 5122 static const struct ephy_info e_info_8402[] = { 5123 { 0x19, 0xffff, 0xff64 }, 5124 { 0x1e, 0, 0x4000 } 5125 }; 5126 5127 rtl_set_def_aspm_entry_latency(tp); 5128 5129 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5130 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5131 5132 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5133 5134 rtl_ephy_init(tp, e_info_8402); 5135 5136 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 5137 rtl_reset_packet_filter(tp); 5138 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 5139 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 5140 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 5141 5142 rtl_pcie_state_l2l3_disable(tp); 5143 } 5144 5145 static void rtl_hw_start_8106(struct rtl8169_private *tp) 5146 { 5147 rtl_hw_aspm_clkreq_enable(tp, false); 5148 5149 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5150 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5151 5152 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 5153 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5154 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5155 5156 rtl_pcie_state_l2l3_disable(tp); 5157 rtl_hw_aspm_clkreq_enable(tp, true); 5158 } 5159 5160 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 5161 { 5162 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 5163 } 5164 5165 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 5166 { 5167 rtl_pcie_state_l2l3_disable(tp); 5168 5169 RTL_W16(tp, 0x382, 0x221b); 5170 RTL_W8(tp, 0x4500, 0); 5171 RTL_W16(tp, 0x4800, 0); 5172 5173 /* disable UPS */ 5174 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 5175 5176 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 5177 5178 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 5179 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 5180 5181 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 5182 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 5183 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 5184 5185 /* disable new tx descriptor format */ 5186 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 5187 5188 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 5189 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 5190 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 5191 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 5192 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 5193 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 5194 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 5195 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 5196 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 5197 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 5198 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 5199 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 5200 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 5201 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 5202 udelay(1); 5203 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 5204 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 5205 5206 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 5207 5208 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 5209 5210 rtl8125_config_eee_mac(tp); 5211 5212 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 5213 udelay(10); 5214 } 5215 5216 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 5217 { 5218 static const struct ephy_info e_info_8125_1[] = { 5219 { 0x01, 0xffff, 0xa812 }, 5220 { 0x09, 0xffff, 0x520c }, 5221 { 0x04, 0xffff, 0xd000 }, 5222 { 0x0d, 0xffff, 0xf702 }, 5223 { 0x0a, 0xffff, 0x8653 }, 5224 { 0x06, 0xffff, 0x001e }, 5225 { 0x08, 0xffff, 0x3595 }, 5226 { 0x20, 0xffff, 0x9455 }, 5227 { 0x21, 0xffff, 0x99ff }, 5228 { 0x02, 0xffff, 0x6046 }, 5229 { 0x29, 0xffff, 0xfe00 }, 5230 { 0x23, 0xffff, 0xab62 }, 5231 5232 { 0x41, 0xffff, 0xa80c }, 5233 { 0x49, 0xffff, 0x520c }, 5234 { 0x44, 0xffff, 0xd000 }, 5235 { 0x4d, 0xffff, 0xf702 }, 5236 { 0x4a, 0xffff, 0x8653 }, 5237 { 0x46, 0xffff, 0x001e }, 5238 { 0x48, 0xffff, 0x3595 }, 5239 { 0x60, 0xffff, 0x9455 }, 5240 { 0x61, 0xffff, 0x99ff }, 5241 { 0x42, 0xffff, 0x6046 }, 5242 { 0x69, 0xffff, 0xfe00 }, 5243 { 0x63, 0xffff, 0xab62 }, 5244 }; 5245 5246 rtl_set_def_aspm_entry_latency(tp); 5247 5248 /* disable aspm and clock request before access ephy */ 5249 rtl_hw_aspm_clkreq_enable(tp, false); 5250 rtl_ephy_init(tp, e_info_8125_1); 5251 5252 rtl_hw_start_8125_common(tp); 5253 } 5254 5255 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 5256 { 5257 static const struct ephy_info e_info_8125_2[] = { 5258 { 0x04, 0xffff, 0xd000 }, 5259 { 0x0a, 0xffff, 0x8653 }, 5260 { 0x23, 0xffff, 0xab66 }, 5261 { 0x20, 0xffff, 0x9455 }, 5262 { 0x21, 0xffff, 0x99ff }, 5263 { 0x29, 0xffff, 0xfe04 }, 5264 5265 { 0x44, 0xffff, 0xd000 }, 5266 { 0x4a, 0xffff, 0x8653 }, 5267 { 0x63, 0xffff, 0xab66 }, 5268 { 0x60, 0xffff, 0x9455 }, 5269 { 0x61, 0xffff, 0x99ff }, 5270 { 0x69, 0xffff, 0xfe04 }, 5271 }; 5272 5273 rtl_set_def_aspm_entry_latency(tp); 5274 5275 /* disable aspm and clock request before access ephy */ 5276 rtl_hw_aspm_clkreq_enable(tp, false); 5277 rtl_ephy_init(tp, e_info_8125_2); 5278 5279 rtl_hw_start_8125_common(tp); 5280 } 5281 5282 static void rtl_hw_config(struct rtl8169_private *tp) 5283 { 5284 static const rtl_generic_fct hw_configs[] = { 5285 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 5286 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 5287 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 5288 [RTL_GIGA_MAC_VER_10] = NULL, 5289 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 5290 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 5291 [RTL_GIGA_MAC_VER_13] = NULL, 5292 [RTL_GIGA_MAC_VER_14] = NULL, 5293 [RTL_GIGA_MAC_VER_15] = NULL, 5294 [RTL_GIGA_MAC_VER_16] = NULL, 5295 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 5296 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 5297 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 5298 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 5299 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 5300 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 5301 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 5302 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 5303 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 5304 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 5305 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 5306 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 5307 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 5308 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 5309 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 5310 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 5311 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 5312 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 5313 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 5314 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 5315 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 5316 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 5317 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 5318 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 5319 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 5320 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 5321 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 5322 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 5323 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 5324 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 5325 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 5326 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 5327 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 5328 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 5329 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 5330 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 5331 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 5332 }; 5333 5334 if (hw_configs[tp->mac_version]) 5335 hw_configs[tp->mac_version](tp); 5336 } 5337 5338 static void rtl_hw_start_8125(struct rtl8169_private *tp) 5339 { 5340 int i; 5341 5342 /* disable interrupt coalescing */ 5343 for (i = 0xa00; i < 0xb00; i += 4) 5344 RTL_W32(tp, i, 0); 5345 5346 rtl_hw_config(tp); 5347 } 5348 5349 static void rtl_hw_start_8168(struct rtl8169_private *tp) 5350 { 5351 if (rtl_is_8168evl_up(tp)) 5352 RTL_W8(tp, MaxTxPacketSize, EarlySize); 5353 else 5354 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5355 5356 rtl_hw_config(tp); 5357 5358 /* disable interrupt coalescing */ 5359 RTL_W16(tp, IntrMitigate, 0x0000); 5360 } 5361 5362 static void rtl_hw_start_8169(struct rtl8169_private *tp) 5363 { 5364 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5365 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 5366 5367 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 5368 5369 tp->cp_cmd |= PCIMulRW; 5370 5371 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 5372 tp->mac_version == RTL_GIGA_MAC_VER_03) { 5373 netif_dbg(tp, drv, tp->dev, 5374 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n"); 5375 tp->cp_cmd |= (1 << 14); 5376 } 5377 5378 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5379 5380 rtl8169_set_magic_reg(tp, tp->mac_version); 5381 5382 RTL_W32(tp, RxMissed, 0); 5383 5384 /* disable interrupt coalescing */ 5385 RTL_W16(tp, IntrMitigate, 0x0000); 5386 } 5387 5388 static void rtl_hw_start(struct rtl8169_private *tp) 5389 { 5390 rtl_unlock_config_regs(tp); 5391 5392 tp->cp_cmd &= CPCMD_MASK; 5393 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5394 5395 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5396 rtl_hw_start_8169(tp); 5397 else if (rtl_is_8125(tp)) 5398 rtl_hw_start_8125(tp); 5399 else 5400 rtl_hw_start_8168(tp); 5401 5402 rtl_set_rx_max_size(tp); 5403 rtl_set_rx_tx_desc_registers(tp); 5404 rtl_lock_config_regs(tp); 5405 5406 rtl_jumbo_config(tp, tp->dev->mtu); 5407 5408 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 5409 RTL_R16(tp, CPlusCmd); 5410 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 5411 rtl_init_rxcfg(tp); 5412 rtl_set_tx_config_registers(tp); 5413 rtl_set_rx_mode(tp->dev); 5414 rtl_irq_enable(tp); 5415 } 5416 5417 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 5418 { 5419 struct rtl8169_private *tp = netdev_priv(dev); 5420 5421 rtl_jumbo_config(tp, new_mtu); 5422 5423 dev->mtu = new_mtu; 5424 netdev_update_features(dev); 5425 5426 return 0; 5427 } 5428 5429 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) 5430 { 5431 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); 5432 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); 5433 } 5434 5435 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 5436 { 5437 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 5438 5439 /* Force memory writes to complete before releasing descriptor */ 5440 dma_wmb(); 5441 5442 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 5443 } 5444 5445 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 5446 struct RxDesc *desc) 5447 { 5448 struct device *d = tp_to_dev(tp); 5449 int node = dev_to_node(d); 5450 dma_addr_t mapping; 5451 struct page *data; 5452 5453 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 5454 if (!data) 5455 return NULL; 5456 5457 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5458 if (unlikely(dma_mapping_error(d, mapping))) { 5459 if (net_ratelimit()) 5460 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); 5461 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 5462 return NULL; 5463 } 5464 5465 desc->addr = cpu_to_le64(mapping); 5466 rtl8169_mark_to_asic(desc); 5467 5468 return data; 5469 } 5470 5471 static void rtl8169_rx_clear(struct rtl8169_private *tp) 5472 { 5473 unsigned int i; 5474 5475 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 5476 dma_unmap_page(tp_to_dev(tp), 5477 le64_to_cpu(tp->RxDescArray[i].addr), 5478 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5479 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 5480 tp->Rx_databuff[i] = NULL; 5481 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5482 } 5483 } 5484 5485 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) 5486 { 5487 desc->opts1 |= cpu_to_le32(RingEnd); 5488 } 5489 5490 static int rtl8169_rx_fill(struct rtl8169_private *tp) 5491 { 5492 unsigned int i; 5493 5494 for (i = 0; i < NUM_RX_DESC; i++) { 5495 struct page *data; 5496 5497 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 5498 if (!data) { 5499 rtl8169_rx_clear(tp); 5500 return -ENOMEM; 5501 } 5502 tp->Rx_databuff[i] = data; 5503 } 5504 5505 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); 5506 5507 return 0; 5508 } 5509 5510 static int rtl8169_init_ring(struct rtl8169_private *tp) 5511 { 5512 rtl8169_init_ring_indexes(tp); 5513 5514 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 5515 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 5516 5517 return rtl8169_rx_fill(tp); 5518 } 5519 5520 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, 5521 struct TxDesc *desc) 5522 { 5523 unsigned int len = tx_skb->len; 5524 5525 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); 5526 5527 desc->opts1 = 0x00; 5528 desc->opts2 = 0x00; 5529 desc->addr = 0x00; 5530 tx_skb->len = 0; 5531 } 5532 5533 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 5534 unsigned int n) 5535 { 5536 unsigned int i; 5537 5538 for (i = 0; i < n; i++) { 5539 unsigned int entry = (start + i) % NUM_TX_DESC; 5540 struct ring_info *tx_skb = tp->tx_skb + entry; 5541 unsigned int len = tx_skb->len; 5542 5543 if (len) { 5544 struct sk_buff *skb = tx_skb->skb; 5545 5546 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5547 tp->TxDescArray + entry); 5548 if (skb) { 5549 dev_consume_skb_any(skb); 5550 tx_skb->skb = NULL; 5551 } 5552 } 5553 } 5554 } 5555 5556 static void rtl8169_tx_clear(struct rtl8169_private *tp) 5557 { 5558 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 5559 tp->cur_tx = tp->dirty_tx = 0; 5560 netdev_reset_queue(tp->dev); 5561 } 5562 5563 static void rtl_reset_work(struct rtl8169_private *tp) 5564 { 5565 struct net_device *dev = tp->dev; 5566 int i; 5567 5568 napi_disable(&tp->napi); 5569 netif_stop_queue(dev); 5570 synchronize_rcu(); 5571 5572 rtl8169_hw_reset(tp); 5573 5574 for (i = 0; i < NUM_RX_DESC; i++) 5575 rtl8169_mark_to_asic(tp->RxDescArray + i); 5576 5577 rtl8169_tx_clear(tp); 5578 rtl8169_init_ring_indexes(tp); 5579 5580 napi_enable(&tp->napi); 5581 rtl_hw_start(tp); 5582 netif_wake_queue(dev); 5583 } 5584 5585 static void rtl8169_tx_timeout(struct net_device *dev) 5586 { 5587 struct rtl8169_private *tp = netdev_priv(dev); 5588 5589 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5590 } 5591 5592 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry) 5593 { 5594 u32 status = opts0 | len; 5595 5596 if (entry == NUM_TX_DESC - 1) 5597 status |= RingEnd; 5598 5599 return cpu_to_le32(status); 5600 } 5601 5602 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 5603 u32 *opts) 5604 { 5605 struct skb_shared_info *info = skb_shinfo(skb); 5606 unsigned int cur_frag, entry; 5607 struct TxDesc *uninitialized_var(txd); 5608 struct device *d = tp_to_dev(tp); 5609 5610 entry = tp->cur_tx; 5611 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 5612 const skb_frag_t *frag = info->frags + cur_frag; 5613 dma_addr_t mapping; 5614 u32 len; 5615 void *addr; 5616 5617 entry = (entry + 1) % NUM_TX_DESC; 5618 5619 txd = tp->TxDescArray + entry; 5620 len = skb_frag_size(frag); 5621 addr = skb_frag_address(frag); 5622 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 5623 if (unlikely(dma_mapping_error(d, mapping))) { 5624 if (net_ratelimit()) 5625 netif_err(tp, drv, tp->dev, 5626 "Failed to map TX fragments DMA!\n"); 5627 goto err_out; 5628 } 5629 5630 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5631 txd->opts2 = cpu_to_le32(opts[1]); 5632 txd->addr = cpu_to_le64(mapping); 5633 5634 tp->tx_skb[entry].len = len; 5635 } 5636 5637 if (cur_frag) { 5638 tp->tx_skb[entry].skb = skb; 5639 txd->opts1 |= cpu_to_le32(LastFrag); 5640 } 5641 5642 return cur_frag; 5643 5644 err_out: 5645 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 5646 return -EIO; 5647 } 5648 5649 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 5650 { 5651 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 5652 } 5653 5654 /* msdn_giant_send_check() 5655 * According to the document of microsoft, the TCP Pseudo Header excludes the 5656 * packet length for IPv6 TCP large packets. 5657 */ 5658 static int msdn_giant_send_check(struct sk_buff *skb) 5659 { 5660 const struct ipv6hdr *ipv6h; 5661 struct tcphdr *th; 5662 int ret; 5663 5664 ret = skb_cow_head(skb, 0); 5665 if (ret) 5666 return ret; 5667 5668 ipv6h = ipv6_hdr(skb); 5669 th = tcp_hdr(skb); 5670 5671 th->check = 0; 5672 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 5673 5674 return ret; 5675 } 5676 5677 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 5678 { 5679 u32 mss = skb_shinfo(skb)->gso_size; 5680 5681 if (mss) { 5682 opts[0] |= TD_LSO; 5683 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; 5684 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5685 const struct iphdr *ip = ip_hdr(skb); 5686 5687 if (ip->protocol == IPPROTO_TCP) 5688 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 5689 else if (ip->protocol == IPPROTO_UDP) 5690 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 5691 else 5692 WARN_ON_ONCE(1); 5693 } 5694 } 5695 5696 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 5697 struct sk_buff *skb, u32 *opts) 5698 { 5699 u32 transport_offset = (u32)skb_transport_offset(skb); 5700 u32 mss = skb_shinfo(skb)->gso_size; 5701 5702 if (mss) { 5703 switch (vlan_get_protocol(skb)) { 5704 case htons(ETH_P_IP): 5705 opts[0] |= TD1_GTSENV4; 5706 break; 5707 5708 case htons(ETH_P_IPV6): 5709 if (msdn_giant_send_check(skb)) 5710 return false; 5711 5712 opts[0] |= TD1_GTSENV6; 5713 break; 5714 5715 default: 5716 WARN_ON_ONCE(1); 5717 break; 5718 } 5719 5720 opts[0] |= transport_offset << GTTCPHO_SHIFT; 5721 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; 5722 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5723 u8 ip_protocol; 5724 5725 switch (vlan_get_protocol(skb)) { 5726 case htons(ETH_P_IP): 5727 opts[1] |= TD1_IPv4_CS; 5728 ip_protocol = ip_hdr(skb)->protocol; 5729 break; 5730 5731 case htons(ETH_P_IPV6): 5732 opts[1] |= TD1_IPv6_CS; 5733 ip_protocol = ipv6_hdr(skb)->nexthdr; 5734 break; 5735 5736 default: 5737 ip_protocol = IPPROTO_RAW; 5738 break; 5739 } 5740 5741 if (ip_protocol == IPPROTO_TCP) 5742 opts[1] |= TD1_TCP_CS; 5743 else if (ip_protocol == IPPROTO_UDP) 5744 opts[1] |= TD1_UDP_CS; 5745 else 5746 WARN_ON_ONCE(1); 5747 5748 opts[1] |= transport_offset << TCPHO_SHIFT; 5749 } else { 5750 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 5751 return !eth_skb_pad(skb); 5752 } 5753 5754 return true; 5755 } 5756 5757 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 5758 unsigned int nr_frags) 5759 { 5760 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 5761 5762 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 5763 return slots_avail > nr_frags; 5764 } 5765 5766 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 5767 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 5768 { 5769 switch (tp->mac_version) { 5770 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5771 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 5772 return false; 5773 default: 5774 return true; 5775 } 5776 } 5777 5778 static void rtl8169_doorbell(struct rtl8169_private *tp) 5779 { 5780 if (rtl_is_8125(tp)) 5781 RTL_W16(tp, TxPoll_8125, BIT(0)); 5782 else 5783 RTL_W8(tp, TxPoll, NPQ); 5784 } 5785 5786 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 5787 struct net_device *dev) 5788 { 5789 struct rtl8169_private *tp = netdev_priv(dev); 5790 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 5791 struct TxDesc *txd = tp->TxDescArray + entry; 5792 struct device *d = tp_to_dev(tp); 5793 dma_addr_t mapping; 5794 u32 opts[2], len; 5795 bool stop_queue; 5796 bool door_bell; 5797 int frags; 5798 5799 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) { 5800 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 5801 goto err_stop_0; 5802 } 5803 5804 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) 5805 goto err_stop_0; 5806 5807 opts[1] = rtl8169_tx_vlan_tag(skb); 5808 opts[0] = DescOwn; 5809 5810 if (rtl_chip_supports_csum_v2(tp)) { 5811 if (!rtl8169_tso_csum_v2(tp, skb, opts)) 5812 goto err_dma_0; 5813 } else { 5814 rtl8169_tso_csum_v1(skb, opts); 5815 } 5816 5817 len = skb_headlen(skb); 5818 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); 5819 if (unlikely(dma_mapping_error(d, mapping))) { 5820 if (net_ratelimit()) 5821 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); 5822 goto err_dma_0; 5823 } 5824 5825 tp->tx_skb[entry].len = len; 5826 txd->addr = cpu_to_le64(mapping); 5827 5828 frags = rtl8169_xmit_frags(tp, skb, opts); 5829 if (frags < 0) 5830 goto err_dma_1; 5831 else if (frags) 5832 opts[0] |= FirstFrag; 5833 else { 5834 opts[0] |= FirstFrag | LastFrag; 5835 tp->tx_skb[entry].skb = skb; 5836 } 5837 5838 txd->opts2 = cpu_to_le32(opts[1]); 5839 5840 skb_tx_timestamp(skb); 5841 5842 /* Force memory writes to complete before releasing descriptor */ 5843 dma_wmb(); 5844 5845 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 5846 5847 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5848 5849 /* Force all memory writes to complete before notifying device */ 5850 wmb(); 5851 5852 tp->cur_tx += frags + 1; 5853 5854 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 5855 if (unlikely(stop_queue)) { 5856 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 5857 * not miss a ring update when it notices a stopped queue. 5858 */ 5859 smp_wmb(); 5860 netif_stop_queue(dev); 5861 door_bell = true; 5862 } 5863 5864 if (door_bell) 5865 rtl8169_doorbell(tp); 5866 5867 if (unlikely(stop_queue)) { 5868 /* Sync with rtl_tx: 5869 * - publish queue status and cur_tx ring index (write barrier) 5870 * - refresh dirty_tx ring index (read barrier). 5871 * May the current thread have a pessimistic view of the ring 5872 * status and forget to wake up queue, a racing rtl_tx thread 5873 * can't. 5874 */ 5875 smp_mb(); 5876 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 5877 netif_start_queue(dev); 5878 } 5879 5880 return NETDEV_TX_OK; 5881 5882 err_dma_1: 5883 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); 5884 err_dma_0: 5885 dev_kfree_skb_any(skb); 5886 dev->stats.tx_dropped++; 5887 return NETDEV_TX_OK; 5888 5889 err_stop_0: 5890 netif_stop_queue(dev); 5891 dev->stats.tx_dropped++; 5892 return NETDEV_TX_BUSY; 5893 } 5894 5895 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 5896 struct net_device *dev, 5897 netdev_features_t features) 5898 { 5899 int transport_offset = skb_transport_offset(skb); 5900 struct rtl8169_private *tp = netdev_priv(dev); 5901 5902 if (skb_is_gso(skb)) { 5903 if (transport_offset > GTTCPHO_MAX && 5904 rtl_chip_supports_csum_v2(tp)) 5905 features &= ~NETIF_F_ALL_TSO; 5906 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5907 if (skb->len < ETH_ZLEN) { 5908 switch (tp->mac_version) { 5909 case RTL_GIGA_MAC_VER_11: 5910 case RTL_GIGA_MAC_VER_12: 5911 case RTL_GIGA_MAC_VER_17: 5912 case RTL_GIGA_MAC_VER_34: 5913 features &= ~NETIF_F_CSUM_MASK; 5914 break; 5915 default: 5916 break; 5917 } 5918 } 5919 5920 if (transport_offset > TCPHO_MAX && 5921 rtl_chip_supports_csum_v2(tp)) 5922 features &= ~NETIF_F_CSUM_MASK; 5923 } 5924 5925 return vlan_features_check(skb, features); 5926 } 5927 5928 static void rtl8169_pcierr_interrupt(struct net_device *dev) 5929 { 5930 struct rtl8169_private *tp = netdev_priv(dev); 5931 struct pci_dev *pdev = tp->pci_dev; 5932 u16 pci_status, pci_cmd; 5933 5934 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 5935 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 5936 5937 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", 5938 pci_cmd, pci_status); 5939 5940 /* 5941 * The recovery sequence below admits a very elaborated explanation: 5942 * - it seems to work; 5943 * - I did not see what else could be done; 5944 * - it makes iop3xx happy. 5945 * 5946 * Feel free to adjust to your needs. 5947 */ 5948 if (pdev->broken_parity_status) 5949 pci_cmd &= ~PCI_COMMAND_PARITY; 5950 else 5951 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 5952 5953 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 5954 5955 pci_write_config_word(pdev, PCI_STATUS, 5956 pci_status & (PCI_STATUS_DETECTED_PARITY | 5957 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | 5958 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); 5959 5960 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5961 } 5962 5963 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 5964 int budget) 5965 { 5966 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 5967 5968 dirty_tx = tp->dirty_tx; 5969 smp_rmb(); 5970 tx_left = tp->cur_tx - dirty_tx; 5971 5972 while (tx_left > 0) { 5973 unsigned int entry = dirty_tx % NUM_TX_DESC; 5974 struct ring_info *tx_skb = tp->tx_skb + entry; 5975 u32 status; 5976 5977 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 5978 if (status & DescOwn) 5979 break; 5980 5981 /* This barrier is needed to keep us from reading 5982 * any other fields out of the Tx descriptor until 5983 * we know the status of DescOwn 5984 */ 5985 dma_rmb(); 5986 5987 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5988 tp->TxDescArray + entry); 5989 if (tx_skb->skb) { 5990 pkts_compl++; 5991 bytes_compl += tx_skb->skb->len; 5992 napi_consume_skb(tx_skb->skb, budget); 5993 tx_skb->skb = NULL; 5994 } 5995 dirty_tx++; 5996 tx_left--; 5997 } 5998 5999 if (tp->dirty_tx != dirty_tx) { 6000 netdev_completed_queue(dev, pkts_compl, bytes_compl); 6001 6002 u64_stats_update_begin(&tp->tx_stats.syncp); 6003 tp->tx_stats.packets += pkts_compl; 6004 tp->tx_stats.bytes += bytes_compl; 6005 u64_stats_update_end(&tp->tx_stats.syncp); 6006 6007 tp->dirty_tx = dirty_tx; 6008 /* Sync with rtl8169_start_xmit: 6009 * - publish dirty_tx ring index (write barrier) 6010 * - refresh cur_tx ring index and queue status (read barrier) 6011 * May the current thread miss the stopped queue condition, 6012 * a racing xmit thread can only have a right view of the 6013 * ring status. 6014 */ 6015 smp_mb(); 6016 if (netif_queue_stopped(dev) && 6017 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 6018 netif_wake_queue(dev); 6019 } 6020 /* 6021 * 8168 hack: TxPoll requests are lost when the Tx packets are 6022 * too close. Let's kick an extra TxPoll request when a burst 6023 * of start_xmit activity is detected (if it is not detected, 6024 * it is slow enough). -- FR 6025 */ 6026 if (tp->cur_tx != dirty_tx) 6027 rtl8169_doorbell(tp); 6028 } 6029 } 6030 6031 static inline int rtl8169_fragmented_frame(u32 status) 6032 { 6033 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 6034 } 6035 6036 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 6037 { 6038 u32 status = opts1 & RxProtoMask; 6039 6040 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 6041 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 6042 skb->ip_summed = CHECKSUM_UNNECESSARY; 6043 else 6044 skb_checksum_none_assert(skb); 6045 } 6046 6047 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 6048 { 6049 unsigned int cur_rx, rx_left; 6050 unsigned int count; 6051 6052 cur_rx = tp->cur_rx; 6053 6054 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 6055 unsigned int entry = cur_rx % NUM_RX_DESC; 6056 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 6057 struct RxDesc *desc = tp->RxDescArray + entry; 6058 u32 status; 6059 6060 status = le32_to_cpu(desc->opts1); 6061 if (status & DescOwn) 6062 break; 6063 6064 /* This barrier is needed to keep us from reading 6065 * any other fields out of the Rx descriptor until 6066 * we know the status of DescOwn 6067 */ 6068 dma_rmb(); 6069 6070 if (unlikely(status & RxRES)) { 6071 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", 6072 status); 6073 dev->stats.rx_errors++; 6074 if (status & (RxRWT | RxRUNT)) 6075 dev->stats.rx_length_errors++; 6076 if (status & RxCRC) 6077 dev->stats.rx_crc_errors++; 6078 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 6079 dev->features & NETIF_F_RXALL) { 6080 goto process_pkt; 6081 } 6082 } else { 6083 unsigned int pkt_size; 6084 struct sk_buff *skb; 6085 6086 process_pkt: 6087 pkt_size = status & GENMASK(13, 0); 6088 if (likely(!(dev->features & NETIF_F_RXFCS))) 6089 pkt_size -= ETH_FCS_LEN; 6090 /* 6091 * The driver does not support incoming fragmented 6092 * frames. They are seen as a symptom of over-mtu 6093 * sized frames. 6094 */ 6095 if (unlikely(rtl8169_fragmented_frame(status))) { 6096 dev->stats.rx_dropped++; 6097 dev->stats.rx_length_errors++; 6098 goto release_descriptor; 6099 } 6100 6101 skb = napi_alloc_skb(&tp->napi, pkt_size); 6102 if (unlikely(!skb)) { 6103 dev->stats.rx_dropped++; 6104 goto release_descriptor; 6105 } 6106 6107 dma_sync_single_for_cpu(tp_to_dev(tp), 6108 le64_to_cpu(desc->addr), 6109 pkt_size, DMA_FROM_DEVICE); 6110 prefetch(rx_buf); 6111 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 6112 skb->tail += pkt_size; 6113 skb->len = pkt_size; 6114 6115 dma_sync_single_for_device(tp_to_dev(tp), 6116 le64_to_cpu(desc->addr), 6117 pkt_size, DMA_FROM_DEVICE); 6118 6119 rtl8169_rx_csum(skb, status); 6120 skb->protocol = eth_type_trans(skb, dev); 6121 6122 rtl8169_rx_vlan_tag(desc, skb); 6123 6124 if (skb->pkt_type == PACKET_MULTICAST) 6125 dev->stats.multicast++; 6126 6127 napi_gro_receive(&tp->napi, skb); 6128 6129 u64_stats_update_begin(&tp->rx_stats.syncp); 6130 tp->rx_stats.packets++; 6131 tp->rx_stats.bytes += pkt_size; 6132 u64_stats_update_end(&tp->rx_stats.syncp); 6133 } 6134 release_descriptor: 6135 desc->opts2 = 0; 6136 rtl8169_mark_to_asic(desc); 6137 } 6138 6139 count = cur_rx - tp->cur_rx; 6140 tp->cur_rx = cur_rx; 6141 6142 return count; 6143 } 6144 6145 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 6146 { 6147 struct rtl8169_private *tp = dev_instance; 6148 u32 status = rtl_get_events(tp); 6149 6150 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 6151 !(status & tp->irq_mask)) 6152 return IRQ_NONE; 6153 6154 if (unlikely(status & SYSErr)) { 6155 rtl8169_pcierr_interrupt(tp->dev); 6156 goto out; 6157 } 6158 6159 if (status & LinkChg) 6160 phy_mac_interrupt(tp->phydev); 6161 6162 if (unlikely(status & RxFIFOOver && 6163 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 6164 netif_stop_queue(tp->dev); 6165 /* XXX - Hack alert. See rtl_task(). */ 6166 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); 6167 } 6168 6169 rtl_irq_disable(tp); 6170 napi_schedule_irqoff(&tp->napi); 6171 out: 6172 rtl_ack_events(tp, status); 6173 6174 return IRQ_HANDLED; 6175 } 6176 6177 static void rtl_task(struct work_struct *work) 6178 { 6179 static const struct { 6180 int bitnr; 6181 void (*action)(struct rtl8169_private *); 6182 } rtl_work[] = { 6183 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, 6184 }; 6185 struct rtl8169_private *tp = 6186 container_of(work, struct rtl8169_private, wk.work); 6187 struct net_device *dev = tp->dev; 6188 int i; 6189 6190 rtl_lock_work(tp); 6191 6192 if (!netif_running(dev) || 6193 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 6194 goto out_unlock; 6195 6196 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { 6197 bool pending; 6198 6199 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); 6200 if (pending) 6201 rtl_work[i].action(tp); 6202 } 6203 6204 out_unlock: 6205 rtl_unlock_work(tp); 6206 } 6207 6208 static int rtl8169_poll(struct napi_struct *napi, int budget) 6209 { 6210 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 6211 struct net_device *dev = tp->dev; 6212 int work_done; 6213 6214 work_done = rtl_rx(dev, tp, (u32) budget); 6215 6216 rtl_tx(dev, tp, budget); 6217 6218 if (work_done < budget) { 6219 napi_complete_done(napi, work_done); 6220 rtl_irq_enable(tp); 6221 } 6222 6223 return work_done; 6224 } 6225 6226 static void rtl8169_rx_missed(struct net_device *dev) 6227 { 6228 struct rtl8169_private *tp = netdev_priv(dev); 6229 6230 if (tp->mac_version > RTL_GIGA_MAC_VER_06) 6231 return; 6232 6233 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff; 6234 RTL_W32(tp, RxMissed, 0); 6235 } 6236 6237 static void r8169_phylink_handler(struct net_device *ndev) 6238 { 6239 struct rtl8169_private *tp = netdev_priv(ndev); 6240 6241 if (netif_carrier_ok(ndev)) { 6242 rtl_link_chg_patch(tp); 6243 pm_request_resume(&tp->pci_dev->dev); 6244 } else { 6245 pm_runtime_idle(&tp->pci_dev->dev); 6246 } 6247 6248 if (net_ratelimit()) 6249 phy_print_status(tp->phydev); 6250 } 6251 6252 static int r8169_phy_connect(struct rtl8169_private *tp) 6253 { 6254 struct phy_device *phydev = tp->phydev; 6255 phy_interface_t phy_mode; 6256 int ret; 6257 6258 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 6259 PHY_INTERFACE_MODE_MII; 6260 6261 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 6262 phy_mode); 6263 if (ret) 6264 return ret; 6265 6266 if (!tp->supports_gmii) 6267 phy_set_max_speed(phydev, SPEED_100); 6268 6269 phy_support_asym_pause(phydev); 6270 6271 phy_attached_info(phydev); 6272 6273 return 0; 6274 } 6275 6276 static void rtl8169_down(struct net_device *dev) 6277 { 6278 struct rtl8169_private *tp = netdev_priv(dev); 6279 6280 phy_stop(tp->phydev); 6281 6282 napi_disable(&tp->napi); 6283 netif_stop_queue(dev); 6284 6285 rtl8169_hw_reset(tp); 6286 /* 6287 * At this point device interrupts can not be enabled in any function, 6288 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) 6289 * and napi is disabled (rtl8169_poll). 6290 */ 6291 rtl8169_rx_missed(dev); 6292 6293 /* Give a racing hard_start_xmit a few cycles to complete. */ 6294 synchronize_rcu(); 6295 6296 rtl8169_tx_clear(tp); 6297 6298 rtl8169_rx_clear(tp); 6299 6300 rtl_pll_power_down(tp); 6301 } 6302 6303 static int rtl8169_close(struct net_device *dev) 6304 { 6305 struct rtl8169_private *tp = netdev_priv(dev); 6306 struct pci_dev *pdev = tp->pci_dev; 6307 6308 pm_runtime_get_sync(&pdev->dev); 6309 6310 /* Update counters before going down */ 6311 rtl8169_update_counters(tp); 6312 6313 rtl_lock_work(tp); 6314 /* Clear all task flags */ 6315 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6316 6317 rtl8169_down(dev); 6318 rtl_unlock_work(tp); 6319 6320 cancel_work_sync(&tp->wk.work); 6321 6322 phy_disconnect(tp->phydev); 6323 6324 pci_free_irq(pdev, 0, tp); 6325 6326 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6327 tp->RxPhyAddr); 6328 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6329 tp->TxPhyAddr); 6330 tp->TxDescArray = NULL; 6331 tp->RxDescArray = NULL; 6332 6333 pm_runtime_put_sync(&pdev->dev); 6334 6335 return 0; 6336 } 6337 6338 #ifdef CONFIG_NET_POLL_CONTROLLER 6339 static void rtl8169_netpoll(struct net_device *dev) 6340 { 6341 struct rtl8169_private *tp = netdev_priv(dev); 6342 6343 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 6344 } 6345 #endif 6346 6347 static int rtl_open(struct net_device *dev) 6348 { 6349 struct rtl8169_private *tp = netdev_priv(dev); 6350 struct pci_dev *pdev = tp->pci_dev; 6351 int retval = -ENOMEM; 6352 6353 pm_runtime_get_sync(&pdev->dev); 6354 6355 /* 6356 * Rx and Tx descriptors needs 256 bytes alignment. 6357 * dma_alloc_coherent provides more. 6358 */ 6359 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 6360 &tp->TxPhyAddr, GFP_KERNEL); 6361 if (!tp->TxDescArray) 6362 goto err_pm_runtime_put; 6363 6364 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 6365 &tp->RxPhyAddr, GFP_KERNEL); 6366 if (!tp->RxDescArray) 6367 goto err_free_tx_0; 6368 6369 retval = rtl8169_init_ring(tp); 6370 if (retval < 0) 6371 goto err_free_rx_1; 6372 6373 rtl_request_firmware(tp); 6374 6375 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 6376 dev->name); 6377 if (retval < 0) 6378 goto err_release_fw_2; 6379 6380 retval = r8169_phy_connect(tp); 6381 if (retval) 6382 goto err_free_irq; 6383 6384 rtl_lock_work(tp); 6385 6386 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6387 6388 napi_enable(&tp->napi); 6389 6390 rtl8169_init_phy(dev, tp); 6391 6392 rtl_pll_power_up(tp); 6393 6394 rtl_hw_start(tp); 6395 6396 if (!rtl8169_init_counter_offsets(tp)) 6397 netif_warn(tp, hw, dev, "counter reset/update failed\n"); 6398 6399 phy_start(tp->phydev); 6400 netif_start_queue(dev); 6401 6402 rtl_unlock_work(tp); 6403 6404 pm_runtime_put_sync(&pdev->dev); 6405 out: 6406 return retval; 6407 6408 err_free_irq: 6409 pci_free_irq(pdev, 0, tp); 6410 err_release_fw_2: 6411 rtl_release_firmware(tp); 6412 rtl8169_rx_clear(tp); 6413 err_free_rx_1: 6414 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6415 tp->RxPhyAddr); 6416 tp->RxDescArray = NULL; 6417 err_free_tx_0: 6418 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6419 tp->TxPhyAddr); 6420 tp->TxDescArray = NULL; 6421 err_pm_runtime_put: 6422 pm_runtime_put_noidle(&pdev->dev); 6423 goto out; 6424 } 6425 6426 static void 6427 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6428 { 6429 struct rtl8169_private *tp = netdev_priv(dev); 6430 struct pci_dev *pdev = tp->pci_dev; 6431 struct rtl8169_counters *counters = tp->counters; 6432 unsigned int start; 6433 6434 pm_runtime_get_noresume(&pdev->dev); 6435 6436 if (netif_running(dev) && pm_runtime_active(&pdev->dev)) 6437 rtl8169_rx_missed(dev); 6438 6439 do { 6440 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 6441 stats->rx_packets = tp->rx_stats.packets; 6442 stats->rx_bytes = tp->rx_stats.bytes; 6443 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 6444 6445 do { 6446 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 6447 stats->tx_packets = tp->tx_stats.packets; 6448 stats->tx_bytes = tp->tx_stats.bytes; 6449 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 6450 6451 stats->rx_dropped = dev->stats.rx_dropped; 6452 stats->tx_dropped = dev->stats.tx_dropped; 6453 stats->rx_length_errors = dev->stats.rx_length_errors; 6454 stats->rx_errors = dev->stats.rx_errors; 6455 stats->rx_crc_errors = dev->stats.rx_crc_errors; 6456 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 6457 stats->rx_missed_errors = dev->stats.rx_missed_errors; 6458 stats->multicast = dev->stats.multicast; 6459 6460 /* 6461 * Fetch additional counter values missing in stats collected by driver 6462 * from tally counters. 6463 */ 6464 if (pm_runtime_active(&pdev->dev)) 6465 rtl8169_update_counters(tp); 6466 6467 /* 6468 * Subtract values fetched during initalization. 6469 * See rtl8169_init_counter_offsets for a description why we do that. 6470 */ 6471 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 6472 le64_to_cpu(tp->tc_offset.tx_errors); 6473 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 6474 le32_to_cpu(tp->tc_offset.tx_multi_collision); 6475 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 6476 le16_to_cpu(tp->tc_offset.tx_aborted); 6477 6478 pm_runtime_put_noidle(&pdev->dev); 6479 } 6480 6481 static void rtl8169_net_suspend(struct net_device *dev) 6482 { 6483 struct rtl8169_private *tp = netdev_priv(dev); 6484 6485 if (!netif_running(dev)) 6486 return; 6487 6488 phy_stop(tp->phydev); 6489 netif_device_detach(dev); 6490 6491 rtl_lock_work(tp); 6492 napi_disable(&tp->napi); 6493 /* Clear all task flags */ 6494 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6495 6496 rtl_unlock_work(tp); 6497 6498 rtl_pll_power_down(tp); 6499 } 6500 6501 #ifdef CONFIG_PM 6502 6503 static int rtl8169_suspend(struct device *device) 6504 { 6505 struct net_device *dev = dev_get_drvdata(device); 6506 struct rtl8169_private *tp = netdev_priv(dev); 6507 6508 rtl8169_net_suspend(dev); 6509 clk_disable_unprepare(tp->clk); 6510 6511 return 0; 6512 } 6513 6514 static void __rtl8169_resume(struct net_device *dev) 6515 { 6516 struct rtl8169_private *tp = netdev_priv(dev); 6517 6518 netif_device_attach(dev); 6519 6520 rtl_pll_power_up(tp); 6521 rtl8169_init_phy(dev, tp); 6522 6523 phy_start(tp->phydev); 6524 6525 rtl_lock_work(tp); 6526 napi_enable(&tp->napi); 6527 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6528 rtl_reset_work(tp); 6529 rtl_unlock_work(tp); 6530 } 6531 6532 static int rtl8169_resume(struct device *device) 6533 { 6534 struct net_device *dev = dev_get_drvdata(device); 6535 struct rtl8169_private *tp = netdev_priv(dev); 6536 6537 rtl_rar_set(tp, dev->dev_addr); 6538 6539 clk_prepare_enable(tp->clk); 6540 6541 if (netif_running(dev)) 6542 __rtl8169_resume(dev); 6543 6544 return 0; 6545 } 6546 6547 static int rtl8169_runtime_suspend(struct device *device) 6548 { 6549 struct net_device *dev = dev_get_drvdata(device); 6550 struct rtl8169_private *tp = netdev_priv(dev); 6551 6552 if (!tp->TxDescArray) 6553 return 0; 6554 6555 rtl_lock_work(tp); 6556 __rtl8169_set_wol(tp, WAKE_ANY); 6557 rtl_unlock_work(tp); 6558 6559 rtl8169_net_suspend(dev); 6560 6561 /* Update counters before going runtime suspend */ 6562 rtl8169_rx_missed(dev); 6563 rtl8169_update_counters(tp); 6564 6565 return 0; 6566 } 6567 6568 static int rtl8169_runtime_resume(struct device *device) 6569 { 6570 struct net_device *dev = dev_get_drvdata(device); 6571 struct rtl8169_private *tp = netdev_priv(dev); 6572 6573 rtl_rar_set(tp, dev->dev_addr); 6574 6575 if (!tp->TxDescArray) 6576 return 0; 6577 6578 rtl_lock_work(tp); 6579 __rtl8169_set_wol(tp, tp->saved_wolopts); 6580 rtl_unlock_work(tp); 6581 6582 __rtl8169_resume(dev); 6583 6584 return 0; 6585 } 6586 6587 static int rtl8169_runtime_idle(struct device *device) 6588 { 6589 struct net_device *dev = dev_get_drvdata(device); 6590 6591 if (!netif_running(dev) || !netif_carrier_ok(dev)) 6592 pm_schedule_suspend(device, 10000); 6593 6594 return -EBUSY; 6595 } 6596 6597 static const struct dev_pm_ops rtl8169_pm_ops = { 6598 .suspend = rtl8169_suspend, 6599 .resume = rtl8169_resume, 6600 .freeze = rtl8169_suspend, 6601 .thaw = rtl8169_resume, 6602 .poweroff = rtl8169_suspend, 6603 .restore = rtl8169_resume, 6604 .runtime_suspend = rtl8169_runtime_suspend, 6605 .runtime_resume = rtl8169_runtime_resume, 6606 .runtime_idle = rtl8169_runtime_idle, 6607 }; 6608 6609 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 6610 6611 #else /* !CONFIG_PM */ 6612 6613 #define RTL8169_PM_OPS NULL 6614 6615 #endif /* !CONFIG_PM */ 6616 6617 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 6618 { 6619 /* WoL fails with 8168b when the receiver is disabled. */ 6620 switch (tp->mac_version) { 6621 case RTL_GIGA_MAC_VER_11: 6622 case RTL_GIGA_MAC_VER_12: 6623 case RTL_GIGA_MAC_VER_17: 6624 pci_clear_master(tp->pci_dev); 6625 6626 RTL_W8(tp, ChipCmd, CmdRxEnb); 6627 /* PCI commit */ 6628 RTL_R8(tp, ChipCmd); 6629 break; 6630 default: 6631 break; 6632 } 6633 } 6634 6635 static void rtl_shutdown(struct pci_dev *pdev) 6636 { 6637 struct net_device *dev = pci_get_drvdata(pdev); 6638 struct rtl8169_private *tp = netdev_priv(dev); 6639 6640 rtl8169_net_suspend(dev); 6641 6642 /* Restore original MAC address */ 6643 rtl_rar_set(tp, dev->perm_addr); 6644 6645 rtl8169_hw_reset(tp); 6646 6647 if (system_state == SYSTEM_POWER_OFF) { 6648 if (tp->saved_wolopts) { 6649 rtl_wol_suspend_quirk(tp); 6650 rtl_wol_shutdown_quirk(tp); 6651 } 6652 6653 pci_wake_from_d3(pdev, true); 6654 pci_set_power_state(pdev, PCI_D3hot); 6655 } 6656 } 6657 6658 static void rtl_remove_one(struct pci_dev *pdev) 6659 { 6660 struct net_device *dev = pci_get_drvdata(pdev); 6661 struct rtl8169_private *tp = netdev_priv(dev); 6662 6663 if (r8168_check_dash(tp)) 6664 rtl8168_driver_stop(tp); 6665 6666 netif_napi_del(&tp->napi); 6667 6668 unregister_netdev(dev); 6669 mdiobus_unregister(tp->phydev->mdio.bus); 6670 6671 rtl_release_firmware(tp); 6672 6673 if (pci_dev_run_wake(pdev)) 6674 pm_runtime_get_noresume(&pdev->dev); 6675 6676 /* restore original MAC address */ 6677 rtl_rar_set(tp, dev->perm_addr); 6678 } 6679 6680 static const struct net_device_ops rtl_netdev_ops = { 6681 .ndo_open = rtl_open, 6682 .ndo_stop = rtl8169_close, 6683 .ndo_get_stats64 = rtl8169_get_stats64, 6684 .ndo_start_xmit = rtl8169_start_xmit, 6685 .ndo_features_check = rtl8169_features_check, 6686 .ndo_tx_timeout = rtl8169_tx_timeout, 6687 .ndo_validate_addr = eth_validate_addr, 6688 .ndo_change_mtu = rtl8169_change_mtu, 6689 .ndo_fix_features = rtl8169_fix_features, 6690 .ndo_set_features = rtl8169_set_features, 6691 .ndo_set_mac_address = rtl_set_mac_address, 6692 .ndo_do_ioctl = rtl8169_ioctl, 6693 .ndo_set_rx_mode = rtl_set_rx_mode, 6694 #ifdef CONFIG_NET_POLL_CONTROLLER 6695 .ndo_poll_controller = rtl8169_netpoll, 6696 #endif 6697 6698 }; 6699 6700 static void rtl_set_irq_mask(struct rtl8169_private *tp) 6701 { 6702 tp->irq_mask = RTL_EVENT_NAPI | LinkChg; 6703 6704 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 6705 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 6706 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 6707 /* special workaround needed */ 6708 tp->irq_mask |= RxFIFOOver; 6709 else 6710 tp->irq_mask |= RxOverflow; 6711 } 6712 6713 static int rtl_alloc_irq(struct rtl8169_private *tp) 6714 { 6715 unsigned int flags; 6716 6717 switch (tp->mac_version) { 6718 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6719 rtl_unlock_config_regs(tp); 6720 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 6721 rtl_lock_config_regs(tp); 6722 /* fall through */ 6723 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24: 6724 flags = PCI_IRQ_LEGACY; 6725 break; 6726 default: 6727 flags = PCI_IRQ_ALL_TYPES; 6728 break; 6729 } 6730 6731 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 6732 } 6733 6734 static void rtl_read_mac_address(struct rtl8169_private *tp, 6735 u8 mac_addr[ETH_ALEN]) 6736 { 6737 /* Get MAC address */ 6738 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 6739 u32 value = rtl_eri_read(tp, 0xe0); 6740 6741 mac_addr[0] = (value >> 0) & 0xff; 6742 mac_addr[1] = (value >> 8) & 0xff; 6743 mac_addr[2] = (value >> 16) & 0xff; 6744 mac_addr[3] = (value >> 24) & 0xff; 6745 6746 value = rtl_eri_read(tp, 0xe4); 6747 mac_addr[4] = (value >> 0) & 0xff; 6748 mac_addr[5] = (value >> 8) & 0xff; 6749 } else if (rtl_is_8125(tp)) { 6750 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 6751 } 6752 } 6753 6754 DECLARE_RTL_COND(rtl_link_list_ready_cond) 6755 { 6756 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 6757 } 6758 6759 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 6760 { 6761 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 6762 } 6763 6764 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 6765 { 6766 struct rtl8169_private *tp = mii_bus->priv; 6767 6768 if (phyaddr > 0) 6769 return -ENODEV; 6770 6771 return rtl_readphy(tp, phyreg); 6772 } 6773 6774 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 6775 int phyreg, u16 val) 6776 { 6777 struct rtl8169_private *tp = mii_bus->priv; 6778 6779 if (phyaddr > 0) 6780 return -ENODEV; 6781 6782 rtl_writephy(tp, phyreg, val); 6783 6784 return 0; 6785 } 6786 6787 static int r8169_mdio_register(struct rtl8169_private *tp) 6788 { 6789 struct pci_dev *pdev = tp->pci_dev; 6790 struct mii_bus *new_bus; 6791 int ret; 6792 6793 new_bus = devm_mdiobus_alloc(&pdev->dev); 6794 if (!new_bus) 6795 return -ENOMEM; 6796 6797 new_bus->name = "r8169"; 6798 new_bus->priv = tp; 6799 new_bus->parent = &pdev->dev; 6800 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 6801 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 6802 6803 new_bus->read = r8169_mdio_read_reg; 6804 new_bus->write = r8169_mdio_write_reg; 6805 6806 ret = mdiobus_register(new_bus); 6807 if (ret) 6808 return ret; 6809 6810 tp->phydev = mdiobus_get_phy(new_bus, 0); 6811 if (!tp->phydev) { 6812 mdiobus_unregister(new_bus); 6813 return -ENODEV; 6814 } 6815 6816 /* PHY will be woken up in rtl_open() */ 6817 phy_suspend(tp->phydev); 6818 6819 return 0; 6820 } 6821 6822 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 6823 { 6824 tp->ocp_base = OCP_STD_PHY_BASE; 6825 6826 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6827 6828 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 6829 return; 6830 6831 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6832 return; 6833 6834 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6835 msleep(1); 6836 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6837 6838 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6839 6840 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6841 return; 6842 6843 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 6844 6845 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6846 } 6847 6848 static void rtl_hw_init_8125(struct rtl8169_private *tp) 6849 { 6850 tp->ocp_base = OCP_STD_PHY_BASE; 6851 6852 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6853 6854 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6855 return; 6856 6857 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6858 msleep(1); 6859 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6860 6861 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6862 6863 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6864 return; 6865 6866 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 6867 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 6868 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 6869 6870 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6871 } 6872 6873 static void rtl_hw_initialize(struct rtl8169_private *tp) 6874 { 6875 switch (tp->mac_version) { 6876 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51: 6877 rtl8168ep_stop_cmac(tp); 6878 /* fall through */ 6879 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 6880 rtl_hw_init_8168g(tp); 6881 break; 6882 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 6883 rtl_hw_init_8125(tp); 6884 break; 6885 default: 6886 break; 6887 } 6888 } 6889 6890 static int rtl_jumbo_max(struct rtl8169_private *tp) 6891 { 6892 /* Non-GBit versions don't support jumbo frames */ 6893 if (!tp->supports_gmii) 6894 return JUMBO_1K; 6895 6896 switch (tp->mac_version) { 6897 /* RTL8169 */ 6898 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6899 return JUMBO_7K; 6900 /* RTL8168b */ 6901 case RTL_GIGA_MAC_VER_11: 6902 case RTL_GIGA_MAC_VER_12: 6903 case RTL_GIGA_MAC_VER_17: 6904 return JUMBO_4K; 6905 /* RTL8168c */ 6906 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 6907 return JUMBO_6K; 6908 default: 6909 return JUMBO_9K; 6910 } 6911 } 6912 6913 static void rtl_disable_clk(void *data) 6914 { 6915 clk_disable_unprepare(data); 6916 } 6917 6918 static int rtl_get_ether_clk(struct rtl8169_private *tp) 6919 { 6920 struct device *d = tp_to_dev(tp); 6921 struct clk *clk; 6922 int rc; 6923 6924 clk = devm_clk_get(d, "ether_clk"); 6925 if (IS_ERR(clk)) { 6926 rc = PTR_ERR(clk); 6927 if (rc == -ENOENT) 6928 /* clk-core allows NULL (for suspend / resume) */ 6929 rc = 0; 6930 else if (rc != -EPROBE_DEFER) 6931 dev_err(d, "failed to get clk: %d\n", rc); 6932 } else { 6933 tp->clk = clk; 6934 rc = clk_prepare_enable(clk); 6935 if (rc) 6936 dev_err(d, "failed to enable clk: %d\n", rc); 6937 else 6938 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 6939 } 6940 6941 return rc; 6942 } 6943 6944 static void rtl_init_mac_address(struct rtl8169_private *tp) 6945 { 6946 struct net_device *dev = tp->dev; 6947 u8 *mac_addr = dev->dev_addr; 6948 int rc; 6949 6950 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 6951 if (!rc) 6952 goto done; 6953 6954 rtl_read_mac_address(tp, mac_addr); 6955 if (is_valid_ether_addr(mac_addr)) 6956 goto done; 6957 6958 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 6959 if (is_valid_ether_addr(mac_addr)) 6960 goto done; 6961 6962 eth_hw_addr_random(dev); 6963 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 6964 done: 6965 rtl_rar_set(tp, mac_addr); 6966 } 6967 6968 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 6969 { 6970 struct rtl8169_private *tp; 6971 struct net_device *dev; 6972 int chipset, region; 6973 int jumbo_max, rc; 6974 6975 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 6976 if (!dev) 6977 return -ENOMEM; 6978 6979 SET_NETDEV_DEV(dev, &pdev->dev); 6980 dev->netdev_ops = &rtl_netdev_ops; 6981 tp = netdev_priv(dev); 6982 tp->dev = dev; 6983 tp->pci_dev = pdev; 6984 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 6985 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 6986 6987 /* Get the *optional* external "ether_clk" used on some boards */ 6988 rc = rtl_get_ether_clk(tp); 6989 if (rc) 6990 return rc; 6991 6992 /* Disable ASPM completely as that cause random device stop working 6993 * problems as well as full system hangs for some PCIe devices users. 6994 */ 6995 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 6996 PCIE_LINK_STATE_L1); 6997 tp->aspm_manageable = !rc; 6998 6999 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 7000 rc = pcim_enable_device(pdev); 7001 if (rc < 0) { 7002 dev_err(&pdev->dev, "enable failure\n"); 7003 return rc; 7004 } 7005 7006 if (pcim_set_mwi(pdev) < 0) 7007 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 7008 7009 /* use first MMIO region */ 7010 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 7011 if (region < 0) { 7012 dev_err(&pdev->dev, "no MMIO resource found\n"); 7013 return -ENODEV; 7014 } 7015 7016 /* check for weird/broken PCI region reporting */ 7017 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 7018 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 7019 return -ENODEV; 7020 } 7021 7022 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 7023 if (rc < 0) { 7024 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 7025 return rc; 7026 } 7027 7028 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 7029 7030 /* Identify chip attached to board */ 7031 rtl8169_get_mac_version(tp); 7032 if (tp->mac_version == RTL_GIGA_MAC_NONE) 7033 return -ENODEV; 7034 7035 tp->cp_cmd = RTL_R16(tp, CPlusCmd); 7036 7037 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 7038 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 7039 dev->features |= NETIF_F_HIGHDMA; 7040 7041 rtl_init_rxcfg(tp); 7042 7043 rtl8169_irq_mask_and_ack(tp); 7044 7045 rtl_hw_initialize(tp); 7046 7047 rtl_hw_reset(tp); 7048 7049 pci_set_master(pdev); 7050 7051 chipset = tp->mac_version; 7052 7053 rc = rtl_alloc_irq(tp); 7054 if (rc < 0) { 7055 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 7056 return rc; 7057 } 7058 7059 mutex_init(&tp->wk.mutex); 7060 INIT_WORK(&tp->wk.work, rtl_task); 7061 u64_stats_init(&tp->rx_stats.syncp); 7062 u64_stats_init(&tp->tx_stats.syncp); 7063 7064 rtl_init_mac_address(tp); 7065 7066 dev->ethtool_ops = &rtl8169_ethtool_ops; 7067 7068 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 7069 7070 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7071 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 7072 NETIF_F_HW_VLAN_CTAG_RX; 7073 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7074 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 7075 NETIF_F_HW_VLAN_CTAG_RX; 7076 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 7077 NETIF_F_HIGHDMA; 7078 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 7079 7080 tp->cp_cmd |= RxChkSum; 7081 /* RTL8125 uses register RxConfig for VLAN offloading config */ 7082 if (!rtl_is_8125(tp)) 7083 tp->cp_cmd |= RxVlan; 7084 /* 7085 * Pretend we are using VLANs; This bypasses a nasty bug where 7086 * Interrupts stop flowing on high load on 8110SCd controllers. 7087 */ 7088 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 7089 /* Disallow toggling */ 7090 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 7091 7092 if (rtl_chip_supports_csum_v2(tp)) { 7093 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 7094 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 7095 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 7096 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 7097 } else { 7098 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 7099 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 7100 } 7101 7102 /* RTL8168e-vl has a HW issue with TSO */ 7103 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { 7104 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7105 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7106 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 7107 } 7108 7109 dev->hw_features |= NETIF_F_RXALL; 7110 dev->hw_features |= NETIF_F_RXFCS; 7111 7112 /* MTU range: 60 - hw-specific max */ 7113 dev->min_mtu = ETH_ZLEN; 7114 jumbo_max = rtl_jumbo_max(tp); 7115 dev->max_mtu = jumbo_max; 7116 7117 rtl_set_irq_mask(tp); 7118 7119 tp->fw_name = rtl_chip_infos[chipset].fw_name; 7120 7121 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 7122 &tp->counters_phys_addr, 7123 GFP_KERNEL); 7124 if (!tp->counters) 7125 return -ENOMEM; 7126 7127 pci_set_drvdata(pdev, dev); 7128 7129 rc = r8169_mdio_register(tp); 7130 if (rc) 7131 return rc; 7132 7133 /* chip gets powered up in rtl_open() */ 7134 rtl_pll_power_down(tp); 7135 7136 rc = register_netdev(dev); 7137 if (rc) 7138 goto err_mdio_unregister; 7139 7140 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n", 7141 rtl_chip_infos[chipset].name, dev->dev_addr, 7142 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf, 7143 pci_irq_vector(pdev, 0)); 7144 7145 if (jumbo_max > JUMBO_1K) 7146 netif_info(tp, probe, dev, 7147 "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 7148 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 7149 "ok" : "ko"); 7150 7151 if (r8168_check_dash(tp)) 7152 rtl8168_driver_start(tp); 7153 7154 if (pci_dev_run_wake(pdev)) 7155 pm_runtime_put_sync(&pdev->dev); 7156 7157 return 0; 7158 7159 err_mdio_unregister: 7160 mdiobus_unregister(tp->phydev->mdio.bus); 7161 return rc; 7162 } 7163 7164 static struct pci_driver rtl8169_pci_driver = { 7165 .name = MODULENAME, 7166 .id_table = rtl8169_pci_tbl, 7167 .probe = rtl_init_one, 7168 .remove = rtl_remove_one, 7169 .shutdown = rtl_shutdown, 7170 .driver.pm = RTL8169_PM_OPS, 7171 }; 7172 7173 module_pci_driver(rtl8169_pci_driver); 7174