1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define MODULENAME "r8169" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 56 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 59 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 60 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 61 62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 64 #define MC_FILTER_LIMIT 32 65 66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 68 69 #define R8169_REGS_SIZE 256 70 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 71 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 75 76 #define OCP_STD_PHY_BASE 0xa400 77 78 #define RTL_CFG_NO_GBIT 1 79 80 /* write/read MMIO register */ 81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 87 88 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 92 93 static const struct { 94 const char *name; 95 const char *fw_name; 96 } rtl_chip_infos[] = { 97 /* PCI devices. */ 98 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 99 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 100 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 101 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 102 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 103 /* PCI-E devices. */ 104 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 106 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 107 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 108 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 110 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 111 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 112 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 113 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 114 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 115 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 119 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 120 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 121 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 122 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 123 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 125 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 126 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 127 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 128 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 129 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 130 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 131 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 132 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 133 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 134 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 135 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 136 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 137 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 138 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 139 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 140 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 141 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 142 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 143 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 144 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 145 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 148 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 149 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 150 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" }, 151 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 152 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 153 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 154 }; 155 156 static const struct pci_device_id rtl8169_pci_tbl[] = { 157 { PCI_VDEVICE(REALTEK, 0x2502) }, 158 { PCI_VDEVICE(REALTEK, 0x2600) }, 159 { PCI_VDEVICE(REALTEK, 0x8129) }, 160 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 161 { PCI_VDEVICE(REALTEK, 0x8161) }, 162 { PCI_VDEVICE(REALTEK, 0x8167) }, 163 { PCI_VDEVICE(REALTEK, 0x8168) }, 164 { PCI_VDEVICE(NCUBE, 0x8168) }, 165 { PCI_VDEVICE(REALTEK, 0x8169) }, 166 { PCI_VENDOR_ID_DLINK, 0x4300, 167 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 168 { PCI_VDEVICE(DLINK, 0x4300) }, 169 { PCI_VDEVICE(DLINK, 0x4302) }, 170 { PCI_VDEVICE(AT, 0xc107) }, 171 { PCI_VDEVICE(USR, 0x0116) }, 172 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 173 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 174 { PCI_VDEVICE(REALTEK, 0x8125) }, 175 { PCI_VDEVICE(REALTEK, 0x3000) }, 176 {} 177 }; 178 179 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 180 181 enum rtl_registers { 182 MAC0 = 0, /* Ethernet hardware address. */ 183 MAC4 = 4, 184 MAR0 = 8, /* Multicast filter. */ 185 CounterAddrLow = 0x10, 186 CounterAddrHigh = 0x14, 187 TxDescStartAddrLow = 0x20, 188 TxDescStartAddrHigh = 0x24, 189 TxHDescStartAddrLow = 0x28, 190 TxHDescStartAddrHigh = 0x2c, 191 FLASH = 0x30, 192 ERSR = 0x36, 193 ChipCmd = 0x37, 194 TxPoll = 0x38, 195 IntrMask = 0x3c, 196 IntrStatus = 0x3e, 197 198 TxConfig = 0x40, 199 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 200 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 201 202 RxConfig = 0x44, 203 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 204 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 205 #define RXCFG_FIFO_SHIFT 13 206 /* No threshold before first PCI xfer */ 207 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 208 #define RX_EARLY_OFF (1 << 11) 209 #define RXCFG_DMA_SHIFT 8 210 /* Unlimited maximum PCI burst. */ 211 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 212 213 Cfg9346 = 0x50, 214 Config0 = 0x51, 215 Config1 = 0x52, 216 Config2 = 0x53, 217 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 218 219 Config3 = 0x54, 220 Config4 = 0x55, 221 Config5 = 0x56, 222 PHYAR = 0x60, 223 PHYstatus = 0x6c, 224 RxMaxSize = 0xda, 225 CPlusCmd = 0xe0, 226 IntrMitigate = 0xe2, 227 228 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 229 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 230 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 231 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 232 233 #define RTL_COALESCE_T_MAX 0x0fU 234 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 235 236 RxDescAddrLow = 0xe4, 237 RxDescAddrHigh = 0xe8, 238 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 239 240 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 241 242 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 243 244 #define TxPacketMax (8064 >> 7) 245 #define EarlySize 0x27 246 247 FuncEvent = 0xf0, 248 FuncEventMask = 0xf4, 249 FuncPresetState = 0xf8, 250 IBCR0 = 0xf8, 251 IBCR2 = 0xf9, 252 IBIMR0 = 0xfa, 253 IBISR0 = 0xfb, 254 FuncForceEvent = 0xfc, 255 }; 256 257 enum rtl8168_8101_registers { 258 CSIDR = 0x64, 259 CSIAR = 0x68, 260 #define CSIAR_FLAG 0x80000000 261 #define CSIAR_WRITE_CMD 0x80000000 262 #define CSIAR_BYTE_ENABLE 0x0000f000 263 #define CSIAR_ADDR_MASK 0x00000fff 264 PMCH = 0x6f, 265 #define D3COLD_NO_PLL_DOWN BIT(7) 266 #define D3HOT_NO_PLL_DOWN BIT(6) 267 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 268 EPHYAR = 0x80, 269 #define EPHYAR_FLAG 0x80000000 270 #define EPHYAR_WRITE_CMD 0x80000000 271 #define EPHYAR_REG_MASK 0x1f 272 #define EPHYAR_REG_SHIFT 16 273 #define EPHYAR_DATA_MASK 0xffff 274 DLLPR = 0xd0, 275 #define PFM_EN (1 << 6) 276 #define TX_10M_PS_EN (1 << 7) 277 DBG_REG = 0xd1, 278 #define FIX_NAK_1 (1 << 4) 279 #define FIX_NAK_2 (1 << 3) 280 TWSI = 0xd2, 281 MCU = 0xd3, 282 #define NOW_IS_OOB (1 << 7) 283 #define TX_EMPTY (1 << 5) 284 #define RX_EMPTY (1 << 4) 285 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 286 #define EN_NDP (1 << 3) 287 #define EN_OOB_RESET (1 << 2) 288 #define LINK_LIST_RDY (1 << 1) 289 EFUSEAR = 0xdc, 290 #define EFUSEAR_FLAG 0x80000000 291 #define EFUSEAR_WRITE_CMD 0x80000000 292 #define EFUSEAR_READ_CMD 0x00000000 293 #define EFUSEAR_REG_MASK 0x03ff 294 #define EFUSEAR_REG_SHIFT 8 295 #define EFUSEAR_DATA_MASK 0xff 296 MISC_1 = 0xf2, 297 #define PFM_D3COLD_EN (1 << 6) 298 }; 299 300 enum rtl8168_registers { 301 LED_FREQ = 0x1a, 302 EEE_LED = 0x1b, 303 ERIDR = 0x70, 304 ERIAR = 0x74, 305 #define ERIAR_FLAG 0x80000000 306 #define ERIAR_WRITE_CMD 0x80000000 307 #define ERIAR_READ_CMD 0x00000000 308 #define ERIAR_ADDR_BYTE_ALIGN 4 309 #define ERIAR_TYPE_SHIFT 16 310 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 311 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 312 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 313 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 314 #define ERIAR_MASK_SHIFT 12 315 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 316 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 317 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 318 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 319 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 320 EPHY_RXER_NUM = 0x7c, 321 OCPDR = 0xb0, /* OCP GPHY access */ 322 #define OCPDR_WRITE_CMD 0x80000000 323 #define OCPDR_READ_CMD 0x00000000 324 #define OCPDR_REG_MASK 0x7f 325 #define OCPDR_GPHY_REG_SHIFT 16 326 #define OCPDR_DATA_MASK 0xffff 327 OCPAR = 0xb4, 328 #define OCPAR_FLAG 0x80000000 329 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 330 #define OCPAR_GPHY_READ_CMD 0x0000f060 331 GPHY_OCP = 0xb8, 332 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 333 MISC = 0xf0, /* 8168e only. */ 334 #define TXPLA_RST (1 << 29) 335 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 336 #define PWM_EN (1 << 22) 337 #define RXDV_GATED_EN (1 << 19) 338 #define EARLY_TALLY_EN (1 << 16) 339 }; 340 341 enum rtl8125_registers { 342 IntrMask_8125 = 0x38, 343 IntrStatus_8125 = 0x3c, 344 TxPoll_8125 = 0x90, 345 MAC0_BKP = 0x19e0, 346 EEE_TXIDLE_TIMER_8125 = 0x6048, 347 }; 348 349 #define RX_VLAN_INNER_8125 BIT(22) 350 #define RX_VLAN_OUTER_8125 BIT(23) 351 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 352 353 #define RX_FETCH_DFLT_8125 (8 << 27) 354 355 enum rtl_register_content { 356 /* InterruptStatusBits */ 357 SYSErr = 0x8000, 358 PCSTimeout = 0x4000, 359 SWInt = 0x0100, 360 TxDescUnavail = 0x0080, 361 RxFIFOOver = 0x0040, 362 LinkChg = 0x0020, 363 RxOverflow = 0x0010, 364 TxErr = 0x0008, 365 TxOK = 0x0004, 366 RxErr = 0x0002, 367 RxOK = 0x0001, 368 369 /* RxStatusDesc */ 370 RxRWT = (1 << 22), 371 RxRES = (1 << 21), 372 RxRUNT = (1 << 20), 373 RxCRC = (1 << 19), 374 375 /* ChipCmdBits */ 376 StopReq = 0x80, 377 CmdReset = 0x10, 378 CmdRxEnb = 0x08, 379 CmdTxEnb = 0x04, 380 RxBufEmpty = 0x01, 381 382 /* TXPoll register p.5 */ 383 HPQ = 0x80, /* Poll cmd on the high prio queue */ 384 NPQ = 0x40, /* Poll cmd on the low prio queue */ 385 FSWInt = 0x01, /* Forced software interrupt */ 386 387 /* Cfg9346Bits */ 388 Cfg9346_Lock = 0x00, 389 Cfg9346_Unlock = 0xc0, 390 391 /* rx_mode_bits */ 392 AcceptErr = 0x20, 393 AcceptRunt = 0x10, 394 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 395 AcceptBroadcast = 0x08, 396 AcceptMulticast = 0x04, 397 AcceptMyPhys = 0x02, 398 AcceptAllPhys = 0x01, 399 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 400 #define RX_CONFIG_ACCEPT_MASK 0x3f 401 402 /* TxConfigBits */ 403 TxInterFrameGapShift = 24, 404 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 405 406 /* Config1 register p.24 */ 407 LEDS1 = (1 << 7), 408 LEDS0 = (1 << 6), 409 Speed_down = (1 << 4), 410 MEMMAP = (1 << 3), 411 IOMAP = (1 << 2), 412 VPD = (1 << 1), 413 PMEnable = (1 << 0), /* Power Management Enable */ 414 415 /* Config2 register p. 25 */ 416 ClkReqEn = (1 << 7), /* Clock Request Enable */ 417 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 418 PCI_Clock_66MHz = 0x01, 419 PCI_Clock_33MHz = 0x00, 420 421 /* Config3 register p.25 */ 422 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 423 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 424 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 425 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 426 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 427 428 /* Config4 register */ 429 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 430 431 /* Config5 register p.27 */ 432 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 433 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 434 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 435 Spi_en = (1 << 3), 436 LanWake = (1 << 1), /* LanWake enable/disable */ 437 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 438 ASPM_en = (1 << 0), /* ASPM enable */ 439 440 /* CPlusCmd p.31 */ 441 EnableBist = (1 << 15), // 8168 8101 442 Mac_dbgo_oe = (1 << 14), // 8168 8101 443 EnAnaPLL = (1 << 14), // 8169 444 Normal_mode = (1 << 13), // unused 445 Force_half_dup = (1 << 12), // 8168 8101 446 Force_rxflow_en = (1 << 11), // 8168 8101 447 Force_txflow_en = (1 << 10), // 8168 8101 448 Cxpl_dbg_sel = (1 << 9), // 8168 8101 449 ASF = (1 << 8), // 8168 8101 450 PktCntrDisable = (1 << 7), // 8168 8101 451 Mac_dbgo_sel = 0x001c, // 8168 452 RxVlan = (1 << 6), 453 RxChkSum = (1 << 5), 454 PCIDAC = (1 << 4), 455 PCIMulRW = (1 << 3), 456 #define INTT_MASK GENMASK(1, 0) 457 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 458 459 /* rtl8169_PHYstatus */ 460 TBI_Enable = 0x80, 461 TxFlowCtrl = 0x40, 462 RxFlowCtrl = 0x20, 463 _1000bpsF = 0x10, 464 _100bps = 0x08, 465 _10bps = 0x04, 466 LinkStatus = 0x02, 467 FullDup = 0x01, 468 469 /* ResetCounterCommand */ 470 CounterReset = 0x1, 471 472 /* DumpCounterCommand */ 473 CounterDump = 0x8, 474 475 /* magic enable v2 */ 476 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 477 }; 478 479 enum rtl_desc_bit { 480 /* First doubleword. */ 481 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 482 RingEnd = (1 << 30), /* End of descriptor ring */ 483 FirstFrag = (1 << 29), /* First segment of a packet */ 484 LastFrag = (1 << 28), /* Final segment of a packet */ 485 }; 486 487 /* Generic case. */ 488 enum rtl_tx_desc_bit { 489 /* First doubleword. */ 490 TD_LSO = (1 << 27), /* Large Send Offload */ 491 #define TD_MSS_MAX 0x07ffu /* MSS value */ 492 493 /* Second doubleword. */ 494 TxVlanTag = (1 << 17), /* Add VLAN tag */ 495 }; 496 497 /* 8169, 8168b and 810x except 8102e. */ 498 enum rtl_tx_desc_bit_0 { 499 /* First doubleword. */ 500 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 501 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 502 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 503 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 504 }; 505 506 /* 8102e, 8168c and beyond. */ 507 enum rtl_tx_desc_bit_1 { 508 /* First doubleword. */ 509 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 510 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 511 #define GTTCPHO_SHIFT 18 512 #define GTTCPHO_MAX 0x7f 513 514 /* Second doubleword. */ 515 #define TCPHO_SHIFT 18 516 #define TCPHO_MAX 0x3ff 517 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 518 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 519 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 520 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 521 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 522 }; 523 524 enum rtl_rx_desc_bit { 525 /* Rx private */ 526 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 527 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 528 529 #define RxProtoUDP (PID1) 530 #define RxProtoTCP (PID0) 531 #define RxProtoIP (PID1 | PID0) 532 #define RxProtoMask RxProtoIP 533 534 IPFail = (1 << 16), /* IP checksum failed */ 535 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 536 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 537 538 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 539 540 RxVlanTag = (1 << 16), /* VLAN tag available */ 541 }; 542 543 #define RTL_GSO_MAX_SIZE_V1 32000 544 #define RTL_GSO_MAX_SEGS_V1 24 545 #define RTL_GSO_MAX_SIZE_V2 64000 546 #define RTL_GSO_MAX_SEGS_V2 64 547 548 struct TxDesc { 549 __le32 opts1; 550 __le32 opts2; 551 __le64 addr; 552 }; 553 554 struct RxDesc { 555 __le32 opts1; 556 __le32 opts2; 557 __le64 addr; 558 }; 559 560 struct ring_info { 561 struct sk_buff *skb; 562 u32 len; 563 }; 564 565 struct rtl8169_counters { 566 __le64 tx_packets; 567 __le64 rx_packets; 568 __le64 tx_errors; 569 __le32 rx_errors; 570 __le16 rx_missed; 571 __le16 align_errors; 572 __le32 tx_one_collision; 573 __le32 tx_multi_collision; 574 __le64 rx_unicast; 575 __le64 rx_broadcast; 576 __le32 rx_multicast; 577 __le16 tx_aborted; 578 __le16 tx_underun; 579 }; 580 581 struct rtl8169_tc_offsets { 582 bool inited; 583 __le64 tx_errors; 584 __le32 tx_multi_collision; 585 __le16 tx_aborted; 586 __le16 rx_missed; 587 }; 588 589 enum rtl_flag { 590 RTL_FLAG_TASK_ENABLED = 0, 591 RTL_FLAG_TASK_RESET_PENDING, 592 RTL_FLAG_MAX 593 }; 594 595 enum rtl_dash_type { 596 RTL_DASH_NONE, 597 RTL_DASH_DP, 598 RTL_DASH_EP, 599 }; 600 601 struct rtl8169_private { 602 void __iomem *mmio_addr; /* memory map physical address */ 603 struct pci_dev *pci_dev; 604 struct net_device *dev; 605 struct phy_device *phydev; 606 struct napi_struct napi; 607 enum mac_version mac_version; 608 enum rtl_dash_type dash_type; 609 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 610 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 611 u32 dirty_tx; 612 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 613 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 614 dma_addr_t TxPhyAddr; 615 dma_addr_t RxPhyAddr; 616 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 617 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 618 u16 cp_cmd; 619 u32 irq_mask; 620 struct clk *clk; 621 622 struct { 623 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 624 struct work_struct work; 625 } wk; 626 627 unsigned supports_gmii:1; 628 unsigned aspm_manageable:1; 629 dma_addr_t counters_phys_addr; 630 struct rtl8169_counters *counters; 631 struct rtl8169_tc_offsets tc_offset; 632 u32 saved_wolopts; 633 int eee_adv; 634 635 const char *fw_name; 636 struct rtl_fw *rtl_fw; 637 638 u32 ocp_base; 639 }; 640 641 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 642 643 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 644 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 645 MODULE_SOFTDEP("pre: realtek"); 646 MODULE_LICENSE("GPL"); 647 MODULE_FIRMWARE(FIRMWARE_8168D_1); 648 MODULE_FIRMWARE(FIRMWARE_8168D_2); 649 MODULE_FIRMWARE(FIRMWARE_8168E_1); 650 MODULE_FIRMWARE(FIRMWARE_8168E_2); 651 MODULE_FIRMWARE(FIRMWARE_8168E_3); 652 MODULE_FIRMWARE(FIRMWARE_8105E_1); 653 MODULE_FIRMWARE(FIRMWARE_8168F_1); 654 MODULE_FIRMWARE(FIRMWARE_8168F_2); 655 MODULE_FIRMWARE(FIRMWARE_8402_1); 656 MODULE_FIRMWARE(FIRMWARE_8411_1); 657 MODULE_FIRMWARE(FIRMWARE_8411_2); 658 MODULE_FIRMWARE(FIRMWARE_8106E_1); 659 MODULE_FIRMWARE(FIRMWARE_8106E_2); 660 MODULE_FIRMWARE(FIRMWARE_8168G_2); 661 MODULE_FIRMWARE(FIRMWARE_8168G_3); 662 MODULE_FIRMWARE(FIRMWARE_8168H_1); 663 MODULE_FIRMWARE(FIRMWARE_8168H_2); 664 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 665 MODULE_FIRMWARE(FIRMWARE_8107E_1); 666 MODULE_FIRMWARE(FIRMWARE_8107E_2); 667 MODULE_FIRMWARE(FIRMWARE_8125A_3); 668 MODULE_FIRMWARE(FIRMWARE_8125B_2); 669 670 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 671 { 672 return &tp->pci_dev->dev; 673 } 674 675 static void rtl_lock_config_regs(struct rtl8169_private *tp) 676 { 677 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 678 } 679 680 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 681 { 682 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 683 } 684 685 static void rtl_pci_commit(struct rtl8169_private *tp) 686 { 687 /* Read an arbitrary register to commit a preceding PCI write */ 688 RTL_R8(tp, ChipCmd); 689 } 690 691 static bool rtl_is_8125(struct rtl8169_private *tp) 692 { 693 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 694 } 695 696 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 697 { 698 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 699 tp->mac_version != RTL_GIGA_MAC_VER_39 && 700 tp->mac_version <= RTL_GIGA_MAC_VER_53; 701 } 702 703 static bool rtl_supports_eee(struct rtl8169_private *tp) 704 { 705 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 706 tp->mac_version != RTL_GIGA_MAC_VER_37 && 707 tp->mac_version != RTL_GIGA_MAC_VER_39; 708 } 709 710 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 711 { 712 int i; 713 714 for (i = 0; i < ETH_ALEN; i++) 715 mac[i] = RTL_R8(tp, reg + i); 716 } 717 718 struct rtl_cond { 719 bool (*check)(struct rtl8169_private *); 720 const char *msg; 721 }; 722 723 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 724 unsigned long usecs, int n, bool high) 725 { 726 int i; 727 728 for (i = 0; i < n; i++) { 729 if (c->check(tp) == high) 730 return true; 731 fsleep(usecs); 732 } 733 734 if (net_ratelimit()) 735 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 736 c->msg, !high, n, usecs); 737 return false; 738 } 739 740 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 741 const struct rtl_cond *c, 742 unsigned long d, int n) 743 { 744 return rtl_loop_wait(tp, c, d, n, true); 745 } 746 747 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 748 const struct rtl_cond *c, 749 unsigned long d, int n) 750 { 751 return rtl_loop_wait(tp, c, d, n, false); 752 } 753 754 #define DECLARE_RTL_COND(name) \ 755 static bool name ## _check(struct rtl8169_private *); \ 756 \ 757 static const struct rtl_cond name = { \ 758 .check = name ## _check, \ 759 .msg = #name \ 760 }; \ 761 \ 762 static bool name ## _check(struct rtl8169_private *tp) 763 764 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 765 { 766 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 767 if (type == ERIAR_OOB && 768 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 769 tp->mac_version == RTL_GIGA_MAC_VER_53)) 770 *cmd |= 0xf70 << 18; 771 } 772 773 DECLARE_RTL_COND(rtl_eriar_cond) 774 { 775 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 776 } 777 778 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 779 u32 val, int type) 780 { 781 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 782 783 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 784 return; 785 786 RTL_W32(tp, ERIDR, val); 787 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 788 RTL_W32(tp, ERIAR, cmd); 789 790 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 791 } 792 793 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 794 u32 val) 795 { 796 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 797 } 798 799 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 800 { 801 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 802 803 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 804 RTL_W32(tp, ERIAR, cmd); 805 806 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 807 RTL_R32(tp, ERIDR) : ~0; 808 } 809 810 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 811 { 812 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 813 } 814 815 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 816 { 817 u32 val = rtl_eri_read(tp, addr); 818 819 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 820 } 821 822 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 823 { 824 rtl_w0w1_eri(tp, addr, p, 0); 825 } 826 827 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 828 { 829 rtl_w0w1_eri(tp, addr, 0, m); 830 } 831 832 static bool rtl_ocp_reg_failure(u32 reg) 833 { 834 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 835 } 836 837 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 838 { 839 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 840 } 841 842 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 843 { 844 if (rtl_ocp_reg_failure(reg)) 845 return; 846 847 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 848 849 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 850 } 851 852 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 853 { 854 if (rtl_ocp_reg_failure(reg)) 855 return 0; 856 857 RTL_W32(tp, GPHY_OCP, reg << 15); 858 859 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 860 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 861 } 862 863 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 864 { 865 if (rtl_ocp_reg_failure(reg)) 866 return; 867 868 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 869 } 870 871 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 872 { 873 if (rtl_ocp_reg_failure(reg)) 874 return 0; 875 876 RTL_W32(tp, OCPDR, reg << 15); 877 878 return RTL_R32(tp, OCPDR); 879 } 880 881 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 882 u16 set) 883 { 884 u16 data = r8168_mac_ocp_read(tp, reg); 885 886 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 887 } 888 889 /* Work around a hw issue with RTL8168g PHY, the quirk disables 890 * PHY MCU interrupts before PHY power-down. 891 */ 892 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 893 { 894 switch (tp->mac_version) { 895 case RTL_GIGA_MAC_VER_40: 896 case RTL_GIGA_MAC_VER_41: 897 case RTL_GIGA_MAC_VER_49: 898 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 899 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 900 else 901 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 902 break; 903 default: 904 break; 905 } 906 }; 907 908 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 909 { 910 if (reg == 0x1f) { 911 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 912 return; 913 } 914 915 if (tp->ocp_base != OCP_STD_PHY_BASE) 916 reg -= 0x10; 917 918 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 919 rtl8168g_phy_suspend_quirk(tp, value); 920 921 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 922 } 923 924 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 925 { 926 if (reg == 0x1f) 927 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 928 929 if (tp->ocp_base != OCP_STD_PHY_BASE) 930 reg -= 0x10; 931 932 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 933 } 934 935 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 936 { 937 if (reg == 0x1f) { 938 tp->ocp_base = value << 4; 939 return; 940 } 941 942 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 943 } 944 945 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 946 { 947 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 948 } 949 950 DECLARE_RTL_COND(rtl_phyar_cond) 951 { 952 return RTL_R32(tp, PHYAR) & 0x80000000; 953 } 954 955 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 956 { 957 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 958 959 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 960 /* 961 * According to hardware specs a 20us delay is required after write 962 * complete indication, but before sending next command. 963 */ 964 udelay(20); 965 } 966 967 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 968 { 969 int value; 970 971 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 972 973 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 974 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 975 976 /* 977 * According to hardware specs a 20us delay is required after read 978 * complete indication, but before sending next command. 979 */ 980 udelay(20); 981 982 return value; 983 } 984 985 DECLARE_RTL_COND(rtl_ocpar_cond) 986 { 987 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 988 } 989 990 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 991 { 992 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 993 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 994 RTL_W32(tp, EPHY_RXER_NUM, 0); 995 996 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 997 } 998 999 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 1000 { 1001 r8168dp_1_mdio_access(tp, reg, 1002 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 1003 } 1004 1005 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 1006 { 1007 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 1008 1009 mdelay(1); 1010 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 1011 RTL_W32(tp, EPHY_RXER_NUM, 0); 1012 1013 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 1014 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 1015 } 1016 1017 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1018 1019 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1020 { 1021 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1022 } 1023 1024 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1025 { 1026 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1027 } 1028 1029 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1030 { 1031 r8168dp_2_mdio_start(tp); 1032 1033 r8169_mdio_write(tp, reg, value); 1034 1035 r8168dp_2_mdio_stop(tp); 1036 } 1037 1038 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1039 { 1040 int value; 1041 1042 /* Work around issue with chip reporting wrong PHY ID */ 1043 if (reg == MII_PHYSID2) 1044 return 0xc912; 1045 1046 r8168dp_2_mdio_start(tp); 1047 1048 value = r8169_mdio_read(tp, reg); 1049 1050 r8168dp_2_mdio_stop(tp); 1051 1052 return value; 1053 } 1054 1055 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1056 { 1057 switch (tp->mac_version) { 1058 case RTL_GIGA_MAC_VER_27: 1059 r8168dp_1_mdio_write(tp, location, val); 1060 break; 1061 case RTL_GIGA_MAC_VER_28: 1062 case RTL_GIGA_MAC_VER_31: 1063 r8168dp_2_mdio_write(tp, location, val); 1064 break; 1065 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1066 r8168g_mdio_write(tp, location, val); 1067 break; 1068 default: 1069 r8169_mdio_write(tp, location, val); 1070 break; 1071 } 1072 } 1073 1074 static int rtl_readphy(struct rtl8169_private *tp, int location) 1075 { 1076 switch (tp->mac_version) { 1077 case RTL_GIGA_MAC_VER_27: 1078 return r8168dp_1_mdio_read(tp, location); 1079 case RTL_GIGA_MAC_VER_28: 1080 case RTL_GIGA_MAC_VER_31: 1081 return r8168dp_2_mdio_read(tp, location); 1082 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1083 return r8168g_mdio_read(tp, location); 1084 default: 1085 return r8169_mdio_read(tp, location); 1086 } 1087 } 1088 1089 DECLARE_RTL_COND(rtl_ephyar_cond) 1090 { 1091 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1092 } 1093 1094 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1095 { 1096 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1097 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1098 1099 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1100 1101 udelay(10); 1102 } 1103 1104 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1105 { 1106 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1107 1108 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1109 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1110 } 1111 1112 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1113 { 1114 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1115 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1116 RTL_R32(tp, OCPDR) : ~0; 1117 } 1118 1119 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1120 { 1121 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1122 } 1123 1124 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1125 u32 data) 1126 { 1127 RTL_W32(tp, OCPDR, data); 1128 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1129 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1130 } 1131 1132 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1133 u32 data) 1134 { 1135 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1136 data, ERIAR_OOB); 1137 } 1138 1139 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1140 { 1141 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1142 1143 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1144 } 1145 1146 #define OOB_CMD_RESET 0x00 1147 #define OOB_CMD_DRIVER_START 0x05 1148 #define OOB_CMD_DRIVER_STOP 0x06 1149 1150 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1151 { 1152 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1153 } 1154 1155 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1156 { 1157 u16 reg; 1158 1159 reg = rtl8168_get_ocp_reg(tp); 1160 1161 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1162 } 1163 1164 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1165 { 1166 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1167 } 1168 1169 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1170 { 1171 return RTL_R8(tp, IBISR0) & 0x20; 1172 } 1173 1174 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1175 { 1176 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1177 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1178 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1179 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1180 } 1181 1182 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1183 { 1184 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1185 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1186 } 1187 1188 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1189 { 1190 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1191 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1192 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1193 } 1194 1195 static void rtl8168_driver_start(struct rtl8169_private *tp) 1196 { 1197 if (tp->dash_type == RTL_DASH_DP) 1198 rtl8168dp_driver_start(tp); 1199 else 1200 rtl8168ep_driver_start(tp); 1201 } 1202 1203 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1204 { 1205 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1206 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1207 } 1208 1209 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1210 { 1211 rtl8168ep_stop_cmac(tp); 1212 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1213 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1214 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1215 } 1216 1217 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1218 { 1219 if (tp->dash_type == RTL_DASH_DP) 1220 rtl8168dp_driver_stop(tp); 1221 else 1222 rtl8168ep_driver_stop(tp); 1223 } 1224 1225 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1226 { 1227 u16 reg = rtl8168_get_ocp_reg(tp); 1228 1229 return r8168dp_ocp_read(tp, reg) & BIT(15); 1230 } 1231 1232 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1233 { 1234 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1235 } 1236 1237 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1238 { 1239 switch (tp->mac_version) { 1240 case RTL_GIGA_MAC_VER_27: 1241 case RTL_GIGA_MAC_VER_28: 1242 case RTL_GIGA_MAC_VER_31: 1243 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1244 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 1245 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1246 default: 1247 return RTL_DASH_NONE; 1248 } 1249 } 1250 1251 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1252 { 1253 switch (tp->mac_version) { 1254 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1255 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1256 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1257 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1258 if (enable) 1259 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1260 else 1261 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1262 break; 1263 default: 1264 break; 1265 } 1266 } 1267 1268 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1269 { 1270 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1271 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1272 } 1273 1274 DECLARE_RTL_COND(rtl_efusear_cond) 1275 { 1276 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1277 } 1278 1279 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1280 { 1281 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1282 1283 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1284 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1285 } 1286 1287 static u32 rtl_get_events(struct rtl8169_private *tp) 1288 { 1289 if (rtl_is_8125(tp)) 1290 return RTL_R32(tp, IntrStatus_8125); 1291 else 1292 return RTL_R16(tp, IntrStatus); 1293 } 1294 1295 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1296 { 1297 if (rtl_is_8125(tp)) 1298 RTL_W32(tp, IntrStatus_8125, bits); 1299 else 1300 RTL_W16(tp, IntrStatus, bits); 1301 } 1302 1303 static void rtl_irq_disable(struct rtl8169_private *tp) 1304 { 1305 if (rtl_is_8125(tp)) 1306 RTL_W32(tp, IntrMask_8125, 0); 1307 else 1308 RTL_W16(tp, IntrMask, 0); 1309 } 1310 1311 static void rtl_irq_enable(struct rtl8169_private *tp) 1312 { 1313 if (rtl_is_8125(tp)) 1314 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1315 else 1316 RTL_W16(tp, IntrMask, tp->irq_mask); 1317 } 1318 1319 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1320 { 1321 rtl_irq_disable(tp); 1322 rtl_ack_events(tp, 0xffffffff); 1323 rtl_pci_commit(tp); 1324 } 1325 1326 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1327 { 1328 struct phy_device *phydev = tp->phydev; 1329 1330 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1331 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1332 if (phydev->speed == SPEED_1000) { 1333 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1334 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1335 } else if (phydev->speed == SPEED_100) { 1336 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1337 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1338 } else { 1339 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1340 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1341 } 1342 rtl_reset_packet_filter(tp); 1343 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1344 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1345 if (phydev->speed == SPEED_1000) { 1346 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1347 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1348 } else { 1349 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1350 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1351 } 1352 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1353 if (phydev->speed == SPEED_10) { 1354 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1355 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1356 } else { 1357 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1358 } 1359 } 1360 } 1361 1362 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1363 1364 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1365 { 1366 struct rtl8169_private *tp = netdev_priv(dev); 1367 1368 wol->supported = WAKE_ANY; 1369 wol->wolopts = tp->saved_wolopts; 1370 } 1371 1372 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1373 { 1374 static const struct { 1375 u32 opt; 1376 u16 reg; 1377 u8 mask; 1378 } cfg[] = { 1379 { WAKE_PHY, Config3, LinkUp }, 1380 { WAKE_UCAST, Config5, UWF }, 1381 { WAKE_BCAST, Config5, BWF }, 1382 { WAKE_MCAST, Config5, MWF }, 1383 { WAKE_ANY, Config5, LanWake }, 1384 { WAKE_MAGIC, Config3, MagicPacket } 1385 }; 1386 unsigned int i, tmp = ARRAY_SIZE(cfg); 1387 u8 options; 1388 1389 rtl_unlock_config_regs(tp); 1390 1391 if (rtl_is_8168evl_up(tp)) { 1392 tmp--; 1393 if (wolopts & WAKE_MAGIC) 1394 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1395 else 1396 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1397 } else if (rtl_is_8125(tp)) { 1398 tmp--; 1399 if (wolopts & WAKE_MAGIC) 1400 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1401 else 1402 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1403 } 1404 1405 for (i = 0; i < tmp; i++) { 1406 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1407 if (wolopts & cfg[i].opt) 1408 options |= cfg[i].mask; 1409 RTL_W8(tp, cfg[i].reg, options); 1410 } 1411 1412 switch (tp->mac_version) { 1413 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1414 options = RTL_R8(tp, Config1) & ~PMEnable; 1415 if (wolopts) 1416 options |= PMEnable; 1417 RTL_W8(tp, Config1, options); 1418 break; 1419 case RTL_GIGA_MAC_VER_34: 1420 case RTL_GIGA_MAC_VER_37: 1421 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1422 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1423 if (wolopts) 1424 options |= PME_SIGNAL; 1425 RTL_W8(tp, Config2, options); 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 rtl_lock_config_regs(tp); 1432 1433 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1434 rtl_set_d3_pll_down(tp, !wolopts); 1435 tp->dev->wol_enabled = wolopts ? 1 : 0; 1436 } 1437 1438 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1439 { 1440 struct rtl8169_private *tp = netdev_priv(dev); 1441 1442 if (wol->wolopts & ~WAKE_ANY) 1443 return -EINVAL; 1444 1445 tp->saved_wolopts = wol->wolopts; 1446 __rtl8169_set_wol(tp, tp->saved_wolopts); 1447 1448 return 0; 1449 } 1450 1451 static void rtl8169_get_drvinfo(struct net_device *dev, 1452 struct ethtool_drvinfo *info) 1453 { 1454 struct rtl8169_private *tp = netdev_priv(dev); 1455 struct rtl_fw *rtl_fw = tp->rtl_fw; 1456 1457 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1458 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1459 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1460 if (rtl_fw) 1461 strlcpy(info->fw_version, rtl_fw->version, 1462 sizeof(info->fw_version)); 1463 } 1464 1465 static int rtl8169_get_regs_len(struct net_device *dev) 1466 { 1467 return R8169_REGS_SIZE; 1468 } 1469 1470 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1471 netdev_features_t features) 1472 { 1473 struct rtl8169_private *tp = netdev_priv(dev); 1474 1475 if (dev->mtu > TD_MSS_MAX) 1476 features &= ~NETIF_F_ALL_TSO; 1477 1478 if (dev->mtu > ETH_DATA_LEN && 1479 tp->mac_version > RTL_GIGA_MAC_VER_06) 1480 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1481 1482 return features; 1483 } 1484 1485 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1486 netdev_features_t features) 1487 { 1488 u32 rx_config = RTL_R32(tp, RxConfig); 1489 1490 if (features & NETIF_F_RXALL) 1491 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1492 else 1493 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1494 1495 if (rtl_is_8125(tp)) { 1496 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1497 rx_config |= RX_VLAN_8125; 1498 else 1499 rx_config &= ~RX_VLAN_8125; 1500 } 1501 1502 RTL_W32(tp, RxConfig, rx_config); 1503 } 1504 1505 static int rtl8169_set_features(struct net_device *dev, 1506 netdev_features_t features) 1507 { 1508 struct rtl8169_private *tp = netdev_priv(dev); 1509 1510 rtl_set_rx_config_features(tp, features); 1511 1512 if (features & NETIF_F_RXCSUM) 1513 tp->cp_cmd |= RxChkSum; 1514 else 1515 tp->cp_cmd &= ~RxChkSum; 1516 1517 if (!rtl_is_8125(tp)) { 1518 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1519 tp->cp_cmd |= RxVlan; 1520 else 1521 tp->cp_cmd &= ~RxVlan; 1522 } 1523 1524 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1525 rtl_pci_commit(tp); 1526 1527 return 0; 1528 } 1529 1530 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1531 { 1532 return (skb_vlan_tag_present(skb)) ? 1533 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1534 } 1535 1536 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1537 { 1538 u32 opts2 = le32_to_cpu(desc->opts2); 1539 1540 if (opts2 & RxVlanTag) 1541 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1542 } 1543 1544 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1545 void *p) 1546 { 1547 struct rtl8169_private *tp = netdev_priv(dev); 1548 u32 __iomem *data = tp->mmio_addr; 1549 u32 *dw = p; 1550 int i; 1551 1552 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1553 memcpy_fromio(dw++, data++, 4); 1554 } 1555 1556 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1557 "tx_packets", 1558 "rx_packets", 1559 "tx_errors", 1560 "rx_errors", 1561 "rx_missed", 1562 "align_errors", 1563 "tx_single_collisions", 1564 "tx_multi_collisions", 1565 "unicast", 1566 "broadcast", 1567 "multicast", 1568 "tx_aborted", 1569 "tx_underrun", 1570 }; 1571 1572 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1573 { 1574 switch (sset) { 1575 case ETH_SS_STATS: 1576 return ARRAY_SIZE(rtl8169_gstrings); 1577 default: 1578 return -EOPNOTSUPP; 1579 } 1580 } 1581 1582 DECLARE_RTL_COND(rtl_counters_cond) 1583 { 1584 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1585 } 1586 1587 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1588 { 1589 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1590 1591 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1592 rtl_pci_commit(tp); 1593 RTL_W32(tp, CounterAddrLow, cmd); 1594 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1595 1596 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1597 } 1598 1599 static void rtl8169_update_counters(struct rtl8169_private *tp) 1600 { 1601 u8 val = RTL_R8(tp, ChipCmd); 1602 1603 /* 1604 * Some chips are unable to dump tally counters when the receiver 1605 * is disabled. If 0xff chip may be in a PCI power-save state. 1606 */ 1607 if (val & CmdRxEnb && val != 0xff) 1608 rtl8169_do_counters(tp, CounterDump); 1609 } 1610 1611 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1612 { 1613 struct rtl8169_counters *counters = tp->counters; 1614 1615 /* 1616 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1617 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1618 * reset by a power cycle, while the counter values collected by the 1619 * driver are reset at every driver unload/load cycle. 1620 * 1621 * To make sure the HW values returned by @get_stats64 match the SW 1622 * values, we collect the initial values at first open(*) and use them 1623 * as offsets to normalize the values returned by @get_stats64. 1624 * 1625 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1626 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1627 * set at open time by rtl_hw_start. 1628 */ 1629 1630 if (tp->tc_offset.inited) 1631 return; 1632 1633 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1634 rtl8169_do_counters(tp, CounterReset); 1635 } else { 1636 rtl8169_update_counters(tp); 1637 tp->tc_offset.tx_errors = counters->tx_errors; 1638 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1639 tp->tc_offset.tx_aborted = counters->tx_aborted; 1640 tp->tc_offset.rx_missed = counters->rx_missed; 1641 } 1642 1643 tp->tc_offset.inited = true; 1644 } 1645 1646 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1647 struct ethtool_stats *stats, u64 *data) 1648 { 1649 struct rtl8169_private *tp = netdev_priv(dev); 1650 struct rtl8169_counters *counters; 1651 1652 counters = tp->counters; 1653 rtl8169_update_counters(tp); 1654 1655 data[0] = le64_to_cpu(counters->tx_packets); 1656 data[1] = le64_to_cpu(counters->rx_packets); 1657 data[2] = le64_to_cpu(counters->tx_errors); 1658 data[3] = le32_to_cpu(counters->rx_errors); 1659 data[4] = le16_to_cpu(counters->rx_missed); 1660 data[5] = le16_to_cpu(counters->align_errors); 1661 data[6] = le32_to_cpu(counters->tx_one_collision); 1662 data[7] = le32_to_cpu(counters->tx_multi_collision); 1663 data[8] = le64_to_cpu(counters->rx_unicast); 1664 data[9] = le64_to_cpu(counters->rx_broadcast); 1665 data[10] = le32_to_cpu(counters->rx_multicast); 1666 data[11] = le16_to_cpu(counters->tx_aborted); 1667 data[12] = le16_to_cpu(counters->tx_underun); 1668 } 1669 1670 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1671 { 1672 switch(stringset) { 1673 case ETH_SS_STATS: 1674 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1675 break; 1676 } 1677 } 1678 1679 /* 1680 * Interrupt coalescing 1681 * 1682 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1683 * > 8169, 8168 and 810x line of chipsets 1684 * 1685 * 8169, 8168, and 8136(810x) serial chipsets support it. 1686 * 1687 * > 2 - the Tx timer unit at gigabit speed 1688 * 1689 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1690 * (0xe0) bit 1 and bit 0. 1691 * 1692 * For 8169 1693 * bit[1:0] \ speed 1000M 100M 10M 1694 * 0 0 320ns 2.56us 40.96us 1695 * 0 1 2.56us 20.48us 327.7us 1696 * 1 0 5.12us 40.96us 655.4us 1697 * 1 1 10.24us 81.92us 1.31ms 1698 * 1699 * For the other 1700 * bit[1:0] \ speed 1000M 100M 10M 1701 * 0 0 5us 2.56us 40.96us 1702 * 0 1 40us 20.48us 327.7us 1703 * 1 0 80us 40.96us 655.4us 1704 * 1 1 160us 81.92us 1.31ms 1705 */ 1706 1707 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1708 struct rtl_coalesce_info { 1709 u32 speed; 1710 u32 scale_nsecs[4]; 1711 }; 1712 1713 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1714 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1715 1716 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1717 { SPEED_1000, COALESCE_DELAY(320) }, 1718 { SPEED_100, COALESCE_DELAY(2560) }, 1719 { SPEED_10, COALESCE_DELAY(40960) }, 1720 { 0 }, 1721 }; 1722 1723 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1724 { SPEED_1000, COALESCE_DELAY(5000) }, 1725 { SPEED_100, COALESCE_DELAY(2560) }, 1726 { SPEED_10, COALESCE_DELAY(40960) }, 1727 { 0 }, 1728 }; 1729 #undef COALESCE_DELAY 1730 1731 /* get rx/tx scale vector corresponding to current speed */ 1732 static const struct rtl_coalesce_info * 1733 rtl_coalesce_info(struct rtl8169_private *tp) 1734 { 1735 const struct rtl_coalesce_info *ci; 1736 1737 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1738 ci = rtl_coalesce_info_8169; 1739 else 1740 ci = rtl_coalesce_info_8168_8136; 1741 1742 /* if speed is unknown assume highest one */ 1743 if (tp->phydev->speed == SPEED_UNKNOWN) 1744 return ci; 1745 1746 for (; ci->speed; ci++) { 1747 if (tp->phydev->speed == ci->speed) 1748 return ci; 1749 } 1750 1751 return ERR_PTR(-ELNRNG); 1752 } 1753 1754 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1755 { 1756 struct rtl8169_private *tp = netdev_priv(dev); 1757 const struct rtl_coalesce_info *ci; 1758 u32 scale, c_us, c_fr; 1759 u16 intrmit; 1760 1761 if (rtl_is_8125(tp)) 1762 return -EOPNOTSUPP; 1763 1764 memset(ec, 0, sizeof(*ec)); 1765 1766 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1767 ci = rtl_coalesce_info(tp); 1768 if (IS_ERR(ci)) 1769 return PTR_ERR(ci); 1770 1771 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1772 1773 intrmit = RTL_R16(tp, IntrMitigate); 1774 1775 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1776 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1777 1778 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1779 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1780 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1781 1782 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1783 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1784 1785 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1786 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1787 1788 return 0; 1789 } 1790 1791 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1792 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1793 u16 *cp01) 1794 { 1795 const struct rtl_coalesce_info *ci; 1796 u16 i; 1797 1798 ci = rtl_coalesce_info(tp); 1799 if (IS_ERR(ci)) 1800 return PTR_ERR(ci); 1801 1802 for (i = 0; i < 4; i++) { 1803 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1804 *cp01 = i; 1805 return ci->scale_nsecs[i]; 1806 } 1807 } 1808 1809 return -ERANGE; 1810 } 1811 1812 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1813 { 1814 struct rtl8169_private *tp = netdev_priv(dev); 1815 u32 tx_fr = ec->tx_max_coalesced_frames; 1816 u32 rx_fr = ec->rx_max_coalesced_frames; 1817 u32 coal_usec_max, units; 1818 u16 w = 0, cp01 = 0; 1819 int scale; 1820 1821 if (rtl_is_8125(tp)) 1822 return -EOPNOTSUPP; 1823 1824 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1825 return -ERANGE; 1826 1827 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1828 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1829 if (scale < 0) 1830 return scale; 1831 1832 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1833 * not only when usecs=0 because of e.g. the following scenario: 1834 * 1835 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1836 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1837 * - then user does `ethtool -C eth0 rx-usecs 100` 1838 * 1839 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1840 * if we want to ignore rx_frames then it has to be set to 0. 1841 */ 1842 if (rx_fr == 1) 1843 rx_fr = 0; 1844 if (tx_fr == 1) 1845 tx_fr = 0; 1846 1847 /* HW requires time limit to be set if frame limit is set */ 1848 if ((tx_fr && !ec->tx_coalesce_usecs) || 1849 (rx_fr && !ec->rx_coalesce_usecs)) 1850 return -EINVAL; 1851 1852 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1853 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1854 1855 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1856 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1857 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1858 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1859 1860 RTL_W16(tp, IntrMitigate, w); 1861 1862 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1863 if (rtl_is_8168evl_up(tp)) { 1864 if (!rx_fr && !tx_fr) 1865 /* disable packet counter */ 1866 tp->cp_cmd |= PktCntrDisable; 1867 else 1868 tp->cp_cmd &= ~PktCntrDisable; 1869 } 1870 1871 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1872 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1873 rtl_pci_commit(tp); 1874 1875 return 0; 1876 } 1877 1878 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1879 { 1880 struct rtl8169_private *tp = netdev_priv(dev); 1881 1882 if (!rtl_supports_eee(tp)) 1883 return -EOPNOTSUPP; 1884 1885 return phy_ethtool_get_eee(tp->phydev, data); 1886 } 1887 1888 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1889 { 1890 struct rtl8169_private *tp = netdev_priv(dev); 1891 int ret; 1892 1893 if (!rtl_supports_eee(tp)) 1894 return -EOPNOTSUPP; 1895 1896 ret = phy_ethtool_set_eee(tp->phydev, data); 1897 1898 if (!ret) 1899 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1900 MDIO_AN_EEE_ADV); 1901 return ret; 1902 } 1903 1904 static void rtl8169_get_ringparam(struct net_device *dev, 1905 struct ethtool_ringparam *data) 1906 { 1907 data->rx_max_pending = NUM_RX_DESC; 1908 data->rx_pending = NUM_RX_DESC; 1909 data->tx_max_pending = NUM_TX_DESC; 1910 data->tx_pending = NUM_TX_DESC; 1911 } 1912 1913 static void rtl8169_get_pauseparam(struct net_device *dev, 1914 struct ethtool_pauseparam *data) 1915 { 1916 struct rtl8169_private *tp = netdev_priv(dev); 1917 bool tx_pause, rx_pause; 1918 1919 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1920 1921 data->autoneg = tp->phydev->autoneg; 1922 data->tx_pause = tx_pause ? 1 : 0; 1923 data->rx_pause = rx_pause ? 1 : 0; 1924 } 1925 1926 static int rtl8169_set_pauseparam(struct net_device *dev, 1927 struct ethtool_pauseparam *data) 1928 { 1929 struct rtl8169_private *tp = netdev_priv(dev); 1930 1931 if (dev->mtu > ETH_DATA_LEN) 1932 return -EOPNOTSUPP; 1933 1934 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1935 1936 return 0; 1937 } 1938 1939 static const struct ethtool_ops rtl8169_ethtool_ops = { 1940 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1941 ETHTOOL_COALESCE_MAX_FRAMES, 1942 .get_drvinfo = rtl8169_get_drvinfo, 1943 .get_regs_len = rtl8169_get_regs_len, 1944 .get_link = ethtool_op_get_link, 1945 .get_coalesce = rtl_get_coalesce, 1946 .set_coalesce = rtl_set_coalesce, 1947 .get_regs = rtl8169_get_regs, 1948 .get_wol = rtl8169_get_wol, 1949 .set_wol = rtl8169_set_wol, 1950 .get_strings = rtl8169_get_strings, 1951 .get_sset_count = rtl8169_get_sset_count, 1952 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1953 .get_ts_info = ethtool_op_get_ts_info, 1954 .nway_reset = phy_ethtool_nway_reset, 1955 .get_eee = rtl8169_get_eee, 1956 .set_eee = rtl8169_set_eee, 1957 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1958 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1959 .get_ringparam = rtl8169_get_ringparam, 1960 .get_pauseparam = rtl8169_get_pauseparam, 1961 .set_pauseparam = rtl8169_set_pauseparam, 1962 }; 1963 1964 static void rtl_enable_eee(struct rtl8169_private *tp) 1965 { 1966 struct phy_device *phydev = tp->phydev; 1967 int adv; 1968 1969 /* respect EEE advertisement the user may have set */ 1970 if (tp->eee_adv >= 0) 1971 adv = tp->eee_adv; 1972 else 1973 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1974 1975 if (adv >= 0) 1976 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1977 } 1978 1979 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1980 { 1981 /* 1982 * The driver currently handles the 8168Bf and the 8168Be identically 1983 * but they can be identified more specifically through the test below 1984 * if needed: 1985 * 1986 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1987 * 1988 * Same thing for the 8101Eb and the 8101Ec: 1989 * 1990 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1991 */ 1992 static const struct rtl_mac_info { 1993 u16 mask; 1994 u16 val; 1995 enum mac_version ver; 1996 } mac_info[] = { 1997 /* 8125B family. */ 1998 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1999 2000 /* 8125A family. */ 2001 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2002 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2003 2004 /* RTL8117 */ 2005 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2006 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2007 2008 /* 8168EP family. */ 2009 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2010 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2011 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2012 2013 /* 8168H family. */ 2014 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2015 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2016 2017 /* 8168G family. */ 2018 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2019 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2020 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2021 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2022 2023 /* 8168F family. */ 2024 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2025 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2026 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2027 2028 /* 8168E family. */ 2029 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2030 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2031 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2032 2033 /* 8168D family. */ 2034 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2035 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2036 2037 /* 8168DP family. */ 2038 /* It seems this early RTL8168dp version never made it to 2039 * the wild. Let's see whether somebody complains, if not 2040 * we'll remove support for this chip version completely. 2041 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2042 */ 2043 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2044 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2045 2046 /* 8168C family. */ 2047 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2048 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2049 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2050 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2051 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2052 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2053 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2054 2055 /* 8168B family. */ 2056 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2057 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2058 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2059 2060 /* 8101 family. */ 2061 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2062 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2063 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2064 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2065 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2066 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2067 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2068 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2069 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2070 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2071 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2072 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2073 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2074 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2075 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2076 /* FIXME: where did these entries come from ? -- FR 2077 * Not even r8101 vendor driver knows these id's, 2078 * so let's disable detection for now. -- HK 2079 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 }, 2080 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 }, 2081 */ 2082 2083 /* 8110 family. */ 2084 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2085 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2086 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2087 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2088 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2089 2090 /* Catch-all */ 2091 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2092 }; 2093 const struct rtl_mac_info *p = mac_info; 2094 enum mac_version ver; 2095 2096 while ((xid & p->mask) != p->val) 2097 p++; 2098 ver = p->ver; 2099 2100 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2101 if (ver == RTL_GIGA_MAC_VER_42) 2102 ver = RTL_GIGA_MAC_VER_43; 2103 else if (ver == RTL_GIGA_MAC_VER_45) 2104 ver = RTL_GIGA_MAC_VER_47; 2105 else if (ver == RTL_GIGA_MAC_VER_46) 2106 ver = RTL_GIGA_MAC_VER_48; 2107 } 2108 2109 return ver; 2110 } 2111 2112 static void rtl_release_firmware(struct rtl8169_private *tp) 2113 { 2114 if (tp->rtl_fw) { 2115 rtl_fw_release_firmware(tp->rtl_fw); 2116 kfree(tp->rtl_fw); 2117 tp->rtl_fw = NULL; 2118 } 2119 } 2120 2121 void r8169_apply_firmware(struct rtl8169_private *tp) 2122 { 2123 int val; 2124 2125 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2126 if (tp->rtl_fw) { 2127 rtl_fw_write_firmware(tp, tp->rtl_fw); 2128 /* At least one firmware doesn't reset tp->ocp_base. */ 2129 tp->ocp_base = OCP_STD_PHY_BASE; 2130 2131 /* PHY soft reset may still be in progress */ 2132 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2133 !(val & BMCR_RESET), 2134 50000, 600000, true); 2135 } 2136 } 2137 2138 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2139 { 2140 /* Adjust EEE LED frequency */ 2141 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2142 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2143 2144 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2145 } 2146 2147 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2148 { 2149 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2150 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2151 } 2152 2153 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2154 { 2155 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2156 } 2157 2158 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2159 { 2160 rtl8125_set_eee_txidle_timer(tp); 2161 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2162 } 2163 2164 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2165 { 2166 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2167 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2168 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2169 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2170 } 2171 2172 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2173 { 2174 u16 data1, data2, ioffset; 2175 2176 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2177 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2178 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2179 2180 ioffset = (data2 >> 1) & 0x7ff8; 2181 ioffset |= data2 & 0x0007; 2182 if (data1 & BIT(7)) 2183 ioffset |= BIT(15); 2184 2185 return ioffset; 2186 } 2187 2188 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2189 { 2190 set_bit(flag, tp->wk.flags); 2191 schedule_work(&tp->wk.work); 2192 } 2193 2194 static void rtl8169_init_phy(struct rtl8169_private *tp) 2195 { 2196 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2197 2198 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2199 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2200 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2201 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2202 RTL_W8(tp, 0x82, 0x01); 2203 } 2204 2205 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2206 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2207 tp->pci_dev->subsystem_device == 0xe000) 2208 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2209 2210 /* We may have called phy_speed_down before */ 2211 phy_speed_up(tp->phydev); 2212 2213 if (rtl_supports_eee(tp)) 2214 rtl_enable_eee(tp); 2215 2216 genphy_soft_reset(tp->phydev); 2217 } 2218 2219 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2220 { 2221 rtl_unlock_config_regs(tp); 2222 2223 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2224 rtl_pci_commit(tp); 2225 2226 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2227 rtl_pci_commit(tp); 2228 2229 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2230 rtl_rar_exgmac_set(tp, addr); 2231 2232 rtl_lock_config_regs(tp); 2233 } 2234 2235 static int rtl_set_mac_address(struct net_device *dev, void *p) 2236 { 2237 struct rtl8169_private *tp = netdev_priv(dev); 2238 int ret; 2239 2240 ret = eth_mac_addr(dev, p); 2241 if (ret) 2242 return ret; 2243 2244 rtl_rar_set(tp, dev->dev_addr); 2245 2246 return 0; 2247 } 2248 2249 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2250 { 2251 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2252 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2253 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2254 } 2255 2256 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2257 { 2258 if (tp->dash_type != RTL_DASH_NONE) 2259 return; 2260 2261 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2262 tp->mac_version == RTL_GIGA_MAC_VER_33) 2263 rtl_ephy_write(tp, 0x19, 0xff64); 2264 2265 if (device_may_wakeup(tp_to_dev(tp))) { 2266 phy_speed_down(tp->phydev, false); 2267 rtl_wol_enable_rx(tp); 2268 } 2269 } 2270 2271 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2272 { 2273 switch (tp->mac_version) { 2274 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2275 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2276 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2277 break; 2278 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2279 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2280 case RTL_GIGA_MAC_VER_38: 2281 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2282 break; 2283 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2284 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2285 break; 2286 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 2287 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2288 break; 2289 default: 2290 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2291 break; 2292 } 2293 } 2294 2295 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2296 { 2297 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2298 } 2299 2300 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2301 { 2302 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2303 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2304 } 2305 2306 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2307 { 2308 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2309 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2310 } 2311 2312 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2313 { 2314 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2315 } 2316 2317 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2318 { 2319 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2320 } 2321 2322 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2323 { 2324 RTL_W8(tp, MaxTxPacketSize, 0x24); 2325 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2326 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2327 } 2328 2329 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2330 { 2331 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2332 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2333 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2334 } 2335 2336 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2337 { 2338 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2339 } 2340 2341 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2342 { 2343 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2344 } 2345 2346 static void rtl_jumbo_config(struct rtl8169_private *tp) 2347 { 2348 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2349 int readrq = 4096; 2350 2351 rtl_unlock_config_regs(tp); 2352 switch (tp->mac_version) { 2353 case RTL_GIGA_MAC_VER_12: 2354 case RTL_GIGA_MAC_VER_17: 2355 if (jumbo) { 2356 readrq = 512; 2357 r8168b_1_hw_jumbo_enable(tp); 2358 } else { 2359 r8168b_1_hw_jumbo_disable(tp); 2360 } 2361 break; 2362 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2363 if (jumbo) { 2364 readrq = 512; 2365 r8168c_hw_jumbo_enable(tp); 2366 } else { 2367 r8168c_hw_jumbo_disable(tp); 2368 } 2369 break; 2370 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2371 if (jumbo) 2372 r8168dp_hw_jumbo_enable(tp); 2373 else 2374 r8168dp_hw_jumbo_disable(tp); 2375 break; 2376 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2377 if (jumbo) 2378 r8168e_hw_jumbo_enable(tp); 2379 else 2380 r8168e_hw_jumbo_disable(tp); 2381 break; 2382 default: 2383 break; 2384 } 2385 rtl_lock_config_regs(tp); 2386 2387 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2388 pcie_set_readrq(tp->pci_dev, readrq); 2389 2390 /* Chip doesn't support pause in jumbo mode */ 2391 if (jumbo) { 2392 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2393 tp->phydev->advertising); 2394 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2395 tp->phydev->advertising); 2396 phy_start_aneg(tp->phydev); 2397 } 2398 } 2399 2400 DECLARE_RTL_COND(rtl_chipcmd_cond) 2401 { 2402 return RTL_R8(tp, ChipCmd) & CmdReset; 2403 } 2404 2405 static void rtl_hw_reset(struct rtl8169_private *tp) 2406 { 2407 RTL_W8(tp, ChipCmd, CmdReset); 2408 2409 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2410 } 2411 2412 static void rtl_request_firmware(struct rtl8169_private *tp) 2413 { 2414 struct rtl_fw *rtl_fw; 2415 2416 /* firmware loaded already or no firmware available */ 2417 if (tp->rtl_fw || !tp->fw_name) 2418 return; 2419 2420 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2421 if (!rtl_fw) 2422 return; 2423 2424 rtl_fw->phy_write = rtl_writephy; 2425 rtl_fw->phy_read = rtl_readphy; 2426 rtl_fw->mac_mcu_write = mac_mcu_write; 2427 rtl_fw->mac_mcu_read = mac_mcu_read; 2428 rtl_fw->fw_name = tp->fw_name; 2429 rtl_fw->dev = tp_to_dev(tp); 2430 2431 if (rtl_fw_request_firmware(rtl_fw)) 2432 kfree(rtl_fw); 2433 else 2434 tp->rtl_fw = rtl_fw; 2435 } 2436 2437 static void rtl_rx_close(struct rtl8169_private *tp) 2438 { 2439 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2440 } 2441 2442 DECLARE_RTL_COND(rtl_npq_cond) 2443 { 2444 return RTL_R8(tp, TxPoll) & NPQ; 2445 } 2446 2447 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2448 { 2449 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2450 } 2451 2452 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2453 { 2454 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2455 } 2456 2457 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2458 { 2459 /* IntrMitigate has new functionality on RTL8125 */ 2460 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2461 } 2462 2463 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2464 { 2465 switch (tp->mac_version) { 2466 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2467 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2468 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2469 break; 2470 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2471 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2472 break; 2473 case RTL_GIGA_MAC_VER_63: 2474 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2475 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2476 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2477 break; 2478 default: 2479 break; 2480 } 2481 } 2482 2483 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2484 { 2485 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2486 fsleep(2000); 2487 rtl_wait_txrx_fifo_empty(tp); 2488 } 2489 2490 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2491 { 2492 u32 val = TX_DMA_BURST << TxDMAShift | 2493 InterFrameGap << TxInterFrameGapShift; 2494 2495 if (rtl_is_8168evl_up(tp)) 2496 val |= TXCFG_AUTO_FIFO; 2497 2498 RTL_W32(tp, TxConfig, val); 2499 } 2500 2501 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2502 { 2503 /* Low hurts. Let's disable the filtering. */ 2504 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2505 } 2506 2507 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2508 { 2509 /* 2510 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2511 * register to be written before TxDescAddrLow to work. 2512 * Switching from MMIO to I/O access fixes the issue as well. 2513 */ 2514 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2515 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2516 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2517 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2518 } 2519 2520 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2521 { 2522 u32 val; 2523 2524 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2525 val = 0x000fff00; 2526 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2527 val = 0x00ffff00; 2528 else 2529 return; 2530 2531 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2532 val |= 0xff; 2533 2534 RTL_W32(tp, 0x7c, val); 2535 } 2536 2537 static void rtl_set_rx_mode(struct net_device *dev) 2538 { 2539 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2540 /* Multicast hash filter */ 2541 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2542 struct rtl8169_private *tp = netdev_priv(dev); 2543 u32 tmp; 2544 2545 if (dev->flags & IFF_PROMISC) { 2546 rx_mode |= AcceptAllPhys; 2547 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2548 dev->flags & IFF_ALLMULTI || 2549 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2550 /* accept all multicasts */ 2551 } else if (netdev_mc_empty(dev)) { 2552 rx_mode &= ~AcceptMulticast; 2553 } else { 2554 struct netdev_hw_addr *ha; 2555 2556 mc_filter[1] = mc_filter[0] = 0; 2557 netdev_for_each_mc_addr(ha, dev) { 2558 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2559 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2560 } 2561 2562 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2563 tmp = mc_filter[0]; 2564 mc_filter[0] = swab32(mc_filter[1]); 2565 mc_filter[1] = swab32(tmp); 2566 } 2567 } 2568 2569 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2570 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2571 2572 tmp = RTL_R32(tp, RxConfig); 2573 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2574 } 2575 2576 DECLARE_RTL_COND(rtl_csiar_cond) 2577 { 2578 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2579 } 2580 2581 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2582 { 2583 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2584 2585 RTL_W32(tp, CSIDR, value); 2586 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2587 CSIAR_BYTE_ENABLE | func << 16); 2588 2589 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2590 } 2591 2592 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2593 { 2594 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2595 2596 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2597 CSIAR_BYTE_ENABLE); 2598 2599 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2600 RTL_R32(tp, CSIDR) : ~0; 2601 } 2602 2603 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2604 { 2605 struct pci_dev *pdev = tp->pci_dev; 2606 u32 csi; 2607 2608 /* According to Realtek the value at config space address 0x070f 2609 * controls the L0s/L1 entrance latency. We try standard ECAM access 2610 * first and if it fails fall back to CSI. 2611 */ 2612 if (pdev->cfg_size > 0x070f && 2613 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2614 return; 2615 2616 netdev_notice_once(tp->dev, 2617 "No native access to PCI extended config space, falling back to CSI\n"); 2618 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2619 rtl_csi_write(tp, 0x070c, csi | val << 24); 2620 } 2621 2622 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2623 { 2624 rtl_csi_access_enable(tp, 0x27); 2625 } 2626 2627 struct ephy_info { 2628 unsigned int offset; 2629 u16 mask; 2630 u16 bits; 2631 }; 2632 2633 static void __rtl_ephy_init(struct rtl8169_private *tp, 2634 const struct ephy_info *e, int len) 2635 { 2636 u16 w; 2637 2638 while (len-- > 0) { 2639 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2640 rtl_ephy_write(tp, e->offset, w); 2641 e++; 2642 } 2643 } 2644 2645 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2646 2647 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2648 { 2649 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2650 PCI_EXP_LNKCTL_CLKREQ_EN); 2651 } 2652 2653 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2654 { 2655 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2656 PCI_EXP_LNKCTL_CLKREQ_EN); 2657 } 2658 2659 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2660 { 2661 /* work around an issue when PCI reset occurs during L2/L3 state */ 2662 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2663 } 2664 2665 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2666 { 2667 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2668 if (enable && tp->aspm_manageable) { 2669 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2670 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2671 } else { 2672 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2673 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2674 } 2675 2676 udelay(10); 2677 } 2678 2679 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2680 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2681 { 2682 /* Usage of dynamic vs. static FIFO is controlled by bit 2683 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2684 */ 2685 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2686 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2687 } 2688 2689 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2690 u8 low, u8 high) 2691 { 2692 /* FIFO thresholds for pause flow control */ 2693 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2694 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2695 } 2696 2697 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2698 { 2699 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2700 } 2701 2702 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2703 { 2704 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2705 2706 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2707 2708 rtl_disable_clock_request(tp); 2709 } 2710 2711 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2712 { 2713 static const struct ephy_info e_info_8168cp[] = { 2714 { 0x01, 0, 0x0001 }, 2715 { 0x02, 0x0800, 0x1000 }, 2716 { 0x03, 0, 0x0042 }, 2717 { 0x06, 0x0080, 0x0000 }, 2718 { 0x07, 0, 0x2000 } 2719 }; 2720 2721 rtl_set_def_aspm_entry_latency(tp); 2722 2723 rtl_ephy_init(tp, e_info_8168cp); 2724 2725 __rtl_hw_start_8168cp(tp); 2726 } 2727 2728 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2729 { 2730 rtl_set_def_aspm_entry_latency(tp); 2731 2732 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2733 } 2734 2735 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2736 { 2737 rtl_set_def_aspm_entry_latency(tp); 2738 2739 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2740 2741 /* Magic. */ 2742 RTL_W8(tp, DBG_REG, 0x20); 2743 } 2744 2745 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2746 { 2747 static const struct ephy_info e_info_8168c_1[] = { 2748 { 0x02, 0x0800, 0x1000 }, 2749 { 0x03, 0, 0x0002 }, 2750 { 0x06, 0x0080, 0x0000 } 2751 }; 2752 2753 rtl_set_def_aspm_entry_latency(tp); 2754 2755 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2756 2757 rtl_ephy_init(tp, e_info_8168c_1); 2758 2759 __rtl_hw_start_8168cp(tp); 2760 } 2761 2762 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2763 { 2764 static const struct ephy_info e_info_8168c_2[] = { 2765 { 0x01, 0, 0x0001 }, 2766 { 0x03, 0x0400, 0x0020 } 2767 }; 2768 2769 rtl_set_def_aspm_entry_latency(tp); 2770 2771 rtl_ephy_init(tp, e_info_8168c_2); 2772 2773 __rtl_hw_start_8168cp(tp); 2774 } 2775 2776 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2777 { 2778 rtl_set_def_aspm_entry_latency(tp); 2779 2780 __rtl_hw_start_8168cp(tp); 2781 } 2782 2783 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2784 { 2785 rtl_set_def_aspm_entry_latency(tp); 2786 2787 rtl_disable_clock_request(tp); 2788 } 2789 2790 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2791 { 2792 static const struct ephy_info e_info_8168d_4[] = { 2793 { 0x0b, 0x0000, 0x0048 }, 2794 { 0x19, 0x0020, 0x0050 }, 2795 { 0x0c, 0x0100, 0x0020 }, 2796 { 0x10, 0x0004, 0x0000 }, 2797 }; 2798 2799 rtl_set_def_aspm_entry_latency(tp); 2800 2801 rtl_ephy_init(tp, e_info_8168d_4); 2802 2803 rtl_enable_clock_request(tp); 2804 } 2805 2806 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2807 { 2808 static const struct ephy_info e_info_8168e_1[] = { 2809 { 0x00, 0x0200, 0x0100 }, 2810 { 0x00, 0x0000, 0x0004 }, 2811 { 0x06, 0x0002, 0x0001 }, 2812 { 0x06, 0x0000, 0x0030 }, 2813 { 0x07, 0x0000, 0x2000 }, 2814 { 0x00, 0x0000, 0x0020 }, 2815 { 0x03, 0x5800, 0x2000 }, 2816 { 0x03, 0x0000, 0x0001 }, 2817 { 0x01, 0x0800, 0x1000 }, 2818 { 0x07, 0x0000, 0x4000 }, 2819 { 0x1e, 0x0000, 0x2000 }, 2820 { 0x19, 0xffff, 0xfe6c }, 2821 { 0x0a, 0x0000, 0x0040 } 2822 }; 2823 2824 rtl_set_def_aspm_entry_latency(tp); 2825 2826 rtl_ephy_init(tp, e_info_8168e_1); 2827 2828 rtl_disable_clock_request(tp); 2829 2830 /* Reset tx FIFO pointer */ 2831 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2832 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2833 2834 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2835 } 2836 2837 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2838 { 2839 static const struct ephy_info e_info_8168e_2[] = { 2840 { 0x09, 0x0000, 0x0080 }, 2841 { 0x19, 0x0000, 0x0224 }, 2842 { 0x00, 0x0000, 0x0004 }, 2843 { 0x0c, 0x3df0, 0x0200 }, 2844 }; 2845 2846 rtl_set_def_aspm_entry_latency(tp); 2847 2848 rtl_ephy_init(tp, e_info_8168e_2); 2849 2850 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2851 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2852 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2853 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2854 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2855 rtl_reset_packet_filter(tp); 2856 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2857 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2858 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2859 2860 rtl_disable_clock_request(tp); 2861 2862 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2863 2864 rtl8168_config_eee_mac(tp); 2865 2866 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2867 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2868 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2869 2870 rtl_hw_aspm_clkreq_enable(tp, true); 2871 } 2872 2873 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2874 { 2875 rtl_set_def_aspm_entry_latency(tp); 2876 2877 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2878 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2879 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2880 rtl_reset_packet_filter(tp); 2881 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2882 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2883 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2884 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2885 2886 rtl_disable_clock_request(tp); 2887 2888 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2889 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2890 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2891 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2892 2893 rtl8168_config_eee_mac(tp); 2894 } 2895 2896 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2897 { 2898 static const struct ephy_info e_info_8168f_1[] = { 2899 { 0x06, 0x00c0, 0x0020 }, 2900 { 0x08, 0x0001, 0x0002 }, 2901 { 0x09, 0x0000, 0x0080 }, 2902 { 0x19, 0x0000, 0x0224 }, 2903 { 0x00, 0x0000, 0x0008 }, 2904 { 0x0c, 0x3df0, 0x0200 }, 2905 }; 2906 2907 rtl_hw_start_8168f(tp); 2908 2909 rtl_ephy_init(tp, e_info_8168f_1); 2910 2911 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2912 } 2913 2914 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2915 { 2916 static const struct ephy_info e_info_8168f_1[] = { 2917 { 0x06, 0x00c0, 0x0020 }, 2918 { 0x0f, 0xffff, 0x5200 }, 2919 { 0x19, 0x0000, 0x0224 }, 2920 { 0x00, 0x0000, 0x0008 }, 2921 { 0x0c, 0x3df0, 0x0200 }, 2922 }; 2923 2924 rtl_hw_start_8168f(tp); 2925 rtl_pcie_state_l2l3_disable(tp); 2926 2927 rtl_ephy_init(tp, e_info_8168f_1); 2928 2929 rtl_eri_set_bits(tp, 0x0d4, 0x0c00); 2930 } 2931 2932 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2933 { 2934 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2935 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2936 2937 rtl_set_def_aspm_entry_latency(tp); 2938 2939 rtl_reset_packet_filter(tp); 2940 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2941 2942 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2943 2944 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2945 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2946 rtl_eri_set_bits(tp, 0x0d4, 0x1f80); 2947 2948 rtl8168_config_eee_mac(tp); 2949 2950 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2951 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2952 2953 rtl_pcie_state_l2l3_disable(tp); 2954 } 2955 2956 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2957 { 2958 static const struct ephy_info e_info_8168g_1[] = { 2959 { 0x00, 0x0008, 0x0000 }, 2960 { 0x0c, 0x3ff0, 0x0820 }, 2961 { 0x1e, 0x0000, 0x0001 }, 2962 { 0x19, 0x8000, 0x0000 } 2963 }; 2964 2965 rtl_hw_start_8168g(tp); 2966 2967 /* disable aspm and clock request before access ephy */ 2968 rtl_hw_aspm_clkreq_enable(tp, false); 2969 rtl_ephy_init(tp, e_info_8168g_1); 2970 rtl_hw_aspm_clkreq_enable(tp, true); 2971 } 2972 2973 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 2974 { 2975 static const struct ephy_info e_info_8168g_2[] = { 2976 { 0x00, 0x0008, 0x0000 }, 2977 { 0x0c, 0x3ff0, 0x0820 }, 2978 { 0x19, 0xffff, 0x7c00 }, 2979 { 0x1e, 0xffff, 0x20eb }, 2980 { 0x0d, 0xffff, 0x1666 }, 2981 { 0x00, 0xffff, 0x10a3 }, 2982 { 0x06, 0xffff, 0xf050 }, 2983 { 0x04, 0x0000, 0x0010 }, 2984 { 0x1d, 0x4000, 0x0000 }, 2985 }; 2986 2987 rtl_hw_start_8168g(tp); 2988 2989 /* disable aspm and clock request before access ephy */ 2990 rtl_hw_aspm_clkreq_enable(tp, false); 2991 rtl_ephy_init(tp, e_info_8168g_2); 2992 } 2993 2994 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 2995 { 2996 static const struct ephy_info e_info_8411_2[] = { 2997 { 0x00, 0x0008, 0x0000 }, 2998 { 0x0c, 0x37d0, 0x0820 }, 2999 { 0x1e, 0x0000, 0x0001 }, 3000 { 0x19, 0x8021, 0x0000 }, 3001 { 0x1e, 0x0000, 0x2000 }, 3002 { 0x0d, 0x0100, 0x0200 }, 3003 { 0x00, 0x0000, 0x0080 }, 3004 { 0x06, 0x0000, 0x0010 }, 3005 { 0x04, 0x0000, 0x0010 }, 3006 { 0x1d, 0x0000, 0x4000 }, 3007 }; 3008 3009 rtl_hw_start_8168g(tp); 3010 3011 /* disable aspm and clock request before access ephy */ 3012 rtl_hw_aspm_clkreq_enable(tp, false); 3013 rtl_ephy_init(tp, e_info_8411_2); 3014 3015 /* The following Realtek-provided magic fixes an issue with the RX unit 3016 * getting confused after the PHY having been powered-down. 3017 */ 3018 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3019 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3020 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3021 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3022 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3023 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3024 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3025 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3026 mdelay(3); 3027 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3028 3029 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3030 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3031 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3032 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3033 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3034 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3035 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3036 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3037 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3038 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3039 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3040 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3041 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3042 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3043 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3044 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3045 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3046 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3047 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3048 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3049 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3050 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3051 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3052 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3053 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3054 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3055 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3056 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3057 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3058 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3059 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3060 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3061 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3062 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3063 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3064 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3065 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3066 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3067 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3068 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3069 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3070 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3071 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3072 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3073 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3074 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3075 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3076 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3077 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3078 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3079 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3080 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3081 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3082 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3083 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3084 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3085 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3086 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3087 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3088 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3089 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3090 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3091 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3092 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3093 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3094 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3095 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3096 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3097 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3098 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3099 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3100 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3101 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3102 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3103 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3104 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3105 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3106 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3107 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3108 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3109 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3110 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3111 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3112 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3113 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3114 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3115 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3116 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3117 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3118 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3119 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3120 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3121 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3122 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3123 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3124 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3125 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3126 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3127 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3128 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3129 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3130 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3131 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3132 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3133 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3134 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3135 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3136 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3137 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3138 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3139 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3140 3141 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3142 3143 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3144 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3145 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3146 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3147 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3148 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3149 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3150 3151 rtl_hw_aspm_clkreq_enable(tp, true); 3152 } 3153 3154 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3155 { 3156 static const struct ephy_info e_info_8168h_1[] = { 3157 { 0x1e, 0x0800, 0x0001 }, 3158 { 0x1d, 0x0000, 0x0800 }, 3159 { 0x05, 0xffff, 0x2089 }, 3160 { 0x06, 0xffff, 0x5881 }, 3161 { 0x04, 0xffff, 0x854a }, 3162 { 0x01, 0xffff, 0x068b } 3163 }; 3164 int rg_saw_cnt; 3165 3166 /* disable aspm and clock request before access ephy */ 3167 rtl_hw_aspm_clkreq_enable(tp, false); 3168 rtl_ephy_init(tp, e_info_8168h_1); 3169 3170 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3171 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3172 3173 rtl_set_def_aspm_entry_latency(tp); 3174 3175 rtl_reset_packet_filter(tp); 3176 3177 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3178 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3179 3180 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3181 3182 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3183 3184 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3185 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3186 3187 rtl8168_config_eee_mac(tp); 3188 3189 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3190 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3191 3192 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3193 3194 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3195 3196 rtl_pcie_state_l2l3_disable(tp); 3197 3198 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3199 if (rg_saw_cnt > 0) { 3200 u16 sw_cnt_1ms_ini; 3201 3202 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3203 sw_cnt_1ms_ini &= 0x0fff; 3204 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3205 } 3206 3207 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3208 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3209 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3210 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3211 3212 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3213 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3214 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3215 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3216 3217 rtl_hw_aspm_clkreq_enable(tp, true); 3218 } 3219 3220 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3221 { 3222 rtl8168ep_stop_cmac(tp); 3223 3224 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3225 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3226 3227 rtl_set_def_aspm_entry_latency(tp); 3228 3229 rtl_reset_packet_filter(tp); 3230 3231 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 3232 3233 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3234 3235 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3236 3237 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3238 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3239 3240 rtl8168_config_eee_mac(tp); 3241 3242 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3243 3244 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3245 3246 rtl_pcie_state_l2l3_disable(tp); 3247 } 3248 3249 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3250 { 3251 static const struct ephy_info e_info_8168ep_1[] = { 3252 { 0x00, 0xffff, 0x10ab }, 3253 { 0x06, 0xffff, 0xf030 }, 3254 { 0x08, 0xffff, 0x2006 }, 3255 { 0x0d, 0xffff, 0x1666 }, 3256 { 0x0c, 0x3ff0, 0x0000 } 3257 }; 3258 3259 /* disable aspm and clock request before access ephy */ 3260 rtl_hw_aspm_clkreq_enable(tp, false); 3261 rtl_ephy_init(tp, e_info_8168ep_1); 3262 3263 rtl_hw_start_8168ep(tp); 3264 3265 rtl_hw_aspm_clkreq_enable(tp, true); 3266 } 3267 3268 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3269 { 3270 static const struct ephy_info e_info_8168ep_2[] = { 3271 { 0x00, 0xffff, 0x10a3 }, 3272 { 0x19, 0xffff, 0xfc00 }, 3273 { 0x1e, 0xffff, 0x20ea } 3274 }; 3275 3276 /* disable aspm and clock request before access ephy */ 3277 rtl_hw_aspm_clkreq_enable(tp, false); 3278 rtl_ephy_init(tp, e_info_8168ep_2); 3279 3280 rtl_hw_start_8168ep(tp); 3281 3282 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3283 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3284 3285 rtl_hw_aspm_clkreq_enable(tp, true); 3286 } 3287 3288 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3289 { 3290 static const struct ephy_info e_info_8168ep_3[] = { 3291 { 0x00, 0x0000, 0x0080 }, 3292 { 0x0d, 0x0100, 0x0200 }, 3293 { 0x19, 0x8021, 0x0000 }, 3294 { 0x1e, 0x0000, 0x2000 }, 3295 }; 3296 3297 /* disable aspm and clock request before access ephy */ 3298 rtl_hw_aspm_clkreq_enable(tp, false); 3299 rtl_ephy_init(tp, e_info_8168ep_3); 3300 3301 rtl_hw_start_8168ep(tp); 3302 3303 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3304 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3305 3306 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3307 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3308 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3309 3310 rtl_hw_aspm_clkreq_enable(tp, true); 3311 } 3312 3313 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3314 { 3315 static const struct ephy_info e_info_8117[] = { 3316 { 0x19, 0x0040, 0x1100 }, 3317 { 0x59, 0x0040, 0x1100 }, 3318 }; 3319 int rg_saw_cnt; 3320 3321 rtl8168ep_stop_cmac(tp); 3322 3323 /* disable aspm and clock request before access ephy */ 3324 rtl_hw_aspm_clkreq_enable(tp, false); 3325 rtl_ephy_init(tp, e_info_8117); 3326 3327 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3328 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3329 3330 rtl_set_def_aspm_entry_latency(tp); 3331 3332 rtl_reset_packet_filter(tp); 3333 3334 rtl_eri_set_bits(tp, 0xd4, 0x1f90); 3335 3336 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3337 3338 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3339 3340 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3341 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3342 3343 rtl8168_config_eee_mac(tp); 3344 3345 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3346 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3347 3348 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3349 3350 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3351 3352 rtl_pcie_state_l2l3_disable(tp); 3353 3354 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3355 if (rg_saw_cnt > 0) { 3356 u16 sw_cnt_1ms_ini; 3357 3358 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3359 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3360 } 3361 3362 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3363 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3364 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3365 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3366 3367 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3368 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3369 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3370 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3371 3372 /* firmware is for MAC only */ 3373 r8169_apply_firmware(tp); 3374 3375 rtl_hw_aspm_clkreq_enable(tp, true); 3376 } 3377 3378 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3379 { 3380 static const struct ephy_info e_info_8102e_1[] = { 3381 { 0x01, 0, 0x6e65 }, 3382 { 0x02, 0, 0x091f }, 3383 { 0x03, 0, 0xc2f9 }, 3384 { 0x06, 0, 0xafb5 }, 3385 { 0x07, 0, 0x0e00 }, 3386 { 0x19, 0, 0xec80 }, 3387 { 0x01, 0, 0x2e65 }, 3388 { 0x01, 0, 0x6e65 } 3389 }; 3390 u8 cfg1; 3391 3392 rtl_set_def_aspm_entry_latency(tp); 3393 3394 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3395 3396 RTL_W8(tp, Config1, 3397 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3398 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3399 3400 cfg1 = RTL_R8(tp, Config1); 3401 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3402 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3403 3404 rtl_ephy_init(tp, e_info_8102e_1); 3405 } 3406 3407 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3408 { 3409 rtl_set_def_aspm_entry_latency(tp); 3410 3411 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3412 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3413 } 3414 3415 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3416 { 3417 rtl_hw_start_8102e_2(tp); 3418 3419 rtl_ephy_write(tp, 0x03, 0xc2f9); 3420 } 3421 3422 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3423 { 3424 static const struct ephy_info e_info_8401[] = { 3425 { 0x01, 0xffff, 0x6fe5 }, 3426 { 0x03, 0xffff, 0x0599 }, 3427 { 0x06, 0xffff, 0xaf25 }, 3428 { 0x07, 0xffff, 0x8e68 }, 3429 }; 3430 3431 rtl_ephy_init(tp, e_info_8401); 3432 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3433 } 3434 3435 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3436 { 3437 static const struct ephy_info e_info_8105e_1[] = { 3438 { 0x07, 0, 0x4000 }, 3439 { 0x19, 0, 0x0200 }, 3440 { 0x19, 0, 0x0020 }, 3441 { 0x1e, 0, 0x2000 }, 3442 { 0x03, 0, 0x0001 }, 3443 { 0x19, 0, 0x0100 }, 3444 { 0x19, 0, 0x0004 }, 3445 { 0x0a, 0, 0x0020 } 3446 }; 3447 3448 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3449 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3450 3451 /* Disable Early Tally Counter */ 3452 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3453 3454 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3455 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3456 3457 rtl_ephy_init(tp, e_info_8105e_1); 3458 3459 rtl_pcie_state_l2l3_disable(tp); 3460 } 3461 3462 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3463 { 3464 rtl_hw_start_8105e_1(tp); 3465 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3466 } 3467 3468 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3469 { 3470 static const struct ephy_info e_info_8402[] = { 3471 { 0x19, 0xffff, 0xff64 }, 3472 { 0x1e, 0, 0x4000 } 3473 }; 3474 3475 rtl_set_def_aspm_entry_latency(tp); 3476 3477 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3478 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3479 3480 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3481 3482 rtl_ephy_init(tp, e_info_8402); 3483 3484 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3485 rtl_reset_packet_filter(tp); 3486 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3487 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3488 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3489 3490 /* disable EEE */ 3491 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3492 3493 rtl_pcie_state_l2l3_disable(tp); 3494 } 3495 3496 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3497 { 3498 rtl_hw_aspm_clkreq_enable(tp, false); 3499 3500 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3501 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3502 3503 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3504 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3505 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3506 3507 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3508 3509 /* disable EEE */ 3510 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3511 3512 rtl_pcie_state_l2l3_disable(tp); 3513 rtl_hw_aspm_clkreq_enable(tp, true); 3514 } 3515 3516 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3517 { 3518 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3519 } 3520 3521 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3522 { 3523 rtl_pcie_state_l2l3_disable(tp); 3524 3525 RTL_W16(tp, 0x382, 0x221b); 3526 RTL_W8(tp, 0x4500, 0); 3527 RTL_W16(tp, 0x4800, 0); 3528 3529 /* disable UPS */ 3530 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3531 3532 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3533 3534 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3535 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3536 3537 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3538 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3539 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3540 3541 /* disable new tx descriptor format */ 3542 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3543 3544 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3545 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3546 else 3547 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3548 3549 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3550 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3551 else 3552 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3553 3554 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3555 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3556 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3557 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3558 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3559 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3560 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3561 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3562 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3563 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3564 3565 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3566 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3567 udelay(1); 3568 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3569 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3570 3571 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3572 3573 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3574 3575 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3576 rtl8125b_config_eee_mac(tp); 3577 else 3578 rtl8125a_config_eee_mac(tp); 3579 3580 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3581 udelay(10); 3582 } 3583 3584 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp) 3585 { 3586 static const struct ephy_info e_info_8125a_1[] = { 3587 { 0x01, 0xffff, 0xa812 }, 3588 { 0x09, 0xffff, 0x520c }, 3589 { 0x04, 0xffff, 0xd000 }, 3590 { 0x0d, 0xffff, 0xf702 }, 3591 { 0x0a, 0xffff, 0x8653 }, 3592 { 0x06, 0xffff, 0x001e }, 3593 { 0x08, 0xffff, 0x3595 }, 3594 { 0x20, 0xffff, 0x9455 }, 3595 { 0x21, 0xffff, 0x99ff }, 3596 { 0x02, 0xffff, 0x6046 }, 3597 { 0x29, 0xffff, 0xfe00 }, 3598 { 0x23, 0xffff, 0xab62 }, 3599 3600 { 0x41, 0xffff, 0xa80c }, 3601 { 0x49, 0xffff, 0x520c }, 3602 { 0x44, 0xffff, 0xd000 }, 3603 { 0x4d, 0xffff, 0xf702 }, 3604 { 0x4a, 0xffff, 0x8653 }, 3605 { 0x46, 0xffff, 0x001e }, 3606 { 0x48, 0xffff, 0x3595 }, 3607 { 0x60, 0xffff, 0x9455 }, 3608 { 0x61, 0xffff, 0x99ff }, 3609 { 0x42, 0xffff, 0x6046 }, 3610 { 0x69, 0xffff, 0xfe00 }, 3611 { 0x63, 0xffff, 0xab62 }, 3612 }; 3613 3614 rtl_set_def_aspm_entry_latency(tp); 3615 3616 /* disable aspm and clock request before access ephy */ 3617 rtl_hw_aspm_clkreq_enable(tp, false); 3618 rtl_ephy_init(tp, e_info_8125a_1); 3619 3620 rtl_hw_start_8125_common(tp); 3621 rtl_hw_aspm_clkreq_enable(tp, true); 3622 } 3623 3624 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3625 { 3626 static const struct ephy_info e_info_8125a_2[] = { 3627 { 0x04, 0xffff, 0xd000 }, 3628 { 0x0a, 0xffff, 0x8653 }, 3629 { 0x23, 0xffff, 0xab66 }, 3630 { 0x20, 0xffff, 0x9455 }, 3631 { 0x21, 0xffff, 0x99ff }, 3632 { 0x29, 0xffff, 0xfe04 }, 3633 3634 { 0x44, 0xffff, 0xd000 }, 3635 { 0x4a, 0xffff, 0x8653 }, 3636 { 0x63, 0xffff, 0xab66 }, 3637 { 0x60, 0xffff, 0x9455 }, 3638 { 0x61, 0xffff, 0x99ff }, 3639 { 0x69, 0xffff, 0xfe04 }, 3640 }; 3641 3642 rtl_set_def_aspm_entry_latency(tp); 3643 3644 /* disable aspm and clock request before access ephy */ 3645 rtl_hw_aspm_clkreq_enable(tp, false); 3646 rtl_ephy_init(tp, e_info_8125a_2); 3647 3648 rtl_hw_start_8125_common(tp); 3649 rtl_hw_aspm_clkreq_enable(tp, true); 3650 } 3651 3652 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3653 { 3654 static const struct ephy_info e_info_8125b[] = { 3655 { 0x0b, 0xffff, 0xa908 }, 3656 { 0x1e, 0xffff, 0x20eb }, 3657 { 0x4b, 0xffff, 0xa908 }, 3658 { 0x5e, 0xffff, 0x20eb }, 3659 { 0x22, 0x0030, 0x0020 }, 3660 { 0x62, 0x0030, 0x0020 }, 3661 }; 3662 3663 rtl_set_def_aspm_entry_latency(tp); 3664 rtl_hw_aspm_clkreq_enable(tp, false); 3665 3666 rtl_ephy_init(tp, e_info_8125b); 3667 rtl_hw_start_8125_common(tp); 3668 3669 rtl_hw_aspm_clkreq_enable(tp, true); 3670 } 3671 3672 static void rtl_hw_config(struct rtl8169_private *tp) 3673 { 3674 static const rtl_generic_fct hw_configs[] = { 3675 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3676 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3677 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3678 [RTL_GIGA_MAC_VER_10] = NULL, 3679 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3680 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3681 [RTL_GIGA_MAC_VER_13] = NULL, 3682 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3683 [RTL_GIGA_MAC_VER_16] = NULL, 3684 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3685 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3686 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3687 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3688 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3689 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3690 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3691 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3692 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3693 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3694 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3695 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3696 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3697 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3698 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3699 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3700 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3701 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3702 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3703 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3704 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3705 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3706 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3707 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3708 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3709 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3710 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3711 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3712 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3713 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3714 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3715 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3716 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3717 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3718 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3719 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3720 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3721 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1, 3722 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3723 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3724 }; 3725 3726 if (hw_configs[tp->mac_version]) 3727 hw_configs[tp->mac_version](tp); 3728 } 3729 3730 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3731 { 3732 int i; 3733 3734 /* disable interrupt coalescing */ 3735 for (i = 0xa00; i < 0xb00; i += 4) 3736 RTL_W32(tp, i, 0); 3737 3738 rtl_hw_config(tp); 3739 } 3740 3741 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3742 { 3743 if (rtl_is_8168evl_up(tp)) 3744 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3745 else 3746 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3747 3748 rtl_hw_config(tp); 3749 3750 /* disable interrupt coalescing */ 3751 RTL_W16(tp, IntrMitigate, 0x0000); 3752 } 3753 3754 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3755 { 3756 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3757 3758 tp->cp_cmd |= PCIMulRW; 3759 3760 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3761 tp->mac_version == RTL_GIGA_MAC_VER_03) 3762 tp->cp_cmd |= EnAnaPLL; 3763 3764 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3765 3766 rtl8169_set_magic_reg(tp); 3767 3768 /* disable interrupt coalescing */ 3769 RTL_W16(tp, IntrMitigate, 0x0000); 3770 } 3771 3772 static void rtl_hw_start(struct rtl8169_private *tp) 3773 { 3774 rtl_unlock_config_regs(tp); 3775 3776 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3777 3778 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3779 rtl_hw_start_8169(tp); 3780 else if (rtl_is_8125(tp)) 3781 rtl_hw_start_8125(tp); 3782 else 3783 rtl_hw_start_8168(tp); 3784 3785 rtl_set_rx_max_size(tp); 3786 rtl_set_rx_tx_desc_registers(tp); 3787 rtl_lock_config_regs(tp); 3788 3789 rtl_jumbo_config(tp); 3790 3791 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3792 rtl_pci_commit(tp); 3793 3794 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3795 rtl_init_rxcfg(tp); 3796 rtl_set_tx_config_registers(tp); 3797 rtl_set_rx_config_features(tp, tp->dev->features); 3798 rtl_set_rx_mode(tp->dev); 3799 rtl_irq_enable(tp); 3800 } 3801 3802 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3803 { 3804 struct rtl8169_private *tp = netdev_priv(dev); 3805 3806 dev->mtu = new_mtu; 3807 netdev_update_features(dev); 3808 rtl_jumbo_config(tp); 3809 3810 switch (tp->mac_version) { 3811 case RTL_GIGA_MAC_VER_61: 3812 case RTL_GIGA_MAC_VER_63: 3813 rtl8125_set_eee_txidle_timer(tp); 3814 break; 3815 default: 3816 break; 3817 } 3818 3819 return 0; 3820 } 3821 3822 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3823 { 3824 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3825 3826 desc->opts2 = 0; 3827 /* Force memory writes to complete before releasing descriptor */ 3828 dma_wmb(); 3829 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3830 } 3831 3832 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3833 struct RxDesc *desc) 3834 { 3835 struct device *d = tp_to_dev(tp); 3836 int node = dev_to_node(d); 3837 dma_addr_t mapping; 3838 struct page *data; 3839 3840 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3841 if (!data) 3842 return NULL; 3843 3844 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3845 if (unlikely(dma_mapping_error(d, mapping))) { 3846 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3847 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3848 return NULL; 3849 } 3850 3851 desc->addr = cpu_to_le64(mapping); 3852 rtl8169_mark_to_asic(desc); 3853 3854 return data; 3855 } 3856 3857 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3858 { 3859 int i; 3860 3861 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3862 dma_unmap_page(tp_to_dev(tp), 3863 le64_to_cpu(tp->RxDescArray[i].addr), 3864 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3865 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3866 tp->Rx_databuff[i] = NULL; 3867 tp->RxDescArray[i].addr = 0; 3868 tp->RxDescArray[i].opts1 = 0; 3869 } 3870 } 3871 3872 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3873 { 3874 int i; 3875 3876 for (i = 0; i < NUM_RX_DESC; i++) { 3877 struct page *data; 3878 3879 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3880 if (!data) { 3881 rtl8169_rx_clear(tp); 3882 return -ENOMEM; 3883 } 3884 tp->Rx_databuff[i] = data; 3885 } 3886 3887 /* mark as last descriptor in the ring */ 3888 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3889 3890 return 0; 3891 } 3892 3893 static int rtl8169_init_ring(struct rtl8169_private *tp) 3894 { 3895 rtl8169_init_ring_indexes(tp); 3896 3897 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3898 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3899 3900 return rtl8169_rx_fill(tp); 3901 } 3902 3903 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3904 { 3905 struct ring_info *tx_skb = tp->tx_skb + entry; 3906 struct TxDesc *desc = tp->TxDescArray + entry; 3907 3908 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3909 DMA_TO_DEVICE); 3910 memset(desc, 0, sizeof(*desc)); 3911 memset(tx_skb, 0, sizeof(*tx_skb)); 3912 } 3913 3914 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3915 unsigned int n) 3916 { 3917 unsigned int i; 3918 3919 for (i = 0; i < n; i++) { 3920 unsigned int entry = (start + i) % NUM_TX_DESC; 3921 struct ring_info *tx_skb = tp->tx_skb + entry; 3922 unsigned int len = tx_skb->len; 3923 3924 if (len) { 3925 struct sk_buff *skb = tx_skb->skb; 3926 3927 rtl8169_unmap_tx_skb(tp, entry); 3928 if (skb) 3929 dev_consume_skb_any(skb); 3930 } 3931 } 3932 } 3933 3934 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3935 { 3936 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3937 netdev_reset_queue(tp->dev); 3938 } 3939 3940 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3941 { 3942 napi_disable(&tp->napi); 3943 3944 /* Give a racing hard_start_xmit a few cycles to complete. */ 3945 synchronize_net(); 3946 3947 /* Disable interrupts */ 3948 rtl8169_irq_mask_and_ack(tp); 3949 3950 rtl_rx_close(tp); 3951 3952 if (going_down && tp->dev->wol_enabled) 3953 goto no_reset; 3954 3955 switch (tp->mac_version) { 3956 case RTL_GIGA_MAC_VER_27: 3957 case RTL_GIGA_MAC_VER_28: 3958 case RTL_GIGA_MAC_VER_31: 3959 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3960 break; 3961 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3962 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3963 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3964 break; 3965 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3966 rtl_enable_rxdvgate(tp); 3967 fsleep(2000); 3968 break; 3969 default: 3970 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3971 fsleep(100); 3972 break; 3973 } 3974 3975 rtl_hw_reset(tp); 3976 no_reset: 3977 rtl8169_tx_clear(tp); 3978 rtl8169_init_ring_indexes(tp); 3979 } 3980 3981 static void rtl_reset_work(struct rtl8169_private *tp) 3982 { 3983 int i; 3984 3985 netif_stop_queue(tp->dev); 3986 3987 rtl8169_cleanup(tp, false); 3988 3989 for (i = 0; i < NUM_RX_DESC; i++) 3990 rtl8169_mark_to_asic(tp->RxDescArray + i); 3991 3992 napi_enable(&tp->napi); 3993 rtl_hw_start(tp); 3994 } 3995 3996 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3997 { 3998 struct rtl8169_private *tp = netdev_priv(dev); 3999 4000 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4001 } 4002 4003 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4004 void *addr, unsigned int entry, bool desc_own) 4005 { 4006 struct TxDesc *txd = tp->TxDescArray + entry; 4007 struct device *d = tp_to_dev(tp); 4008 dma_addr_t mapping; 4009 u32 opts1; 4010 int ret; 4011 4012 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4013 ret = dma_mapping_error(d, mapping); 4014 if (unlikely(ret)) { 4015 if (net_ratelimit()) 4016 netdev_err(tp->dev, "Failed to map TX data!\n"); 4017 return ret; 4018 } 4019 4020 txd->addr = cpu_to_le64(mapping); 4021 txd->opts2 = cpu_to_le32(opts[1]); 4022 4023 opts1 = opts[0] | len; 4024 if (entry == NUM_TX_DESC - 1) 4025 opts1 |= RingEnd; 4026 if (desc_own) 4027 opts1 |= DescOwn; 4028 txd->opts1 = cpu_to_le32(opts1); 4029 4030 tp->tx_skb[entry].len = len; 4031 4032 return 0; 4033 } 4034 4035 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4036 const u32 *opts, unsigned int entry) 4037 { 4038 struct skb_shared_info *info = skb_shinfo(skb); 4039 unsigned int cur_frag; 4040 4041 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4042 const skb_frag_t *frag = info->frags + cur_frag; 4043 void *addr = skb_frag_address(frag); 4044 u32 len = skb_frag_size(frag); 4045 4046 entry = (entry + 1) % NUM_TX_DESC; 4047 4048 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4049 goto err_out; 4050 } 4051 4052 return 0; 4053 4054 err_out: 4055 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4056 return -EIO; 4057 } 4058 4059 static bool rtl_skb_is_udp(struct sk_buff *skb) 4060 { 4061 int no = skb_network_offset(skb); 4062 struct ipv6hdr *i6h, _i6h; 4063 struct iphdr *ih, _ih; 4064 4065 switch (vlan_get_protocol(skb)) { 4066 case htons(ETH_P_IP): 4067 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4068 return ih && ih->protocol == IPPROTO_UDP; 4069 case htons(ETH_P_IPV6): 4070 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4071 return i6h && i6h->nexthdr == IPPROTO_UDP; 4072 default: 4073 return false; 4074 } 4075 } 4076 4077 #define RTL_MIN_PATCH_LEN 47 4078 4079 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4080 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4081 struct sk_buff *skb) 4082 { 4083 unsigned int padto = 0, len = skb->len; 4084 4085 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4086 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4087 unsigned int trans_data_len = skb_tail_pointer(skb) - 4088 skb_transport_header(skb); 4089 4090 if (trans_data_len >= offsetof(struct udphdr, len) && 4091 trans_data_len < RTL_MIN_PATCH_LEN) { 4092 u16 dest = ntohs(udp_hdr(skb)->dest); 4093 4094 /* dest is a standard PTP port */ 4095 if (dest == 319 || dest == 320) 4096 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4097 } 4098 4099 if (trans_data_len < sizeof(struct udphdr)) 4100 padto = max_t(unsigned int, padto, 4101 len + sizeof(struct udphdr) - trans_data_len); 4102 } 4103 4104 return padto; 4105 } 4106 4107 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4108 struct sk_buff *skb) 4109 { 4110 unsigned int padto; 4111 4112 padto = rtl8125_quirk_udp_padto(tp, skb); 4113 4114 switch (tp->mac_version) { 4115 case RTL_GIGA_MAC_VER_34: 4116 case RTL_GIGA_MAC_VER_60: 4117 case RTL_GIGA_MAC_VER_61: 4118 case RTL_GIGA_MAC_VER_63: 4119 padto = max_t(unsigned int, padto, ETH_ZLEN); 4120 default: 4121 break; 4122 } 4123 4124 return padto; 4125 } 4126 4127 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4128 { 4129 u32 mss = skb_shinfo(skb)->gso_size; 4130 4131 if (mss) { 4132 opts[0] |= TD_LSO; 4133 opts[0] |= mss << TD0_MSS_SHIFT; 4134 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4135 const struct iphdr *ip = ip_hdr(skb); 4136 4137 if (ip->protocol == IPPROTO_TCP) 4138 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4139 else if (ip->protocol == IPPROTO_UDP) 4140 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4141 else 4142 WARN_ON_ONCE(1); 4143 } 4144 } 4145 4146 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4147 struct sk_buff *skb, u32 *opts) 4148 { 4149 u32 transport_offset = (u32)skb_transport_offset(skb); 4150 struct skb_shared_info *shinfo = skb_shinfo(skb); 4151 u32 mss = shinfo->gso_size; 4152 4153 if (mss) { 4154 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4155 opts[0] |= TD1_GTSENV4; 4156 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4157 if (skb_cow_head(skb, 0)) 4158 return false; 4159 4160 tcp_v6_gso_csum_prep(skb); 4161 opts[0] |= TD1_GTSENV6; 4162 } else { 4163 WARN_ON_ONCE(1); 4164 } 4165 4166 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4167 opts[1] |= mss << TD1_MSS_SHIFT; 4168 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4169 u8 ip_protocol; 4170 4171 switch (vlan_get_protocol(skb)) { 4172 case htons(ETH_P_IP): 4173 opts[1] |= TD1_IPv4_CS; 4174 ip_protocol = ip_hdr(skb)->protocol; 4175 break; 4176 4177 case htons(ETH_P_IPV6): 4178 opts[1] |= TD1_IPv6_CS; 4179 ip_protocol = ipv6_hdr(skb)->nexthdr; 4180 break; 4181 4182 default: 4183 ip_protocol = IPPROTO_RAW; 4184 break; 4185 } 4186 4187 if (ip_protocol == IPPROTO_TCP) 4188 opts[1] |= TD1_TCP_CS; 4189 else if (ip_protocol == IPPROTO_UDP) 4190 opts[1] |= TD1_UDP_CS; 4191 else 4192 WARN_ON_ONCE(1); 4193 4194 opts[1] |= transport_offset << TCPHO_SHIFT; 4195 } else { 4196 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4197 4198 /* skb_padto would free the skb on error */ 4199 return !__skb_put_padto(skb, padto, false); 4200 } 4201 4202 return true; 4203 } 4204 4205 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4206 { 4207 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4208 - READ_ONCE(tp->cur_tx); 4209 4210 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4211 return slots_avail > MAX_SKB_FRAGS; 4212 } 4213 4214 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4215 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4216 { 4217 switch (tp->mac_version) { 4218 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4219 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4220 return false; 4221 default: 4222 return true; 4223 } 4224 } 4225 4226 static void rtl8169_doorbell(struct rtl8169_private *tp) 4227 { 4228 if (rtl_is_8125(tp)) 4229 RTL_W16(tp, TxPoll_8125, BIT(0)); 4230 else 4231 RTL_W8(tp, TxPoll, NPQ); 4232 } 4233 4234 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4235 struct net_device *dev) 4236 { 4237 unsigned int frags = skb_shinfo(skb)->nr_frags; 4238 struct rtl8169_private *tp = netdev_priv(dev); 4239 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4240 struct TxDesc *txd_first, *txd_last; 4241 bool stop_queue, door_bell; 4242 u32 opts[2]; 4243 4244 if (unlikely(!rtl_tx_slots_avail(tp))) { 4245 if (net_ratelimit()) 4246 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4247 goto err_stop_0; 4248 } 4249 4250 opts[1] = rtl8169_tx_vlan_tag(skb); 4251 opts[0] = 0; 4252 4253 if (!rtl_chip_supports_csum_v2(tp)) 4254 rtl8169_tso_csum_v1(skb, opts); 4255 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4256 goto err_dma_0; 4257 4258 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4259 entry, false))) 4260 goto err_dma_0; 4261 4262 txd_first = tp->TxDescArray + entry; 4263 4264 if (frags) { 4265 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4266 goto err_dma_1; 4267 entry = (entry + frags) % NUM_TX_DESC; 4268 } 4269 4270 txd_last = tp->TxDescArray + entry; 4271 txd_last->opts1 |= cpu_to_le32(LastFrag); 4272 tp->tx_skb[entry].skb = skb; 4273 4274 skb_tx_timestamp(skb); 4275 4276 /* Force memory writes to complete before releasing descriptor */ 4277 dma_wmb(); 4278 4279 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4280 4281 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4282 4283 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4284 smp_wmb(); 4285 4286 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4287 4288 stop_queue = !rtl_tx_slots_avail(tp); 4289 if (unlikely(stop_queue)) { 4290 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4291 * not miss a ring update when it notices a stopped queue. 4292 */ 4293 smp_wmb(); 4294 netif_stop_queue(dev); 4295 /* Sync with rtl_tx: 4296 * - publish queue status and cur_tx ring index (write barrier) 4297 * - refresh dirty_tx ring index (read barrier). 4298 * May the current thread have a pessimistic view of the ring 4299 * status and forget to wake up queue, a racing rtl_tx thread 4300 * can't. 4301 */ 4302 smp_mb__after_atomic(); 4303 if (rtl_tx_slots_avail(tp)) 4304 netif_start_queue(dev); 4305 door_bell = true; 4306 } 4307 4308 if (door_bell) 4309 rtl8169_doorbell(tp); 4310 4311 return NETDEV_TX_OK; 4312 4313 err_dma_1: 4314 rtl8169_unmap_tx_skb(tp, entry); 4315 err_dma_0: 4316 dev_kfree_skb_any(skb); 4317 dev->stats.tx_dropped++; 4318 return NETDEV_TX_OK; 4319 4320 err_stop_0: 4321 netif_stop_queue(dev); 4322 dev->stats.tx_dropped++; 4323 return NETDEV_TX_BUSY; 4324 } 4325 4326 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4327 { 4328 struct skb_shared_info *info = skb_shinfo(skb); 4329 unsigned int nr_frags = info->nr_frags; 4330 4331 if (!nr_frags) 4332 return UINT_MAX; 4333 4334 return skb_frag_size(info->frags + nr_frags - 1); 4335 } 4336 4337 /* Workaround for hw issues with TSO on RTL8168evl */ 4338 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4339 netdev_features_t features) 4340 { 4341 /* IPv4 header has options field */ 4342 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4343 ip_hdrlen(skb) > sizeof(struct iphdr)) 4344 features &= ~NETIF_F_ALL_TSO; 4345 4346 /* IPv4 TCP header has options field */ 4347 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4348 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4349 features &= ~NETIF_F_ALL_TSO; 4350 4351 else if (rtl_last_frag_len(skb) <= 6) 4352 features &= ~NETIF_F_ALL_TSO; 4353 4354 return features; 4355 } 4356 4357 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4358 struct net_device *dev, 4359 netdev_features_t features) 4360 { 4361 int transport_offset = skb_transport_offset(skb); 4362 struct rtl8169_private *tp = netdev_priv(dev); 4363 4364 if (skb_is_gso(skb)) { 4365 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4366 features = rtl8168evl_fix_tso(skb, features); 4367 4368 if (transport_offset > GTTCPHO_MAX && 4369 rtl_chip_supports_csum_v2(tp)) 4370 features &= ~NETIF_F_ALL_TSO; 4371 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4372 /* work around hw bug on some chip versions */ 4373 if (skb->len < ETH_ZLEN) 4374 features &= ~NETIF_F_CSUM_MASK; 4375 4376 if (rtl_quirk_packet_padto(tp, skb)) 4377 features &= ~NETIF_F_CSUM_MASK; 4378 4379 if (transport_offset > TCPHO_MAX && 4380 rtl_chip_supports_csum_v2(tp)) 4381 features &= ~NETIF_F_CSUM_MASK; 4382 } 4383 4384 return vlan_features_check(skb, features); 4385 } 4386 4387 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4388 { 4389 struct rtl8169_private *tp = netdev_priv(dev); 4390 struct pci_dev *pdev = tp->pci_dev; 4391 int pci_status_errs; 4392 u16 pci_cmd; 4393 4394 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4395 4396 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4397 4398 if (net_ratelimit()) 4399 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4400 pci_cmd, pci_status_errs); 4401 4402 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4403 } 4404 4405 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4406 int budget) 4407 { 4408 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4409 struct sk_buff *skb; 4410 4411 dirty_tx = tp->dirty_tx; 4412 4413 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4414 unsigned int entry = dirty_tx % NUM_TX_DESC; 4415 u32 status; 4416 4417 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4418 if (status & DescOwn) 4419 break; 4420 4421 skb = tp->tx_skb[entry].skb; 4422 rtl8169_unmap_tx_skb(tp, entry); 4423 4424 if (skb) { 4425 pkts_compl++; 4426 bytes_compl += skb->len; 4427 napi_consume_skb(skb, budget); 4428 } 4429 dirty_tx++; 4430 } 4431 4432 if (tp->dirty_tx != dirty_tx) { 4433 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4434 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4435 4436 /* Sync with rtl8169_start_xmit: 4437 * - publish dirty_tx ring index (write barrier) 4438 * - refresh cur_tx ring index and queue status (read barrier) 4439 * May the current thread miss the stopped queue condition, 4440 * a racing xmit thread can only have a right view of the 4441 * ring status. 4442 */ 4443 smp_store_mb(tp->dirty_tx, dirty_tx); 4444 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4445 netif_wake_queue(dev); 4446 /* 4447 * 8168 hack: TxPoll requests are lost when the Tx packets are 4448 * too close. Let's kick an extra TxPoll request when a burst 4449 * of start_xmit activity is detected (if it is not detected, 4450 * it is slow enough). -- FR 4451 * If skb is NULL then we come here again once a tx irq is 4452 * triggered after the last fragment is marked transmitted. 4453 */ 4454 if (tp->cur_tx != dirty_tx && skb) 4455 rtl8169_doorbell(tp); 4456 } 4457 } 4458 4459 static inline int rtl8169_fragmented_frame(u32 status) 4460 { 4461 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4462 } 4463 4464 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4465 { 4466 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4467 4468 if (status == RxProtoTCP || status == RxProtoUDP) 4469 skb->ip_summed = CHECKSUM_UNNECESSARY; 4470 else 4471 skb_checksum_none_assert(skb); 4472 } 4473 4474 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4475 { 4476 struct device *d = tp_to_dev(tp); 4477 int count; 4478 4479 for (count = 0; count < budget; count++, tp->cur_rx++) { 4480 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4481 struct RxDesc *desc = tp->RxDescArray + entry; 4482 struct sk_buff *skb; 4483 const void *rx_buf; 4484 dma_addr_t addr; 4485 u32 status; 4486 4487 status = le32_to_cpu(desc->opts1); 4488 if (status & DescOwn) 4489 break; 4490 4491 /* This barrier is needed to keep us from reading 4492 * any other fields out of the Rx descriptor until 4493 * we know the status of DescOwn 4494 */ 4495 dma_rmb(); 4496 4497 if (unlikely(status & RxRES)) { 4498 if (net_ratelimit()) 4499 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4500 status); 4501 dev->stats.rx_errors++; 4502 if (status & (RxRWT | RxRUNT)) 4503 dev->stats.rx_length_errors++; 4504 if (status & RxCRC) 4505 dev->stats.rx_crc_errors++; 4506 4507 if (!(dev->features & NETIF_F_RXALL)) 4508 goto release_descriptor; 4509 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4510 goto release_descriptor; 4511 } 4512 4513 pkt_size = status & GENMASK(13, 0); 4514 if (likely(!(dev->features & NETIF_F_RXFCS))) 4515 pkt_size -= ETH_FCS_LEN; 4516 4517 /* The driver does not support incoming fragmented frames. 4518 * They are seen as a symptom of over-mtu sized frames. 4519 */ 4520 if (unlikely(rtl8169_fragmented_frame(status))) { 4521 dev->stats.rx_dropped++; 4522 dev->stats.rx_length_errors++; 4523 goto release_descriptor; 4524 } 4525 4526 skb = napi_alloc_skb(&tp->napi, pkt_size); 4527 if (unlikely(!skb)) { 4528 dev->stats.rx_dropped++; 4529 goto release_descriptor; 4530 } 4531 4532 addr = le64_to_cpu(desc->addr); 4533 rx_buf = page_address(tp->Rx_databuff[entry]); 4534 4535 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4536 prefetch(rx_buf); 4537 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4538 skb->tail += pkt_size; 4539 skb->len = pkt_size; 4540 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4541 4542 rtl8169_rx_csum(skb, status); 4543 skb->protocol = eth_type_trans(skb, dev); 4544 4545 rtl8169_rx_vlan_tag(desc, skb); 4546 4547 if (skb->pkt_type == PACKET_MULTICAST) 4548 dev->stats.multicast++; 4549 4550 napi_gro_receive(&tp->napi, skb); 4551 4552 dev_sw_netstats_rx_add(dev, pkt_size); 4553 release_descriptor: 4554 rtl8169_mark_to_asic(desc); 4555 } 4556 4557 return count; 4558 } 4559 4560 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4561 { 4562 struct rtl8169_private *tp = dev_instance; 4563 u32 status = rtl_get_events(tp); 4564 4565 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4566 return IRQ_NONE; 4567 4568 if (unlikely(status & SYSErr)) { 4569 rtl8169_pcierr_interrupt(tp->dev); 4570 goto out; 4571 } 4572 4573 if (status & LinkChg) 4574 phy_mac_interrupt(tp->phydev); 4575 4576 if (unlikely(status & RxFIFOOver && 4577 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4578 netif_stop_queue(tp->dev); 4579 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4580 } 4581 4582 if (napi_schedule_prep(&tp->napi)) { 4583 rtl_irq_disable(tp); 4584 __napi_schedule(&tp->napi); 4585 } 4586 out: 4587 rtl_ack_events(tp, status); 4588 4589 return IRQ_HANDLED; 4590 } 4591 4592 static void rtl_task(struct work_struct *work) 4593 { 4594 struct rtl8169_private *tp = 4595 container_of(work, struct rtl8169_private, wk.work); 4596 4597 rtnl_lock(); 4598 4599 if (!netif_running(tp->dev) || 4600 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4601 goto out_unlock; 4602 4603 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4604 rtl_reset_work(tp); 4605 netif_wake_queue(tp->dev); 4606 } 4607 out_unlock: 4608 rtnl_unlock(); 4609 } 4610 4611 static int rtl8169_poll(struct napi_struct *napi, int budget) 4612 { 4613 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4614 struct net_device *dev = tp->dev; 4615 int work_done; 4616 4617 rtl_tx(dev, tp, budget); 4618 4619 work_done = rtl_rx(dev, tp, budget); 4620 4621 if (work_done < budget && napi_complete_done(napi, work_done)) 4622 rtl_irq_enable(tp); 4623 4624 return work_done; 4625 } 4626 4627 static void r8169_phylink_handler(struct net_device *ndev) 4628 { 4629 struct rtl8169_private *tp = netdev_priv(ndev); 4630 4631 if (netif_carrier_ok(ndev)) { 4632 rtl_link_chg_patch(tp); 4633 pm_request_resume(&tp->pci_dev->dev); 4634 } else { 4635 pm_runtime_idle(&tp->pci_dev->dev); 4636 } 4637 4638 if (net_ratelimit()) 4639 phy_print_status(tp->phydev); 4640 } 4641 4642 static int r8169_phy_connect(struct rtl8169_private *tp) 4643 { 4644 struct phy_device *phydev = tp->phydev; 4645 phy_interface_t phy_mode; 4646 int ret; 4647 4648 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4649 PHY_INTERFACE_MODE_MII; 4650 4651 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4652 phy_mode); 4653 if (ret) 4654 return ret; 4655 4656 if (!tp->supports_gmii) 4657 phy_set_max_speed(phydev, SPEED_100); 4658 4659 phy_attached_info(phydev); 4660 4661 return 0; 4662 } 4663 4664 static void rtl8169_down(struct rtl8169_private *tp) 4665 { 4666 /* Clear all task flags */ 4667 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4668 4669 phy_stop(tp->phydev); 4670 4671 rtl8169_update_counters(tp); 4672 4673 pci_clear_master(tp->pci_dev); 4674 rtl_pci_commit(tp); 4675 4676 rtl8169_cleanup(tp, true); 4677 4678 rtl_prepare_power_down(tp); 4679 } 4680 4681 static void rtl8169_up(struct rtl8169_private *tp) 4682 { 4683 pci_set_master(tp->pci_dev); 4684 phy_init_hw(tp->phydev); 4685 phy_resume(tp->phydev); 4686 rtl8169_init_phy(tp); 4687 napi_enable(&tp->napi); 4688 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4689 rtl_reset_work(tp); 4690 4691 phy_start(tp->phydev); 4692 } 4693 4694 static int rtl8169_close(struct net_device *dev) 4695 { 4696 struct rtl8169_private *tp = netdev_priv(dev); 4697 struct pci_dev *pdev = tp->pci_dev; 4698 4699 pm_runtime_get_sync(&pdev->dev); 4700 4701 netif_stop_queue(dev); 4702 rtl8169_down(tp); 4703 rtl8169_rx_clear(tp); 4704 4705 cancel_work_sync(&tp->wk.work); 4706 4707 free_irq(pci_irq_vector(pdev, 0), tp); 4708 4709 phy_disconnect(tp->phydev); 4710 4711 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4712 tp->RxPhyAddr); 4713 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4714 tp->TxPhyAddr); 4715 tp->TxDescArray = NULL; 4716 tp->RxDescArray = NULL; 4717 4718 pm_runtime_put_sync(&pdev->dev); 4719 4720 return 0; 4721 } 4722 4723 #ifdef CONFIG_NET_POLL_CONTROLLER 4724 static void rtl8169_netpoll(struct net_device *dev) 4725 { 4726 struct rtl8169_private *tp = netdev_priv(dev); 4727 4728 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4729 } 4730 #endif 4731 4732 static int rtl_open(struct net_device *dev) 4733 { 4734 struct rtl8169_private *tp = netdev_priv(dev); 4735 struct pci_dev *pdev = tp->pci_dev; 4736 unsigned long irqflags; 4737 int retval = -ENOMEM; 4738 4739 pm_runtime_get_sync(&pdev->dev); 4740 4741 /* 4742 * Rx and Tx descriptors needs 256 bytes alignment. 4743 * dma_alloc_coherent provides more. 4744 */ 4745 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4746 &tp->TxPhyAddr, GFP_KERNEL); 4747 if (!tp->TxDescArray) 4748 goto out; 4749 4750 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4751 &tp->RxPhyAddr, GFP_KERNEL); 4752 if (!tp->RxDescArray) 4753 goto err_free_tx_0; 4754 4755 retval = rtl8169_init_ring(tp); 4756 if (retval < 0) 4757 goto err_free_rx_1; 4758 4759 rtl_request_firmware(tp); 4760 4761 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4762 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt, 4763 irqflags, dev->name, tp); 4764 if (retval < 0) 4765 goto err_release_fw_2; 4766 4767 retval = r8169_phy_connect(tp); 4768 if (retval) 4769 goto err_free_irq; 4770 4771 rtl8169_up(tp); 4772 rtl8169_init_counter_offsets(tp); 4773 netif_start_queue(dev); 4774 out: 4775 pm_runtime_put_sync(&pdev->dev); 4776 4777 return retval; 4778 4779 err_free_irq: 4780 free_irq(pci_irq_vector(pdev, 0), tp); 4781 err_release_fw_2: 4782 rtl_release_firmware(tp); 4783 rtl8169_rx_clear(tp); 4784 err_free_rx_1: 4785 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4786 tp->RxPhyAddr); 4787 tp->RxDescArray = NULL; 4788 err_free_tx_0: 4789 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4790 tp->TxPhyAddr); 4791 tp->TxDescArray = NULL; 4792 goto out; 4793 } 4794 4795 static void 4796 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4797 { 4798 struct rtl8169_private *tp = netdev_priv(dev); 4799 struct pci_dev *pdev = tp->pci_dev; 4800 struct rtl8169_counters *counters = tp->counters; 4801 4802 pm_runtime_get_noresume(&pdev->dev); 4803 4804 netdev_stats_to_stats64(stats, &dev->stats); 4805 dev_fetch_sw_netstats(stats, dev->tstats); 4806 4807 /* 4808 * Fetch additional counter values missing in stats collected by driver 4809 * from tally counters. 4810 */ 4811 if (pm_runtime_active(&pdev->dev)) 4812 rtl8169_update_counters(tp); 4813 4814 /* 4815 * Subtract values fetched during initalization. 4816 * See rtl8169_init_counter_offsets for a description why we do that. 4817 */ 4818 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4819 le64_to_cpu(tp->tc_offset.tx_errors); 4820 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4821 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4822 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4823 le16_to_cpu(tp->tc_offset.tx_aborted); 4824 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4825 le16_to_cpu(tp->tc_offset.rx_missed); 4826 4827 pm_runtime_put_noidle(&pdev->dev); 4828 } 4829 4830 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4831 { 4832 netif_device_detach(tp->dev); 4833 4834 if (netif_running(tp->dev)) 4835 rtl8169_down(tp); 4836 } 4837 4838 #ifdef CONFIG_PM 4839 4840 static int rtl8169_runtime_resume(struct device *dev) 4841 { 4842 struct rtl8169_private *tp = dev_get_drvdata(dev); 4843 4844 rtl_rar_set(tp, tp->dev->dev_addr); 4845 __rtl8169_set_wol(tp, tp->saved_wolopts); 4846 4847 if (tp->TxDescArray) 4848 rtl8169_up(tp); 4849 4850 netif_device_attach(tp->dev); 4851 4852 return 0; 4853 } 4854 4855 static int __maybe_unused rtl8169_suspend(struct device *device) 4856 { 4857 struct rtl8169_private *tp = dev_get_drvdata(device); 4858 4859 rtnl_lock(); 4860 rtl8169_net_suspend(tp); 4861 if (!device_may_wakeup(tp_to_dev(tp))) 4862 clk_disable_unprepare(tp->clk); 4863 rtnl_unlock(); 4864 4865 return 0; 4866 } 4867 4868 static int __maybe_unused rtl8169_resume(struct device *device) 4869 { 4870 struct rtl8169_private *tp = dev_get_drvdata(device); 4871 4872 if (!device_may_wakeup(tp_to_dev(tp))) 4873 clk_prepare_enable(tp->clk); 4874 4875 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4876 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4877 rtl_init_rxcfg(tp); 4878 4879 return rtl8169_runtime_resume(device); 4880 } 4881 4882 static int rtl8169_runtime_suspend(struct device *device) 4883 { 4884 struct rtl8169_private *tp = dev_get_drvdata(device); 4885 4886 if (!tp->TxDescArray) { 4887 netif_device_detach(tp->dev); 4888 return 0; 4889 } 4890 4891 rtnl_lock(); 4892 __rtl8169_set_wol(tp, WAKE_PHY); 4893 rtl8169_net_suspend(tp); 4894 rtnl_unlock(); 4895 4896 return 0; 4897 } 4898 4899 static int rtl8169_runtime_idle(struct device *device) 4900 { 4901 struct rtl8169_private *tp = dev_get_drvdata(device); 4902 4903 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4904 pm_schedule_suspend(device, 10000); 4905 4906 return -EBUSY; 4907 } 4908 4909 static const struct dev_pm_ops rtl8169_pm_ops = { 4910 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4911 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4912 rtl8169_runtime_idle) 4913 }; 4914 4915 #endif /* CONFIG_PM */ 4916 4917 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4918 { 4919 /* WoL fails with 8168b when the receiver is disabled. */ 4920 switch (tp->mac_version) { 4921 case RTL_GIGA_MAC_VER_11: 4922 case RTL_GIGA_MAC_VER_12: 4923 case RTL_GIGA_MAC_VER_17: 4924 pci_clear_master(tp->pci_dev); 4925 4926 RTL_W8(tp, ChipCmd, CmdRxEnb); 4927 rtl_pci_commit(tp); 4928 break; 4929 default: 4930 break; 4931 } 4932 } 4933 4934 static void rtl_shutdown(struct pci_dev *pdev) 4935 { 4936 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4937 4938 rtnl_lock(); 4939 rtl8169_net_suspend(tp); 4940 rtnl_unlock(); 4941 4942 /* Restore original MAC address */ 4943 rtl_rar_set(tp, tp->dev->perm_addr); 4944 4945 if (system_state == SYSTEM_POWER_OFF) { 4946 if (tp->saved_wolopts) 4947 rtl_wol_shutdown_quirk(tp); 4948 4949 pci_wake_from_d3(pdev, tp->saved_wolopts); 4950 pci_set_power_state(pdev, PCI_D3hot); 4951 } 4952 } 4953 4954 static void rtl_remove_one(struct pci_dev *pdev) 4955 { 4956 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4957 4958 if (pci_dev_run_wake(pdev)) 4959 pm_runtime_get_noresume(&pdev->dev); 4960 4961 unregister_netdev(tp->dev); 4962 4963 if (tp->dash_type != RTL_DASH_NONE) 4964 rtl8168_driver_stop(tp); 4965 4966 rtl_release_firmware(tp); 4967 4968 /* restore original MAC address */ 4969 rtl_rar_set(tp, tp->dev->perm_addr); 4970 } 4971 4972 static const struct net_device_ops rtl_netdev_ops = { 4973 .ndo_open = rtl_open, 4974 .ndo_stop = rtl8169_close, 4975 .ndo_get_stats64 = rtl8169_get_stats64, 4976 .ndo_start_xmit = rtl8169_start_xmit, 4977 .ndo_features_check = rtl8169_features_check, 4978 .ndo_tx_timeout = rtl8169_tx_timeout, 4979 .ndo_validate_addr = eth_validate_addr, 4980 .ndo_change_mtu = rtl8169_change_mtu, 4981 .ndo_fix_features = rtl8169_fix_features, 4982 .ndo_set_features = rtl8169_set_features, 4983 .ndo_set_mac_address = rtl_set_mac_address, 4984 .ndo_do_ioctl = phy_do_ioctl_running, 4985 .ndo_set_rx_mode = rtl_set_rx_mode, 4986 #ifdef CONFIG_NET_POLL_CONTROLLER 4987 .ndo_poll_controller = rtl8169_netpoll, 4988 #endif 4989 4990 }; 4991 4992 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4993 { 4994 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4995 4996 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4997 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4998 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4999 /* special workaround needed */ 5000 tp->irq_mask |= RxFIFOOver; 5001 else 5002 tp->irq_mask |= RxOverflow; 5003 } 5004 5005 static int rtl_alloc_irq(struct rtl8169_private *tp) 5006 { 5007 unsigned int flags; 5008 5009 switch (tp->mac_version) { 5010 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5011 rtl_unlock_config_regs(tp); 5012 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5013 rtl_lock_config_regs(tp); 5014 fallthrough; 5015 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5016 flags = PCI_IRQ_LEGACY; 5017 break; 5018 default: 5019 flags = PCI_IRQ_ALL_TYPES; 5020 break; 5021 } 5022 5023 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5024 } 5025 5026 static void rtl_read_mac_address(struct rtl8169_private *tp, 5027 u8 mac_addr[ETH_ALEN]) 5028 { 5029 /* Get MAC address */ 5030 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5031 u32 value; 5032 5033 value = rtl_eri_read(tp, 0xe0); 5034 put_unaligned_le32(value, mac_addr); 5035 value = rtl_eri_read(tp, 0xe4); 5036 put_unaligned_le16(value, mac_addr + 4); 5037 } else if (rtl_is_8125(tp)) { 5038 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5039 } 5040 } 5041 5042 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5043 { 5044 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5045 } 5046 5047 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5048 { 5049 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5050 } 5051 5052 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5053 { 5054 struct rtl8169_private *tp = mii_bus->priv; 5055 5056 if (phyaddr > 0) 5057 return -ENODEV; 5058 5059 return rtl_readphy(tp, phyreg); 5060 } 5061 5062 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5063 int phyreg, u16 val) 5064 { 5065 struct rtl8169_private *tp = mii_bus->priv; 5066 5067 if (phyaddr > 0) 5068 return -ENODEV; 5069 5070 rtl_writephy(tp, phyreg, val); 5071 5072 return 0; 5073 } 5074 5075 static int r8169_mdio_register(struct rtl8169_private *tp) 5076 { 5077 struct pci_dev *pdev = tp->pci_dev; 5078 struct mii_bus *new_bus; 5079 int ret; 5080 5081 new_bus = devm_mdiobus_alloc(&pdev->dev); 5082 if (!new_bus) 5083 return -ENOMEM; 5084 5085 new_bus->name = "r8169"; 5086 new_bus->priv = tp; 5087 new_bus->parent = &pdev->dev; 5088 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5089 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5090 5091 new_bus->read = r8169_mdio_read_reg; 5092 new_bus->write = r8169_mdio_write_reg; 5093 5094 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5095 if (ret) 5096 return ret; 5097 5098 tp->phydev = mdiobus_get_phy(new_bus, 0); 5099 if (!tp->phydev) { 5100 return -ENODEV; 5101 } else if (!tp->phydev->drv) { 5102 /* Most chip versions fail with the genphy driver. 5103 * Therefore ensure that the dedicated PHY driver is loaded. 5104 */ 5105 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5106 tp->phydev->phy_id); 5107 return -EUNATCH; 5108 } 5109 5110 tp->phydev->mac_managed_pm = 1; 5111 5112 phy_support_asym_pause(tp->phydev); 5113 5114 /* PHY will be woken up in rtl_open() */ 5115 phy_suspend(tp->phydev); 5116 5117 return 0; 5118 } 5119 5120 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5121 { 5122 rtl_enable_rxdvgate(tp); 5123 5124 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5125 msleep(1); 5126 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5127 5128 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5129 r8168g_wait_ll_share_fifo_ready(tp); 5130 5131 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5132 r8168g_wait_ll_share_fifo_ready(tp); 5133 } 5134 5135 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5136 { 5137 rtl_enable_rxdvgate(tp); 5138 5139 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5140 msleep(1); 5141 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5142 5143 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5144 r8168g_wait_ll_share_fifo_ready(tp); 5145 5146 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5147 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5148 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5149 r8168g_wait_ll_share_fifo_ready(tp); 5150 } 5151 5152 static void rtl_hw_initialize(struct rtl8169_private *tp) 5153 { 5154 switch (tp->mac_version) { 5155 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53: 5156 rtl8168ep_stop_cmac(tp); 5157 fallthrough; 5158 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5159 rtl_hw_init_8168g(tp); 5160 break; 5161 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63: 5162 rtl_hw_init_8125(tp); 5163 break; 5164 default: 5165 break; 5166 } 5167 } 5168 5169 static int rtl_jumbo_max(struct rtl8169_private *tp) 5170 { 5171 /* Non-GBit versions don't support jumbo frames */ 5172 if (!tp->supports_gmii) 5173 return 0; 5174 5175 switch (tp->mac_version) { 5176 /* RTL8169 */ 5177 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5178 return JUMBO_7K; 5179 /* RTL8168b */ 5180 case RTL_GIGA_MAC_VER_11: 5181 case RTL_GIGA_MAC_VER_12: 5182 case RTL_GIGA_MAC_VER_17: 5183 return JUMBO_4K; 5184 /* RTL8168c */ 5185 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5186 return JUMBO_6K; 5187 default: 5188 return JUMBO_9K; 5189 } 5190 } 5191 5192 static void rtl_disable_clk(void *data) 5193 { 5194 clk_disable_unprepare(data); 5195 } 5196 5197 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5198 { 5199 struct device *d = tp_to_dev(tp); 5200 struct clk *clk; 5201 int rc; 5202 5203 clk = devm_clk_get(d, "ether_clk"); 5204 if (IS_ERR(clk)) { 5205 rc = PTR_ERR(clk); 5206 if (rc == -ENOENT) 5207 /* clk-core allows NULL (for suspend / resume) */ 5208 rc = 0; 5209 else 5210 dev_err_probe(d, rc, "failed to get clk\n"); 5211 } else { 5212 tp->clk = clk; 5213 rc = clk_prepare_enable(clk); 5214 if (rc) 5215 dev_err(d, "failed to enable clk: %d\n", rc); 5216 else 5217 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5218 } 5219 5220 return rc; 5221 } 5222 5223 static void rtl_init_mac_address(struct rtl8169_private *tp) 5224 { 5225 struct net_device *dev = tp->dev; 5226 u8 *mac_addr = dev->dev_addr; 5227 int rc; 5228 5229 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5230 if (!rc) 5231 goto done; 5232 5233 rtl_read_mac_address(tp, mac_addr); 5234 if (is_valid_ether_addr(mac_addr)) 5235 goto done; 5236 5237 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5238 if (is_valid_ether_addr(mac_addr)) 5239 goto done; 5240 5241 eth_hw_addr_random(dev); 5242 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5243 done: 5244 rtl_rar_set(tp, mac_addr); 5245 } 5246 5247 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5248 { 5249 struct rtl8169_private *tp; 5250 int jumbo_max, region, rc; 5251 enum mac_version chipset; 5252 struct net_device *dev; 5253 u16 xid; 5254 5255 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5256 if (!dev) 5257 return -ENOMEM; 5258 5259 SET_NETDEV_DEV(dev, &pdev->dev); 5260 dev->netdev_ops = &rtl_netdev_ops; 5261 tp = netdev_priv(dev); 5262 tp->dev = dev; 5263 tp->pci_dev = pdev; 5264 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5265 tp->eee_adv = -1; 5266 tp->ocp_base = OCP_STD_PHY_BASE; 5267 5268 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5269 struct pcpu_sw_netstats); 5270 if (!dev->tstats) 5271 return -ENOMEM; 5272 5273 /* Get the *optional* external "ether_clk" used on some boards */ 5274 rc = rtl_get_ether_clk(tp); 5275 if (rc) 5276 return rc; 5277 5278 /* Disable ASPM completely as that cause random device stop working 5279 * problems as well as full system hangs for some PCIe devices users. 5280 */ 5281 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5282 PCIE_LINK_STATE_L1); 5283 tp->aspm_manageable = !rc; 5284 5285 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5286 rc = pcim_enable_device(pdev); 5287 if (rc < 0) { 5288 dev_err(&pdev->dev, "enable failure\n"); 5289 return rc; 5290 } 5291 5292 if (pcim_set_mwi(pdev) < 0) 5293 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5294 5295 /* use first MMIO region */ 5296 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5297 if (region < 0) { 5298 dev_err(&pdev->dev, "no MMIO resource found\n"); 5299 return -ENODEV; 5300 } 5301 5302 /* check for weird/broken PCI region reporting */ 5303 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5304 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5305 return -ENODEV; 5306 } 5307 5308 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5309 if (rc < 0) { 5310 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5311 return rc; 5312 } 5313 5314 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5315 5316 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5317 5318 /* Identify chip attached to board */ 5319 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5320 if (chipset == RTL_GIGA_MAC_NONE) { 5321 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5322 return -ENODEV; 5323 } 5324 5325 tp->mac_version = chipset; 5326 5327 tp->dash_type = rtl_check_dash(tp); 5328 5329 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5330 5331 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5332 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5333 dev->features |= NETIF_F_HIGHDMA; 5334 5335 rtl_init_rxcfg(tp); 5336 5337 rtl8169_irq_mask_and_ack(tp); 5338 5339 rtl_hw_initialize(tp); 5340 5341 rtl_hw_reset(tp); 5342 5343 rc = rtl_alloc_irq(tp); 5344 if (rc < 0) { 5345 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5346 return rc; 5347 } 5348 5349 INIT_WORK(&tp->wk.work, rtl_task); 5350 5351 rtl_init_mac_address(tp); 5352 5353 dev->ethtool_ops = &rtl8169_ethtool_ops; 5354 5355 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5356 5357 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5358 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5359 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5360 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5361 5362 /* 5363 * Pretend we are using VLANs; This bypasses a nasty bug where 5364 * Interrupts stop flowing on high load on 8110SCd controllers. 5365 */ 5366 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5367 /* Disallow toggling */ 5368 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5369 5370 if (rtl_chip_supports_csum_v2(tp)) 5371 dev->hw_features |= NETIF_F_IPV6_CSUM; 5372 5373 dev->features |= dev->hw_features; 5374 5375 /* There has been a number of reports that using SG/TSO results in 5376 * tx timeouts. However for a lot of people SG/TSO works fine. 5377 * Therefore disable both features by default, but allow users to 5378 * enable them. Use at own risk! 5379 */ 5380 if (rtl_chip_supports_csum_v2(tp)) { 5381 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5382 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5383 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5384 } else { 5385 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5386 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5387 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5388 } 5389 5390 dev->hw_features |= NETIF_F_RXALL; 5391 dev->hw_features |= NETIF_F_RXFCS; 5392 5393 /* configure chip for default features */ 5394 rtl8169_set_features(dev, dev->features); 5395 5396 rtl_set_d3_pll_down(tp, true); 5397 5398 jumbo_max = rtl_jumbo_max(tp); 5399 if (jumbo_max) 5400 dev->max_mtu = jumbo_max; 5401 5402 rtl_set_irq_mask(tp); 5403 5404 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5405 5406 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5407 &tp->counters_phys_addr, 5408 GFP_KERNEL); 5409 if (!tp->counters) 5410 return -ENOMEM; 5411 5412 pci_set_drvdata(pdev, tp); 5413 5414 rc = r8169_mdio_register(tp); 5415 if (rc) 5416 return rc; 5417 5418 rc = register_netdev(dev); 5419 if (rc) 5420 return rc; 5421 5422 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5423 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5424 pci_irq_vector(pdev, 0)); 5425 5426 if (jumbo_max) 5427 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5428 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5429 "ok" : "ko"); 5430 5431 if (tp->dash_type != RTL_DASH_NONE) { 5432 netdev_info(dev, "DASH enabled\n"); 5433 rtl8168_driver_start(tp); 5434 } 5435 5436 if (pci_dev_run_wake(pdev)) 5437 pm_runtime_put_sync(&pdev->dev); 5438 5439 return 0; 5440 } 5441 5442 static struct pci_driver rtl8169_pci_driver = { 5443 .name = MODULENAME, 5444 .id_table = rtl8169_pci_tbl, 5445 .probe = rtl_init_one, 5446 .remove = rtl_remove_one, 5447 .shutdown = rtl_shutdown, 5448 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5449 }; 5450 5451 module_pci_driver(rtl8169_pci_driver); 5452