1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/pci.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/ethtool.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/crc32.h> 23 #include <linux/in.h> 24 #include <linux/io.h> 25 #include <linux/ip.h> 26 #include <linux/tcp.h> 27 #include <linux/interrupt.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/prefetch.h> 31 #include <linux/pci-aspm.h> 32 #include <linux/ipv6.h> 33 #include <net/ip6_checksum.h> 34 35 #include "r8169_firmware.h" 36 37 #define MODULENAME "r8169" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 58 59 #define R8169_MSG_DEFAULT \ 60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) 61 62 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 63 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 64 #define MC_FILTER_LIMIT 32 65 66 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 68 69 #define R8169_REGS_SIZE 256 70 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 72 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 73 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 74 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 enum mac_version { 87 /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */ 88 RTL_GIGA_MAC_VER_02, 89 RTL_GIGA_MAC_VER_03, 90 RTL_GIGA_MAC_VER_04, 91 RTL_GIGA_MAC_VER_05, 92 RTL_GIGA_MAC_VER_06, 93 RTL_GIGA_MAC_VER_07, 94 RTL_GIGA_MAC_VER_08, 95 RTL_GIGA_MAC_VER_09, 96 RTL_GIGA_MAC_VER_10, 97 RTL_GIGA_MAC_VER_11, 98 RTL_GIGA_MAC_VER_12, 99 RTL_GIGA_MAC_VER_13, 100 RTL_GIGA_MAC_VER_14, 101 RTL_GIGA_MAC_VER_15, 102 RTL_GIGA_MAC_VER_16, 103 RTL_GIGA_MAC_VER_17, 104 RTL_GIGA_MAC_VER_18, 105 RTL_GIGA_MAC_VER_19, 106 RTL_GIGA_MAC_VER_20, 107 RTL_GIGA_MAC_VER_21, 108 RTL_GIGA_MAC_VER_22, 109 RTL_GIGA_MAC_VER_23, 110 RTL_GIGA_MAC_VER_24, 111 RTL_GIGA_MAC_VER_25, 112 RTL_GIGA_MAC_VER_26, 113 RTL_GIGA_MAC_VER_27, 114 RTL_GIGA_MAC_VER_28, 115 RTL_GIGA_MAC_VER_29, 116 RTL_GIGA_MAC_VER_30, 117 RTL_GIGA_MAC_VER_31, 118 RTL_GIGA_MAC_VER_32, 119 RTL_GIGA_MAC_VER_33, 120 RTL_GIGA_MAC_VER_34, 121 RTL_GIGA_MAC_VER_35, 122 RTL_GIGA_MAC_VER_36, 123 RTL_GIGA_MAC_VER_37, 124 RTL_GIGA_MAC_VER_38, 125 RTL_GIGA_MAC_VER_39, 126 RTL_GIGA_MAC_VER_40, 127 RTL_GIGA_MAC_VER_41, 128 RTL_GIGA_MAC_VER_42, 129 RTL_GIGA_MAC_VER_43, 130 RTL_GIGA_MAC_VER_44, 131 RTL_GIGA_MAC_VER_45, 132 RTL_GIGA_MAC_VER_46, 133 RTL_GIGA_MAC_VER_47, 134 RTL_GIGA_MAC_VER_48, 135 RTL_GIGA_MAC_VER_49, 136 RTL_GIGA_MAC_VER_50, 137 RTL_GIGA_MAC_VER_51, 138 RTL_GIGA_MAC_NONE 139 }; 140 141 #define JUMBO_1K ETH_DATA_LEN 142 #define JUMBO_4K (4*1024 - ETH_HLEN - 2) 143 #define JUMBO_6K (6*1024 - ETH_HLEN - 2) 144 #define JUMBO_7K (7*1024 - ETH_HLEN - 2) 145 #define JUMBO_9K (9*1024 - ETH_HLEN - 2) 146 147 static const struct { 148 const char *name; 149 const char *fw_name; 150 } rtl_chip_infos[] = { 151 /* PCI devices. */ 152 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 153 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 154 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 155 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 156 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 157 /* PCI-E devices. */ 158 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 159 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 160 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 161 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 162 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 163 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 164 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 165 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 166 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 167 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 168 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 169 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 170 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 171 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 172 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 173 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 174 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 175 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 176 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 177 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 178 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 179 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 180 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 181 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 182 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 183 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 184 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 185 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 186 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 187 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 188 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 189 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 190 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 191 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 192 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 193 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 194 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 195 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 196 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 197 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 198 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 199 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 200 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 201 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 202 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 203 }; 204 205 static const struct pci_device_id rtl8169_pci_tbl[] = { 206 { PCI_VDEVICE(REALTEK, 0x2502) }, 207 { PCI_VDEVICE(REALTEK, 0x2600) }, 208 { PCI_VDEVICE(REALTEK, 0x8129) }, 209 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 210 { PCI_VDEVICE(REALTEK, 0x8161) }, 211 { PCI_VDEVICE(REALTEK, 0x8167) }, 212 { PCI_VDEVICE(REALTEK, 0x8168) }, 213 { PCI_VDEVICE(NCUBE, 0x8168) }, 214 { PCI_VDEVICE(REALTEK, 0x8169) }, 215 { PCI_VENDOR_ID_DLINK, 0x4300, 216 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 217 { PCI_VDEVICE(DLINK, 0x4300) }, 218 { PCI_VDEVICE(DLINK, 0x4302) }, 219 { PCI_VDEVICE(AT, 0xc107) }, 220 { PCI_VDEVICE(USR, 0x0116) }, 221 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 222 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 223 {} 224 }; 225 226 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 227 228 static struct { 229 u32 msg_enable; 230 } debug = { -1 }; 231 232 enum rtl_registers { 233 MAC0 = 0, /* Ethernet hardware address. */ 234 MAC4 = 4, 235 MAR0 = 8, /* Multicast filter. */ 236 CounterAddrLow = 0x10, 237 CounterAddrHigh = 0x14, 238 TxDescStartAddrLow = 0x20, 239 TxDescStartAddrHigh = 0x24, 240 TxHDescStartAddrLow = 0x28, 241 TxHDescStartAddrHigh = 0x2c, 242 FLASH = 0x30, 243 ERSR = 0x36, 244 ChipCmd = 0x37, 245 TxPoll = 0x38, 246 IntrMask = 0x3c, 247 IntrStatus = 0x3e, 248 249 TxConfig = 0x40, 250 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 251 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 252 253 RxConfig = 0x44, 254 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 255 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 256 #define RXCFG_FIFO_SHIFT 13 257 /* No threshold before first PCI xfer */ 258 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 259 #define RX_EARLY_OFF (1 << 11) 260 #define RXCFG_DMA_SHIFT 8 261 /* Unlimited maximum PCI burst. */ 262 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 263 264 RxMissed = 0x4c, 265 Cfg9346 = 0x50, 266 Config0 = 0x51, 267 Config1 = 0x52, 268 Config2 = 0x53, 269 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 270 271 Config3 = 0x54, 272 Config4 = 0x55, 273 Config5 = 0x56, 274 PHYAR = 0x60, 275 PHYstatus = 0x6c, 276 RxMaxSize = 0xda, 277 CPlusCmd = 0xe0, 278 IntrMitigate = 0xe2, 279 280 #define RTL_COALESCE_MASK 0x0f 281 #define RTL_COALESCE_SHIFT 4 282 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK) 283 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2) 284 285 RxDescAddrLow = 0xe4, 286 RxDescAddrHigh = 0xe8, 287 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 288 289 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 290 291 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 292 293 #define TxPacketMax (8064 >> 7) 294 #define EarlySize 0x27 295 296 FuncEvent = 0xf0, 297 FuncEventMask = 0xf4, 298 FuncPresetState = 0xf8, 299 IBCR0 = 0xf8, 300 IBCR2 = 0xf9, 301 IBIMR0 = 0xfa, 302 IBISR0 = 0xfb, 303 FuncForceEvent = 0xfc, 304 }; 305 306 enum rtl8168_8101_registers { 307 CSIDR = 0x64, 308 CSIAR = 0x68, 309 #define CSIAR_FLAG 0x80000000 310 #define CSIAR_WRITE_CMD 0x80000000 311 #define CSIAR_BYTE_ENABLE 0x0000f000 312 #define CSIAR_ADDR_MASK 0x00000fff 313 PMCH = 0x6f, 314 EPHYAR = 0x80, 315 #define EPHYAR_FLAG 0x80000000 316 #define EPHYAR_WRITE_CMD 0x80000000 317 #define EPHYAR_REG_MASK 0x1f 318 #define EPHYAR_REG_SHIFT 16 319 #define EPHYAR_DATA_MASK 0xffff 320 DLLPR = 0xd0, 321 #define PFM_EN (1 << 6) 322 #define TX_10M_PS_EN (1 << 7) 323 DBG_REG = 0xd1, 324 #define FIX_NAK_1 (1 << 4) 325 #define FIX_NAK_2 (1 << 3) 326 TWSI = 0xd2, 327 MCU = 0xd3, 328 #define NOW_IS_OOB (1 << 7) 329 #define TX_EMPTY (1 << 5) 330 #define RX_EMPTY (1 << 4) 331 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 332 #define EN_NDP (1 << 3) 333 #define EN_OOB_RESET (1 << 2) 334 #define LINK_LIST_RDY (1 << 1) 335 EFUSEAR = 0xdc, 336 #define EFUSEAR_FLAG 0x80000000 337 #define EFUSEAR_WRITE_CMD 0x80000000 338 #define EFUSEAR_READ_CMD 0x00000000 339 #define EFUSEAR_REG_MASK 0x03ff 340 #define EFUSEAR_REG_SHIFT 8 341 #define EFUSEAR_DATA_MASK 0xff 342 MISC_1 = 0xf2, 343 #define PFM_D3COLD_EN (1 << 6) 344 }; 345 346 enum rtl8168_registers { 347 LED_FREQ = 0x1a, 348 EEE_LED = 0x1b, 349 ERIDR = 0x70, 350 ERIAR = 0x74, 351 #define ERIAR_FLAG 0x80000000 352 #define ERIAR_WRITE_CMD 0x80000000 353 #define ERIAR_READ_CMD 0x00000000 354 #define ERIAR_ADDR_BYTE_ALIGN 4 355 #define ERIAR_TYPE_SHIFT 16 356 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 357 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 358 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 359 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 360 #define ERIAR_MASK_SHIFT 12 361 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 362 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 363 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 364 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 365 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 366 EPHY_RXER_NUM = 0x7c, 367 OCPDR = 0xb0, /* OCP GPHY access */ 368 #define OCPDR_WRITE_CMD 0x80000000 369 #define OCPDR_READ_CMD 0x00000000 370 #define OCPDR_REG_MASK 0x7f 371 #define OCPDR_GPHY_REG_SHIFT 16 372 #define OCPDR_DATA_MASK 0xffff 373 OCPAR = 0xb4, 374 #define OCPAR_FLAG 0x80000000 375 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 376 #define OCPAR_GPHY_READ_CMD 0x0000f060 377 GPHY_OCP = 0xb8, 378 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 379 MISC = 0xf0, /* 8168e only. */ 380 #define TXPLA_RST (1 << 29) 381 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 382 #define PWM_EN (1 << 22) 383 #define RXDV_GATED_EN (1 << 19) 384 #define EARLY_TALLY_EN (1 << 16) 385 }; 386 387 enum rtl_register_content { 388 /* InterruptStatusBits */ 389 SYSErr = 0x8000, 390 PCSTimeout = 0x4000, 391 SWInt = 0x0100, 392 TxDescUnavail = 0x0080, 393 RxFIFOOver = 0x0040, 394 LinkChg = 0x0020, 395 RxOverflow = 0x0010, 396 TxErr = 0x0008, 397 TxOK = 0x0004, 398 RxErr = 0x0002, 399 RxOK = 0x0001, 400 401 /* RxStatusDesc */ 402 RxRWT = (1 << 22), 403 RxRES = (1 << 21), 404 RxRUNT = (1 << 20), 405 RxCRC = (1 << 19), 406 407 /* ChipCmdBits */ 408 StopReq = 0x80, 409 CmdReset = 0x10, 410 CmdRxEnb = 0x08, 411 CmdTxEnb = 0x04, 412 RxBufEmpty = 0x01, 413 414 /* TXPoll register p.5 */ 415 HPQ = 0x80, /* Poll cmd on the high prio queue */ 416 NPQ = 0x40, /* Poll cmd on the low prio queue */ 417 FSWInt = 0x01, /* Forced software interrupt */ 418 419 /* Cfg9346Bits */ 420 Cfg9346_Lock = 0x00, 421 Cfg9346_Unlock = 0xc0, 422 423 /* rx_mode_bits */ 424 AcceptErr = 0x20, 425 AcceptRunt = 0x10, 426 AcceptBroadcast = 0x08, 427 AcceptMulticast = 0x04, 428 AcceptMyPhys = 0x02, 429 AcceptAllPhys = 0x01, 430 #define RX_CONFIG_ACCEPT_MASK 0x3f 431 432 /* TxConfigBits */ 433 TxInterFrameGapShift = 24, 434 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 435 436 /* Config1 register p.24 */ 437 LEDS1 = (1 << 7), 438 LEDS0 = (1 << 6), 439 Speed_down = (1 << 4), 440 MEMMAP = (1 << 3), 441 IOMAP = (1 << 2), 442 VPD = (1 << 1), 443 PMEnable = (1 << 0), /* Power Management Enable */ 444 445 /* Config2 register p. 25 */ 446 ClkReqEn = (1 << 7), /* Clock Request Enable */ 447 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 448 PCI_Clock_66MHz = 0x01, 449 PCI_Clock_33MHz = 0x00, 450 451 /* Config3 register p.25 */ 452 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 453 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 454 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 455 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 456 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 457 458 /* Config4 register */ 459 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 460 461 /* Config5 register p.27 */ 462 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 463 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 464 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 465 Spi_en = (1 << 3), 466 LanWake = (1 << 1), /* LanWake enable/disable */ 467 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 468 ASPM_en = (1 << 0), /* ASPM enable */ 469 470 /* CPlusCmd p.31 */ 471 EnableBist = (1 << 15), // 8168 8101 472 Mac_dbgo_oe = (1 << 14), // 8168 8101 473 Normal_mode = (1 << 13), // unused 474 Force_half_dup = (1 << 12), // 8168 8101 475 Force_rxflow_en = (1 << 11), // 8168 8101 476 Force_txflow_en = (1 << 10), // 8168 8101 477 Cxpl_dbg_sel = (1 << 9), // 8168 8101 478 ASF = (1 << 8), // 8168 8101 479 PktCntrDisable = (1 << 7), // 8168 8101 480 Mac_dbgo_sel = 0x001c, // 8168 481 RxVlan = (1 << 6), 482 RxChkSum = (1 << 5), 483 PCIDAC = (1 << 4), 484 PCIMulRW = (1 << 3), 485 #define INTT_MASK GENMASK(1, 0) 486 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 487 488 /* rtl8169_PHYstatus */ 489 TBI_Enable = 0x80, 490 TxFlowCtrl = 0x40, 491 RxFlowCtrl = 0x20, 492 _1000bpsF = 0x10, 493 _100bps = 0x08, 494 _10bps = 0x04, 495 LinkStatus = 0x02, 496 FullDup = 0x01, 497 498 /* ResetCounterCommand */ 499 CounterReset = 0x1, 500 501 /* DumpCounterCommand */ 502 CounterDump = 0x8, 503 504 /* magic enable v2 */ 505 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 506 }; 507 508 enum rtl_desc_bit { 509 /* First doubleword. */ 510 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 511 RingEnd = (1 << 30), /* End of descriptor ring */ 512 FirstFrag = (1 << 29), /* First segment of a packet */ 513 LastFrag = (1 << 28), /* Final segment of a packet */ 514 }; 515 516 /* Generic case. */ 517 enum rtl_tx_desc_bit { 518 /* First doubleword. */ 519 TD_LSO = (1 << 27), /* Large Send Offload */ 520 #define TD_MSS_MAX 0x07ffu /* MSS value */ 521 522 /* Second doubleword. */ 523 TxVlanTag = (1 << 17), /* Add VLAN tag */ 524 }; 525 526 /* 8169, 8168b and 810x except 8102e. */ 527 enum rtl_tx_desc_bit_0 { 528 /* First doubleword. */ 529 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 530 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 531 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 532 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 533 }; 534 535 /* 8102e, 8168c and beyond. */ 536 enum rtl_tx_desc_bit_1 { 537 /* First doubleword. */ 538 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 539 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 540 #define GTTCPHO_SHIFT 18 541 #define GTTCPHO_MAX 0x7f 542 543 /* Second doubleword. */ 544 #define TCPHO_SHIFT 18 545 #define TCPHO_MAX 0x3ff 546 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 547 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 548 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 549 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 550 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 551 }; 552 553 enum rtl_rx_desc_bit { 554 /* Rx private */ 555 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 556 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 557 558 #define RxProtoUDP (PID1) 559 #define RxProtoTCP (PID0) 560 #define RxProtoIP (PID1 | PID0) 561 #define RxProtoMask RxProtoIP 562 563 IPFail = (1 << 16), /* IP checksum failed */ 564 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 565 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 566 RxVlanTag = (1 << 16), /* VLAN tag available */ 567 }; 568 569 #define RsvdMask 0x3fffc000 570 571 #define RTL_GSO_MAX_SIZE_V1 32000 572 #define RTL_GSO_MAX_SEGS_V1 24 573 #define RTL_GSO_MAX_SIZE_V2 64000 574 #define RTL_GSO_MAX_SEGS_V2 64 575 576 struct TxDesc { 577 __le32 opts1; 578 __le32 opts2; 579 __le64 addr; 580 }; 581 582 struct RxDesc { 583 __le32 opts1; 584 __le32 opts2; 585 __le64 addr; 586 }; 587 588 struct ring_info { 589 struct sk_buff *skb; 590 u32 len; 591 }; 592 593 struct rtl8169_counters { 594 __le64 tx_packets; 595 __le64 rx_packets; 596 __le64 tx_errors; 597 __le32 rx_errors; 598 __le16 rx_missed; 599 __le16 align_errors; 600 __le32 tx_one_collision; 601 __le32 tx_multi_collision; 602 __le64 rx_unicast; 603 __le64 rx_broadcast; 604 __le32 rx_multicast; 605 __le16 tx_aborted; 606 __le16 tx_underun; 607 }; 608 609 struct rtl8169_tc_offsets { 610 bool inited; 611 __le64 tx_errors; 612 __le32 tx_multi_collision; 613 __le16 tx_aborted; 614 }; 615 616 enum rtl_flag { 617 RTL_FLAG_TASK_ENABLED = 0, 618 RTL_FLAG_TASK_RESET_PENDING, 619 RTL_FLAG_MAX 620 }; 621 622 struct rtl8169_stats { 623 u64 packets; 624 u64 bytes; 625 struct u64_stats_sync syncp; 626 }; 627 628 struct rtl8169_private { 629 void __iomem *mmio_addr; /* memory map physical address */ 630 struct pci_dev *pci_dev; 631 struct net_device *dev; 632 struct phy_device *phydev; 633 struct napi_struct napi; 634 u32 msg_enable; 635 enum mac_version mac_version; 636 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 637 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 638 u32 dirty_tx; 639 struct rtl8169_stats rx_stats; 640 struct rtl8169_stats tx_stats; 641 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 642 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 643 dma_addr_t TxPhyAddr; 644 dma_addr_t RxPhyAddr; 645 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 646 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 647 u16 cp_cmd; 648 u16 irq_mask; 649 struct clk *clk; 650 651 struct { 652 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 653 struct mutex mutex; 654 struct work_struct work; 655 } wk; 656 657 unsigned irq_enabled:1; 658 unsigned supports_gmii:1; 659 unsigned aspm_manageable:1; 660 dma_addr_t counters_phys_addr; 661 struct rtl8169_counters *counters; 662 struct rtl8169_tc_offsets tc_offset; 663 u32 saved_wolopts; 664 665 const char *fw_name; 666 struct rtl_fw *rtl_fw; 667 668 u32 ocp_base; 669 }; 670 671 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 672 673 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 674 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 675 module_param_named(debug, debug.msg_enable, int, 0); 676 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); 677 MODULE_SOFTDEP("pre: realtek"); 678 MODULE_LICENSE("GPL"); 679 MODULE_FIRMWARE(FIRMWARE_8168D_1); 680 MODULE_FIRMWARE(FIRMWARE_8168D_2); 681 MODULE_FIRMWARE(FIRMWARE_8168E_1); 682 MODULE_FIRMWARE(FIRMWARE_8168E_2); 683 MODULE_FIRMWARE(FIRMWARE_8168E_3); 684 MODULE_FIRMWARE(FIRMWARE_8105E_1); 685 MODULE_FIRMWARE(FIRMWARE_8168F_1); 686 MODULE_FIRMWARE(FIRMWARE_8168F_2); 687 MODULE_FIRMWARE(FIRMWARE_8402_1); 688 MODULE_FIRMWARE(FIRMWARE_8411_1); 689 MODULE_FIRMWARE(FIRMWARE_8411_2); 690 MODULE_FIRMWARE(FIRMWARE_8106E_1); 691 MODULE_FIRMWARE(FIRMWARE_8106E_2); 692 MODULE_FIRMWARE(FIRMWARE_8168G_2); 693 MODULE_FIRMWARE(FIRMWARE_8168G_3); 694 MODULE_FIRMWARE(FIRMWARE_8168H_1); 695 MODULE_FIRMWARE(FIRMWARE_8168H_2); 696 MODULE_FIRMWARE(FIRMWARE_8107E_1); 697 MODULE_FIRMWARE(FIRMWARE_8107E_2); 698 699 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 700 { 701 return &tp->pci_dev->dev; 702 } 703 704 static void rtl_lock_work(struct rtl8169_private *tp) 705 { 706 mutex_lock(&tp->wk.mutex); 707 } 708 709 static void rtl_unlock_work(struct rtl8169_private *tp) 710 { 711 mutex_unlock(&tp->wk.mutex); 712 } 713 714 static void rtl_lock_config_regs(struct rtl8169_private *tp) 715 { 716 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 717 } 718 719 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 720 { 721 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 722 } 723 724 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force) 725 { 726 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL, 727 PCI_EXP_DEVCTL_READRQ, force); 728 } 729 730 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 731 { 732 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 733 tp->mac_version != RTL_GIGA_MAC_VER_39; 734 } 735 736 struct rtl_cond { 737 bool (*check)(struct rtl8169_private *); 738 const char *msg; 739 }; 740 741 static void rtl_udelay(unsigned int d) 742 { 743 udelay(d); 744 } 745 746 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 747 void (*delay)(unsigned int), unsigned int d, int n, 748 bool high) 749 { 750 int i; 751 752 for (i = 0; i < n; i++) { 753 if (c->check(tp) == high) 754 return true; 755 delay(d); 756 } 757 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", 758 c->msg, !high, n, d); 759 return false; 760 } 761 762 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp, 763 const struct rtl_cond *c, 764 unsigned int d, int n) 765 { 766 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true); 767 } 768 769 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp, 770 const struct rtl_cond *c, 771 unsigned int d, int n) 772 { 773 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false); 774 } 775 776 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp, 777 const struct rtl_cond *c, 778 unsigned int d, int n) 779 { 780 return rtl_loop_wait(tp, c, msleep, d, n, true); 781 } 782 783 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp, 784 const struct rtl_cond *c, 785 unsigned int d, int n) 786 { 787 return rtl_loop_wait(tp, c, msleep, d, n, false); 788 } 789 790 #define DECLARE_RTL_COND(name) \ 791 static bool name ## _check(struct rtl8169_private *); \ 792 \ 793 static const struct rtl_cond name = { \ 794 .check = name ## _check, \ 795 .msg = #name \ 796 }; \ 797 \ 798 static bool name ## _check(struct rtl8169_private *tp) 799 800 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 801 { 802 if (reg & 0xffff0001) { 803 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg); 804 return true; 805 } 806 return false; 807 } 808 809 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 810 { 811 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 812 } 813 814 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 815 { 816 if (rtl_ocp_reg_failure(tp, reg)) 817 return; 818 819 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 820 821 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 822 } 823 824 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 825 { 826 if (rtl_ocp_reg_failure(tp, reg)) 827 return 0; 828 829 RTL_W32(tp, GPHY_OCP, reg << 15); 830 831 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 832 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 833 } 834 835 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 836 { 837 if (rtl_ocp_reg_failure(tp, reg)) 838 return; 839 840 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 841 } 842 843 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 844 { 845 if (rtl_ocp_reg_failure(tp, reg)) 846 return 0; 847 848 RTL_W32(tp, OCPDR, reg << 15); 849 850 return RTL_R32(tp, OCPDR); 851 } 852 853 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 854 u16 set) 855 { 856 u16 data = r8168_mac_ocp_read(tp, reg); 857 858 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 859 } 860 861 #define OCP_STD_PHY_BASE 0xa400 862 863 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 864 { 865 if (reg == 0x1f) { 866 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 867 return; 868 } 869 870 if (tp->ocp_base != OCP_STD_PHY_BASE) 871 reg -= 0x10; 872 873 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 874 } 875 876 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 877 { 878 if (tp->ocp_base != OCP_STD_PHY_BASE) 879 reg -= 0x10; 880 881 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 882 } 883 884 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 885 { 886 if (reg == 0x1f) { 887 tp->ocp_base = value << 4; 888 return; 889 } 890 891 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 892 } 893 894 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 895 { 896 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 897 } 898 899 DECLARE_RTL_COND(rtl_phyar_cond) 900 { 901 return RTL_R32(tp, PHYAR) & 0x80000000; 902 } 903 904 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 905 { 906 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 907 908 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 909 /* 910 * According to hardware specs a 20us delay is required after write 911 * complete indication, but before sending next command. 912 */ 913 udelay(20); 914 } 915 916 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 917 { 918 int value; 919 920 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 921 922 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 923 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 924 925 /* 926 * According to hardware specs a 20us delay is required after read 927 * complete indication, but before sending next command. 928 */ 929 udelay(20); 930 931 return value; 932 } 933 934 DECLARE_RTL_COND(rtl_ocpar_cond) 935 { 936 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 937 } 938 939 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 940 { 941 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 942 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 943 RTL_W32(tp, EPHY_RXER_NUM, 0); 944 945 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 946 } 947 948 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 949 { 950 r8168dp_1_mdio_access(tp, reg, 951 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 952 } 953 954 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 955 { 956 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 957 958 mdelay(1); 959 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 960 RTL_W32(tp, EPHY_RXER_NUM, 0); 961 962 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 963 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 964 } 965 966 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 967 968 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 969 { 970 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 971 } 972 973 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 974 { 975 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 976 } 977 978 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 979 { 980 r8168dp_2_mdio_start(tp); 981 982 r8169_mdio_write(tp, reg, value); 983 984 r8168dp_2_mdio_stop(tp); 985 } 986 987 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 988 { 989 int value; 990 991 r8168dp_2_mdio_start(tp); 992 993 value = r8169_mdio_read(tp, reg); 994 995 r8168dp_2_mdio_stop(tp); 996 997 return value; 998 } 999 1000 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1001 { 1002 switch (tp->mac_version) { 1003 case RTL_GIGA_MAC_VER_27: 1004 r8168dp_1_mdio_write(tp, location, val); 1005 break; 1006 case RTL_GIGA_MAC_VER_28: 1007 case RTL_GIGA_MAC_VER_31: 1008 r8168dp_2_mdio_write(tp, location, val); 1009 break; 1010 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 1011 r8168g_mdio_write(tp, location, val); 1012 break; 1013 default: 1014 r8169_mdio_write(tp, location, val); 1015 break; 1016 } 1017 } 1018 1019 static int rtl_readphy(struct rtl8169_private *tp, int location) 1020 { 1021 switch (tp->mac_version) { 1022 case RTL_GIGA_MAC_VER_27: 1023 return r8168dp_1_mdio_read(tp, location); 1024 case RTL_GIGA_MAC_VER_28: 1025 case RTL_GIGA_MAC_VER_31: 1026 return r8168dp_2_mdio_read(tp, location); 1027 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 1028 return r8168g_mdio_read(tp, location); 1029 default: 1030 return r8169_mdio_read(tp, location); 1031 } 1032 } 1033 1034 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) 1035 { 1036 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); 1037 } 1038 1039 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) 1040 { 1041 int val; 1042 1043 val = rtl_readphy(tp, reg_addr); 1044 rtl_writephy(tp, reg_addr, (val & ~m) | p); 1045 } 1046 1047 DECLARE_RTL_COND(rtl_ephyar_cond) 1048 { 1049 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1050 } 1051 1052 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1053 { 1054 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1055 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1056 1057 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1058 1059 udelay(10); 1060 } 1061 1062 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1063 { 1064 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1065 1066 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1067 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1068 } 1069 1070 DECLARE_RTL_COND(rtl_eriar_cond) 1071 { 1072 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1073 } 1074 1075 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1076 u32 val, int type) 1077 { 1078 BUG_ON((addr & 3) || (mask == 0)); 1079 RTL_W32(tp, ERIDR, val); 1080 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1081 1082 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1083 } 1084 1085 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1086 u32 val) 1087 { 1088 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1089 } 1090 1091 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1092 { 1093 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1094 1095 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1096 RTL_R32(tp, ERIDR) : ~0; 1097 } 1098 1099 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1100 { 1101 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1102 } 1103 1104 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1105 u32 m) 1106 { 1107 u32 val; 1108 1109 val = rtl_eri_read(tp, addr); 1110 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1111 } 1112 1113 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1114 u32 p) 1115 { 1116 rtl_w0w1_eri(tp, addr, mask, p, 0); 1117 } 1118 1119 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1120 u32 m) 1121 { 1122 rtl_w0w1_eri(tp, addr, mask, 0, m); 1123 } 1124 1125 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1126 { 1127 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1128 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1129 RTL_R32(tp, OCPDR) : ~0; 1130 } 1131 1132 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1133 { 1134 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1135 } 1136 1137 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1138 u32 data) 1139 { 1140 RTL_W32(tp, OCPDR, data); 1141 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1142 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1143 } 1144 1145 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1146 u32 data) 1147 { 1148 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1149 data, ERIAR_OOB); 1150 } 1151 1152 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1153 { 1154 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1155 1156 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1157 } 1158 1159 #define OOB_CMD_RESET 0x00 1160 #define OOB_CMD_DRIVER_START 0x05 1161 #define OOB_CMD_DRIVER_STOP 0x06 1162 1163 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1164 { 1165 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1166 } 1167 1168 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1169 { 1170 u16 reg; 1171 1172 reg = rtl8168_get_ocp_reg(tp); 1173 1174 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1175 } 1176 1177 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1178 { 1179 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1180 } 1181 1182 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1183 { 1184 return RTL_R8(tp, IBISR0) & 0x20; 1185 } 1186 1187 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1188 { 1189 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1190 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000); 1191 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1192 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1193 } 1194 1195 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1196 { 1197 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1198 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10); 1199 } 1200 1201 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1202 { 1203 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1204 r8168ep_ocp_write(tp, 0x01, 0x30, 1205 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1206 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10); 1207 } 1208 1209 static void rtl8168_driver_start(struct rtl8169_private *tp) 1210 { 1211 switch (tp->mac_version) { 1212 case RTL_GIGA_MAC_VER_27: 1213 case RTL_GIGA_MAC_VER_28: 1214 case RTL_GIGA_MAC_VER_31: 1215 rtl8168dp_driver_start(tp); 1216 break; 1217 case RTL_GIGA_MAC_VER_49: 1218 case RTL_GIGA_MAC_VER_50: 1219 case RTL_GIGA_MAC_VER_51: 1220 rtl8168ep_driver_start(tp); 1221 break; 1222 default: 1223 BUG(); 1224 break; 1225 } 1226 } 1227 1228 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1229 { 1230 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1231 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10); 1232 } 1233 1234 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1235 { 1236 rtl8168ep_stop_cmac(tp); 1237 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1238 r8168ep_ocp_write(tp, 0x01, 0x30, 1239 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1240 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10); 1241 } 1242 1243 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1244 { 1245 switch (tp->mac_version) { 1246 case RTL_GIGA_MAC_VER_27: 1247 case RTL_GIGA_MAC_VER_28: 1248 case RTL_GIGA_MAC_VER_31: 1249 rtl8168dp_driver_stop(tp); 1250 break; 1251 case RTL_GIGA_MAC_VER_49: 1252 case RTL_GIGA_MAC_VER_50: 1253 case RTL_GIGA_MAC_VER_51: 1254 rtl8168ep_driver_stop(tp); 1255 break; 1256 default: 1257 BUG(); 1258 break; 1259 } 1260 } 1261 1262 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1263 { 1264 u16 reg = rtl8168_get_ocp_reg(tp); 1265 1266 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1267 } 1268 1269 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1270 { 1271 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1272 } 1273 1274 static bool r8168_check_dash(struct rtl8169_private *tp) 1275 { 1276 switch (tp->mac_version) { 1277 case RTL_GIGA_MAC_VER_27: 1278 case RTL_GIGA_MAC_VER_28: 1279 case RTL_GIGA_MAC_VER_31: 1280 return r8168dp_check_dash(tp); 1281 case RTL_GIGA_MAC_VER_49: 1282 case RTL_GIGA_MAC_VER_50: 1283 case RTL_GIGA_MAC_VER_51: 1284 return r8168ep_check_dash(tp); 1285 default: 1286 return false; 1287 } 1288 } 1289 1290 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1291 { 1292 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1293 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1294 } 1295 1296 DECLARE_RTL_COND(rtl_efusear_cond) 1297 { 1298 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1299 } 1300 1301 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1302 { 1303 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1304 1305 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1306 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1307 } 1308 1309 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits) 1310 { 1311 RTL_W16(tp, IntrStatus, bits); 1312 } 1313 1314 static void rtl_irq_disable(struct rtl8169_private *tp) 1315 { 1316 RTL_W16(tp, IntrMask, 0); 1317 tp->irq_enabled = 0; 1318 } 1319 1320 #define RTL_EVENT_NAPI_RX (RxOK | RxErr) 1321 #define RTL_EVENT_NAPI_TX (TxOK | TxErr) 1322 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) 1323 1324 static void rtl_irq_enable(struct rtl8169_private *tp) 1325 { 1326 tp->irq_enabled = 1; 1327 RTL_W16(tp, IntrMask, tp->irq_mask); 1328 } 1329 1330 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1331 { 1332 rtl_irq_disable(tp); 1333 rtl_ack_events(tp, 0xffff); 1334 /* PCI commit */ 1335 RTL_R8(tp, ChipCmd); 1336 } 1337 1338 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1339 { 1340 struct net_device *dev = tp->dev; 1341 struct phy_device *phydev = tp->phydev; 1342 1343 if (!netif_running(dev)) 1344 return; 1345 1346 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1347 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1348 if (phydev->speed == SPEED_1000) { 1349 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1350 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1351 } else if (phydev->speed == SPEED_100) { 1352 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1353 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1354 } else { 1355 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1356 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1357 } 1358 rtl_reset_packet_filter(tp); 1359 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1360 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1361 if (phydev->speed == SPEED_1000) { 1362 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1363 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1364 } else { 1365 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1366 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1367 } 1368 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1369 if (phydev->speed == SPEED_10) { 1370 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1371 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1372 } else { 1373 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1374 } 1375 } 1376 } 1377 1378 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1379 1380 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1381 { 1382 struct rtl8169_private *tp = netdev_priv(dev); 1383 1384 rtl_lock_work(tp); 1385 wol->supported = WAKE_ANY; 1386 wol->wolopts = tp->saved_wolopts; 1387 rtl_unlock_work(tp); 1388 } 1389 1390 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1391 { 1392 unsigned int i, tmp; 1393 static const struct { 1394 u32 opt; 1395 u16 reg; 1396 u8 mask; 1397 } cfg[] = { 1398 { WAKE_PHY, Config3, LinkUp }, 1399 { WAKE_UCAST, Config5, UWF }, 1400 { WAKE_BCAST, Config5, BWF }, 1401 { WAKE_MCAST, Config5, MWF }, 1402 { WAKE_ANY, Config5, LanWake }, 1403 { WAKE_MAGIC, Config3, MagicPacket } 1404 }; 1405 u8 options; 1406 1407 rtl_unlock_config_regs(tp); 1408 1409 if (rtl_is_8168evl_up(tp)) { 1410 tmp = ARRAY_SIZE(cfg) - 1; 1411 if (wolopts & WAKE_MAGIC) 1412 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1413 MagicPacket_v2); 1414 else 1415 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1416 MagicPacket_v2); 1417 } else { 1418 tmp = ARRAY_SIZE(cfg); 1419 } 1420 1421 for (i = 0; i < tmp; i++) { 1422 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1423 if (wolopts & cfg[i].opt) 1424 options |= cfg[i].mask; 1425 RTL_W8(tp, cfg[i].reg, options); 1426 } 1427 1428 switch (tp->mac_version) { 1429 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1430 options = RTL_R8(tp, Config1) & ~PMEnable; 1431 if (wolopts) 1432 options |= PMEnable; 1433 RTL_W8(tp, Config1, options); 1434 break; 1435 case RTL_GIGA_MAC_VER_34: 1436 case RTL_GIGA_MAC_VER_37: 1437 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51: 1438 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1439 if (wolopts) 1440 options |= PME_SIGNAL; 1441 RTL_W8(tp, Config2, options); 1442 break; 1443 default: 1444 break; 1445 } 1446 1447 rtl_lock_config_regs(tp); 1448 1449 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1450 } 1451 1452 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1453 { 1454 struct rtl8169_private *tp = netdev_priv(dev); 1455 struct device *d = tp_to_dev(tp); 1456 1457 if (wol->wolopts & ~WAKE_ANY) 1458 return -EINVAL; 1459 1460 pm_runtime_get_noresume(d); 1461 1462 rtl_lock_work(tp); 1463 1464 tp->saved_wolopts = wol->wolopts; 1465 1466 if (pm_runtime_active(d)) 1467 __rtl8169_set_wol(tp, tp->saved_wolopts); 1468 1469 rtl_unlock_work(tp); 1470 1471 pm_runtime_put_noidle(d); 1472 1473 return 0; 1474 } 1475 1476 static void rtl8169_get_drvinfo(struct net_device *dev, 1477 struct ethtool_drvinfo *info) 1478 { 1479 struct rtl8169_private *tp = netdev_priv(dev); 1480 struct rtl_fw *rtl_fw = tp->rtl_fw; 1481 1482 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1483 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1484 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1485 if (rtl_fw) 1486 strlcpy(info->fw_version, rtl_fw->version, 1487 sizeof(info->fw_version)); 1488 } 1489 1490 static int rtl8169_get_regs_len(struct net_device *dev) 1491 { 1492 return R8169_REGS_SIZE; 1493 } 1494 1495 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1496 netdev_features_t features) 1497 { 1498 struct rtl8169_private *tp = netdev_priv(dev); 1499 1500 if (dev->mtu > TD_MSS_MAX) 1501 features &= ~NETIF_F_ALL_TSO; 1502 1503 if (dev->mtu > JUMBO_1K && 1504 tp->mac_version > RTL_GIGA_MAC_VER_06) 1505 features &= ~NETIF_F_IP_CSUM; 1506 1507 return features; 1508 } 1509 1510 static int rtl8169_set_features(struct net_device *dev, 1511 netdev_features_t features) 1512 { 1513 struct rtl8169_private *tp = netdev_priv(dev); 1514 u32 rx_config; 1515 1516 rtl_lock_work(tp); 1517 1518 rx_config = RTL_R32(tp, RxConfig); 1519 if (features & NETIF_F_RXALL) 1520 rx_config |= (AcceptErr | AcceptRunt); 1521 else 1522 rx_config &= ~(AcceptErr | AcceptRunt); 1523 1524 RTL_W32(tp, RxConfig, rx_config); 1525 1526 if (features & NETIF_F_RXCSUM) 1527 tp->cp_cmd |= RxChkSum; 1528 else 1529 tp->cp_cmd &= ~RxChkSum; 1530 1531 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1532 tp->cp_cmd |= RxVlan; 1533 else 1534 tp->cp_cmd &= ~RxVlan; 1535 1536 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1537 RTL_R16(tp, CPlusCmd); 1538 1539 rtl_unlock_work(tp); 1540 1541 return 0; 1542 } 1543 1544 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1545 { 1546 return (skb_vlan_tag_present(skb)) ? 1547 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1548 } 1549 1550 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1551 { 1552 u32 opts2 = le32_to_cpu(desc->opts2); 1553 1554 if (opts2 & RxVlanTag) 1555 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1556 } 1557 1558 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1559 void *p) 1560 { 1561 struct rtl8169_private *tp = netdev_priv(dev); 1562 u32 __iomem *data = tp->mmio_addr; 1563 u32 *dw = p; 1564 int i; 1565 1566 rtl_lock_work(tp); 1567 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1568 memcpy_fromio(dw++, data++, 4); 1569 rtl_unlock_work(tp); 1570 } 1571 1572 static u32 rtl8169_get_msglevel(struct net_device *dev) 1573 { 1574 struct rtl8169_private *tp = netdev_priv(dev); 1575 1576 return tp->msg_enable; 1577 } 1578 1579 static void rtl8169_set_msglevel(struct net_device *dev, u32 value) 1580 { 1581 struct rtl8169_private *tp = netdev_priv(dev); 1582 1583 tp->msg_enable = value; 1584 } 1585 1586 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1587 "tx_packets", 1588 "rx_packets", 1589 "tx_errors", 1590 "rx_errors", 1591 "rx_missed", 1592 "align_errors", 1593 "tx_single_collisions", 1594 "tx_multi_collisions", 1595 "unicast", 1596 "broadcast", 1597 "multicast", 1598 "tx_aborted", 1599 "tx_underrun", 1600 }; 1601 1602 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1603 { 1604 switch (sset) { 1605 case ETH_SS_STATS: 1606 return ARRAY_SIZE(rtl8169_gstrings); 1607 default: 1608 return -EOPNOTSUPP; 1609 } 1610 } 1611 1612 DECLARE_RTL_COND(rtl_counters_cond) 1613 { 1614 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1615 } 1616 1617 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1618 { 1619 dma_addr_t paddr = tp->counters_phys_addr; 1620 u32 cmd; 1621 1622 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1623 RTL_R32(tp, CounterAddrHigh); 1624 cmd = (u64)paddr & DMA_BIT_MASK(32); 1625 RTL_W32(tp, CounterAddrLow, cmd); 1626 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1627 1628 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1629 } 1630 1631 static bool rtl8169_reset_counters(struct rtl8169_private *tp) 1632 { 1633 /* 1634 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1635 * tally counters. 1636 */ 1637 if (tp->mac_version < RTL_GIGA_MAC_VER_19) 1638 return true; 1639 1640 return rtl8169_do_counters(tp, CounterReset); 1641 } 1642 1643 static bool rtl8169_update_counters(struct rtl8169_private *tp) 1644 { 1645 u8 val = RTL_R8(tp, ChipCmd); 1646 1647 /* 1648 * Some chips are unable to dump tally counters when the receiver 1649 * is disabled. If 0xff chip may be in a PCI power-save state. 1650 */ 1651 if (!(val & CmdRxEnb) || val == 0xff) 1652 return true; 1653 1654 return rtl8169_do_counters(tp, CounterDump); 1655 } 1656 1657 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1658 { 1659 struct rtl8169_counters *counters = tp->counters; 1660 bool ret = false; 1661 1662 /* 1663 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1664 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1665 * reset by a power cycle, while the counter values collected by the 1666 * driver are reset at every driver unload/load cycle. 1667 * 1668 * To make sure the HW values returned by @get_stats64 match the SW 1669 * values, we collect the initial values at first open(*) and use them 1670 * as offsets to normalize the values returned by @get_stats64. 1671 * 1672 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1673 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1674 * set at open time by rtl_hw_start. 1675 */ 1676 1677 if (tp->tc_offset.inited) 1678 return true; 1679 1680 /* If both, reset and update fail, propagate to caller. */ 1681 if (rtl8169_reset_counters(tp)) 1682 ret = true; 1683 1684 if (rtl8169_update_counters(tp)) 1685 ret = true; 1686 1687 tp->tc_offset.tx_errors = counters->tx_errors; 1688 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1689 tp->tc_offset.tx_aborted = counters->tx_aborted; 1690 tp->tc_offset.inited = true; 1691 1692 return ret; 1693 } 1694 1695 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1696 struct ethtool_stats *stats, u64 *data) 1697 { 1698 struct rtl8169_private *tp = netdev_priv(dev); 1699 struct device *d = tp_to_dev(tp); 1700 struct rtl8169_counters *counters = tp->counters; 1701 1702 ASSERT_RTNL(); 1703 1704 pm_runtime_get_noresume(d); 1705 1706 if (pm_runtime_active(d)) 1707 rtl8169_update_counters(tp); 1708 1709 pm_runtime_put_noidle(d); 1710 1711 data[0] = le64_to_cpu(counters->tx_packets); 1712 data[1] = le64_to_cpu(counters->rx_packets); 1713 data[2] = le64_to_cpu(counters->tx_errors); 1714 data[3] = le32_to_cpu(counters->rx_errors); 1715 data[4] = le16_to_cpu(counters->rx_missed); 1716 data[5] = le16_to_cpu(counters->align_errors); 1717 data[6] = le32_to_cpu(counters->tx_one_collision); 1718 data[7] = le32_to_cpu(counters->tx_multi_collision); 1719 data[8] = le64_to_cpu(counters->rx_unicast); 1720 data[9] = le64_to_cpu(counters->rx_broadcast); 1721 data[10] = le32_to_cpu(counters->rx_multicast); 1722 data[11] = le16_to_cpu(counters->tx_aborted); 1723 data[12] = le16_to_cpu(counters->tx_underun); 1724 } 1725 1726 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1727 { 1728 switch(stringset) { 1729 case ETH_SS_STATS: 1730 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1731 break; 1732 } 1733 } 1734 1735 /* 1736 * Interrupt coalescing 1737 * 1738 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1739 * > 8169, 8168 and 810x line of chipsets 1740 * 1741 * 8169, 8168, and 8136(810x) serial chipsets support it. 1742 * 1743 * > 2 - the Tx timer unit at gigabit speed 1744 * 1745 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1746 * (0xe0) bit 1 and bit 0. 1747 * 1748 * For 8169 1749 * bit[1:0] \ speed 1000M 100M 10M 1750 * 0 0 320ns 2.56us 40.96us 1751 * 0 1 2.56us 20.48us 327.7us 1752 * 1 0 5.12us 40.96us 655.4us 1753 * 1 1 10.24us 81.92us 1.31ms 1754 * 1755 * For the other 1756 * bit[1:0] \ speed 1000M 100M 10M 1757 * 0 0 5us 2.56us 40.96us 1758 * 0 1 40us 20.48us 327.7us 1759 * 1 0 80us 40.96us 655.4us 1760 * 1 1 160us 81.92us 1.31ms 1761 */ 1762 1763 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */ 1764 struct rtl_coalesce_scale { 1765 /* Rx / Tx */ 1766 u32 nsecs[2]; 1767 }; 1768 1769 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1770 struct rtl_coalesce_info { 1771 u32 speed; 1772 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */ 1773 }; 1774 1775 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */ 1776 #define rxtx_x1822(r, t) { \ 1777 {{(r), (t)}}, \ 1778 {{(r)*8, (t)*8}}, \ 1779 {{(r)*8*2, (t)*8*2}}, \ 1780 {{(r)*8*2*2, (t)*8*2*2}}, \ 1781 } 1782 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1783 /* speed delays: rx00 tx00 */ 1784 { SPEED_10, rxtx_x1822(40960, 40960) }, 1785 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1786 { SPEED_1000, rxtx_x1822( 320, 320) }, 1787 { 0 }, 1788 }; 1789 1790 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1791 /* speed delays: rx00 tx00 */ 1792 { SPEED_10, rxtx_x1822(40960, 40960) }, 1793 { SPEED_100, rxtx_x1822( 2560, 2560) }, 1794 { SPEED_1000, rxtx_x1822( 5000, 5000) }, 1795 { 0 }, 1796 }; 1797 #undef rxtx_x1822 1798 1799 /* get rx/tx scale vector corresponding to current speed */ 1800 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev) 1801 { 1802 struct rtl8169_private *tp = netdev_priv(dev); 1803 const struct rtl_coalesce_info *ci; 1804 1805 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1806 ci = rtl_coalesce_info_8169; 1807 else 1808 ci = rtl_coalesce_info_8168_8136; 1809 1810 for (; ci->speed; ci++) { 1811 if (tp->phydev->speed == ci->speed) 1812 return ci; 1813 } 1814 1815 return ERR_PTR(-ELNRNG); 1816 } 1817 1818 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1819 { 1820 struct rtl8169_private *tp = netdev_priv(dev); 1821 const struct rtl_coalesce_info *ci; 1822 const struct rtl_coalesce_scale *scale; 1823 struct { 1824 u32 *max_frames; 1825 u32 *usecs; 1826 } coal_settings [] = { 1827 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs }, 1828 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs } 1829 }, *p = coal_settings; 1830 int i; 1831 u16 w; 1832 1833 memset(ec, 0, sizeof(*ec)); 1834 1835 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1836 ci = rtl_coalesce_info(dev); 1837 if (IS_ERR(ci)) 1838 return PTR_ERR(ci); 1839 1840 scale = &ci->scalev[tp->cp_cmd & INTT_MASK]; 1841 1842 /* read IntrMitigate and adjust according to scale */ 1843 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) { 1844 *p->max_frames = (w & RTL_COALESCE_MASK) << 2; 1845 w >>= RTL_COALESCE_SHIFT; 1846 *p->usecs = w & RTL_COALESCE_MASK; 1847 } 1848 1849 for (i = 0; i < 2; i++) { 1850 p = coal_settings + i; 1851 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000; 1852 1853 /* 1854 * ethtool_coalesce says it is illegal to set both usecs and 1855 * max_frames to 0. 1856 */ 1857 if (!*p->usecs && !*p->max_frames) 1858 *p->max_frames = 1; 1859 } 1860 1861 return 0; 1862 } 1863 1864 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */ 1865 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale( 1866 struct net_device *dev, u32 nsec, u16 *cp01) 1867 { 1868 const struct rtl_coalesce_info *ci; 1869 u16 i; 1870 1871 ci = rtl_coalesce_info(dev); 1872 if (IS_ERR(ci)) 1873 return ERR_CAST(ci); 1874 1875 for (i = 0; i < 4; i++) { 1876 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0], 1877 ci->scalev[i].nsecs[1]); 1878 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) { 1879 *cp01 = i; 1880 return &ci->scalev[i]; 1881 } 1882 } 1883 1884 return ERR_PTR(-EINVAL); 1885 } 1886 1887 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1888 { 1889 struct rtl8169_private *tp = netdev_priv(dev); 1890 const struct rtl_coalesce_scale *scale; 1891 struct { 1892 u32 frames; 1893 u32 usecs; 1894 } coal_settings [] = { 1895 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs }, 1896 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs } 1897 }, *p = coal_settings; 1898 u16 w = 0, cp01; 1899 int i; 1900 1901 scale = rtl_coalesce_choose_scale(dev, 1902 max(p[0].usecs, p[1].usecs) * 1000, &cp01); 1903 if (IS_ERR(scale)) 1904 return PTR_ERR(scale); 1905 1906 for (i = 0; i < 2; i++, p++) { 1907 u32 units; 1908 1909 /* 1910 * accept max_frames=1 we returned in rtl_get_coalesce. 1911 * accept it not only when usecs=0 because of e.g. the following scenario: 1912 * 1913 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1914 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1915 * - then user does `ethtool -C eth0 rx-usecs 100` 1916 * 1917 * since ethtool sends to kernel whole ethtool_coalesce 1918 * settings, if we do not handle rx_usecs=!0, rx_frames=1 1919 * we'll reject it below in `frames % 4 != 0`. 1920 */ 1921 if (p->frames == 1) { 1922 p->frames = 0; 1923 } 1924 1925 units = p->usecs * 1000 / scale->nsecs[i]; 1926 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4) 1927 return -EINVAL; 1928 1929 w <<= RTL_COALESCE_SHIFT; 1930 w |= units; 1931 w <<= RTL_COALESCE_SHIFT; 1932 w |= p->frames >> 2; 1933 } 1934 1935 rtl_lock_work(tp); 1936 1937 RTL_W16(tp, IntrMitigate, swab16(w)); 1938 1939 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1940 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1941 RTL_R16(tp, CPlusCmd); 1942 1943 rtl_unlock_work(tp); 1944 1945 return 0; 1946 } 1947 1948 static int rtl_get_eee_supp(struct rtl8169_private *tp) 1949 { 1950 struct phy_device *phydev = tp->phydev; 1951 int ret; 1952 1953 switch (tp->mac_version) { 1954 case RTL_GIGA_MAC_VER_34: 1955 case RTL_GIGA_MAC_VER_35: 1956 case RTL_GIGA_MAC_VER_36: 1957 case RTL_GIGA_MAC_VER_38: 1958 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1959 break; 1960 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 1961 ret = phy_read_paged(phydev, 0x0a5c, 0x12); 1962 break; 1963 default: 1964 ret = -EPROTONOSUPPORT; 1965 break; 1966 } 1967 1968 return ret; 1969 } 1970 1971 static int rtl_get_eee_lpadv(struct rtl8169_private *tp) 1972 { 1973 struct phy_device *phydev = tp->phydev; 1974 int ret; 1975 1976 switch (tp->mac_version) { 1977 case RTL_GIGA_MAC_VER_34: 1978 case RTL_GIGA_MAC_VER_35: 1979 case RTL_GIGA_MAC_VER_36: 1980 case RTL_GIGA_MAC_VER_38: 1981 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 1982 break; 1983 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 1984 ret = phy_read_paged(phydev, 0x0a5d, 0x11); 1985 break; 1986 default: 1987 ret = -EPROTONOSUPPORT; 1988 break; 1989 } 1990 1991 return ret; 1992 } 1993 1994 static int rtl_get_eee_adv(struct rtl8169_private *tp) 1995 { 1996 struct phy_device *phydev = tp->phydev; 1997 int ret; 1998 1999 switch (tp->mac_version) { 2000 case RTL_GIGA_MAC_VER_34: 2001 case RTL_GIGA_MAC_VER_35: 2002 case RTL_GIGA_MAC_VER_36: 2003 case RTL_GIGA_MAC_VER_38: 2004 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 2005 break; 2006 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 2007 ret = phy_read_paged(phydev, 0x0a5d, 0x10); 2008 break; 2009 default: 2010 ret = -EPROTONOSUPPORT; 2011 break; 2012 } 2013 2014 return ret; 2015 } 2016 2017 static int rtl_set_eee_adv(struct rtl8169_private *tp, int val) 2018 { 2019 struct phy_device *phydev = tp->phydev; 2020 int ret = 0; 2021 2022 switch (tp->mac_version) { 2023 case RTL_GIGA_MAC_VER_34: 2024 case RTL_GIGA_MAC_VER_35: 2025 case RTL_GIGA_MAC_VER_36: 2026 case RTL_GIGA_MAC_VER_38: 2027 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); 2028 break; 2029 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 2030 phy_write_paged(phydev, 0x0a5d, 0x10, val); 2031 break; 2032 default: 2033 ret = -EPROTONOSUPPORT; 2034 break; 2035 } 2036 2037 return ret; 2038 } 2039 2040 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 2041 { 2042 struct rtl8169_private *tp = netdev_priv(dev); 2043 struct device *d = tp_to_dev(tp); 2044 int ret; 2045 2046 pm_runtime_get_noresume(d); 2047 2048 if (!pm_runtime_active(d)) { 2049 ret = -EOPNOTSUPP; 2050 goto out; 2051 } 2052 2053 /* Get Supported EEE */ 2054 ret = rtl_get_eee_supp(tp); 2055 if (ret < 0) 2056 goto out; 2057 data->supported = mmd_eee_cap_to_ethtool_sup_t(ret); 2058 2059 /* Get advertisement EEE */ 2060 ret = rtl_get_eee_adv(tp); 2061 if (ret < 0) 2062 goto out; 2063 data->advertised = mmd_eee_adv_to_ethtool_adv_t(ret); 2064 data->eee_enabled = !!data->advertised; 2065 2066 /* Get LP advertisement EEE */ 2067 ret = rtl_get_eee_lpadv(tp); 2068 if (ret < 0) 2069 goto out; 2070 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(ret); 2071 data->eee_active = !!(data->advertised & data->lp_advertised); 2072 out: 2073 pm_runtime_put_noidle(d); 2074 return ret < 0 ? ret : 0; 2075 } 2076 2077 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 2078 { 2079 struct rtl8169_private *tp = netdev_priv(dev); 2080 struct device *d = tp_to_dev(tp); 2081 int old_adv, adv = 0, cap, ret; 2082 2083 pm_runtime_get_noresume(d); 2084 2085 if (!dev->phydev || !pm_runtime_active(d)) { 2086 ret = -EOPNOTSUPP; 2087 goto out; 2088 } 2089 2090 if (dev->phydev->autoneg == AUTONEG_DISABLE || 2091 dev->phydev->duplex != DUPLEX_FULL) { 2092 ret = -EPROTONOSUPPORT; 2093 goto out; 2094 } 2095 2096 /* Get Supported EEE */ 2097 ret = rtl_get_eee_supp(tp); 2098 if (ret < 0) 2099 goto out; 2100 cap = ret; 2101 2102 ret = rtl_get_eee_adv(tp); 2103 if (ret < 0) 2104 goto out; 2105 old_adv = ret; 2106 2107 if (data->eee_enabled) { 2108 adv = !data->advertised ? cap : 2109 ethtool_adv_to_mmd_eee_adv_t(data->advertised) & cap; 2110 /* Mask prohibited EEE modes */ 2111 adv &= ~dev->phydev->eee_broken_modes; 2112 } 2113 2114 if (old_adv != adv) { 2115 ret = rtl_set_eee_adv(tp, adv); 2116 if (ret < 0) 2117 goto out; 2118 2119 /* Restart autonegotiation so the new modes get sent to the 2120 * link partner. 2121 */ 2122 ret = phy_restart_aneg(dev->phydev); 2123 } 2124 2125 out: 2126 pm_runtime_put_noidle(d); 2127 return ret < 0 ? ret : 0; 2128 } 2129 2130 static const struct ethtool_ops rtl8169_ethtool_ops = { 2131 .get_drvinfo = rtl8169_get_drvinfo, 2132 .get_regs_len = rtl8169_get_regs_len, 2133 .get_link = ethtool_op_get_link, 2134 .get_coalesce = rtl_get_coalesce, 2135 .set_coalesce = rtl_set_coalesce, 2136 .get_msglevel = rtl8169_get_msglevel, 2137 .set_msglevel = rtl8169_set_msglevel, 2138 .get_regs = rtl8169_get_regs, 2139 .get_wol = rtl8169_get_wol, 2140 .set_wol = rtl8169_set_wol, 2141 .get_strings = rtl8169_get_strings, 2142 .get_sset_count = rtl8169_get_sset_count, 2143 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2144 .get_ts_info = ethtool_op_get_ts_info, 2145 .nway_reset = phy_ethtool_nway_reset, 2146 .get_eee = rtl8169_get_eee, 2147 .set_eee = rtl8169_set_eee, 2148 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2149 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2150 }; 2151 2152 static void rtl_enable_eee(struct rtl8169_private *tp) 2153 { 2154 int supported = rtl_get_eee_supp(tp); 2155 2156 if (supported > 0) 2157 rtl_set_eee_adv(tp, supported); 2158 } 2159 2160 static void rtl8169_get_mac_version(struct rtl8169_private *tp) 2161 { 2162 /* 2163 * The driver currently handles the 8168Bf and the 8168Be identically 2164 * but they can be identified more specifically through the test below 2165 * if needed: 2166 * 2167 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2168 * 2169 * Same thing for the 8101Eb and the 8101Ec: 2170 * 2171 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2172 */ 2173 static const struct rtl_mac_info { 2174 u16 mask; 2175 u16 val; 2176 u16 mac_version; 2177 } mac_info[] = { 2178 /* 8168EP family. */ 2179 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2180 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2181 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2182 2183 /* 8168H family. */ 2184 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2185 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2186 2187 /* 8168G family. */ 2188 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2189 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2190 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2191 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2192 2193 /* 8168F family. */ 2194 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2195 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2196 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2197 2198 /* 8168E family. */ 2199 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2200 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2201 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2202 2203 /* 8168D family. */ 2204 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2205 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2206 2207 /* 8168DP family. */ 2208 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2209 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2210 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2211 2212 /* 8168C family. */ 2213 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2214 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2215 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2216 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2217 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2218 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2219 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2220 2221 /* 8168B family. */ 2222 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2223 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2224 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2225 2226 /* 8101 family. */ 2227 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2228 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2229 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2230 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2231 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2232 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2233 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2234 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2235 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2236 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2237 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2238 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2239 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2240 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2241 /* FIXME: where did these entries come from ? -- FR */ 2242 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2243 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2244 2245 /* 8110 family. */ 2246 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2247 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2248 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2249 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2250 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2251 2252 /* Catch-all */ 2253 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2254 }; 2255 const struct rtl_mac_info *p = mac_info; 2256 u16 reg = RTL_R32(tp, TxConfig) >> 20; 2257 2258 while ((reg & p->mask) != p->val) 2259 p++; 2260 tp->mac_version = p->mac_version; 2261 2262 if (tp->mac_version == RTL_GIGA_MAC_NONE) { 2263 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf); 2264 } else if (!tp->supports_gmii) { 2265 if (tp->mac_version == RTL_GIGA_MAC_VER_42) 2266 tp->mac_version = RTL_GIGA_MAC_VER_43; 2267 else if (tp->mac_version == RTL_GIGA_MAC_VER_45) 2268 tp->mac_version = RTL_GIGA_MAC_VER_47; 2269 else if (tp->mac_version == RTL_GIGA_MAC_VER_46) 2270 tp->mac_version = RTL_GIGA_MAC_VER_48; 2271 } 2272 } 2273 2274 struct phy_reg { 2275 u16 reg; 2276 u16 val; 2277 }; 2278 2279 static void __rtl_writephy_batch(struct rtl8169_private *tp, 2280 const struct phy_reg *regs, int len) 2281 { 2282 while (len-- > 0) { 2283 rtl_writephy(tp, regs->reg, regs->val); 2284 regs++; 2285 } 2286 } 2287 2288 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a)) 2289 2290 static void rtl_release_firmware(struct rtl8169_private *tp) 2291 { 2292 if (tp->rtl_fw) { 2293 rtl_fw_release_firmware(tp->rtl_fw); 2294 kfree(tp->rtl_fw); 2295 tp->rtl_fw = NULL; 2296 } 2297 } 2298 2299 static void rtl_apply_firmware(struct rtl8169_private *tp) 2300 { 2301 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2302 if (tp->rtl_fw) 2303 rtl_fw_write_firmware(tp, tp->rtl_fw); 2304 } 2305 2306 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) 2307 { 2308 if (rtl_readphy(tp, reg) != val) 2309 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); 2310 else 2311 rtl_apply_firmware(tp); 2312 } 2313 2314 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2315 { 2316 /* Adjust EEE LED frequency */ 2317 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2318 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2319 2320 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2321 } 2322 2323 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp) 2324 { 2325 struct phy_device *phydev = tp->phydev; 2326 2327 phy_write(phydev, 0x1f, 0x0007); 2328 phy_write(phydev, 0x1e, 0x0020); 2329 phy_set_bits(phydev, 0x15, BIT(8)); 2330 2331 phy_write(phydev, 0x1f, 0x0005); 2332 phy_write(phydev, 0x05, 0x8b85); 2333 phy_set_bits(phydev, 0x06, BIT(13)); 2334 2335 phy_write(phydev, 0x1f, 0x0000); 2336 } 2337 2338 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp) 2339 { 2340 phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4)); 2341 } 2342 2343 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) 2344 { 2345 static const struct phy_reg phy_reg_init[] = { 2346 { 0x1f, 0x0001 }, 2347 { 0x06, 0x006e }, 2348 { 0x08, 0x0708 }, 2349 { 0x15, 0x4000 }, 2350 { 0x18, 0x65c7 }, 2351 2352 { 0x1f, 0x0001 }, 2353 { 0x03, 0x00a1 }, 2354 { 0x02, 0x0008 }, 2355 { 0x01, 0x0120 }, 2356 { 0x00, 0x1000 }, 2357 { 0x04, 0x0800 }, 2358 { 0x04, 0x0000 }, 2359 2360 { 0x03, 0xff41 }, 2361 { 0x02, 0xdf60 }, 2362 { 0x01, 0x0140 }, 2363 { 0x00, 0x0077 }, 2364 { 0x04, 0x7800 }, 2365 { 0x04, 0x7000 }, 2366 2367 { 0x03, 0x802f }, 2368 { 0x02, 0x4f02 }, 2369 { 0x01, 0x0409 }, 2370 { 0x00, 0xf0f9 }, 2371 { 0x04, 0x9800 }, 2372 { 0x04, 0x9000 }, 2373 2374 { 0x03, 0xdf01 }, 2375 { 0x02, 0xdf20 }, 2376 { 0x01, 0xff95 }, 2377 { 0x00, 0xba00 }, 2378 { 0x04, 0xa800 }, 2379 { 0x04, 0xa000 }, 2380 2381 { 0x03, 0xff41 }, 2382 { 0x02, 0xdf20 }, 2383 { 0x01, 0x0140 }, 2384 { 0x00, 0x00bb }, 2385 { 0x04, 0xb800 }, 2386 { 0x04, 0xb000 }, 2387 2388 { 0x03, 0xdf41 }, 2389 { 0x02, 0xdc60 }, 2390 { 0x01, 0x6340 }, 2391 { 0x00, 0x007d }, 2392 { 0x04, 0xd800 }, 2393 { 0x04, 0xd000 }, 2394 2395 { 0x03, 0xdf01 }, 2396 { 0x02, 0xdf20 }, 2397 { 0x01, 0x100a }, 2398 { 0x00, 0xa0ff }, 2399 { 0x04, 0xf800 }, 2400 { 0x04, 0xf000 }, 2401 2402 { 0x1f, 0x0000 }, 2403 { 0x0b, 0x0000 }, 2404 { 0x00, 0x9200 } 2405 }; 2406 2407 rtl_writephy_batch(tp, phy_reg_init); 2408 } 2409 2410 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) 2411 { 2412 static const struct phy_reg phy_reg_init[] = { 2413 { 0x1f, 0x0002 }, 2414 { 0x01, 0x90d0 }, 2415 { 0x1f, 0x0000 } 2416 }; 2417 2418 rtl_writephy_batch(tp, phy_reg_init); 2419 } 2420 2421 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) 2422 { 2423 struct pci_dev *pdev = tp->pci_dev; 2424 2425 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || 2426 (pdev->subsystem_device != 0xe000)) 2427 return; 2428 2429 rtl_writephy(tp, 0x1f, 0x0001); 2430 rtl_writephy(tp, 0x10, 0xf01b); 2431 rtl_writephy(tp, 0x1f, 0x0000); 2432 } 2433 2434 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) 2435 { 2436 static const struct phy_reg phy_reg_init[] = { 2437 { 0x1f, 0x0001 }, 2438 { 0x04, 0x0000 }, 2439 { 0x03, 0x00a1 }, 2440 { 0x02, 0x0008 }, 2441 { 0x01, 0x0120 }, 2442 { 0x00, 0x1000 }, 2443 { 0x04, 0x0800 }, 2444 { 0x04, 0x9000 }, 2445 { 0x03, 0x802f }, 2446 { 0x02, 0x4f02 }, 2447 { 0x01, 0x0409 }, 2448 { 0x00, 0xf099 }, 2449 { 0x04, 0x9800 }, 2450 { 0x04, 0xa000 }, 2451 { 0x03, 0xdf01 }, 2452 { 0x02, 0xdf20 }, 2453 { 0x01, 0xff95 }, 2454 { 0x00, 0xba00 }, 2455 { 0x04, 0xa800 }, 2456 { 0x04, 0xf000 }, 2457 { 0x03, 0xdf01 }, 2458 { 0x02, 0xdf20 }, 2459 { 0x01, 0x101a }, 2460 { 0x00, 0xa0ff }, 2461 { 0x04, 0xf800 }, 2462 { 0x04, 0x0000 }, 2463 { 0x1f, 0x0000 }, 2464 2465 { 0x1f, 0x0001 }, 2466 { 0x10, 0xf41b }, 2467 { 0x14, 0xfb54 }, 2468 { 0x18, 0xf5c7 }, 2469 { 0x1f, 0x0000 }, 2470 2471 { 0x1f, 0x0001 }, 2472 { 0x17, 0x0cc0 }, 2473 { 0x1f, 0x0000 } 2474 }; 2475 2476 rtl_writephy_batch(tp, phy_reg_init); 2477 2478 rtl8169scd_hw_phy_config_quirk(tp); 2479 } 2480 2481 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) 2482 { 2483 static const struct phy_reg phy_reg_init[] = { 2484 { 0x1f, 0x0001 }, 2485 { 0x04, 0x0000 }, 2486 { 0x03, 0x00a1 }, 2487 { 0x02, 0x0008 }, 2488 { 0x01, 0x0120 }, 2489 { 0x00, 0x1000 }, 2490 { 0x04, 0x0800 }, 2491 { 0x04, 0x9000 }, 2492 { 0x03, 0x802f }, 2493 { 0x02, 0x4f02 }, 2494 { 0x01, 0x0409 }, 2495 { 0x00, 0xf099 }, 2496 { 0x04, 0x9800 }, 2497 { 0x04, 0xa000 }, 2498 { 0x03, 0xdf01 }, 2499 { 0x02, 0xdf20 }, 2500 { 0x01, 0xff95 }, 2501 { 0x00, 0xba00 }, 2502 { 0x04, 0xa800 }, 2503 { 0x04, 0xf000 }, 2504 { 0x03, 0xdf01 }, 2505 { 0x02, 0xdf20 }, 2506 { 0x01, 0x101a }, 2507 { 0x00, 0xa0ff }, 2508 { 0x04, 0xf800 }, 2509 { 0x04, 0x0000 }, 2510 { 0x1f, 0x0000 }, 2511 2512 { 0x1f, 0x0001 }, 2513 { 0x0b, 0x8480 }, 2514 { 0x1f, 0x0000 }, 2515 2516 { 0x1f, 0x0001 }, 2517 { 0x18, 0x67c7 }, 2518 { 0x04, 0x2000 }, 2519 { 0x03, 0x002f }, 2520 { 0x02, 0x4360 }, 2521 { 0x01, 0x0109 }, 2522 { 0x00, 0x3022 }, 2523 { 0x04, 0x2800 }, 2524 { 0x1f, 0x0000 }, 2525 2526 { 0x1f, 0x0001 }, 2527 { 0x17, 0x0cc0 }, 2528 { 0x1f, 0x0000 } 2529 }; 2530 2531 rtl_writephy_batch(tp, phy_reg_init); 2532 } 2533 2534 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) 2535 { 2536 static const struct phy_reg phy_reg_init[] = { 2537 { 0x10, 0xf41b }, 2538 { 0x1f, 0x0000 } 2539 }; 2540 2541 rtl_writephy(tp, 0x1f, 0x0001); 2542 rtl_patchphy(tp, 0x16, 1 << 0); 2543 2544 rtl_writephy_batch(tp, phy_reg_init); 2545 } 2546 2547 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) 2548 { 2549 static const struct phy_reg phy_reg_init[] = { 2550 { 0x1f, 0x0001 }, 2551 { 0x10, 0xf41b }, 2552 { 0x1f, 0x0000 } 2553 }; 2554 2555 rtl_writephy_batch(tp, phy_reg_init); 2556 } 2557 2558 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) 2559 { 2560 static const struct phy_reg phy_reg_init[] = { 2561 { 0x1f, 0x0000 }, 2562 { 0x1d, 0x0f00 }, 2563 { 0x1f, 0x0002 }, 2564 { 0x0c, 0x1ec8 }, 2565 { 0x1f, 0x0000 } 2566 }; 2567 2568 rtl_writephy_batch(tp, phy_reg_init); 2569 } 2570 2571 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) 2572 { 2573 static const struct phy_reg phy_reg_init[] = { 2574 { 0x1f, 0x0001 }, 2575 { 0x1d, 0x3d98 }, 2576 { 0x1f, 0x0000 } 2577 }; 2578 2579 rtl_writephy(tp, 0x1f, 0x0000); 2580 rtl_patchphy(tp, 0x14, 1 << 5); 2581 rtl_patchphy(tp, 0x0d, 1 << 5); 2582 2583 rtl_writephy_batch(tp, phy_reg_init); 2584 } 2585 2586 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) 2587 { 2588 static const struct phy_reg phy_reg_init[] = { 2589 { 0x1f, 0x0001 }, 2590 { 0x12, 0x2300 }, 2591 { 0x1f, 0x0002 }, 2592 { 0x00, 0x88d4 }, 2593 { 0x01, 0x82b1 }, 2594 { 0x03, 0x7002 }, 2595 { 0x08, 0x9e30 }, 2596 { 0x09, 0x01f0 }, 2597 { 0x0a, 0x5500 }, 2598 { 0x0c, 0x00c8 }, 2599 { 0x1f, 0x0003 }, 2600 { 0x12, 0xc096 }, 2601 { 0x16, 0x000a }, 2602 { 0x1f, 0x0000 }, 2603 { 0x1f, 0x0000 }, 2604 { 0x09, 0x2000 }, 2605 { 0x09, 0x0000 } 2606 }; 2607 2608 rtl_writephy_batch(tp, phy_reg_init); 2609 2610 rtl_patchphy(tp, 0x14, 1 << 5); 2611 rtl_patchphy(tp, 0x0d, 1 << 5); 2612 rtl_writephy(tp, 0x1f, 0x0000); 2613 } 2614 2615 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) 2616 { 2617 static const struct phy_reg phy_reg_init[] = { 2618 { 0x1f, 0x0001 }, 2619 { 0x12, 0x2300 }, 2620 { 0x03, 0x802f }, 2621 { 0x02, 0x4f02 }, 2622 { 0x01, 0x0409 }, 2623 { 0x00, 0xf099 }, 2624 { 0x04, 0x9800 }, 2625 { 0x04, 0x9000 }, 2626 { 0x1d, 0x3d98 }, 2627 { 0x1f, 0x0002 }, 2628 { 0x0c, 0x7eb8 }, 2629 { 0x06, 0x0761 }, 2630 { 0x1f, 0x0003 }, 2631 { 0x16, 0x0f0a }, 2632 { 0x1f, 0x0000 } 2633 }; 2634 2635 rtl_writephy_batch(tp, phy_reg_init); 2636 2637 rtl_patchphy(tp, 0x16, 1 << 0); 2638 rtl_patchphy(tp, 0x14, 1 << 5); 2639 rtl_patchphy(tp, 0x0d, 1 << 5); 2640 rtl_writephy(tp, 0x1f, 0x0000); 2641 } 2642 2643 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) 2644 { 2645 static const struct phy_reg phy_reg_init[] = { 2646 { 0x1f, 0x0001 }, 2647 { 0x12, 0x2300 }, 2648 { 0x1d, 0x3d98 }, 2649 { 0x1f, 0x0002 }, 2650 { 0x0c, 0x7eb8 }, 2651 { 0x06, 0x5461 }, 2652 { 0x1f, 0x0003 }, 2653 { 0x16, 0x0f0a }, 2654 { 0x1f, 0x0000 } 2655 }; 2656 2657 rtl_writephy_batch(tp, phy_reg_init); 2658 2659 rtl_patchphy(tp, 0x16, 1 << 0); 2660 rtl_patchphy(tp, 0x14, 1 << 5); 2661 rtl_patchphy(tp, 0x0d, 1 << 5); 2662 rtl_writephy(tp, 0x1f, 0x0000); 2663 } 2664 2665 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) 2666 { 2667 rtl8168c_3_hw_phy_config(tp); 2668 } 2669 2670 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = { 2671 /* Channel Estimation */ 2672 { 0x1f, 0x0001 }, 2673 { 0x06, 0x4064 }, 2674 { 0x07, 0x2863 }, 2675 { 0x08, 0x059c }, 2676 { 0x09, 0x26b4 }, 2677 { 0x0a, 0x6a19 }, 2678 { 0x0b, 0xdcc8 }, 2679 { 0x10, 0xf06d }, 2680 { 0x14, 0x7f68 }, 2681 { 0x18, 0x7fd9 }, 2682 { 0x1c, 0xf0ff }, 2683 { 0x1d, 0x3d9c }, 2684 { 0x1f, 0x0003 }, 2685 { 0x12, 0xf49f }, 2686 { 0x13, 0x070b }, 2687 { 0x1a, 0x05ad }, 2688 { 0x14, 0x94c0 }, 2689 2690 /* 2691 * Tx Error Issue 2692 * Enhance line driver power 2693 */ 2694 { 0x1f, 0x0002 }, 2695 { 0x06, 0x5561 }, 2696 { 0x1f, 0x0005 }, 2697 { 0x05, 0x8332 }, 2698 { 0x06, 0x5561 }, 2699 2700 /* 2701 * Can not link to 1Gbps with bad cable 2702 * Decrease SNR threshold form 21.07dB to 19.04dB 2703 */ 2704 { 0x1f, 0x0001 }, 2705 { 0x17, 0x0cc0 }, 2706 2707 { 0x1f, 0x0000 }, 2708 { 0x0d, 0xf880 } 2709 }; 2710 2711 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = { 2712 { 0x1f, 0x0002 }, 2713 { 0x05, 0x669a }, 2714 { 0x1f, 0x0005 }, 2715 { 0x05, 0x8330 }, 2716 { 0x06, 0x669a }, 2717 { 0x1f, 0x0002 } 2718 }; 2719 2720 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) 2721 { 2722 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2723 2724 /* 2725 * Rx Error Issue 2726 * Fine Tune Switching regulator parameter 2727 */ 2728 rtl_writephy(tp, 0x1f, 0x0002); 2729 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef); 2730 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00); 2731 2732 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2733 int val; 2734 2735 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2736 2737 val = rtl_readphy(tp, 0x0d); 2738 2739 if ((val & 0x00ff) != 0x006c) { 2740 static const u32 set[] = { 2741 0x0065, 0x0066, 0x0067, 0x0068, 2742 0x0069, 0x006a, 0x006b, 0x006c 2743 }; 2744 int i; 2745 2746 rtl_writephy(tp, 0x1f, 0x0002); 2747 2748 val &= 0xff00; 2749 for (i = 0; i < ARRAY_SIZE(set); i++) 2750 rtl_writephy(tp, 0x0d, val | set[i]); 2751 } 2752 } else { 2753 static const struct phy_reg phy_reg_init[] = { 2754 { 0x1f, 0x0002 }, 2755 { 0x05, 0x6662 }, 2756 { 0x1f, 0x0005 }, 2757 { 0x05, 0x8330 }, 2758 { 0x06, 0x6662 } 2759 }; 2760 2761 rtl_writephy_batch(tp, phy_reg_init); 2762 } 2763 2764 /* RSET couple improve */ 2765 rtl_writephy(tp, 0x1f, 0x0002); 2766 rtl_patchphy(tp, 0x0d, 0x0300); 2767 rtl_patchphy(tp, 0x0f, 0x0010); 2768 2769 /* Fine tune PLL performance */ 2770 rtl_writephy(tp, 0x1f, 0x0002); 2771 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2772 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2773 2774 rtl_writephy(tp, 0x1f, 0x0005); 2775 rtl_writephy(tp, 0x05, 0x001b); 2776 2777 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); 2778 2779 rtl_writephy(tp, 0x1f, 0x0000); 2780 } 2781 2782 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) 2783 { 2784 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0); 2785 2786 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) { 2787 int val; 2788 2789 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1); 2790 2791 val = rtl_readphy(tp, 0x0d); 2792 if ((val & 0x00ff) != 0x006c) { 2793 static const u32 set[] = { 2794 0x0065, 0x0066, 0x0067, 0x0068, 2795 0x0069, 0x006a, 0x006b, 0x006c 2796 }; 2797 int i; 2798 2799 rtl_writephy(tp, 0x1f, 0x0002); 2800 2801 val &= 0xff00; 2802 for (i = 0; i < ARRAY_SIZE(set); i++) 2803 rtl_writephy(tp, 0x0d, val | set[i]); 2804 } 2805 } else { 2806 static const struct phy_reg phy_reg_init[] = { 2807 { 0x1f, 0x0002 }, 2808 { 0x05, 0x2642 }, 2809 { 0x1f, 0x0005 }, 2810 { 0x05, 0x8330 }, 2811 { 0x06, 0x2642 } 2812 }; 2813 2814 rtl_writephy_batch(tp, phy_reg_init); 2815 } 2816 2817 /* Fine tune PLL performance */ 2818 rtl_writephy(tp, 0x1f, 0x0002); 2819 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600); 2820 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000); 2821 2822 /* Switching regulator Slew rate */ 2823 rtl_writephy(tp, 0x1f, 0x0002); 2824 rtl_patchphy(tp, 0x0f, 0x0017); 2825 2826 rtl_writephy(tp, 0x1f, 0x0005); 2827 rtl_writephy(tp, 0x05, 0x001b); 2828 2829 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); 2830 2831 rtl_writephy(tp, 0x1f, 0x0000); 2832 } 2833 2834 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) 2835 { 2836 static const struct phy_reg phy_reg_init[] = { 2837 { 0x1f, 0x0002 }, 2838 { 0x10, 0x0008 }, 2839 { 0x0d, 0x006c }, 2840 2841 { 0x1f, 0x0000 }, 2842 { 0x0d, 0xf880 }, 2843 2844 { 0x1f, 0x0001 }, 2845 { 0x17, 0x0cc0 }, 2846 2847 { 0x1f, 0x0001 }, 2848 { 0x0b, 0xa4d8 }, 2849 { 0x09, 0x281c }, 2850 { 0x07, 0x2883 }, 2851 { 0x0a, 0x6b35 }, 2852 { 0x1d, 0x3da4 }, 2853 { 0x1c, 0xeffd }, 2854 { 0x14, 0x7f52 }, 2855 { 0x18, 0x7fc6 }, 2856 { 0x08, 0x0601 }, 2857 { 0x06, 0x4063 }, 2858 { 0x10, 0xf074 }, 2859 { 0x1f, 0x0003 }, 2860 { 0x13, 0x0789 }, 2861 { 0x12, 0xf4bd }, 2862 { 0x1a, 0x04fd }, 2863 { 0x14, 0x84b0 }, 2864 { 0x1f, 0x0000 }, 2865 { 0x00, 0x9200 }, 2866 2867 { 0x1f, 0x0005 }, 2868 { 0x01, 0x0340 }, 2869 { 0x1f, 0x0001 }, 2870 { 0x04, 0x4000 }, 2871 { 0x03, 0x1d21 }, 2872 { 0x02, 0x0c32 }, 2873 { 0x01, 0x0200 }, 2874 { 0x00, 0x5554 }, 2875 { 0x04, 0x4800 }, 2876 { 0x04, 0x4000 }, 2877 { 0x04, 0xf000 }, 2878 { 0x03, 0xdf01 }, 2879 { 0x02, 0xdf20 }, 2880 { 0x01, 0x101a }, 2881 { 0x00, 0xa0ff }, 2882 { 0x04, 0xf800 }, 2883 { 0x04, 0xf000 }, 2884 { 0x1f, 0x0000 }, 2885 2886 { 0x1f, 0x0007 }, 2887 { 0x1e, 0x0023 }, 2888 { 0x16, 0x0000 }, 2889 { 0x1f, 0x0000 } 2890 }; 2891 2892 rtl_writephy_batch(tp, phy_reg_init); 2893 } 2894 2895 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) 2896 { 2897 static const struct phy_reg phy_reg_init[] = { 2898 { 0x1f, 0x0001 }, 2899 { 0x17, 0x0cc0 }, 2900 2901 { 0x1f, 0x0007 }, 2902 { 0x1e, 0x002d }, 2903 { 0x18, 0x0040 }, 2904 { 0x1f, 0x0000 } 2905 }; 2906 2907 rtl_writephy_batch(tp, phy_reg_init); 2908 rtl_patchphy(tp, 0x0d, 1 << 5); 2909 } 2910 2911 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) 2912 { 2913 static const struct phy_reg phy_reg_init[] = { 2914 /* Enable Delay cap */ 2915 { 0x1f, 0x0005 }, 2916 { 0x05, 0x8b80 }, 2917 { 0x06, 0xc896 }, 2918 { 0x1f, 0x0000 }, 2919 2920 /* Channel estimation fine tune */ 2921 { 0x1f, 0x0001 }, 2922 { 0x0b, 0x6c20 }, 2923 { 0x07, 0x2872 }, 2924 { 0x1c, 0xefff }, 2925 { 0x1f, 0x0003 }, 2926 { 0x14, 0x6420 }, 2927 { 0x1f, 0x0000 }, 2928 2929 /* Update PFM & 10M TX idle timer */ 2930 { 0x1f, 0x0007 }, 2931 { 0x1e, 0x002f }, 2932 { 0x15, 0x1919 }, 2933 { 0x1f, 0x0000 }, 2934 2935 { 0x1f, 0x0007 }, 2936 { 0x1e, 0x00ac }, 2937 { 0x18, 0x0006 }, 2938 { 0x1f, 0x0000 } 2939 }; 2940 2941 rtl_apply_firmware(tp); 2942 2943 rtl_writephy_batch(tp, phy_reg_init); 2944 2945 /* DCO enable for 10M IDLE Power */ 2946 rtl_writephy(tp, 0x1f, 0x0007); 2947 rtl_writephy(tp, 0x1e, 0x0023); 2948 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 2949 rtl_writephy(tp, 0x1f, 0x0000); 2950 2951 /* For impedance matching */ 2952 rtl_writephy(tp, 0x1f, 0x0002); 2953 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00); 2954 rtl_writephy(tp, 0x1f, 0x0000); 2955 2956 /* PHY auto speed down */ 2957 rtl_writephy(tp, 0x1f, 0x0007); 2958 rtl_writephy(tp, 0x1e, 0x002d); 2959 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000); 2960 rtl_writephy(tp, 0x1f, 0x0000); 2961 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 2962 2963 rtl_writephy(tp, 0x1f, 0x0005); 2964 rtl_writephy(tp, 0x05, 0x8b86); 2965 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 2966 rtl_writephy(tp, 0x1f, 0x0000); 2967 2968 rtl_writephy(tp, 0x1f, 0x0005); 2969 rtl_writephy(tp, 0x05, 0x8b85); 2970 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000); 2971 rtl_writephy(tp, 0x1f, 0x0007); 2972 rtl_writephy(tp, 0x1e, 0x0020); 2973 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100); 2974 rtl_writephy(tp, 0x1f, 0x0006); 2975 rtl_writephy(tp, 0x00, 0x5a00); 2976 rtl_writephy(tp, 0x1f, 0x0000); 2977 rtl_writephy(tp, 0x0d, 0x0007); 2978 rtl_writephy(tp, 0x0e, 0x003c); 2979 rtl_writephy(tp, 0x0d, 0x4007); 2980 rtl_writephy(tp, 0x0e, 0x0000); 2981 rtl_writephy(tp, 0x0d, 0x0000); 2982 } 2983 2984 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2985 { 2986 const u16 w[] = { 2987 addr[0] | (addr[1] << 8), 2988 addr[2] | (addr[3] << 8), 2989 addr[4] | (addr[5] << 8) 2990 }; 2991 2992 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2993 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2994 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2995 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2996 } 2997 2998 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) 2999 { 3000 static const struct phy_reg phy_reg_init[] = { 3001 /* Enable Delay cap */ 3002 { 0x1f, 0x0004 }, 3003 { 0x1f, 0x0007 }, 3004 { 0x1e, 0x00ac }, 3005 { 0x18, 0x0006 }, 3006 { 0x1f, 0x0002 }, 3007 { 0x1f, 0x0000 }, 3008 { 0x1f, 0x0000 }, 3009 3010 /* Channel estimation fine tune */ 3011 { 0x1f, 0x0003 }, 3012 { 0x09, 0xa20f }, 3013 { 0x1f, 0x0000 }, 3014 { 0x1f, 0x0000 }, 3015 3016 /* Green Setting */ 3017 { 0x1f, 0x0005 }, 3018 { 0x05, 0x8b5b }, 3019 { 0x06, 0x9222 }, 3020 { 0x05, 0x8b6d }, 3021 { 0x06, 0x8000 }, 3022 { 0x05, 0x8b76 }, 3023 { 0x06, 0x8000 }, 3024 { 0x1f, 0x0000 } 3025 }; 3026 3027 rtl_apply_firmware(tp); 3028 3029 rtl_writephy_batch(tp, phy_reg_init); 3030 3031 /* For 4-corner performance improve */ 3032 rtl_writephy(tp, 0x1f, 0x0005); 3033 rtl_writephy(tp, 0x05, 0x8b80); 3034 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000); 3035 rtl_writephy(tp, 0x1f, 0x0000); 3036 3037 /* PHY auto speed down */ 3038 rtl_writephy(tp, 0x1f, 0x0004); 3039 rtl_writephy(tp, 0x1f, 0x0007); 3040 rtl_writephy(tp, 0x1e, 0x002d); 3041 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); 3042 rtl_writephy(tp, 0x1f, 0x0002); 3043 rtl_writephy(tp, 0x1f, 0x0000); 3044 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3045 3046 /* improve 10M EEE waveform */ 3047 rtl_writephy(tp, 0x1f, 0x0005); 3048 rtl_writephy(tp, 0x05, 0x8b86); 3049 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 3050 rtl_writephy(tp, 0x1f, 0x0000); 3051 3052 /* Improve 2-pair detection performance */ 3053 rtl_writephy(tp, 0x1f, 0x0005); 3054 rtl_writephy(tp, 0x05, 0x8b85); 3055 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3056 rtl_writephy(tp, 0x1f, 0x0000); 3057 3058 rtl8168f_config_eee_phy(tp); 3059 rtl_enable_eee(tp); 3060 3061 /* Green feature */ 3062 rtl_writephy(tp, 0x1f, 0x0003); 3063 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000); 3064 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000); 3065 rtl_writephy(tp, 0x1f, 0x0000); 3066 rtl_writephy(tp, 0x1f, 0x0005); 3067 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000); 3068 rtl_writephy(tp, 0x1f, 0x0000); 3069 3070 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */ 3071 rtl_rar_exgmac_set(tp, tp->dev->dev_addr); 3072 } 3073 3074 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp) 3075 { 3076 /* For 4-corner performance improve */ 3077 rtl_writephy(tp, 0x1f, 0x0005); 3078 rtl_writephy(tp, 0x05, 0x8b80); 3079 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000); 3080 rtl_writephy(tp, 0x1f, 0x0000); 3081 3082 /* PHY auto speed down */ 3083 rtl_writephy(tp, 0x1f, 0x0007); 3084 rtl_writephy(tp, 0x1e, 0x002d); 3085 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000); 3086 rtl_writephy(tp, 0x1f, 0x0000); 3087 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3088 3089 /* Improve 10M EEE waveform */ 3090 rtl_writephy(tp, 0x1f, 0x0005); 3091 rtl_writephy(tp, 0x05, 0x8b86); 3092 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000); 3093 rtl_writephy(tp, 0x1f, 0x0000); 3094 3095 rtl8168f_config_eee_phy(tp); 3096 rtl_enable_eee(tp); 3097 } 3098 3099 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp) 3100 { 3101 static const struct phy_reg phy_reg_init[] = { 3102 /* Channel estimation fine tune */ 3103 { 0x1f, 0x0003 }, 3104 { 0x09, 0xa20f }, 3105 { 0x1f, 0x0000 }, 3106 3107 /* Modify green table for giga & fnet */ 3108 { 0x1f, 0x0005 }, 3109 { 0x05, 0x8b55 }, 3110 { 0x06, 0x0000 }, 3111 { 0x05, 0x8b5e }, 3112 { 0x06, 0x0000 }, 3113 { 0x05, 0x8b67 }, 3114 { 0x06, 0x0000 }, 3115 { 0x05, 0x8b70 }, 3116 { 0x06, 0x0000 }, 3117 { 0x1f, 0x0000 }, 3118 { 0x1f, 0x0007 }, 3119 { 0x1e, 0x0078 }, 3120 { 0x17, 0x0000 }, 3121 { 0x19, 0x00fb }, 3122 { 0x1f, 0x0000 }, 3123 3124 /* Modify green table for 10M */ 3125 { 0x1f, 0x0005 }, 3126 { 0x05, 0x8b79 }, 3127 { 0x06, 0xaa00 }, 3128 { 0x1f, 0x0000 }, 3129 3130 /* Disable hiimpedance detection (RTCT) */ 3131 { 0x1f, 0x0003 }, 3132 { 0x01, 0x328a }, 3133 { 0x1f, 0x0000 } 3134 }; 3135 3136 rtl_apply_firmware(tp); 3137 3138 rtl_writephy_batch(tp, phy_reg_init); 3139 3140 rtl8168f_hw_phy_config(tp); 3141 3142 /* Improve 2-pair detection performance */ 3143 rtl_writephy(tp, 0x1f, 0x0005); 3144 rtl_writephy(tp, 0x05, 0x8b85); 3145 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3146 rtl_writephy(tp, 0x1f, 0x0000); 3147 } 3148 3149 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp) 3150 { 3151 rtl_apply_firmware(tp); 3152 3153 rtl8168f_hw_phy_config(tp); 3154 } 3155 3156 static void rtl8411_hw_phy_config(struct rtl8169_private *tp) 3157 { 3158 static const struct phy_reg phy_reg_init[] = { 3159 /* Channel estimation fine tune */ 3160 { 0x1f, 0x0003 }, 3161 { 0x09, 0xa20f }, 3162 { 0x1f, 0x0000 }, 3163 3164 /* Modify green table for giga & fnet */ 3165 { 0x1f, 0x0005 }, 3166 { 0x05, 0x8b55 }, 3167 { 0x06, 0x0000 }, 3168 { 0x05, 0x8b5e }, 3169 { 0x06, 0x0000 }, 3170 { 0x05, 0x8b67 }, 3171 { 0x06, 0x0000 }, 3172 { 0x05, 0x8b70 }, 3173 { 0x06, 0x0000 }, 3174 { 0x1f, 0x0000 }, 3175 { 0x1f, 0x0007 }, 3176 { 0x1e, 0x0078 }, 3177 { 0x17, 0x0000 }, 3178 { 0x19, 0x00aa }, 3179 { 0x1f, 0x0000 }, 3180 3181 /* Modify green table for 10M */ 3182 { 0x1f, 0x0005 }, 3183 { 0x05, 0x8b79 }, 3184 { 0x06, 0xaa00 }, 3185 { 0x1f, 0x0000 }, 3186 3187 /* Disable hiimpedance detection (RTCT) */ 3188 { 0x1f, 0x0003 }, 3189 { 0x01, 0x328a }, 3190 { 0x1f, 0x0000 } 3191 }; 3192 3193 3194 rtl_apply_firmware(tp); 3195 3196 rtl8168f_hw_phy_config(tp); 3197 3198 /* Improve 2-pair detection performance */ 3199 rtl_writephy(tp, 0x1f, 0x0005); 3200 rtl_writephy(tp, 0x05, 0x8b85); 3201 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000); 3202 rtl_writephy(tp, 0x1f, 0x0000); 3203 3204 rtl_writephy_batch(tp, phy_reg_init); 3205 3206 /* Modify green table for giga */ 3207 rtl_writephy(tp, 0x1f, 0x0005); 3208 rtl_writephy(tp, 0x05, 0x8b54); 3209 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); 3210 rtl_writephy(tp, 0x05, 0x8b5d); 3211 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800); 3212 rtl_writephy(tp, 0x05, 0x8a7c); 3213 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3214 rtl_writephy(tp, 0x05, 0x8a7f); 3215 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000); 3216 rtl_writephy(tp, 0x05, 0x8a82); 3217 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3218 rtl_writephy(tp, 0x05, 0x8a85); 3219 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3220 rtl_writephy(tp, 0x05, 0x8a88); 3221 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100); 3222 rtl_writephy(tp, 0x1f, 0x0000); 3223 3224 /* uc same-seed solution */ 3225 rtl_writephy(tp, 0x1f, 0x0005); 3226 rtl_writephy(tp, 0x05, 0x8b85); 3227 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000); 3228 rtl_writephy(tp, 0x1f, 0x0000); 3229 3230 /* Green feature */ 3231 rtl_writephy(tp, 0x1f, 0x0003); 3232 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001); 3233 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400); 3234 rtl_writephy(tp, 0x1f, 0x0000); 3235 } 3236 3237 static void rtl8168g_disable_aldps(struct rtl8169_private *tp) 3238 { 3239 phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0); 3240 } 3241 3242 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp) 3243 { 3244 struct phy_device *phydev = tp->phydev; 3245 3246 phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0); 3247 phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6)); 3248 phy_write(phydev, 0x1f, 0x0a43); 3249 phy_write(phydev, 0x13, 0x8084); 3250 phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13)); 3251 phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0)); 3252 3253 phy_write(phydev, 0x1f, 0x0000); 3254 } 3255 3256 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp) 3257 { 3258 int ret; 3259 3260 rtl_apply_firmware(tp); 3261 3262 ret = phy_read_paged(tp->phydev, 0x0a46, 0x10); 3263 if (ret & BIT(8)) 3264 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0); 3265 else 3266 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15)); 3267 3268 ret = phy_read_paged(tp->phydev, 0x0a46, 0x13); 3269 if (ret & BIT(8)) 3270 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1)); 3271 else 3272 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0); 3273 3274 /* Enable PHY auto speed down */ 3275 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3276 3277 rtl8168g_phy_adjust_10m_aldps(tp); 3278 3279 /* EEE auto-fallback function */ 3280 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3281 3282 /* Enable UC LPF tune function */ 3283 rtl_writephy(tp, 0x1f, 0x0a43); 3284 rtl_writephy(tp, 0x13, 0x8012); 3285 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3286 3287 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3288 3289 /* Improve SWR Efficiency */ 3290 rtl_writephy(tp, 0x1f, 0x0bcd); 3291 rtl_writephy(tp, 0x14, 0x5065); 3292 rtl_writephy(tp, 0x14, 0xd065); 3293 rtl_writephy(tp, 0x1f, 0x0bc8); 3294 rtl_writephy(tp, 0x11, 0x5655); 3295 rtl_writephy(tp, 0x1f, 0x0bcd); 3296 rtl_writephy(tp, 0x14, 0x1065); 3297 rtl_writephy(tp, 0x14, 0x9065); 3298 rtl_writephy(tp, 0x14, 0x1065); 3299 rtl_writephy(tp, 0x1f, 0x0000); 3300 3301 rtl8168g_disable_aldps(tp); 3302 rtl8168g_config_eee_phy(tp); 3303 rtl_enable_eee(tp); 3304 } 3305 3306 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp) 3307 { 3308 rtl_apply_firmware(tp); 3309 rtl8168g_config_eee_phy(tp); 3310 rtl_enable_eee(tp); 3311 } 3312 3313 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp) 3314 { 3315 u16 dout_tapbin; 3316 u32 data; 3317 3318 rtl_apply_firmware(tp); 3319 3320 /* CHN EST parameters adjust - giga master */ 3321 rtl_writephy(tp, 0x1f, 0x0a43); 3322 rtl_writephy(tp, 0x13, 0x809b); 3323 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800); 3324 rtl_writephy(tp, 0x13, 0x80a2); 3325 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00); 3326 rtl_writephy(tp, 0x13, 0x80a4); 3327 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00); 3328 rtl_writephy(tp, 0x13, 0x809c); 3329 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00); 3330 rtl_writephy(tp, 0x1f, 0x0000); 3331 3332 /* CHN EST parameters adjust - giga slave */ 3333 rtl_writephy(tp, 0x1f, 0x0a43); 3334 rtl_writephy(tp, 0x13, 0x80ad); 3335 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800); 3336 rtl_writephy(tp, 0x13, 0x80b4); 3337 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00); 3338 rtl_writephy(tp, 0x13, 0x80ac); 3339 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00); 3340 rtl_writephy(tp, 0x1f, 0x0000); 3341 3342 /* CHN EST parameters adjust - fnet */ 3343 rtl_writephy(tp, 0x1f, 0x0a43); 3344 rtl_writephy(tp, 0x13, 0x808e); 3345 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00); 3346 rtl_writephy(tp, 0x13, 0x8090); 3347 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00); 3348 rtl_writephy(tp, 0x13, 0x8092); 3349 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00); 3350 rtl_writephy(tp, 0x1f, 0x0000); 3351 3352 /* enable R-tune & PGA-retune function */ 3353 dout_tapbin = 0; 3354 rtl_writephy(tp, 0x1f, 0x0a46); 3355 data = rtl_readphy(tp, 0x13); 3356 data &= 3; 3357 data <<= 2; 3358 dout_tapbin |= data; 3359 data = rtl_readphy(tp, 0x12); 3360 data &= 0xc000; 3361 data >>= 14; 3362 dout_tapbin |= data; 3363 dout_tapbin = ~(dout_tapbin^0x08); 3364 dout_tapbin <<= 12; 3365 dout_tapbin &= 0xf000; 3366 rtl_writephy(tp, 0x1f, 0x0a43); 3367 rtl_writephy(tp, 0x13, 0x827a); 3368 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3369 rtl_writephy(tp, 0x13, 0x827b); 3370 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3371 rtl_writephy(tp, 0x13, 0x827c); 3372 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3373 rtl_writephy(tp, 0x13, 0x827d); 3374 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000); 3375 3376 rtl_writephy(tp, 0x1f, 0x0a43); 3377 rtl_writephy(tp, 0x13, 0x0811); 3378 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); 3379 rtl_writephy(tp, 0x1f, 0x0a42); 3380 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); 3381 rtl_writephy(tp, 0x1f, 0x0000); 3382 3383 /* enable GPHY 10M */ 3384 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3385 3386 /* SAR ADC performance */ 3387 phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14)); 3388 3389 rtl_writephy(tp, 0x1f, 0x0a43); 3390 rtl_writephy(tp, 0x13, 0x803f); 3391 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3392 rtl_writephy(tp, 0x13, 0x8047); 3393 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3394 rtl_writephy(tp, 0x13, 0x804f); 3395 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3396 rtl_writephy(tp, 0x13, 0x8057); 3397 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3398 rtl_writephy(tp, 0x13, 0x805f); 3399 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3400 rtl_writephy(tp, 0x13, 0x8067); 3401 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3402 rtl_writephy(tp, 0x13, 0x806f); 3403 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000); 3404 rtl_writephy(tp, 0x1f, 0x0000); 3405 3406 /* disable phy pfm mode */ 3407 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3408 3409 rtl8168g_disable_aldps(tp); 3410 rtl8168g_config_eee_phy(tp); 3411 rtl_enable_eee(tp); 3412 } 3413 3414 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp) 3415 { 3416 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0; 3417 u16 rlen; 3418 u32 data; 3419 3420 rtl_apply_firmware(tp); 3421 3422 /* CHIN EST parameter update */ 3423 rtl_writephy(tp, 0x1f, 0x0a43); 3424 rtl_writephy(tp, 0x13, 0x808a); 3425 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f); 3426 rtl_writephy(tp, 0x1f, 0x0000); 3427 3428 /* enable R-tune & PGA-retune function */ 3429 rtl_writephy(tp, 0x1f, 0x0a43); 3430 rtl_writephy(tp, 0x13, 0x0811); 3431 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000); 3432 rtl_writephy(tp, 0x1f, 0x0a42); 3433 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000); 3434 rtl_writephy(tp, 0x1f, 0x0000); 3435 3436 /* enable GPHY 10M */ 3437 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11)); 3438 3439 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 3440 data = r8168_mac_ocp_read(tp, 0xdd02); 3441 ioffset_p3 = ((data & 0x80)>>7); 3442 ioffset_p3 <<= 3; 3443 3444 data = r8168_mac_ocp_read(tp, 0xdd00); 3445 ioffset_p3 |= ((data & (0xe000))>>13); 3446 ioffset_p2 = ((data & (0x1e00))>>9); 3447 ioffset_p1 = ((data & (0x01e0))>>5); 3448 ioffset_p0 = ((data & 0x0010)>>4); 3449 ioffset_p0 <<= 3; 3450 ioffset_p0 |= (data & (0x07)); 3451 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0); 3452 3453 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) || 3454 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) { 3455 rtl_writephy(tp, 0x1f, 0x0bcf); 3456 rtl_writephy(tp, 0x16, data); 3457 rtl_writephy(tp, 0x1f, 0x0000); 3458 } 3459 3460 /* Modify rlen (TX LPF corner frequency) level */ 3461 rtl_writephy(tp, 0x1f, 0x0bcd); 3462 data = rtl_readphy(tp, 0x16); 3463 data &= 0x000f; 3464 rlen = 0; 3465 if (data > 3) 3466 rlen = data - 3; 3467 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12); 3468 rtl_writephy(tp, 0x17, data); 3469 rtl_writephy(tp, 0x1f, 0x0bcd); 3470 rtl_writephy(tp, 0x1f, 0x0000); 3471 3472 /* disable phy pfm mode */ 3473 phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0); 3474 3475 rtl8168g_disable_aldps(tp); 3476 rtl8168g_config_eee_phy(tp); 3477 rtl_enable_eee(tp); 3478 } 3479 3480 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp) 3481 { 3482 /* Enable PHY auto speed down */ 3483 phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2)); 3484 3485 rtl8168g_phy_adjust_10m_aldps(tp); 3486 3487 /* Enable EEE auto-fallback function */ 3488 phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2)); 3489 3490 /* Enable UC LPF tune function */ 3491 rtl_writephy(tp, 0x1f, 0x0a43); 3492 rtl_writephy(tp, 0x13, 0x8012); 3493 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3494 rtl_writephy(tp, 0x1f, 0x0000); 3495 3496 /* set rg_sel_sdm_rate */ 3497 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3498 3499 rtl8168g_disable_aldps(tp); 3500 rtl8168g_config_eee_phy(tp); 3501 rtl_enable_eee(tp); 3502 } 3503 3504 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp) 3505 { 3506 rtl8168g_phy_adjust_10m_aldps(tp); 3507 3508 /* Enable UC LPF tune function */ 3509 rtl_writephy(tp, 0x1f, 0x0a43); 3510 rtl_writephy(tp, 0x13, 0x8012); 3511 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000); 3512 rtl_writephy(tp, 0x1f, 0x0000); 3513 3514 /* Set rg_sel_sdm_rate */ 3515 phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14)); 3516 3517 /* Channel estimation parameters */ 3518 rtl_writephy(tp, 0x1f, 0x0a43); 3519 rtl_writephy(tp, 0x13, 0x80f3); 3520 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff); 3521 rtl_writephy(tp, 0x13, 0x80f0); 3522 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff); 3523 rtl_writephy(tp, 0x13, 0x80ef); 3524 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff); 3525 rtl_writephy(tp, 0x13, 0x80f6); 3526 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff); 3527 rtl_writephy(tp, 0x13, 0x80ec); 3528 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff); 3529 rtl_writephy(tp, 0x13, 0x80ed); 3530 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); 3531 rtl_writephy(tp, 0x13, 0x80f2); 3532 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff); 3533 rtl_writephy(tp, 0x13, 0x80f4); 3534 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff); 3535 rtl_writephy(tp, 0x1f, 0x0a43); 3536 rtl_writephy(tp, 0x13, 0x8110); 3537 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff); 3538 rtl_writephy(tp, 0x13, 0x810f); 3539 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff); 3540 rtl_writephy(tp, 0x13, 0x8111); 3541 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff); 3542 rtl_writephy(tp, 0x13, 0x8113); 3543 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff); 3544 rtl_writephy(tp, 0x13, 0x8115); 3545 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff); 3546 rtl_writephy(tp, 0x13, 0x810e); 3547 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff); 3548 rtl_writephy(tp, 0x13, 0x810c); 3549 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff); 3550 rtl_writephy(tp, 0x13, 0x810b); 3551 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff); 3552 rtl_writephy(tp, 0x1f, 0x0a43); 3553 rtl_writephy(tp, 0x13, 0x80d1); 3554 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff); 3555 rtl_writephy(tp, 0x13, 0x80cd); 3556 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff); 3557 rtl_writephy(tp, 0x13, 0x80d3); 3558 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff); 3559 rtl_writephy(tp, 0x13, 0x80d5); 3560 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff); 3561 rtl_writephy(tp, 0x13, 0x80d7); 3562 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff); 3563 3564 /* Force PWM-mode */ 3565 rtl_writephy(tp, 0x1f, 0x0bcd); 3566 rtl_writephy(tp, 0x14, 0x5065); 3567 rtl_writephy(tp, 0x14, 0xd065); 3568 rtl_writephy(tp, 0x1f, 0x0bc8); 3569 rtl_writephy(tp, 0x12, 0x00ed); 3570 rtl_writephy(tp, 0x1f, 0x0bcd); 3571 rtl_writephy(tp, 0x14, 0x1065); 3572 rtl_writephy(tp, 0x14, 0x9065); 3573 rtl_writephy(tp, 0x14, 0x1065); 3574 rtl_writephy(tp, 0x1f, 0x0000); 3575 3576 rtl8168g_disable_aldps(tp); 3577 rtl8168g_config_eee_phy(tp); 3578 rtl_enable_eee(tp); 3579 } 3580 3581 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) 3582 { 3583 static const struct phy_reg phy_reg_init[] = { 3584 { 0x1f, 0x0003 }, 3585 { 0x08, 0x441d }, 3586 { 0x01, 0x9100 }, 3587 { 0x1f, 0x0000 } 3588 }; 3589 3590 rtl_writephy(tp, 0x1f, 0x0000); 3591 rtl_patchphy(tp, 0x11, 1 << 12); 3592 rtl_patchphy(tp, 0x19, 1 << 13); 3593 rtl_patchphy(tp, 0x10, 1 << 15); 3594 3595 rtl_writephy_batch(tp, phy_reg_init); 3596 } 3597 3598 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) 3599 { 3600 static const struct phy_reg phy_reg_init[] = { 3601 { 0x1f, 0x0005 }, 3602 { 0x1a, 0x0000 }, 3603 { 0x1f, 0x0000 }, 3604 3605 { 0x1f, 0x0004 }, 3606 { 0x1c, 0x0000 }, 3607 { 0x1f, 0x0000 }, 3608 3609 { 0x1f, 0x0001 }, 3610 { 0x15, 0x7701 }, 3611 { 0x1f, 0x0000 } 3612 }; 3613 3614 /* Disable ALDPS before ram code */ 3615 rtl_writephy(tp, 0x1f, 0x0000); 3616 rtl_writephy(tp, 0x18, 0x0310); 3617 msleep(100); 3618 3619 rtl_apply_firmware(tp); 3620 3621 rtl_writephy_batch(tp, phy_reg_init); 3622 } 3623 3624 static void rtl8402_hw_phy_config(struct rtl8169_private *tp) 3625 { 3626 /* Disable ALDPS before setting firmware */ 3627 rtl_writephy(tp, 0x1f, 0x0000); 3628 rtl_writephy(tp, 0x18, 0x0310); 3629 msleep(20); 3630 3631 rtl_apply_firmware(tp); 3632 3633 /* EEE setting */ 3634 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3635 rtl_writephy(tp, 0x1f, 0x0004); 3636 rtl_writephy(tp, 0x10, 0x401f); 3637 rtl_writephy(tp, 0x19, 0x7030); 3638 rtl_writephy(tp, 0x1f, 0x0000); 3639 } 3640 3641 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) 3642 { 3643 static const struct phy_reg phy_reg_init[] = { 3644 { 0x1f, 0x0004 }, 3645 { 0x10, 0xc07f }, 3646 { 0x19, 0x7030 }, 3647 { 0x1f, 0x0000 } 3648 }; 3649 3650 /* Disable ALDPS before ram code */ 3651 rtl_writephy(tp, 0x1f, 0x0000); 3652 rtl_writephy(tp, 0x18, 0x0310); 3653 msleep(100); 3654 3655 rtl_apply_firmware(tp); 3656 3657 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3658 rtl_writephy_batch(tp, phy_reg_init); 3659 3660 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3661 } 3662 3663 static void rtl_hw_phy_config(struct net_device *dev) 3664 { 3665 static const rtl_generic_fct phy_configs[] = { 3666 /* PCI devices. */ 3667 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config, 3668 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config, 3669 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config, 3670 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config, 3671 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config, 3672 /* PCI-E devices. */ 3673 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config, 3674 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config, 3675 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config, 3676 [RTL_GIGA_MAC_VER_10] = NULL, 3677 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config, 3678 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config, 3679 [RTL_GIGA_MAC_VER_13] = NULL, 3680 [RTL_GIGA_MAC_VER_14] = NULL, 3681 [RTL_GIGA_MAC_VER_15] = NULL, 3682 [RTL_GIGA_MAC_VER_16] = NULL, 3683 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config, 3684 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config, 3685 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config, 3686 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config, 3687 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config, 3688 [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config, 3689 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config, 3690 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config, 3691 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config, 3692 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config, 3693 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config, 3694 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config, 3695 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config, 3696 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config, 3697 [RTL_GIGA_MAC_VER_31] = NULL, 3698 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config, 3699 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config, 3700 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config, 3701 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config, 3702 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config, 3703 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config, 3704 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config, 3705 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config, 3706 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config, 3707 [RTL_GIGA_MAC_VER_41] = NULL, 3708 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config, 3709 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config, 3710 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config, 3711 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config, 3712 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config, 3713 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config, 3714 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config, 3715 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config, 3716 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config, 3717 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config, 3718 }; 3719 struct rtl8169_private *tp = netdev_priv(dev); 3720 3721 if (phy_configs[tp->mac_version]) 3722 phy_configs[tp->mac_version](tp); 3723 } 3724 3725 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 3726 { 3727 if (!test_and_set_bit(flag, tp->wk.flags)) 3728 schedule_work(&tp->wk.work); 3729 } 3730 3731 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) 3732 { 3733 rtl_hw_phy_config(dev); 3734 3735 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 3736 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 3737 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 3738 netif_dbg(tp, drv, dev, 3739 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 3740 RTL_W8(tp, 0x82, 0x01); 3741 } 3742 3743 /* We may have called phy_speed_down before */ 3744 phy_speed_up(tp->phydev); 3745 3746 genphy_soft_reset(tp->phydev); 3747 } 3748 3749 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 3750 { 3751 rtl_lock_work(tp); 3752 3753 rtl_unlock_config_regs(tp); 3754 3755 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 3756 RTL_R32(tp, MAC4); 3757 3758 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3759 RTL_R32(tp, MAC0); 3760 3761 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 3762 rtl_rar_exgmac_set(tp, addr); 3763 3764 rtl_lock_config_regs(tp); 3765 3766 rtl_unlock_work(tp); 3767 } 3768 3769 static int rtl_set_mac_address(struct net_device *dev, void *p) 3770 { 3771 struct rtl8169_private *tp = netdev_priv(dev); 3772 struct device *d = tp_to_dev(tp); 3773 int ret; 3774 3775 ret = eth_mac_addr(dev, p); 3776 if (ret) 3777 return ret; 3778 3779 pm_runtime_get_noresume(d); 3780 3781 if (pm_runtime_active(d)) 3782 rtl_rar_set(tp, dev->dev_addr); 3783 3784 pm_runtime_put_noidle(d); 3785 3786 return 0; 3787 } 3788 3789 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3790 { 3791 struct rtl8169_private *tp = netdev_priv(dev); 3792 3793 if (!netif_running(dev)) 3794 return -ENODEV; 3795 3796 return phy_mii_ioctl(tp->phydev, ifr, cmd); 3797 } 3798 3799 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 3800 { 3801 switch (tp->mac_version) { 3802 case RTL_GIGA_MAC_VER_25: 3803 case RTL_GIGA_MAC_VER_26: 3804 case RTL_GIGA_MAC_VER_29: 3805 case RTL_GIGA_MAC_VER_30: 3806 case RTL_GIGA_MAC_VER_32: 3807 case RTL_GIGA_MAC_VER_33: 3808 case RTL_GIGA_MAC_VER_34: 3809 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51: 3810 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 3811 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 3812 break; 3813 default: 3814 break; 3815 } 3816 } 3817 3818 static void rtl_pll_power_down(struct rtl8169_private *tp) 3819 { 3820 if (r8168_check_dash(tp)) 3821 return; 3822 3823 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 3824 tp->mac_version == RTL_GIGA_MAC_VER_33) 3825 rtl_ephy_write(tp, 0x19, 0xff64); 3826 3827 if (device_may_wakeup(tp_to_dev(tp))) { 3828 phy_speed_down(tp->phydev, false); 3829 rtl_wol_suspend_quirk(tp); 3830 return; 3831 } 3832 3833 switch (tp->mac_version) { 3834 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3835 case RTL_GIGA_MAC_VER_37: 3836 case RTL_GIGA_MAC_VER_39: 3837 case RTL_GIGA_MAC_VER_43: 3838 case RTL_GIGA_MAC_VER_44: 3839 case RTL_GIGA_MAC_VER_45: 3840 case RTL_GIGA_MAC_VER_46: 3841 case RTL_GIGA_MAC_VER_47: 3842 case RTL_GIGA_MAC_VER_48: 3843 case RTL_GIGA_MAC_VER_50: 3844 case RTL_GIGA_MAC_VER_51: 3845 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3846 break; 3847 case RTL_GIGA_MAC_VER_40: 3848 case RTL_GIGA_MAC_VER_41: 3849 case RTL_GIGA_MAC_VER_49: 3850 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3851 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 3852 break; 3853 default: 3854 break; 3855 } 3856 } 3857 3858 static void rtl_pll_power_up(struct rtl8169_private *tp) 3859 { 3860 switch (tp->mac_version) { 3861 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 3862 case RTL_GIGA_MAC_VER_37: 3863 case RTL_GIGA_MAC_VER_39: 3864 case RTL_GIGA_MAC_VER_43: 3865 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 3866 break; 3867 case RTL_GIGA_MAC_VER_44: 3868 case RTL_GIGA_MAC_VER_45: 3869 case RTL_GIGA_MAC_VER_46: 3870 case RTL_GIGA_MAC_VER_47: 3871 case RTL_GIGA_MAC_VER_48: 3872 case RTL_GIGA_MAC_VER_50: 3873 case RTL_GIGA_MAC_VER_51: 3874 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3875 break; 3876 case RTL_GIGA_MAC_VER_40: 3877 case RTL_GIGA_MAC_VER_41: 3878 case RTL_GIGA_MAC_VER_49: 3879 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 3880 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 3881 break; 3882 default: 3883 break; 3884 } 3885 3886 phy_resume(tp->phydev); 3887 /* give MAC/PHY some time to resume */ 3888 msleep(20); 3889 } 3890 3891 static void rtl_init_rxcfg(struct rtl8169_private *tp) 3892 { 3893 switch (tp->mac_version) { 3894 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 3895 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 3896 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 3897 break; 3898 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 3899 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 3900 case RTL_GIGA_MAC_VER_38: 3901 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 3902 break; 3903 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 3904 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 3905 break; 3906 default: 3907 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 3908 break; 3909 } 3910 } 3911 3912 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 3913 { 3914 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 3915 } 3916 3917 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 3918 { 3919 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 3920 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 3921 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); 3922 } 3923 3924 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 3925 { 3926 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 3927 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 3928 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 3929 } 3930 3931 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 3932 { 3933 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 3934 } 3935 3936 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 3937 { 3938 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 3939 } 3940 3941 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 3942 { 3943 RTL_W8(tp, MaxTxPacketSize, 0x3f); 3944 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 3945 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 3946 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); 3947 } 3948 3949 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 3950 { 3951 RTL_W8(tp, MaxTxPacketSize, 0x0c); 3952 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 3953 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 3954 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 3955 } 3956 3957 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) 3958 { 3959 rtl_tx_performance_tweak(tp, 3960 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN); 3961 } 3962 3963 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) 3964 { 3965 rtl_tx_performance_tweak(tp, 3966 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN); 3967 } 3968 3969 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 3970 { 3971 r8168b_0_hw_jumbo_enable(tp); 3972 3973 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 3974 } 3975 3976 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 3977 { 3978 r8168b_0_hw_jumbo_disable(tp); 3979 3980 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 3981 } 3982 3983 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) 3984 { 3985 rtl_unlock_config_regs(tp); 3986 switch (tp->mac_version) { 3987 case RTL_GIGA_MAC_VER_11: 3988 r8168b_0_hw_jumbo_enable(tp); 3989 break; 3990 case RTL_GIGA_MAC_VER_12: 3991 case RTL_GIGA_MAC_VER_17: 3992 r8168b_1_hw_jumbo_enable(tp); 3993 break; 3994 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 3995 r8168c_hw_jumbo_enable(tp); 3996 break; 3997 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 3998 r8168dp_hw_jumbo_enable(tp); 3999 break; 4000 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 4001 r8168e_hw_jumbo_enable(tp); 4002 break; 4003 default: 4004 break; 4005 } 4006 rtl_lock_config_regs(tp); 4007 } 4008 4009 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) 4010 { 4011 rtl_unlock_config_regs(tp); 4012 switch (tp->mac_version) { 4013 case RTL_GIGA_MAC_VER_11: 4014 r8168b_0_hw_jumbo_disable(tp); 4015 break; 4016 case RTL_GIGA_MAC_VER_12: 4017 case RTL_GIGA_MAC_VER_17: 4018 r8168b_1_hw_jumbo_disable(tp); 4019 break; 4020 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 4021 r8168c_hw_jumbo_disable(tp); 4022 break; 4023 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 4024 r8168dp_hw_jumbo_disable(tp); 4025 break; 4026 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34: 4027 r8168e_hw_jumbo_disable(tp); 4028 break; 4029 default: 4030 break; 4031 } 4032 rtl_lock_config_regs(tp); 4033 } 4034 4035 DECLARE_RTL_COND(rtl_chipcmd_cond) 4036 { 4037 return RTL_R8(tp, ChipCmd) & CmdReset; 4038 } 4039 4040 static void rtl_hw_reset(struct rtl8169_private *tp) 4041 { 4042 RTL_W8(tp, ChipCmd, CmdReset); 4043 4044 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 4045 } 4046 4047 static void rtl_request_firmware(struct rtl8169_private *tp) 4048 { 4049 struct rtl_fw *rtl_fw; 4050 4051 /* firmware loaded already or no firmware available */ 4052 if (tp->rtl_fw || !tp->fw_name) 4053 return; 4054 4055 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 4056 if (!rtl_fw) { 4057 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n"); 4058 return; 4059 } 4060 4061 rtl_fw->phy_write = rtl_writephy; 4062 rtl_fw->phy_read = rtl_readphy; 4063 rtl_fw->mac_mcu_write = mac_mcu_write; 4064 rtl_fw->mac_mcu_read = mac_mcu_read; 4065 rtl_fw->fw_name = tp->fw_name; 4066 rtl_fw->dev = tp_to_dev(tp); 4067 4068 if (rtl_fw_request_firmware(rtl_fw)) 4069 kfree(rtl_fw); 4070 else 4071 tp->rtl_fw = rtl_fw; 4072 } 4073 4074 static void rtl_rx_close(struct rtl8169_private *tp) 4075 { 4076 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 4077 } 4078 4079 DECLARE_RTL_COND(rtl_npq_cond) 4080 { 4081 return RTL_R8(tp, TxPoll) & NPQ; 4082 } 4083 4084 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 4085 { 4086 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 4087 } 4088 4089 static void rtl8169_hw_reset(struct rtl8169_private *tp) 4090 { 4091 /* Disable interrupts */ 4092 rtl8169_irq_mask_and_ack(tp); 4093 4094 rtl_rx_close(tp); 4095 4096 switch (tp->mac_version) { 4097 case RTL_GIGA_MAC_VER_27: 4098 case RTL_GIGA_MAC_VER_28: 4099 case RTL_GIGA_MAC_VER_31: 4100 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42); 4101 break; 4102 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4103 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51: 4104 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4105 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4106 break; 4107 default: 4108 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4109 udelay(100); 4110 break; 4111 } 4112 4113 rtl_hw_reset(tp); 4114 } 4115 4116 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 4117 { 4118 u32 val = TX_DMA_BURST << TxDMAShift | 4119 InterFrameGap << TxInterFrameGapShift; 4120 4121 if (rtl_is_8168evl_up(tp)) 4122 val |= TXCFG_AUTO_FIFO; 4123 4124 RTL_W32(tp, TxConfig, val); 4125 } 4126 4127 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 4128 { 4129 /* Low hurts. Let's disable the filtering. */ 4130 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 4131 } 4132 4133 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 4134 { 4135 /* 4136 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 4137 * register to be written before TxDescAddrLow to work. 4138 * Switching from MMIO to I/O access fixes the issue as well. 4139 */ 4140 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 4141 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 4142 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 4143 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 4144 } 4145 4146 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version) 4147 { 4148 u32 val; 4149 4150 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 4151 val = 0x000fff00; 4152 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 4153 val = 0x00ffff00; 4154 else 4155 return; 4156 4157 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 4158 val |= 0xff; 4159 4160 RTL_W32(tp, 0x7c, val); 4161 } 4162 4163 static void rtl_set_rx_mode(struct net_device *dev) 4164 { 4165 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 4166 /* Multicast hash filter */ 4167 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 4168 struct rtl8169_private *tp = netdev_priv(dev); 4169 u32 tmp; 4170 4171 if (dev->flags & IFF_PROMISC) { 4172 /* Unconditionally log net taps. */ 4173 netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); 4174 rx_mode |= AcceptAllPhys; 4175 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 4176 dev->flags & IFF_ALLMULTI || 4177 tp->mac_version == RTL_GIGA_MAC_VER_35) { 4178 /* accept all multicasts */ 4179 } else if (netdev_mc_empty(dev)) { 4180 rx_mode &= ~AcceptMulticast; 4181 } else { 4182 struct netdev_hw_addr *ha; 4183 4184 mc_filter[1] = mc_filter[0] = 0; 4185 netdev_for_each_mc_addr(ha, dev) { 4186 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 4187 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 4188 } 4189 4190 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 4191 tmp = mc_filter[0]; 4192 mc_filter[0] = swab32(mc_filter[1]); 4193 mc_filter[1] = swab32(tmp); 4194 } 4195 } 4196 4197 if (dev->features & NETIF_F_RXALL) 4198 rx_mode |= (AcceptErr | AcceptRunt); 4199 4200 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 4201 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 4202 4203 tmp = RTL_R32(tp, RxConfig); 4204 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); 4205 } 4206 4207 DECLARE_RTL_COND(rtl_csiar_cond) 4208 { 4209 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 4210 } 4211 4212 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 4213 { 4214 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4215 4216 RTL_W32(tp, CSIDR, value); 4217 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 4218 CSIAR_BYTE_ENABLE | func << 16); 4219 4220 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 4221 } 4222 4223 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 4224 { 4225 u32 func = PCI_FUNC(tp->pci_dev->devfn); 4226 4227 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 4228 CSIAR_BYTE_ENABLE); 4229 4230 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 4231 RTL_R32(tp, CSIDR) : ~0; 4232 } 4233 4234 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 4235 { 4236 struct pci_dev *pdev = tp->pci_dev; 4237 u32 csi; 4238 4239 /* According to Realtek the value at config space address 0x070f 4240 * controls the L0s/L1 entrance latency. We try standard ECAM access 4241 * first and if it fails fall back to CSI. 4242 */ 4243 if (pdev->cfg_size > 0x070f && 4244 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 4245 return; 4246 4247 netdev_notice_once(tp->dev, 4248 "No native access to PCI extended config space, falling back to CSI\n"); 4249 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 4250 rtl_csi_write(tp, 0x070c, csi | val << 24); 4251 } 4252 4253 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 4254 { 4255 rtl_csi_access_enable(tp, 0x27); 4256 } 4257 4258 struct ephy_info { 4259 unsigned int offset; 4260 u16 mask; 4261 u16 bits; 4262 }; 4263 4264 static void __rtl_ephy_init(struct rtl8169_private *tp, 4265 const struct ephy_info *e, int len) 4266 { 4267 u16 w; 4268 4269 while (len-- > 0) { 4270 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 4271 rtl_ephy_write(tp, e->offset, w); 4272 e++; 4273 } 4274 } 4275 4276 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 4277 4278 static void rtl_disable_clock_request(struct rtl8169_private *tp) 4279 { 4280 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 4281 PCI_EXP_LNKCTL_CLKREQ_EN); 4282 } 4283 4284 static void rtl_enable_clock_request(struct rtl8169_private *tp) 4285 { 4286 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 4287 PCI_EXP_LNKCTL_CLKREQ_EN); 4288 } 4289 4290 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 4291 { 4292 /* work around an issue when PCI reset occurs during L2/L3 state */ 4293 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 4294 } 4295 4296 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 4297 { 4298 /* Don't enable ASPM in the chip if OS can't control ASPM */ 4299 if (enable && tp->aspm_manageable) { 4300 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 4301 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 4302 } else { 4303 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4304 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4305 } 4306 4307 udelay(10); 4308 } 4309 4310 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 4311 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 4312 { 4313 /* Usage of dynamic vs. static FIFO is controlled by bit 4314 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 4315 */ 4316 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 4317 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 4318 } 4319 4320 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 4321 u8 low, u8 high) 4322 { 4323 /* FIFO thresholds for pause flow control */ 4324 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 4325 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 4326 } 4327 4328 static void rtl_hw_start_8168bb(struct rtl8169_private *tp) 4329 { 4330 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4331 4332 if (tp->dev->mtu <= ETH_DATA_LEN) { 4333 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B | 4334 PCI_EXP_DEVCTL_NOSNOOP_EN); 4335 } 4336 } 4337 4338 static void rtl_hw_start_8168bef(struct rtl8169_private *tp) 4339 { 4340 rtl_hw_start_8168bb(tp); 4341 4342 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 4343 } 4344 4345 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 4346 { 4347 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 4348 4349 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4350 4351 if (tp->dev->mtu <= ETH_DATA_LEN) 4352 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4353 4354 rtl_disable_clock_request(tp); 4355 } 4356 4357 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 4358 { 4359 static const struct ephy_info e_info_8168cp[] = { 4360 { 0x01, 0, 0x0001 }, 4361 { 0x02, 0x0800, 0x1000 }, 4362 { 0x03, 0, 0x0042 }, 4363 { 0x06, 0x0080, 0x0000 }, 4364 { 0x07, 0, 0x2000 } 4365 }; 4366 4367 rtl_set_def_aspm_entry_latency(tp); 4368 4369 rtl_ephy_init(tp, e_info_8168cp); 4370 4371 __rtl_hw_start_8168cp(tp); 4372 } 4373 4374 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 4375 { 4376 rtl_set_def_aspm_entry_latency(tp); 4377 4378 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4379 4380 if (tp->dev->mtu <= ETH_DATA_LEN) 4381 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4382 } 4383 4384 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 4385 { 4386 rtl_set_def_aspm_entry_latency(tp); 4387 4388 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 4389 4390 /* Magic. */ 4391 RTL_W8(tp, DBG_REG, 0x20); 4392 4393 if (tp->dev->mtu <= ETH_DATA_LEN) 4394 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4395 } 4396 4397 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 4398 { 4399 static const struct ephy_info e_info_8168c_1[] = { 4400 { 0x02, 0x0800, 0x1000 }, 4401 { 0x03, 0, 0x0002 }, 4402 { 0x06, 0x0080, 0x0000 } 4403 }; 4404 4405 rtl_set_def_aspm_entry_latency(tp); 4406 4407 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 4408 4409 rtl_ephy_init(tp, e_info_8168c_1); 4410 4411 __rtl_hw_start_8168cp(tp); 4412 } 4413 4414 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 4415 { 4416 static const struct ephy_info e_info_8168c_2[] = { 4417 { 0x01, 0, 0x0001 }, 4418 { 0x03, 0x0400, 0x0020 } 4419 }; 4420 4421 rtl_set_def_aspm_entry_latency(tp); 4422 4423 rtl_ephy_init(tp, e_info_8168c_2); 4424 4425 __rtl_hw_start_8168cp(tp); 4426 } 4427 4428 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 4429 { 4430 rtl_hw_start_8168c_2(tp); 4431 } 4432 4433 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 4434 { 4435 rtl_set_def_aspm_entry_latency(tp); 4436 4437 __rtl_hw_start_8168cp(tp); 4438 } 4439 4440 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 4441 { 4442 rtl_set_def_aspm_entry_latency(tp); 4443 4444 rtl_disable_clock_request(tp); 4445 4446 if (tp->dev->mtu <= ETH_DATA_LEN) 4447 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4448 } 4449 4450 static void rtl_hw_start_8168dp(struct rtl8169_private *tp) 4451 { 4452 rtl_set_def_aspm_entry_latency(tp); 4453 4454 if (tp->dev->mtu <= ETH_DATA_LEN) 4455 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4456 4457 rtl_disable_clock_request(tp); 4458 } 4459 4460 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 4461 { 4462 static const struct ephy_info e_info_8168d_4[] = { 4463 { 0x0b, 0x0000, 0x0048 }, 4464 { 0x19, 0x0020, 0x0050 }, 4465 { 0x0c, 0x0100, 0x0020 }, 4466 { 0x10, 0x0004, 0x0000 }, 4467 }; 4468 4469 rtl_set_def_aspm_entry_latency(tp); 4470 4471 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4472 4473 rtl_ephy_init(tp, e_info_8168d_4); 4474 4475 rtl_enable_clock_request(tp); 4476 } 4477 4478 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 4479 { 4480 static const struct ephy_info e_info_8168e_1[] = { 4481 { 0x00, 0x0200, 0x0100 }, 4482 { 0x00, 0x0000, 0x0004 }, 4483 { 0x06, 0x0002, 0x0001 }, 4484 { 0x06, 0x0000, 0x0030 }, 4485 { 0x07, 0x0000, 0x2000 }, 4486 { 0x00, 0x0000, 0x0020 }, 4487 { 0x03, 0x5800, 0x2000 }, 4488 { 0x03, 0x0000, 0x0001 }, 4489 { 0x01, 0x0800, 0x1000 }, 4490 { 0x07, 0x0000, 0x4000 }, 4491 { 0x1e, 0x0000, 0x2000 }, 4492 { 0x19, 0xffff, 0xfe6c }, 4493 { 0x0a, 0x0000, 0x0040 } 4494 }; 4495 4496 rtl_set_def_aspm_entry_latency(tp); 4497 4498 rtl_ephy_init(tp, e_info_8168e_1); 4499 4500 if (tp->dev->mtu <= ETH_DATA_LEN) 4501 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4502 4503 rtl_disable_clock_request(tp); 4504 4505 /* Reset tx FIFO pointer */ 4506 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 4507 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 4508 4509 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4510 } 4511 4512 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 4513 { 4514 static const struct ephy_info e_info_8168e_2[] = { 4515 { 0x09, 0x0000, 0x0080 }, 4516 { 0x19, 0x0000, 0x0224 }, 4517 { 0x00, 0x0000, 0x0004 }, 4518 { 0x0c, 0x3df0, 0x0200 }, 4519 }; 4520 4521 rtl_set_def_aspm_entry_latency(tp); 4522 4523 rtl_ephy_init(tp, e_info_8168e_2); 4524 4525 if (tp->dev->mtu <= ETH_DATA_LEN) 4526 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4527 4528 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4529 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4530 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4531 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4532 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 4533 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4534 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4535 4536 rtl_disable_clock_request(tp); 4537 4538 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4539 4540 rtl8168_config_eee_mac(tp); 4541 4542 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4543 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4544 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4545 4546 rtl_hw_aspm_clkreq_enable(tp, true); 4547 } 4548 4549 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 4550 { 4551 rtl_set_def_aspm_entry_latency(tp); 4552 4553 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4554 4555 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4556 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4557 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 4558 rtl_reset_packet_filter(tp); 4559 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 4560 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 4561 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 4562 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 4563 4564 rtl_disable_clock_request(tp); 4565 4566 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 4567 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 4568 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 4569 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 4570 4571 rtl8168_config_eee_mac(tp); 4572 } 4573 4574 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 4575 { 4576 static const struct ephy_info e_info_8168f_1[] = { 4577 { 0x06, 0x00c0, 0x0020 }, 4578 { 0x08, 0x0001, 0x0002 }, 4579 { 0x09, 0x0000, 0x0080 }, 4580 { 0x19, 0x0000, 0x0224 }, 4581 { 0x00, 0x0000, 0x0004 }, 4582 { 0x0c, 0x3df0, 0x0200 }, 4583 }; 4584 4585 rtl_hw_start_8168f(tp); 4586 4587 rtl_ephy_init(tp, e_info_8168f_1); 4588 4589 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 4590 } 4591 4592 static void rtl_hw_start_8411(struct rtl8169_private *tp) 4593 { 4594 static const struct ephy_info e_info_8168f_1[] = { 4595 { 0x06, 0x00c0, 0x0020 }, 4596 { 0x0f, 0xffff, 0x5200 }, 4597 { 0x19, 0x0000, 0x0224 }, 4598 { 0x00, 0x0000, 0x0004 }, 4599 { 0x0c, 0x3df0, 0x0200 }, 4600 }; 4601 4602 rtl_hw_start_8168f(tp); 4603 rtl_pcie_state_l2l3_disable(tp); 4604 4605 rtl_ephy_init(tp, e_info_8168f_1); 4606 4607 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 4608 } 4609 4610 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 4611 { 4612 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4613 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4614 4615 rtl_set_def_aspm_entry_latency(tp); 4616 4617 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4618 4619 rtl_reset_packet_filter(tp); 4620 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 4621 4622 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4623 4624 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4625 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4626 4627 rtl8168_config_eee_mac(tp); 4628 4629 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4630 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4631 4632 rtl_pcie_state_l2l3_disable(tp); 4633 } 4634 4635 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 4636 { 4637 static const struct ephy_info e_info_8168g_1[] = { 4638 { 0x00, 0x0008, 0x0000 }, 4639 { 0x0c, 0x3ff0, 0x0820 }, 4640 { 0x1e, 0x0000, 0x0001 }, 4641 { 0x19, 0x8000, 0x0000 } 4642 }; 4643 4644 rtl_hw_start_8168g(tp); 4645 4646 /* disable aspm and clock request before access ephy */ 4647 rtl_hw_aspm_clkreq_enable(tp, false); 4648 rtl_ephy_init(tp, e_info_8168g_1); 4649 rtl_hw_aspm_clkreq_enable(tp, true); 4650 } 4651 4652 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 4653 { 4654 static const struct ephy_info e_info_8168g_2[] = { 4655 { 0x00, 0x0008, 0x0000 }, 4656 { 0x0c, 0x3ff0, 0x0820 }, 4657 { 0x19, 0xffff, 0x7c00 }, 4658 { 0x1e, 0xffff, 0x20eb }, 4659 { 0x0d, 0xffff, 0x1666 }, 4660 { 0x00, 0xffff, 0x10a3 }, 4661 { 0x06, 0xffff, 0xf050 }, 4662 { 0x04, 0x0000, 0x0010 }, 4663 { 0x1d, 0x4000, 0x0000 }, 4664 }; 4665 4666 rtl_hw_start_8168g(tp); 4667 4668 /* disable aspm and clock request before access ephy */ 4669 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 4670 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 4671 rtl_ephy_init(tp, e_info_8168g_2); 4672 } 4673 4674 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 4675 { 4676 static const struct ephy_info e_info_8411_2[] = { 4677 { 0x00, 0x0008, 0x0000 }, 4678 { 0x0c, 0x37d0, 0x0820 }, 4679 { 0x1e, 0x0000, 0x0001 }, 4680 { 0x19, 0x8021, 0x0000 }, 4681 { 0x1e, 0x0000, 0x2000 }, 4682 { 0x0d, 0x0100, 0x0200 }, 4683 { 0x00, 0x0000, 0x0080 }, 4684 { 0x06, 0x0000, 0x0010 }, 4685 { 0x04, 0x0000, 0x0010 }, 4686 { 0x1d, 0x0000, 0x4000 }, 4687 }; 4688 4689 rtl_hw_start_8168g(tp); 4690 4691 /* disable aspm and clock request before access ephy */ 4692 rtl_hw_aspm_clkreq_enable(tp, false); 4693 rtl_ephy_init(tp, e_info_8411_2); 4694 4695 /* The following Realtek-provided magic fixes an issue with the RX unit 4696 * getting confused after the PHY having been powered-down. 4697 */ 4698 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 4699 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 4700 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 4701 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 4702 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 4703 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 4704 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 4705 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 4706 mdelay(3); 4707 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 4708 4709 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 4710 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 4711 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 4712 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 4713 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 4714 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 4715 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 4716 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 4717 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 4718 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 4719 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 4720 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 4721 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 4722 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 4723 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 4724 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 4725 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 4726 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 4727 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 4728 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 4729 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 4730 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 4731 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 4732 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 4733 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 4734 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 4735 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 4736 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 4737 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 4738 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 4739 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 4740 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 4741 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 4742 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 4743 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 4744 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 4745 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 4746 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 4747 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 4748 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 4749 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 4750 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 4751 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 4752 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 4753 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 4754 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 4755 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 4756 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 4757 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 4758 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 4759 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 4760 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 4761 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 4762 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 4763 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 4764 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 4765 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 4766 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 4767 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 4768 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 4769 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 4770 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 4771 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 4772 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 4773 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 4774 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 4775 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 4776 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 4777 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 4778 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 4779 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 4780 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 4781 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 4782 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 4783 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 4784 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 4785 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 4786 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 4787 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 4788 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 4789 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 4790 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 4791 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 4792 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 4793 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 4794 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 4795 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 4796 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 4797 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 4798 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 4799 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 4800 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 4801 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 4802 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 4803 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 4804 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 4805 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 4806 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 4807 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 4808 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 4809 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 4810 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 4811 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 4812 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 4813 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 4814 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 4815 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 4816 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 4817 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 4818 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 4819 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 4820 4821 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 4822 4823 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 4824 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 4825 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 4826 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 4827 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 4828 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 4829 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 4830 4831 rtl_hw_aspm_clkreq_enable(tp, true); 4832 } 4833 4834 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 4835 { 4836 static const struct ephy_info e_info_8168h_1[] = { 4837 { 0x1e, 0x0800, 0x0001 }, 4838 { 0x1d, 0x0000, 0x0800 }, 4839 { 0x05, 0xffff, 0x2089 }, 4840 { 0x06, 0xffff, 0x5881 }, 4841 { 0x04, 0xffff, 0x854a }, 4842 { 0x01, 0xffff, 0x068b } 4843 }; 4844 int rg_saw_cnt; 4845 4846 /* disable aspm and clock request before access ephy */ 4847 rtl_hw_aspm_clkreq_enable(tp, false); 4848 rtl_ephy_init(tp, e_info_8168h_1); 4849 4850 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4851 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 4852 4853 rtl_set_def_aspm_entry_latency(tp); 4854 4855 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4856 4857 rtl_reset_packet_filter(tp); 4858 4859 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 4860 4861 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 4862 4863 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4864 4865 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4866 4867 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4868 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4869 4870 rtl8168_config_eee_mac(tp); 4871 4872 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4873 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4874 4875 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4876 4877 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 4878 4879 rtl_pcie_state_l2l3_disable(tp); 4880 4881 rtl_writephy(tp, 0x1f, 0x0c42); 4882 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff); 4883 rtl_writephy(tp, 0x1f, 0x0000); 4884 if (rg_saw_cnt > 0) { 4885 u16 sw_cnt_1ms_ini; 4886 4887 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 4888 sw_cnt_1ms_ini &= 0x0fff; 4889 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 4890 } 4891 4892 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 4893 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 4894 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 4895 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 4896 4897 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 4898 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 4899 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 4900 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 4901 4902 rtl_hw_aspm_clkreq_enable(tp, true); 4903 } 4904 4905 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 4906 { 4907 rtl8168ep_stop_cmac(tp); 4908 4909 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 4910 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 4911 4912 rtl_set_def_aspm_entry_latency(tp); 4913 4914 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 4915 4916 rtl_reset_packet_filter(tp); 4917 4918 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 4919 4920 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 4921 4922 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 4923 4924 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 4925 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 4926 4927 rtl8168_config_eee_mac(tp); 4928 4929 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 4930 4931 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 4932 4933 rtl_pcie_state_l2l3_disable(tp); 4934 } 4935 4936 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 4937 { 4938 static const struct ephy_info e_info_8168ep_1[] = { 4939 { 0x00, 0xffff, 0x10ab }, 4940 { 0x06, 0xffff, 0xf030 }, 4941 { 0x08, 0xffff, 0x2006 }, 4942 { 0x0d, 0xffff, 0x1666 }, 4943 { 0x0c, 0x3ff0, 0x0000 } 4944 }; 4945 4946 /* disable aspm and clock request before access ephy */ 4947 rtl_hw_aspm_clkreq_enable(tp, false); 4948 rtl_ephy_init(tp, e_info_8168ep_1); 4949 4950 rtl_hw_start_8168ep(tp); 4951 4952 rtl_hw_aspm_clkreq_enable(tp, true); 4953 } 4954 4955 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 4956 { 4957 static const struct ephy_info e_info_8168ep_2[] = { 4958 { 0x00, 0xffff, 0x10a3 }, 4959 { 0x19, 0xffff, 0xfc00 }, 4960 { 0x1e, 0xffff, 0x20ea } 4961 }; 4962 4963 /* disable aspm and clock request before access ephy */ 4964 rtl_hw_aspm_clkreq_enable(tp, false); 4965 rtl_ephy_init(tp, e_info_8168ep_2); 4966 4967 rtl_hw_start_8168ep(tp); 4968 4969 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4970 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4971 4972 rtl_hw_aspm_clkreq_enable(tp, true); 4973 } 4974 4975 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 4976 { 4977 static const struct ephy_info e_info_8168ep_3[] = { 4978 { 0x00, 0x0000, 0x0080 }, 4979 { 0x0d, 0x0100, 0x0200 }, 4980 { 0x19, 0x8021, 0x0000 }, 4981 { 0x1e, 0x0000, 0x2000 }, 4982 }; 4983 4984 /* disable aspm and clock request before access ephy */ 4985 rtl_hw_aspm_clkreq_enable(tp, false); 4986 rtl_ephy_init(tp, e_info_8168ep_3); 4987 4988 rtl_hw_start_8168ep(tp); 4989 4990 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 4991 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 4992 4993 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 4994 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 4995 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 4996 4997 rtl_hw_aspm_clkreq_enable(tp, true); 4998 } 4999 5000 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 5001 { 5002 static const struct ephy_info e_info_8102e_1[] = { 5003 { 0x01, 0, 0x6e65 }, 5004 { 0x02, 0, 0x091f }, 5005 { 0x03, 0, 0xc2f9 }, 5006 { 0x06, 0, 0xafb5 }, 5007 { 0x07, 0, 0x0e00 }, 5008 { 0x19, 0, 0xec80 }, 5009 { 0x01, 0, 0x2e65 }, 5010 { 0x01, 0, 0x6e65 } 5011 }; 5012 u8 cfg1; 5013 5014 rtl_set_def_aspm_entry_latency(tp); 5015 5016 RTL_W8(tp, DBG_REG, FIX_NAK_1); 5017 5018 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5019 5020 RTL_W8(tp, Config1, 5021 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 5022 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5023 5024 cfg1 = RTL_R8(tp, Config1); 5025 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 5026 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 5027 5028 rtl_ephy_init(tp, e_info_8102e_1); 5029 } 5030 5031 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 5032 { 5033 rtl_set_def_aspm_entry_latency(tp); 5034 5035 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5036 5037 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 5038 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 5039 } 5040 5041 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 5042 { 5043 rtl_hw_start_8102e_2(tp); 5044 5045 rtl_ephy_write(tp, 0x03, 0xc2f9); 5046 } 5047 5048 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 5049 { 5050 static const struct ephy_info e_info_8105e_1[] = { 5051 { 0x07, 0, 0x4000 }, 5052 { 0x19, 0, 0x0200 }, 5053 { 0x19, 0, 0x0020 }, 5054 { 0x1e, 0, 0x2000 }, 5055 { 0x03, 0, 0x0001 }, 5056 { 0x19, 0, 0x0100 }, 5057 { 0x19, 0, 0x0004 }, 5058 { 0x0a, 0, 0x0020 } 5059 }; 5060 5061 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5062 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5063 5064 /* Disable Early Tally Counter */ 5065 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 5066 5067 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5068 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 5069 5070 rtl_ephy_init(tp, e_info_8105e_1); 5071 5072 rtl_pcie_state_l2l3_disable(tp); 5073 } 5074 5075 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 5076 { 5077 rtl_hw_start_8105e_1(tp); 5078 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 5079 } 5080 5081 static void rtl_hw_start_8402(struct rtl8169_private *tp) 5082 { 5083 static const struct ephy_info e_info_8402[] = { 5084 { 0x19, 0xffff, 0xff64 }, 5085 { 0x1e, 0, 0x4000 } 5086 }; 5087 5088 rtl_set_def_aspm_entry_latency(tp); 5089 5090 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5091 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5092 5093 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5094 5095 rtl_ephy_init(tp, e_info_8402); 5096 5097 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); 5098 5099 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 5100 rtl_reset_packet_filter(tp); 5101 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 5102 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 5103 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 5104 5105 rtl_pcie_state_l2l3_disable(tp); 5106 } 5107 5108 static void rtl_hw_start_8106(struct rtl8169_private *tp) 5109 { 5110 rtl_hw_aspm_clkreq_enable(tp, false); 5111 5112 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 5113 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 5114 5115 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 5116 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 5117 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 5118 5119 rtl_pcie_state_l2l3_disable(tp); 5120 rtl_hw_aspm_clkreq_enable(tp, true); 5121 } 5122 5123 static void rtl_hw_config(struct rtl8169_private *tp) 5124 { 5125 static const rtl_generic_fct hw_configs[] = { 5126 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 5127 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 5128 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 5129 [RTL_GIGA_MAC_VER_10] = NULL, 5130 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168bb, 5131 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168bef, 5132 [RTL_GIGA_MAC_VER_13] = NULL, 5133 [RTL_GIGA_MAC_VER_14] = NULL, 5134 [RTL_GIGA_MAC_VER_15] = NULL, 5135 [RTL_GIGA_MAC_VER_16] = NULL, 5136 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168bef, 5137 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 5138 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 5139 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 5140 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 5141 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 5142 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 5143 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 5144 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 5145 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 5146 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 5147 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 5148 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 5149 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 5150 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168dp, 5151 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 5152 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 5153 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 5154 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 5155 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 5156 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 5157 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 5158 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 5159 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 5160 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 5161 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 5162 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 5163 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 5164 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 5165 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 5166 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 5167 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 5168 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 5169 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 5170 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 5171 }; 5172 5173 if (hw_configs[tp->mac_version]) 5174 hw_configs[tp->mac_version](tp); 5175 } 5176 5177 static void rtl_hw_start_8168(struct rtl8169_private *tp) 5178 { 5179 if (tp->mac_version == RTL_GIGA_MAC_VER_13 || 5180 tp->mac_version == RTL_GIGA_MAC_VER_16) 5181 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL, 5182 PCI_EXP_DEVCTL_NOSNOOP_EN); 5183 5184 if (rtl_is_8168evl_up(tp)) 5185 RTL_W8(tp, MaxTxPacketSize, EarlySize); 5186 else 5187 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 5188 5189 rtl_hw_config(tp); 5190 } 5191 5192 static void rtl_hw_start_8169(struct rtl8169_private *tp) 5193 { 5194 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5195 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 5196 5197 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 5198 5199 tp->cp_cmd |= PCIMulRW; 5200 5201 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 5202 tp->mac_version == RTL_GIGA_MAC_VER_03) { 5203 netif_dbg(tp, drv, tp->dev, 5204 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n"); 5205 tp->cp_cmd |= (1 << 14); 5206 } 5207 5208 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5209 5210 rtl8169_set_magic_reg(tp, tp->mac_version); 5211 5212 RTL_W32(tp, RxMissed, 0); 5213 } 5214 5215 static void rtl_hw_start(struct rtl8169_private *tp) 5216 { 5217 rtl_unlock_config_regs(tp); 5218 5219 tp->cp_cmd &= CPCMD_MASK; 5220 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 5221 5222 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5223 rtl_hw_start_8169(tp); 5224 else 5225 rtl_hw_start_8168(tp); 5226 5227 rtl_set_rx_max_size(tp); 5228 rtl_set_rx_tx_desc_registers(tp); 5229 rtl_lock_config_regs(tp); 5230 5231 /* disable interrupt coalescing */ 5232 RTL_W16(tp, IntrMitigate, 0x0000); 5233 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 5234 RTL_R8(tp, IntrMask); 5235 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 5236 rtl_init_rxcfg(tp); 5237 rtl_set_tx_config_registers(tp); 5238 rtl_set_rx_mode(tp->dev); 5239 rtl_irq_enable(tp); 5240 } 5241 5242 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 5243 { 5244 struct rtl8169_private *tp = netdev_priv(dev); 5245 5246 if (new_mtu > ETH_DATA_LEN) 5247 rtl_hw_jumbo_enable(tp); 5248 else 5249 rtl_hw_jumbo_disable(tp); 5250 5251 dev->mtu = new_mtu; 5252 netdev_update_features(dev); 5253 5254 return 0; 5255 } 5256 5257 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) 5258 { 5259 desc->addr = cpu_to_le64(0x0badbadbadbadbadull); 5260 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); 5261 } 5262 5263 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 5264 { 5265 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 5266 5267 /* Force memory writes to complete before releasing descriptor */ 5268 dma_wmb(); 5269 5270 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 5271 } 5272 5273 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 5274 struct RxDesc *desc) 5275 { 5276 struct device *d = tp_to_dev(tp); 5277 int node = dev_to_node(d); 5278 dma_addr_t mapping; 5279 struct page *data; 5280 5281 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 5282 if (!data) 5283 return NULL; 5284 5285 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5286 if (unlikely(dma_mapping_error(d, mapping))) { 5287 if (net_ratelimit()) 5288 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); 5289 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 5290 return NULL; 5291 } 5292 5293 desc->addr = cpu_to_le64(mapping); 5294 rtl8169_mark_to_asic(desc); 5295 5296 return data; 5297 } 5298 5299 static void rtl8169_rx_clear(struct rtl8169_private *tp) 5300 { 5301 unsigned int i; 5302 5303 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 5304 dma_unmap_page(tp_to_dev(tp), 5305 le64_to_cpu(tp->RxDescArray[i].addr), 5306 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 5307 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 5308 tp->Rx_databuff[i] = NULL; 5309 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5310 } 5311 } 5312 5313 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) 5314 { 5315 desc->opts1 |= cpu_to_le32(RingEnd); 5316 } 5317 5318 static int rtl8169_rx_fill(struct rtl8169_private *tp) 5319 { 5320 unsigned int i; 5321 5322 for (i = 0; i < NUM_RX_DESC; i++) { 5323 struct page *data; 5324 5325 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 5326 if (!data) { 5327 rtl8169_make_unusable_by_asic(tp->RxDescArray + i); 5328 goto err_out; 5329 } 5330 tp->Rx_databuff[i] = data; 5331 } 5332 5333 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); 5334 return 0; 5335 5336 err_out: 5337 rtl8169_rx_clear(tp); 5338 return -ENOMEM; 5339 } 5340 5341 static int rtl8169_init_ring(struct rtl8169_private *tp) 5342 { 5343 rtl8169_init_ring_indexes(tp); 5344 5345 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 5346 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 5347 5348 return rtl8169_rx_fill(tp); 5349 } 5350 5351 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, 5352 struct TxDesc *desc) 5353 { 5354 unsigned int len = tx_skb->len; 5355 5356 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); 5357 5358 desc->opts1 = 0x00; 5359 desc->opts2 = 0x00; 5360 desc->addr = 0x00; 5361 tx_skb->len = 0; 5362 } 5363 5364 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 5365 unsigned int n) 5366 { 5367 unsigned int i; 5368 5369 for (i = 0; i < n; i++) { 5370 unsigned int entry = (start + i) % NUM_TX_DESC; 5371 struct ring_info *tx_skb = tp->tx_skb + entry; 5372 unsigned int len = tx_skb->len; 5373 5374 if (len) { 5375 struct sk_buff *skb = tx_skb->skb; 5376 5377 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5378 tp->TxDescArray + entry); 5379 if (skb) { 5380 dev_consume_skb_any(skb); 5381 tx_skb->skb = NULL; 5382 } 5383 } 5384 } 5385 } 5386 5387 static void rtl8169_tx_clear(struct rtl8169_private *tp) 5388 { 5389 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 5390 tp->cur_tx = tp->dirty_tx = 0; 5391 netdev_reset_queue(tp->dev); 5392 } 5393 5394 static void rtl_reset_work(struct rtl8169_private *tp) 5395 { 5396 struct net_device *dev = tp->dev; 5397 int i; 5398 5399 napi_disable(&tp->napi); 5400 netif_stop_queue(dev); 5401 synchronize_rcu(); 5402 5403 rtl8169_hw_reset(tp); 5404 5405 for (i = 0; i < NUM_RX_DESC; i++) 5406 rtl8169_mark_to_asic(tp->RxDescArray + i); 5407 5408 rtl8169_tx_clear(tp); 5409 rtl8169_init_ring_indexes(tp); 5410 5411 napi_enable(&tp->napi); 5412 rtl_hw_start(tp); 5413 netif_wake_queue(dev); 5414 } 5415 5416 static void rtl8169_tx_timeout(struct net_device *dev) 5417 { 5418 struct rtl8169_private *tp = netdev_priv(dev); 5419 5420 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5421 } 5422 5423 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry) 5424 { 5425 u32 status = opts0 | len; 5426 5427 if (entry == NUM_TX_DESC - 1) 5428 status |= RingEnd; 5429 5430 return cpu_to_le32(status); 5431 } 5432 5433 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 5434 u32 *opts) 5435 { 5436 struct skb_shared_info *info = skb_shinfo(skb); 5437 unsigned int cur_frag, entry; 5438 struct TxDesc *uninitialized_var(txd); 5439 struct device *d = tp_to_dev(tp); 5440 5441 entry = tp->cur_tx; 5442 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 5443 const skb_frag_t *frag = info->frags + cur_frag; 5444 dma_addr_t mapping; 5445 u32 len; 5446 void *addr; 5447 5448 entry = (entry + 1) % NUM_TX_DESC; 5449 5450 txd = tp->TxDescArray + entry; 5451 len = skb_frag_size(frag); 5452 addr = skb_frag_address(frag); 5453 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 5454 if (unlikely(dma_mapping_error(d, mapping))) { 5455 if (net_ratelimit()) 5456 netif_err(tp, drv, tp->dev, 5457 "Failed to map TX fragments DMA!\n"); 5458 goto err_out; 5459 } 5460 5461 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5462 txd->opts2 = cpu_to_le32(opts[1]); 5463 txd->addr = cpu_to_le64(mapping); 5464 5465 tp->tx_skb[entry].len = len; 5466 } 5467 5468 if (cur_frag) { 5469 tp->tx_skb[entry].skb = skb; 5470 txd->opts1 |= cpu_to_le32(LastFrag); 5471 } 5472 5473 return cur_frag; 5474 5475 err_out: 5476 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 5477 return -EIO; 5478 } 5479 5480 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 5481 { 5482 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 5483 } 5484 5485 /* msdn_giant_send_check() 5486 * According to the document of microsoft, the TCP Pseudo Header excludes the 5487 * packet length for IPv6 TCP large packets. 5488 */ 5489 static int msdn_giant_send_check(struct sk_buff *skb) 5490 { 5491 const struct ipv6hdr *ipv6h; 5492 struct tcphdr *th; 5493 int ret; 5494 5495 ret = skb_cow_head(skb, 0); 5496 if (ret) 5497 return ret; 5498 5499 ipv6h = ipv6_hdr(skb); 5500 th = tcp_hdr(skb); 5501 5502 th->check = 0; 5503 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); 5504 5505 return ret; 5506 } 5507 5508 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 5509 { 5510 u32 mss = skb_shinfo(skb)->gso_size; 5511 5512 if (mss) { 5513 opts[0] |= TD_LSO; 5514 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT; 5515 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5516 const struct iphdr *ip = ip_hdr(skb); 5517 5518 if (ip->protocol == IPPROTO_TCP) 5519 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 5520 else if (ip->protocol == IPPROTO_UDP) 5521 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 5522 else 5523 WARN_ON_ONCE(1); 5524 } 5525 } 5526 5527 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 5528 struct sk_buff *skb, u32 *opts) 5529 { 5530 u32 transport_offset = (u32)skb_transport_offset(skb); 5531 u32 mss = skb_shinfo(skb)->gso_size; 5532 5533 if (mss) { 5534 switch (vlan_get_protocol(skb)) { 5535 case htons(ETH_P_IP): 5536 opts[0] |= TD1_GTSENV4; 5537 break; 5538 5539 case htons(ETH_P_IPV6): 5540 if (msdn_giant_send_check(skb)) 5541 return false; 5542 5543 opts[0] |= TD1_GTSENV6; 5544 break; 5545 5546 default: 5547 WARN_ON_ONCE(1); 5548 break; 5549 } 5550 5551 opts[0] |= transport_offset << GTTCPHO_SHIFT; 5552 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT; 5553 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5554 u8 ip_protocol; 5555 5556 switch (vlan_get_protocol(skb)) { 5557 case htons(ETH_P_IP): 5558 opts[1] |= TD1_IPv4_CS; 5559 ip_protocol = ip_hdr(skb)->protocol; 5560 break; 5561 5562 case htons(ETH_P_IPV6): 5563 opts[1] |= TD1_IPv6_CS; 5564 ip_protocol = ipv6_hdr(skb)->nexthdr; 5565 break; 5566 5567 default: 5568 ip_protocol = IPPROTO_RAW; 5569 break; 5570 } 5571 5572 if (ip_protocol == IPPROTO_TCP) 5573 opts[1] |= TD1_TCP_CS; 5574 else if (ip_protocol == IPPROTO_UDP) 5575 opts[1] |= TD1_UDP_CS; 5576 else 5577 WARN_ON_ONCE(1); 5578 5579 opts[1] |= transport_offset << TCPHO_SHIFT; 5580 } else { 5581 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 5582 return !eth_skb_pad(skb); 5583 } 5584 5585 return true; 5586 } 5587 5588 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 5589 unsigned int nr_frags) 5590 { 5591 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 5592 5593 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 5594 return slots_avail > nr_frags; 5595 } 5596 5597 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 5598 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 5599 { 5600 switch (tp->mac_version) { 5601 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5602 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 5603 return false; 5604 default: 5605 return true; 5606 } 5607 } 5608 5609 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 5610 struct net_device *dev) 5611 { 5612 struct rtl8169_private *tp = netdev_priv(dev); 5613 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 5614 struct TxDesc *txd = tp->TxDescArray + entry; 5615 struct device *d = tp_to_dev(tp); 5616 dma_addr_t mapping; 5617 u32 opts[2], len; 5618 bool stop_queue; 5619 bool door_bell; 5620 int frags; 5621 5622 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) { 5623 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); 5624 goto err_stop_0; 5625 } 5626 5627 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) 5628 goto err_stop_0; 5629 5630 opts[1] = rtl8169_tx_vlan_tag(skb); 5631 opts[0] = DescOwn; 5632 5633 if (rtl_chip_supports_csum_v2(tp)) { 5634 if (!rtl8169_tso_csum_v2(tp, skb, opts)) 5635 goto err_dma_0; 5636 } else { 5637 rtl8169_tso_csum_v1(skb, opts); 5638 } 5639 5640 len = skb_headlen(skb); 5641 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); 5642 if (unlikely(dma_mapping_error(d, mapping))) { 5643 if (net_ratelimit()) 5644 netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); 5645 goto err_dma_0; 5646 } 5647 5648 tp->tx_skb[entry].len = len; 5649 txd->addr = cpu_to_le64(mapping); 5650 5651 frags = rtl8169_xmit_frags(tp, skb, opts); 5652 if (frags < 0) 5653 goto err_dma_1; 5654 else if (frags) 5655 opts[0] |= FirstFrag; 5656 else { 5657 opts[0] |= FirstFrag | LastFrag; 5658 tp->tx_skb[entry].skb = skb; 5659 } 5660 5661 txd->opts2 = cpu_to_le32(opts[1]); 5662 5663 skb_tx_timestamp(skb); 5664 5665 /* Force memory writes to complete before releasing descriptor */ 5666 dma_wmb(); 5667 5668 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 5669 5670 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry); 5671 5672 /* Force all memory writes to complete before notifying device */ 5673 wmb(); 5674 5675 tp->cur_tx += frags + 1; 5676 5677 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 5678 if (unlikely(stop_queue)) { 5679 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 5680 * not miss a ring update when it notices a stopped queue. 5681 */ 5682 smp_wmb(); 5683 netif_stop_queue(dev); 5684 } 5685 5686 if (door_bell) 5687 RTL_W8(tp, TxPoll, NPQ); 5688 5689 if (unlikely(stop_queue)) { 5690 /* Sync with rtl_tx: 5691 * - publish queue status and cur_tx ring index (write barrier) 5692 * - refresh dirty_tx ring index (read barrier). 5693 * May the current thread have a pessimistic view of the ring 5694 * status and forget to wake up queue, a racing rtl_tx thread 5695 * can't. 5696 */ 5697 smp_mb(); 5698 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 5699 netif_start_queue(dev); 5700 } 5701 5702 return NETDEV_TX_OK; 5703 5704 err_dma_1: 5705 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); 5706 err_dma_0: 5707 dev_kfree_skb_any(skb); 5708 dev->stats.tx_dropped++; 5709 return NETDEV_TX_OK; 5710 5711 err_stop_0: 5712 netif_stop_queue(dev); 5713 dev->stats.tx_dropped++; 5714 return NETDEV_TX_BUSY; 5715 } 5716 5717 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 5718 struct net_device *dev, 5719 netdev_features_t features) 5720 { 5721 int transport_offset = skb_transport_offset(skb); 5722 struct rtl8169_private *tp = netdev_priv(dev); 5723 5724 if (skb_is_gso(skb)) { 5725 if (transport_offset > GTTCPHO_MAX && 5726 rtl_chip_supports_csum_v2(tp)) 5727 features &= ~NETIF_F_ALL_TSO; 5728 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 5729 if (skb->len < ETH_ZLEN) { 5730 switch (tp->mac_version) { 5731 case RTL_GIGA_MAC_VER_11: 5732 case RTL_GIGA_MAC_VER_12: 5733 case RTL_GIGA_MAC_VER_17: 5734 case RTL_GIGA_MAC_VER_34: 5735 features &= ~NETIF_F_CSUM_MASK; 5736 break; 5737 default: 5738 break; 5739 } 5740 } 5741 5742 if (transport_offset > TCPHO_MAX && 5743 rtl_chip_supports_csum_v2(tp)) 5744 features &= ~NETIF_F_CSUM_MASK; 5745 } 5746 5747 return vlan_features_check(skb, features); 5748 } 5749 5750 static void rtl8169_pcierr_interrupt(struct net_device *dev) 5751 { 5752 struct rtl8169_private *tp = netdev_priv(dev); 5753 struct pci_dev *pdev = tp->pci_dev; 5754 u16 pci_status, pci_cmd; 5755 5756 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 5757 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 5758 5759 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", 5760 pci_cmd, pci_status); 5761 5762 /* 5763 * The recovery sequence below admits a very elaborated explanation: 5764 * - it seems to work; 5765 * - I did not see what else could be done; 5766 * - it makes iop3xx happy. 5767 * 5768 * Feel free to adjust to your needs. 5769 */ 5770 if (pdev->broken_parity_status) 5771 pci_cmd &= ~PCI_COMMAND_PARITY; 5772 else 5773 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 5774 5775 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 5776 5777 pci_write_config_word(pdev, PCI_STATUS, 5778 pci_status & (PCI_STATUS_DETECTED_PARITY | 5779 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | 5780 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); 5781 5782 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 5783 } 5784 5785 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 5786 int budget) 5787 { 5788 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 5789 5790 dirty_tx = tp->dirty_tx; 5791 smp_rmb(); 5792 tx_left = tp->cur_tx - dirty_tx; 5793 5794 while (tx_left > 0) { 5795 unsigned int entry = dirty_tx % NUM_TX_DESC; 5796 struct ring_info *tx_skb = tp->tx_skb + entry; 5797 u32 status; 5798 5799 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 5800 if (status & DescOwn) 5801 break; 5802 5803 /* This barrier is needed to keep us from reading 5804 * any other fields out of the Tx descriptor until 5805 * we know the status of DescOwn 5806 */ 5807 dma_rmb(); 5808 5809 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb, 5810 tp->TxDescArray + entry); 5811 if (status & LastFrag) { 5812 pkts_compl++; 5813 bytes_compl += tx_skb->skb->len; 5814 napi_consume_skb(tx_skb->skb, budget); 5815 tx_skb->skb = NULL; 5816 } 5817 dirty_tx++; 5818 tx_left--; 5819 } 5820 5821 if (tp->dirty_tx != dirty_tx) { 5822 netdev_completed_queue(dev, pkts_compl, bytes_compl); 5823 5824 u64_stats_update_begin(&tp->tx_stats.syncp); 5825 tp->tx_stats.packets += pkts_compl; 5826 tp->tx_stats.bytes += bytes_compl; 5827 u64_stats_update_end(&tp->tx_stats.syncp); 5828 5829 tp->dirty_tx = dirty_tx; 5830 /* Sync with rtl8169_start_xmit: 5831 * - publish dirty_tx ring index (write barrier) 5832 * - refresh cur_tx ring index and queue status (read barrier) 5833 * May the current thread miss the stopped queue condition, 5834 * a racing xmit thread can only have a right view of the 5835 * ring status. 5836 */ 5837 smp_mb(); 5838 if (netif_queue_stopped(dev) && 5839 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 5840 netif_wake_queue(dev); 5841 } 5842 /* 5843 * 8168 hack: TxPoll requests are lost when the Tx packets are 5844 * too close. Let's kick an extra TxPoll request when a burst 5845 * of start_xmit activity is detected (if it is not detected, 5846 * it is slow enough). -- FR 5847 */ 5848 if (tp->cur_tx != dirty_tx) 5849 RTL_W8(tp, TxPoll, NPQ); 5850 } 5851 } 5852 5853 static inline int rtl8169_fragmented_frame(u32 status) 5854 { 5855 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 5856 } 5857 5858 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 5859 { 5860 u32 status = opts1 & RxProtoMask; 5861 5862 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 5863 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 5864 skb->ip_summed = CHECKSUM_UNNECESSARY; 5865 else 5866 skb_checksum_none_assert(skb); 5867 } 5868 5869 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 5870 { 5871 unsigned int cur_rx, rx_left; 5872 unsigned int count; 5873 5874 cur_rx = tp->cur_rx; 5875 5876 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 5877 unsigned int entry = cur_rx % NUM_RX_DESC; 5878 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 5879 struct RxDesc *desc = tp->RxDescArray + entry; 5880 u32 status; 5881 5882 status = le32_to_cpu(desc->opts1); 5883 if (status & DescOwn) 5884 break; 5885 5886 /* This barrier is needed to keep us from reading 5887 * any other fields out of the Rx descriptor until 5888 * we know the status of DescOwn 5889 */ 5890 dma_rmb(); 5891 5892 if (unlikely(status & RxRES)) { 5893 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", 5894 status); 5895 dev->stats.rx_errors++; 5896 if (status & (RxRWT | RxRUNT)) 5897 dev->stats.rx_length_errors++; 5898 if (status & RxCRC) 5899 dev->stats.rx_crc_errors++; 5900 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 5901 dev->features & NETIF_F_RXALL) { 5902 goto process_pkt; 5903 } 5904 } else { 5905 unsigned int pkt_size; 5906 struct sk_buff *skb; 5907 5908 process_pkt: 5909 pkt_size = status & GENMASK(13, 0); 5910 if (likely(!(dev->features & NETIF_F_RXFCS))) 5911 pkt_size -= ETH_FCS_LEN; 5912 /* 5913 * The driver does not support incoming fragmented 5914 * frames. They are seen as a symptom of over-mtu 5915 * sized frames. 5916 */ 5917 if (unlikely(rtl8169_fragmented_frame(status))) { 5918 dev->stats.rx_dropped++; 5919 dev->stats.rx_length_errors++; 5920 goto release_descriptor; 5921 } 5922 5923 dma_sync_single_for_cpu(tp_to_dev(tp), 5924 le64_to_cpu(desc->addr), 5925 pkt_size, DMA_FROM_DEVICE); 5926 5927 skb = napi_alloc_skb(&tp->napi, pkt_size); 5928 if (unlikely(!skb)) { 5929 dev->stats.rx_dropped++; 5930 goto release_descriptor; 5931 } 5932 5933 prefetch(rx_buf); 5934 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 5935 skb->tail += pkt_size; 5936 skb->len = pkt_size; 5937 5938 rtl8169_rx_csum(skb, status); 5939 skb->protocol = eth_type_trans(skb, dev); 5940 5941 rtl8169_rx_vlan_tag(desc, skb); 5942 5943 if (skb->pkt_type == PACKET_MULTICAST) 5944 dev->stats.multicast++; 5945 5946 napi_gro_receive(&tp->napi, skb); 5947 5948 u64_stats_update_begin(&tp->rx_stats.syncp); 5949 tp->rx_stats.packets++; 5950 tp->rx_stats.bytes += pkt_size; 5951 u64_stats_update_end(&tp->rx_stats.syncp); 5952 } 5953 release_descriptor: 5954 desc->opts2 = 0; 5955 rtl8169_mark_to_asic(desc); 5956 } 5957 5958 count = cur_rx - tp->cur_rx; 5959 tp->cur_rx = cur_rx; 5960 5961 return count; 5962 } 5963 5964 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 5965 { 5966 struct rtl8169_private *tp = dev_instance; 5967 u16 status = RTL_R16(tp, IntrStatus); 5968 5969 if (!tp->irq_enabled || status == 0xffff || !(status & tp->irq_mask)) 5970 return IRQ_NONE; 5971 5972 if (unlikely(status & SYSErr)) { 5973 rtl8169_pcierr_interrupt(tp->dev); 5974 goto out; 5975 } 5976 5977 if (status & LinkChg) 5978 phy_mac_interrupt(tp->phydev); 5979 5980 if (unlikely(status & RxFIFOOver && 5981 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 5982 netif_stop_queue(tp->dev); 5983 /* XXX - Hack alert. See rtl_task(). */ 5984 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags); 5985 } 5986 5987 rtl_irq_disable(tp); 5988 napi_schedule_irqoff(&tp->napi); 5989 out: 5990 rtl_ack_events(tp, status); 5991 5992 return IRQ_HANDLED; 5993 } 5994 5995 static void rtl_task(struct work_struct *work) 5996 { 5997 static const struct { 5998 int bitnr; 5999 void (*action)(struct rtl8169_private *); 6000 } rtl_work[] = { 6001 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work }, 6002 }; 6003 struct rtl8169_private *tp = 6004 container_of(work, struct rtl8169_private, wk.work); 6005 struct net_device *dev = tp->dev; 6006 int i; 6007 6008 rtl_lock_work(tp); 6009 6010 if (!netif_running(dev) || 6011 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 6012 goto out_unlock; 6013 6014 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) { 6015 bool pending; 6016 6017 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags); 6018 if (pending) 6019 rtl_work[i].action(tp); 6020 } 6021 6022 out_unlock: 6023 rtl_unlock_work(tp); 6024 } 6025 6026 static int rtl8169_poll(struct napi_struct *napi, int budget) 6027 { 6028 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 6029 struct net_device *dev = tp->dev; 6030 int work_done; 6031 6032 work_done = rtl_rx(dev, tp, (u32) budget); 6033 6034 rtl_tx(dev, tp, budget); 6035 6036 if (work_done < budget) { 6037 napi_complete_done(napi, work_done); 6038 rtl_irq_enable(tp); 6039 } 6040 6041 return work_done; 6042 } 6043 6044 static void rtl8169_rx_missed(struct net_device *dev) 6045 { 6046 struct rtl8169_private *tp = netdev_priv(dev); 6047 6048 if (tp->mac_version > RTL_GIGA_MAC_VER_06) 6049 return; 6050 6051 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff; 6052 RTL_W32(tp, RxMissed, 0); 6053 } 6054 6055 static void r8169_phylink_handler(struct net_device *ndev) 6056 { 6057 struct rtl8169_private *tp = netdev_priv(ndev); 6058 6059 if (netif_carrier_ok(ndev)) { 6060 rtl_link_chg_patch(tp); 6061 pm_request_resume(&tp->pci_dev->dev); 6062 } else { 6063 pm_runtime_idle(&tp->pci_dev->dev); 6064 } 6065 6066 if (net_ratelimit()) 6067 phy_print_status(tp->phydev); 6068 } 6069 6070 static int r8169_phy_connect(struct rtl8169_private *tp) 6071 { 6072 struct phy_device *phydev = tp->phydev; 6073 phy_interface_t phy_mode; 6074 int ret; 6075 6076 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 6077 PHY_INTERFACE_MODE_MII; 6078 6079 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 6080 phy_mode); 6081 if (ret) 6082 return ret; 6083 6084 if (!tp->supports_gmii) 6085 phy_set_max_speed(phydev, SPEED_100); 6086 6087 phy_support_asym_pause(phydev); 6088 6089 phy_attached_info(phydev); 6090 6091 return 0; 6092 } 6093 6094 static void rtl8169_down(struct net_device *dev) 6095 { 6096 struct rtl8169_private *tp = netdev_priv(dev); 6097 6098 phy_stop(tp->phydev); 6099 6100 napi_disable(&tp->napi); 6101 netif_stop_queue(dev); 6102 6103 rtl8169_hw_reset(tp); 6104 /* 6105 * At this point device interrupts can not be enabled in any function, 6106 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task) 6107 * and napi is disabled (rtl8169_poll). 6108 */ 6109 rtl8169_rx_missed(dev); 6110 6111 /* Give a racing hard_start_xmit a few cycles to complete. */ 6112 synchronize_rcu(); 6113 6114 rtl8169_tx_clear(tp); 6115 6116 rtl8169_rx_clear(tp); 6117 6118 rtl_pll_power_down(tp); 6119 } 6120 6121 static int rtl8169_close(struct net_device *dev) 6122 { 6123 struct rtl8169_private *tp = netdev_priv(dev); 6124 struct pci_dev *pdev = tp->pci_dev; 6125 6126 pm_runtime_get_sync(&pdev->dev); 6127 6128 /* Update counters before going down */ 6129 rtl8169_update_counters(tp); 6130 6131 rtl_lock_work(tp); 6132 /* Clear all task flags */ 6133 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6134 6135 rtl8169_down(dev); 6136 rtl_unlock_work(tp); 6137 6138 cancel_work_sync(&tp->wk.work); 6139 6140 phy_disconnect(tp->phydev); 6141 6142 pci_free_irq(pdev, 0, tp); 6143 6144 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6145 tp->RxPhyAddr); 6146 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6147 tp->TxPhyAddr); 6148 tp->TxDescArray = NULL; 6149 tp->RxDescArray = NULL; 6150 6151 pm_runtime_put_sync(&pdev->dev); 6152 6153 return 0; 6154 } 6155 6156 #ifdef CONFIG_NET_POLL_CONTROLLER 6157 static void rtl8169_netpoll(struct net_device *dev) 6158 { 6159 struct rtl8169_private *tp = netdev_priv(dev); 6160 6161 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 6162 } 6163 #endif 6164 6165 static int rtl_open(struct net_device *dev) 6166 { 6167 struct rtl8169_private *tp = netdev_priv(dev); 6168 struct pci_dev *pdev = tp->pci_dev; 6169 int retval = -ENOMEM; 6170 6171 pm_runtime_get_sync(&pdev->dev); 6172 6173 /* 6174 * Rx and Tx descriptors needs 256 bytes alignment. 6175 * dma_alloc_coherent provides more. 6176 */ 6177 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 6178 &tp->TxPhyAddr, GFP_KERNEL); 6179 if (!tp->TxDescArray) 6180 goto err_pm_runtime_put; 6181 6182 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 6183 &tp->RxPhyAddr, GFP_KERNEL); 6184 if (!tp->RxDescArray) 6185 goto err_free_tx_0; 6186 6187 retval = rtl8169_init_ring(tp); 6188 if (retval < 0) 6189 goto err_free_rx_1; 6190 6191 rtl_request_firmware(tp); 6192 6193 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 6194 dev->name); 6195 if (retval < 0) 6196 goto err_release_fw_2; 6197 6198 retval = r8169_phy_connect(tp); 6199 if (retval) 6200 goto err_free_irq; 6201 6202 rtl_lock_work(tp); 6203 6204 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6205 6206 napi_enable(&tp->napi); 6207 6208 rtl8169_init_phy(dev, tp); 6209 6210 rtl_pll_power_up(tp); 6211 6212 rtl_hw_start(tp); 6213 6214 if (!rtl8169_init_counter_offsets(tp)) 6215 netif_warn(tp, hw, dev, "counter reset/update failed\n"); 6216 6217 phy_start(tp->phydev); 6218 netif_start_queue(dev); 6219 6220 rtl_unlock_work(tp); 6221 6222 pm_runtime_put_sync(&pdev->dev); 6223 out: 6224 return retval; 6225 6226 err_free_irq: 6227 pci_free_irq(pdev, 0, tp); 6228 err_release_fw_2: 6229 rtl_release_firmware(tp); 6230 rtl8169_rx_clear(tp); 6231 err_free_rx_1: 6232 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 6233 tp->RxPhyAddr); 6234 tp->RxDescArray = NULL; 6235 err_free_tx_0: 6236 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 6237 tp->TxPhyAddr); 6238 tp->TxDescArray = NULL; 6239 err_pm_runtime_put: 6240 pm_runtime_put_noidle(&pdev->dev); 6241 goto out; 6242 } 6243 6244 static void 6245 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6246 { 6247 struct rtl8169_private *tp = netdev_priv(dev); 6248 struct pci_dev *pdev = tp->pci_dev; 6249 struct rtl8169_counters *counters = tp->counters; 6250 unsigned int start; 6251 6252 pm_runtime_get_noresume(&pdev->dev); 6253 6254 if (netif_running(dev) && pm_runtime_active(&pdev->dev)) 6255 rtl8169_rx_missed(dev); 6256 6257 do { 6258 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 6259 stats->rx_packets = tp->rx_stats.packets; 6260 stats->rx_bytes = tp->rx_stats.bytes; 6261 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 6262 6263 do { 6264 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 6265 stats->tx_packets = tp->tx_stats.packets; 6266 stats->tx_bytes = tp->tx_stats.bytes; 6267 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 6268 6269 stats->rx_dropped = dev->stats.rx_dropped; 6270 stats->tx_dropped = dev->stats.tx_dropped; 6271 stats->rx_length_errors = dev->stats.rx_length_errors; 6272 stats->rx_errors = dev->stats.rx_errors; 6273 stats->rx_crc_errors = dev->stats.rx_crc_errors; 6274 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 6275 stats->rx_missed_errors = dev->stats.rx_missed_errors; 6276 stats->multicast = dev->stats.multicast; 6277 6278 /* 6279 * Fetch additional counter values missing in stats collected by driver 6280 * from tally counters. 6281 */ 6282 if (pm_runtime_active(&pdev->dev)) 6283 rtl8169_update_counters(tp); 6284 6285 /* 6286 * Subtract values fetched during initalization. 6287 * See rtl8169_init_counter_offsets for a description why we do that. 6288 */ 6289 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 6290 le64_to_cpu(tp->tc_offset.tx_errors); 6291 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 6292 le32_to_cpu(tp->tc_offset.tx_multi_collision); 6293 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 6294 le16_to_cpu(tp->tc_offset.tx_aborted); 6295 6296 pm_runtime_put_noidle(&pdev->dev); 6297 } 6298 6299 static void rtl8169_net_suspend(struct net_device *dev) 6300 { 6301 struct rtl8169_private *tp = netdev_priv(dev); 6302 6303 if (!netif_running(dev)) 6304 return; 6305 6306 phy_stop(tp->phydev); 6307 netif_device_detach(dev); 6308 6309 rtl_lock_work(tp); 6310 napi_disable(&tp->napi); 6311 /* Clear all task flags */ 6312 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 6313 6314 rtl_unlock_work(tp); 6315 6316 rtl_pll_power_down(tp); 6317 } 6318 6319 #ifdef CONFIG_PM 6320 6321 static int rtl8169_suspend(struct device *device) 6322 { 6323 struct net_device *dev = dev_get_drvdata(device); 6324 struct rtl8169_private *tp = netdev_priv(dev); 6325 6326 rtl8169_net_suspend(dev); 6327 clk_disable_unprepare(tp->clk); 6328 6329 return 0; 6330 } 6331 6332 static void __rtl8169_resume(struct net_device *dev) 6333 { 6334 struct rtl8169_private *tp = netdev_priv(dev); 6335 6336 netif_device_attach(dev); 6337 6338 rtl_pll_power_up(tp); 6339 rtl8169_init_phy(dev, tp); 6340 6341 phy_start(tp->phydev); 6342 6343 rtl_lock_work(tp); 6344 napi_enable(&tp->napi); 6345 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 6346 rtl_reset_work(tp); 6347 rtl_unlock_work(tp); 6348 } 6349 6350 static int rtl8169_resume(struct device *device) 6351 { 6352 struct net_device *dev = dev_get_drvdata(device); 6353 struct rtl8169_private *tp = netdev_priv(dev); 6354 6355 rtl_rar_set(tp, dev->dev_addr); 6356 6357 clk_prepare_enable(tp->clk); 6358 6359 if (netif_running(dev)) 6360 __rtl8169_resume(dev); 6361 6362 return 0; 6363 } 6364 6365 static int rtl8169_runtime_suspend(struct device *device) 6366 { 6367 struct net_device *dev = dev_get_drvdata(device); 6368 struct rtl8169_private *tp = netdev_priv(dev); 6369 6370 if (!tp->TxDescArray) 6371 return 0; 6372 6373 rtl_lock_work(tp); 6374 __rtl8169_set_wol(tp, WAKE_ANY); 6375 rtl_unlock_work(tp); 6376 6377 rtl8169_net_suspend(dev); 6378 6379 /* Update counters before going runtime suspend */ 6380 rtl8169_rx_missed(dev); 6381 rtl8169_update_counters(tp); 6382 6383 return 0; 6384 } 6385 6386 static int rtl8169_runtime_resume(struct device *device) 6387 { 6388 struct net_device *dev = dev_get_drvdata(device); 6389 struct rtl8169_private *tp = netdev_priv(dev); 6390 6391 rtl_rar_set(tp, dev->dev_addr); 6392 6393 if (!tp->TxDescArray) 6394 return 0; 6395 6396 rtl_lock_work(tp); 6397 __rtl8169_set_wol(tp, tp->saved_wolopts); 6398 rtl_unlock_work(tp); 6399 6400 __rtl8169_resume(dev); 6401 6402 return 0; 6403 } 6404 6405 static int rtl8169_runtime_idle(struct device *device) 6406 { 6407 struct net_device *dev = dev_get_drvdata(device); 6408 6409 if (!netif_running(dev) || !netif_carrier_ok(dev)) 6410 pm_schedule_suspend(device, 10000); 6411 6412 return -EBUSY; 6413 } 6414 6415 static const struct dev_pm_ops rtl8169_pm_ops = { 6416 .suspend = rtl8169_suspend, 6417 .resume = rtl8169_resume, 6418 .freeze = rtl8169_suspend, 6419 .thaw = rtl8169_resume, 6420 .poweroff = rtl8169_suspend, 6421 .restore = rtl8169_resume, 6422 .runtime_suspend = rtl8169_runtime_suspend, 6423 .runtime_resume = rtl8169_runtime_resume, 6424 .runtime_idle = rtl8169_runtime_idle, 6425 }; 6426 6427 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 6428 6429 #else /* !CONFIG_PM */ 6430 6431 #define RTL8169_PM_OPS NULL 6432 6433 #endif /* !CONFIG_PM */ 6434 6435 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 6436 { 6437 /* WoL fails with 8168b when the receiver is disabled. */ 6438 switch (tp->mac_version) { 6439 case RTL_GIGA_MAC_VER_11: 6440 case RTL_GIGA_MAC_VER_12: 6441 case RTL_GIGA_MAC_VER_17: 6442 pci_clear_master(tp->pci_dev); 6443 6444 RTL_W8(tp, ChipCmd, CmdRxEnb); 6445 /* PCI commit */ 6446 RTL_R8(tp, ChipCmd); 6447 break; 6448 default: 6449 break; 6450 } 6451 } 6452 6453 static void rtl_shutdown(struct pci_dev *pdev) 6454 { 6455 struct net_device *dev = pci_get_drvdata(pdev); 6456 struct rtl8169_private *tp = netdev_priv(dev); 6457 6458 rtl8169_net_suspend(dev); 6459 6460 /* Restore original MAC address */ 6461 rtl_rar_set(tp, dev->perm_addr); 6462 6463 rtl8169_hw_reset(tp); 6464 6465 if (system_state == SYSTEM_POWER_OFF) { 6466 if (tp->saved_wolopts) { 6467 rtl_wol_suspend_quirk(tp); 6468 rtl_wol_shutdown_quirk(tp); 6469 } 6470 6471 pci_wake_from_d3(pdev, true); 6472 pci_set_power_state(pdev, PCI_D3hot); 6473 } 6474 } 6475 6476 static void rtl_remove_one(struct pci_dev *pdev) 6477 { 6478 struct net_device *dev = pci_get_drvdata(pdev); 6479 struct rtl8169_private *tp = netdev_priv(dev); 6480 6481 if (r8168_check_dash(tp)) 6482 rtl8168_driver_stop(tp); 6483 6484 netif_napi_del(&tp->napi); 6485 6486 unregister_netdev(dev); 6487 mdiobus_unregister(tp->phydev->mdio.bus); 6488 6489 rtl_release_firmware(tp); 6490 6491 if (pci_dev_run_wake(pdev)) 6492 pm_runtime_get_noresume(&pdev->dev); 6493 6494 /* restore original MAC address */ 6495 rtl_rar_set(tp, dev->perm_addr); 6496 } 6497 6498 static const struct net_device_ops rtl_netdev_ops = { 6499 .ndo_open = rtl_open, 6500 .ndo_stop = rtl8169_close, 6501 .ndo_get_stats64 = rtl8169_get_stats64, 6502 .ndo_start_xmit = rtl8169_start_xmit, 6503 .ndo_features_check = rtl8169_features_check, 6504 .ndo_tx_timeout = rtl8169_tx_timeout, 6505 .ndo_validate_addr = eth_validate_addr, 6506 .ndo_change_mtu = rtl8169_change_mtu, 6507 .ndo_fix_features = rtl8169_fix_features, 6508 .ndo_set_features = rtl8169_set_features, 6509 .ndo_set_mac_address = rtl_set_mac_address, 6510 .ndo_do_ioctl = rtl8169_ioctl, 6511 .ndo_set_rx_mode = rtl_set_rx_mode, 6512 #ifdef CONFIG_NET_POLL_CONTROLLER 6513 .ndo_poll_controller = rtl8169_netpoll, 6514 #endif 6515 6516 }; 6517 6518 static void rtl_set_irq_mask(struct rtl8169_private *tp) 6519 { 6520 tp->irq_mask = RTL_EVENT_NAPI | LinkChg; 6521 6522 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 6523 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 6524 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 6525 /* special workaround needed */ 6526 tp->irq_mask |= RxFIFOOver; 6527 else 6528 tp->irq_mask |= RxOverflow; 6529 } 6530 6531 static int rtl_alloc_irq(struct rtl8169_private *tp) 6532 { 6533 unsigned int flags; 6534 6535 switch (tp->mac_version) { 6536 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6537 rtl_unlock_config_regs(tp); 6538 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 6539 rtl_lock_config_regs(tp); 6540 /* fall through */ 6541 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24: 6542 flags = PCI_IRQ_LEGACY; 6543 break; 6544 default: 6545 flags = PCI_IRQ_ALL_TYPES; 6546 break; 6547 } 6548 6549 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 6550 } 6551 6552 static void rtl_read_mac_address(struct rtl8169_private *tp, 6553 u8 mac_addr[ETH_ALEN]) 6554 { 6555 /* Get MAC address */ 6556 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 6557 u32 value = rtl_eri_read(tp, 0xe0); 6558 6559 mac_addr[0] = (value >> 0) & 0xff; 6560 mac_addr[1] = (value >> 8) & 0xff; 6561 mac_addr[2] = (value >> 16) & 0xff; 6562 mac_addr[3] = (value >> 24) & 0xff; 6563 6564 value = rtl_eri_read(tp, 0xe4); 6565 mac_addr[4] = (value >> 0) & 0xff; 6566 mac_addr[5] = (value >> 8) & 0xff; 6567 } 6568 } 6569 6570 DECLARE_RTL_COND(rtl_link_list_ready_cond) 6571 { 6572 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 6573 } 6574 6575 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 6576 { 6577 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 6578 } 6579 6580 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 6581 { 6582 struct rtl8169_private *tp = mii_bus->priv; 6583 6584 if (phyaddr > 0) 6585 return -ENODEV; 6586 6587 return rtl_readphy(tp, phyreg); 6588 } 6589 6590 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 6591 int phyreg, u16 val) 6592 { 6593 struct rtl8169_private *tp = mii_bus->priv; 6594 6595 if (phyaddr > 0) 6596 return -ENODEV; 6597 6598 rtl_writephy(tp, phyreg, val); 6599 6600 return 0; 6601 } 6602 6603 static int r8169_mdio_register(struct rtl8169_private *tp) 6604 { 6605 struct pci_dev *pdev = tp->pci_dev; 6606 struct mii_bus *new_bus; 6607 int ret; 6608 6609 new_bus = devm_mdiobus_alloc(&pdev->dev); 6610 if (!new_bus) 6611 return -ENOMEM; 6612 6613 new_bus->name = "r8169"; 6614 new_bus->priv = tp; 6615 new_bus->parent = &pdev->dev; 6616 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 6617 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 6618 6619 new_bus->read = r8169_mdio_read_reg; 6620 new_bus->write = r8169_mdio_write_reg; 6621 6622 ret = mdiobus_register(new_bus); 6623 if (ret) 6624 return ret; 6625 6626 tp->phydev = mdiobus_get_phy(new_bus, 0); 6627 if (!tp->phydev) { 6628 mdiobus_unregister(new_bus); 6629 return -ENODEV; 6630 } 6631 6632 /* PHY will be woken up in rtl_open() */ 6633 phy_suspend(tp->phydev); 6634 6635 return 0; 6636 } 6637 6638 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 6639 { 6640 tp->ocp_base = OCP_STD_PHY_BASE; 6641 6642 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 6643 6644 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42)) 6645 return; 6646 6647 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42)) 6648 return; 6649 6650 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 6651 msleep(1); 6652 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 6653 6654 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 6655 6656 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42)) 6657 return; 6658 6659 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 6660 6661 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 6662 } 6663 6664 static void rtl_hw_initialize(struct rtl8169_private *tp) 6665 { 6666 switch (tp->mac_version) { 6667 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51: 6668 rtl8168ep_stop_cmac(tp); 6669 /* fall through */ 6670 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 6671 rtl_hw_init_8168g(tp); 6672 break; 6673 default: 6674 break; 6675 } 6676 } 6677 6678 static int rtl_jumbo_max(struct rtl8169_private *tp) 6679 { 6680 /* Non-GBit versions don't support jumbo frames */ 6681 if (!tp->supports_gmii) 6682 return JUMBO_1K; 6683 6684 switch (tp->mac_version) { 6685 /* RTL8169 */ 6686 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 6687 return JUMBO_7K; 6688 /* RTL8168b */ 6689 case RTL_GIGA_MAC_VER_11: 6690 case RTL_GIGA_MAC_VER_12: 6691 case RTL_GIGA_MAC_VER_17: 6692 return JUMBO_4K; 6693 /* RTL8168c */ 6694 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 6695 return JUMBO_6K; 6696 default: 6697 return JUMBO_9K; 6698 } 6699 } 6700 6701 static void rtl_disable_clk(void *data) 6702 { 6703 clk_disable_unprepare(data); 6704 } 6705 6706 static int rtl_get_ether_clk(struct rtl8169_private *tp) 6707 { 6708 struct device *d = tp_to_dev(tp); 6709 struct clk *clk; 6710 int rc; 6711 6712 clk = devm_clk_get(d, "ether_clk"); 6713 if (IS_ERR(clk)) { 6714 rc = PTR_ERR(clk); 6715 if (rc == -ENOENT) 6716 /* clk-core allows NULL (for suspend / resume) */ 6717 rc = 0; 6718 else if (rc != -EPROBE_DEFER) 6719 dev_err(d, "failed to get clk: %d\n", rc); 6720 } else { 6721 tp->clk = clk; 6722 rc = clk_prepare_enable(clk); 6723 if (rc) 6724 dev_err(d, "failed to enable clk: %d\n", rc); 6725 else 6726 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 6727 } 6728 6729 return rc; 6730 } 6731 6732 static void rtl_init_mac_address(struct rtl8169_private *tp) 6733 { 6734 struct net_device *dev = tp->dev; 6735 u8 *mac_addr = dev->dev_addr; 6736 int rc, i; 6737 6738 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 6739 if (!rc) 6740 goto done; 6741 6742 rtl_read_mac_address(tp, mac_addr); 6743 if (is_valid_ether_addr(mac_addr)) 6744 goto done; 6745 6746 for (i = 0; i < ETH_ALEN; i++) 6747 mac_addr[i] = RTL_R8(tp, MAC0 + i); 6748 if (is_valid_ether_addr(mac_addr)) 6749 goto done; 6750 6751 eth_hw_addr_random(dev); 6752 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 6753 done: 6754 rtl_rar_set(tp, mac_addr); 6755 } 6756 6757 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 6758 { 6759 struct rtl8169_private *tp; 6760 struct net_device *dev; 6761 int chipset, region; 6762 int jumbo_max, rc; 6763 6764 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 6765 if (!dev) 6766 return -ENOMEM; 6767 6768 SET_NETDEV_DEV(dev, &pdev->dev); 6769 dev->netdev_ops = &rtl_netdev_ops; 6770 tp = netdev_priv(dev); 6771 tp->dev = dev; 6772 tp->pci_dev = pdev; 6773 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); 6774 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 6775 6776 /* Get the *optional* external "ether_clk" used on some boards */ 6777 rc = rtl_get_ether_clk(tp); 6778 if (rc) 6779 return rc; 6780 6781 /* Disable ASPM completely as that cause random device stop working 6782 * problems as well as full system hangs for some PCIe devices users. 6783 */ 6784 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 6785 PCIE_LINK_STATE_L1); 6786 tp->aspm_manageable = !rc; 6787 6788 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 6789 rc = pcim_enable_device(pdev); 6790 if (rc < 0) { 6791 dev_err(&pdev->dev, "enable failure\n"); 6792 return rc; 6793 } 6794 6795 if (pcim_set_mwi(pdev) < 0) 6796 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 6797 6798 /* use first MMIO region */ 6799 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 6800 if (region < 0) { 6801 dev_err(&pdev->dev, "no MMIO resource found\n"); 6802 return -ENODEV; 6803 } 6804 6805 /* check for weird/broken PCI region reporting */ 6806 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 6807 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 6808 return -ENODEV; 6809 } 6810 6811 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 6812 if (rc < 0) { 6813 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 6814 return rc; 6815 } 6816 6817 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 6818 6819 /* Identify chip attached to board */ 6820 rtl8169_get_mac_version(tp); 6821 if (tp->mac_version == RTL_GIGA_MAC_NONE) 6822 return -ENODEV; 6823 6824 tp->cp_cmd = RTL_R16(tp, CPlusCmd); 6825 6826 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 6827 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 6828 dev->features |= NETIF_F_HIGHDMA; 6829 6830 rtl_init_rxcfg(tp); 6831 6832 rtl8169_irq_mask_and_ack(tp); 6833 6834 rtl_hw_initialize(tp); 6835 6836 rtl_hw_reset(tp); 6837 6838 pci_set_master(pdev); 6839 6840 chipset = tp->mac_version; 6841 6842 rc = rtl_alloc_irq(tp); 6843 if (rc < 0) { 6844 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 6845 return rc; 6846 } 6847 6848 mutex_init(&tp->wk.mutex); 6849 INIT_WORK(&tp->wk.work, rtl_task); 6850 u64_stats_init(&tp->rx_stats.syncp); 6851 u64_stats_init(&tp->tx_stats.syncp); 6852 6853 rtl_init_mac_address(tp); 6854 6855 dev->ethtool_ops = &rtl8169_ethtool_ops; 6856 6857 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 6858 6859 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 6860 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 6861 NETIF_F_HW_VLAN_CTAG_RX; 6862 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 6863 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX | 6864 NETIF_F_HW_VLAN_CTAG_RX; 6865 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 6866 NETIF_F_HIGHDMA; 6867 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 6868 6869 tp->cp_cmd |= RxChkSum | RxVlan; 6870 6871 /* 6872 * Pretend we are using VLANs; This bypasses a nasty bug where 6873 * Interrupts stop flowing on high load on 8110SCd controllers. 6874 */ 6875 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 6876 /* Disallow toggling */ 6877 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 6878 6879 if (rtl_chip_supports_csum_v2(tp)) { 6880 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 6881 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 6882 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 6883 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 6884 } else { 6885 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 6886 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 6887 } 6888 6889 /* RTL8168e-vl has a HW issue with TSO */ 6890 if (tp->mac_version == RTL_GIGA_MAC_VER_34) { 6891 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 6892 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 6893 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG); 6894 } 6895 6896 dev->hw_features |= NETIF_F_RXALL; 6897 dev->hw_features |= NETIF_F_RXFCS; 6898 6899 /* MTU range: 60 - hw-specific max */ 6900 dev->min_mtu = ETH_ZLEN; 6901 jumbo_max = rtl_jumbo_max(tp); 6902 dev->max_mtu = jumbo_max; 6903 6904 rtl_set_irq_mask(tp); 6905 6906 tp->fw_name = rtl_chip_infos[chipset].fw_name; 6907 6908 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 6909 &tp->counters_phys_addr, 6910 GFP_KERNEL); 6911 if (!tp->counters) 6912 return -ENOMEM; 6913 6914 pci_set_drvdata(pdev, dev); 6915 6916 rc = r8169_mdio_register(tp); 6917 if (rc) 6918 return rc; 6919 6920 /* chip gets powered up in rtl_open() */ 6921 rtl_pll_power_down(tp); 6922 6923 rc = register_netdev(dev); 6924 if (rc) 6925 goto err_mdio_unregister; 6926 6927 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n", 6928 rtl_chip_infos[chipset].name, dev->dev_addr, 6929 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf, 6930 pci_irq_vector(pdev, 0)); 6931 6932 if (jumbo_max > JUMBO_1K) 6933 netif_info(tp, probe, dev, 6934 "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 6935 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 6936 "ok" : "ko"); 6937 6938 if (r8168_check_dash(tp)) 6939 rtl8168_driver_start(tp); 6940 6941 if (pci_dev_run_wake(pdev)) 6942 pm_runtime_put_sync(&pdev->dev); 6943 6944 return 0; 6945 6946 err_mdio_unregister: 6947 mdiobus_unregister(tp->phydev->mdio.bus); 6948 return rc; 6949 } 6950 6951 static struct pci_driver rtl8169_pci_driver = { 6952 .name = MODULENAME, 6953 .id_table = rtl8169_pci_tbl, 6954 .probe = rtl_init_one, 6955 .remove = rtl_remove_one, 6956 .shutdown = rtl_shutdown, 6957 .driver.pm = RTL8169_PM_OPS, 6958 }; 6959 6960 module_pci_driver(rtl8169_pci_driver); 6961