1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <linux/unaligned.h> 32 #include <net/ip6_checksum.h> 33 #include <net/netdev_queues.h> 34 35 #include "r8169.h" 36 #include "r8169_firmware.h" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 56 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 57 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 58 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 59 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 60 61 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 62 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 63 64 #define R8169_REGS_SIZE 256 65 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 66 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 67 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 68 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 69 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 70 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 71 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 72 73 #define OCP_STD_PHY_BASE 0xa400 74 75 #define RTL_CFG_NO_GBIT 1 76 77 /* write/read MMIO register */ 78 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 79 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 80 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 81 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 82 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 83 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 84 85 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 90 static const struct { 91 const char *name; 92 const char *fw_name; 93 } rtl_chip_infos[] = { 94 /* PCI devices. */ 95 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 96 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 97 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 98 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 99 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 100 /* PCI-E devices. */ 101 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 102 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 103 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 104 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 105 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 106 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 107 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 109 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 110 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 115 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 116 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 117 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 118 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 119 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 120 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 121 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 122 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 123 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 124 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 125 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 126 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 127 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 128 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 129 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 130 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 131 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 132 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 133 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 134 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 135 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 136 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 137 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 138 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 139 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 140 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 141 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 142 [RTL_GIGA_MAC_VER_66] = {"RTL8126A", FIRMWARE_8126A_3}, 143 }; 144 145 static const struct pci_device_id rtl8169_pci_tbl[] = { 146 { PCI_VDEVICE(REALTEK, 0x2502) }, 147 { PCI_VDEVICE(REALTEK, 0x2600) }, 148 { PCI_VDEVICE(REALTEK, 0x8129) }, 149 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 150 { PCI_VDEVICE(REALTEK, 0x8161) }, 151 { PCI_VDEVICE(REALTEK, 0x8162) }, 152 { PCI_VDEVICE(REALTEK, 0x8167) }, 153 { PCI_VDEVICE(REALTEK, 0x8168) }, 154 { PCI_VDEVICE(NCUBE, 0x8168) }, 155 { PCI_VDEVICE(REALTEK, 0x8169) }, 156 { PCI_VENDOR_ID_DLINK, 0x4300, 157 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 158 { PCI_VDEVICE(DLINK, 0x4300) }, 159 { PCI_VDEVICE(DLINK, 0x4302) }, 160 { PCI_VDEVICE(AT, 0xc107) }, 161 { PCI_VDEVICE(USR, 0x0116) }, 162 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 163 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 164 { PCI_VDEVICE(REALTEK, 0x8125) }, 165 { PCI_VDEVICE(REALTEK, 0x8126) }, 166 { PCI_VDEVICE(REALTEK, 0x3000) }, 167 {} 168 }; 169 170 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 171 172 enum rtl_registers { 173 MAC0 = 0, /* Ethernet hardware address. */ 174 MAC4 = 4, 175 MAR0 = 8, /* Multicast filter. */ 176 CounterAddrLow = 0x10, 177 CounterAddrHigh = 0x14, 178 TxDescStartAddrLow = 0x20, 179 TxDescStartAddrHigh = 0x24, 180 TxHDescStartAddrLow = 0x28, 181 TxHDescStartAddrHigh = 0x2c, 182 FLASH = 0x30, 183 ERSR = 0x36, 184 ChipCmd = 0x37, 185 TxPoll = 0x38, 186 IntrMask = 0x3c, 187 IntrStatus = 0x3e, 188 189 TxConfig = 0x40, 190 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 191 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 192 193 RxConfig = 0x44, 194 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 195 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 196 #define RXCFG_FIFO_SHIFT 13 197 /* No threshold before first PCI xfer */ 198 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 199 #define RX_EARLY_OFF (1 << 11) 200 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 201 #define RXCFG_DMA_SHIFT 8 202 /* Unlimited maximum PCI burst. */ 203 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 204 205 Cfg9346 = 0x50, 206 Config0 = 0x51, 207 Config1 = 0x52, 208 Config2 = 0x53, 209 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 210 211 Config3 = 0x54, 212 Config4 = 0x55, 213 Config5 = 0x56, 214 PHYAR = 0x60, 215 PHYstatus = 0x6c, 216 RxMaxSize = 0xda, 217 CPlusCmd = 0xe0, 218 IntrMitigate = 0xe2, 219 220 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 221 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 222 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 223 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 224 225 #define RTL_COALESCE_T_MAX 0x0fU 226 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 227 228 RxDescAddrLow = 0xe4, 229 RxDescAddrHigh = 0xe8, 230 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 231 232 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 233 234 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 235 236 #define TxPacketMax (8064 >> 7) 237 #define EarlySize 0x27 238 239 FuncEvent = 0xf0, 240 FuncEventMask = 0xf4, 241 FuncPresetState = 0xf8, 242 IBCR0 = 0xf8, 243 IBCR2 = 0xf9, 244 IBIMR0 = 0xfa, 245 IBISR0 = 0xfb, 246 FuncForceEvent = 0xfc, 247 }; 248 249 enum rtl8168_8101_registers { 250 CSIDR = 0x64, 251 CSIAR = 0x68, 252 #define CSIAR_FLAG 0x80000000 253 #define CSIAR_WRITE_CMD 0x80000000 254 #define CSIAR_BYTE_ENABLE 0x0000f000 255 #define CSIAR_ADDR_MASK 0x00000fff 256 PMCH = 0x6f, 257 #define D3COLD_NO_PLL_DOWN BIT(7) 258 #define D3HOT_NO_PLL_DOWN BIT(6) 259 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 260 EPHYAR = 0x80, 261 #define EPHYAR_FLAG 0x80000000 262 #define EPHYAR_WRITE_CMD 0x80000000 263 #define EPHYAR_REG_MASK 0x1f 264 #define EPHYAR_REG_SHIFT 16 265 #define EPHYAR_DATA_MASK 0xffff 266 DLLPR = 0xd0, 267 #define PFM_EN (1 << 6) 268 #define TX_10M_PS_EN (1 << 7) 269 DBG_REG = 0xd1, 270 #define FIX_NAK_1 (1 << 4) 271 #define FIX_NAK_2 (1 << 3) 272 TWSI = 0xd2, 273 MCU = 0xd3, 274 #define NOW_IS_OOB (1 << 7) 275 #define TX_EMPTY (1 << 5) 276 #define RX_EMPTY (1 << 4) 277 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 278 #define EN_NDP (1 << 3) 279 #define EN_OOB_RESET (1 << 2) 280 #define LINK_LIST_RDY (1 << 1) 281 EFUSEAR = 0xdc, 282 #define EFUSEAR_FLAG 0x80000000 283 #define EFUSEAR_WRITE_CMD 0x80000000 284 #define EFUSEAR_READ_CMD 0x00000000 285 #define EFUSEAR_REG_MASK 0x03ff 286 #define EFUSEAR_REG_SHIFT 8 287 #define EFUSEAR_DATA_MASK 0xff 288 MISC_1 = 0xf2, 289 #define PFM_D3COLD_EN (1 << 6) 290 }; 291 292 enum rtl8168_registers { 293 LED_CTRL = 0x18, 294 LED_FREQ = 0x1a, 295 EEE_LED = 0x1b, 296 ERIDR = 0x70, 297 ERIAR = 0x74, 298 #define ERIAR_FLAG 0x80000000 299 #define ERIAR_WRITE_CMD 0x80000000 300 #define ERIAR_READ_CMD 0x00000000 301 #define ERIAR_ADDR_BYTE_ALIGN 4 302 #define ERIAR_TYPE_SHIFT 16 303 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 306 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_MASK_SHIFT 12 308 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 311 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 313 EPHY_RXER_NUM = 0x7c, 314 OCPDR = 0xb0, /* OCP GPHY access */ 315 #define OCPDR_WRITE_CMD 0x80000000 316 #define OCPDR_READ_CMD 0x00000000 317 #define OCPDR_REG_MASK 0x7f 318 #define OCPDR_GPHY_REG_SHIFT 16 319 #define OCPDR_DATA_MASK 0xffff 320 OCPAR = 0xb4, 321 #define OCPAR_FLAG 0x80000000 322 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 323 #define OCPAR_GPHY_READ_CMD 0x0000f060 324 GPHY_OCP = 0xb8, 325 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 326 MISC = 0xf0, /* 8168e only. */ 327 #define TXPLA_RST (1 << 29) 328 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 329 #define PWM_EN (1 << 22) 330 #define RXDV_GATED_EN (1 << 19) 331 #define EARLY_TALLY_EN (1 << 16) 332 }; 333 334 enum rtl8125_registers { 335 LEDSEL0 = 0x18, 336 INT_CFG0_8125 = 0x34, 337 #define INT_CFG0_ENABLE_8125 BIT(0) 338 #define INT_CFG0_CLKREQEN BIT(3) 339 IntrMask_8125 = 0x38, 340 IntrStatus_8125 = 0x3c, 341 INT_CFG1_8125 = 0x7a, 342 LEDSEL2 = 0x84, 343 LEDSEL1 = 0x86, 344 TxPoll_8125 = 0x90, 345 LEDSEL3 = 0x96, 346 MAC0_BKP = 0x19e0, 347 EEE_TXIDLE_TIMER_8125 = 0x6048, 348 }; 349 350 #define LEDSEL_MASK_8125 0x23f 351 352 #define RX_VLAN_INNER_8125 BIT(22) 353 #define RX_VLAN_OUTER_8125 BIT(23) 354 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 355 356 #define RX_FETCH_DFLT_8125 (8 << 27) 357 358 enum rtl_register_content { 359 /* InterruptStatusBits */ 360 SYSErr = 0x8000, 361 PCSTimeout = 0x4000, 362 SWInt = 0x0100, 363 TxDescUnavail = 0x0080, 364 RxFIFOOver = 0x0040, 365 LinkChg = 0x0020, 366 RxOverflow = 0x0010, 367 TxErr = 0x0008, 368 TxOK = 0x0004, 369 RxErr = 0x0002, 370 RxOK = 0x0001, 371 372 /* RxStatusDesc */ 373 RxRWT = (1 << 22), 374 RxRES = (1 << 21), 375 RxRUNT = (1 << 20), 376 RxCRC = (1 << 19), 377 378 /* ChipCmdBits */ 379 StopReq = 0x80, 380 CmdReset = 0x10, 381 CmdRxEnb = 0x08, 382 CmdTxEnb = 0x04, 383 RxBufEmpty = 0x01, 384 385 /* TXPoll register p.5 */ 386 HPQ = 0x80, /* Poll cmd on the high prio queue */ 387 NPQ = 0x40, /* Poll cmd on the low prio queue */ 388 FSWInt = 0x01, /* Forced software interrupt */ 389 390 /* Cfg9346Bits */ 391 Cfg9346_Lock = 0x00, 392 Cfg9346_Unlock = 0xc0, 393 394 /* rx_mode_bits */ 395 AcceptErr = 0x20, 396 AcceptRunt = 0x10, 397 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 398 AcceptBroadcast = 0x08, 399 AcceptMulticast = 0x04, 400 AcceptMyPhys = 0x02, 401 AcceptAllPhys = 0x01, 402 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 403 #define RX_CONFIG_ACCEPT_MASK 0x3f 404 405 /* TxConfigBits */ 406 TxInterFrameGapShift = 24, 407 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 408 409 /* Config1 register p.24 */ 410 LEDS1 = (1 << 7), 411 LEDS0 = (1 << 6), 412 Speed_down = (1 << 4), 413 MEMMAP = (1 << 3), 414 IOMAP = (1 << 2), 415 VPD = (1 << 1), 416 PMEnable = (1 << 0), /* Power Management Enable */ 417 418 /* Config2 register p. 25 */ 419 ClkReqEn = (1 << 7), /* Clock Request Enable */ 420 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 421 PCI_Clock_66MHz = 0x01, 422 PCI_Clock_33MHz = 0x00, 423 424 /* Config3 register p.25 */ 425 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 426 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 427 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 428 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 429 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 430 431 /* Config4 register */ 432 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 433 434 /* Config5 register p.27 */ 435 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 436 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 437 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 438 Spi_en = (1 << 3), 439 LanWake = (1 << 1), /* LanWake enable/disable */ 440 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 441 ASPM_en = (1 << 0), /* ASPM enable */ 442 443 /* CPlusCmd p.31 */ 444 EnableBist = (1 << 15), // 8168 8101 445 Mac_dbgo_oe = (1 << 14), // 8168 8101 446 EnAnaPLL = (1 << 14), // 8169 447 Normal_mode = (1 << 13), // unused 448 Force_half_dup = (1 << 12), // 8168 8101 449 Force_rxflow_en = (1 << 11), // 8168 8101 450 Force_txflow_en = (1 << 10), // 8168 8101 451 Cxpl_dbg_sel = (1 << 9), // 8168 8101 452 ASF = (1 << 8), // 8168 8101 453 PktCntrDisable = (1 << 7), // 8168 8101 454 Mac_dbgo_sel = 0x001c, // 8168 455 RxVlan = (1 << 6), 456 RxChkSum = (1 << 5), 457 PCIDAC = (1 << 4), 458 PCIMulRW = (1 << 3), 459 #define INTT_MASK GENMASK(1, 0) 460 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 461 462 /* rtl8169_PHYstatus */ 463 TBI_Enable = 0x80, 464 TxFlowCtrl = 0x40, 465 RxFlowCtrl = 0x20, 466 _1000bpsF = 0x10, 467 _100bps = 0x08, 468 _10bps = 0x04, 469 LinkStatus = 0x02, 470 FullDup = 0x01, 471 472 /* ResetCounterCommand */ 473 CounterReset = 0x1, 474 475 /* DumpCounterCommand */ 476 CounterDump = 0x8, 477 478 /* magic enable v2 */ 479 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 480 }; 481 482 enum rtl_desc_bit { 483 /* First doubleword. */ 484 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 485 RingEnd = (1 << 30), /* End of descriptor ring */ 486 FirstFrag = (1 << 29), /* First segment of a packet */ 487 LastFrag = (1 << 28), /* Final segment of a packet */ 488 }; 489 490 /* Generic case. */ 491 enum rtl_tx_desc_bit { 492 /* First doubleword. */ 493 TD_LSO = (1 << 27), /* Large Send Offload */ 494 #define TD_MSS_MAX 0x07ffu /* MSS value */ 495 496 /* Second doubleword. */ 497 TxVlanTag = (1 << 17), /* Add VLAN tag */ 498 }; 499 500 /* 8169, 8168b and 810x except 8102e. */ 501 enum rtl_tx_desc_bit_0 { 502 /* First doubleword. */ 503 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 504 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 505 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 506 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 507 }; 508 509 /* 8102e, 8168c and beyond. */ 510 enum rtl_tx_desc_bit_1 { 511 /* First doubleword. */ 512 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 513 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 514 #define GTTCPHO_SHIFT 18 515 #define GTTCPHO_MAX 0x7f 516 517 /* Second doubleword. */ 518 #define TCPHO_SHIFT 18 519 #define TCPHO_MAX 0x3ff 520 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 521 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 522 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 523 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 524 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 525 }; 526 527 enum rtl_rx_desc_bit { 528 /* Rx private */ 529 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 530 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 531 532 #define RxProtoUDP (PID1) 533 #define RxProtoTCP (PID0) 534 #define RxProtoIP (PID1 | PID0) 535 #define RxProtoMask RxProtoIP 536 537 IPFail = (1 << 16), /* IP checksum failed */ 538 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 539 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 540 541 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 542 543 RxVlanTag = (1 << 16), /* VLAN tag available */ 544 }; 545 546 #define RTL_GSO_MAX_SIZE_V1 32000 547 #define RTL_GSO_MAX_SEGS_V1 24 548 #define RTL_GSO_MAX_SIZE_V2 64000 549 #define RTL_GSO_MAX_SEGS_V2 64 550 551 struct TxDesc { 552 __le32 opts1; 553 __le32 opts2; 554 __le64 addr; 555 }; 556 557 struct RxDesc { 558 __le32 opts1; 559 __le32 opts2; 560 __le64 addr; 561 }; 562 563 struct ring_info { 564 struct sk_buff *skb; 565 u32 len; 566 }; 567 568 struct rtl8169_counters { 569 __le64 tx_packets; 570 __le64 rx_packets; 571 __le64 tx_errors; 572 __le32 rx_errors; 573 __le16 rx_missed; 574 __le16 align_errors; 575 __le32 tx_one_collision; 576 __le32 tx_multi_collision; 577 __le64 rx_unicast; 578 __le64 rx_broadcast; 579 __le32 rx_multicast; 580 __le16 tx_aborted; 581 __le16 tx_underrun; 582 /* new since RTL8125 */ 583 __le64 tx_octets; 584 __le64 rx_octets; 585 __le64 rx_multicast64; 586 __le64 tx_unicast64; 587 __le64 tx_broadcast64; 588 __le64 tx_multicast64; 589 __le32 tx_pause_on; 590 __le32 tx_pause_off; 591 __le32 tx_pause_all; 592 __le32 tx_deferred; 593 __le32 tx_late_collision; 594 __le32 tx_all_collision; 595 __le32 tx_aborted32; 596 __le32 align_errors32; 597 __le32 rx_frame_too_long; 598 __le32 rx_runt; 599 __le32 rx_pause_on; 600 __le32 rx_pause_off; 601 __le32 rx_pause_all; 602 __le32 rx_unknown_opcode; 603 __le32 rx_mac_error; 604 __le32 tx_underrun32; 605 __le32 rx_mac_missed; 606 __le32 rx_tcam_dropped; 607 __le32 tdu; 608 __le32 rdu; 609 }; 610 611 struct rtl8169_tc_offsets { 612 bool inited; 613 __le64 tx_errors; 614 __le32 tx_multi_collision; 615 __le16 tx_aborted; 616 __le16 rx_missed; 617 }; 618 619 enum rtl_flag { 620 RTL_FLAG_TASK_ENABLED = 0, 621 RTL_FLAG_TASK_RESET_PENDING, 622 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, 623 RTL_FLAG_TASK_TX_TIMEOUT, 624 RTL_FLAG_MAX 625 }; 626 627 enum rtl_dash_type { 628 RTL_DASH_NONE, 629 RTL_DASH_DP, 630 RTL_DASH_EP, 631 }; 632 633 struct rtl8169_private { 634 void __iomem *mmio_addr; /* memory map physical address */ 635 struct pci_dev *pci_dev; 636 struct net_device *dev; 637 struct phy_device *phydev; 638 struct napi_struct napi; 639 enum mac_version mac_version; 640 enum rtl_dash_type dash_type; 641 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 642 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 643 u32 dirty_tx; 644 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 645 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 646 dma_addr_t TxPhyAddr; 647 dma_addr_t RxPhyAddr; 648 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 649 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 650 u16 cp_cmd; 651 u16 tx_lpi_timer; 652 u32 irq_mask; 653 int irq; 654 struct clk *clk; 655 656 struct { 657 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 658 struct work_struct work; 659 } wk; 660 661 raw_spinlock_t config25_lock; 662 raw_spinlock_t mac_ocp_lock; 663 struct mutex led_lock; /* serialize LED ctrl RMW access */ 664 665 raw_spinlock_t cfg9346_usage_lock; 666 int cfg9346_usage_count; 667 668 unsigned supports_gmii:1; 669 unsigned aspm_manageable:1; 670 unsigned dash_enabled:1; 671 dma_addr_t counters_phys_addr; 672 struct rtl8169_counters *counters; 673 struct rtl8169_tc_offsets tc_offset; 674 u32 saved_wolopts; 675 676 const char *fw_name; 677 struct rtl_fw *rtl_fw; 678 679 struct r8169_led_classdev *leds; 680 681 u32 ocp_base; 682 }; 683 684 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 685 686 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 687 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 688 MODULE_SOFTDEP("pre: realtek"); 689 MODULE_LICENSE("GPL"); 690 MODULE_FIRMWARE(FIRMWARE_8168D_1); 691 MODULE_FIRMWARE(FIRMWARE_8168D_2); 692 MODULE_FIRMWARE(FIRMWARE_8168E_1); 693 MODULE_FIRMWARE(FIRMWARE_8168E_2); 694 MODULE_FIRMWARE(FIRMWARE_8168E_3); 695 MODULE_FIRMWARE(FIRMWARE_8105E_1); 696 MODULE_FIRMWARE(FIRMWARE_8168F_1); 697 MODULE_FIRMWARE(FIRMWARE_8168F_2); 698 MODULE_FIRMWARE(FIRMWARE_8402_1); 699 MODULE_FIRMWARE(FIRMWARE_8411_1); 700 MODULE_FIRMWARE(FIRMWARE_8411_2); 701 MODULE_FIRMWARE(FIRMWARE_8106E_1); 702 MODULE_FIRMWARE(FIRMWARE_8106E_2); 703 MODULE_FIRMWARE(FIRMWARE_8168G_2); 704 MODULE_FIRMWARE(FIRMWARE_8168G_3); 705 MODULE_FIRMWARE(FIRMWARE_8168H_2); 706 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 707 MODULE_FIRMWARE(FIRMWARE_8107E_2); 708 MODULE_FIRMWARE(FIRMWARE_8125A_3); 709 MODULE_FIRMWARE(FIRMWARE_8125B_2); 710 MODULE_FIRMWARE(FIRMWARE_8126A_2); 711 MODULE_FIRMWARE(FIRMWARE_8126A_3); 712 713 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 714 { 715 return &tp->pci_dev->dev; 716 } 717 718 static void rtl_lock_config_regs(struct rtl8169_private *tp) 719 { 720 unsigned long flags; 721 722 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 723 if (!--tp->cfg9346_usage_count) 724 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 725 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 726 } 727 728 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 729 { 730 unsigned long flags; 731 732 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); 733 if (!tp->cfg9346_usage_count++) 734 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 735 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); 736 } 737 738 static void rtl_pci_commit(struct rtl8169_private *tp) 739 { 740 /* Read an arbitrary register to commit a preceding PCI write */ 741 RTL_R8(tp, ChipCmd); 742 } 743 744 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 745 { 746 unsigned long flags; 747 u8 val; 748 749 raw_spin_lock_irqsave(&tp->config25_lock, flags); 750 val = RTL_R8(tp, Config2); 751 RTL_W8(tp, Config2, (val & ~clear) | set); 752 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 753 } 754 755 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 756 { 757 unsigned long flags; 758 u8 val; 759 760 raw_spin_lock_irqsave(&tp->config25_lock, flags); 761 val = RTL_R8(tp, Config5); 762 RTL_W8(tp, Config5, (val & ~clear) | set); 763 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 764 } 765 766 static bool rtl_is_8125(struct rtl8169_private *tp) 767 { 768 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 769 } 770 771 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 772 { 773 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 774 tp->mac_version != RTL_GIGA_MAC_VER_39 && 775 tp->mac_version <= RTL_GIGA_MAC_VER_53; 776 } 777 778 static bool rtl_supports_eee(struct rtl8169_private *tp) 779 { 780 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 781 tp->mac_version != RTL_GIGA_MAC_VER_37 && 782 tp->mac_version != RTL_GIGA_MAC_VER_39; 783 } 784 785 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 786 { 787 int i; 788 789 for (i = 0; i < ETH_ALEN; i++) 790 mac[i] = RTL_R8(tp, reg + i); 791 } 792 793 struct rtl_cond { 794 bool (*check)(struct rtl8169_private *); 795 const char *msg; 796 }; 797 798 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 799 unsigned long usecs, int n, bool high) 800 { 801 int i; 802 803 for (i = 0; i < n; i++) { 804 if (c->check(tp) == high) 805 return true; 806 fsleep(usecs); 807 } 808 809 if (net_ratelimit()) 810 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 811 c->msg, !high, n, usecs); 812 return false; 813 } 814 815 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 816 const struct rtl_cond *c, 817 unsigned long d, int n) 818 { 819 return rtl_loop_wait(tp, c, d, n, true); 820 } 821 822 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 823 const struct rtl_cond *c, 824 unsigned long d, int n) 825 { 826 return rtl_loop_wait(tp, c, d, n, false); 827 } 828 829 #define DECLARE_RTL_COND(name) \ 830 static bool name ## _check(struct rtl8169_private *); \ 831 \ 832 static const struct rtl_cond name = { \ 833 .check = name ## _check, \ 834 .msg = #name \ 835 }; \ 836 \ 837 static bool name ## _check(struct rtl8169_private *tp) 838 839 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 840 { 841 struct device *dev = tp_to_dev(tp); 842 int ret; 843 844 ret = pm_runtime_resume_and_get(dev); 845 if (ret < 0) 846 return ret; 847 848 mutex_lock(&tp->led_lock); 849 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 850 mutex_unlock(&tp->led_lock); 851 852 pm_runtime_put_sync(dev); 853 854 return 0; 855 } 856 857 int rtl8168_get_led_mode(struct rtl8169_private *tp) 858 { 859 struct device *dev = tp_to_dev(tp); 860 int ret; 861 862 ret = pm_runtime_resume_and_get(dev); 863 if (ret < 0) 864 return ret; 865 866 ret = RTL_R16(tp, LED_CTRL); 867 868 pm_runtime_put_sync(dev); 869 870 return ret; 871 } 872 873 static int rtl8125_get_led_reg(int index) 874 { 875 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 876 877 return led_regs[index]; 878 } 879 880 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 881 { 882 int reg = rtl8125_get_led_reg(index); 883 struct device *dev = tp_to_dev(tp); 884 int ret; 885 u16 val; 886 887 ret = pm_runtime_resume_and_get(dev); 888 if (ret < 0) 889 return ret; 890 891 mutex_lock(&tp->led_lock); 892 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 893 RTL_W16(tp, reg, val | mode); 894 mutex_unlock(&tp->led_lock); 895 896 pm_runtime_put_sync(dev); 897 898 return 0; 899 } 900 901 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 902 { 903 int reg = rtl8125_get_led_reg(index); 904 struct device *dev = tp_to_dev(tp); 905 int ret; 906 907 ret = pm_runtime_resume_and_get(dev); 908 if (ret < 0) 909 return ret; 910 911 ret = RTL_R16(tp, reg); 912 913 pm_runtime_put_sync(dev); 914 915 return ret; 916 } 917 918 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 919 char *buf, int buf_len) 920 { 921 struct pci_dev *pdev = tp->pci_dev; 922 char pdom[8], pfun[8]; 923 int domain; 924 925 domain = pci_domain_nr(pdev->bus); 926 if (domain) 927 snprintf(pdom, sizeof(pdom), "P%d", domain); 928 else 929 pdom[0] = '\0'; 930 931 if (pdev->multifunction) 932 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 933 else 934 pfun[0] = '\0'; 935 936 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 937 PCI_SLOT(pdev->devfn), pfun, idx); 938 } 939 940 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 941 { 942 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 943 if (type == ERIAR_OOB && 944 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 945 tp->mac_version == RTL_GIGA_MAC_VER_53)) 946 *cmd |= 0xf70 << 18; 947 } 948 949 DECLARE_RTL_COND(rtl_eriar_cond) 950 { 951 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 952 } 953 954 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 955 u32 val, int type) 956 { 957 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 958 959 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 960 return; 961 962 RTL_W32(tp, ERIDR, val); 963 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 964 RTL_W32(tp, ERIAR, cmd); 965 966 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 967 } 968 969 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 970 u32 val) 971 { 972 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 973 } 974 975 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 976 { 977 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 978 979 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 980 RTL_W32(tp, ERIAR, cmd); 981 982 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 983 RTL_R32(tp, ERIDR) : ~0; 984 } 985 986 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 987 { 988 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 989 } 990 991 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 992 { 993 u32 val = rtl_eri_read(tp, addr); 994 995 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 996 } 997 998 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 999 { 1000 rtl_w0w1_eri(tp, addr, p, 0); 1001 } 1002 1003 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1004 { 1005 rtl_w0w1_eri(tp, addr, 0, m); 1006 } 1007 1008 static bool rtl_ocp_reg_failure(u32 reg) 1009 { 1010 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1011 } 1012 1013 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1014 { 1015 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1016 } 1017 1018 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1019 { 1020 if (rtl_ocp_reg_failure(reg)) 1021 return; 1022 1023 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1024 1025 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1026 } 1027 1028 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1029 { 1030 if (rtl_ocp_reg_failure(reg)) 1031 return 0; 1032 1033 RTL_W32(tp, GPHY_OCP, reg << 15); 1034 1035 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1036 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1037 } 1038 1039 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1040 { 1041 if (rtl_ocp_reg_failure(reg)) 1042 return; 1043 1044 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1045 } 1046 1047 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1048 { 1049 unsigned long flags; 1050 1051 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1052 __r8168_mac_ocp_write(tp, reg, data); 1053 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1054 } 1055 1056 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1057 { 1058 if (rtl_ocp_reg_failure(reg)) 1059 return 0; 1060 1061 RTL_W32(tp, OCPDR, reg << 15); 1062 1063 return RTL_R32(tp, OCPDR); 1064 } 1065 1066 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1067 { 1068 unsigned long flags; 1069 u16 val; 1070 1071 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1072 val = __r8168_mac_ocp_read(tp, reg); 1073 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1074 1075 return val; 1076 } 1077 1078 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1079 u16 set) 1080 { 1081 unsigned long flags; 1082 u16 data; 1083 1084 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1085 data = __r8168_mac_ocp_read(tp, reg); 1086 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1087 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1088 } 1089 1090 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1091 * PHY MCU interrupts before PHY power-down. 1092 */ 1093 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1094 { 1095 switch (tp->mac_version) { 1096 case RTL_GIGA_MAC_VER_40: 1097 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1098 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1099 else 1100 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1101 break; 1102 default: 1103 break; 1104 } 1105 }; 1106 1107 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1108 { 1109 if (reg == 0x1f) { 1110 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1111 return; 1112 } 1113 1114 if (tp->ocp_base != OCP_STD_PHY_BASE) 1115 reg -= 0x10; 1116 1117 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1118 rtl8168g_phy_suspend_quirk(tp, value); 1119 1120 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1121 } 1122 1123 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1124 { 1125 if (reg == 0x1f) 1126 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1127 1128 if (tp->ocp_base != OCP_STD_PHY_BASE) 1129 reg -= 0x10; 1130 1131 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1132 } 1133 1134 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1135 { 1136 if (reg == 0x1f) { 1137 tp->ocp_base = value << 4; 1138 return; 1139 } 1140 1141 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1142 } 1143 1144 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1145 { 1146 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1147 } 1148 1149 DECLARE_RTL_COND(rtl_phyar_cond) 1150 { 1151 return RTL_R32(tp, PHYAR) & 0x80000000; 1152 } 1153 1154 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1155 { 1156 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1157 1158 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1159 /* 1160 * According to hardware specs a 20us delay is required after write 1161 * complete indication, but before sending next command. 1162 */ 1163 udelay(20); 1164 } 1165 1166 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1167 { 1168 int value; 1169 1170 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1171 1172 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1173 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1174 1175 /* 1176 * According to hardware specs a 20us delay is required after read 1177 * complete indication, but before sending next command. 1178 */ 1179 udelay(20); 1180 1181 return value; 1182 } 1183 1184 DECLARE_RTL_COND(rtl_ocpar_cond) 1185 { 1186 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1187 } 1188 1189 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1190 1191 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1192 { 1193 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1194 } 1195 1196 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1197 { 1198 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1199 } 1200 1201 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1202 { 1203 r8168dp_2_mdio_start(tp); 1204 1205 r8169_mdio_write(tp, reg, value); 1206 1207 r8168dp_2_mdio_stop(tp); 1208 } 1209 1210 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1211 { 1212 int value; 1213 1214 /* Work around issue with chip reporting wrong PHY ID */ 1215 if (reg == MII_PHYSID2) 1216 return 0xc912; 1217 1218 r8168dp_2_mdio_start(tp); 1219 1220 value = r8169_mdio_read(tp, reg); 1221 1222 r8168dp_2_mdio_stop(tp); 1223 1224 return value; 1225 } 1226 1227 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1228 { 1229 switch (tp->mac_version) { 1230 case RTL_GIGA_MAC_VER_28: 1231 case RTL_GIGA_MAC_VER_31: 1232 r8168dp_2_mdio_write(tp, location, val); 1233 break; 1234 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1235 r8168g_mdio_write(tp, location, val); 1236 break; 1237 default: 1238 r8169_mdio_write(tp, location, val); 1239 break; 1240 } 1241 } 1242 1243 static int rtl_readphy(struct rtl8169_private *tp, int location) 1244 { 1245 switch (tp->mac_version) { 1246 case RTL_GIGA_MAC_VER_28: 1247 case RTL_GIGA_MAC_VER_31: 1248 return r8168dp_2_mdio_read(tp, location); 1249 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1250 return r8168g_mdio_read(tp, location); 1251 default: 1252 return r8169_mdio_read(tp, location); 1253 } 1254 } 1255 1256 DECLARE_RTL_COND(rtl_ephyar_cond) 1257 { 1258 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1259 } 1260 1261 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1262 { 1263 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1264 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1265 1266 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1267 1268 udelay(10); 1269 } 1270 1271 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1272 { 1273 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1274 1275 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1276 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1277 } 1278 1279 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1280 { 1281 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1282 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1283 RTL_R32(tp, OCPDR) : ~0; 1284 } 1285 1286 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1287 { 1288 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1289 } 1290 1291 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1292 u32 data) 1293 { 1294 RTL_W32(tp, OCPDR, data); 1295 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1296 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1297 } 1298 1299 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1300 u32 data) 1301 { 1302 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1303 data, ERIAR_OOB); 1304 } 1305 1306 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1307 { 1308 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1309 1310 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1311 } 1312 1313 #define OOB_CMD_RESET 0x00 1314 #define OOB_CMD_DRIVER_START 0x05 1315 #define OOB_CMD_DRIVER_STOP 0x06 1316 1317 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1318 { 1319 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1320 } 1321 1322 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1323 { 1324 u16 reg; 1325 1326 reg = rtl8168_get_ocp_reg(tp); 1327 1328 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1329 } 1330 1331 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1332 { 1333 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1334 } 1335 1336 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1337 { 1338 return RTL_R8(tp, IBISR0) & 0x20; 1339 } 1340 1341 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1342 { 1343 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1344 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1345 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1346 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1347 } 1348 1349 static void rtl_dash_loop_wait(struct rtl8169_private *tp, 1350 const struct rtl_cond *c, 1351 unsigned long usecs, int n, bool high) 1352 { 1353 if (!tp->dash_enabled) 1354 return; 1355 rtl_loop_wait(tp, c, usecs, n, high); 1356 } 1357 1358 static void rtl_dash_loop_wait_high(struct rtl8169_private *tp, 1359 const struct rtl_cond *c, 1360 unsigned long d, int n) 1361 { 1362 rtl_dash_loop_wait(tp, c, d, n, true); 1363 } 1364 1365 static void rtl_dash_loop_wait_low(struct rtl8169_private *tp, 1366 const struct rtl_cond *c, 1367 unsigned long d, int n) 1368 { 1369 rtl_dash_loop_wait(tp, c, d, n, false); 1370 } 1371 1372 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1373 { 1374 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1375 rtl_dash_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1376 } 1377 1378 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1379 { 1380 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1381 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1382 rtl_dash_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1383 } 1384 1385 static void rtl8168_driver_start(struct rtl8169_private *tp) 1386 { 1387 if (tp->dash_type == RTL_DASH_DP) 1388 rtl8168dp_driver_start(tp); 1389 else 1390 rtl8168ep_driver_start(tp); 1391 } 1392 1393 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1394 { 1395 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1396 rtl_dash_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1397 } 1398 1399 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1400 { 1401 rtl8168ep_stop_cmac(tp); 1402 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1403 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1404 rtl_dash_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1405 } 1406 1407 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1408 { 1409 if (tp->dash_type == RTL_DASH_DP) 1410 rtl8168dp_driver_stop(tp); 1411 else 1412 rtl8168ep_driver_stop(tp); 1413 } 1414 1415 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1416 { 1417 u16 reg = rtl8168_get_ocp_reg(tp); 1418 1419 return r8168dp_ocp_read(tp, reg) & BIT(15); 1420 } 1421 1422 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1423 { 1424 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1425 } 1426 1427 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1428 { 1429 switch (tp->dash_type) { 1430 case RTL_DASH_DP: 1431 return r8168dp_check_dash(tp); 1432 case RTL_DASH_EP: 1433 return r8168ep_check_dash(tp); 1434 default: 1435 return false; 1436 } 1437 } 1438 1439 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1440 { 1441 switch (tp->mac_version) { 1442 case RTL_GIGA_MAC_VER_28: 1443 case RTL_GIGA_MAC_VER_31: 1444 return RTL_DASH_DP; 1445 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1446 return RTL_DASH_EP; 1447 default: 1448 return RTL_DASH_NONE; 1449 } 1450 } 1451 1452 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1453 { 1454 switch (tp->mac_version) { 1455 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1456 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1457 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1458 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1459 if (enable) 1460 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1461 else 1462 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1463 break; 1464 default: 1465 break; 1466 } 1467 } 1468 1469 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1470 { 1471 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1472 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1473 } 1474 1475 DECLARE_RTL_COND(rtl_efusear_cond) 1476 { 1477 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1478 } 1479 1480 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1481 { 1482 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1483 1484 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1485 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1486 } 1487 1488 static u32 rtl_get_events(struct rtl8169_private *tp) 1489 { 1490 if (rtl_is_8125(tp)) 1491 return RTL_R32(tp, IntrStatus_8125); 1492 else 1493 return RTL_R16(tp, IntrStatus); 1494 } 1495 1496 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1497 { 1498 if (rtl_is_8125(tp)) 1499 RTL_W32(tp, IntrStatus_8125, bits); 1500 else 1501 RTL_W16(tp, IntrStatus, bits); 1502 } 1503 1504 static void rtl_irq_disable(struct rtl8169_private *tp) 1505 { 1506 if (rtl_is_8125(tp)) 1507 RTL_W32(tp, IntrMask_8125, 0); 1508 else 1509 RTL_W16(tp, IntrMask, 0); 1510 } 1511 1512 static void rtl_irq_enable(struct rtl8169_private *tp) 1513 { 1514 if (rtl_is_8125(tp)) 1515 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1516 else 1517 RTL_W16(tp, IntrMask, tp->irq_mask); 1518 } 1519 1520 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1521 { 1522 rtl_irq_disable(tp); 1523 rtl_ack_events(tp, 0xffffffff); 1524 rtl_pci_commit(tp); 1525 } 1526 1527 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1528 { 1529 struct phy_device *phydev = tp->phydev; 1530 1531 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1532 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1533 if (phydev->speed == SPEED_1000) { 1534 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1535 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1536 } else if (phydev->speed == SPEED_100) { 1537 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1538 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1539 } else { 1540 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1541 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1542 } 1543 rtl_reset_packet_filter(tp); 1544 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1545 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1546 if (phydev->speed == SPEED_1000) { 1547 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1548 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1549 } else { 1550 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1551 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1552 } 1553 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1554 if (phydev->speed == SPEED_10) { 1555 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1556 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1557 } else { 1558 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1559 } 1560 } 1561 } 1562 1563 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1564 1565 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1566 { 1567 struct rtl8169_private *tp = netdev_priv(dev); 1568 1569 wol->supported = WAKE_ANY; 1570 wol->wolopts = tp->saved_wolopts; 1571 } 1572 1573 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1574 { 1575 static const struct { 1576 u32 opt; 1577 u16 reg; 1578 u8 mask; 1579 } cfg[] = { 1580 { WAKE_PHY, Config3, LinkUp }, 1581 { WAKE_UCAST, Config5, UWF }, 1582 { WAKE_BCAST, Config5, BWF }, 1583 { WAKE_MCAST, Config5, MWF }, 1584 { WAKE_ANY, Config5, LanWake }, 1585 { WAKE_MAGIC, Config3, MagicPacket } 1586 }; 1587 unsigned int i, tmp = ARRAY_SIZE(cfg); 1588 unsigned long flags; 1589 u8 options; 1590 1591 rtl_unlock_config_regs(tp); 1592 1593 if (rtl_is_8168evl_up(tp)) { 1594 tmp--; 1595 if (wolopts & WAKE_MAGIC) 1596 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1597 else 1598 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1599 } else if (rtl_is_8125(tp)) { 1600 tmp--; 1601 if (wolopts & WAKE_MAGIC) 1602 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1603 else 1604 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1605 } 1606 1607 raw_spin_lock_irqsave(&tp->config25_lock, flags); 1608 for (i = 0; i < tmp; i++) { 1609 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1610 if (wolopts & cfg[i].opt) 1611 options |= cfg[i].mask; 1612 RTL_W8(tp, cfg[i].reg, options); 1613 } 1614 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); 1615 1616 switch (tp->mac_version) { 1617 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1618 options = RTL_R8(tp, Config1) & ~PMEnable; 1619 if (wolopts) 1620 options |= PMEnable; 1621 RTL_W8(tp, Config1, options); 1622 break; 1623 case RTL_GIGA_MAC_VER_34: 1624 case RTL_GIGA_MAC_VER_37: 1625 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1626 if (wolopts) 1627 rtl_mod_config2(tp, 0, PME_SIGNAL); 1628 else 1629 rtl_mod_config2(tp, PME_SIGNAL, 0); 1630 break; 1631 default: 1632 break; 1633 } 1634 1635 rtl_lock_config_regs(tp); 1636 1637 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1638 1639 if (!tp->dash_enabled) { 1640 rtl_set_d3_pll_down(tp, !wolopts); 1641 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1642 } 1643 } 1644 1645 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1646 { 1647 struct rtl8169_private *tp = netdev_priv(dev); 1648 1649 if (wol->wolopts & ~WAKE_ANY) 1650 return -EINVAL; 1651 1652 tp->saved_wolopts = wol->wolopts; 1653 __rtl8169_set_wol(tp, tp->saved_wolopts); 1654 1655 return 0; 1656 } 1657 1658 static void rtl8169_get_drvinfo(struct net_device *dev, 1659 struct ethtool_drvinfo *info) 1660 { 1661 struct rtl8169_private *tp = netdev_priv(dev); 1662 struct rtl_fw *rtl_fw = tp->rtl_fw; 1663 1664 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1665 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1666 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1667 if (rtl_fw) 1668 strscpy(info->fw_version, rtl_fw->version, 1669 sizeof(info->fw_version)); 1670 } 1671 1672 static int rtl8169_get_regs_len(struct net_device *dev) 1673 { 1674 return R8169_REGS_SIZE; 1675 } 1676 1677 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1678 netdev_features_t features) 1679 { 1680 struct rtl8169_private *tp = netdev_priv(dev); 1681 1682 if (dev->mtu > TD_MSS_MAX) 1683 features &= ~NETIF_F_ALL_TSO; 1684 1685 if (dev->mtu > ETH_DATA_LEN && 1686 tp->mac_version > RTL_GIGA_MAC_VER_06) 1687 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1688 1689 return features; 1690 } 1691 1692 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1693 netdev_features_t features) 1694 { 1695 u32 rx_config = RTL_R32(tp, RxConfig); 1696 1697 if (features & NETIF_F_RXALL) 1698 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1699 else 1700 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1701 1702 if (rtl_is_8125(tp)) { 1703 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1704 rx_config |= RX_VLAN_8125; 1705 else 1706 rx_config &= ~RX_VLAN_8125; 1707 } 1708 1709 RTL_W32(tp, RxConfig, rx_config); 1710 } 1711 1712 static int rtl8169_set_features(struct net_device *dev, 1713 netdev_features_t features) 1714 { 1715 struct rtl8169_private *tp = netdev_priv(dev); 1716 1717 rtl_set_rx_config_features(tp, features); 1718 1719 if (features & NETIF_F_RXCSUM) 1720 tp->cp_cmd |= RxChkSum; 1721 else 1722 tp->cp_cmd &= ~RxChkSum; 1723 1724 if (!rtl_is_8125(tp)) { 1725 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1726 tp->cp_cmd |= RxVlan; 1727 else 1728 tp->cp_cmd &= ~RxVlan; 1729 } 1730 1731 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1732 rtl_pci_commit(tp); 1733 1734 return 0; 1735 } 1736 1737 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1738 { 1739 return (skb_vlan_tag_present(skb)) ? 1740 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1741 } 1742 1743 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1744 { 1745 u32 opts2 = le32_to_cpu(desc->opts2); 1746 1747 if (opts2 & RxVlanTag) 1748 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1749 } 1750 1751 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1752 void *p) 1753 { 1754 struct rtl8169_private *tp = netdev_priv(dev); 1755 u32 __iomem *data = tp->mmio_addr; 1756 u32 *dw = p; 1757 int i; 1758 1759 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1760 memcpy_fromio(dw++, data++, 4); 1761 } 1762 1763 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1764 "tx_packets", 1765 "rx_packets", 1766 "tx_errors", 1767 "rx_errors", 1768 "rx_missed", 1769 "align_errors", 1770 "tx_single_collisions", 1771 "tx_multi_collisions", 1772 "unicast", 1773 "broadcast", 1774 "multicast", 1775 "tx_aborted", 1776 "tx_underrun", 1777 }; 1778 1779 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1780 { 1781 switch (sset) { 1782 case ETH_SS_STATS: 1783 return ARRAY_SIZE(rtl8169_gstrings); 1784 default: 1785 return -EOPNOTSUPP; 1786 } 1787 } 1788 1789 DECLARE_RTL_COND(rtl_counters_cond) 1790 { 1791 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1792 } 1793 1794 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1795 { 1796 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1797 1798 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1799 rtl_pci_commit(tp); 1800 RTL_W32(tp, CounterAddrLow, cmd); 1801 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1802 1803 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1804 } 1805 1806 static void rtl8169_update_counters(struct rtl8169_private *tp) 1807 { 1808 u8 val = RTL_R8(tp, ChipCmd); 1809 1810 /* 1811 * Some chips are unable to dump tally counters when the receiver 1812 * is disabled. If 0xff chip may be in a PCI power-save state. 1813 */ 1814 if (val & CmdRxEnb && val != 0xff) 1815 rtl8169_do_counters(tp, CounterDump); 1816 } 1817 1818 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1819 { 1820 struct rtl8169_counters *counters = tp->counters; 1821 1822 /* 1823 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1824 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1825 * reset by a power cycle, while the counter values collected by the 1826 * driver are reset at every driver unload/load cycle. 1827 * 1828 * To make sure the HW values returned by @get_stats64 match the SW 1829 * values, we collect the initial values at first open(*) and use them 1830 * as offsets to normalize the values returned by @get_stats64. 1831 * 1832 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1833 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1834 * set at open time by rtl_hw_start. 1835 */ 1836 1837 if (tp->tc_offset.inited) 1838 return; 1839 1840 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1841 rtl8169_do_counters(tp, CounterReset); 1842 } else { 1843 rtl8169_update_counters(tp); 1844 tp->tc_offset.tx_errors = counters->tx_errors; 1845 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1846 tp->tc_offset.tx_aborted = counters->tx_aborted; 1847 tp->tc_offset.rx_missed = counters->rx_missed; 1848 } 1849 1850 tp->tc_offset.inited = true; 1851 } 1852 1853 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1854 struct ethtool_stats *stats, u64 *data) 1855 { 1856 struct rtl8169_private *tp = netdev_priv(dev); 1857 struct rtl8169_counters *counters; 1858 1859 counters = tp->counters; 1860 rtl8169_update_counters(tp); 1861 1862 data[0] = le64_to_cpu(counters->tx_packets); 1863 data[1] = le64_to_cpu(counters->rx_packets); 1864 data[2] = le64_to_cpu(counters->tx_errors); 1865 data[3] = le32_to_cpu(counters->rx_errors); 1866 data[4] = le16_to_cpu(counters->rx_missed); 1867 data[5] = le16_to_cpu(counters->align_errors); 1868 data[6] = le32_to_cpu(counters->tx_one_collision); 1869 data[7] = le32_to_cpu(counters->tx_multi_collision); 1870 data[8] = le64_to_cpu(counters->rx_unicast); 1871 data[9] = le64_to_cpu(counters->rx_broadcast); 1872 data[10] = le32_to_cpu(counters->rx_multicast); 1873 data[11] = le16_to_cpu(counters->tx_aborted); 1874 data[12] = le16_to_cpu(counters->tx_underrun); 1875 } 1876 1877 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1878 { 1879 switch(stringset) { 1880 case ETH_SS_STATS: 1881 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1882 break; 1883 } 1884 } 1885 1886 /* 1887 * Interrupt coalescing 1888 * 1889 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1890 * > 8169, 8168 and 810x line of chipsets 1891 * 1892 * 8169, 8168, and 8136(810x) serial chipsets support it. 1893 * 1894 * > 2 - the Tx timer unit at gigabit speed 1895 * 1896 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1897 * (0xe0) bit 1 and bit 0. 1898 * 1899 * For 8169 1900 * bit[1:0] \ speed 1000M 100M 10M 1901 * 0 0 320ns 2.56us 40.96us 1902 * 0 1 2.56us 20.48us 327.7us 1903 * 1 0 5.12us 40.96us 655.4us 1904 * 1 1 10.24us 81.92us 1.31ms 1905 * 1906 * For the other 1907 * bit[1:0] \ speed 1000M 100M 10M 1908 * 0 0 5us 2.56us 40.96us 1909 * 0 1 40us 20.48us 327.7us 1910 * 1 0 80us 40.96us 655.4us 1911 * 1 1 160us 81.92us 1.31ms 1912 */ 1913 1914 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1915 struct rtl_coalesce_info { 1916 u32 speed; 1917 u32 scale_nsecs[4]; 1918 }; 1919 1920 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1921 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1922 1923 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1924 { SPEED_1000, COALESCE_DELAY(320) }, 1925 { SPEED_100, COALESCE_DELAY(2560) }, 1926 { SPEED_10, COALESCE_DELAY(40960) }, 1927 { 0 }, 1928 }; 1929 1930 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1931 { SPEED_1000, COALESCE_DELAY(5000) }, 1932 { SPEED_100, COALESCE_DELAY(2560) }, 1933 { SPEED_10, COALESCE_DELAY(40960) }, 1934 { 0 }, 1935 }; 1936 #undef COALESCE_DELAY 1937 1938 /* get rx/tx scale vector corresponding to current speed */ 1939 static const struct rtl_coalesce_info * 1940 rtl_coalesce_info(struct rtl8169_private *tp) 1941 { 1942 const struct rtl_coalesce_info *ci; 1943 1944 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1945 ci = rtl_coalesce_info_8169; 1946 else 1947 ci = rtl_coalesce_info_8168_8136; 1948 1949 /* if speed is unknown assume highest one */ 1950 if (tp->phydev->speed == SPEED_UNKNOWN) 1951 return ci; 1952 1953 for (; ci->speed; ci++) { 1954 if (tp->phydev->speed == ci->speed) 1955 return ci; 1956 } 1957 1958 return ERR_PTR(-ELNRNG); 1959 } 1960 1961 static int rtl_get_coalesce(struct net_device *dev, 1962 struct ethtool_coalesce *ec, 1963 struct kernel_ethtool_coalesce *kernel_coal, 1964 struct netlink_ext_ack *extack) 1965 { 1966 struct rtl8169_private *tp = netdev_priv(dev); 1967 const struct rtl_coalesce_info *ci; 1968 u32 scale, c_us, c_fr; 1969 u16 intrmit; 1970 1971 if (rtl_is_8125(tp)) 1972 return -EOPNOTSUPP; 1973 1974 memset(ec, 0, sizeof(*ec)); 1975 1976 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1977 ci = rtl_coalesce_info(tp); 1978 if (IS_ERR(ci)) 1979 return PTR_ERR(ci); 1980 1981 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1982 1983 intrmit = RTL_R16(tp, IntrMitigate); 1984 1985 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1986 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1987 1988 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1989 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1990 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1991 1992 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1993 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1994 1995 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1996 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1997 1998 return 0; 1999 } 2000 2001 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 2002 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 2003 u16 *cp01) 2004 { 2005 const struct rtl_coalesce_info *ci; 2006 u16 i; 2007 2008 ci = rtl_coalesce_info(tp); 2009 if (IS_ERR(ci)) 2010 return PTR_ERR(ci); 2011 2012 for (i = 0; i < 4; i++) { 2013 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 2014 *cp01 = i; 2015 return ci->scale_nsecs[i]; 2016 } 2017 } 2018 2019 return -ERANGE; 2020 } 2021 2022 static int rtl_set_coalesce(struct net_device *dev, 2023 struct ethtool_coalesce *ec, 2024 struct kernel_ethtool_coalesce *kernel_coal, 2025 struct netlink_ext_ack *extack) 2026 { 2027 struct rtl8169_private *tp = netdev_priv(dev); 2028 u32 tx_fr = ec->tx_max_coalesced_frames; 2029 u32 rx_fr = ec->rx_max_coalesced_frames; 2030 u32 coal_usec_max, units; 2031 u16 w = 0, cp01 = 0; 2032 int scale; 2033 2034 if (rtl_is_8125(tp)) 2035 return -EOPNOTSUPP; 2036 2037 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 2038 return -ERANGE; 2039 2040 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 2041 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 2042 if (scale < 0) 2043 return scale; 2044 2045 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 2046 * not only when usecs=0 because of e.g. the following scenario: 2047 * 2048 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 2049 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 2050 * - then user does `ethtool -C eth0 rx-usecs 100` 2051 * 2052 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2053 * if we want to ignore rx_frames then it has to be set to 0. 2054 */ 2055 if (rx_fr == 1) 2056 rx_fr = 0; 2057 if (tx_fr == 1) 2058 tx_fr = 0; 2059 2060 /* HW requires time limit to be set if frame limit is set */ 2061 if ((tx_fr && !ec->tx_coalesce_usecs) || 2062 (rx_fr && !ec->rx_coalesce_usecs)) 2063 return -EINVAL; 2064 2065 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2066 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2067 2068 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2069 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2070 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2071 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2072 2073 RTL_W16(tp, IntrMitigate, w); 2074 2075 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2076 if (rtl_is_8168evl_up(tp)) { 2077 if (!rx_fr && !tx_fr) 2078 /* disable packet counter */ 2079 tp->cp_cmd |= PktCntrDisable; 2080 else 2081 tp->cp_cmd &= ~PktCntrDisable; 2082 } 2083 2084 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2085 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2086 rtl_pci_commit(tp); 2087 2088 return 0; 2089 } 2090 2091 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2092 { 2093 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2094 2095 switch (tp->mac_version) { 2096 case RTL_GIGA_MAC_VER_46: 2097 case RTL_GIGA_MAC_VER_48: 2098 tp->tx_lpi_timer = timer_val; 2099 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2100 break; 2101 case RTL_GIGA_MAC_VER_61: 2102 case RTL_GIGA_MAC_VER_63: 2103 case RTL_GIGA_MAC_VER_65: 2104 case RTL_GIGA_MAC_VER_66: 2105 tp->tx_lpi_timer = timer_val; 2106 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2107 break; 2108 default: 2109 break; 2110 } 2111 } 2112 2113 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2114 { 2115 unsigned int speed = tp->phydev->speed; 2116 unsigned int timer = tp->tx_lpi_timer; 2117 2118 if (!timer || speed == SPEED_UNKNOWN) 2119 return 0; 2120 2121 /* tx_lpi_timer value is in bytes */ 2122 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2123 } 2124 2125 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2126 { 2127 struct rtl8169_private *tp = netdev_priv(dev); 2128 int ret; 2129 2130 if (!rtl_supports_eee(tp)) 2131 return -EOPNOTSUPP; 2132 2133 ret = phy_ethtool_get_eee(tp->phydev, data); 2134 if (ret) 2135 return ret; 2136 2137 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2138 2139 return 0; 2140 } 2141 2142 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2143 { 2144 struct rtl8169_private *tp = netdev_priv(dev); 2145 2146 if (!rtl_supports_eee(tp)) 2147 return -EOPNOTSUPP; 2148 2149 return phy_ethtool_set_eee(tp->phydev, data); 2150 } 2151 2152 static void rtl8169_get_ringparam(struct net_device *dev, 2153 struct ethtool_ringparam *data, 2154 struct kernel_ethtool_ringparam *kernel_data, 2155 struct netlink_ext_ack *extack) 2156 { 2157 data->rx_max_pending = NUM_RX_DESC; 2158 data->rx_pending = NUM_RX_DESC; 2159 data->tx_max_pending = NUM_TX_DESC; 2160 data->tx_pending = NUM_TX_DESC; 2161 } 2162 2163 static void rtl8169_get_pauseparam(struct net_device *dev, 2164 struct ethtool_pauseparam *data) 2165 { 2166 struct rtl8169_private *tp = netdev_priv(dev); 2167 bool tx_pause, rx_pause; 2168 2169 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2170 2171 data->autoneg = tp->phydev->autoneg; 2172 data->tx_pause = tx_pause ? 1 : 0; 2173 data->rx_pause = rx_pause ? 1 : 0; 2174 } 2175 2176 static int rtl8169_set_pauseparam(struct net_device *dev, 2177 struct ethtool_pauseparam *data) 2178 { 2179 struct rtl8169_private *tp = netdev_priv(dev); 2180 2181 if (dev->mtu > ETH_DATA_LEN) 2182 return -EOPNOTSUPP; 2183 2184 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2185 2186 return 0; 2187 } 2188 2189 static const struct ethtool_ops rtl8169_ethtool_ops = { 2190 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2191 ETHTOOL_COALESCE_MAX_FRAMES, 2192 .get_drvinfo = rtl8169_get_drvinfo, 2193 .get_regs_len = rtl8169_get_regs_len, 2194 .get_link = ethtool_op_get_link, 2195 .get_coalesce = rtl_get_coalesce, 2196 .set_coalesce = rtl_set_coalesce, 2197 .get_regs = rtl8169_get_regs, 2198 .get_wol = rtl8169_get_wol, 2199 .set_wol = rtl8169_set_wol, 2200 .get_strings = rtl8169_get_strings, 2201 .get_sset_count = rtl8169_get_sset_count, 2202 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2203 .get_ts_info = ethtool_op_get_ts_info, 2204 .nway_reset = phy_ethtool_nway_reset, 2205 .get_eee = rtl8169_get_eee, 2206 .set_eee = rtl8169_set_eee, 2207 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2208 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2209 .get_ringparam = rtl8169_get_ringparam, 2210 .get_pauseparam = rtl8169_get_pauseparam, 2211 .set_pauseparam = rtl8169_set_pauseparam, 2212 }; 2213 2214 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2215 { 2216 /* 2217 * The driver currently handles the 8168Bf and the 8168Be identically 2218 * but they can be identified more specifically through the test below 2219 * if needed: 2220 * 2221 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2222 * 2223 * Same thing for the 8101Eb and the 8101Ec: 2224 * 2225 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2226 */ 2227 static const struct rtl_mac_info { 2228 u16 mask; 2229 u16 val; 2230 enum mac_version ver; 2231 } mac_info[] = { 2232 /* 8126A family. */ 2233 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 }, 2234 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2235 2236 /* 8125B family. */ 2237 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2238 2239 /* 8125A family. */ 2240 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2241 /* It seems only XID 609 made it to the mass market. 2242 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2243 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2244 */ 2245 2246 /* RTL8117 */ 2247 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2248 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2249 2250 /* 8168EP family. */ 2251 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2252 /* It seems this chip version never made it to 2253 * the wild. Let's disable detection. 2254 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2255 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2256 */ 2257 2258 /* 8168H family. */ 2259 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2260 /* It seems this chip version never made it to 2261 * the wild. Let's disable detection. 2262 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2263 */ 2264 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 2265 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, 2266 2267 /* 8168G family. */ 2268 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2269 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2270 /* It seems this chip version never made it to 2271 * the wild. Let's disable detection. 2272 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2273 */ 2274 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2275 2276 /* 8168F family. */ 2277 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2278 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2279 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2280 2281 /* 8168E family. */ 2282 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2283 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2284 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2285 2286 /* 8168D family. */ 2287 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2288 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2289 2290 /* 8168DP family. */ 2291 /* It seems this early RTL8168dp version never made it to 2292 * the wild. Support has been removed. 2293 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2294 */ 2295 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2296 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2297 2298 /* 8168C family. */ 2299 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2300 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2301 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2302 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2303 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2304 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2305 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2306 2307 /* 8168B family. */ 2308 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2309 /* This one is very old and rare, let's see if anybody complains. 2310 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2311 */ 2312 2313 /* 8101 family. */ 2314 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2315 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2316 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2317 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2318 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2319 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2320 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2321 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2322 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2323 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2324 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2325 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2326 2327 /* 8110 family. */ 2328 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2329 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2330 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2331 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2332 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2333 2334 /* Catch-all */ 2335 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2336 }; 2337 const struct rtl_mac_info *p = mac_info; 2338 enum mac_version ver; 2339 2340 while ((xid & p->mask) != p->val) 2341 p++; 2342 ver = p->ver; 2343 2344 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2345 if (ver == RTL_GIGA_MAC_VER_42) 2346 ver = RTL_GIGA_MAC_VER_43; 2347 else if (ver == RTL_GIGA_MAC_VER_46) 2348 ver = RTL_GIGA_MAC_VER_48; 2349 } 2350 2351 return ver; 2352 } 2353 2354 static void rtl_release_firmware(struct rtl8169_private *tp) 2355 { 2356 if (tp->rtl_fw) { 2357 rtl_fw_release_firmware(tp->rtl_fw); 2358 kfree(tp->rtl_fw); 2359 tp->rtl_fw = NULL; 2360 } 2361 } 2362 2363 void r8169_apply_firmware(struct rtl8169_private *tp) 2364 { 2365 int val; 2366 2367 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2368 if (tp->rtl_fw) { 2369 rtl_fw_write_firmware(tp, tp->rtl_fw); 2370 /* At least one firmware doesn't reset tp->ocp_base. */ 2371 tp->ocp_base = OCP_STD_PHY_BASE; 2372 2373 /* PHY soft reset may still be in progress */ 2374 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2375 !(val & BMCR_RESET), 2376 50000, 600000, true); 2377 } 2378 } 2379 2380 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2381 { 2382 /* Adjust EEE LED frequency */ 2383 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2384 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2385 2386 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2387 } 2388 2389 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2390 { 2391 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2392 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2393 } 2394 2395 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2396 { 2397 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2398 } 2399 2400 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2401 { 2402 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2403 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2404 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2405 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2406 } 2407 2408 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2409 { 2410 u16 data1, data2, ioffset; 2411 2412 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2413 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2414 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2415 2416 ioffset = (data2 >> 1) & 0x7ff8; 2417 ioffset |= data2 & 0x0007; 2418 if (data1 & BIT(7)) 2419 ioffset |= BIT(15); 2420 2421 return ioffset; 2422 } 2423 2424 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2425 { 2426 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 2427 return; 2428 2429 set_bit(flag, tp->wk.flags); 2430 schedule_work(&tp->wk.work); 2431 } 2432 2433 static void rtl8169_init_phy(struct rtl8169_private *tp) 2434 { 2435 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2436 2437 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2438 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2439 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2440 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2441 RTL_W8(tp, 0x82, 0x01); 2442 } 2443 2444 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2445 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2446 tp->pci_dev->subsystem_device == 0xe000) 2447 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2448 2449 /* We may have called phy_speed_down before */ 2450 phy_speed_up(tp->phydev); 2451 2452 genphy_soft_reset(tp->phydev); 2453 } 2454 2455 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2456 { 2457 rtl_unlock_config_regs(tp); 2458 2459 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2460 rtl_pci_commit(tp); 2461 2462 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2463 rtl_pci_commit(tp); 2464 2465 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2466 rtl_rar_exgmac_set(tp, addr); 2467 2468 rtl_lock_config_regs(tp); 2469 } 2470 2471 static int rtl_set_mac_address(struct net_device *dev, void *p) 2472 { 2473 struct rtl8169_private *tp = netdev_priv(dev); 2474 int ret; 2475 2476 ret = eth_mac_addr(dev, p); 2477 if (ret) 2478 return ret; 2479 2480 rtl_rar_set(tp, dev->dev_addr); 2481 2482 return 0; 2483 } 2484 2485 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2486 { 2487 switch (tp->mac_version) { 2488 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2489 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2490 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2491 break; 2492 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2493 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2494 case RTL_GIGA_MAC_VER_38: 2495 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2496 break; 2497 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2498 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2499 break; 2500 case RTL_GIGA_MAC_VER_61: 2501 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2502 break; 2503 case RTL_GIGA_MAC_VER_63: 2504 case RTL_GIGA_MAC_VER_65: 2505 case RTL_GIGA_MAC_VER_66: 2506 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2507 RX_PAUSE_SLOT_ON); 2508 break; 2509 default: 2510 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2511 break; 2512 } 2513 } 2514 2515 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2516 { 2517 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2518 } 2519 2520 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2521 { 2522 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2523 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2524 } 2525 2526 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2527 { 2528 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2529 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2530 } 2531 2532 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2533 { 2534 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2535 } 2536 2537 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2538 { 2539 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2540 } 2541 2542 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2543 { 2544 RTL_W8(tp, MaxTxPacketSize, 0x24); 2545 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2546 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2547 } 2548 2549 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2550 { 2551 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2552 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2553 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2554 } 2555 2556 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2557 { 2558 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2559 } 2560 2561 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2562 { 2563 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2564 } 2565 2566 static void rtl_jumbo_config(struct rtl8169_private *tp) 2567 { 2568 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2569 int readrq = 4096; 2570 2571 rtl_unlock_config_regs(tp); 2572 switch (tp->mac_version) { 2573 case RTL_GIGA_MAC_VER_17: 2574 if (jumbo) { 2575 readrq = 512; 2576 r8168b_1_hw_jumbo_enable(tp); 2577 } else { 2578 r8168b_1_hw_jumbo_disable(tp); 2579 } 2580 break; 2581 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2582 if (jumbo) { 2583 readrq = 512; 2584 r8168c_hw_jumbo_enable(tp); 2585 } else { 2586 r8168c_hw_jumbo_disable(tp); 2587 } 2588 break; 2589 case RTL_GIGA_MAC_VER_28: 2590 if (jumbo) 2591 r8168dp_hw_jumbo_enable(tp); 2592 else 2593 r8168dp_hw_jumbo_disable(tp); 2594 break; 2595 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2596 if (jumbo) 2597 r8168e_hw_jumbo_enable(tp); 2598 else 2599 r8168e_hw_jumbo_disable(tp); 2600 break; 2601 default: 2602 break; 2603 } 2604 rtl_lock_config_regs(tp); 2605 2606 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2607 pcie_set_readrq(tp->pci_dev, readrq); 2608 2609 /* Chip doesn't support pause in jumbo mode */ 2610 if (jumbo) { 2611 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2612 tp->phydev->advertising); 2613 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2614 tp->phydev->advertising); 2615 phy_start_aneg(tp->phydev); 2616 } 2617 } 2618 2619 DECLARE_RTL_COND(rtl_chipcmd_cond) 2620 { 2621 return RTL_R8(tp, ChipCmd) & CmdReset; 2622 } 2623 2624 static void rtl_hw_reset(struct rtl8169_private *tp) 2625 { 2626 RTL_W8(tp, ChipCmd, CmdReset); 2627 2628 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2629 } 2630 2631 static void rtl_request_firmware(struct rtl8169_private *tp) 2632 { 2633 struct rtl_fw *rtl_fw; 2634 2635 /* firmware loaded already or no firmware available */ 2636 if (tp->rtl_fw || !tp->fw_name) 2637 return; 2638 2639 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2640 if (!rtl_fw) 2641 return; 2642 2643 rtl_fw->phy_write = rtl_writephy; 2644 rtl_fw->phy_read = rtl_readphy; 2645 rtl_fw->mac_mcu_write = mac_mcu_write; 2646 rtl_fw->mac_mcu_read = mac_mcu_read; 2647 rtl_fw->fw_name = tp->fw_name; 2648 rtl_fw->dev = tp_to_dev(tp); 2649 2650 if (rtl_fw_request_firmware(rtl_fw)) 2651 kfree(rtl_fw); 2652 else 2653 tp->rtl_fw = rtl_fw; 2654 } 2655 2656 static void rtl_rx_close(struct rtl8169_private *tp) 2657 { 2658 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2659 } 2660 2661 DECLARE_RTL_COND(rtl_npq_cond) 2662 { 2663 return RTL_R8(tp, TxPoll) & NPQ; 2664 } 2665 2666 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2667 { 2668 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2669 } 2670 2671 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2672 { 2673 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2674 } 2675 2676 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2677 { 2678 /* IntrMitigate has new functionality on RTL8125 */ 2679 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2680 } 2681 2682 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2683 { 2684 switch (tp->mac_version) { 2685 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2686 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2687 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2688 break; 2689 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2690 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2691 break; 2692 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2693 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2694 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2695 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2696 break; 2697 default: 2698 break; 2699 } 2700 } 2701 2702 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2703 { 2704 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2705 } 2706 2707 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2708 { 2709 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2710 fsleep(2000); 2711 rtl_wait_txrx_fifo_empty(tp); 2712 } 2713 2714 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2715 { 2716 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2717 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2718 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2719 2720 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2721 rtl_disable_rxdvgate(tp); 2722 } 2723 2724 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2725 { 2726 if (tp->dash_enabled) 2727 return; 2728 2729 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2730 tp->mac_version == RTL_GIGA_MAC_VER_33) 2731 rtl_ephy_write(tp, 0x19, 0xff64); 2732 2733 if (device_may_wakeup(tp_to_dev(tp))) { 2734 phy_speed_down(tp->phydev, false); 2735 rtl_wol_enable_rx(tp); 2736 } 2737 } 2738 2739 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2740 { 2741 u32 val = TX_DMA_BURST << TxDMAShift | 2742 InterFrameGap << TxInterFrameGapShift; 2743 2744 if (rtl_is_8168evl_up(tp)) 2745 val |= TXCFG_AUTO_FIFO; 2746 2747 RTL_W32(tp, TxConfig, val); 2748 } 2749 2750 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2751 { 2752 /* Low hurts. Let's disable the filtering. */ 2753 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2754 } 2755 2756 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2757 { 2758 /* 2759 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2760 * register to be written before TxDescAddrLow to work. 2761 * Switching from MMIO to I/O access fixes the issue as well. 2762 */ 2763 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2764 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2765 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2766 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2767 } 2768 2769 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2770 { 2771 u32 val; 2772 2773 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2774 val = 0x000fff00; 2775 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2776 val = 0x00ffff00; 2777 else 2778 return; 2779 2780 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2781 val |= 0xff; 2782 2783 RTL_W32(tp, 0x7c, val); 2784 } 2785 2786 static void rtl_set_rx_mode(struct net_device *dev) 2787 { 2788 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2789 /* Multicast hash filter */ 2790 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2791 struct rtl8169_private *tp = netdev_priv(dev); 2792 u32 tmp; 2793 2794 if (dev->flags & IFF_PROMISC) { 2795 rx_mode |= AcceptAllPhys; 2796 } else if (!(dev->flags & IFF_MULTICAST)) { 2797 rx_mode &= ~AcceptMulticast; 2798 } else if (dev->flags & IFF_ALLMULTI || 2799 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2800 /* accept all multicasts */ 2801 } else if (netdev_mc_empty(dev)) { 2802 rx_mode &= ~AcceptMulticast; 2803 } else { 2804 struct netdev_hw_addr *ha; 2805 2806 mc_filter[1] = mc_filter[0] = 0; 2807 netdev_for_each_mc_addr(ha, dev) { 2808 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2809 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2810 } 2811 2812 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2813 tmp = mc_filter[0]; 2814 mc_filter[0] = swab32(mc_filter[1]); 2815 mc_filter[1] = swab32(tmp); 2816 } 2817 } 2818 2819 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2820 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2821 2822 tmp = RTL_R32(tp, RxConfig); 2823 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2824 } 2825 2826 DECLARE_RTL_COND(rtl_csiar_cond) 2827 { 2828 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2829 } 2830 2831 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2832 { 2833 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2834 2835 RTL_W32(tp, CSIDR, value); 2836 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2837 CSIAR_BYTE_ENABLE | func << 16); 2838 2839 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2840 } 2841 2842 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2843 { 2844 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2845 2846 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2847 CSIAR_BYTE_ENABLE); 2848 2849 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2850 RTL_R32(tp, CSIDR) : ~0; 2851 } 2852 2853 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2854 { 2855 struct pci_dev *pdev = tp->pci_dev; 2856 u32 csi; 2857 2858 /* According to Realtek the value at config space address 0x070f 2859 * controls the L0s/L1 entrance latency. We try standard ECAM access 2860 * first and if it fails fall back to CSI. 2861 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2862 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2863 */ 2864 if (pdev->cfg_size > 0x070f && 2865 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2866 return; 2867 2868 netdev_notice_once(tp->dev, 2869 "No native access to PCI extended config space, falling back to CSI\n"); 2870 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2871 rtl_csi_write(tp, 0x070c, csi | val << 24); 2872 } 2873 2874 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2875 { 2876 /* L0 7us, L1 16us */ 2877 rtl_set_aspm_entry_latency(tp, 0x27); 2878 } 2879 2880 struct ephy_info { 2881 unsigned int offset; 2882 u16 mask; 2883 u16 bits; 2884 }; 2885 2886 static void __rtl_ephy_init(struct rtl8169_private *tp, 2887 const struct ephy_info *e, int len) 2888 { 2889 u16 w; 2890 2891 while (len-- > 0) { 2892 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2893 rtl_ephy_write(tp, e->offset, w); 2894 e++; 2895 } 2896 } 2897 2898 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2899 2900 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2901 { 2902 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2903 PCI_EXP_LNKCTL_CLKREQ_EN); 2904 } 2905 2906 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2907 { 2908 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2909 PCI_EXP_LNKCTL_CLKREQ_EN); 2910 } 2911 2912 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2913 { 2914 /* work around an issue when PCI reset occurs during L2/L3 state */ 2915 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2916 } 2917 2918 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2919 { 2920 /* Bits control which events trigger ASPM L1 exit: 2921 * Bit 12: rxdv 2922 * Bit 11: ltr_msg 2923 * Bit 10: txdma_poll 2924 * Bit 9: xadm 2925 * Bit 8: pktavi 2926 * Bit 7: txpla 2927 */ 2928 switch (tp->mac_version) { 2929 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2930 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2931 break; 2932 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2933 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2934 break; 2935 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2936 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2937 break; 2938 default: 2939 break; 2940 } 2941 } 2942 2943 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2944 { 2945 switch (tp->mac_version) { 2946 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2947 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2948 break; 2949 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2950 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2951 break; 2952 default: 2953 break; 2954 } 2955 } 2956 2957 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2958 { 2959 u8 val8; 2960 2961 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2962 return; 2963 2964 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2965 if (enable && tp->aspm_manageable) { 2966 /* On these chip versions ASPM can even harm 2967 * bus communication of other PCI devices. 2968 */ 2969 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2970 tp->mac_version == RTL_GIGA_MAC_VER_43) 2971 return; 2972 2973 rtl_mod_config5(tp, 0, ASPM_en); 2974 switch (tp->mac_version) { 2975 case RTL_GIGA_MAC_VER_65: 2976 case RTL_GIGA_MAC_VER_66: 2977 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2978 RTL_W8(tp, INT_CFG0_8125, val8); 2979 break; 2980 default: 2981 rtl_mod_config2(tp, 0, ClkReqEn); 2982 break; 2983 } 2984 2985 switch (tp->mac_version) { 2986 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2987 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2988 /* reset ephy tx/rx disable timer */ 2989 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2990 /* chip can trigger L1.2 */ 2991 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2992 break; 2993 default: 2994 break; 2995 } 2996 } else { 2997 switch (tp->mac_version) { 2998 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2999 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 3000 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 3001 break; 3002 default: 3003 break; 3004 } 3005 3006 switch (tp->mac_version) { 3007 case RTL_GIGA_MAC_VER_65: 3008 case RTL_GIGA_MAC_VER_66: 3009 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 3010 RTL_W8(tp, INT_CFG0_8125, val8); 3011 break; 3012 default: 3013 rtl_mod_config2(tp, ClkReqEn, 0); 3014 break; 3015 } 3016 rtl_mod_config5(tp, ASPM_en, 0); 3017 } 3018 } 3019 3020 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 3021 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 3022 { 3023 /* Usage of dynamic vs. static FIFO is controlled by bit 3024 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 3025 */ 3026 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 3027 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 3028 } 3029 3030 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3031 u8 low, u8 high) 3032 { 3033 /* FIFO thresholds for pause flow control */ 3034 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3035 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3036 } 3037 3038 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3039 { 3040 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3041 } 3042 3043 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3044 { 3045 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3046 3047 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3048 3049 rtl_disable_clock_request(tp); 3050 } 3051 3052 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3053 { 3054 static const struct ephy_info e_info_8168cp[] = { 3055 { 0x01, 0, 0x0001 }, 3056 { 0x02, 0x0800, 0x1000 }, 3057 { 0x03, 0, 0x0042 }, 3058 { 0x06, 0x0080, 0x0000 }, 3059 { 0x07, 0, 0x2000 } 3060 }; 3061 3062 rtl_set_def_aspm_entry_latency(tp); 3063 3064 rtl_ephy_init(tp, e_info_8168cp); 3065 3066 __rtl_hw_start_8168cp(tp); 3067 } 3068 3069 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3070 { 3071 rtl_set_def_aspm_entry_latency(tp); 3072 3073 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3074 } 3075 3076 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3077 { 3078 rtl_set_def_aspm_entry_latency(tp); 3079 3080 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3081 3082 /* Magic. */ 3083 RTL_W8(tp, DBG_REG, 0x20); 3084 } 3085 3086 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3087 { 3088 static const struct ephy_info e_info_8168c_1[] = { 3089 { 0x02, 0x0800, 0x1000 }, 3090 { 0x03, 0, 0x0002 }, 3091 { 0x06, 0x0080, 0x0000 } 3092 }; 3093 3094 rtl_set_def_aspm_entry_latency(tp); 3095 3096 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3097 3098 rtl_ephy_init(tp, e_info_8168c_1); 3099 3100 __rtl_hw_start_8168cp(tp); 3101 } 3102 3103 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3104 { 3105 static const struct ephy_info e_info_8168c_2[] = { 3106 { 0x01, 0, 0x0001 }, 3107 { 0x03, 0x0400, 0x0020 } 3108 }; 3109 3110 rtl_set_def_aspm_entry_latency(tp); 3111 3112 rtl_ephy_init(tp, e_info_8168c_2); 3113 3114 __rtl_hw_start_8168cp(tp); 3115 } 3116 3117 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3118 { 3119 rtl_set_def_aspm_entry_latency(tp); 3120 3121 __rtl_hw_start_8168cp(tp); 3122 } 3123 3124 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3125 { 3126 rtl_set_def_aspm_entry_latency(tp); 3127 3128 rtl_disable_clock_request(tp); 3129 } 3130 3131 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3132 { 3133 static const struct ephy_info e_info_8168d_4[] = { 3134 { 0x0b, 0x0000, 0x0048 }, 3135 { 0x19, 0x0020, 0x0050 }, 3136 { 0x0c, 0x0100, 0x0020 }, 3137 { 0x10, 0x0004, 0x0000 }, 3138 }; 3139 3140 rtl_set_def_aspm_entry_latency(tp); 3141 3142 rtl_ephy_init(tp, e_info_8168d_4); 3143 3144 rtl_enable_clock_request(tp); 3145 } 3146 3147 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3148 { 3149 static const struct ephy_info e_info_8168e_1[] = { 3150 { 0x00, 0x0200, 0x0100 }, 3151 { 0x00, 0x0000, 0x0004 }, 3152 { 0x06, 0x0002, 0x0001 }, 3153 { 0x06, 0x0000, 0x0030 }, 3154 { 0x07, 0x0000, 0x2000 }, 3155 { 0x00, 0x0000, 0x0020 }, 3156 { 0x03, 0x5800, 0x2000 }, 3157 { 0x03, 0x0000, 0x0001 }, 3158 { 0x01, 0x0800, 0x1000 }, 3159 { 0x07, 0x0000, 0x4000 }, 3160 { 0x1e, 0x0000, 0x2000 }, 3161 { 0x19, 0xffff, 0xfe6c }, 3162 { 0x0a, 0x0000, 0x0040 } 3163 }; 3164 3165 rtl_set_def_aspm_entry_latency(tp); 3166 3167 rtl_ephy_init(tp, e_info_8168e_1); 3168 3169 rtl_disable_clock_request(tp); 3170 3171 /* Reset tx FIFO pointer */ 3172 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3173 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3174 3175 rtl_mod_config5(tp, Spi_en, 0); 3176 } 3177 3178 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3179 { 3180 static const struct ephy_info e_info_8168e_2[] = { 3181 { 0x09, 0x0000, 0x0080 }, 3182 { 0x19, 0x0000, 0x0224 }, 3183 { 0x00, 0x0000, 0x0004 }, 3184 { 0x0c, 0x3df0, 0x0200 }, 3185 }; 3186 3187 rtl_set_def_aspm_entry_latency(tp); 3188 3189 rtl_ephy_init(tp, e_info_8168e_2); 3190 3191 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3192 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3193 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3194 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3195 rtl_reset_packet_filter(tp); 3196 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3197 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3198 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3199 3200 rtl_disable_clock_request(tp); 3201 3202 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3203 3204 rtl8168_config_eee_mac(tp); 3205 3206 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3207 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3208 rtl_mod_config5(tp, Spi_en, 0); 3209 } 3210 3211 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3212 { 3213 rtl_set_def_aspm_entry_latency(tp); 3214 3215 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3216 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3217 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3218 rtl_reset_packet_filter(tp); 3219 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3220 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3221 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3222 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3223 3224 rtl_disable_clock_request(tp); 3225 3226 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3227 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3228 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3229 rtl_mod_config5(tp, Spi_en, 0); 3230 3231 rtl8168_config_eee_mac(tp); 3232 } 3233 3234 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3235 { 3236 static const struct ephy_info e_info_8168f_1[] = { 3237 { 0x06, 0x00c0, 0x0020 }, 3238 { 0x08, 0x0001, 0x0002 }, 3239 { 0x09, 0x0000, 0x0080 }, 3240 { 0x19, 0x0000, 0x0224 }, 3241 { 0x00, 0x0000, 0x0008 }, 3242 { 0x0c, 0x3df0, 0x0200 }, 3243 }; 3244 3245 rtl_hw_start_8168f(tp); 3246 3247 rtl_ephy_init(tp, e_info_8168f_1); 3248 } 3249 3250 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3251 { 3252 static const struct ephy_info e_info_8168f_1[] = { 3253 { 0x06, 0x00c0, 0x0020 }, 3254 { 0x0f, 0xffff, 0x5200 }, 3255 { 0x19, 0x0000, 0x0224 }, 3256 { 0x00, 0x0000, 0x0008 }, 3257 { 0x0c, 0x3df0, 0x0200 }, 3258 }; 3259 3260 rtl_hw_start_8168f(tp); 3261 rtl_pcie_state_l2l3_disable(tp); 3262 3263 rtl_ephy_init(tp, e_info_8168f_1); 3264 } 3265 3266 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3267 { 3268 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3269 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3270 3271 rtl_set_def_aspm_entry_latency(tp); 3272 3273 rtl_reset_packet_filter(tp); 3274 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3275 3276 rtl_disable_rxdvgate(tp); 3277 3278 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3279 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3280 3281 rtl8168_config_eee_mac(tp); 3282 3283 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3284 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3285 3286 rtl_pcie_state_l2l3_disable(tp); 3287 } 3288 3289 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3290 { 3291 static const struct ephy_info e_info_8168g_1[] = { 3292 { 0x00, 0x0008, 0x0000 }, 3293 { 0x0c, 0x3ff0, 0x0820 }, 3294 { 0x1e, 0x0000, 0x0001 }, 3295 { 0x19, 0x8000, 0x0000 } 3296 }; 3297 3298 rtl_hw_start_8168g(tp); 3299 rtl_ephy_init(tp, e_info_8168g_1); 3300 } 3301 3302 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3303 { 3304 static const struct ephy_info e_info_8168g_2[] = { 3305 { 0x00, 0x0008, 0x0000 }, 3306 { 0x0c, 0x3ff0, 0x0820 }, 3307 { 0x19, 0xffff, 0x7c00 }, 3308 { 0x1e, 0xffff, 0x20eb }, 3309 { 0x0d, 0xffff, 0x1666 }, 3310 { 0x00, 0xffff, 0x10a3 }, 3311 { 0x06, 0xffff, 0xf050 }, 3312 { 0x04, 0x0000, 0x0010 }, 3313 { 0x1d, 0x4000, 0x0000 }, 3314 }; 3315 3316 rtl_hw_start_8168g(tp); 3317 rtl_ephy_init(tp, e_info_8168g_2); 3318 } 3319 3320 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3321 { 3322 static const u16 fix_data[] = { 3323 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3324 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3325 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3326 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3327 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3328 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3329 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3330 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3331 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3332 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3333 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3334 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3335 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3336 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3337 }; 3338 unsigned long flags; 3339 int i; 3340 3341 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3342 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3343 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3344 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3345 } 3346 3347 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3348 { 3349 static const struct ephy_info e_info_8411_2[] = { 3350 { 0x00, 0x0008, 0x0000 }, 3351 { 0x0c, 0x37d0, 0x0820 }, 3352 { 0x1e, 0x0000, 0x0001 }, 3353 { 0x19, 0x8021, 0x0000 }, 3354 { 0x1e, 0x0000, 0x2000 }, 3355 { 0x0d, 0x0100, 0x0200 }, 3356 { 0x00, 0x0000, 0x0080 }, 3357 { 0x06, 0x0000, 0x0010 }, 3358 { 0x04, 0x0000, 0x0010 }, 3359 { 0x1d, 0x0000, 0x4000 }, 3360 }; 3361 3362 rtl_hw_start_8168g(tp); 3363 3364 rtl_ephy_init(tp, e_info_8411_2); 3365 3366 /* The following Realtek-provided magic fixes an issue with the RX unit 3367 * getting confused after the PHY having been powered-down. 3368 */ 3369 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3370 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3371 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3372 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3373 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3374 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3375 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3376 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3377 mdelay(3); 3378 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3379 3380 rtl8411b_fix_phy_down(tp); 3381 3382 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3383 3384 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3385 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3386 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3387 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3388 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3389 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3390 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3391 } 3392 3393 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3394 { 3395 static const struct ephy_info e_info_8168h_1[] = { 3396 { 0x1e, 0x0800, 0x0001 }, 3397 { 0x1d, 0x0000, 0x0800 }, 3398 { 0x05, 0xffff, 0x2089 }, 3399 { 0x06, 0xffff, 0x5881 }, 3400 { 0x04, 0xffff, 0x854a }, 3401 { 0x01, 0xffff, 0x068b } 3402 }; 3403 int rg_saw_cnt; 3404 3405 rtl_ephy_init(tp, e_info_8168h_1); 3406 3407 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3408 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3409 3410 rtl_set_def_aspm_entry_latency(tp); 3411 3412 rtl_reset_packet_filter(tp); 3413 3414 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3415 3416 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3417 3418 rtl_disable_rxdvgate(tp); 3419 3420 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3421 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3422 3423 rtl8168_config_eee_mac(tp); 3424 3425 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3426 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3427 3428 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3429 3430 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3431 3432 rtl_pcie_state_l2l3_disable(tp); 3433 3434 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3435 if (rg_saw_cnt > 0) { 3436 u16 sw_cnt_1ms_ini; 3437 3438 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3439 sw_cnt_1ms_ini &= 0x0fff; 3440 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3441 } 3442 3443 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3444 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3445 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3446 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3447 3448 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3449 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3450 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3451 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3452 } 3453 3454 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3455 { 3456 rtl8168ep_stop_cmac(tp); 3457 3458 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3459 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3460 3461 rtl_set_def_aspm_entry_latency(tp); 3462 3463 rtl_reset_packet_filter(tp); 3464 3465 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3466 3467 rtl_disable_rxdvgate(tp); 3468 3469 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3470 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3471 3472 rtl8168_config_eee_mac(tp); 3473 3474 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3475 3476 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3477 3478 rtl_pcie_state_l2l3_disable(tp); 3479 } 3480 3481 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3482 { 3483 static const struct ephy_info e_info_8168ep_3[] = { 3484 { 0x00, 0x0000, 0x0080 }, 3485 { 0x0d, 0x0100, 0x0200 }, 3486 { 0x19, 0x8021, 0x0000 }, 3487 { 0x1e, 0x0000, 0x2000 }, 3488 }; 3489 3490 rtl_ephy_init(tp, e_info_8168ep_3); 3491 3492 rtl_hw_start_8168ep(tp); 3493 3494 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3495 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3496 3497 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3498 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3499 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3500 } 3501 3502 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3503 { 3504 static const struct ephy_info e_info_8117[] = { 3505 { 0x19, 0x0040, 0x1100 }, 3506 { 0x59, 0x0040, 0x1100 }, 3507 }; 3508 int rg_saw_cnt; 3509 3510 rtl8168ep_stop_cmac(tp); 3511 rtl_ephy_init(tp, e_info_8117); 3512 3513 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3514 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3515 3516 rtl_set_def_aspm_entry_latency(tp); 3517 3518 rtl_reset_packet_filter(tp); 3519 3520 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3521 3522 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3523 3524 rtl_disable_rxdvgate(tp); 3525 3526 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3527 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3528 3529 rtl8168_config_eee_mac(tp); 3530 3531 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3532 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3533 3534 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3535 3536 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3537 3538 rtl_pcie_state_l2l3_disable(tp); 3539 3540 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3541 if (rg_saw_cnt > 0) { 3542 u16 sw_cnt_1ms_ini; 3543 3544 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3545 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3546 } 3547 3548 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3549 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3550 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3551 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3552 3553 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3554 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3555 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3556 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3557 3558 /* firmware is for MAC only */ 3559 r8169_apply_firmware(tp); 3560 } 3561 3562 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3563 { 3564 static const struct ephy_info e_info_8102e_1[] = { 3565 { 0x01, 0, 0x6e65 }, 3566 { 0x02, 0, 0x091f }, 3567 { 0x03, 0, 0xc2f9 }, 3568 { 0x06, 0, 0xafb5 }, 3569 { 0x07, 0, 0x0e00 }, 3570 { 0x19, 0, 0xec80 }, 3571 { 0x01, 0, 0x2e65 }, 3572 { 0x01, 0, 0x6e65 } 3573 }; 3574 u8 cfg1; 3575 3576 rtl_set_def_aspm_entry_latency(tp); 3577 3578 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3579 3580 RTL_W8(tp, Config1, 3581 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3582 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3583 3584 cfg1 = RTL_R8(tp, Config1); 3585 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3586 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3587 3588 rtl_ephy_init(tp, e_info_8102e_1); 3589 } 3590 3591 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3592 { 3593 rtl_set_def_aspm_entry_latency(tp); 3594 3595 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3596 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3597 } 3598 3599 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3600 { 3601 rtl_hw_start_8102e_2(tp); 3602 3603 rtl_ephy_write(tp, 0x03, 0xc2f9); 3604 } 3605 3606 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3607 { 3608 static const struct ephy_info e_info_8401[] = { 3609 { 0x01, 0xffff, 0x6fe5 }, 3610 { 0x03, 0xffff, 0x0599 }, 3611 { 0x06, 0xffff, 0xaf25 }, 3612 { 0x07, 0xffff, 0x8e68 }, 3613 }; 3614 3615 rtl_ephy_init(tp, e_info_8401); 3616 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3617 } 3618 3619 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3620 { 3621 static const struct ephy_info e_info_8105e_1[] = { 3622 { 0x07, 0, 0x4000 }, 3623 { 0x19, 0, 0x0200 }, 3624 { 0x19, 0, 0x0020 }, 3625 { 0x1e, 0, 0x2000 }, 3626 { 0x03, 0, 0x0001 }, 3627 { 0x19, 0, 0x0100 }, 3628 { 0x19, 0, 0x0004 }, 3629 { 0x0a, 0, 0x0020 } 3630 }; 3631 3632 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3633 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3634 3635 /* Disable Early Tally Counter */ 3636 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3637 3638 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3639 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3640 3641 rtl_ephy_init(tp, e_info_8105e_1); 3642 3643 rtl_pcie_state_l2l3_disable(tp); 3644 } 3645 3646 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3647 { 3648 rtl_hw_start_8105e_1(tp); 3649 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3650 } 3651 3652 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3653 { 3654 static const struct ephy_info e_info_8402[] = { 3655 { 0x19, 0xffff, 0xff64 }, 3656 { 0x1e, 0, 0x4000 } 3657 }; 3658 3659 rtl_set_def_aspm_entry_latency(tp); 3660 3661 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3662 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3663 3664 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3665 3666 rtl_ephy_init(tp, e_info_8402); 3667 3668 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3669 rtl_reset_packet_filter(tp); 3670 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3671 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3672 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3673 3674 /* disable EEE */ 3675 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3676 3677 rtl_pcie_state_l2l3_disable(tp); 3678 } 3679 3680 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3681 { 3682 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3683 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3684 3685 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3686 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3687 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3688 3689 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3690 rtl_set_aspm_entry_latency(tp, 0x2f); 3691 3692 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3693 3694 /* disable EEE */ 3695 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3696 3697 rtl_pcie_state_l2l3_disable(tp); 3698 } 3699 3700 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3701 { 3702 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3703 } 3704 3705 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3706 { 3707 rtl_pcie_state_l2l3_disable(tp); 3708 3709 RTL_W16(tp, 0x382, 0x221b); 3710 RTL_W8(tp, 0x4500, 0); 3711 RTL_W16(tp, 0x4800, 0); 3712 3713 /* disable UPS */ 3714 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3715 3716 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3717 3718 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3719 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3720 3721 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3722 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3723 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3724 3725 /* disable new tx descriptor format */ 3726 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3727 3728 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3729 tp->mac_version == RTL_GIGA_MAC_VER_66) 3730 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3731 3732 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3733 tp->mac_version == RTL_GIGA_MAC_VER_66) 3734 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3735 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3736 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3737 else 3738 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3739 3740 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3741 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3742 else 3743 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3744 3745 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3746 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3747 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3748 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3749 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3750 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3751 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3752 tp->mac_version == RTL_GIGA_MAC_VER_66) 3753 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3754 else 3755 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3756 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3757 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3758 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3759 3760 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3761 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3762 udelay(1); 3763 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3764 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3765 3766 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3767 3768 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3769 3770 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3771 rtl8125a_config_eee_mac(tp); 3772 else 3773 rtl8125b_config_eee_mac(tp); 3774 3775 rtl_disable_rxdvgate(tp); 3776 } 3777 3778 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3779 { 3780 static const struct ephy_info e_info_8125a_2[] = { 3781 { 0x04, 0xffff, 0xd000 }, 3782 { 0x0a, 0xffff, 0x8653 }, 3783 { 0x23, 0xffff, 0xab66 }, 3784 { 0x20, 0xffff, 0x9455 }, 3785 { 0x21, 0xffff, 0x99ff }, 3786 { 0x29, 0xffff, 0xfe04 }, 3787 3788 { 0x44, 0xffff, 0xd000 }, 3789 { 0x4a, 0xffff, 0x8653 }, 3790 { 0x63, 0xffff, 0xab66 }, 3791 { 0x60, 0xffff, 0x9455 }, 3792 { 0x61, 0xffff, 0x99ff }, 3793 { 0x69, 0xffff, 0xfe04 }, 3794 }; 3795 3796 rtl_set_def_aspm_entry_latency(tp); 3797 rtl_ephy_init(tp, e_info_8125a_2); 3798 rtl_hw_start_8125_common(tp); 3799 } 3800 3801 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3802 { 3803 static const struct ephy_info e_info_8125b[] = { 3804 { 0x0b, 0xffff, 0xa908 }, 3805 { 0x1e, 0xffff, 0x20eb }, 3806 { 0x4b, 0xffff, 0xa908 }, 3807 { 0x5e, 0xffff, 0x20eb }, 3808 { 0x22, 0x0030, 0x0020 }, 3809 { 0x62, 0x0030, 0x0020 }, 3810 }; 3811 3812 rtl_set_def_aspm_entry_latency(tp); 3813 rtl_ephy_init(tp, e_info_8125b); 3814 rtl_hw_start_8125_common(tp); 3815 } 3816 3817 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3818 { 3819 rtl_set_def_aspm_entry_latency(tp); 3820 rtl_hw_start_8125_common(tp); 3821 } 3822 3823 static void rtl_hw_config(struct rtl8169_private *tp) 3824 { 3825 static const rtl_generic_fct hw_configs[] = { 3826 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3827 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3828 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3829 [RTL_GIGA_MAC_VER_10] = NULL, 3830 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3831 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3832 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3833 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3834 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3835 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3836 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3837 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3838 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3839 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3840 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3841 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3842 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3843 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3844 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3845 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3846 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3847 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3848 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3849 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3850 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3851 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3852 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3853 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3854 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3855 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3856 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3857 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3858 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3859 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3860 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3861 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3862 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3863 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3864 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3865 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3866 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a, 3867 }; 3868 3869 if (hw_configs[tp->mac_version]) 3870 hw_configs[tp->mac_version](tp); 3871 } 3872 3873 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3874 { 3875 int i; 3876 3877 RTL_W8(tp, INT_CFG0_8125, 0x00); 3878 3879 /* disable interrupt coalescing */ 3880 switch (tp->mac_version) { 3881 case RTL_GIGA_MAC_VER_61: 3882 for (i = 0xa00; i < 0xb00; i += 4) 3883 RTL_W32(tp, i, 0); 3884 break; 3885 case RTL_GIGA_MAC_VER_63: 3886 case RTL_GIGA_MAC_VER_65: 3887 case RTL_GIGA_MAC_VER_66: 3888 for (i = 0xa00; i < 0xa80; i += 4) 3889 RTL_W32(tp, i, 0); 3890 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3891 break; 3892 default: 3893 break; 3894 } 3895 3896 rtl_hw_config(tp); 3897 } 3898 3899 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3900 { 3901 if (rtl_is_8168evl_up(tp)) 3902 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3903 else 3904 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3905 3906 rtl_hw_config(tp); 3907 3908 /* disable interrupt coalescing */ 3909 RTL_W16(tp, IntrMitigate, 0x0000); 3910 } 3911 3912 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3913 { 3914 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3915 3916 tp->cp_cmd |= PCIMulRW; 3917 3918 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3919 tp->mac_version == RTL_GIGA_MAC_VER_03) 3920 tp->cp_cmd |= EnAnaPLL; 3921 3922 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3923 3924 rtl8169_set_magic_reg(tp); 3925 3926 /* disable interrupt coalescing */ 3927 RTL_W16(tp, IntrMitigate, 0x0000); 3928 } 3929 3930 static void rtl_hw_start(struct rtl8169_private *tp) 3931 { 3932 rtl_unlock_config_regs(tp); 3933 /* disable aspm and clock request before ephy access */ 3934 rtl_hw_aspm_clkreq_enable(tp, false); 3935 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3936 3937 rtl_set_eee_txidle_timer(tp); 3938 3939 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3940 rtl_hw_start_8169(tp); 3941 else if (rtl_is_8125(tp)) 3942 rtl_hw_start_8125(tp); 3943 else 3944 rtl_hw_start_8168(tp); 3945 3946 rtl_enable_exit_l1(tp); 3947 rtl_hw_aspm_clkreq_enable(tp, true); 3948 rtl_set_rx_max_size(tp); 3949 rtl_set_rx_tx_desc_registers(tp); 3950 rtl_lock_config_regs(tp); 3951 3952 rtl_jumbo_config(tp); 3953 3954 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3955 rtl_pci_commit(tp); 3956 3957 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3958 rtl_init_rxcfg(tp); 3959 rtl_set_tx_config_registers(tp); 3960 rtl_set_rx_config_features(tp, tp->dev->features); 3961 rtl_set_rx_mode(tp->dev); 3962 rtl_irq_enable(tp); 3963 } 3964 3965 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3966 { 3967 struct rtl8169_private *tp = netdev_priv(dev); 3968 3969 WRITE_ONCE(dev->mtu, new_mtu); 3970 netdev_update_features(dev); 3971 rtl_jumbo_config(tp); 3972 rtl_set_eee_txidle_timer(tp); 3973 3974 return 0; 3975 } 3976 3977 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3978 { 3979 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3980 3981 desc->opts2 = 0; 3982 /* Force memory writes to complete before releasing descriptor */ 3983 dma_wmb(); 3984 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3985 } 3986 3987 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3988 struct RxDesc *desc) 3989 { 3990 struct device *d = tp_to_dev(tp); 3991 int node = dev_to_node(d); 3992 dma_addr_t mapping; 3993 struct page *data; 3994 3995 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3996 if (!data) 3997 return NULL; 3998 3999 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4000 if (unlikely(dma_mapping_error(d, mapping))) { 4001 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 4002 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 4003 return NULL; 4004 } 4005 4006 desc->addr = cpu_to_le64(mapping); 4007 rtl8169_mark_to_asic(desc); 4008 4009 return data; 4010 } 4011 4012 static void rtl8169_rx_clear(struct rtl8169_private *tp) 4013 { 4014 int i; 4015 4016 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 4017 dma_unmap_page(tp_to_dev(tp), 4018 le64_to_cpu(tp->RxDescArray[i].addr), 4019 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 4020 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4021 tp->Rx_databuff[i] = NULL; 4022 tp->RxDescArray[i].addr = 0; 4023 tp->RxDescArray[i].opts1 = 0; 4024 } 4025 } 4026 4027 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4028 { 4029 int i; 4030 4031 for (i = 0; i < NUM_RX_DESC; i++) { 4032 struct page *data; 4033 4034 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4035 if (!data) { 4036 rtl8169_rx_clear(tp); 4037 return -ENOMEM; 4038 } 4039 tp->Rx_databuff[i] = data; 4040 } 4041 4042 /* mark as last descriptor in the ring */ 4043 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4044 4045 return 0; 4046 } 4047 4048 static int rtl8169_init_ring(struct rtl8169_private *tp) 4049 { 4050 rtl8169_init_ring_indexes(tp); 4051 4052 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4053 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4054 4055 return rtl8169_rx_fill(tp); 4056 } 4057 4058 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4059 { 4060 struct ring_info *tx_skb = tp->tx_skb + entry; 4061 struct TxDesc *desc = tp->TxDescArray + entry; 4062 4063 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4064 DMA_TO_DEVICE); 4065 memset(desc, 0, sizeof(*desc)); 4066 memset(tx_skb, 0, sizeof(*tx_skb)); 4067 } 4068 4069 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4070 unsigned int n) 4071 { 4072 unsigned int i; 4073 4074 for (i = 0; i < n; i++) { 4075 unsigned int entry = (start + i) % NUM_TX_DESC; 4076 struct ring_info *tx_skb = tp->tx_skb + entry; 4077 unsigned int len = tx_skb->len; 4078 4079 if (len) { 4080 struct sk_buff *skb = tx_skb->skb; 4081 4082 rtl8169_unmap_tx_skb(tp, entry); 4083 if (skb) 4084 dev_consume_skb_any(skb); 4085 } 4086 } 4087 } 4088 4089 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4090 { 4091 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4092 netdev_reset_queue(tp->dev); 4093 } 4094 4095 static void rtl8169_cleanup(struct rtl8169_private *tp) 4096 { 4097 napi_disable(&tp->napi); 4098 4099 /* Give a racing hard_start_xmit a few cycles to complete. */ 4100 synchronize_net(); 4101 4102 /* Disable interrupts */ 4103 rtl8169_irq_mask_and_ack(tp); 4104 4105 rtl_rx_close(tp); 4106 4107 switch (tp->mac_version) { 4108 case RTL_GIGA_MAC_VER_28: 4109 case RTL_GIGA_MAC_VER_31: 4110 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4111 break; 4112 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4113 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4114 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4115 break; 4116 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 4117 rtl_enable_rxdvgate(tp); 4118 fsleep(2000); 4119 break; 4120 default: 4121 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4122 fsleep(100); 4123 break; 4124 } 4125 4126 rtl_hw_reset(tp); 4127 4128 rtl8169_tx_clear(tp); 4129 rtl8169_init_ring_indexes(tp); 4130 } 4131 4132 static void rtl_reset_work(struct rtl8169_private *tp) 4133 { 4134 int i; 4135 4136 netif_stop_queue(tp->dev); 4137 4138 rtl8169_cleanup(tp); 4139 4140 for (i = 0; i < NUM_RX_DESC; i++) 4141 rtl8169_mark_to_asic(tp->RxDescArray + i); 4142 4143 napi_enable(&tp->napi); 4144 rtl_hw_start(tp); 4145 } 4146 4147 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4148 { 4149 struct rtl8169_private *tp = netdev_priv(dev); 4150 4151 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4152 } 4153 4154 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4155 void *addr, unsigned int entry, bool desc_own) 4156 { 4157 struct TxDesc *txd = tp->TxDescArray + entry; 4158 struct device *d = tp_to_dev(tp); 4159 dma_addr_t mapping; 4160 u32 opts1; 4161 int ret; 4162 4163 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4164 ret = dma_mapping_error(d, mapping); 4165 if (unlikely(ret)) { 4166 if (net_ratelimit()) 4167 netdev_err(tp->dev, "Failed to map TX data!\n"); 4168 return ret; 4169 } 4170 4171 txd->addr = cpu_to_le64(mapping); 4172 txd->opts2 = cpu_to_le32(opts[1]); 4173 4174 opts1 = opts[0] | len; 4175 if (entry == NUM_TX_DESC - 1) 4176 opts1 |= RingEnd; 4177 if (desc_own) 4178 opts1 |= DescOwn; 4179 txd->opts1 = cpu_to_le32(opts1); 4180 4181 tp->tx_skb[entry].len = len; 4182 4183 return 0; 4184 } 4185 4186 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4187 const u32 *opts, unsigned int entry) 4188 { 4189 struct skb_shared_info *info = skb_shinfo(skb); 4190 unsigned int cur_frag; 4191 4192 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4193 const skb_frag_t *frag = info->frags + cur_frag; 4194 void *addr = skb_frag_address(frag); 4195 u32 len = skb_frag_size(frag); 4196 4197 entry = (entry + 1) % NUM_TX_DESC; 4198 4199 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4200 goto err_out; 4201 } 4202 4203 return 0; 4204 4205 err_out: 4206 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4207 return -EIO; 4208 } 4209 4210 static bool rtl_skb_is_udp(struct sk_buff *skb) 4211 { 4212 int no = skb_network_offset(skb); 4213 struct ipv6hdr *i6h, _i6h; 4214 struct iphdr *ih, _ih; 4215 4216 switch (vlan_get_protocol(skb)) { 4217 case htons(ETH_P_IP): 4218 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4219 return ih && ih->protocol == IPPROTO_UDP; 4220 case htons(ETH_P_IPV6): 4221 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4222 return i6h && i6h->nexthdr == IPPROTO_UDP; 4223 default: 4224 return false; 4225 } 4226 } 4227 4228 #define RTL_MIN_PATCH_LEN 47 4229 4230 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4231 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4232 struct sk_buff *skb) 4233 { 4234 unsigned int padto = 0, len = skb->len; 4235 4236 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4237 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4238 unsigned int trans_data_len = skb_tail_pointer(skb) - 4239 skb_transport_header(skb); 4240 4241 if (trans_data_len >= offsetof(struct udphdr, len) && 4242 trans_data_len < RTL_MIN_PATCH_LEN) { 4243 u16 dest = ntohs(udp_hdr(skb)->dest); 4244 4245 /* dest is a standard PTP port */ 4246 if (dest == 319 || dest == 320) 4247 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4248 } 4249 4250 if (trans_data_len < sizeof(struct udphdr)) 4251 padto = max_t(unsigned int, padto, 4252 len + sizeof(struct udphdr) - trans_data_len); 4253 } 4254 4255 return padto; 4256 } 4257 4258 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4259 struct sk_buff *skb) 4260 { 4261 unsigned int padto; 4262 4263 padto = rtl8125_quirk_udp_padto(tp, skb); 4264 4265 switch (tp->mac_version) { 4266 case RTL_GIGA_MAC_VER_34: 4267 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 4268 padto = max_t(unsigned int, padto, ETH_ZLEN); 4269 break; 4270 default: 4271 break; 4272 } 4273 4274 return padto; 4275 } 4276 4277 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4278 { 4279 u32 mss = skb_shinfo(skb)->gso_size; 4280 4281 if (mss) { 4282 opts[0] |= TD_LSO; 4283 opts[0] |= mss << TD0_MSS_SHIFT; 4284 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4285 const struct iphdr *ip = ip_hdr(skb); 4286 4287 if (ip->protocol == IPPROTO_TCP) 4288 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4289 else if (ip->protocol == IPPROTO_UDP) 4290 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4291 else 4292 WARN_ON_ONCE(1); 4293 } 4294 } 4295 4296 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4297 struct sk_buff *skb, u32 *opts) 4298 { 4299 struct skb_shared_info *shinfo = skb_shinfo(skb); 4300 u32 mss = shinfo->gso_size; 4301 4302 if (mss) { 4303 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4304 opts[0] |= TD1_GTSENV4; 4305 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4306 if (skb_cow_head(skb, 0)) 4307 return false; 4308 4309 tcp_v6_gso_csum_prep(skb); 4310 opts[0] |= TD1_GTSENV6; 4311 } else { 4312 WARN_ON_ONCE(1); 4313 } 4314 4315 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4316 opts[1] |= mss << TD1_MSS_SHIFT; 4317 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4318 u8 ip_protocol; 4319 4320 switch (vlan_get_protocol(skb)) { 4321 case htons(ETH_P_IP): 4322 opts[1] |= TD1_IPv4_CS; 4323 ip_protocol = ip_hdr(skb)->protocol; 4324 break; 4325 4326 case htons(ETH_P_IPV6): 4327 opts[1] |= TD1_IPv6_CS; 4328 ip_protocol = ipv6_hdr(skb)->nexthdr; 4329 break; 4330 4331 default: 4332 ip_protocol = IPPROTO_RAW; 4333 break; 4334 } 4335 4336 if (ip_protocol == IPPROTO_TCP) 4337 opts[1] |= TD1_TCP_CS; 4338 else if (ip_protocol == IPPROTO_UDP) 4339 opts[1] |= TD1_UDP_CS; 4340 else 4341 WARN_ON_ONCE(1); 4342 4343 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4344 } else { 4345 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4346 4347 /* skb_padto would free the skb on error */ 4348 return !__skb_put_padto(skb, padto, false); 4349 } 4350 4351 return true; 4352 } 4353 4354 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4355 { 4356 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4357 } 4358 4359 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4360 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4361 { 4362 switch (tp->mac_version) { 4363 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4364 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4365 return false; 4366 default: 4367 return true; 4368 } 4369 } 4370 4371 static void rtl8169_doorbell(struct rtl8169_private *tp) 4372 { 4373 if (rtl_is_8125(tp)) 4374 RTL_W16(tp, TxPoll_8125, BIT(0)); 4375 else 4376 RTL_W8(tp, TxPoll, NPQ); 4377 } 4378 4379 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4380 struct net_device *dev) 4381 { 4382 struct rtl8169_private *tp = netdev_priv(dev); 4383 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4384 struct TxDesc *txd_first, *txd_last; 4385 bool stop_queue, door_bell; 4386 unsigned int frags; 4387 u32 opts[2]; 4388 4389 if (unlikely(!rtl_tx_slots_avail(tp))) { 4390 if (net_ratelimit()) 4391 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4392 netif_stop_queue(dev); 4393 return NETDEV_TX_BUSY; 4394 } 4395 4396 opts[1] = rtl8169_tx_vlan_tag(skb); 4397 opts[0] = 0; 4398 4399 if (!rtl_chip_supports_csum_v2(tp)) 4400 rtl8169_tso_csum_v1(skb, opts); 4401 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4402 goto err_dma_0; 4403 4404 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4405 entry, false))) 4406 goto err_dma_0; 4407 4408 txd_first = tp->TxDescArray + entry; 4409 4410 frags = skb_shinfo(skb)->nr_frags; 4411 if (frags) { 4412 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4413 goto err_dma_1; 4414 entry = (entry + frags) % NUM_TX_DESC; 4415 } 4416 4417 txd_last = tp->TxDescArray + entry; 4418 txd_last->opts1 |= cpu_to_le32(LastFrag); 4419 tp->tx_skb[entry].skb = skb; 4420 4421 skb_tx_timestamp(skb); 4422 4423 /* Force memory writes to complete before releasing descriptor */ 4424 dma_wmb(); 4425 4426 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4427 4428 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4429 4430 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4431 smp_wmb(); 4432 4433 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4434 4435 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4436 R8169_TX_STOP_THRS, 4437 R8169_TX_START_THRS); 4438 if (door_bell || stop_queue) 4439 rtl8169_doorbell(tp); 4440 4441 return NETDEV_TX_OK; 4442 4443 err_dma_1: 4444 rtl8169_unmap_tx_skb(tp, entry); 4445 err_dma_0: 4446 dev_kfree_skb_any(skb); 4447 dev->stats.tx_dropped++; 4448 return NETDEV_TX_OK; 4449 } 4450 4451 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4452 { 4453 struct skb_shared_info *info = skb_shinfo(skb); 4454 unsigned int nr_frags = info->nr_frags; 4455 4456 if (!nr_frags) 4457 return UINT_MAX; 4458 4459 return skb_frag_size(info->frags + nr_frags - 1); 4460 } 4461 4462 /* Workaround for hw issues with TSO on RTL8168evl */ 4463 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4464 netdev_features_t features) 4465 { 4466 /* IPv4 header has options field */ 4467 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4468 ip_hdrlen(skb) > sizeof(struct iphdr)) 4469 features &= ~NETIF_F_ALL_TSO; 4470 4471 /* IPv4 TCP header has options field */ 4472 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4473 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4474 features &= ~NETIF_F_ALL_TSO; 4475 4476 else if (rtl_last_frag_len(skb) <= 6) 4477 features &= ~NETIF_F_ALL_TSO; 4478 4479 return features; 4480 } 4481 4482 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4483 struct net_device *dev, 4484 netdev_features_t features) 4485 { 4486 struct rtl8169_private *tp = netdev_priv(dev); 4487 4488 if (skb_is_gso(skb)) { 4489 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4490 features = rtl8168evl_fix_tso(skb, features); 4491 4492 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4493 rtl_chip_supports_csum_v2(tp)) 4494 features &= ~NETIF_F_ALL_TSO; 4495 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4496 /* work around hw bug on some chip versions */ 4497 if (skb->len < ETH_ZLEN) 4498 features &= ~NETIF_F_CSUM_MASK; 4499 4500 if (rtl_quirk_packet_padto(tp, skb)) 4501 features &= ~NETIF_F_CSUM_MASK; 4502 4503 if (skb_transport_offset(skb) > TCPHO_MAX && 4504 rtl_chip_supports_csum_v2(tp)) 4505 features &= ~NETIF_F_CSUM_MASK; 4506 } 4507 4508 return vlan_features_check(skb, features); 4509 } 4510 4511 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4512 { 4513 struct rtl8169_private *tp = netdev_priv(dev); 4514 struct pci_dev *pdev = tp->pci_dev; 4515 int pci_status_errs; 4516 u16 pci_cmd; 4517 4518 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4519 4520 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4521 4522 if (net_ratelimit()) 4523 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4524 pci_cmd, pci_status_errs); 4525 4526 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4527 } 4528 4529 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4530 int budget) 4531 { 4532 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4533 struct sk_buff *skb; 4534 4535 dirty_tx = tp->dirty_tx; 4536 4537 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4538 unsigned int entry = dirty_tx % NUM_TX_DESC; 4539 u32 status; 4540 4541 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4542 if (status & DescOwn) 4543 break; 4544 4545 skb = tp->tx_skb[entry].skb; 4546 rtl8169_unmap_tx_skb(tp, entry); 4547 4548 if (skb) { 4549 pkts_compl++; 4550 bytes_compl += skb->len; 4551 napi_consume_skb(skb, budget); 4552 } 4553 dirty_tx++; 4554 } 4555 4556 if (tp->dirty_tx != dirty_tx) { 4557 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4558 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4559 4560 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4561 rtl_tx_slots_avail(tp), 4562 R8169_TX_START_THRS); 4563 /* 4564 * 8168 hack: TxPoll requests are lost when the Tx packets are 4565 * too close. Let's kick an extra TxPoll request when a burst 4566 * of start_xmit activity is detected (if it is not detected, 4567 * it is slow enough). -- FR 4568 * If skb is NULL then we come here again once a tx irq is 4569 * triggered after the last fragment is marked transmitted. 4570 */ 4571 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4572 rtl8169_doorbell(tp); 4573 } 4574 } 4575 4576 static inline int rtl8169_fragmented_frame(u32 status) 4577 { 4578 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4579 } 4580 4581 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4582 { 4583 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4584 4585 if (status == RxProtoTCP || status == RxProtoUDP) 4586 skb->ip_summed = CHECKSUM_UNNECESSARY; 4587 else 4588 skb_checksum_none_assert(skb); 4589 } 4590 4591 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4592 { 4593 struct device *d = tp_to_dev(tp); 4594 int count; 4595 4596 for (count = 0; count < budget; count++, tp->cur_rx++) { 4597 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4598 struct RxDesc *desc = tp->RxDescArray + entry; 4599 struct sk_buff *skb; 4600 const void *rx_buf; 4601 dma_addr_t addr; 4602 u32 status; 4603 4604 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4605 if (status & DescOwn) 4606 break; 4607 4608 /* This barrier is needed to keep us from reading 4609 * any other fields out of the Rx descriptor until 4610 * we know the status of DescOwn 4611 */ 4612 dma_rmb(); 4613 4614 if (unlikely(status & RxRES)) { 4615 if (net_ratelimit()) 4616 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4617 status); 4618 dev->stats.rx_errors++; 4619 if (status & (RxRWT | RxRUNT)) 4620 dev->stats.rx_length_errors++; 4621 if (status & RxCRC) 4622 dev->stats.rx_crc_errors++; 4623 4624 if (!(dev->features & NETIF_F_RXALL)) 4625 goto release_descriptor; 4626 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4627 goto release_descriptor; 4628 } 4629 4630 pkt_size = status & GENMASK(13, 0); 4631 if (likely(!(dev->features & NETIF_F_RXFCS))) 4632 pkt_size -= ETH_FCS_LEN; 4633 4634 /* The driver does not support incoming fragmented frames. 4635 * They are seen as a symptom of over-mtu sized frames. 4636 */ 4637 if (unlikely(rtl8169_fragmented_frame(status))) { 4638 dev->stats.rx_dropped++; 4639 dev->stats.rx_length_errors++; 4640 goto release_descriptor; 4641 } 4642 4643 skb = napi_alloc_skb(&tp->napi, pkt_size); 4644 if (unlikely(!skb)) { 4645 dev->stats.rx_dropped++; 4646 goto release_descriptor; 4647 } 4648 4649 addr = le64_to_cpu(desc->addr); 4650 rx_buf = page_address(tp->Rx_databuff[entry]); 4651 4652 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4653 prefetch(rx_buf); 4654 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4655 skb->tail += pkt_size; 4656 skb->len = pkt_size; 4657 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4658 4659 rtl8169_rx_csum(skb, status); 4660 skb->protocol = eth_type_trans(skb, dev); 4661 4662 rtl8169_rx_vlan_tag(desc, skb); 4663 4664 if (skb->pkt_type == PACKET_MULTICAST) 4665 dev->stats.multicast++; 4666 4667 napi_gro_receive(&tp->napi, skb); 4668 4669 dev_sw_netstats_rx_add(dev, pkt_size); 4670 release_descriptor: 4671 rtl8169_mark_to_asic(desc); 4672 } 4673 4674 return count; 4675 } 4676 4677 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4678 { 4679 struct rtl8169_private *tp = dev_instance; 4680 u32 status = rtl_get_events(tp); 4681 4682 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4683 return IRQ_NONE; 4684 4685 if (unlikely(status & SYSErr)) { 4686 rtl8169_pcierr_interrupt(tp->dev); 4687 goto out; 4688 } 4689 4690 if (status & LinkChg) 4691 phy_mac_interrupt(tp->phydev); 4692 4693 if (unlikely(status & RxFIFOOver && 4694 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4695 netif_stop_queue(tp->dev); 4696 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4697 } 4698 4699 rtl_irq_disable(tp); 4700 napi_schedule(&tp->napi); 4701 out: 4702 rtl_ack_events(tp, status); 4703 4704 return IRQ_HANDLED; 4705 } 4706 4707 static void rtl_task(struct work_struct *work) 4708 { 4709 struct rtl8169_private *tp = 4710 container_of(work, struct rtl8169_private, wk.work); 4711 int ret; 4712 4713 rtnl_lock(); 4714 4715 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4716 goto out_unlock; 4717 4718 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4719 /* if chip isn't accessible, reset bus to revive it */ 4720 if (RTL_R32(tp, TxConfig) == ~0) { 4721 ret = pci_reset_bus(tp->pci_dev); 4722 if (ret < 0) { 4723 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4724 netif_device_detach(tp->dev); 4725 goto out_unlock; 4726 } 4727 } 4728 4729 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4730 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4731 PCIE_LINK_STATE_L0S); 4732 if (!ret) 4733 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4734 goto reset; 4735 } 4736 4737 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4738 reset: 4739 rtl_reset_work(tp); 4740 netif_wake_queue(tp->dev); 4741 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { 4742 rtl_reset_work(tp); 4743 } 4744 out_unlock: 4745 rtnl_unlock(); 4746 } 4747 4748 static int rtl8169_poll(struct napi_struct *napi, int budget) 4749 { 4750 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4751 struct net_device *dev = tp->dev; 4752 int work_done; 4753 4754 rtl_tx(dev, tp, budget); 4755 4756 work_done = rtl_rx(dev, tp, budget); 4757 4758 if (work_done < budget && napi_complete_done(napi, work_done)) 4759 rtl_irq_enable(tp); 4760 4761 return work_done; 4762 } 4763 4764 static void r8169_phylink_handler(struct net_device *ndev) 4765 { 4766 struct rtl8169_private *tp = netdev_priv(ndev); 4767 struct device *d = tp_to_dev(tp); 4768 4769 if (netif_carrier_ok(ndev)) { 4770 rtl_link_chg_patch(tp); 4771 pm_request_resume(d); 4772 netif_wake_queue(tp->dev); 4773 } else { 4774 /* In few cases rx is broken after link-down otherwise */ 4775 if (rtl_is_8125(tp)) 4776 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); 4777 pm_runtime_idle(d); 4778 } 4779 4780 phy_print_status(tp->phydev); 4781 } 4782 4783 static int r8169_phy_connect(struct rtl8169_private *tp) 4784 { 4785 struct phy_device *phydev = tp->phydev; 4786 phy_interface_t phy_mode; 4787 int ret; 4788 4789 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4790 PHY_INTERFACE_MODE_MII; 4791 4792 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4793 phy_mode); 4794 if (ret) 4795 return ret; 4796 4797 if (!tp->supports_gmii) 4798 phy_set_max_speed(phydev, SPEED_100); 4799 4800 phy_attached_info(phydev); 4801 4802 return 0; 4803 } 4804 4805 static void rtl8169_down(struct rtl8169_private *tp) 4806 { 4807 /* Clear all task flags */ 4808 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4809 4810 phy_stop(tp->phydev); 4811 4812 rtl8169_update_counters(tp); 4813 4814 pci_clear_master(tp->pci_dev); 4815 rtl_pci_commit(tp); 4816 4817 rtl8169_cleanup(tp); 4818 rtl_disable_exit_l1(tp); 4819 rtl_prepare_power_down(tp); 4820 4821 if (tp->dash_type != RTL_DASH_NONE) 4822 rtl8168_driver_stop(tp); 4823 } 4824 4825 static void rtl8169_up(struct rtl8169_private *tp) 4826 { 4827 if (tp->dash_type != RTL_DASH_NONE) 4828 rtl8168_driver_start(tp); 4829 4830 pci_set_master(tp->pci_dev); 4831 phy_init_hw(tp->phydev); 4832 phy_resume(tp->phydev); 4833 rtl8169_init_phy(tp); 4834 napi_enable(&tp->napi); 4835 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4836 rtl_reset_work(tp); 4837 4838 phy_start(tp->phydev); 4839 } 4840 4841 static int rtl8169_close(struct net_device *dev) 4842 { 4843 struct rtl8169_private *tp = netdev_priv(dev); 4844 struct pci_dev *pdev = tp->pci_dev; 4845 4846 pm_runtime_get_sync(&pdev->dev); 4847 4848 netif_stop_queue(dev); 4849 rtl8169_down(tp); 4850 rtl8169_rx_clear(tp); 4851 4852 cancel_work(&tp->wk.work); 4853 4854 free_irq(tp->irq, tp); 4855 4856 phy_disconnect(tp->phydev); 4857 4858 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4859 tp->RxPhyAddr); 4860 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4861 tp->TxPhyAddr); 4862 tp->TxDescArray = NULL; 4863 tp->RxDescArray = NULL; 4864 4865 pm_runtime_put_sync(&pdev->dev); 4866 4867 return 0; 4868 } 4869 4870 #ifdef CONFIG_NET_POLL_CONTROLLER 4871 static void rtl8169_netpoll(struct net_device *dev) 4872 { 4873 struct rtl8169_private *tp = netdev_priv(dev); 4874 4875 rtl8169_interrupt(tp->irq, tp); 4876 } 4877 #endif 4878 4879 static int rtl_open(struct net_device *dev) 4880 { 4881 struct rtl8169_private *tp = netdev_priv(dev); 4882 struct pci_dev *pdev = tp->pci_dev; 4883 unsigned long irqflags; 4884 int retval = -ENOMEM; 4885 4886 pm_runtime_get_sync(&pdev->dev); 4887 4888 /* 4889 * Rx and Tx descriptors needs 256 bytes alignment. 4890 * dma_alloc_coherent provides more. 4891 */ 4892 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4893 &tp->TxPhyAddr, GFP_KERNEL); 4894 if (!tp->TxDescArray) 4895 goto out; 4896 4897 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4898 &tp->RxPhyAddr, GFP_KERNEL); 4899 if (!tp->RxDescArray) 4900 goto err_free_tx_0; 4901 4902 retval = rtl8169_init_ring(tp); 4903 if (retval < 0) 4904 goto err_free_rx_1; 4905 4906 rtl_request_firmware(tp); 4907 4908 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4909 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4910 if (retval < 0) 4911 goto err_release_fw_2; 4912 4913 retval = r8169_phy_connect(tp); 4914 if (retval) 4915 goto err_free_irq; 4916 4917 rtl8169_up(tp); 4918 rtl8169_init_counter_offsets(tp); 4919 netif_start_queue(dev); 4920 out: 4921 pm_runtime_put_sync(&pdev->dev); 4922 4923 return retval; 4924 4925 err_free_irq: 4926 free_irq(tp->irq, tp); 4927 err_release_fw_2: 4928 rtl_release_firmware(tp); 4929 rtl8169_rx_clear(tp); 4930 err_free_rx_1: 4931 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4932 tp->RxPhyAddr); 4933 tp->RxDescArray = NULL; 4934 err_free_tx_0: 4935 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4936 tp->TxPhyAddr); 4937 tp->TxDescArray = NULL; 4938 goto out; 4939 } 4940 4941 static void 4942 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4943 { 4944 struct rtl8169_private *tp = netdev_priv(dev); 4945 struct pci_dev *pdev = tp->pci_dev; 4946 struct rtl8169_counters *counters = tp->counters; 4947 4948 pm_runtime_get_noresume(&pdev->dev); 4949 4950 netdev_stats_to_stats64(stats, &dev->stats); 4951 dev_fetch_sw_netstats(stats, dev->tstats); 4952 4953 /* 4954 * Fetch additional counter values missing in stats collected by driver 4955 * from tally counters. 4956 */ 4957 if (pm_runtime_active(&pdev->dev)) 4958 rtl8169_update_counters(tp); 4959 4960 /* 4961 * Subtract values fetched during initalization. 4962 * See rtl8169_init_counter_offsets for a description why we do that. 4963 */ 4964 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4965 le64_to_cpu(tp->tc_offset.tx_errors); 4966 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4967 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4968 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4969 le16_to_cpu(tp->tc_offset.tx_aborted); 4970 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4971 le16_to_cpu(tp->tc_offset.rx_missed); 4972 4973 pm_runtime_put_noidle(&pdev->dev); 4974 } 4975 4976 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4977 { 4978 netif_device_detach(tp->dev); 4979 4980 if (netif_running(tp->dev)) 4981 rtl8169_down(tp); 4982 } 4983 4984 static int rtl8169_runtime_resume(struct device *dev) 4985 { 4986 struct rtl8169_private *tp = dev_get_drvdata(dev); 4987 4988 rtl_rar_set(tp, tp->dev->dev_addr); 4989 __rtl8169_set_wol(tp, tp->saved_wolopts); 4990 4991 if (tp->TxDescArray) 4992 rtl8169_up(tp); 4993 4994 netif_device_attach(tp->dev); 4995 4996 return 0; 4997 } 4998 4999 static int rtl8169_suspend(struct device *device) 5000 { 5001 struct rtl8169_private *tp = dev_get_drvdata(device); 5002 5003 rtnl_lock(); 5004 rtl8169_net_suspend(tp); 5005 if (!device_may_wakeup(tp_to_dev(tp))) 5006 clk_disable_unprepare(tp->clk); 5007 rtnl_unlock(); 5008 5009 return 0; 5010 } 5011 5012 static int rtl8169_resume(struct device *device) 5013 { 5014 struct rtl8169_private *tp = dev_get_drvdata(device); 5015 5016 if (!device_may_wakeup(tp_to_dev(tp))) 5017 clk_prepare_enable(tp->clk); 5018 5019 /* Reportedly at least Asus X453MA truncates packets otherwise */ 5020 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 5021 rtl_init_rxcfg(tp); 5022 5023 return rtl8169_runtime_resume(device); 5024 } 5025 5026 static int rtl8169_runtime_suspend(struct device *device) 5027 { 5028 struct rtl8169_private *tp = dev_get_drvdata(device); 5029 5030 if (!tp->TxDescArray) { 5031 netif_device_detach(tp->dev); 5032 return 0; 5033 } 5034 5035 rtnl_lock(); 5036 __rtl8169_set_wol(tp, WAKE_PHY); 5037 rtl8169_net_suspend(tp); 5038 rtnl_unlock(); 5039 5040 return 0; 5041 } 5042 5043 static int rtl8169_runtime_idle(struct device *device) 5044 { 5045 struct rtl8169_private *tp = dev_get_drvdata(device); 5046 5047 if (tp->dash_enabled) 5048 return -EBUSY; 5049 5050 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5051 pm_schedule_suspend(device, 10000); 5052 5053 return -EBUSY; 5054 } 5055 5056 static const struct dev_pm_ops rtl8169_pm_ops = { 5057 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5058 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5059 rtl8169_runtime_idle) 5060 }; 5061 5062 static void rtl_shutdown(struct pci_dev *pdev) 5063 { 5064 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5065 5066 rtnl_lock(); 5067 rtl8169_net_suspend(tp); 5068 rtnl_unlock(); 5069 5070 /* Restore original MAC address */ 5071 rtl_rar_set(tp, tp->dev->perm_addr); 5072 5073 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5074 pci_wake_from_d3(pdev, tp->saved_wolopts); 5075 pci_set_power_state(pdev, PCI_D3hot); 5076 } 5077 } 5078 5079 static void rtl_remove_one(struct pci_dev *pdev) 5080 { 5081 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5082 5083 if (pci_dev_run_wake(pdev)) 5084 pm_runtime_get_noresume(&pdev->dev); 5085 5086 cancel_work_sync(&tp->wk.work); 5087 5088 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5089 r8169_remove_leds(tp->leds); 5090 5091 unregister_netdev(tp->dev); 5092 5093 if (tp->dash_type != RTL_DASH_NONE) 5094 rtl8168_driver_stop(tp); 5095 5096 rtl_release_firmware(tp); 5097 5098 /* restore original MAC address */ 5099 rtl_rar_set(tp, tp->dev->perm_addr); 5100 } 5101 5102 static const struct net_device_ops rtl_netdev_ops = { 5103 .ndo_open = rtl_open, 5104 .ndo_stop = rtl8169_close, 5105 .ndo_get_stats64 = rtl8169_get_stats64, 5106 .ndo_start_xmit = rtl8169_start_xmit, 5107 .ndo_features_check = rtl8169_features_check, 5108 .ndo_tx_timeout = rtl8169_tx_timeout, 5109 .ndo_validate_addr = eth_validate_addr, 5110 .ndo_change_mtu = rtl8169_change_mtu, 5111 .ndo_fix_features = rtl8169_fix_features, 5112 .ndo_set_features = rtl8169_set_features, 5113 .ndo_set_mac_address = rtl_set_mac_address, 5114 .ndo_eth_ioctl = phy_do_ioctl_running, 5115 .ndo_set_rx_mode = rtl_set_rx_mode, 5116 #ifdef CONFIG_NET_POLL_CONTROLLER 5117 .ndo_poll_controller = rtl8169_netpoll, 5118 #endif 5119 5120 }; 5121 5122 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5123 { 5124 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5125 5126 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5127 tp->irq_mask |= SYSErr | RxFIFOOver; 5128 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5129 /* special workaround needed */ 5130 tp->irq_mask |= RxFIFOOver; 5131 } 5132 5133 static int rtl_alloc_irq(struct rtl8169_private *tp) 5134 { 5135 unsigned int flags; 5136 5137 switch (tp->mac_version) { 5138 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5139 rtl_unlock_config_regs(tp); 5140 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5141 rtl_lock_config_regs(tp); 5142 fallthrough; 5143 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5144 flags = PCI_IRQ_INTX; 5145 break; 5146 default: 5147 flags = PCI_IRQ_ALL_TYPES; 5148 break; 5149 } 5150 5151 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5152 } 5153 5154 static void rtl_read_mac_address(struct rtl8169_private *tp, 5155 u8 mac_addr[ETH_ALEN]) 5156 { 5157 /* Get MAC address */ 5158 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5159 u32 value; 5160 5161 value = rtl_eri_read(tp, 0xe0); 5162 put_unaligned_le32(value, mac_addr); 5163 value = rtl_eri_read(tp, 0xe4); 5164 put_unaligned_le16(value, mac_addr + 4); 5165 } else if (rtl_is_8125(tp)) { 5166 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5167 } 5168 } 5169 5170 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5171 { 5172 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5173 } 5174 5175 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5176 { 5177 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5178 } 5179 5180 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5181 { 5182 struct rtl8169_private *tp = mii_bus->priv; 5183 5184 if (phyaddr > 0) 5185 return -ENODEV; 5186 5187 return rtl_readphy(tp, phyreg); 5188 } 5189 5190 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5191 int phyreg, u16 val) 5192 { 5193 struct rtl8169_private *tp = mii_bus->priv; 5194 5195 if (phyaddr > 0) 5196 return -ENODEV; 5197 5198 rtl_writephy(tp, phyreg, val); 5199 5200 return 0; 5201 } 5202 5203 static int r8169_mdio_register(struct rtl8169_private *tp) 5204 { 5205 struct pci_dev *pdev = tp->pci_dev; 5206 struct mii_bus *new_bus; 5207 int ret; 5208 5209 /* On some boards with this chip version the BIOS is buggy and misses 5210 * to reset the PHY page selector. This results in the PHY ID read 5211 * accessing registers on a different page, returning a more or 5212 * less random value. Fix this by resetting the page selector first. 5213 */ 5214 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5215 tp->mac_version == RTL_GIGA_MAC_VER_26) 5216 r8169_mdio_write(tp, 0x1f, 0); 5217 5218 new_bus = devm_mdiobus_alloc(&pdev->dev); 5219 if (!new_bus) 5220 return -ENOMEM; 5221 5222 new_bus->name = "r8169"; 5223 new_bus->priv = tp; 5224 new_bus->parent = &pdev->dev; 5225 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5226 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5227 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5228 5229 new_bus->read = r8169_mdio_read_reg; 5230 new_bus->write = r8169_mdio_write_reg; 5231 5232 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5233 if (ret) 5234 return ret; 5235 5236 tp->phydev = mdiobus_get_phy(new_bus, 0); 5237 if (!tp->phydev) { 5238 return -ENODEV; 5239 } else if (!tp->phydev->drv) { 5240 /* Most chip versions fail with the genphy driver. 5241 * Therefore ensure that the dedicated PHY driver is loaded. 5242 */ 5243 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5244 tp->phydev->phy_id); 5245 return -EUNATCH; 5246 } 5247 5248 tp->phydev->mac_managed_pm = true; 5249 if (rtl_supports_eee(tp)) 5250 phy_support_eee(tp->phydev); 5251 phy_support_asym_pause(tp->phydev); 5252 5253 /* PHY will be woken up in rtl_open() */ 5254 phy_suspend(tp->phydev); 5255 5256 return 0; 5257 } 5258 5259 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5260 { 5261 rtl_enable_rxdvgate(tp); 5262 5263 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5264 msleep(1); 5265 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5266 5267 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5268 r8168g_wait_ll_share_fifo_ready(tp); 5269 5270 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5271 r8168g_wait_ll_share_fifo_ready(tp); 5272 } 5273 5274 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5275 { 5276 rtl_enable_rxdvgate(tp); 5277 5278 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5279 msleep(1); 5280 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5281 5282 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5283 r8168g_wait_ll_share_fifo_ready(tp); 5284 5285 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5286 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5287 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5288 r8168g_wait_ll_share_fifo_ready(tp); 5289 } 5290 5291 static void rtl_hw_initialize(struct rtl8169_private *tp) 5292 { 5293 switch (tp->mac_version) { 5294 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5295 rtl8168ep_stop_cmac(tp); 5296 fallthrough; 5297 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5298 rtl_hw_init_8168g(tp); 5299 break; 5300 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 5301 rtl_hw_init_8125(tp); 5302 break; 5303 default: 5304 break; 5305 } 5306 } 5307 5308 static int rtl_jumbo_max(struct rtl8169_private *tp) 5309 { 5310 /* Non-GBit versions don't support jumbo frames */ 5311 if (!tp->supports_gmii) 5312 return 0; 5313 5314 switch (tp->mac_version) { 5315 /* RTL8169 */ 5316 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5317 return JUMBO_7K; 5318 /* RTL8168b */ 5319 case RTL_GIGA_MAC_VER_11: 5320 case RTL_GIGA_MAC_VER_17: 5321 return JUMBO_4K; 5322 /* RTL8168c */ 5323 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5324 return JUMBO_6K; 5325 default: 5326 return JUMBO_9K; 5327 } 5328 } 5329 5330 static void rtl_init_mac_address(struct rtl8169_private *tp) 5331 { 5332 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5333 struct net_device *dev = tp->dev; 5334 int rc; 5335 5336 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5337 if (!rc) 5338 goto done; 5339 5340 rtl_read_mac_address(tp, mac_addr); 5341 if (is_valid_ether_addr(mac_addr)) 5342 goto done; 5343 5344 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5345 if (is_valid_ether_addr(mac_addr)) 5346 goto done; 5347 5348 eth_random_addr(mac_addr); 5349 dev->addr_assign_type = NET_ADDR_RANDOM; 5350 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5351 done: 5352 eth_hw_addr_set(dev, mac_addr); 5353 rtl_rar_set(tp, mac_addr); 5354 } 5355 5356 /* register is set if system vendor successfully tested ASPM 1.2 */ 5357 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5358 { 5359 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5360 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5361 return true; 5362 5363 return false; 5364 } 5365 5366 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5367 { 5368 struct rtl8169_private *tp; 5369 int jumbo_max, region, rc; 5370 enum mac_version chipset; 5371 struct net_device *dev; 5372 u32 txconfig; 5373 u16 xid; 5374 5375 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5376 if (!dev) 5377 return -ENOMEM; 5378 5379 SET_NETDEV_DEV(dev, &pdev->dev); 5380 dev->netdev_ops = &rtl_netdev_ops; 5381 tp = netdev_priv(dev); 5382 tp->dev = dev; 5383 tp->pci_dev = pdev; 5384 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5385 tp->ocp_base = OCP_STD_PHY_BASE; 5386 5387 raw_spin_lock_init(&tp->cfg9346_usage_lock); 5388 raw_spin_lock_init(&tp->config25_lock); 5389 raw_spin_lock_init(&tp->mac_ocp_lock); 5390 mutex_init(&tp->led_lock); 5391 5392 /* Get the *optional* external "ether_clk" used on some boards */ 5393 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5394 if (IS_ERR(tp->clk)) 5395 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5396 5397 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5398 rc = pcim_enable_device(pdev); 5399 if (rc < 0) 5400 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5401 5402 if (pcim_set_mwi(pdev) < 0) 5403 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5404 5405 /* use first MMIO region */ 5406 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5407 if (region < 0) 5408 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5409 5410 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5411 if (rc < 0) 5412 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5413 5414 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5415 5416 txconfig = RTL_R32(tp, TxConfig); 5417 if (txconfig == ~0U) 5418 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5419 5420 xid = (txconfig >> 20) & 0xfcf; 5421 5422 /* Identify chip attached to board */ 5423 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5424 if (chipset == RTL_GIGA_MAC_NONE) 5425 return dev_err_probe(&pdev->dev, -ENODEV, 5426 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5427 xid); 5428 tp->mac_version = chipset; 5429 5430 /* Disable ASPM L1 as that cause random device stop working 5431 * problems as well as full system hangs for some PCIe devices users. 5432 */ 5433 if (rtl_aspm_is_safe(tp)) 5434 rc = 0; 5435 else 5436 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5437 tp->aspm_manageable = !rc; 5438 5439 tp->dash_type = rtl_get_dash_type(tp); 5440 tp->dash_enabled = rtl_dash_is_enabled(tp); 5441 5442 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5443 5444 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5445 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5446 dev->features |= NETIF_F_HIGHDMA; 5447 5448 rtl_init_rxcfg(tp); 5449 5450 rtl8169_irq_mask_and_ack(tp); 5451 5452 rtl_hw_initialize(tp); 5453 5454 rtl_hw_reset(tp); 5455 5456 rc = rtl_alloc_irq(tp); 5457 if (rc < 0) 5458 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5459 5460 tp->irq = pci_irq_vector(pdev, 0); 5461 5462 INIT_WORK(&tp->wk.work, rtl_task); 5463 5464 rtl_init_mac_address(tp); 5465 5466 dev->ethtool_ops = &rtl8169_ethtool_ops; 5467 5468 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5469 5470 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5471 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5472 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5473 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5474 5475 /* 5476 * Pretend we are using VLANs; This bypasses a nasty bug where 5477 * Interrupts stop flowing on high load on 8110SCd controllers. 5478 */ 5479 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5480 /* Disallow toggling */ 5481 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5482 5483 if (rtl_chip_supports_csum_v2(tp)) 5484 dev->hw_features |= NETIF_F_IPV6_CSUM; 5485 5486 dev->features |= dev->hw_features; 5487 5488 /* There has been a number of reports that using SG/TSO results in 5489 * tx timeouts. However for a lot of people SG/TSO works fine. 5490 * Therefore disable both features by default, but allow users to 5491 * enable them. Use at own risk! 5492 */ 5493 if (rtl_chip_supports_csum_v2(tp)) { 5494 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5495 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5496 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5497 } else { 5498 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5499 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5500 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5501 } 5502 5503 dev->hw_features |= NETIF_F_RXALL; 5504 dev->hw_features |= NETIF_F_RXFCS; 5505 5506 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5507 5508 netdev_sw_irq_coalesce_default_on(dev); 5509 5510 /* configure chip for default features */ 5511 rtl8169_set_features(dev, dev->features); 5512 5513 if (!tp->dash_enabled) { 5514 rtl_set_d3_pll_down(tp, true); 5515 } else { 5516 rtl_set_d3_pll_down(tp, false); 5517 dev->ethtool->wol_enabled = 1; 5518 } 5519 5520 jumbo_max = rtl_jumbo_max(tp); 5521 if (jumbo_max) 5522 dev->max_mtu = jumbo_max; 5523 5524 rtl_set_irq_mask(tp); 5525 5526 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5527 5528 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5529 &tp->counters_phys_addr, 5530 GFP_KERNEL); 5531 if (!tp->counters) 5532 return -ENOMEM; 5533 5534 pci_set_drvdata(pdev, tp); 5535 5536 rc = r8169_mdio_register(tp); 5537 if (rc) 5538 return rc; 5539 5540 rc = register_netdev(dev); 5541 if (rc) 5542 return rc; 5543 5544 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5545 if (rtl_is_8125(tp)) 5546 tp->leds = rtl8125_init_leds(dev); 5547 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5548 tp->leds = rtl8168_init_leds(dev); 5549 } 5550 5551 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5552 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5553 5554 if (jumbo_max) 5555 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5556 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5557 "ok" : "ko"); 5558 5559 if (tp->dash_type != RTL_DASH_NONE) { 5560 netdev_info(dev, "DASH %s\n", 5561 tp->dash_enabled ? "enabled" : "disabled"); 5562 rtl8168_driver_start(tp); 5563 } 5564 5565 if (pci_dev_run_wake(pdev)) 5566 pm_runtime_put_sync(&pdev->dev); 5567 5568 return 0; 5569 } 5570 5571 static struct pci_driver rtl8169_pci_driver = { 5572 .name = KBUILD_MODNAME, 5573 .id_table = rtl8169_pci_tbl, 5574 .probe = rtl_init_one, 5575 .remove = rtl_remove_one, 5576 .shutdown = rtl_shutdown, 5577 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5578 }; 5579 5580 module_pci_driver(rtl8169_pci_driver); 5581