1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <asm/unaligned.h> 32 #include <net/ip6_checksum.h> 33 34 #include "r8169.h" 35 #include "r8169_firmware.h" 36 37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 52 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 53 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 54 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 55 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 56 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 57 58 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 59 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 60 #define MC_FILTER_LIMIT 32 61 62 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 63 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 64 65 #define R8169_REGS_SIZE 256 66 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 67 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 68 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 69 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 70 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 71 72 #define OCP_STD_PHY_BASE 0xa400 73 74 #define RTL_CFG_NO_GBIT 1 75 76 /* write/read MMIO register */ 77 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 78 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 79 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 81 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 82 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 83 84 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 85 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 86 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 89 static const struct { 90 const char *name; 91 const char *fw_name; 92 } rtl_chip_infos[] = { 93 /* PCI devices. */ 94 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 95 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 96 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 97 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 98 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 99 /* PCI-E devices. */ 100 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 101 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 102 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 103 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 104 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 105 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" }, 106 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 107 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 108 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 110 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 115 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 117 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 118 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 119 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 120 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 122 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 123 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 124 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 125 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 126 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 127 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 128 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 129 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 130 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 131 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 132 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 133 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 134 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 135 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 136 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 137 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 138 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 139 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 140 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 141 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 142 }; 143 144 static const struct pci_device_id rtl8169_pci_tbl[] = { 145 { PCI_VDEVICE(REALTEK, 0x2502) }, 146 { PCI_VDEVICE(REALTEK, 0x2600) }, 147 { PCI_VDEVICE(REALTEK, 0x8129) }, 148 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 149 { PCI_VDEVICE(REALTEK, 0x8161) }, 150 { PCI_VDEVICE(REALTEK, 0x8162) }, 151 { PCI_VDEVICE(REALTEK, 0x8167) }, 152 { PCI_VDEVICE(REALTEK, 0x8168) }, 153 { PCI_VDEVICE(NCUBE, 0x8168) }, 154 { PCI_VDEVICE(REALTEK, 0x8169) }, 155 { PCI_VENDOR_ID_DLINK, 0x4300, 156 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 157 { PCI_VDEVICE(DLINK, 0x4300) }, 158 { PCI_VDEVICE(DLINK, 0x4302) }, 159 { PCI_VDEVICE(AT, 0xc107) }, 160 { PCI_VDEVICE(USR, 0x0116) }, 161 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 162 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 163 { PCI_VDEVICE(REALTEK, 0x8125) }, 164 { PCI_VDEVICE(REALTEK, 0x3000) }, 165 {} 166 }; 167 168 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 169 170 enum rtl_registers { 171 MAC0 = 0, /* Ethernet hardware address. */ 172 MAC4 = 4, 173 MAR0 = 8, /* Multicast filter. */ 174 CounterAddrLow = 0x10, 175 CounterAddrHigh = 0x14, 176 TxDescStartAddrLow = 0x20, 177 TxDescStartAddrHigh = 0x24, 178 TxHDescStartAddrLow = 0x28, 179 TxHDescStartAddrHigh = 0x2c, 180 FLASH = 0x30, 181 ERSR = 0x36, 182 ChipCmd = 0x37, 183 TxPoll = 0x38, 184 IntrMask = 0x3c, 185 IntrStatus = 0x3e, 186 187 TxConfig = 0x40, 188 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 189 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 190 191 RxConfig = 0x44, 192 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 193 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 194 #define RXCFG_FIFO_SHIFT 13 195 /* No threshold before first PCI xfer */ 196 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 197 #define RX_EARLY_OFF (1 << 11) 198 #define RXCFG_DMA_SHIFT 8 199 /* Unlimited maximum PCI burst. */ 200 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 201 202 Cfg9346 = 0x50, 203 Config0 = 0x51, 204 Config1 = 0x52, 205 Config2 = 0x53, 206 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 207 208 Config3 = 0x54, 209 Config4 = 0x55, 210 Config5 = 0x56, 211 PHYAR = 0x60, 212 PHYstatus = 0x6c, 213 RxMaxSize = 0xda, 214 CPlusCmd = 0xe0, 215 IntrMitigate = 0xe2, 216 217 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 218 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 219 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 220 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 221 222 #define RTL_COALESCE_T_MAX 0x0fU 223 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 224 225 RxDescAddrLow = 0xe4, 226 RxDescAddrHigh = 0xe8, 227 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 228 229 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 230 231 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 232 233 #define TxPacketMax (8064 >> 7) 234 #define EarlySize 0x27 235 236 FuncEvent = 0xf0, 237 FuncEventMask = 0xf4, 238 FuncPresetState = 0xf8, 239 IBCR0 = 0xf8, 240 IBCR2 = 0xf9, 241 IBIMR0 = 0xfa, 242 IBISR0 = 0xfb, 243 FuncForceEvent = 0xfc, 244 }; 245 246 enum rtl8168_8101_registers { 247 CSIDR = 0x64, 248 CSIAR = 0x68, 249 #define CSIAR_FLAG 0x80000000 250 #define CSIAR_WRITE_CMD 0x80000000 251 #define CSIAR_BYTE_ENABLE 0x0000f000 252 #define CSIAR_ADDR_MASK 0x00000fff 253 PMCH = 0x6f, 254 #define D3COLD_NO_PLL_DOWN BIT(7) 255 #define D3HOT_NO_PLL_DOWN BIT(6) 256 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 257 EPHYAR = 0x80, 258 #define EPHYAR_FLAG 0x80000000 259 #define EPHYAR_WRITE_CMD 0x80000000 260 #define EPHYAR_REG_MASK 0x1f 261 #define EPHYAR_REG_SHIFT 16 262 #define EPHYAR_DATA_MASK 0xffff 263 DLLPR = 0xd0, 264 #define PFM_EN (1 << 6) 265 #define TX_10M_PS_EN (1 << 7) 266 DBG_REG = 0xd1, 267 #define FIX_NAK_1 (1 << 4) 268 #define FIX_NAK_2 (1 << 3) 269 TWSI = 0xd2, 270 MCU = 0xd3, 271 #define NOW_IS_OOB (1 << 7) 272 #define TX_EMPTY (1 << 5) 273 #define RX_EMPTY (1 << 4) 274 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 275 #define EN_NDP (1 << 3) 276 #define EN_OOB_RESET (1 << 2) 277 #define LINK_LIST_RDY (1 << 1) 278 EFUSEAR = 0xdc, 279 #define EFUSEAR_FLAG 0x80000000 280 #define EFUSEAR_WRITE_CMD 0x80000000 281 #define EFUSEAR_READ_CMD 0x00000000 282 #define EFUSEAR_REG_MASK 0x03ff 283 #define EFUSEAR_REG_SHIFT 8 284 #define EFUSEAR_DATA_MASK 0xff 285 MISC_1 = 0xf2, 286 #define PFM_D3COLD_EN (1 << 6) 287 }; 288 289 enum rtl8168_registers { 290 LED_FREQ = 0x1a, 291 EEE_LED = 0x1b, 292 ERIDR = 0x70, 293 ERIAR = 0x74, 294 #define ERIAR_FLAG 0x80000000 295 #define ERIAR_WRITE_CMD 0x80000000 296 #define ERIAR_READ_CMD 0x00000000 297 #define ERIAR_ADDR_BYTE_ALIGN 4 298 #define ERIAR_TYPE_SHIFT 16 299 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 300 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 301 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 302 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 303 #define ERIAR_MASK_SHIFT 12 304 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 305 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 306 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 307 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 308 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 309 EPHY_RXER_NUM = 0x7c, 310 OCPDR = 0xb0, /* OCP GPHY access */ 311 #define OCPDR_WRITE_CMD 0x80000000 312 #define OCPDR_READ_CMD 0x00000000 313 #define OCPDR_REG_MASK 0x7f 314 #define OCPDR_GPHY_REG_SHIFT 16 315 #define OCPDR_DATA_MASK 0xffff 316 OCPAR = 0xb4, 317 #define OCPAR_FLAG 0x80000000 318 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 319 #define OCPAR_GPHY_READ_CMD 0x0000f060 320 GPHY_OCP = 0xb8, 321 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 322 MISC = 0xf0, /* 8168e only. */ 323 #define TXPLA_RST (1 << 29) 324 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 325 #define PWM_EN (1 << 22) 326 #define RXDV_GATED_EN (1 << 19) 327 #define EARLY_TALLY_EN (1 << 16) 328 }; 329 330 enum rtl8125_registers { 331 IntrMask_8125 = 0x38, 332 IntrStatus_8125 = 0x3c, 333 TxPoll_8125 = 0x90, 334 MAC0_BKP = 0x19e0, 335 EEE_TXIDLE_TIMER_8125 = 0x6048, 336 }; 337 338 #define RX_VLAN_INNER_8125 BIT(22) 339 #define RX_VLAN_OUTER_8125 BIT(23) 340 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 341 342 #define RX_FETCH_DFLT_8125 (8 << 27) 343 344 enum rtl_register_content { 345 /* InterruptStatusBits */ 346 SYSErr = 0x8000, 347 PCSTimeout = 0x4000, 348 SWInt = 0x0100, 349 TxDescUnavail = 0x0080, 350 RxFIFOOver = 0x0040, 351 LinkChg = 0x0020, 352 RxOverflow = 0x0010, 353 TxErr = 0x0008, 354 TxOK = 0x0004, 355 RxErr = 0x0002, 356 RxOK = 0x0001, 357 358 /* RxStatusDesc */ 359 RxRWT = (1 << 22), 360 RxRES = (1 << 21), 361 RxRUNT = (1 << 20), 362 RxCRC = (1 << 19), 363 364 /* ChipCmdBits */ 365 StopReq = 0x80, 366 CmdReset = 0x10, 367 CmdRxEnb = 0x08, 368 CmdTxEnb = 0x04, 369 RxBufEmpty = 0x01, 370 371 /* TXPoll register p.5 */ 372 HPQ = 0x80, /* Poll cmd on the high prio queue */ 373 NPQ = 0x40, /* Poll cmd on the low prio queue */ 374 FSWInt = 0x01, /* Forced software interrupt */ 375 376 /* Cfg9346Bits */ 377 Cfg9346_Lock = 0x00, 378 Cfg9346_Unlock = 0xc0, 379 380 /* rx_mode_bits */ 381 AcceptErr = 0x20, 382 AcceptRunt = 0x10, 383 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 384 AcceptBroadcast = 0x08, 385 AcceptMulticast = 0x04, 386 AcceptMyPhys = 0x02, 387 AcceptAllPhys = 0x01, 388 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 389 #define RX_CONFIG_ACCEPT_MASK 0x3f 390 391 /* TxConfigBits */ 392 TxInterFrameGapShift = 24, 393 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 394 395 /* Config1 register p.24 */ 396 LEDS1 = (1 << 7), 397 LEDS0 = (1 << 6), 398 Speed_down = (1 << 4), 399 MEMMAP = (1 << 3), 400 IOMAP = (1 << 2), 401 VPD = (1 << 1), 402 PMEnable = (1 << 0), /* Power Management Enable */ 403 404 /* Config2 register p. 25 */ 405 ClkReqEn = (1 << 7), /* Clock Request Enable */ 406 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 407 PCI_Clock_66MHz = 0x01, 408 PCI_Clock_33MHz = 0x00, 409 410 /* Config3 register p.25 */ 411 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 412 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 413 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 414 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 415 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 416 417 /* Config4 register */ 418 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 419 420 /* Config5 register p.27 */ 421 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 422 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 423 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 424 Spi_en = (1 << 3), 425 LanWake = (1 << 1), /* LanWake enable/disable */ 426 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 427 ASPM_en = (1 << 0), /* ASPM enable */ 428 429 /* CPlusCmd p.31 */ 430 EnableBist = (1 << 15), // 8168 8101 431 Mac_dbgo_oe = (1 << 14), // 8168 8101 432 EnAnaPLL = (1 << 14), // 8169 433 Normal_mode = (1 << 13), // unused 434 Force_half_dup = (1 << 12), // 8168 8101 435 Force_rxflow_en = (1 << 11), // 8168 8101 436 Force_txflow_en = (1 << 10), // 8168 8101 437 Cxpl_dbg_sel = (1 << 9), // 8168 8101 438 ASF = (1 << 8), // 8168 8101 439 PktCntrDisable = (1 << 7), // 8168 8101 440 Mac_dbgo_sel = 0x001c, // 8168 441 RxVlan = (1 << 6), 442 RxChkSum = (1 << 5), 443 PCIDAC = (1 << 4), 444 PCIMulRW = (1 << 3), 445 #define INTT_MASK GENMASK(1, 0) 446 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 447 448 /* rtl8169_PHYstatus */ 449 TBI_Enable = 0x80, 450 TxFlowCtrl = 0x40, 451 RxFlowCtrl = 0x20, 452 _1000bpsF = 0x10, 453 _100bps = 0x08, 454 _10bps = 0x04, 455 LinkStatus = 0x02, 456 FullDup = 0x01, 457 458 /* ResetCounterCommand */ 459 CounterReset = 0x1, 460 461 /* DumpCounterCommand */ 462 CounterDump = 0x8, 463 464 /* magic enable v2 */ 465 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 466 }; 467 468 enum rtl_desc_bit { 469 /* First doubleword. */ 470 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 471 RingEnd = (1 << 30), /* End of descriptor ring */ 472 FirstFrag = (1 << 29), /* First segment of a packet */ 473 LastFrag = (1 << 28), /* Final segment of a packet */ 474 }; 475 476 /* Generic case. */ 477 enum rtl_tx_desc_bit { 478 /* First doubleword. */ 479 TD_LSO = (1 << 27), /* Large Send Offload */ 480 #define TD_MSS_MAX 0x07ffu /* MSS value */ 481 482 /* Second doubleword. */ 483 TxVlanTag = (1 << 17), /* Add VLAN tag */ 484 }; 485 486 /* 8169, 8168b and 810x except 8102e. */ 487 enum rtl_tx_desc_bit_0 { 488 /* First doubleword. */ 489 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 490 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 491 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 492 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 493 }; 494 495 /* 8102e, 8168c and beyond. */ 496 enum rtl_tx_desc_bit_1 { 497 /* First doubleword. */ 498 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 499 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 500 #define GTTCPHO_SHIFT 18 501 #define GTTCPHO_MAX 0x7f 502 503 /* Second doubleword. */ 504 #define TCPHO_SHIFT 18 505 #define TCPHO_MAX 0x3ff 506 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 507 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 508 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 509 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 510 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 511 }; 512 513 enum rtl_rx_desc_bit { 514 /* Rx private */ 515 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 516 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 517 518 #define RxProtoUDP (PID1) 519 #define RxProtoTCP (PID0) 520 #define RxProtoIP (PID1 | PID0) 521 #define RxProtoMask RxProtoIP 522 523 IPFail = (1 << 16), /* IP checksum failed */ 524 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 525 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 526 527 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 528 529 RxVlanTag = (1 << 16), /* VLAN tag available */ 530 }; 531 532 #define RTL_GSO_MAX_SIZE_V1 32000 533 #define RTL_GSO_MAX_SEGS_V1 24 534 #define RTL_GSO_MAX_SIZE_V2 64000 535 #define RTL_GSO_MAX_SEGS_V2 64 536 537 struct TxDesc { 538 __le32 opts1; 539 __le32 opts2; 540 __le64 addr; 541 }; 542 543 struct RxDesc { 544 __le32 opts1; 545 __le32 opts2; 546 __le64 addr; 547 }; 548 549 struct ring_info { 550 struct sk_buff *skb; 551 u32 len; 552 }; 553 554 struct rtl8169_counters { 555 __le64 tx_packets; 556 __le64 rx_packets; 557 __le64 tx_errors; 558 __le32 rx_errors; 559 __le16 rx_missed; 560 __le16 align_errors; 561 __le32 tx_one_collision; 562 __le32 tx_multi_collision; 563 __le64 rx_unicast; 564 __le64 rx_broadcast; 565 __le32 rx_multicast; 566 __le16 tx_aborted; 567 __le16 tx_underun; 568 }; 569 570 struct rtl8169_tc_offsets { 571 bool inited; 572 __le64 tx_errors; 573 __le32 tx_multi_collision; 574 __le16 tx_aborted; 575 __le16 rx_missed; 576 }; 577 578 enum rtl_flag { 579 RTL_FLAG_TASK_ENABLED = 0, 580 RTL_FLAG_TASK_RESET_PENDING, 581 RTL_FLAG_MAX 582 }; 583 584 enum rtl_dash_type { 585 RTL_DASH_NONE, 586 RTL_DASH_DP, 587 RTL_DASH_EP, 588 }; 589 590 struct rtl8169_private { 591 void __iomem *mmio_addr; /* memory map physical address */ 592 struct pci_dev *pci_dev; 593 struct net_device *dev; 594 struct phy_device *phydev; 595 struct napi_struct napi; 596 enum mac_version mac_version; 597 enum rtl_dash_type dash_type; 598 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 599 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 600 u32 dirty_tx; 601 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 602 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 603 dma_addr_t TxPhyAddr; 604 dma_addr_t RxPhyAddr; 605 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 606 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 607 u16 cp_cmd; 608 u32 irq_mask; 609 int irq; 610 struct clk *clk; 611 612 struct { 613 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 614 struct work_struct work; 615 } wk; 616 617 unsigned supports_gmii:1; 618 unsigned aspm_manageable:1; 619 dma_addr_t counters_phys_addr; 620 struct rtl8169_counters *counters; 621 struct rtl8169_tc_offsets tc_offset; 622 u32 saved_wolopts; 623 int eee_adv; 624 625 const char *fw_name; 626 struct rtl_fw *rtl_fw; 627 628 u32 ocp_base; 629 }; 630 631 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 632 633 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 634 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 635 MODULE_SOFTDEP("pre: realtek"); 636 MODULE_LICENSE("GPL"); 637 MODULE_FIRMWARE(FIRMWARE_8168D_1); 638 MODULE_FIRMWARE(FIRMWARE_8168D_2); 639 MODULE_FIRMWARE(FIRMWARE_8168E_1); 640 MODULE_FIRMWARE(FIRMWARE_8168E_2); 641 MODULE_FIRMWARE(FIRMWARE_8168E_3); 642 MODULE_FIRMWARE(FIRMWARE_8105E_1); 643 MODULE_FIRMWARE(FIRMWARE_8168F_1); 644 MODULE_FIRMWARE(FIRMWARE_8168F_2); 645 MODULE_FIRMWARE(FIRMWARE_8402_1); 646 MODULE_FIRMWARE(FIRMWARE_8411_1); 647 MODULE_FIRMWARE(FIRMWARE_8411_2); 648 MODULE_FIRMWARE(FIRMWARE_8106E_1); 649 MODULE_FIRMWARE(FIRMWARE_8106E_2); 650 MODULE_FIRMWARE(FIRMWARE_8168G_2); 651 MODULE_FIRMWARE(FIRMWARE_8168G_3); 652 MODULE_FIRMWARE(FIRMWARE_8168H_2); 653 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 654 MODULE_FIRMWARE(FIRMWARE_8107E_2); 655 MODULE_FIRMWARE(FIRMWARE_8125A_3); 656 MODULE_FIRMWARE(FIRMWARE_8125B_2); 657 658 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 659 { 660 return &tp->pci_dev->dev; 661 } 662 663 static void rtl_lock_config_regs(struct rtl8169_private *tp) 664 { 665 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 666 } 667 668 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 669 { 670 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 671 } 672 673 static void rtl_pci_commit(struct rtl8169_private *tp) 674 { 675 /* Read an arbitrary register to commit a preceding PCI write */ 676 RTL_R8(tp, ChipCmd); 677 } 678 679 static bool rtl_is_8125(struct rtl8169_private *tp) 680 { 681 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 682 } 683 684 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 685 { 686 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 687 tp->mac_version != RTL_GIGA_MAC_VER_39 && 688 tp->mac_version <= RTL_GIGA_MAC_VER_53; 689 } 690 691 static bool rtl_supports_eee(struct rtl8169_private *tp) 692 { 693 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 694 tp->mac_version != RTL_GIGA_MAC_VER_37 && 695 tp->mac_version != RTL_GIGA_MAC_VER_39; 696 } 697 698 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 699 { 700 int i; 701 702 for (i = 0; i < ETH_ALEN; i++) 703 mac[i] = RTL_R8(tp, reg + i); 704 } 705 706 struct rtl_cond { 707 bool (*check)(struct rtl8169_private *); 708 const char *msg; 709 }; 710 711 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 712 unsigned long usecs, int n, bool high) 713 { 714 int i; 715 716 for (i = 0; i < n; i++) { 717 if (c->check(tp) == high) 718 return true; 719 fsleep(usecs); 720 } 721 722 if (net_ratelimit()) 723 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 724 c->msg, !high, n, usecs); 725 return false; 726 } 727 728 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 729 const struct rtl_cond *c, 730 unsigned long d, int n) 731 { 732 return rtl_loop_wait(tp, c, d, n, true); 733 } 734 735 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 736 const struct rtl_cond *c, 737 unsigned long d, int n) 738 { 739 return rtl_loop_wait(tp, c, d, n, false); 740 } 741 742 #define DECLARE_RTL_COND(name) \ 743 static bool name ## _check(struct rtl8169_private *); \ 744 \ 745 static const struct rtl_cond name = { \ 746 .check = name ## _check, \ 747 .msg = #name \ 748 }; \ 749 \ 750 static bool name ## _check(struct rtl8169_private *tp) 751 752 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 753 { 754 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 755 if (type == ERIAR_OOB && 756 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 757 tp->mac_version == RTL_GIGA_MAC_VER_53)) 758 *cmd |= 0xf70 << 18; 759 } 760 761 DECLARE_RTL_COND(rtl_eriar_cond) 762 { 763 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 764 } 765 766 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 767 u32 val, int type) 768 { 769 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 770 771 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 772 return; 773 774 RTL_W32(tp, ERIDR, val); 775 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 776 RTL_W32(tp, ERIAR, cmd); 777 778 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 779 } 780 781 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 782 u32 val) 783 { 784 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 785 } 786 787 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 788 { 789 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 790 791 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 792 RTL_W32(tp, ERIAR, cmd); 793 794 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 795 RTL_R32(tp, ERIDR) : ~0; 796 } 797 798 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 799 { 800 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 801 } 802 803 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 804 { 805 u32 val = rtl_eri_read(tp, addr); 806 807 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 808 } 809 810 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 811 { 812 rtl_w0w1_eri(tp, addr, p, 0); 813 } 814 815 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 816 { 817 rtl_w0w1_eri(tp, addr, 0, m); 818 } 819 820 static bool rtl_ocp_reg_failure(u32 reg) 821 { 822 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 823 } 824 825 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 826 { 827 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 828 } 829 830 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 831 { 832 if (rtl_ocp_reg_failure(reg)) 833 return; 834 835 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 836 837 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 838 } 839 840 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 841 { 842 if (rtl_ocp_reg_failure(reg)) 843 return 0; 844 845 RTL_W32(tp, GPHY_OCP, reg << 15); 846 847 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 848 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 849 } 850 851 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 852 { 853 if (rtl_ocp_reg_failure(reg)) 854 return; 855 856 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 857 } 858 859 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 860 { 861 if (rtl_ocp_reg_failure(reg)) 862 return 0; 863 864 RTL_W32(tp, OCPDR, reg << 15); 865 866 return RTL_R32(tp, OCPDR); 867 } 868 869 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 870 u16 set) 871 { 872 u16 data = r8168_mac_ocp_read(tp, reg); 873 874 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 875 } 876 877 /* Work around a hw issue with RTL8168g PHY, the quirk disables 878 * PHY MCU interrupts before PHY power-down. 879 */ 880 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 881 { 882 switch (tp->mac_version) { 883 case RTL_GIGA_MAC_VER_40: 884 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 885 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 886 else 887 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 888 break; 889 default: 890 break; 891 } 892 }; 893 894 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 895 { 896 if (reg == 0x1f) { 897 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 898 return; 899 } 900 901 if (tp->ocp_base != OCP_STD_PHY_BASE) 902 reg -= 0x10; 903 904 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 905 rtl8168g_phy_suspend_quirk(tp, value); 906 907 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 908 } 909 910 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 911 { 912 if (reg == 0x1f) 913 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 914 915 if (tp->ocp_base != OCP_STD_PHY_BASE) 916 reg -= 0x10; 917 918 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 919 } 920 921 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 922 { 923 if (reg == 0x1f) { 924 tp->ocp_base = value << 4; 925 return; 926 } 927 928 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 929 } 930 931 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 932 { 933 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 934 } 935 936 DECLARE_RTL_COND(rtl_phyar_cond) 937 { 938 return RTL_R32(tp, PHYAR) & 0x80000000; 939 } 940 941 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 942 { 943 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 944 945 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 946 /* 947 * According to hardware specs a 20us delay is required after write 948 * complete indication, but before sending next command. 949 */ 950 udelay(20); 951 } 952 953 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 954 { 955 int value; 956 957 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 958 959 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 960 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 961 962 /* 963 * According to hardware specs a 20us delay is required after read 964 * complete indication, but before sending next command. 965 */ 966 udelay(20); 967 968 return value; 969 } 970 971 DECLARE_RTL_COND(rtl_ocpar_cond) 972 { 973 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 974 } 975 976 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 977 978 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 979 { 980 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 981 } 982 983 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 984 { 985 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 986 } 987 988 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 989 { 990 r8168dp_2_mdio_start(tp); 991 992 r8169_mdio_write(tp, reg, value); 993 994 r8168dp_2_mdio_stop(tp); 995 } 996 997 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 998 { 999 int value; 1000 1001 /* Work around issue with chip reporting wrong PHY ID */ 1002 if (reg == MII_PHYSID2) 1003 return 0xc912; 1004 1005 r8168dp_2_mdio_start(tp); 1006 1007 value = r8169_mdio_read(tp, reg); 1008 1009 r8168dp_2_mdio_stop(tp); 1010 1011 return value; 1012 } 1013 1014 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1015 { 1016 switch (tp->mac_version) { 1017 case RTL_GIGA_MAC_VER_28: 1018 case RTL_GIGA_MAC_VER_31: 1019 r8168dp_2_mdio_write(tp, location, val); 1020 break; 1021 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1022 r8168g_mdio_write(tp, location, val); 1023 break; 1024 default: 1025 r8169_mdio_write(tp, location, val); 1026 break; 1027 } 1028 } 1029 1030 static int rtl_readphy(struct rtl8169_private *tp, int location) 1031 { 1032 switch (tp->mac_version) { 1033 case RTL_GIGA_MAC_VER_28: 1034 case RTL_GIGA_MAC_VER_31: 1035 return r8168dp_2_mdio_read(tp, location); 1036 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 1037 return r8168g_mdio_read(tp, location); 1038 default: 1039 return r8169_mdio_read(tp, location); 1040 } 1041 } 1042 1043 DECLARE_RTL_COND(rtl_ephyar_cond) 1044 { 1045 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1046 } 1047 1048 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1049 { 1050 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1051 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1052 1053 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1054 1055 udelay(10); 1056 } 1057 1058 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1059 { 1060 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1061 1062 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1063 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1064 } 1065 1066 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1067 { 1068 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1069 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1070 RTL_R32(tp, OCPDR) : ~0; 1071 } 1072 1073 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1074 { 1075 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1076 } 1077 1078 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1079 u32 data) 1080 { 1081 RTL_W32(tp, OCPDR, data); 1082 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1083 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1084 } 1085 1086 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1087 u32 data) 1088 { 1089 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1090 data, ERIAR_OOB); 1091 } 1092 1093 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1094 { 1095 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1096 1097 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1098 } 1099 1100 #define OOB_CMD_RESET 0x00 1101 #define OOB_CMD_DRIVER_START 0x05 1102 #define OOB_CMD_DRIVER_STOP 0x06 1103 1104 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1105 { 1106 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1107 } 1108 1109 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1110 { 1111 u16 reg; 1112 1113 reg = rtl8168_get_ocp_reg(tp); 1114 1115 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1116 } 1117 1118 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1119 { 1120 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1121 } 1122 1123 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1124 { 1125 return RTL_R8(tp, IBISR0) & 0x20; 1126 } 1127 1128 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1129 { 1130 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1131 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1132 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1133 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1134 } 1135 1136 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1137 { 1138 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1139 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1140 } 1141 1142 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1143 { 1144 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1145 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1146 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1147 } 1148 1149 static void rtl8168_driver_start(struct rtl8169_private *tp) 1150 { 1151 if (tp->dash_type == RTL_DASH_DP) 1152 rtl8168dp_driver_start(tp); 1153 else 1154 rtl8168ep_driver_start(tp); 1155 } 1156 1157 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1158 { 1159 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1160 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1161 } 1162 1163 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1164 { 1165 rtl8168ep_stop_cmac(tp); 1166 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1167 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1168 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1169 } 1170 1171 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1172 { 1173 if (tp->dash_type == RTL_DASH_DP) 1174 rtl8168dp_driver_stop(tp); 1175 else 1176 rtl8168ep_driver_stop(tp); 1177 } 1178 1179 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1180 { 1181 u16 reg = rtl8168_get_ocp_reg(tp); 1182 1183 return r8168dp_ocp_read(tp, reg) & BIT(15); 1184 } 1185 1186 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1187 { 1188 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1189 } 1190 1191 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) 1192 { 1193 switch (tp->mac_version) { 1194 case RTL_GIGA_MAC_VER_28: 1195 case RTL_GIGA_MAC_VER_31: 1196 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE; 1197 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1198 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE; 1199 default: 1200 return RTL_DASH_NONE; 1201 } 1202 } 1203 1204 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1205 { 1206 switch (tp->mac_version) { 1207 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26: 1208 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30: 1209 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37: 1210 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1211 if (enable) 1212 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); 1213 else 1214 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); 1215 break; 1216 default: 1217 break; 1218 } 1219 } 1220 1221 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1222 { 1223 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1224 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1225 } 1226 1227 DECLARE_RTL_COND(rtl_efusear_cond) 1228 { 1229 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1230 } 1231 1232 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1233 { 1234 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1235 1236 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1237 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1238 } 1239 1240 static u32 rtl_get_events(struct rtl8169_private *tp) 1241 { 1242 if (rtl_is_8125(tp)) 1243 return RTL_R32(tp, IntrStatus_8125); 1244 else 1245 return RTL_R16(tp, IntrStatus); 1246 } 1247 1248 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1249 { 1250 if (rtl_is_8125(tp)) 1251 RTL_W32(tp, IntrStatus_8125, bits); 1252 else 1253 RTL_W16(tp, IntrStatus, bits); 1254 } 1255 1256 static void rtl_irq_disable(struct rtl8169_private *tp) 1257 { 1258 if (rtl_is_8125(tp)) 1259 RTL_W32(tp, IntrMask_8125, 0); 1260 else 1261 RTL_W16(tp, IntrMask, 0); 1262 } 1263 1264 static void rtl_irq_enable(struct rtl8169_private *tp) 1265 { 1266 if (rtl_is_8125(tp)) 1267 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1268 else 1269 RTL_W16(tp, IntrMask, tp->irq_mask); 1270 } 1271 1272 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1273 { 1274 rtl_irq_disable(tp); 1275 rtl_ack_events(tp, 0xffffffff); 1276 rtl_pci_commit(tp); 1277 } 1278 1279 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1280 { 1281 struct phy_device *phydev = tp->phydev; 1282 1283 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1284 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1285 if (phydev->speed == SPEED_1000) { 1286 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1287 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1288 } else if (phydev->speed == SPEED_100) { 1289 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1290 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1291 } else { 1292 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1293 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1294 } 1295 rtl_reset_packet_filter(tp); 1296 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1297 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1298 if (phydev->speed == SPEED_1000) { 1299 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1300 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1301 } else { 1302 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1303 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1304 } 1305 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1306 if (phydev->speed == SPEED_10) { 1307 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1308 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1309 } else { 1310 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1311 } 1312 } 1313 } 1314 1315 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1316 1317 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1318 { 1319 struct rtl8169_private *tp = netdev_priv(dev); 1320 1321 wol->supported = WAKE_ANY; 1322 wol->wolopts = tp->saved_wolopts; 1323 } 1324 1325 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1326 { 1327 static const struct { 1328 u32 opt; 1329 u16 reg; 1330 u8 mask; 1331 } cfg[] = { 1332 { WAKE_PHY, Config3, LinkUp }, 1333 { WAKE_UCAST, Config5, UWF }, 1334 { WAKE_BCAST, Config5, BWF }, 1335 { WAKE_MCAST, Config5, MWF }, 1336 { WAKE_ANY, Config5, LanWake }, 1337 { WAKE_MAGIC, Config3, MagicPacket } 1338 }; 1339 unsigned int i, tmp = ARRAY_SIZE(cfg); 1340 u8 options; 1341 1342 rtl_unlock_config_regs(tp); 1343 1344 if (rtl_is_8168evl_up(tp)) { 1345 tmp--; 1346 if (wolopts & WAKE_MAGIC) 1347 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1348 else 1349 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1350 } else if (rtl_is_8125(tp)) { 1351 tmp--; 1352 if (wolopts & WAKE_MAGIC) 1353 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1354 else 1355 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1356 } 1357 1358 for (i = 0; i < tmp; i++) { 1359 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1360 if (wolopts & cfg[i].opt) 1361 options |= cfg[i].mask; 1362 RTL_W8(tp, cfg[i].reg, options); 1363 } 1364 1365 switch (tp->mac_version) { 1366 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1367 options = RTL_R8(tp, Config1) & ~PMEnable; 1368 if (wolopts) 1369 options |= PMEnable; 1370 RTL_W8(tp, Config1, options); 1371 break; 1372 case RTL_GIGA_MAC_VER_34: 1373 case RTL_GIGA_MAC_VER_37: 1374 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63: 1375 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1376 if (wolopts) 1377 options |= PME_SIGNAL; 1378 RTL_W8(tp, Config2, options); 1379 break; 1380 default: 1381 break; 1382 } 1383 1384 rtl_lock_config_regs(tp); 1385 1386 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1387 1388 if (tp->dash_type == RTL_DASH_NONE) { 1389 rtl_set_d3_pll_down(tp, !wolopts); 1390 tp->dev->wol_enabled = wolopts ? 1 : 0; 1391 } 1392 } 1393 1394 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1395 { 1396 struct rtl8169_private *tp = netdev_priv(dev); 1397 1398 if (wol->wolopts & ~WAKE_ANY) 1399 return -EINVAL; 1400 1401 tp->saved_wolopts = wol->wolopts; 1402 __rtl8169_set_wol(tp, tp->saved_wolopts); 1403 1404 return 0; 1405 } 1406 1407 static void rtl8169_get_drvinfo(struct net_device *dev, 1408 struct ethtool_drvinfo *info) 1409 { 1410 struct rtl8169_private *tp = netdev_priv(dev); 1411 struct rtl_fw *rtl_fw = tp->rtl_fw; 1412 1413 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1414 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1415 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1416 if (rtl_fw) 1417 strscpy(info->fw_version, rtl_fw->version, 1418 sizeof(info->fw_version)); 1419 } 1420 1421 static int rtl8169_get_regs_len(struct net_device *dev) 1422 { 1423 return R8169_REGS_SIZE; 1424 } 1425 1426 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1427 netdev_features_t features) 1428 { 1429 struct rtl8169_private *tp = netdev_priv(dev); 1430 1431 if (dev->mtu > TD_MSS_MAX) 1432 features &= ~NETIF_F_ALL_TSO; 1433 1434 if (dev->mtu > ETH_DATA_LEN && 1435 tp->mac_version > RTL_GIGA_MAC_VER_06) 1436 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1437 1438 return features; 1439 } 1440 1441 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1442 netdev_features_t features) 1443 { 1444 u32 rx_config = RTL_R32(tp, RxConfig); 1445 1446 if (features & NETIF_F_RXALL) 1447 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1448 else 1449 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1450 1451 if (rtl_is_8125(tp)) { 1452 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1453 rx_config |= RX_VLAN_8125; 1454 else 1455 rx_config &= ~RX_VLAN_8125; 1456 } 1457 1458 RTL_W32(tp, RxConfig, rx_config); 1459 } 1460 1461 static int rtl8169_set_features(struct net_device *dev, 1462 netdev_features_t features) 1463 { 1464 struct rtl8169_private *tp = netdev_priv(dev); 1465 1466 rtl_set_rx_config_features(tp, features); 1467 1468 if (features & NETIF_F_RXCSUM) 1469 tp->cp_cmd |= RxChkSum; 1470 else 1471 tp->cp_cmd &= ~RxChkSum; 1472 1473 if (!rtl_is_8125(tp)) { 1474 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1475 tp->cp_cmd |= RxVlan; 1476 else 1477 tp->cp_cmd &= ~RxVlan; 1478 } 1479 1480 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1481 rtl_pci_commit(tp); 1482 1483 return 0; 1484 } 1485 1486 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1487 { 1488 return (skb_vlan_tag_present(skb)) ? 1489 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1490 } 1491 1492 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1493 { 1494 u32 opts2 = le32_to_cpu(desc->opts2); 1495 1496 if (opts2 & RxVlanTag) 1497 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1498 } 1499 1500 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1501 void *p) 1502 { 1503 struct rtl8169_private *tp = netdev_priv(dev); 1504 u32 __iomem *data = tp->mmio_addr; 1505 u32 *dw = p; 1506 int i; 1507 1508 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1509 memcpy_fromio(dw++, data++, 4); 1510 } 1511 1512 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1513 "tx_packets", 1514 "rx_packets", 1515 "tx_errors", 1516 "rx_errors", 1517 "rx_missed", 1518 "align_errors", 1519 "tx_single_collisions", 1520 "tx_multi_collisions", 1521 "unicast", 1522 "broadcast", 1523 "multicast", 1524 "tx_aborted", 1525 "tx_underrun", 1526 }; 1527 1528 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1529 { 1530 switch (sset) { 1531 case ETH_SS_STATS: 1532 return ARRAY_SIZE(rtl8169_gstrings); 1533 default: 1534 return -EOPNOTSUPP; 1535 } 1536 } 1537 1538 DECLARE_RTL_COND(rtl_counters_cond) 1539 { 1540 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1541 } 1542 1543 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1544 { 1545 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1546 1547 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1548 rtl_pci_commit(tp); 1549 RTL_W32(tp, CounterAddrLow, cmd); 1550 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1551 1552 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1553 } 1554 1555 static void rtl8169_update_counters(struct rtl8169_private *tp) 1556 { 1557 u8 val = RTL_R8(tp, ChipCmd); 1558 1559 /* 1560 * Some chips are unable to dump tally counters when the receiver 1561 * is disabled. If 0xff chip may be in a PCI power-save state. 1562 */ 1563 if (val & CmdRxEnb && val != 0xff) 1564 rtl8169_do_counters(tp, CounterDump); 1565 } 1566 1567 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1568 { 1569 struct rtl8169_counters *counters = tp->counters; 1570 1571 /* 1572 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1573 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1574 * reset by a power cycle, while the counter values collected by the 1575 * driver are reset at every driver unload/load cycle. 1576 * 1577 * To make sure the HW values returned by @get_stats64 match the SW 1578 * values, we collect the initial values at first open(*) and use them 1579 * as offsets to normalize the values returned by @get_stats64. 1580 * 1581 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1582 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1583 * set at open time by rtl_hw_start. 1584 */ 1585 1586 if (tp->tc_offset.inited) 1587 return; 1588 1589 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1590 rtl8169_do_counters(tp, CounterReset); 1591 } else { 1592 rtl8169_update_counters(tp); 1593 tp->tc_offset.tx_errors = counters->tx_errors; 1594 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1595 tp->tc_offset.tx_aborted = counters->tx_aborted; 1596 tp->tc_offset.rx_missed = counters->rx_missed; 1597 } 1598 1599 tp->tc_offset.inited = true; 1600 } 1601 1602 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1603 struct ethtool_stats *stats, u64 *data) 1604 { 1605 struct rtl8169_private *tp = netdev_priv(dev); 1606 struct rtl8169_counters *counters; 1607 1608 counters = tp->counters; 1609 rtl8169_update_counters(tp); 1610 1611 data[0] = le64_to_cpu(counters->tx_packets); 1612 data[1] = le64_to_cpu(counters->rx_packets); 1613 data[2] = le64_to_cpu(counters->tx_errors); 1614 data[3] = le32_to_cpu(counters->rx_errors); 1615 data[4] = le16_to_cpu(counters->rx_missed); 1616 data[5] = le16_to_cpu(counters->align_errors); 1617 data[6] = le32_to_cpu(counters->tx_one_collision); 1618 data[7] = le32_to_cpu(counters->tx_multi_collision); 1619 data[8] = le64_to_cpu(counters->rx_unicast); 1620 data[9] = le64_to_cpu(counters->rx_broadcast); 1621 data[10] = le32_to_cpu(counters->rx_multicast); 1622 data[11] = le16_to_cpu(counters->tx_aborted); 1623 data[12] = le16_to_cpu(counters->tx_underun); 1624 } 1625 1626 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1627 { 1628 switch(stringset) { 1629 case ETH_SS_STATS: 1630 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1631 break; 1632 } 1633 } 1634 1635 /* 1636 * Interrupt coalescing 1637 * 1638 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1639 * > 8169, 8168 and 810x line of chipsets 1640 * 1641 * 8169, 8168, and 8136(810x) serial chipsets support it. 1642 * 1643 * > 2 - the Tx timer unit at gigabit speed 1644 * 1645 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1646 * (0xe0) bit 1 and bit 0. 1647 * 1648 * For 8169 1649 * bit[1:0] \ speed 1000M 100M 10M 1650 * 0 0 320ns 2.56us 40.96us 1651 * 0 1 2.56us 20.48us 327.7us 1652 * 1 0 5.12us 40.96us 655.4us 1653 * 1 1 10.24us 81.92us 1.31ms 1654 * 1655 * For the other 1656 * bit[1:0] \ speed 1000M 100M 10M 1657 * 0 0 5us 2.56us 40.96us 1658 * 0 1 40us 20.48us 327.7us 1659 * 1 0 80us 40.96us 655.4us 1660 * 1 1 160us 81.92us 1.31ms 1661 */ 1662 1663 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1664 struct rtl_coalesce_info { 1665 u32 speed; 1666 u32 scale_nsecs[4]; 1667 }; 1668 1669 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1670 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1671 1672 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1673 { SPEED_1000, COALESCE_DELAY(320) }, 1674 { SPEED_100, COALESCE_DELAY(2560) }, 1675 { SPEED_10, COALESCE_DELAY(40960) }, 1676 { 0 }, 1677 }; 1678 1679 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1680 { SPEED_1000, COALESCE_DELAY(5000) }, 1681 { SPEED_100, COALESCE_DELAY(2560) }, 1682 { SPEED_10, COALESCE_DELAY(40960) }, 1683 { 0 }, 1684 }; 1685 #undef COALESCE_DELAY 1686 1687 /* get rx/tx scale vector corresponding to current speed */ 1688 static const struct rtl_coalesce_info * 1689 rtl_coalesce_info(struct rtl8169_private *tp) 1690 { 1691 const struct rtl_coalesce_info *ci; 1692 1693 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1694 ci = rtl_coalesce_info_8169; 1695 else 1696 ci = rtl_coalesce_info_8168_8136; 1697 1698 /* if speed is unknown assume highest one */ 1699 if (tp->phydev->speed == SPEED_UNKNOWN) 1700 return ci; 1701 1702 for (; ci->speed; ci++) { 1703 if (tp->phydev->speed == ci->speed) 1704 return ci; 1705 } 1706 1707 return ERR_PTR(-ELNRNG); 1708 } 1709 1710 static int rtl_get_coalesce(struct net_device *dev, 1711 struct ethtool_coalesce *ec, 1712 struct kernel_ethtool_coalesce *kernel_coal, 1713 struct netlink_ext_ack *extack) 1714 { 1715 struct rtl8169_private *tp = netdev_priv(dev); 1716 const struct rtl_coalesce_info *ci; 1717 u32 scale, c_us, c_fr; 1718 u16 intrmit; 1719 1720 if (rtl_is_8125(tp)) 1721 return -EOPNOTSUPP; 1722 1723 memset(ec, 0, sizeof(*ec)); 1724 1725 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1726 ci = rtl_coalesce_info(tp); 1727 if (IS_ERR(ci)) 1728 return PTR_ERR(ci); 1729 1730 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1731 1732 intrmit = RTL_R16(tp, IntrMitigate); 1733 1734 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1735 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1736 1737 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1738 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1739 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1740 1741 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1742 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1743 1744 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1745 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1746 1747 return 0; 1748 } 1749 1750 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1751 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1752 u16 *cp01) 1753 { 1754 const struct rtl_coalesce_info *ci; 1755 u16 i; 1756 1757 ci = rtl_coalesce_info(tp); 1758 if (IS_ERR(ci)) 1759 return PTR_ERR(ci); 1760 1761 for (i = 0; i < 4; i++) { 1762 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1763 *cp01 = i; 1764 return ci->scale_nsecs[i]; 1765 } 1766 } 1767 1768 return -ERANGE; 1769 } 1770 1771 static int rtl_set_coalesce(struct net_device *dev, 1772 struct ethtool_coalesce *ec, 1773 struct kernel_ethtool_coalesce *kernel_coal, 1774 struct netlink_ext_ack *extack) 1775 { 1776 struct rtl8169_private *tp = netdev_priv(dev); 1777 u32 tx_fr = ec->tx_max_coalesced_frames; 1778 u32 rx_fr = ec->rx_max_coalesced_frames; 1779 u32 coal_usec_max, units; 1780 u16 w = 0, cp01 = 0; 1781 int scale; 1782 1783 if (rtl_is_8125(tp)) 1784 return -EOPNOTSUPP; 1785 1786 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1787 return -ERANGE; 1788 1789 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1790 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1791 if (scale < 0) 1792 return scale; 1793 1794 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1795 * not only when usecs=0 because of e.g. the following scenario: 1796 * 1797 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1798 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1799 * - then user does `ethtool -C eth0 rx-usecs 100` 1800 * 1801 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1802 * if we want to ignore rx_frames then it has to be set to 0. 1803 */ 1804 if (rx_fr == 1) 1805 rx_fr = 0; 1806 if (tx_fr == 1) 1807 tx_fr = 0; 1808 1809 /* HW requires time limit to be set if frame limit is set */ 1810 if ((tx_fr && !ec->tx_coalesce_usecs) || 1811 (rx_fr && !ec->rx_coalesce_usecs)) 1812 return -EINVAL; 1813 1814 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1815 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1816 1817 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1818 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1819 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1820 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1821 1822 RTL_W16(tp, IntrMitigate, w); 1823 1824 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1825 if (rtl_is_8168evl_up(tp)) { 1826 if (!rx_fr && !tx_fr) 1827 /* disable packet counter */ 1828 tp->cp_cmd |= PktCntrDisable; 1829 else 1830 tp->cp_cmd &= ~PktCntrDisable; 1831 } 1832 1833 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1834 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1835 rtl_pci_commit(tp); 1836 1837 return 0; 1838 } 1839 1840 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1841 { 1842 struct rtl8169_private *tp = netdev_priv(dev); 1843 1844 if (!rtl_supports_eee(tp)) 1845 return -EOPNOTSUPP; 1846 1847 return phy_ethtool_get_eee(tp->phydev, data); 1848 } 1849 1850 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1851 { 1852 struct rtl8169_private *tp = netdev_priv(dev); 1853 int ret; 1854 1855 if (!rtl_supports_eee(tp)) 1856 return -EOPNOTSUPP; 1857 1858 ret = phy_ethtool_set_eee(tp->phydev, data); 1859 1860 if (!ret) 1861 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1862 MDIO_AN_EEE_ADV); 1863 return ret; 1864 } 1865 1866 static void rtl8169_get_ringparam(struct net_device *dev, 1867 struct ethtool_ringparam *data, 1868 struct kernel_ethtool_ringparam *kernel_data, 1869 struct netlink_ext_ack *extack) 1870 { 1871 data->rx_max_pending = NUM_RX_DESC; 1872 data->rx_pending = NUM_RX_DESC; 1873 data->tx_max_pending = NUM_TX_DESC; 1874 data->tx_pending = NUM_TX_DESC; 1875 } 1876 1877 static void rtl8169_get_pauseparam(struct net_device *dev, 1878 struct ethtool_pauseparam *data) 1879 { 1880 struct rtl8169_private *tp = netdev_priv(dev); 1881 bool tx_pause, rx_pause; 1882 1883 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 1884 1885 data->autoneg = tp->phydev->autoneg; 1886 data->tx_pause = tx_pause ? 1 : 0; 1887 data->rx_pause = rx_pause ? 1 : 0; 1888 } 1889 1890 static int rtl8169_set_pauseparam(struct net_device *dev, 1891 struct ethtool_pauseparam *data) 1892 { 1893 struct rtl8169_private *tp = netdev_priv(dev); 1894 1895 if (dev->mtu > ETH_DATA_LEN) 1896 return -EOPNOTSUPP; 1897 1898 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 1899 1900 return 0; 1901 } 1902 1903 static const struct ethtool_ops rtl8169_ethtool_ops = { 1904 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1905 ETHTOOL_COALESCE_MAX_FRAMES, 1906 .get_drvinfo = rtl8169_get_drvinfo, 1907 .get_regs_len = rtl8169_get_regs_len, 1908 .get_link = ethtool_op_get_link, 1909 .get_coalesce = rtl_get_coalesce, 1910 .set_coalesce = rtl_set_coalesce, 1911 .get_regs = rtl8169_get_regs, 1912 .get_wol = rtl8169_get_wol, 1913 .set_wol = rtl8169_set_wol, 1914 .get_strings = rtl8169_get_strings, 1915 .get_sset_count = rtl8169_get_sset_count, 1916 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1917 .get_ts_info = ethtool_op_get_ts_info, 1918 .nway_reset = phy_ethtool_nway_reset, 1919 .get_eee = rtl8169_get_eee, 1920 .set_eee = rtl8169_set_eee, 1921 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1922 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1923 .get_ringparam = rtl8169_get_ringparam, 1924 .get_pauseparam = rtl8169_get_pauseparam, 1925 .set_pauseparam = rtl8169_set_pauseparam, 1926 }; 1927 1928 static void rtl_enable_eee(struct rtl8169_private *tp) 1929 { 1930 struct phy_device *phydev = tp->phydev; 1931 int adv; 1932 1933 /* respect EEE advertisement the user may have set */ 1934 if (tp->eee_adv >= 0) 1935 adv = tp->eee_adv; 1936 else 1937 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1938 1939 if (adv >= 0) 1940 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1941 } 1942 1943 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1944 { 1945 /* 1946 * The driver currently handles the 8168Bf and the 8168Be identically 1947 * but they can be identified more specifically through the test below 1948 * if needed: 1949 * 1950 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1951 * 1952 * Same thing for the 8101Eb and the 8101Ec: 1953 * 1954 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1955 */ 1956 static const struct rtl_mac_info { 1957 u16 mask; 1958 u16 val; 1959 enum mac_version ver; 1960 } mac_info[] = { 1961 /* 8125B family. */ 1962 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 1963 1964 /* 8125A family. */ 1965 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 1966 /* It seems only XID 609 made it to the mass market. 1967 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1968 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1969 */ 1970 1971 /* RTL8117 */ 1972 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 1973 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1974 1975 /* 8168EP family. */ 1976 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1977 /* It seems this chip version never made it to 1978 * the wild. Let's disable detection. 1979 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1980 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1981 */ 1982 1983 /* 8168H family. */ 1984 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 1985 /* It seems this chip version never made it to 1986 * the wild. Let's disable detection. 1987 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 1988 */ 1989 1990 /* 8168G family. */ 1991 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 1992 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 1993 /* It seems this chip version never made it to 1994 * the wild. Let's disable detection. 1995 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 1996 */ 1997 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 1998 1999 /* 8168F family. */ 2000 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2001 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2002 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2003 2004 /* 8168E family. */ 2005 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2006 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2007 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2008 2009 /* 8168D family. */ 2010 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2011 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2012 2013 /* 8168DP family. */ 2014 /* It seems this early RTL8168dp version never made it to 2015 * the wild. Support has been removed. 2016 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2017 */ 2018 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2019 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2020 2021 /* 8168C family. */ 2022 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2023 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2024 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2025 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2026 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2027 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2028 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2029 2030 /* 8168B family. */ 2031 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2032 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2033 2034 /* 8101 family. */ 2035 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2036 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2037 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2038 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2039 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2040 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2041 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2042 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2043 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2044 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2045 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2046 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2047 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2048 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2049 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2050 2051 /* 8110 family. */ 2052 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2053 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2054 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2055 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2056 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2057 2058 /* Catch-all */ 2059 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2060 }; 2061 const struct rtl_mac_info *p = mac_info; 2062 enum mac_version ver; 2063 2064 while ((xid & p->mask) != p->val) 2065 p++; 2066 ver = p->ver; 2067 2068 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2069 if (ver == RTL_GIGA_MAC_VER_42) 2070 ver = RTL_GIGA_MAC_VER_43; 2071 else if (ver == RTL_GIGA_MAC_VER_46) 2072 ver = RTL_GIGA_MAC_VER_48; 2073 } 2074 2075 return ver; 2076 } 2077 2078 static void rtl_release_firmware(struct rtl8169_private *tp) 2079 { 2080 if (tp->rtl_fw) { 2081 rtl_fw_release_firmware(tp->rtl_fw); 2082 kfree(tp->rtl_fw); 2083 tp->rtl_fw = NULL; 2084 } 2085 } 2086 2087 void r8169_apply_firmware(struct rtl8169_private *tp) 2088 { 2089 int val; 2090 2091 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2092 if (tp->rtl_fw) { 2093 rtl_fw_write_firmware(tp, tp->rtl_fw); 2094 /* At least one firmware doesn't reset tp->ocp_base. */ 2095 tp->ocp_base = OCP_STD_PHY_BASE; 2096 2097 /* PHY soft reset may still be in progress */ 2098 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2099 !(val & BMCR_RESET), 2100 50000, 600000, true); 2101 } 2102 } 2103 2104 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2105 { 2106 /* Adjust EEE LED frequency */ 2107 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2108 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2109 2110 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2111 } 2112 2113 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2114 { 2115 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2116 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2117 } 2118 2119 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp) 2120 { 2121 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20); 2122 } 2123 2124 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2125 { 2126 rtl8125_set_eee_txidle_timer(tp); 2127 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2128 } 2129 2130 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2131 { 2132 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2133 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2134 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2135 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2136 } 2137 2138 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2139 { 2140 u16 data1, data2, ioffset; 2141 2142 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2143 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2144 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2145 2146 ioffset = (data2 >> 1) & 0x7ff8; 2147 ioffset |= data2 & 0x0007; 2148 if (data1 & BIT(7)) 2149 ioffset |= BIT(15); 2150 2151 return ioffset; 2152 } 2153 2154 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2155 { 2156 set_bit(flag, tp->wk.flags); 2157 schedule_work(&tp->wk.work); 2158 } 2159 2160 static void rtl8169_init_phy(struct rtl8169_private *tp) 2161 { 2162 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2163 2164 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2165 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2166 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2167 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2168 RTL_W8(tp, 0x82, 0x01); 2169 } 2170 2171 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2172 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2173 tp->pci_dev->subsystem_device == 0xe000) 2174 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2175 2176 /* We may have called phy_speed_down before */ 2177 phy_speed_up(tp->phydev); 2178 2179 if (rtl_supports_eee(tp)) 2180 rtl_enable_eee(tp); 2181 2182 genphy_soft_reset(tp->phydev); 2183 } 2184 2185 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2186 { 2187 rtl_unlock_config_regs(tp); 2188 2189 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2190 rtl_pci_commit(tp); 2191 2192 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2193 rtl_pci_commit(tp); 2194 2195 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2196 rtl_rar_exgmac_set(tp, addr); 2197 2198 rtl_lock_config_regs(tp); 2199 } 2200 2201 static int rtl_set_mac_address(struct net_device *dev, void *p) 2202 { 2203 struct rtl8169_private *tp = netdev_priv(dev); 2204 int ret; 2205 2206 ret = eth_mac_addr(dev, p); 2207 if (ret) 2208 return ret; 2209 2210 rtl_rar_set(tp, dev->dev_addr); 2211 2212 return 0; 2213 } 2214 2215 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2216 { 2217 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2218 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2219 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2220 } 2221 2222 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2223 { 2224 if (tp->dash_type != RTL_DASH_NONE) 2225 return; 2226 2227 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2228 tp->mac_version == RTL_GIGA_MAC_VER_33) 2229 rtl_ephy_write(tp, 0x19, 0xff64); 2230 2231 if (device_may_wakeup(tp_to_dev(tp))) { 2232 phy_speed_down(tp->phydev, false); 2233 rtl_wol_enable_rx(tp); 2234 } 2235 } 2236 2237 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2238 { 2239 switch (tp->mac_version) { 2240 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2241 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2242 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2243 break; 2244 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2245 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2246 case RTL_GIGA_MAC_VER_38: 2247 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2248 break; 2249 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2250 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2251 break; 2252 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2253 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2254 break; 2255 default: 2256 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2257 break; 2258 } 2259 } 2260 2261 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2262 { 2263 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2264 } 2265 2266 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2267 { 2268 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2269 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2270 } 2271 2272 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2273 { 2274 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2275 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2276 } 2277 2278 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2279 { 2280 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2281 } 2282 2283 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2284 { 2285 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2286 } 2287 2288 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2289 { 2290 RTL_W8(tp, MaxTxPacketSize, 0x24); 2291 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2292 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2293 } 2294 2295 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2296 { 2297 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2298 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2299 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2300 } 2301 2302 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2303 { 2304 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2305 } 2306 2307 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2308 { 2309 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2310 } 2311 2312 static void rtl_jumbo_config(struct rtl8169_private *tp) 2313 { 2314 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2315 int readrq = 4096; 2316 2317 rtl_unlock_config_regs(tp); 2318 switch (tp->mac_version) { 2319 case RTL_GIGA_MAC_VER_17: 2320 if (jumbo) { 2321 readrq = 512; 2322 r8168b_1_hw_jumbo_enable(tp); 2323 } else { 2324 r8168b_1_hw_jumbo_disable(tp); 2325 } 2326 break; 2327 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2328 if (jumbo) { 2329 readrq = 512; 2330 r8168c_hw_jumbo_enable(tp); 2331 } else { 2332 r8168c_hw_jumbo_disable(tp); 2333 } 2334 break; 2335 case RTL_GIGA_MAC_VER_28: 2336 if (jumbo) 2337 r8168dp_hw_jumbo_enable(tp); 2338 else 2339 r8168dp_hw_jumbo_disable(tp); 2340 break; 2341 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2342 if (jumbo) 2343 r8168e_hw_jumbo_enable(tp); 2344 else 2345 r8168e_hw_jumbo_disable(tp); 2346 break; 2347 default: 2348 break; 2349 } 2350 rtl_lock_config_regs(tp); 2351 2352 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2353 pcie_set_readrq(tp->pci_dev, readrq); 2354 2355 /* Chip doesn't support pause in jumbo mode */ 2356 if (jumbo) { 2357 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2358 tp->phydev->advertising); 2359 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2360 tp->phydev->advertising); 2361 phy_start_aneg(tp->phydev); 2362 } 2363 } 2364 2365 DECLARE_RTL_COND(rtl_chipcmd_cond) 2366 { 2367 return RTL_R8(tp, ChipCmd) & CmdReset; 2368 } 2369 2370 static void rtl_hw_reset(struct rtl8169_private *tp) 2371 { 2372 RTL_W8(tp, ChipCmd, CmdReset); 2373 2374 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2375 } 2376 2377 static void rtl_request_firmware(struct rtl8169_private *tp) 2378 { 2379 struct rtl_fw *rtl_fw; 2380 2381 /* firmware loaded already or no firmware available */ 2382 if (tp->rtl_fw || !tp->fw_name) 2383 return; 2384 2385 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2386 if (!rtl_fw) 2387 return; 2388 2389 rtl_fw->phy_write = rtl_writephy; 2390 rtl_fw->phy_read = rtl_readphy; 2391 rtl_fw->mac_mcu_write = mac_mcu_write; 2392 rtl_fw->mac_mcu_read = mac_mcu_read; 2393 rtl_fw->fw_name = tp->fw_name; 2394 rtl_fw->dev = tp_to_dev(tp); 2395 2396 if (rtl_fw_request_firmware(rtl_fw)) 2397 kfree(rtl_fw); 2398 else 2399 tp->rtl_fw = rtl_fw; 2400 } 2401 2402 static void rtl_rx_close(struct rtl8169_private *tp) 2403 { 2404 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2405 } 2406 2407 DECLARE_RTL_COND(rtl_npq_cond) 2408 { 2409 return RTL_R8(tp, TxPoll) & NPQ; 2410 } 2411 2412 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2413 { 2414 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2415 } 2416 2417 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2418 { 2419 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2420 } 2421 2422 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2423 { 2424 /* IntrMitigate has new functionality on RTL8125 */ 2425 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2426 } 2427 2428 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2429 { 2430 switch (tp->mac_version) { 2431 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2432 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2433 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2434 break; 2435 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2436 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2437 break; 2438 case RTL_GIGA_MAC_VER_63: 2439 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2440 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2441 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2442 break; 2443 default: 2444 break; 2445 } 2446 } 2447 2448 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2449 { 2450 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2451 fsleep(2000); 2452 rtl_wait_txrx_fifo_empty(tp); 2453 } 2454 2455 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2456 { 2457 u32 val = TX_DMA_BURST << TxDMAShift | 2458 InterFrameGap << TxInterFrameGapShift; 2459 2460 if (rtl_is_8168evl_up(tp)) 2461 val |= TXCFG_AUTO_FIFO; 2462 2463 RTL_W32(tp, TxConfig, val); 2464 } 2465 2466 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2467 { 2468 /* Low hurts. Let's disable the filtering. */ 2469 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2470 } 2471 2472 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2473 { 2474 /* 2475 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2476 * register to be written before TxDescAddrLow to work. 2477 * Switching from MMIO to I/O access fixes the issue as well. 2478 */ 2479 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2480 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2481 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2482 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2483 } 2484 2485 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2486 { 2487 u32 val; 2488 2489 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2490 val = 0x000fff00; 2491 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2492 val = 0x00ffff00; 2493 else 2494 return; 2495 2496 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2497 val |= 0xff; 2498 2499 RTL_W32(tp, 0x7c, val); 2500 } 2501 2502 static void rtl_set_rx_mode(struct net_device *dev) 2503 { 2504 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2505 /* Multicast hash filter */ 2506 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2507 struct rtl8169_private *tp = netdev_priv(dev); 2508 u32 tmp; 2509 2510 if (dev->flags & IFF_PROMISC) { 2511 rx_mode |= AcceptAllPhys; 2512 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2513 dev->flags & IFF_ALLMULTI || 2514 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2515 /* accept all multicasts */ 2516 } else if (netdev_mc_empty(dev)) { 2517 rx_mode &= ~AcceptMulticast; 2518 } else { 2519 struct netdev_hw_addr *ha; 2520 2521 mc_filter[1] = mc_filter[0] = 0; 2522 netdev_for_each_mc_addr(ha, dev) { 2523 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2524 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2525 } 2526 2527 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2528 tmp = mc_filter[0]; 2529 mc_filter[0] = swab32(mc_filter[1]); 2530 mc_filter[1] = swab32(tmp); 2531 } 2532 } 2533 2534 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2535 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2536 2537 tmp = RTL_R32(tp, RxConfig); 2538 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2539 } 2540 2541 DECLARE_RTL_COND(rtl_csiar_cond) 2542 { 2543 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2544 } 2545 2546 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2547 { 2548 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2549 2550 RTL_W32(tp, CSIDR, value); 2551 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2552 CSIAR_BYTE_ENABLE | func << 16); 2553 2554 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2555 } 2556 2557 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2558 { 2559 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2560 2561 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2562 CSIAR_BYTE_ENABLE); 2563 2564 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2565 RTL_R32(tp, CSIDR) : ~0; 2566 } 2567 2568 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2569 { 2570 struct pci_dev *pdev = tp->pci_dev; 2571 u32 csi; 2572 2573 /* According to Realtek the value at config space address 0x070f 2574 * controls the L0s/L1 entrance latency. We try standard ECAM access 2575 * first and if it fails fall back to CSI. 2576 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2577 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2578 */ 2579 if (pdev->cfg_size > 0x070f && 2580 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2581 return; 2582 2583 netdev_notice_once(tp->dev, 2584 "No native access to PCI extended config space, falling back to CSI\n"); 2585 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2586 rtl_csi_write(tp, 0x070c, csi | val << 24); 2587 } 2588 2589 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2590 { 2591 /* L0 7us, L1 16us */ 2592 rtl_set_aspm_entry_latency(tp, 0x27); 2593 } 2594 2595 struct ephy_info { 2596 unsigned int offset; 2597 u16 mask; 2598 u16 bits; 2599 }; 2600 2601 static void __rtl_ephy_init(struct rtl8169_private *tp, 2602 const struct ephy_info *e, int len) 2603 { 2604 u16 w; 2605 2606 while (len-- > 0) { 2607 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2608 rtl_ephy_write(tp, e->offset, w); 2609 e++; 2610 } 2611 } 2612 2613 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2614 2615 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2616 { 2617 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2618 PCI_EXP_LNKCTL_CLKREQ_EN); 2619 } 2620 2621 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2622 { 2623 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2624 PCI_EXP_LNKCTL_CLKREQ_EN); 2625 } 2626 2627 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2628 { 2629 /* work around an issue when PCI reset occurs during L2/L3 state */ 2630 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2631 } 2632 2633 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2634 { 2635 /* Bits control which events trigger ASPM L1 exit: 2636 * Bit 12: rxdv 2637 * Bit 11: ltr_msg 2638 * Bit 10: txdma_poll 2639 * Bit 9: xadm 2640 * Bit 8: pktavi 2641 * Bit 7: txpla 2642 */ 2643 switch (tp->mac_version) { 2644 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2645 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2646 break; 2647 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2648 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2649 break; 2650 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2651 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2652 break; 2653 default: 2654 break; 2655 } 2656 } 2657 2658 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2659 { 2660 switch (tp->mac_version) { 2661 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2662 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2663 break; 2664 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 2665 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2666 break; 2667 default: 2668 break; 2669 } 2670 } 2671 2672 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2673 { 2674 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2675 if (enable && tp->aspm_manageable) { 2676 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2677 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2678 2679 switch (tp->mac_version) { 2680 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2681 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2682 /* reset ephy tx/rx disable timer */ 2683 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2684 /* chip can trigger L1.2 */ 2685 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2686 break; 2687 default: 2688 break; 2689 } 2690 } else { 2691 switch (tp->mac_version) { 2692 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2693 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 2694 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2695 break; 2696 default: 2697 break; 2698 } 2699 2700 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2701 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2702 } 2703 2704 udelay(10); 2705 } 2706 2707 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2708 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2709 { 2710 /* Usage of dynamic vs. static FIFO is controlled by bit 2711 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2712 */ 2713 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2714 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2715 } 2716 2717 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2718 u8 low, u8 high) 2719 { 2720 /* FIFO thresholds for pause flow control */ 2721 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2722 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2723 } 2724 2725 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2726 { 2727 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2728 } 2729 2730 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2731 { 2732 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2733 2734 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2735 2736 rtl_disable_clock_request(tp); 2737 } 2738 2739 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2740 { 2741 static const struct ephy_info e_info_8168cp[] = { 2742 { 0x01, 0, 0x0001 }, 2743 { 0x02, 0x0800, 0x1000 }, 2744 { 0x03, 0, 0x0042 }, 2745 { 0x06, 0x0080, 0x0000 }, 2746 { 0x07, 0, 0x2000 } 2747 }; 2748 2749 rtl_set_def_aspm_entry_latency(tp); 2750 2751 rtl_ephy_init(tp, e_info_8168cp); 2752 2753 __rtl_hw_start_8168cp(tp); 2754 } 2755 2756 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2757 { 2758 rtl_set_def_aspm_entry_latency(tp); 2759 2760 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2761 } 2762 2763 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2764 { 2765 rtl_set_def_aspm_entry_latency(tp); 2766 2767 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2768 2769 /* Magic. */ 2770 RTL_W8(tp, DBG_REG, 0x20); 2771 } 2772 2773 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2774 { 2775 static const struct ephy_info e_info_8168c_1[] = { 2776 { 0x02, 0x0800, 0x1000 }, 2777 { 0x03, 0, 0x0002 }, 2778 { 0x06, 0x0080, 0x0000 } 2779 }; 2780 2781 rtl_set_def_aspm_entry_latency(tp); 2782 2783 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2784 2785 rtl_ephy_init(tp, e_info_8168c_1); 2786 2787 __rtl_hw_start_8168cp(tp); 2788 } 2789 2790 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2791 { 2792 static const struct ephy_info e_info_8168c_2[] = { 2793 { 0x01, 0, 0x0001 }, 2794 { 0x03, 0x0400, 0x0020 } 2795 }; 2796 2797 rtl_set_def_aspm_entry_latency(tp); 2798 2799 rtl_ephy_init(tp, e_info_8168c_2); 2800 2801 __rtl_hw_start_8168cp(tp); 2802 } 2803 2804 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2805 { 2806 rtl_set_def_aspm_entry_latency(tp); 2807 2808 __rtl_hw_start_8168cp(tp); 2809 } 2810 2811 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2812 { 2813 rtl_set_def_aspm_entry_latency(tp); 2814 2815 rtl_disable_clock_request(tp); 2816 } 2817 2818 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2819 { 2820 static const struct ephy_info e_info_8168d_4[] = { 2821 { 0x0b, 0x0000, 0x0048 }, 2822 { 0x19, 0x0020, 0x0050 }, 2823 { 0x0c, 0x0100, 0x0020 }, 2824 { 0x10, 0x0004, 0x0000 }, 2825 }; 2826 2827 rtl_set_def_aspm_entry_latency(tp); 2828 2829 rtl_ephy_init(tp, e_info_8168d_4); 2830 2831 rtl_enable_clock_request(tp); 2832 } 2833 2834 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2835 { 2836 static const struct ephy_info e_info_8168e_1[] = { 2837 { 0x00, 0x0200, 0x0100 }, 2838 { 0x00, 0x0000, 0x0004 }, 2839 { 0x06, 0x0002, 0x0001 }, 2840 { 0x06, 0x0000, 0x0030 }, 2841 { 0x07, 0x0000, 0x2000 }, 2842 { 0x00, 0x0000, 0x0020 }, 2843 { 0x03, 0x5800, 0x2000 }, 2844 { 0x03, 0x0000, 0x0001 }, 2845 { 0x01, 0x0800, 0x1000 }, 2846 { 0x07, 0x0000, 0x4000 }, 2847 { 0x1e, 0x0000, 0x2000 }, 2848 { 0x19, 0xffff, 0xfe6c }, 2849 { 0x0a, 0x0000, 0x0040 } 2850 }; 2851 2852 rtl_set_def_aspm_entry_latency(tp); 2853 2854 rtl_ephy_init(tp, e_info_8168e_1); 2855 2856 rtl_disable_clock_request(tp); 2857 2858 /* Reset tx FIFO pointer */ 2859 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2860 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2861 2862 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2863 } 2864 2865 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2866 { 2867 static const struct ephy_info e_info_8168e_2[] = { 2868 { 0x09, 0x0000, 0x0080 }, 2869 { 0x19, 0x0000, 0x0224 }, 2870 { 0x00, 0x0000, 0x0004 }, 2871 { 0x0c, 0x3df0, 0x0200 }, 2872 }; 2873 2874 rtl_set_def_aspm_entry_latency(tp); 2875 2876 rtl_ephy_init(tp, e_info_8168e_2); 2877 2878 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2879 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2880 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2881 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2882 rtl_reset_packet_filter(tp); 2883 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2884 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2885 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2886 2887 rtl_disable_clock_request(tp); 2888 2889 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2890 2891 rtl8168_config_eee_mac(tp); 2892 2893 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2894 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2895 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2896 2897 rtl_hw_aspm_clkreq_enable(tp, true); 2898 } 2899 2900 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2901 { 2902 rtl_set_def_aspm_entry_latency(tp); 2903 2904 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2905 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2906 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2907 rtl_reset_packet_filter(tp); 2908 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2909 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2910 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2911 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2912 2913 rtl_disable_clock_request(tp); 2914 2915 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2916 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2917 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2918 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2919 2920 rtl8168_config_eee_mac(tp); 2921 } 2922 2923 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2924 { 2925 static const struct ephy_info e_info_8168f_1[] = { 2926 { 0x06, 0x00c0, 0x0020 }, 2927 { 0x08, 0x0001, 0x0002 }, 2928 { 0x09, 0x0000, 0x0080 }, 2929 { 0x19, 0x0000, 0x0224 }, 2930 { 0x00, 0x0000, 0x0008 }, 2931 { 0x0c, 0x3df0, 0x0200 }, 2932 }; 2933 2934 rtl_hw_start_8168f(tp); 2935 2936 rtl_ephy_init(tp, e_info_8168f_1); 2937 } 2938 2939 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2940 { 2941 static const struct ephy_info e_info_8168f_1[] = { 2942 { 0x06, 0x00c0, 0x0020 }, 2943 { 0x0f, 0xffff, 0x5200 }, 2944 { 0x19, 0x0000, 0x0224 }, 2945 { 0x00, 0x0000, 0x0008 }, 2946 { 0x0c, 0x3df0, 0x0200 }, 2947 }; 2948 2949 rtl_hw_start_8168f(tp); 2950 rtl_pcie_state_l2l3_disable(tp); 2951 2952 rtl_ephy_init(tp, e_info_8168f_1); 2953 } 2954 2955 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2956 { 2957 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2958 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2959 2960 rtl_set_def_aspm_entry_latency(tp); 2961 2962 rtl_reset_packet_filter(tp); 2963 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2964 2965 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2966 2967 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2968 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2969 2970 rtl8168_config_eee_mac(tp); 2971 2972 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2973 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 2974 2975 rtl_pcie_state_l2l3_disable(tp); 2976 } 2977 2978 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 2979 { 2980 static const struct ephy_info e_info_8168g_1[] = { 2981 { 0x00, 0x0008, 0x0000 }, 2982 { 0x0c, 0x3ff0, 0x0820 }, 2983 { 0x1e, 0x0000, 0x0001 }, 2984 { 0x19, 0x8000, 0x0000 } 2985 }; 2986 2987 rtl_hw_start_8168g(tp); 2988 2989 /* disable aspm and clock request before access ephy */ 2990 rtl_hw_aspm_clkreq_enable(tp, false); 2991 rtl_ephy_init(tp, e_info_8168g_1); 2992 rtl_hw_aspm_clkreq_enable(tp, true); 2993 } 2994 2995 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 2996 { 2997 static const struct ephy_info e_info_8168g_2[] = { 2998 { 0x00, 0x0008, 0x0000 }, 2999 { 0x0c, 0x3ff0, 0x0820 }, 3000 { 0x19, 0xffff, 0x7c00 }, 3001 { 0x1e, 0xffff, 0x20eb }, 3002 { 0x0d, 0xffff, 0x1666 }, 3003 { 0x00, 0xffff, 0x10a3 }, 3004 { 0x06, 0xffff, 0xf050 }, 3005 { 0x04, 0x0000, 0x0010 }, 3006 { 0x1d, 0x4000, 0x0000 }, 3007 }; 3008 3009 rtl_hw_start_8168g(tp); 3010 3011 /* disable aspm and clock request before access ephy */ 3012 rtl_hw_aspm_clkreq_enable(tp, false); 3013 rtl_ephy_init(tp, e_info_8168g_2); 3014 } 3015 3016 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3017 { 3018 static const struct ephy_info e_info_8411_2[] = { 3019 { 0x00, 0x0008, 0x0000 }, 3020 { 0x0c, 0x37d0, 0x0820 }, 3021 { 0x1e, 0x0000, 0x0001 }, 3022 { 0x19, 0x8021, 0x0000 }, 3023 { 0x1e, 0x0000, 0x2000 }, 3024 { 0x0d, 0x0100, 0x0200 }, 3025 { 0x00, 0x0000, 0x0080 }, 3026 { 0x06, 0x0000, 0x0010 }, 3027 { 0x04, 0x0000, 0x0010 }, 3028 { 0x1d, 0x0000, 0x4000 }, 3029 }; 3030 3031 rtl_hw_start_8168g(tp); 3032 3033 /* disable aspm and clock request before access ephy */ 3034 rtl_hw_aspm_clkreq_enable(tp, false); 3035 rtl_ephy_init(tp, e_info_8411_2); 3036 3037 /* The following Realtek-provided magic fixes an issue with the RX unit 3038 * getting confused after the PHY having been powered-down. 3039 */ 3040 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3041 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3042 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3043 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3044 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3045 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3046 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3047 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3048 mdelay(3); 3049 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3050 3051 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3052 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3053 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3054 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3055 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3056 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3057 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3058 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3059 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3060 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3061 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3062 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3063 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3064 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3065 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3066 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3067 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3068 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3069 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3070 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3071 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3072 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3073 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3074 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3075 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3076 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3077 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3078 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3079 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3080 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3081 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3082 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3083 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3084 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3085 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3086 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3087 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3088 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3089 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3090 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3091 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3092 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3093 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3094 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3095 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3096 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3097 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3098 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3099 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3100 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3101 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3102 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3103 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3104 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3105 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3106 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3107 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3108 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3109 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3110 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3111 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3112 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3113 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3114 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3115 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3116 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3117 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3118 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3119 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3120 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3121 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3122 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3123 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3124 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3125 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3126 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3127 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3128 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3129 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3130 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3131 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3132 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3133 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3134 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3135 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3136 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3137 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3138 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3139 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3140 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3141 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3142 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3143 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3144 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3145 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3146 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3147 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3148 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3149 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3150 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3151 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3152 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3153 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3154 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3155 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3156 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3157 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3158 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3159 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3160 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3161 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3162 3163 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3164 3165 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3166 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3167 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3168 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3169 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3170 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3171 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3172 3173 rtl_hw_aspm_clkreq_enable(tp, true); 3174 } 3175 3176 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3177 { 3178 static const struct ephy_info e_info_8168h_1[] = { 3179 { 0x1e, 0x0800, 0x0001 }, 3180 { 0x1d, 0x0000, 0x0800 }, 3181 { 0x05, 0xffff, 0x2089 }, 3182 { 0x06, 0xffff, 0x5881 }, 3183 { 0x04, 0xffff, 0x854a }, 3184 { 0x01, 0xffff, 0x068b } 3185 }; 3186 int rg_saw_cnt; 3187 3188 /* disable aspm and clock request before access ephy */ 3189 rtl_hw_aspm_clkreq_enable(tp, false); 3190 rtl_ephy_init(tp, e_info_8168h_1); 3191 3192 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3193 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3194 3195 rtl_set_def_aspm_entry_latency(tp); 3196 3197 rtl_reset_packet_filter(tp); 3198 3199 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3200 3201 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3202 3203 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3204 3205 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3206 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3207 3208 rtl8168_config_eee_mac(tp); 3209 3210 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3211 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3212 3213 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3214 3215 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3216 3217 rtl_pcie_state_l2l3_disable(tp); 3218 3219 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3220 if (rg_saw_cnt > 0) { 3221 u16 sw_cnt_1ms_ini; 3222 3223 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3224 sw_cnt_1ms_ini &= 0x0fff; 3225 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3226 } 3227 3228 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3229 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3230 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3231 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3232 3233 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3234 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3235 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3236 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3237 3238 rtl_hw_aspm_clkreq_enable(tp, true); 3239 } 3240 3241 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3242 { 3243 rtl8168ep_stop_cmac(tp); 3244 3245 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3246 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3247 3248 rtl_set_def_aspm_entry_latency(tp); 3249 3250 rtl_reset_packet_filter(tp); 3251 3252 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3253 3254 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3255 3256 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3257 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3258 3259 rtl8168_config_eee_mac(tp); 3260 3261 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3262 3263 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3264 3265 rtl_pcie_state_l2l3_disable(tp); 3266 } 3267 3268 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3269 { 3270 static const struct ephy_info e_info_8168ep_3[] = { 3271 { 0x00, 0x0000, 0x0080 }, 3272 { 0x0d, 0x0100, 0x0200 }, 3273 { 0x19, 0x8021, 0x0000 }, 3274 { 0x1e, 0x0000, 0x2000 }, 3275 }; 3276 3277 /* disable aspm and clock request before access ephy */ 3278 rtl_hw_aspm_clkreq_enable(tp, false); 3279 rtl_ephy_init(tp, e_info_8168ep_3); 3280 3281 rtl_hw_start_8168ep(tp); 3282 3283 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3284 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3285 3286 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3287 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3288 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3289 3290 rtl_hw_aspm_clkreq_enable(tp, true); 3291 } 3292 3293 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3294 { 3295 static const struct ephy_info e_info_8117[] = { 3296 { 0x19, 0x0040, 0x1100 }, 3297 { 0x59, 0x0040, 0x1100 }, 3298 }; 3299 int rg_saw_cnt; 3300 3301 rtl8168ep_stop_cmac(tp); 3302 3303 /* disable aspm and clock request before access ephy */ 3304 rtl_hw_aspm_clkreq_enable(tp, false); 3305 rtl_ephy_init(tp, e_info_8117); 3306 3307 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3308 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3309 3310 rtl_set_def_aspm_entry_latency(tp); 3311 3312 rtl_reset_packet_filter(tp); 3313 3314 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3315 3316 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3317 3318 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3319 3320 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3321 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3322 3323 rtl8168_config_eee_mac(tp); 3324 3325 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3326 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3327 3328 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3329 3330 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3331 3332 rtl_pcie_state_l2l3_disable(tp); 3333 3334 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3335 if (rg_saw_cnt > 0) { 3336 u16 sw_cnt_1ms_ini; 3337 3338 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3339 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3340 } 3341 3342 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3343 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3344 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3345 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3346 3347 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3348 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3349 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3350 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3351 3352 /* firmware is for MAC only */ 3353 r8169_apply_firmware(tp); 3354 3355 rtl_hw_aspm_clkreq_enable(tp, true); 3356 } 3357 3358 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3359 { 3360 static const struct ephy_info e_info_8102e_1[] = { 3361 { 0x01, 0, 0x6e65 }, 3362 { 0x02, 0, 0x091f }, 3363 { 0x03, 0, 0xc2f9 }, 3364 { 0x06, 0, 0xafb5 }, 3365 { 0x07, 0, 0x0e00 }, 3366 { 0x19, 0, 0xec80 }, 3367 { 0x01, 0, 0x2e65 }, 3368 { 0x01, 0, 0x6e65 } 3369 }; 3370 u8 cfg1; 3371 3372 rtl_set_def_aspm_entry_latency(tp); 3373 3374 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3375 3376 RTL_W8(tp, Config1, 3377 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3378 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3379 3380 cfg1 = RTL_R8(tp, Config1); 3381 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3382 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3383 3384 rtl_ephy_init(tp, e_info_8102e_1); 3385 } 3386 3387 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3388 { 3389 rtl_set_def_aspm_entry_latency(tp); 3390 3391 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3392 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3393 } 3394 3395 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3396 { 3397 rtl_hw_start_8102e_2(tp); 3398 3399 rtl_ephy_write(tp, 0x03, 0xc2f9); 3400 } 3401 3402 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3403 { 3404 static const struct ephy_info e_info_8401[] = { 3405 { 0x01, 0xffff, 0x6fe5 }, 3406 { 0x03, 0xffff, 0x0599 }, 3407 { 0x06, 0xffff, 0xaf25 }, 3408 { 0x07, 0xffff, 0x8e68 }, 3409 }; 3410 3411 rtl_ephy_init(tp, e_info_8401); 3412 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3413 } 3414 3415 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3416 { 3417 static const struct ephy_info e_info_8105e_1[] = { 3418 { 0x07, 0, 0x4000 }, 3419 { 0x19, 0, 0x0200 }, 3420 { 0x19, 0, 0x0020 }, 3421 { 0x1e, 0, 0x2000 }, 3422 { 0x03, 0, 0x0001 }, 3423 { 0x19, 0, 0x0100 }, 3424 { 0x19, 0, 0x0004 }, 3425 { 0x0a, 0, 0x0020 } 3426 }; 3427 3428 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3429 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3430 3431 /* Disable Early Tally Counter */ 3432 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3433 3434 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3435 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3436 3437 rtl_ephy_init(tp, e_info_8105e_1); 3438 3439 rtl_pcie_state_l2l3_disable(tp); 3440 } 3441 3442 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3443 { 3444 rtl_hw_start_8105e_1(tp); 3445 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3446 } 3447 3448 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3449 { 3450 static const struct ephy_info e_info_8402[] = { 3451 { 0x19, 0xffff, 0xff64 }, 3452 { 0x1e, 0, 0x4000 } 3453 }; 3454 3455 rtl_set_def_aspm_entry_latency(tp); 3456 3457 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3458 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3459 3460 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3461 3462 rtl_ephy_init(tp, e_info_8402); 3463 3464 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3465 rtl_reset_packet_filter(tp); 3466 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3467 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3468 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3469 3470 /* disable EEE */ 3471 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3472 3473 rtl_pcie_state_l2l3_disable(tp); 3474 } 3475 3476 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3477 { 3478 rtl_hw_aspm_clkreq_enable(tp, false); 3479 3480 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3481 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3482 3483 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3484 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3485 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3486 3487 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3488 rtl_set_aspm_entry_latency(tp, 0x2f); 3489 3490 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3491 3492 /* disable EEE */ 3493 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3494 3495 rtl_pcie_state_l2l3_disable(tp); 3496 rtl_hw_aspm_clkreq_enable(tp, true); 3497 } 3498 3499 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3500 { 3501 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3502 } 3503 3504 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3505 { 3506 rtl_pcie_state_l2l3_disable(tp); 3507 3508 RTL_W16(tp, 0x382, 0x221b); 3509 RTL_W8(tp, 0x4500, 0); 3510 RTL_W16(tp, 0x4800, 0); 3511 3512 /* disable UPS */ 3513 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3514 3515 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3516 3517 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3518 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3519 3520 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3521 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3522 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3523 3524 /* disable new tx descriptor format */ 3525 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3526 3527 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3528 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3529 else 3530 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3531 3532 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3533 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3534 else 3535 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3536 3537 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3538 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3539 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3540 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3541 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3542 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3543 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3544 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3545 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3546 3547 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3548 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3549 udelay(1); 3550 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3551 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3552 3553 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3554 3555 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3556 3557 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3558 rtl8125b_config_eee_mac(tp); 3559 else 3560 rtl8125a_config_eee_mac(tp); 3561 3562 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3563 udelay(10); 3564 } 3565 3566 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3567 { 3568 static const struct ephy_info e_info_8125a_2[] = { 3569 { 0x04, 0xffff, 0xd000 }, 3570 { 0x0a, 0xffff, 0x8653 }, 3571 { 0x23, 0xffff, 0xab66 }, 3572 { 0x20, 0xffff, 0x9455 }, 3573 { 0x21, 0xffff, 0x99ff }, 3574 { 0x29, 0xffff, 0xfe04 }, 3575 3576 { 0x44, 0xffff, 0xd000 }, 3577 { 0x4a, 0xffff, 0x8653 }, 3578 { 0x63, 0xffff, 0xab66 }, 3579 { 0x60, 0xffff, 0x9455 }, 3580 { 0x61, 0xffff, 0x99ff }, 3581 { 0x69, 0xffff, 0xfe04 }, 3582 }; 3583 3584 rtl_set_def_aspm_entry_latency(tp); 3585 3586 /* disable aspm and clock request before access ephy */ 3587 rtl_hw_aspm_clkreq_enable(tp, false); 3588 rtl_ephy_init(tp, e_info_8125a_2); 3589 3590 rtl_hw_start_8125_common(tp); 3591 rtl_hw_aspm_clkreq_enable(tp, true); 3592 } 3593 3594 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3595 { 3596 static const struct ephy_info e_info_8125b[] = { 3597 { 0x0b, 0xffff, 0xa908 }, 3598 { 0x1e, 0xffff, 0x20eb }, 3599 { 0x4b, 0xffff, 0xa908 }, 3600 { 0x5e, 0xffff, 0x20eb }, 3601 { 0x22, 0x0030, 0x0020 }, 3602 { 0x62, 0x0030, 0x0020 }, 3603 }; 3604 3605 rtl_set_def_aspm_entry_latency(tp); 3606 rtl_hw_aspm_clkreq_enable(tp, false); 3607 3608 rtl_ephy_init(tp, e_info_8125b); 3609 rtl_hw_start_8125_common(tp); 3610 3611 rtl_hw_aspm_clkreq_enable(tp, true); 3612 } 3613 3614 static void rtl_hw_config(struct rtl8169_private *tp) 3615 { 3616 static const rtl_generic_fct hw_configs[] = { 3617 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3618 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3619 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3620 [RTL_GIGA_MAC_VER_10] = NULL, 3621 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3622 [RTL_GIGA_MAC_VER_13] = NULL, 3623 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3624 [RTL_GIGA_MAC_VER_16] = NULL, 3625 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3626 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3627 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3628 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3629 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3630 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3631 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3632 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3633 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3634 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3635 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3636 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3637 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3638 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3639 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3640 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3641 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3642 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3643 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3644 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3645 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3646 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3647 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3648 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3649 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3650 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3651 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3652 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3653 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3654 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3655 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3656 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3657 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3658 }; 3659 3660 if (hw_configs[tp->mac_version]) 3661 hw_configs[tp->mac_version](tp); 3662 } 3663 3664 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3665 { 3666 int i; 3667 3668 /* disable interrupt coalescing */ 3669 for (i = 0xa00; i < 0xb00; i += 4) 3670 RTL_W32(tp, i, 0); 3671 3672 rtl_hw_config(tp); 3673 } 3674 3675 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3676 { 3677 if (rtl_is_8168evl_up(tp)) 3678 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3679 else 3680 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3681 3682 rtl_hw_config(tp); 3683 3684 /* disable interrupt coalescing */ 3685 RTL_W16(tp, IntrMitigate, 0x0000); 3686 } 3687 3688 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3689 { 3690 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3691 3692 tp->cp_cmd |= PCIMulRW; 3693 3694 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3695 tp->mac_version == RTL_GIGA_MAC_VER_03) 3696 tp->cp_cmd |= EnAnaPLL; 3697 3698 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3699 3700 rtl8169_set_magic_reg(tp); 3701 3702 /* disable interrupt coalescing */ 3703 RTL_W16(tp, IntrMitigate, 0x0000); 3704 } 3705 3706 static void rtl_hw_start(struct rtl8169_private *tp) 3707 { 3708 rtl_unlock_config_regs(tp); 3709 3710 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3711 3712 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3713 rtl_hw_start_8169(tp); 3714 else if (rtl_is_8125(tp)) 3715 rtl_hw_start_8125(tp); 3716 else 3717 rtl_hw_start_8168(tp); 3718 3719 rtl_enable_exit_l1(tp); 3720 rtl_set_rx_max_size(tp); 3721 rtl_set_rx_tx_desc_registers(tp); 3722 rtl_lock_config_regs(tp); 3723 3724 rtl_jumbo_config(tp); 3725 3726 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3727 rtl_pci_commit(tp); 3728 3729 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3730 rtl_init_rxcfg(tp); 3731 rtl_set_tx_config_registers(tp); 3732 rtl_set_rx_config_features(tp, tp->dev->features); 3733 rtl_set_rx_mode(tp->dev); 3734 rtl_irq_enable(tp); 3735 } 3736 3737 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3738 { 3739 struct rtl8169_private *tp = netdev_priv(dev); 3740 3741 dev->mtu = new_mtu; 3742 netdev_update_features(dev); 3743 rtl_jumbo_config(tp); 3744 3745 switch (tp->mac_version) { 3746 case RTL_GIGA_MAC_VER_61: 3747 case RTL_GIGA_MAC_VER_63: 3748 rtl8125_set_eee_txidle_timer(tp); 3749 break; 3750 default: 3751 break; 3752 } 3753 3754 return 0; 3755 } 3756 3757 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3758 { 3759 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3760 3761 desc->opts2 = 0; 3762 /* Force memory writes to complete before releasing descriptor */ 3763 dma_wmb(); 3764 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3765 } 3766 3767 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3768 struct RxDesc *desc) 3769 { 3770 struct device *d = tp_to_dev(tp); 3771 int node = dev_to_node(d); 3772 dma_addr_t mapping; 3773 struct page *data; 3774 3775 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3776 if (!data) 3777 return NULL; 3778 3779 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3780 if (unlikely(dma_mapping_error(d, mapping))) { 3781 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3782 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3783 return NULL; 3784 } 3785 3786 desc->addr = cpu_to_le64(mapping); 3787 rtl8169_mark_to_asic(desc); 3788 3789 return data; 3790 } 3791 3792 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3793 { 3794 int i; 3795 3796 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3797 dma_unmap_page(tp_to_dev(tp), 3798 le64_to_cpu(tp->RxDescArray[i].addr), 3799 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3800 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3801 tp->Rx_databuff[i] = NULL; 3802 tp->RxDescArray[i].addr = 0; 3803 tp->RxDescArray[i].opts1 = 0; 3804 } 3805 } 3806 3807 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3808 { 3809 int i; 3810 3811 for (i = 0; i < NUM_RX_DESC; i++) { 3812 struct page *data; 3813 3814 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3815 if (!data) { 3816 rtl8169_rx_clear(tp); 3817 return -ENOMEM; 3818 } 3819 tp->Rx_databuff[i] = data; 3820 } 3821 3822 /* mark as last descriptor in the ring */ 3823 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3824 3825 return 0; 3826 } 3827 3828 static int rtl8169_init_ring(struct rtl8169_private *tp) 3829 { 3830 rtl8169_init_ring_indexes(tp); 3831 3832 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3833 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3834 3835 return rtl8169_rx_fill(tp); 3836 } 3837 3838 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3839 { 3840 struct ring_info *tx_skb = tp->tx_skb + entry; 3841 struct TxDesc *desc = tp->TxDescArray + entry; 3842 3843 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3844 DMA_TO_DEVICE); 3845 memset(desc, 0, sizeof(*desc)); 3846 memset(tx_skb, 0, sizeof(*tx_skb)); 3847 } 3848 3849 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3850 unsigned int n) 3851 { 3852 unsigned int i; 3853 3854 for (i = 0; i < n; i++) { 3855 unsigned int entry = (start + i) % NUM_TX_DESC; 3856 struct ring_info *tx_skb = tp->tx_skb + entry; 3857 unsigned int len = tx_skb->len; 3858 3859 if (len) { 3860 struct sk_buff *skb = tx_skb->skb; 3861 3862 rtl8169_unmap_tx_skb(tp, entry); 3863 if (skb) 3864 dev_consume_skb_any(skb); 3865 } 3866 } 3867 } 3868 3869 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3870 { 3871 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3872 netdev_reset_queue(tp->dev); 3873 } 3874 3875 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down) 3876 { 3877 napi_disable(&tp->napi); 3878 3879 /* Give a racing hard_start_xmit a few cycles to complete. */ 3880 synchronize_net(); 3881 3882 /* Disable interrupts */ 3883 rtl8169_irq_mask_and_ack(tp); 3884 3885 rtl_rx_close(tp); 3886 3887 if (going_down && tp->dev->wol_enabled) 3888 goto no_reset; 3889 3890 switch (tp->mac_version) { 3891 case RTL_GIGA_MAC_VER_28: 3892 case RTL_GIGA_MAC_VER_31: 3893 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3894 break; 3895 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3896 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3897 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3898 break; 3899 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63: 3900 rtl_enable_rxdvgate(tp); 3901 fsleep(2000); 3902 break; 3903 default: 3904 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3905 fsleep(100); 3906 break; 3907 } 3908 3909 rtl_hw_reset(tp); 3910 no_reset: 3911 rtl8169_tx_clear(tp); 3912 rtl8169_init_ring_indexes(tp); 3913 } 3914 3915 static void rtl_reset_work(struct rtl8169_private *tp) 3916 { 3917 int i; 3918 3919 netif_stop_queue(tp->dev); 3920 3921 rtl8169_cleanup(tp, false); 3922 3923 for (i = 0; i < NUM_RX_DESC; i++) 3924 rtl8169_mark_to_asic(tp->RxDescArray + i); 3925 3926 napi_enable(&tp->napi); 3927 rtl_hw_start(tp); 3928 } 3929 3930 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3931 { 3932 struct rtl8169_private *tp = netdev_priv(dev); 3933 3934 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3935 } 3936 3937 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3938 void *addr, unsigned int entry, bool desc_own) 3939 { 3940 struct TxDesc *txd = tp->TxDescArray + entry; 3941 struct device *d = tp_to_dev(tp); 3942 dma_addr_t mapping; 3943 u32 opts1; 3944 int ret; 3945 3946 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3947 ret = dma_mapping_error(d, mapping); 3948 if (unlikely(ret)) { 3949 if (net_ratelimit()) 3950 netdev_err(tp->dev, "Failed to map TX data!\n"); 3951 return ret; 3952 } 3953 3954 txd->addr = cpu_to_le64(mapping); 3955 txd->opts2 = cpu_to_le32(opts[1]); 3956 3957 opts1 = opts[0] | len; 3958 if (entry == NUM_TX_DESC - 1) 3959 opts1 |= RingEnd; 3960 if (desc_own) 3961 opts1 |= DescOwn; 3962 txd->opts1 = cpu_to_le32(opts1); 3963 3964 tp->tx_skb[entry].len = len; 3965 3966 return 0; 3967 } 3968 3969 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 3970 const u32 *opts, unsigned int entry) 3971 { 3972 struct skb_shared_info *info = skb_shinfo(skb); 3973 unsigned int cur_frag; 3974 3975 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 3976 const skb_frag_t *frag = info->frags + cur_frag; 3977 void *addr = skb_frag_address(frag); 3978 u32 len = skb_frag_size(frag); 3979 3980 entry = (entry + 1) % NUM_TX_DESC; 3981 3982 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 3983 goto err_out; 3984 } 3985 3986 return 0; 3987 3988 err_out: 3989 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 3990 return -EIO; 3991 } 3992 3993 static bool rtl_skb_is_udp(struct sk_buff *skb) 3994 { 3995 int no = skb_network_offset(skb); 3996 struct ipv6hdr *i6h, _i6h; 3997 struct iphdr *ih, _ih; 3998 3999 switch (vlan_get_protocol(skb)) { 4000 case htons(ETH_P_IP): 4001 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4002 return ih && ih->protocol == IPPROTO_UDP; 4003 case htons(ETH_P_IPV6): 4004 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4005 return i6h && i6h->nexthdr == IPPROTO_UDP; 4006 default: 4007 return false; 4008 } 4009 } 4010 4011 #define RTL_MIN_PATCH_LEN 47 4012 4013 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4014 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4015 struct sk_buff *skb) 4016 { 4017 unsigned int padto = 0, len = skb->len; 4018 4019 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && 4020 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) { 4021 unsigned int trans_data_len = skb_tail_pointer(skb) - 4022 skb_transport_header(skb); 4023 4024 if (trans_data_len >= offsetof(struct udphdr, len) && 4025 trans_data_len < RTL_MIN_PATCH_LEN) { 4026 u16 dest = ntohs(udp_hdr(skb)->dest); 4027 4028 /* dest is a standard PTP port */ 4029 if (dest == 319 || dest == 320) 4030 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4031 } 4032 4033 if (trans_data_len < sizeof(struct udphdr)) 4034 padto = max_t(unsigned int, padto, 4035 len + sizeof(struct udphdr) - trans_data_len); 4036 } 4037 4038 return padto; 4039 } 4040 4041 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4042 struct sk_buff *skb) 4043 { 4044 unsigned int padto; 4045 4046 padto = rtl8125_quirk_udp_padto(tp, skb); 4047 4048 switch (tp->mac_version) { 4049 case RTL_GIGA_MAC_VER_34: 4050 case RTL_GIGA_MAC_VER_61: 4051 case RTL_GIGA_MAC_VER_63: 4052 padto = max_t(unsigned int, padto, ETH_ZLEN); 4053 break; 4054 default: 4055 break; 4056 } 4057 4058 return padto; 4059 } 4060 4061 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4062 { 4063 u32 mss = skb_shinfo(skb)->gso_size; 4064 4065 if (mss) { 4066 opts[0] |= TD_LSO; 4067 opts[0] |= mss << TD0_MSS_SHIFT; 4068 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4069 const struct iphdr *ip = ip_hdr(skb); 4070 4071 if (ip->protocol == IPPROTO_TCP) 4072 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4073 else if (ip->protocol == IPPROTO_UDP) 4074 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4075 else 4076 WARN_ON_ONCE(1); 4077 } 4078 } 4079 4080 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4081 struct sk_buff *skb, u32 *opts) 4082 { 4083 struct skb_shared_info *shinfo = skb_shinfo(skb); 4084 u32 mss = shinfo->gso_size; 4085 4086 if (mss) { 4087 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4088 opts[0] |= TD1_GTSENV4; 4089 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4090 if (skb_cow_head(skb, 0)) 4091 return false; 4092 4093 tcp_v6_gso_csum_prep(skb); 4094 opts[0] |= TD1_GTSENV6; 4095 } else { 4096 WARN_ON_ONCE(1); 4097 } 4098 4099 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4100 opts[1] |= mss << TD1_MSS_SHIFT; 4101 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4102 u8 ip_protocol; 4103 4104 switch (vlan_get_protocol(skb)) { 4105 case htons(ETH_P_IP): 4106 opts[1] |= TD1_IPv4_CS; 4107 ip_protocol = ip_hdr(skb)->protocol; 4108 break; 4109 4110 case htons(ETH_P_IPV6): 4111 opts[1] |= TD1_IPv6_CS; 4112 ip_protocol = ipv6_hdr(skb)->nexthdr; 4113 break; 4114 4115 default: 4116 ip_protocol = IPPROTO_RAW; 4117 break; 4118 } 4119 4120 if (ip_protocol == IPPROTO_TCP) 4121 opts[1] |= TD1_TCP_CS; 4122 else if (ip_protocol == IPPROTO_UDP) 4123 opts[1] |= TD1_UDP_CS; 4124 else 4125 WARN_ON_ONCE(1); 4126 4127 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4128 } else { 4129 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4130 4131 /* skb_padto would free the skb on error */ 4132 return !__skb_put_padto(skb, padto, false); 4133 } 4134 4135 return true; 4136 } 4137 4138 static bool rtl_tx_slots_avail(struct rtl8169_private *tp) 4139 { 4140 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC 4141 - READ_ONCE(tp->cur_tx); 4142 4143 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4144 return slots_avail > MAX_SKB_FRAGS; 4145 } 4146 4147 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4148 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4149 { 4150 switch (tp->mac_version) { 4151 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4152 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4153 return false; 4154 default: 4155 return true; 4156 } 4157 } 4158 4159 static void rtl8169_doorbell(struct rtl8169_private *tp) 4160 { 4161 if (rtl_is_8125(tp)) 4162 RTL_W16(tp, TxPoll_8125, BIT(0)); 4163 else 4164 RTL_W8(tp, TxPoll, NPQ); 4165 } 4166 4167 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4168 struct net_device *dev) 4169 { 4170 unsigned int frags = skb_shinfo(skb)->nr_frags; 4171 struct rtl8169_private *tp = netdev_priv(dev); 4172 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4173 struct TxDesc *txd_first, *txd_last; 4174 bool stop_queue, door_bell; 4175 u32 opts[2]; 4176 4177 if (unlikely(!rtl_tx_slots_avail(tp))) { 4178 if (net_ratelimit()) 4179 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4180 goto err_stop_0; 4181 } 4182 4183 opts[1] = rtl8169_tx_vlan_tag(skb); 4184 opts[0] = 0; 4185 4186 if (!rtl_chip_supports_csum_v2(tp)) 4187 rtl8169_tso_csum_v1(skb, opts); 4188 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4189 goto err_dma_0; 4190 4191 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4192 entry, false))) 4193 goto err_dma_0; 4194 4195 txd_first = tp->TxDescArray + entry; 4196 4197 if (frags) { 4198 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4199 goto err_dma_1; 4200 entry = (entry + frags) % NUM_TX_DESC; 4201 } 4202 4203 txd_last = tp->TxDescArray + entry; 4204 txd_last->opts1 |= cpu_to_le32(LastFrag); 4205 tp->tx_skb[entry].skb = skb; 4206 4207 skb_tx_timestamp(skb); 4208 4209 /* Force memory writes to complete before releasing descriptor */ 4210 dma_wmb(); 4211 4212 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4213 4214 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4215 4216 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4217 smp_wmb(); 4218 4219 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4220 4221 stop_queue = !rtl_tx_slots_avail(tp); 4222 if (unlikely(stop_queue)) { 4223 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4224 * not miss a ring update when it notices a stopped queue. 4225 */ 4226 smp_wmb(); 4227 netif_stop_queue(dev); 4228 /* Sync with rtl_tx: 4229 * - publish queue status and cur_tx ring index (write barrier) 4230 * - refresh dirty_tx ring index (read barrier). 4231 * May the current thread have a pessimistic view of the ring 4232 * status and forget to wake up queue, a racing rtl_tx thread 4233 * can't. 4234 */ 4235 smp_mb__after_atomic(); 4236 if (rtl_tx_slots_avail(tp)) 4237 netif_start_queue(dev); 4238 door_bell = true; 4239 } 4240 4241 if (door_bell) 4242 rtl8169_doorbell(tp); 4243 4244 return NETDEV_TX_OK; 4245 4246 err_dma_1: 4247 rtl8169_unmap_tx_skb(tp, entry); 4248 err_dma_0: 4249 dev_kfree_skb_any(skb); 4250 dev->stats.tx_dropped++; 4251 return NETDEV_TX_OK; 4252 4253 err_stop_0: 4254 netif_stop_queue(dev); 4255 dev->stats.tx_dropped++; 4256 return NETDEV_TX_BUSY; 4257 } 4258 4259 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4260 { 4261 struct skb_shared_info *info = skb_shinfo(skb); 4262 unsigned int nr_frags = info->nr_frags; 4263 4264 if (!nr_frags) 4265 return UINT_MAX; 4266 4267 return skb_frag_size(info->frags + nr_frags - 1); 4268 } 4269 4270 /* Workaround for hw issues with TSO on RTL8168evl */ 4271 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4272 netdev_features_t features) 4273 { 4274 /* IPv4 header has options field */ 4275 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4276 ip_hdrlen(skb) > sizeof(struct iphdr)) 4277 features &= ~NETIF_F_ALL_TSO; 4278 4279 /* IPv4 TCP header has options field */ 4280 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4281 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4282 features &= ~NETIF_F_ALL_TSO; 4283 4284 else if (rtl_last_frag_len(skb) <= 6) 4285 features &= ~NETIF_F_ALL_TSO; 4286 4287 return features; 4288 } 4289 4290 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4291 struct net_device *dev, 4292 netdev_features_t features) 4293 { 4294 struct rtl8169_private *tp = netdev_priv(dev); 4295 4296 if (skb_is_gso(skb)) { 4297 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4298 features = rtl8168evl_fix_tso(skb, features); 4299 4300 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4301 rtl_chip_supports_csum_v2(tp)) 4302 features &= ~NETIF_F_ALL_TSO; 4303 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4304 /* work around hw bug on some chip versions */ 4305 if (skb->len < ETH_ZLEN) 4306 features &= ~NETIF_F_CSUM_MASK; 4307 4308 if (rtl_quirk_packet_padto(tp, skb)) 4309 features &= ~NETIF_F_CSUM_MASK; 4310 4311 if (skb_transport_offset(skb) > TCPHO_MAX && 4312 rtl_chip_supports_csum_v2(tp)) 4313 features &= ~NETIF_F_CSUM_MASK; 4314 } 4315 4316 return vlan_features_check(skb, features); 4317 } 4318 4319 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4320 { 4321 struct rtl8169_private *tp = netdev_priv(dev); 4322 struct pci_dev *pdev = tp->pci_dev; 4323 int pci_status_errs; 4324 u16 pci_cmd; 4325 4326 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4327 4328 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4329 4330 if (net_ratelimit()) 4331 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4332 pci_cmd, pci_status_errs); 4333 4334 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4335 } 4336 4337 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4338 int budget) 4339 { 4340 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4341 struct sk_buff *skb; 4342 4343 dirty_tx = tp->dirty_tx; 4344 4345 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4346 unsigned int entry = dirty_tx % NUM_TX_DESC; 4347 u32 status; 4348 4349 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4350 if (status & DescOwn) 4351 break; 4352 4353 skb = tp->tx_skb[entry].skb; 4354 rtl8169_unmap_tx_skb(tp, entry); 4355 4356 if (skb) { 4357 pkts_compl++; 4358 bytes_compl += skb->len; 4359 napi_consume_skb(skb, budget); 4360 } 4361 dirty_tx++; 4362 } 4363 4364 if (tp->dirty_tx != dirty_tx) { 4365 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4366 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4367 4368 /* Sync with rtl8169_start_xmit: 4369 * - publish dirty_tx ring index (write barrier) 4370 * - refresh cur_tx ring index and queue status (read barrier) 4371 * May the current thread miss the stopped queue condition, 4372 * a racing xmit thread can only have a right view of the 4373 * ring status. 4374 */ 4375 smp_store_mb(tp->dirty_tx, dirty_tx); 4376 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp)) 4377 netif_wake_queue(dev); 4378 /* 4379 * 8168 hack: TxPoll requests are lost when the Tx packets are 4380 * too close. Let's kick an extra TxPoll request when a burst 4381 * of start_xmit activity is detected (if it is not detected, 4382 * it is slow enough). -- FR 4383 * If skb is NULL then we come here again once a tx irq is 4384 * triggered after the last fragment is marked transmitted. 4385 */ 4386 if (tp->cur_tx != dirty_tx && skb) 4387 rtl8169_doorbell(tp); 4388 } 4389 } 4390 4391 static inline int rtl8169_fragmented_frame(u32 status) 4392 { 4393 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4394 } 4395 4396 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4397 { 4398 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4399 4400 if (status == RxProtoTCP || status == RxProtoUDP) 4401 skb->ip_summed = CHECKSUM_UNNECESSARY; 4402 else 4403 skb_checksum_none_assert(skb); 4404 } 4405 4406 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4407 { 4408 struct device *d = tp_to_dev(tp); 4409 int count; 4410 4411 for (count = 0; count < budget; count++, tp->cur_rx++) { 4412 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4413 struct RxDesc *desc = tp->RxDescArray + entry; 4414 struct sk_buff *skb; 4415 const void *rx_buf; 4416 dma_addr_t addr; 4417 u32 status; 4418 4419 status = le32_to_cpu(desc->opts1); 4420 if (status & DescOwn) 4421 break; 4422 4423 /* This barrier is needed to keep us from reading 4424 * any other fields out of the Rx descriptor until 4425 * we know the status of DescOwn 4426 */ 4427 dma_rmb(); 4428 4429 if (unlikely(status & RxRES)) { 4430 if (net_ratelimit()) 4431 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4432 status); 4433 dev->stats.rx_errors++; 4434 if (status & (RxRWT | RxRUNT)) 4435 dev->stats.rx_length_errors++; 4436 if (status & RxCRC) 4437 dev->stats.rx_crc_errors++; 4438 4439 if (!(dev->features & NETIF_F_RXALL)) 4440 goto release_descriptor; 4441 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4442 goto release_descriptor; 4443 } 4444 4445 pkt_size = status & GENMASK(13, 0); 4446 if (likely(!(dev->features & NETIF_F_RXFCS))) 4447 pkt_size -= ETH_FCS_LEN; 4448 4449 /* The driver does not support incoming fragmented frames. 4450 * They are seen as a symptom of over-mtu sized frames. 4451 */ 4452 if (unlikely(rtl8169_fragmented_frame(status))) { 4453 dev->stats.rx_dropped++; 4454 dev->stats.rx_length_errors++; 4455 goto release_descriptor; 4456 } 4457 4458 skb = napi_alloc_skb(&tp->napi, pkt_size); 4459 if (unlikely(!skb)) { 4460 dev->stats.rx_dropped++; 4461 goto release_descriptor; 4462 } 4463 4464 addr = le64_to_cpu(desc->addr); 4465 rx_buf = page_address(tp->Rx_databuff[entry]); 4466 4467 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4468 prefetch(rx_buf); 4469 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4470 skb->tail += pkt_size; 4471 skb->len = pkt_size; 4472 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4473 4474 rtl8169_rx_csum(skb, status); 4475 skb->protocol = eth_type_trans(skb, dev); 4476 4477 rtl8169_rx_vlan_tag(desc, skb); 4478 4479 if (skb->pkt_type == PACKET_MULTICAST) 4480 dev->stats.multicast++; 4481 4482 napi_gro_receive(&tp->napi, skb); 4483 4484 dev_sw_netstats_rx_add(dev, pkt_size); 4485 release_descriptor: 4486 rtl8169_mark_to_asic(desc); 4487 } 4488 4489 return count; 4490 } 4491 4492 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4493 { 4494 struct rtl8169_private *tp = dev_instance; 4495 u32 status = rtl_get_events(tp); 4496 4497 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4498 return IRQ_NONE; 4499 4500 if (unlikely(status & SYSErr)) { 4501 rtl8169_pcierr_interrupt(tp->dev); 4502 goto out; 4503 } 4504 4505 if (status & LinkChg) 4506 phy_mac_interrupt(tp->phydev); 4507 4508 if (unlikely(status & RxFIFOOver && 4509 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4510 netif_stop_queue(tp->dev); 4511 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4512 } 4513 4514 if (napi_schedule_prep(&tp->napi)) { 4515 rtl_irq_disable(tp); 4516 __napi_schedule(&tp->napi); 4517 } 4518 out: 4519 rtl_ack_events(tp, status); 4520 4521 return IRQ_HANDLED; 4522 } 4523 4524 static void rtl_task(struct work_struct *work) 4525 { 4526 struct rtl8169_private *tp = 4527 container_of(work, struct rtl8169_private, wk.work); 4528 4529 rtnl_lock(); 4530 4531 if (!netif_running(tp->dev) || 4532 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4533 goto out_unlock; 4534 4535 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4536 rtl_reset_work(tp); 4537 netif_wake_queue(tp->dev); 4538 } 4539 out_unlock: 4540 rtnl_unlock(); 4541 } 4542 4543 static int rtl8169_poll(struct napi_struct *napi, int budget) 4544 { 4545 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4546 struct net_device *dev = tp->dev; 4547 int work_done; 4548 4549 rtl_tx(dev, tp, budget); 4550 4551 work_done = rtl_rx(dev, tp, budget); 4552 4553 if (work_done < budget && napi_complete_done(napi, work_done)) 4554 rtl_irq_enable(tp); 4555 4556 return work_done; 4557 } 4558 4559 static void r8169_phylink_handler(struct net_device *ndev) 4560 { 4561 struct rtl8169_private *tp = netdev_priv(ndev); 4562 4563 if (netif_carrier_ok(ndev)) { 4564 rtl_link_chg_patch(tp); 4565 pm_request_resume(&tp->pci_dev->dev); 4566 } else { 4567 pm_runtime_idle(&tp->pci_dev->dev); 4568 } 4569 4570 phy_print_status(tp->phydev); 4571 } 4572 4573 static int r8169_phy_connect(struct rtl8169_private *tp) 4574 { 4575 struct phy_device *phydev = tp->phydev; 4576 phy_interface_t phy_mode; 4577 int ret; 4578 4579 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4580 PHY_INTERFACE_MODE_MII; 4581 4582 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4583 phy_mode); 4584 if (ret) 4585 return ret; 4586 4587 if (!tp->supports_gmii) 4588 phy_set_max_speed(phydev, SPEED_100); 4589 4590 phy_attached_info(phydev); 4591 4592 return 0; 4593 } 4594 4595 static void rtl8169_down(struct rtl8169_private *tp) 4596 { 4597 /* Clear all task flags */ 4598 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4599 4600 phy_stop(tp->phydev); 4601 4602 rtl8169_update_counters(tp); 4603 4604 pci_clear_master(tp->pci_dev); 4605 rtl_pci_commit(tp); 4606 4607 rtl8169_cleanup(tp, true); 4608 rtl_disable_exit_l1(tp); 4609 rtl_prepare_power_down(tp); 4610 } 4611 4612 static void rtl8169_up(struct rtl8169_private *tp) 4613 { 4614 pci_set_master(tp->pci_dev); 4615 phy_init_hw(tp->phydev); 4616 phy_resume(tp->phydev); 4617 rtl8169_init_phy(tp); 4618 napi_enable(&tp->napi); 4619 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4620 rtl_reset_work(tp); 4621 4622 phy_start(tp->phydev); 4623 } 4624 4625 static int rtl8169_close(struct net_device *dev) 4626 { 4627 struct rtl8169_private *tp = netdev_priv(dev); 4628 struct pci_dev *pdev = tp->pci_dev; 4629 4630 pm_runtime_get_sync(&pdev->dev); 4631 4632 netif_stop_queue(dev); 4633 rtl8169_down(tp); 4634 rtl8169_rx_clear(tp); 4635 4636 cancel_work_sync(&tp->wk.work); 4637 4638 free_irq(tp->irq, tp); 4639 4640 phy_disconnect(tp->phydev); 4641 4642 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4643 tp->RxPhyAddr); 4644 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4645 tp->TxPhyAddr); 4646 tp->TxDescArray = NULL; 4647 tp->RxDescArray = NULL; 4648 4649 pm_runtime_put_sync(&pdev->dev); 4650 4651 return 0; 4652 } 4653 4654 #ifdef CONFIG_NET_POLL_CONTROLLER 4655 static void rtl8169_netpoll(struct net_device *dev) 4656 { 4657 struct rtl8169_private *tp = netdev_priv(dev); 4658 4659 rtl8169_interrupt(tp->irq, tp); 4660 } 4661 #endif 4662 4663 static int rtl_open(struct net_device *dev) 4664 { 4665 struct rtl8169_private *tp = netdev_priv(dev); 4666 struct pci_dev *pdev = tp->pci_dev; 4667 unsigned long irqflags; 4668 int retval = -ENOMEM; 4669 4670 pm_runtime_get_sync(&pdev->dev); 4671 4672 /* 4673 * Rx and Tx descriptors needs 256 bytes alignment. 4674 * dma_alloc_coherent provides more. 4675 */ 4676 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4677 &tp->TxPhyAddr, GFP_KERNEL); 4678 if (!tp->TxDescArray) 4679 goto out; 4680 4681 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4682 &tp->RxPhyAddr, GFP_KERNEL); 4683 if (!tp->RxDescArray) 4684 goto err_free_tx_0; 4685 4686 retval = rtl8169_init_ring(tp); 4687 if (retval < 0) 4688 goto err_free_rx_1; 4689 4690 rtl_request_firmware(tp); 4691 4692 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4693 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4694 if (retval < 0) 4695 goto err_release_fw_2; 4696 4697 retval = r8169_phy_connect(tp); 4698 if (retval) 4699 goto err_free_irq; 4700 4701 rtl8169_up(tp); 4702 rtl8169_init_counter_offsets(tp); 4703 netif_start_queue(dev); 4704 out: 4705 pm_runtime_put_sync(&pdev->dev); 4706 4707 return retval; 4708 4709 err_free_irq: 4710 free_irq(tp->irq, tp); 4711 err_release_fw_2: 4712 rtl_release_firmware(tp); 4713 rtl8169_rx_clear(tp); 4714 err_free_rx_1: 4715 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4716 tp->RxPhyAddr); 4717 tp->RxDescArray = NULL; 4718 err_free_tx_0: 4719 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4720 tp->TxPhyAddr); 4721 tp->TxDescArray = NULL; 4722 goto out; 4723 } 4724 4725 static void 4726 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4727 { 4728 struct rtl8169_private *tp = netdev_priv(dev); 4729 struct pci_dev *pdev = tp->pci_dev; 4730 struct rtl8169_counters *counters = tp->counters; 4731 4732 pm_runtime_get_noresume(&pdev->dev); 4733 4734 netdev_stats_to_stats64(stats, &dev->stats); 4735 dev_fetch_sw_netstats(stats, dev->tstats); 4736 4737 /* 4738 * Fetch additional counter values missing in stats collected by driver 4739 * from tally counters. 4740 */ 4741 if (pm_runtime_active(&pdev->dev)) 4742 rtl8169_update_counters(tp); 4743 4744 /* 4745 * Subtract values fetched during initalization. 4746 * See rtl8169_init_counter_offsets for a description why we do that. 4747 */ 4748 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4749 le64_to_cpu(tp->tc_offset.tx_errors); 4750 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4751 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4752 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4753 le16_to_cpu(tp->tc_offset.tx_aborted); 4754 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4755 le16_to_cpu(tp->tc_offset.rx_missed); 4756 4757 pm_runtime_put_noidle(&pdev->dev); 4758 } 4759 4760 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4761 { 4762 netif_device_detach(tp->dev); 4763 4764 if (netif_running(tp->dev)) 4765 rtl8169_down(tp); 4766 } 4767 4768 static int rtl8169_runtime_resume(struct device *dev) 4769 { 4770 struct rtl8169_private *tp = dev_get_drvdata(dev); 4771 4772 rtl_rar_set(tp, tp->dev->dev_addr); 4773 __rtl8169_set_wol(tp, tp->saved_wolopts); 4774 4775 if (tp->TxDescArray) 4776 rtl8169_up(tp); 4777 4778 netif_device_attach(tp->dev); 4779 4780 return 0; 4781 } 4782 4783 static int rtl8169_suspend(struct device *device) 4784 { 4785 struct rtl8169_private *tp = dev_get_drvdata(device); 4786 4787 rtnl_lock(); 4788 rtl8169_net_suspend(tp); 4789 if (!device_may_wakeup(tp_to_dev(tp))) 4790 clk_disable_unprepare(tp->clk); 4791 rtnl_unlock(); 4792 4793 return 0; 4794 } 4795 4796 static int rtl8169_resume(struct device *device) 4797 { 4798 struct rtl8169_private *tp = dev_get_drvdata(device); 4799 4800 if (!device_may_wakeup(tp_to_dev(tp))) 4801 clk_prepare_enable(tp->clk); 4802 4803 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4804 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4805 rtl_init_rxcfg(tp); 4806 4807 return rtl8169_runtime_resume(device); 4808 } 4809 4810 static int rtl8169_runtime_suspend(struct device *device) 4811 { 4812 struct rtl8169_private *tp = dev_get_drvdata(device); 4813 4814 if (!tp->TxDescArray) { 4815 netif_device_detach(tp->dev); 4816 return 0; 4817 } 4818 4819 rtnl_lock(); 4820 __rtl8169_set_wol(tp, WAKE_PHY); 4821 rtl8169_net_suspend(tp); 4822 rtnl_unlock(); 4823 4824 return 0; 4825 } 4826 4827 static int rtl8169_runtime_idle(struct device *device) 4828 { 4829 struct rtl8169_private *tp = dev_get_drvdata(device); 4830 4831 if (tp->dash_type != RTL_DASH_NONE) 4832 return -EBUSY; 4833 4834 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4835 pm_schedule_suspend(device, 10000); 4836 4837 return -EBUSY; 4838 } 4839 4840 static const struct dev_pm_ops rtl8169_pm_ops = { 4841 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4842 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4843 rtl8169_runtime_idle) 4844 }; 4845 4846 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4847 { 4848 /* WoL fails with 8168b when the receiver is disabled. */ 4849 switch (tp->mac_version) { 4850 case RTL_GIGA_MAC_VER_11: 4851 case RTL_GIGA_MAC_VER_17: 4852 pci_clear_master(tp->pci_dev); 4853 4854 RTL_W8(tp, ChipCmd, CmdRxEnb); 4855 rtl_pci_commit(tp); 4856 break; 4857 default: 4858 break; 4859 } 4860 } 4861 4862 static void rtl_shutdown(struct pci_dev *pdev) 4863 { 4864 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4865 4866 rtnl_lock(); 4867 rtl8169_net_suspend(tp); 4868 rtnl_unlock(); 4869 4870 /* Restore original MAC address */ 4871 rtl_rar_set(tp, tp->dev->perm_addr); 4872 4873 if (system_state == SYSTEM_POWER_OFF && 4874 tp->dash_type == RTL_DASH_NONE) { 4875 if (tp->saved_wolopts) 4876 rtl_wol_shutdown_quirk(tp); 4877 4878 pci_wake_from_d3(pdev, tp->saved_wolopts); 4879 pci_set_power_state(pdev, PCI_D3hot); 4880 } 4881 } 4882 4883 static void rtl_remove_one(struct pci_dev *pdev) 4884 { 4885 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4886 4887 if (pci_dev_run_wake(pdev)) 4888 pm_runtime_get_noresume(&pdev->dev); 4889 4890 unregister_netdev(tp->dev); 4891 4892 if (tp->dash_type != RTL_DASH_NONE) 4893 rtl8168_driver_stop(tp); 4894 4895 rtl_release_firmware(tp); 4896 4897 /* restore original MAC address */ 4898 rtl_rar_set(tp, tp->dev->perm_addr); 4899 } 4900 4901 static const struct net_device_ops rtl_netdev_ops = { 4902 .ndo_open = rtl_open, 4903 .ndo_stop = rtl8169_close, 4904 .ndo_get_stats64 = rtl8169_get_stats64, 4905 .ndo_start_xmit = rtl8169_start_xmit, 4906 .ndo_features_check = rtl8169_features_check, 4907 .ndo_tx_timeout = rtl8169_tx_timeout, 4908 .ndo_validate_addr = eth_validate_addr, 4909 .ndo_change_mtu = rtl8169_change_mtu, 4910 .ndo_fix_features = rtl8169_fix_features, 4911 .ndo_set_features = rtl8169_set_features, 4912 .ndo_set_mac_address = rtl_set_mac_address, 4913 .ndo_eth_ioctl = phy_do_ioctl_running, 4914 .ndo_set_rx_mode = rtl_set_rx_mode, 4915 #ifdef CONFIG_NET_POLL_CONTROLLER 4916 .ndo_poll_controller = rtl8169_netpoll, 4917 #endif 4918 4919 }; 4920 4921 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4922 { 4923 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 4924 4925 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 4926 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 4927 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 4928 /* special workaround needed */ 4929 tp->irq_mask |= RxFIFOOver; 4930 else 4931 tp->irq_mask |= RxOverflow; 4932 } 4933 4934 static int rtl_alloc_irq(struct rtl8169_private *tp) 4935 { 4936 unsigned int flags; 4937 4938 switch (tp->mac_version) { 4939 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4940 rtl_unlock_config_regs(tp); 4941 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 4942 rtl_lock_config_regs(tp); 4943 fallthrough; 4944 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 4945 flags = PCI_IRQ_LEGACY; 4946 break; 4947 default: 4948 flags = PCI_IRQ_ALL_TYPES; 4949 break; 4950 } 4951 4952 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 4953 } 4954 4955 static void rtl_read_mac_address(struct rtl8169_private *tp, 4956 u8 mac_addr[ETH_ALEN]) 4957 { 4958 /* Get MAC address */ 4959 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 4960 u32 value; 4961 4962 value = rtl_eri_read(tp, 0xe0); 4963 put_unaligned_le32(value, mac_addr); 4964 value = rtl_eri_read(tp, 0xe4); 4965 put_unaligned_le16(value, mac_addr + 4); 4966 } else if (rtl_is_8125(tp)) { 4967 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 4968 } 4969 } 4970 4971 DECLARE_RTL_COND(rtl_link_list_ready_cond) 4972 { 4973 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 4974 } 4975 4976 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 4977 { 4978 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 4979 } 4980 4981 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 4982 { 4983 struct rtl8169_private *tp = mii_bus->priv; 4984 4985 if (phyaddr > 0) 4986 return -ENODEV; 4987 4988 return rtl_readphy(tp, phyreg); 4989 } 4990 4991 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 4992 int phyreg, u16 val) 4993 { 4994 struct rtl8169_private *tp = mii_bus->priv; 4995 4996 if (phyaddr > 0) 4997 return -ENODEV; 4998 4999 rtl_writephy(tp, phyreg, val); 5000 5001 return 0; 5002 } 5003 5004 static int r8169_mdio_register(struct rtl8169_private *tp) 5005 { 5006 struct pci_dev *pdev = tp->pci_dev; 5007 struct mii_bus *new_bus; 5008 int ret; 5009 5010 new_bus = devm_mdiobus_alloc(&pdev->dev); 5011 if (!new_bus) 5012 return -ENOMEM; 5013 5014 new_bus->name = "r8169"; 5015 new_bus->priv = tp; 5016 new_bus->parent = &pdev->dev; 5017 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5018 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5019 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5020 5021 new_bus->read = r8169_mdio_read_reg; 5022 new_bus->write = r8169_mdio_write_reg; 5023 5024 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5025 if (ret) 5026 return ret; 5027 5028 tp->phydev = mdiobus_get_phy(new_bus, 0); 5029 if (!tp->phydev) { 5030 return -ENODEV; 5031 } else if (!tp->phydev->drv) { 5032 /* Most chip versions fail with the genphy driver. 5033 * Therefore ensure that the dedicated PHY driver is loaded. 5034 */ 5035 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5036 tp->phydev->phy_id); 5037 return -EUNATCH; 5038 } 5039 5040 tp->phydev->mac_managed_pm = 1; 5041 5042 phy_support_asym_pause(tp->phydev); 5043 5044 /* PHY will be woken up in rtl_open() */ 5045 phy_suspend(tp->phydev); 5046 5047 return 0; 5048 } 5049 5050 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5051 { 5052 rtl_enable_rxdvgate(tp); 5053 5054 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5055 msleep(1); 5056 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5057 5058 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5059 r8168g_wait_ll_share_fifo_ready(tp); 5060 5061 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5062 r8168g_wait_ll_share_fifo_ready(tp); 5063 } 5064 5065 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5066 { 5067 rtl_enable_rxdvgate(tp); 5068 5069 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5070 msleep(1); 5071 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5072 5073 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5074 r8168g_wait_ll_share_fifo_ready(tp); 5075 5076 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5077 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5078 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5079 r8168g_wait_ll_share_fifo_ready(tp); 5080 } 5081 5082 static void rtl_hw_initialize(struct rtl8169_private *tp) 5083 { 5084 switch (tp->mac_version) { 5085 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5086 rtl8168ep_stop_cmac(tp); 5087 fallthrough; 5088 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5089 rtl_hw_init_8168g(tp); 5090 break; 5091 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 5092 rtl_hw_init_8125(tp); 5093 break; 5094 default: 5095 break; 5096 } 5097 } 5098 5099 static int rtl_jumbo_max(struct rtl8169_private *tp) 5100 { 5101 /* Non-GBit versions don't support jumbo frames */ 5102 if (!tp->supports_gmii) 5103 return 0; 5104 5105 switch (tp->mac_version) { 5106 /* RTL8169 */ 5107 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5108 return JUMBO_7K; 5109 /* RTL8168b */ 5110 case RTL_GIGA_MAC_VER_11: 5111 case RTL_GIGA_MAC_VER_17: 5112 return JUMBO_4K; 5113 /* RTL8168c */ 5114 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5115 return JUMBO_6K; 5116 default: 5117 return JUMBO_9K; 5118 } 5119 } 5120 5121 static void rtl_init_mac_address(struct rtl8169_private *tp) 5122 { 5123 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5124 struct net_device *dev = tp->dev; 5125 int rc; 5126 5127 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5128 if (!rc) 5129 goto done; 5130 5131 rtl_read_mac_address(tp, mac_addr); 5132 if (is_valid_ether_addr(mac_addr)) 5133 goto done; 5134 5135 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5136 if (is_valid_ether_addr(mac_addr)) 5137 goto done; 5138 5139 eth_random_addr(mac_addr); 5140 dev->addr_assign_type = NET_ADDR_RANDOM; 5141 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5142 done: 5143 eth_hw_addr_set(dev, mac_addr); 5144 rtl_rar_set(tp, mac_addr); 5145 } 5146 5147 /* register is set if system vendor successfully tested ASPM 1.2 */ 5148 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5149 { 5150 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5151 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5152 return true; 5153 5154 return false; 5155 } 5156 5157 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5158 { 5159 struct rtl8169_private *tp; 5160 int jumbo_max, region, rc; 5161 enum mac_version chipset; 5162 struct net_device *dev; 5163 u16 xid; 5164 5165 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5166 if (!dev) 5167 return -ENOMEM; 5168 5169 SET_NETDEV_DEV(dev, &pdev->dev); 5170 dev->netdev_ops = &rtl_netdev_ops; 5171 tp = netdev_priv(dev); 5172 tp->dev = dev; 5173 tp->pci_dev = pdev; 5174 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5175 tp->eee_adv = -1; 5176 tp->ocp_base = OCP_STD_PHY_BASE; 5177 5178 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev, 5179 struct pcpu_sw_netstats); 5180 if (!dev->tstats) 5181 return -ENOMEM; 5182 5183 /* Get the *optional* external "ether_clk" used on some boards */ 5184 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5185 if (IS_ERR(tp->clk)) 5186 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5187 5188 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5189 rc = pcim_enable_device(pdev); 5190 if (rc < 0) { 5191 dev_err(&pdev->dev, "enable failure\n"); 5192 return rc; 5193 } 5194 5195 if (pcim_set_mwi(pdev) < 0) 5196 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5197 5198 /* use first MMIO region */ 5199 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5200 if (region < 0) { 5201 dev_err(&pdev->dev, "no MMIO resource found\n"); 5202 return -ENODEV; 5203 } 5204 5205 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5206 if (rc < 0) { 5207 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5208 return rc; 5209 } 5210 5211 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5212 5213 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5214 5215 /* Identify chip attached to board */ 5216 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5217 if (chipset == RTL_GIGA_MAC_NONE) { 5218 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid); 5219 return -ENODEV; 5220 } 5221 5222 tp->mac_version = chipset; 5223 5224 /* Disable ASPM L1 as that cause random device stop working 5225 * problems as well as full system hangs for some PCIe devices users. 5226 * Chips from RTL8168h partially have issues with L1.2, but seem 5227 * to work fine with L1 and L1.1. 5228 */ 5229 if (rtl_aspm_is_safe(tp)) 5230 rc = 0; 5231 else if (tp->mac_version >= RTL_GIGA_MAC_VER_46) 5232 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2); 5233 else 5234 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5235 tp->aspm_manageable = !rc; 5236 5237 tp->dash_type = rtl_check_dash(tp); 5238 5239 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5240 5241 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5242 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5243 dev->features |= NETIF_F_HIGHDMA; 5244 5245 rtl_init_rxcfg(tp); 5246 5247 rtl8169_irq_mask_and_ack(tp); 5248 5249 rtl_hw_initialize(tp); 5250 5251 rtl_hw_reset(tp); 5252 5253 rc = rtl_alloc_irq(tp); 5254 if (rc < 0) { 5255 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5256 return rc; 5257 } 5258 tp->irq = pci_irq_vector(pdev, 0); 5259 5260 INIT_WORK(&tp->wk.work, rtl_task); 5261 5262 rtl_init_mac_address(tp); 5263 5264 dev->ethtool_ops = &rtl8169_ethtool_ops; 5265 5266 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5267 5268 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5269 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5270 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5271 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5272 5273 /* 5274 * Pretend we are using VLANs; This bypasses a nasty bug where 5275 * Interrupts stop flowing on high load on 8110SCd controllers. 5276 */ 5277 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5278 /* Disallow toggling */ 5279 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5280 5281 if (rtl_chip_supports_csum_v2(tp)) 5282 dev->hw_features |= NETIF_F_IPV6_CSUM; 5283 5284 dev->features |= dev->hw_features; 5285 5286 /* There has been a number of reports that using SG/TSO results in 5287 * tx timeouts. However for a lot of people SG/TSO works fine. 5288 * Therefore disable both features by default, but allow users to 5289 * enable them. Use at own risk! 5290 */ 5291 if (rtl_chip_supports_csum_v2(tp)) { 5292 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5293 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5294 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5295 } else { 5296 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5297 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5298 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5299 } 5300 5301 dev->hw_features |= NETIF_F_RXALL; 5302 dev->hw_features |= NETIF_F_RXFCS; 5303 5304 /* configure chip for default features */ 5305 rtl8169_set_features(dev, dev->features); 5306 5307 if (tp->dash_type == RTL_DASH_NONE) { 5308 rtl_set_d3_pll_down(tp, true); 5309 } else { 5310 rtl_set_d3_pll_down(tp, false); 5311 dev->wol_enabled = 1; 5312 } 5313 5314 jumbo_max = rtl_jumbo_max(tp); 5315 if (jumbo_max) 5316 dev->max_mtu = jumbo_max; 5317 5318 rtl_set_irq_mask(tp); 5319 5320 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5321 5322 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5323 &tp->counters_phys_addr, 5324 GFP_KERNEL); 5325 if (!tp->counters) 5326 return -ENOMEM; 5327 5328 pci_set_drvdata(pdev, tp); 5329 5330 rc = r8169_mdio_register(tp); 5331 if (rc) 5332 return rc; 5333 5334 rc = register_netdev(dev); 5335 if (rc) 5336 return rc; 5337 5338 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5339 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5340 5341 if (jumbo_max) 5342 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5343 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5344 "ok" : "ko"); 5345 5346 if (tp->dash_type != RTL_DASH_NONE) { 5347 netdev_info(dev, "DASH enabled\n"); 5348 rtl8168_driver_start(tp); 5349 } 5350 5351 if (pci_dev_run_wake(pdev)) 5352 pm_runtime_put_sync(&pdev->dev); 5353 5354 return 0; 5355 } 5356 5357 static struct pci_driver rtl8169_pci_driver = { 5358 .name = KBUILD_MODNAME, 5359 .id_table = rtl8169_pci_tbl, 5360 .probe = rtl_init_one, 5361 .remove = rtl_remove_one, 5362 .shutdown = rtl_shutdown, 5363 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5364 }; 5365 5366 module_pci_driver(rtl8169_pci_driver); 5367