1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <net/ip6_checksum.h> 32 33 #include "r8169.h" 34 #include "r8169_firmware.h" 35 36 #define MODULENAME "r8169" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 58 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 59 60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 62 #define MC_FILTER_LIMIT 32 63 64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 66 67 #define R8169_REGS_SIZE 256 68 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 69 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 70 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 73 74 #define OCP_STD_PHY_BASE 0xa400 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 91 static const struct { 92 const char *name; 93 const char *fw_name; 94 } rtl_chip_infos[] = { 95 /* PCI devices. */ 96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 101 /* PCI-E devices. */ 102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 109 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 110 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 111 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 112 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 113 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 119 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 120 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 121 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 122 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 125 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 126 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 127 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 128 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 129 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 130 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 131 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 132 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 133 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 134 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 135 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 136 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 137 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 138 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 139 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 140 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 141 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 142 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 143 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 144 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 145 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 148 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 149 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 150 }; 151 152 static const struct pci_device_id rtl8169_pci_tbl[] = { 153 { PCI_VDEVICE(REALTEK, 0x2502) }, 154 { PCI_VDEVICE(REALTEK, 0x2600) }, 155 { PCI_VDEVICE(REALTEK, 0x8129) }, 156 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 157 { PCI_VDEVICE(REALTEK, 0x8161) }, 158 { PCI_VDEVICE(REALTEK, 0x8167) }, 159 { PCI_VDEVICE(REALTEK, 0x8168) }, 160 { PCI_VDEVICE(NCUBE, 0x8168) }, 161 { PCI_VDEVICE(REALTEK, 0x8169) }, 162 { PCI_VENDOR_ID_DLINK, 0x4300, 163 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 164 { PCI_VDEVICE(DLINK, 0x4300) }, 165 { PCI_VDEVICE(DLINK, 0x4302) }, 166 { PCI_VDEVICE(AT, 0xc107) }, 167 { PCI_VDEVICE(USR, 0x0116) }, 168 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 169 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 170 { PCI_VDEVICE(REALTEK, 0x8125) }, 171 { PCI_VDEVICE(REALTEK, 0x3000) }, 172 {} 173 }; 174 175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 176 177 enum rtl_registers { 178 MAC0 = 0, /* Ethernet hardware address. */ 179 MAC4 = 4, 180 MAR0 = 8, /* Multicast filter. */ 181 CounterAddrLow = 0x10, 182 CounterAddrHigh = 0x14, 183 TxDescStartAddrLow = 0x20, 184 TxDescStartAddrHigh = 0x24, 185 TxHDescStartAddrLow = 0x28, 186 TxHDescStartAddrHigh = 0x2c, 187 FLASH = 0x30, 188 ERSR = 0x36, 189 ChipCmd = 0x37, 190 TxPoll = 0x38, 191 IntrMask = 0x3c, 192 IntrStatus = 0x3e, 193 194 TxConfig = 0x40, 195 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 196 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 197 198 RxConfig = 0x44, 199 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 200 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 201 #define RXCFG_FIFO_SHIFT 13 202 /* No threshold before first PCI xfer */ 203 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 204 #define RX_EARLY_OFF (1 << 11) 205 #define RXCFG_DMA_SHIFT 8 206 /* Unlimited maximum PCI burst. */ 207 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 208 209 Cfg9346 = 0x50, 210 Config0 = 0x51, 211 Config1 = 0x52, 212 Config2 = 0x53, 213 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 214 215 Config3 = 0x54, 216 Config4 = 0x55, 217 Config5 = 0x56, 218 PHYAR = 0x60, 219 PHYstatus = 0x6c, 220 RxMaxSize = 0xda, 221 CPlusCmd = 0xe0, 222 IntrMitigate = 0xe2, 223 224 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 225 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 226 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 227 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 228 229 #define RTL_COALESCE_T_MAX 0x0fU 230 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 231 232 RxDescAddrLow = 0xe4, 233 RxDescAddrHigh = 0xe8, 234 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 235 236 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 237 238 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 239 240 #define TxPacketMax (8064 >> 7) 241 #define EarlySize 0x27 242 243 FuncEvent = 0xf0, 244 FuncEventMask = 0xf4, 245 FuncPresetState = 0xf8, 246 IBCR0 = 0xf8, 247 IBCR2 = 0xf9, 248 IBIMR0 = 0xfa, 249 IBISR0 = 0xfb, 250 FuncForceEvent = 0xfc, 251 }; 252 253 enum rtl8168_8101_registers { 254 CSIDR = 0x64, 255 CSIAR = 0x68, 256 #define CSIAR_FLAG 0x80000000 257 #define CSIAR_WRITE_CMD 0x80000000 258 #define CSIAR_BYTE_ENABLE 0x0000f000 259 #define CSIAR_ADDR_MASK 0x00000fff 260 PMCH = 0x6f, 261 EPHYAR = 0x80, 262 #define EPHYAR_FLAG 0x80000000 263 #define EPHYAR_WRITE_CMD 0x80000000 264 #define EPHYAR_REG_MASK 0x1f 265 #define EPHYAR_REG_SHIFT 16 266 #define EPHYAR_DATA_MASK 0xffff 267 DLLPR = 0xd0, 268 #define PFM_EN (1 << 6) 269 #define TX_10M_PS_EN (1 << 7) 270 DBG_REG = 0xd1, 271 #define FIX_NAK_1 (1 << 4) 272 #define FIX_NAK_2 (1 << 3) 273 TWSI = 0xd2, 274 MCU = 0xd3, 275 #define NOW_IS_OOB (1 << 7) 276 #define TX_EMPTY (1 << 5) 277 #define RX_EMPTY (1 << 4) 278 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 279 #define EN_NDP (1 << 3) 280 #define EN_OOB_RESET (1 << 2) 281 #define LINK_LIST_RDY (1 << 1) 282 EFUSEAR = 0xdc, 283 #define EFUSEAR_FLAG 0x80000000 284 #define EFUSEAR_WRITE_CMD 0x80000000 285 #define EFUSEAR_READ_CMD 0x00000000 286 #define EFUSEAR_REG_MASK 0x03ff 287 #define EFUSEAR_REG_SHIFT 8 288 #define EFUSEAR_DATA_MASK 0xff 289 MISC_1 = 0xf2, 290 #define PFM_D3COLD_EN (1 << 6) 291 }; 292 293 enum rtl8168_registers { 294 LED_FREQ = 0x1a, 295 EEE_LED = 0x1b, 296 ERIDR = 0x70, 297 ERIAR = 0x74, 298 #define ERIAR_FLAG 0x80000000 299 #define ERIAR_WRITE_CMD 0x80000000 300 #define ERIAR_READ_CMD 0x00000000 301 #define ERIAR_ADDR_BYTE_ALIGN 4 302 #define ERIAR_TYPE_SHIFT 16 303 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 306 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_MASK_SHIFT 12 308 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 311 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 313 EPHY_RXER_NUM = 0x7c, 314 OCPDR = 0xb0, /* OCP GPHY access */ 315 #define OCPDR_WRITE_CMD 0x80000000 316 #define OCPDR_READ_CMD 0x00000000 317 #define OCPDR_REG_MASK 0x7f 318 #define OCPDR_GPHY_REG_SHIFT 16 319 #define OCPDR_DATA_MASK 0xffff 320 OCPAR = 0xb4, 321 #define OCPAR_FLAG 0x80000000 322 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 323 #define OCPAR_GPHY_READ_CMD 0x0000f060 324 GPHY_OCP = 0xb8, 325 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 326 MISC = 0xf0, /* 8168e only. */ 327 #define TXPLA_RST (1 << 29) 328 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 329 #define PWM_EN (1 << 22) 330 #define RXDV_GATED_EN (1 << 19) 331 #define EARLY_TALLY_EN (1 << 16) 332 }; 333 334 enum rtl8125_registers { 335 IntrMask_8125 = 0x38, 336 IntrStatus_8125 = 0x3c, 337 TxPoll_8125 = 0x90, 338 MAC0_BKP = 0x19e0, 339 }; 340 341 #define RX_VLAN_INNER_8125 BIT(22) 342 #define RX_VLAN_OUTER_8125 BIT(23) 343 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 344 345 #define RX_FETCH_DFLT_8125 (8 << 27) 346 347 enum rtl_register_content { 348 /* InterruptStatusBits */ 349 SYSErr = 0x8000, 350 PCSTimeout = 0x4000, 351 SWInt = 0x0100, 352 TxDescUnavail = 0x0080, 353 RxFIFOOver = 0x0040, 354 LinkChg = 0x0020, 355 RxOverflow = 0x0010, 356 TxErr = 0x0008, 357 TxOK = 0x0004, 358 RxErr = 0x0002, 359 RxOK = 0x0001, 360 361 /* RxStatusDesc */ 362 RxRWT = (1 << 22), 363 RxRES = (1 << 21), 364 RxRUNT = (1 << 20), 365 RxCRC = (1 << 19), 366 367 /* ChipCmdBits */ 368 StopReq = 0x80, 369 CmdReset = 0x10, 370 CmdRxEnb = 0x08, 371 CmdTxEnb = 0x04, 372 RxBufEmpty = 0x01, 373 374 /* TXPoll register p.5 */ 375 HPQ = 0x80, /* Poll cmd on the high prio queue */ 376 NPQ = 0x40, /* Poll cmd on the low prio queue */ 377 FSWInt = 0x01, /* Forced software interrupt */ 378 379 /* Cfg9346Bits */ 380 Cfg9346_Lock = 0x00, 381 Cfg9346_Unlock = 0xc0, 382 383 /* rx_mode_bits */ 384 AcceptErr = 0x20, 385 AcceptRunt = 0x10, 386 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 387 AcceptBroadcast = 0x08, 388 AcceptMulticast = 0x04, 389 AcceptMyPhys = 0x02, 390 AcceptAllPhys = 0x01, 391 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 392 #define RX_CONFIG_ACCEPT_MASK 0x3f 393 394 /* TxConfigBits */ 395 TxInterFrameGapShift = 24, 396 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 397 398 /* Config1 register p.24 */ 399 LEDS1 = (1 << 7), 400 LEDS0 = (1 << 6), 401 Speed_down = (1 << 4), 402 MEMMAP = (1 << 3), 403 IOMAP = (1 << 2), 404 VPD = (1 << 1), 405 PMEnable = (1 << 0), /* Power Management Enable */ 406 407 /* Config2 register p. 25 */ 408 ClkReqEn = (1 << 7), /* Clock Request Enable */ 409 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 410 PCI_Clock_66MHz = 0x01, 411 PCI_Clock_33MHz = 0x00, 412 413 /* Config3 register p.25 */ 414 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 415 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 416 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 417 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 418 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 419 420 /* Config4 register */ 421 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 422 423 /* Config5 register p.27 */ 424 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 425 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 426 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 427 Spi_en = (1 << 3), 428 LanWake = (1 << 1), /* LanWake enable/disable */ 429 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 430 ASPM_en = (1 << 0), /* ASPM enable */ 431 432 /* CPlusCmd p.31 */ 433 EnableBist = (1 << 15), // 8168 8101 434 Mac_dbgo_oe = (1 << 14), // 8168 8101 435 EnAnaPLL = (1 << 14), // 8169 436 Normal_mode = (1 << 13), // unused 437 Force_half_dup = (1 << 12), // 8168 8101 438 Force_rxflow_en = (1 << 11), // 8168 8101 439 Force_txflow_en = (1 << 10), // 8168 8101 440 Cxpl_dbg_sel = (1 << 9), // 8168 8101 441 ASF = (1 << 8), // 8168 8101 442 PktCntrDisable = (1 << 7), // 8168 8101 443 Mac_dbgo_sel = 0x001c, // 8168 444 RxVlan = (1 << 6), 445 RxChkSum = (1 << 5), 446 PCIDAC = (1 << 4), 447 PCIMulRW = (1 << 3), 448 #define INTT_MASK GENMASK(1, 0) 449 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 450 451 /* rtl8169_PHYstatus */ 452 TBI_Enable = 0x80, 453 TxFlowCtrl = 0x40, 454 RxFlowCtrl = 0x20, 455 _1000bpsF = 0x10, 456 _100bps = 0x08, 457 _10bps = 0x04, 458 LinkStatus = 0x02, 459 FullDup = 0x01, 460 461 /* ResetCounterCommand */ 462 CounterReset = 0x1, 463 464 /* DumpCounterCommand */ 465 CounterDump = 0x8, 466 467 /* magic enable v2 */ 468 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 469 }; 470 471 enum rtl_desc_bit { 472 /* First doubleword. */ 473 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 474 RingEnd = (1 << 30), /* End of descriptor ring */ 475 FirstFrag = (1 << 29), /* First segment of a packet */ 476 LastFrag = (1 << 28), /* Final segment of a packet */ 477 }; 478 479 /* Generic case. */ 480 enum rtl_tx_desc_bit { 481 /* First doubleword. */ 482 TD_LSO = (1 << 27), /* Large Send Offload */ 483 #define TD_MSS_MAX 0x07ffu /* MSS value */ 484 485 /* Second doubleword. */ 486 TxVlanTag = (1 << 17), /* Add VLAN tag */ 487 }; 488 489 /* 8169, 8168b and 810x except 8102e. */ 490 enum rtl_tx_desc_bit_0 { 491 /* First doubleword. */ 492 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 493 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 494 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 495 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 496 }; 497 498 /* 8102e, 8168c and beyond. */ 499 enum rtl_tx_desc_bit_1 { 500 /* First doubleword. */ 501 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 502 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 503 #define GTTCPHO_SHIFT 18 504 #define GTTCPHO_MAX 0x7f 505 506 /* Second doubleword. */ 507 #define TCPHO_SHIFT 18 508 #define TCPHO_MAX 0x3ff 509 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 510 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 511 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 512 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 513 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 514 }; 515 516 enum rtl_rx_desc_bit { 517 /* Rx private */ 518 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 519 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 520 521 #define RxProtoUDP (PID1) 522 #define RxProtoTCP (PID0) 523 #define RxProtoIP (PID1 | PID0) 524 #define RxProtoMask RxProtoIP 525 526 IPFail = (1 << 16), /* IP checksum failed */ 527 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 528 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 529 RxVlanTag = (1 << 16), /* VLAN tag available */ 530 }; 531 532 #define RsvdMask 0x3fffc000 533 534 #define RTL_GSO_MAX_SIZE_V1 32000 535 #define RTL_GSO_MAX_SEGS_V1 24 536 #define RTL_GSO_MAX_SIZE_V2 64000 537 #define RTL_GSO_MAX_SEGS_V2 64 538 539 struct TxDesc { 540 __le32 opts1; 541 __le32 opts2; 542 __le64 addr; 543 }; 544 545 struct RxDesc { 546 __le32 opts1; 547 __le32 opts2; 548 __le64 addr; 549 }; 550 551 struct ring_info { 552 struct sk_buff *skb; 553 u32 len; 554 }; 555 556 struct rtl8169_counters { 557 __le64 tx_packets; 558 __le64 rx_packets; 559 __le64 tx_errors; 560 __le32 rx_errors; 561 __le16 rx_missed; 562 __le16 align_errors; 563 __le32 tx_one_collision; 564 __le32 tx_multi_collision; 565 __le64 rx_unicast; 566 __le64 rx_broadcast; 567 __le32 rx_multicast; 568 __le16 tx_aborted; 569 __le16 tx_underun; 570 }; 571 572 struct rtl8169_tc_offsets { 573 bool inited; 574 __le64 tx_errors; 575 __le32 tx_multi_collision; 576 __le16 tx_aborted; 577 __le16 rx_missed; 578 }; 579 580 enum rtl_flag { 581 RTL_FLAG_TASK_ENABLED = 0, 582 RTL_FLAG_TASK_RESET_PENDING, 583 RTL_FLAG_MAX 584 }; 585 586 struct rtl8169_stats { 587 u64 packets; 588 u64 bytes; 589 struct u64_stats_sync syncp; 590 }; 591 592 struct rtl8169_private { 593 void __iomem *mmio_addr; /* memory map physical address */ 594 struct pci_dev *pci_dev; 595 struct net_device *dev; 596 struct phy_device *phydev; 597 struct napi_struct napi; 598 enum mac_version mac_version; 599 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 600 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 601 u32 dirty_tx; 602 struct rtl8169_stats rx_stats; 603 struct rtl8169_stats tx_stats; 604 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 605 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 606 dma_addr_t TxPhyAddr; 607 dma_addr_t RxPhyAddr; 608 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 609 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 610 u16 cp_cmd; 611 u32 irq_mask; 612 struct clk *clk; 613 614 struct { 615 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 616 struct mutex mutex; 617 struct work_struct work; 618 } wk; 619 620 unsigned irq_enabled:1; 621 unsigned supports_gmii:1; 622 unsigned aspm_manageable:1; 623 dma_addr_t counters_phys_addr; 624 struct rtl8169_counters *counters; 625 struct rtl8169_tc_offsets tc_offset; 626 u32 saved_wolopts; 627 int eee_adv; 628 629 const char *fw_name; 630 struct rtl_fw *rtl_fw; 631 632 u32 ocp_base; 633 }; 634 635 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 636 637 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 638 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 639 MODULE_SOFTDEP("pre: realtek"); 640 MODULE_LICENSE("GPL"); 641 MODULE_FIRMWARE(FIRMWARE_8168D_1); 642 MODULE_FIRMWARE(FIRMWARE_8168D_2); 643 MODULE_FIRMWARE(FIRMWARE_8168E_1); 644 MODULE_FIRMWARE(FIRMWARE_8168E_2); 645 MODULE_FIRMWARE(FIRMWARE_8168E_3); 646 MODULE_FIRMWARE(FIRMWARE_8105E_1); 647 MODULE_FIRMWARE(FIRMWARE_8168F_1); 648 MODULE_FIRMWARE(FIRMWARE_8168F_2); 649 MODULE_FIRMWARE(FIRMWARE_8402_1); 650 MODULE_FIRMWARE(FIRMWARE_8411_1); 651 MODULE_FIRMWARE(FIRMWARE_8411_2); 652 MODULE_FIRMWARE(FIRMWARE_8106E_1); 653 MODULE_FIRMWARE(FIRMWARE_8106E_2); 654 MODULE_FIRMWARE(FIRMWARE_8168G_2); 655 MODULE_FIRMWARE(FIRMWARE_8168G_3); 656 MODULE_FIRMWARE(FIRMWARE_8168H_1); 657 MODULE_FIRMWARE(FIRMWARE_8168H_2); 658 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 659 MODULE_FIRMWARE(FIRMWARE_8107E_1); 660 MODULE_FIRMWARE(FIRMWARE_8107E_2); 661 MODULE_FIRMWARE(FIRMWARE_8125A_3); 662 663 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 664 { 665 return &tp->pci_dev->dev; 666 } 667 668 static void rtl_lock_work(struct rtl8169_private *tp) 669 { 670 mutex_lock(&tp->wk.mutex); 671 } 672 673 static void rtl_unlock_work(struct rtl8169_private *tp) 674 { 675 mutex_unlock(&tp->wk.mutex); 676 } 677 678 static void rtl_lock_config_regs(struct rtl8169_private *tp) 679 { 680 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 681 } 682 683 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 684 { 685 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 686 } 687 688 static void rtl_pci_commit(struct rtl8169_private *tp) 689 { 690 /* Read an arbitrary register to commit a preceding PCI write */ 691 RTL_R8(tp, ChipCmd); 692 } 693 694 static bool rtl_is_8125(struct rtl8169_private *tp) 695 { 696 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 697 } 698 699 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 700 { 701 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 702 tp->mac_version != RTL_GIGA_MAC_VER_39 && 703 tp->mac_version <= RTL_GIGA_MAC_VER_52; 704 } 705 706 static bool rtl_supports_eee(struct rtl8169_private *tp) 707 { 708 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 709 tp->mac_version != RTL_GIGA_MAC_VER_37 && 710 tp->mac_version != RTL_GIGA_MAC_VER_39; 711 } 712 713 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 714 { 715 int i; 716 717 for (i = 0; i < ETH_ALEN; i++) 718 mac[i] = RTL_R8(tp, reg + i); 719 } 720 721 struct rtl_cond { 722 bool (*check)(struct rtl8169_private *); 723 const char *msg; 724 }; 725 726 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 727 unsigned long usecs, int n, bool high) 728 { 729 int i; 730 731 for (i = 0; i < n; i++) { 732 if (c->check(tp) == high) 733 return true; 734 fsleep(usecs); 735 } 736 737 if (net_ratelimit()) 738 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 739 c->msg, !high, n, usecs); 740 return false; 741 } 742 743 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 744 const struct rtl_cond *c, 745 unsigned long d, int n) 746 { 747 return rtl_loop_wait(tp, c, d, n, true); 748 } 749 750 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 751 const struct rtl_cond *c, 752 unsigned long d, int n) 753 { 754 return rtl_loop_wait(tp, c, d, n, false); 755 } 756 757 #define DECLARE_RTL_COND(name) \ 758 static bool name ## _check(struct rtl8169_private *); \ 759 \ 760 static const struct rtl_cond name = { \ 761 .check = name ## _check, \ 762 .msg = #name \ 763 }; \ 764 \ 765 static bool name ## _check(struct rtl8169_private *tp) 766 767 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 768 { 769 if (reg & 0xffff0001) { 770 if (net_ratelimit()) 771 netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg); 772 return true; 773 } 774 return false; 775 } 776 777 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 778 { 779 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 780 } 781 782 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 783 { 784 if (rtl_ocp_reg_failure(tp, reg)) 785 return; 786 787 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 788 789 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 790 } 791 792 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 793 { 794 if (rtl_ocp_reg_failure(tp, reg)) 795 return 0; 796 797 RTL_W32(tp, GPHY_OCP, reg << 15); 798 799 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 800 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 801 } 802 803 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 804 { 805 if (rtl_ocp_reg_failure(tp, reg)) 806 return; 807 808 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 809 } 810 811 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 812 { 813 if (rtl_ocp_reg_failure(tp, reg)) 814 return 0; 815 816 RTL_W32(tp, OCPDR, reg << 15); 817 818 return RTL_R32(tp, OCPDR); 819 } 820 821 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 822 u16 set) 823 { 824 u16 data = r8168_mac_ocp_read(tp, reg); 825 826 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 827 } 828 829 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 830 { 831 if (reg == 0x1f) { 832 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 833 return; 834 } 835 836 if (tp->ocp_base != OCP_STD_PHY_BASE) 837 reg -= 0x10; 838 839 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 840 } 841 842 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 843 { 844 if (reg == 0x1f) 845 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 846 847 if (tp->ocp_base != OCP_STD_PHY_BASE) 848 reg -= 0x10; 849 850 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 851 } 852 853 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 854 { 855 if (reg == 0x1f) { 856 tp->ocp_base = value << 4; 857 return; 858 } 859 860 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 861 } 862 863 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 864 { 865 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 866 } 867 868 DECLARE_RTL_COND(rtl_phyar_cond) 869 { 870 return RTL_R32(tp, PHYAR) & 0x80000000; 871 } 872 873 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 874 { 875 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 876 877 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 878 /* 879 * According to hardware specs a 20us delay is required after write 880 * complete indication, but before sending next command. 881 */ 882 udelay(20); 883 } 884 885 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 886 { 887 int value; 888 889 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 890 891 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 892 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 893 894 /* 895 * According to hardware specs a 20us delay is required after read 896 * complete indication, but before sending next command. 897 */ 898 udelay(20); 899 900 return value; 901 } 902 903 DECLARE_RTL_COND(rtl_ocpar_cond) 904 { 905 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 906 } 907 908 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 909 { 910 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 911 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 912 RTL_W32(tp, EPHY_RXER_NUM, 0); 913 914 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 915 } 916 917 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 918 { 919 r8168dp_1_mdio_access(tp, reg, 920 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 921 } 922 923 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 924 { 925 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 926 927 mdelay(1); 928 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 929 RTL_W32(tp, EPHY_RXER_NUM, 0); 930 931 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 932 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 933 } 934 935 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 936 937 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 938 { 939 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 940 } 941 942 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 943 { 944 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 945 } 946 947 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 948 { 949 r8168dp_2_mdio_start(tp); 950 951 r8169_mdio_write(tp, reg, value); 952 953 r8168dp_2_mdio_stop(tp); 954 } 955 956 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 957 { 958 int value; 959 960 /* Work around issue with chip reporting wrong PHY ID */ 961 if (reg == MII_PHYSID2) 962 return 0xc912; 963 964 r8168dp_2_mdio_start(tp); 965 966 value = r8169_mdio_read(tp, reg); 967 968 r8168dp_2_mdio_stop(tp); 969 970 return value; 971 } 972 973 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 974 { 975 switch (tp->mac_version) { 976 case RTL_GIGA_MAC_VER_27: 977 r8168dp_1_mdio_write(tp, location, val); 978 break; 979 case RTL_GIGA_MAC_VER_28: 980 case RTL_GIGA_MAC_VER_31: 981 r8168dp_2_mdio_write(tp, location, val); 982 break; 983 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 984 r8168g_mdio_write(tp, location, val); 985 break; 986 default: 987 r8169_mdio_write(tp, location, val); 988 break; 989 } 990 } 991 992 static int rtl_readphy(struct rtl8169_private *tp, int location) 993 { 994 switch (tp->mac_version) { 995 case RTL_GIGA_MAC_VER_27: 996 return r8168dp_1_mdio_read(tp, location); 997 case RTL_GIGA_MAC_VER_28: 998 case RTL_GIGA_MAC_VER_31: 999 return r8168dp_2_mdio_read(tp, location); 1000 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1001 return r8168g_mdio_read(tp, location); 1002 default: 1003 return r8169_mdio_read(tp, location); 1004 } 1005 } 1006 1007 DECLARE_RTL_COND(rtl_ephyar_cond) 1008 { 1009 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1010 } 1011 1012 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1013 { 1014 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1015 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1016 1017 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1018 1019 udelay(10); 1020 } 1021 1022 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1023 { 1024 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1025 1026 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1027 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1028 } 1029 1030 DECLARE_RTL_COND(rtl_eriar_cond) 1031 { 1032 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1033 } 1034 1035 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1036 u32 val, int type) 1037 { 1038 BUG_ON((addr & 3) || (mask == 0)); 1039 RTL_W32(tp, ERIDR, val); 1040 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr); 1041 1042 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1043 } 1044 1045 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1046 u32 val) 1047 { 1048 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1049 } 1050 1051 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1052 { 1053 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); 1054 1055 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1056 RTL_R32(tp, ERIDR) : ~0; 1057 } 1058 1059 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1060 { 1061 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1062 } 1063 1064 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p, 1065 u32 m) 1066 { 1067 u32 val; 1068 1069 val = rtl_eri_read(tp, addr); 1070 rtl_eri_write(tp, addr, mask, (val & ~m) | p); 1071 } 1072 1073 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask, 1074 u32 p) 1075 { 1076 rtl_w0w1_eri(tp, addr, mask, p, 0); 1077 } 1078 1079 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask, 1080 u32 m) 1081 { 1082 rtl_w0w1_eri(tp, addr, mask, 0, m); 1083 } 1084 1085 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1086 { 1087 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1088 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1089 RTL_R32(tp, OCPDR) : ~0; 1090 } 1091 1092 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 1093 { 1094 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1095 } 1096 1097 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1098 u32 data) 1099 { 1100 RTL_W32(tp, OCPDR, data); 1101 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1102 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1103 } 1104 1105 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1106 u32 data) 1107 { 1108 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1109 data, ERIAR_OOB); 1110 } 1111 1112 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1113 { 1114 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1115 1116 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1117 } 1118 1119 #define OOB_CMD_RESET 0x00 1120 #define OOB_CMD_DRIVER_START 0x05 1121 #define OOB_CMD_DRIVER_STOP 0x06 1122 1123 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1124 { 1125 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1126 } 1127 1128 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1129 { 1130 u16 reg; 1131 1132 reg = rtl8168_get_ocp_reg(tp); 1133 1134 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800; 1135 } 1136 1137 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1138 { 1139 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001; 1140 } 1141 1142 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1143 { 1144 return RTL_R8(tp, IBISR0) & 0x20; 1145 } 1146 1147 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1148 { 1149 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1150 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1151 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1152 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1153 } 1154 1155 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1156 { 1157 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1158 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1159 } 1160 1161 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1162 { 1163 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1164 r8168ep_ocp_write(tp, 0x01, 0x30, 1165 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1166 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1167 } 1168 1169 static void rtl8168_driver_start(struct rtl8169_private *tp) 1170 { 1171 switch (tp->mac_version) { 1172 case RTL_GIGA_MAC_VER_27: 1173 case RTL_GIGA_MAC_VER_28: 1174 case RTL_GIGA_MAC_VER_31: 1175 rtl8168dp_driver_start(tp); 1176 break; 1177 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1178 rtl8168ep_driver_start(tp); 1179 break; 1180 default: 1181 BUG(); 1182 break; 1183 } 1184 } 1185 1186 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1187 { 1188 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1189 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1190 } 1191 1192 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1193 { 1194 rtl8168ep_stop_cmac(tp); 1195 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1196 r8168ep_ocp_write(tp, 0x01, 0x30, 1197 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01); 1198 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1199 } 1200 1201 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1202 { 1203 switch (tp->mac_version) { 1204 case RTL_GIGA_MAC_VER_27: 1205 case RTL_GIGA_MAC_VER_28: 1206 case RTL_GIGA_MAC_VER_31: 1207 rtl8168dp_driver_stop(tp); 1208 break; 1209 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1210 rtl8168ep_driver_stop(tp); 1211 break; 1212 default: 1213 BUG(); 1214 break; 1215 } 1216 } 1217 1218 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1219 { 1220 u16 reg = rtl8168_get_ocp_reg(tp); 1221 1222 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000); 1223 } 1224 1225 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1226 { 1227 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001); 1228 } 1229 1230 static bool r8168_check_dash(struct rtl8169_private *tp) 1231 { 1232 switch (tp->mac_version) { 1233 case RTL_GIGA_MAC_VER_27: 1234 case RTL_GIGA_MAC_VER_28: 1235 case RTL_GIGA_MAC_VER_31: 1236 return r8168dp_check_dash(tp); 1237 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1238 return r8168ep_check_dash(tp); 1239 default: 1240 return false; 1241 } 1242 } 1243 1244 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1245 { 1246 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1247 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0)); 1248 } 1249 1250 DECLARE_RTL_COND(rtl_efusear_cond) 1251 { 1252 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1253 } 1254 1255 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1256 { 1257 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1258 1259 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1260 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1261 } 1262 1263 static u32 rtl_get_events(struct rtl8169_private *tp) 1264 { 1265 if (rtl_is_8125(tp)) 1266 return RTL_R32(tp, IntrStatus_8125); 1267 else 1268 return RTL_R16(tp, IntrStatus); 1269 } 1270 1271 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1272 { 1273 if (rtl_is_8125(tp)) 1274 RTL_W32(tp, IntrStatus_8125, bits); 1275 else 1276 RTL_W16(tp, IntrStatus, bits); 1277 } 1278 1279 static void rtl_irq_disable(struct rtl8169_private *tp) 1280 { 1281 if (rtl_is_8125(tp)) 1282 RTL_W32(tp, IntrMask_8125, 0); 1283 else 1284 RTL_W16(tp, IntrMask, 0); 1285 tp->irq_enabled = 0; 1286 } 1287 1288 static void rtl_irq_enable(struct rtl8169_private *tp) 1289 { 1290 tp->irq_enabled = 1; 1291 if (rtl_is_8125(tp)) 1292 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1293 else 1294 RTL_W16(tp, IntrMask, tp->irq_mask); 1295 } 1296 1297 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1298 { 1299 rtl_irq_disable(tp); 1300 rtl_ack_events(tp, 0xffffffff); 1301 rtl_pci_commit(tp); 1302 } 1303 1304 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1305 { 1306 struct phy_device *phydev = tp->phydev; 1307 1308 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1309 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1310 if (phydev->speed == SPEED_1000) { 1311 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1312 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1313 } else if (phydev->speed == SPEED_100) { 1314 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1315 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1316 } else { 1317 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1318 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1319 } 1320 rtl_reset_packet_filter(tp); 1321 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1322 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1323 if (phydev->speed == SPEED_1000) { 1324 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1325 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1326 } else { 1327 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1328 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1329 } 1330 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1331 if (phydev->speed == SPEED_10) { 1332 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1333 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1334 } else { 1335 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1336 } 1337 } 1338 } 1339 1340 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1341 1342 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1343 { 1344 struct rtl8169_private *tp = netdev_priv(dev); 1345 1346 rtl_lock_work(tp); 1347 wol->supported = WAKE_ANY; 1348 wol->wolopts = tp->saved_wolopts; 1349 rtl_unlock_work(tp); 1350 } 1351 1352 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1353 { 1354 static const struct { 1355 u32 opt; 1356 u16 reg; 1357 u8 mask; 1358 } cfg[] = { 1359 { WAKE_PHY, Config3, LinkUp }, 1360 { WAKE_UCAST, Config5, UWF }, 1361 { WAKE_BCAST, Config5, BWF }, 1362 { WAKE_MCAST, Config5, MWF }, 1363 { WAKE_ANY, Config5, LanWake }, 1364 { WAKE_MAGIC, Config3, MagicPacket } 1365 }; 1366 unsigned int i, tmp = ARRAY_SIZE(cfg); 1367 u8 options; 1368 1369 rtl_unlock_config_regs(tp); 1370 1371 if (rtl_is_8168evl_up(tp)) { 1372 tmp--; 1373 if (wolopts & WAKE_MAGIC) 1374 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100, 1375 MagicPacket_v2); 1376 else 1377 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100, 1378 MagicPacket_v2); 1379 } else if (rtl_is_8125(tp)) { 1380 tmp--; 1381 if (wolopts & WAKE_MAGIC) 1382 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1383 else 1384 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1385 } 1386 1387 for (i = 0; i < tmp; i++) { 1388 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1389 if (wolopts & cfg[i].opt) 1390 options |= cfg[i].mask; 1391 RTL_W8(tp, cfg[i].reg, options); 1392 } 1393 1394 switch (tp->mac_version) { 1395 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1396 options = RTL_R8(tp, Config1) & ~PMEnable; 1397 if (wolopts) 1398 options |= PMEnable; 1399 RTL_W8(tp, Config1, options); 1400 break; 1401 case RTL_GIGA_MAC_VER_34: 1402 case RTL_GIGA_MAC_VER_37: 1403 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_61: 1404 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1405 if (wolopts) 1406 options |= PME_SIGNAL; 1407 RTL_W8(tp, Config2, options); 1408 break; 1409 default: 1410 break; 1411 } 1412 1413 rtl_lock_config_regs(tp); 1414 1415 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1416 tp->dev->wol_enabled = wolopts ? 1 : 0; 1417 } 1418 1419 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1420 { 1421 struct rtl8169_private *tp = netdev_priv(dev); 1422 struct device *d = tp_to_dev(tp); 1423 1424 if (wol->wolopts & ~WAKE_ANY) 1425 return -EINVAL; 1426 1427 pm_runtime_get_noresume(d); 1428 1429 rtl_lock_work(tp); 1430 1431 tp->saved_wolopts = wol->wolopts; 1432 1433 if (pm_runtime_active(d)) 1434 __rtl8169_set_wol(tp, tp->saved_wolopts); 1435 1436 rtl_unlock_work(tp); 1437 1438 pm_runtime_put_noidle(d); 1439 1440 return 0; 1441 } 1442 1443 static void rtl8169_get_drvinfo(struct net_device *dev, 1444 struct ethtool_drvinfo *info) 1445 { 1446 struct rtl8169_private *tp = netdev_priv(dev); 1447 struct rtl_fw *rtl_fw = tp->rtl_fw; 1448 1449 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1450 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1451 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1452 if (rtl_fw) 1453 strlcpy(info->fw_version, rtl_fw->version, 1454 sizeof(info->fw_version)); 1455 } 1456 1457 static int rtl8169_get_regs_len(struct net_device *dev) 1458 { 1459 return R8169_REGS_SIZE; 1460 } 1461 1462 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1463 netdev_features_t features) 1464 { 1465 struct rtl8169_private *tp = netdev_priv(dev); 1466 1467 if (dev->mtu > TD_MSS_MAX) 1468 features &= ~NETIF_F_ALL_TSO; 1469 1470 if (dev->mtu > ETH_DATA_LEN && 1471 tp->mac_version > RTL_GIGA_MAC_VER_06) 1472 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1473 1474 return features; 1475 } 1476 1477 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1478 netdev_features_t features) 1479 { 1480 u32 rx_config = RTL_R32(tp, RxConfig); 1481 1482 if (features & NETIF_F_RXALL) 1483 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1484 else 1485 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1486 1487 if (rtl_is_8125(tp)) { 1488 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1489 rx_config |= RX_VLAN_8125; 1490 else 1491 rx_config &= ~RX_VLAN_8125; 1492 } 1493 1494 RTL_W32(tp, RxConfig, rx_config); 1495 } 1496 1497 static int rtl8169_set_features(struct net_device *dev, 1498 netdev_features_t features) 1499 { 1500 struct rtl8169_private *tp = netdev_priv(dev); 1501 1502 rtl_lock_work(tp); 1503 1504 rtl_set_rx_config_features(tp, features); 1505 1506 if (features & NETIF_F_RXCSUM) 1507 tp->cp_cmd |= RxChkSum; 1508 else 1509 tp->cp_cmd &= ~RxChkSum; 1510 1511 if (!rtl_is_8125(tp)) { 1512 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1513 tp->cp_cmd |= RxVlan; 1514 else 1515 tp->cp_cmd &= ~RxVlan; 1516 } 1517 1518 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1519 rtl_pci_commit(tp); 1520 1521 rtl_unlock_work(tp); 1522 1523 return 0; 1524 } 1525 1526 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1527 { 1528 return (skb_vlan_tag_present(skb)) ? 1529 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1530 } 1531 1532 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1533 { 1534 u32 opts2 = le32_to_cpu(desc->opts2); 1535 1536 if (opts2 & RxVlanTag) 1537 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1538 } 1539 1540 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1541 void *p) 1542 { 1543 struct rtl8169_private *tp = netdev_priv(dev); 1544 u32 __iomem *data = tp->mmio_addr; 1545 u32 *dw = p; 1546 int i; 1547 1548 rtl_lock_work(tp); 1549 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1550 memcpy_fromio(dw++, data++, 4); 1551 rtl_unlock_work(tp); 1552 } 1553 1554 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1555 "tx_packets", 1556 "rx_packets", 1557 "tx_errors", 1558 "rx_errors", 1559 "rx_missed", 1560 "align_errors", 1561 "tx_single_collisions", 1562 "tx_multi_collisions", 1563 "unicast", 1564 "broadcast", 1565 "multicast", 1566 "tx_aborted", 1567 "tx_underrun", 1568 }; 1569 1570 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1571 { 1572 switch (sset) { 1573 case ETH_SS_STATS: 1574 return ARRAY_SIZE(rtl8169_gstrings); 1575 default: 1576 return -EOPNOTSUPP; 1577 } 1578 } 1579 1580 DECLARE_RTL_COND(rtl_counters_cond) 1581 { 1582 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1583 } 1584 1585 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1586 { 1587 dma_addr_t paddr = tp->counters_phys_addr; 1588 u32 cmd; 1589 1590 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1591 rtl_pci_commit(tp); 1592 cmd = (u64)paddr & DMA_BIT_MASK(32); 1593 RTL_W32(tp, CounterAddrLow, cmd); 1594 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1595 1596 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1597 } 1598 1599 static void rtl8169_reset_counters(struct rtl8169_private *tp) 1600 { 1601 /* 1602 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1603 * tally counters. 1604 */ 1605 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) 1606 rtl8169_do_counters(tp, CounterReset); 1607 } 1608 1609 static void rtl8169_update_counters(struct rtl8169_private *tp) 1610 { 1611 u8 val = RTL_R8(tp, ChipCmd); 1612 1613 /* 1614 * Some chips are unable to dump tally counters when the receiver 1615 * is disabled. If 0xff chip may be in a PCI power-save state. 1616 */ 1617 if (val & CmdRxEnb && val != 0xff) 1618 rtl8169_do_counters(tp, CounterDump); 1619 } 1620 1621 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1622 { 1623 struct rtl8169_counters *counters = tp->counters; 1624 1625 /* 1626 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1627 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1628 * reset by a power cycle, while the counter values collected by the 1629 * driver are reset at every driver unload/load cycle. 1630 * 1631 * To make sure the HW values returned by @get_stats64 match the SW 1632 * values, we collect the initial values at first open(*) and use them 1633 * as offsets to normalize the values returned by @get_stats64. 1634 * 1635 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1636 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1637 * set at open time by rtl_hw_start. 1638 */ 1639 1640 if (tp->tc_offset.inited) 1641 return; 1642 1643 rtl8169_reset_counters(tp); 1644 rtl8169_update_counters(tp); 1645 1646 tp->tc_offset.tx_errors = counters->tx_errors; 1647 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1648 tp->tc_offset.tx_aborted = counters->tx_aborted; 1649 tp->tc_offset.rx_missed = counters->rx_missed; 1650 tp->tc_offset.inited = true; 1651 } 1652 1653 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1654 struct ethtool_stats *stats, u64 *data) 1655 { 1656 struct rtl8169_private *tp = netdev_priv(dev); 1657 struct device *d = tp_to_dev(tp); 1658 struct rtl8169_counters *counters = tp->counters; 1659 1660 ASSERT_RTNL(); 1661 1662 pm_runtime_get_noresume(d); 1663 1664 if (pm_runtime_active(d)) 1665 rtl8169_update_counters(tp); 1666 1667 pm_runtime_put_noidle(d); 1668 1669 data[0] = le64_to_cpu(counters->tx_packets); 1670 data[1] = le64_to_cpu(counters->rx_packets); 1671 data[2] = le64_to_cpu(counters->tx_errors); 1672 data[3] = le32_to_cpu(counters->rx_errors); 1673 data[4] = le16_to_cpu(counters->rx_missed); 1674 data[5] = le16_to_cpu(counters->align_errors); 1675 data[6] = le32_to_cpu(counters->tx_one_collision); 1676 data[7] = le32_to_cpu(counters->tx_multi_collision); 1677 data[8] = le64_to_cpu(counters->rx_unicast); 1678 data[9] = le64_to_cpu(counters->rx_broadcast); 1679 data[10] = le32_to_cpu(counters->rx_multicast); 1680 data[11] = le16_to_cpu(counters->tx_aborted); 1681 data[12] = le16_to_cpu(counters->tx_underun); 1682 } 1683 1684 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1685 { 1686 switch(stringset) { 1687 case ETH_SS_STATS: 1688 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1689 break; 1690 } 1691 } 1692 1693 /* 1694 * Interrupt coalescing 1695 * 1696 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1697 * > 8169, 8168 and 810x line of chipsets 1698 * 1699 * 8169, 8168, and 8136(810x) serial chipsets support it. 1700 * 1701 * > 2 - the Tx timer unit at gigabit speed 1702 * 1703 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1704 * (0xe0) bit 1 and bit 0. 1705 * 1706 * For 8169 1707 * bit[1:0] \ speed 1000M 100M 10M 1708 * 0 0 320ns 2.56us 40.96us 1709 * 0 1 2.56us 20.48us 327.7us 1710 * 1 0 5.12us 40.96us 655.4us 1711 * 1 1 10.24us 81.92us 1.31ms 1712 * 1713 * For the other 1714 * bit[1:0] \ speed 1000M 100M 10M 1715 * 0 0 5us 2.56us 40.96us 1716 * 0 1 40us 20.48us 327.7us 1717 * 1 0 80us 40.96us 655.4us 1718 * 1 1 160us 81.92us 1.31ms 1719 */ 1720 1721 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1722 struct rtl_coalesce_info { 1723 u32 speed; 1724 u32 scale_nsecs[4]; 1725 }; 1726 1727 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1728 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1729 1730 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1731 { SPEED_10, COALESCE_DELAY(40960) }, 1732 { SPEED_100, COALESCE_DELAY(2560) }, 1733 { SPEED_1000, COALESCE_DELAY(320) }, 1734 { 0 }, 1735 }; 1736 1737 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1738 { SPEED_10, COALESCE_DELAY(40960) }, 1739 { SPEED_100, COALESCE_DELAY(2560) }, 1740 { SPEED_1000, COALESCE_DELAY(5000) }, 1741 { 0 }, 1742 }; 1743 #undef COALESCE_DELAY 1744 1745 /* get rx/tx scale vector corresponding to current speed */ 1746 static const struct rtl_coalesce_info * 1747 rtl_coalesce_info(struct rtl8169_private *tp) 1748 { 1749 const struct rtl_coalesce_info *ci; 1750 1751 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1752 ci = rtl_coalesce_info_8169; 1753 else 1754 ci = rtl_coalesce_info_8168_8136; 1755 1756 for (; ci->speed; ci++) { 1757 if (tp->phydev->speed == ci->speed) 1758 return ci; 1759 } 1760 1761 return ERR_PTR(-ELNRNG); 1762 } 1763 1764 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1765 { 1766 struct rtl8169_private *tp = netdev_priv(dev); 1767 const struct rtl_coalesce_info *ci; 1768 u32 scale, c_us, c_fr; 1769 u16 intrmit; 1770 1771 if (rtl_is_8125(tp)) 1772 return -EOPNOTSUPP; 1773 1774 memset(ec, 0, sizeof(*ec)); 1775 1776 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1777 ci = rtl_coalesce_info(tp); 1778 if (IS_ERR(ci)) 1779 return PTR_ERR(ci); 1780 1781 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1782 1783 intrmit = RTL_R16(tp, IntrMitigate); 1784 1785 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1786 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1787 1788 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1789 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1790 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1791 1792 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1793 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1794 1795 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1796 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1797 1798 return 0; 1799 } 1800 1801 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1802 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1803 u16 *cp01) 1804 { 1805 const struct rtl_coalesce_info *ci; 1806 u16 i; 1807 1808 ci = rtl_coalesce_info(tp); 1809 if (IS_ERR(ci)) 1810 return PTR_ERR(ci); 1811 1812 for (i = 0; i < 4; i++) { 1813 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1814 *cp01 = i; 1815 return ci->scale_nsecs[i]; 1816 } 1817 } 1818 1819 return -ERANGE; 1820 } 1821 1822 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1823 { 1824 struct rtl8169_private *tp = netdev_priv(dev); 1825 u32 tx_fr = ec->tx_max_coalesced_frames; 1826 u32 rx_fr = ec->rx_max_coalesced_frames; 1827 u32 coal_usec_max, units; 1828 u16 w = 0, cp01 = 0; 1829 int scale; 1830 1831 if (rtl_is_8125(tp)) 1832 return -EOPNOTSUPP; 1833 1834 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1835 return -ERANGE; 1836 1837 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1838 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1839 if (scale < 0) 1840 return scale; 1841 1842 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1843 * not only when usecs=0 because of e.g. the following scenario: 1844 * 1845 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1846 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1847 * - then user does `ethtool -C eth0 rx-usecs 100` 1848 * 1849 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1850 * if we want to ignore rx_frames then it has to be set to 0. 1851 */ 1852 if (rx_fr == 1) 1853 rx_fr = 0; 1854 if (tx_fr == 1) 1855 tx_fr = 0; 1856 1857 /* HW requires time limit to be set if frame limit is set */ 1858 if ((tx_fr && !ec->tx_coalesce_usecs) || 1859 (rx_fr && !ec->rx_coalesce_usecs)) 1860 return -EINVAL; 1861 1862 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1863 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1864 1865 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1866 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1867 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1868 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1869 1870 rtl_lock_work(tp); 1871 1872 RTL_W16(tp, IntrMitigate, w); 1873 1874 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1875 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1876 rtl_pci_commit(tp); 1877 1878 rtl_unlock_work(tp); 1879 1880 return 0; 1881 } 1882 1883 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1884 { 1885 struct rtl8169_private *tp = netdev_priv(dev); 1886 struct device *d = tp_to_dev(tp); 1887 int ret; 1888 1889 if (!rtl_supports_eee(tp)) 1890 return -EOPNOTSUPP; 1891 1892 pm_runtime_get_noresume(d); 1893 1894 if (!pm_runtime_active(d)) { 1895 ret = -EOPNOTSUPP; 1896 } else { 1897 ret = phy_ethtool_get_eee(tp->phydev, data); 1898 } 1899 1900 pm_runtime_put_noidle(d); 1901 1902 return ret; 1903 } 1904 1905 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1906 { 1907 struct rtl8169_private *tp = netdev_priv(dev); 1908 struct device *d = tp_to_dev(tp); 1909 int ret; 1910 1911 if (!rtl_supports_eee(tp)) 1912 return -EOPNOTSUPP; 1913 1914 pm_runtime_get_noresume(d); 1915 1916 if (!pm_runtime_active(d)) { 1917 ret = -EOPNOTSUPP; 1918 goto out; 1919 } 1920 1921 ret = phy_ethtool_set_eee(tp->phydev, data); 1922 1923 if (!ret) 1924 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1925 MDIO_AN_EEE_ADV); 1926 out: 1927 pm_runtime_put_noidle(d); 1928 return ret; 1929 } 1930 1931 static const struct ethtool_ops rtl8169_ethtool_ops = { 1932 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1933 ETHTOOL_COALESCE_MAX_FRAMES, 1934 .get_drvinfo = rtl8169_get_drvinfo, 1935 .get_regs_len = rtl8169_get_regs_len, 1936 .get_link = ethtool_op_get_link, 1937 .get_coalesce = rtl_get_coalesce, 1938 .set_coalesce = rtl_set_coalesce, 1939 .get_regs = rtl8169_get_regs, 1940 .get_wol = rtl8169_get_wol, 1941 .set_wol = rtl8169_set_wol, 1942 .get_strings = rtl8169_get_strings, 1943 .get_sset_count = rtl8169_get_sset_count, 1944 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1945 .get_ts_info = ethtool_op_get_ts_info, 1946 .nway_reset = phy_ethtool_nway_reset, 1947 .get_eee = rtl8169_get_eee, 1948 .set_eee = rtl8169_set_eee, 1949 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1950 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1951 }; 1952 1953 static void rtl_enable_eee(struct rtl8169_private *tp) 1954 { 1955 struct phy_device *phydev = tp->phydev; 1956 int adv; 1957 1958 /* respect EEE advertisement the user may have set */ 1959 if (tp->eee_adv >= 0) 1960 adv = tp->eee_adv; 1961 else 1962 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1963 1964 if (adv >= 0) 1965 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1966 } 1967 1968 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1969 { 1970 /* 1971 * The driver currently handles the 8168Bf and the 8168Be identically 1972 * but they can be identified more specifically through the test below 1973 * if needed: 1974 * 1975 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1976 * 1977 * Same thing for the 8101Eb and the 8101Ec: 1978 * 1979 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1980 */ 1981 static const struct rtl_mac_info { 1982 u16 mask; 1983 u16 val; 1984 enum mac_version ver; 1985 } mac_info[] = { 1986 /* 8125 family. */ 1987 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 1988 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 1989 1990 /* RTL8117 */ 1991 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 1992 1993 /* 8168EP family. */ 1994 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 1995 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 1996 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 1997 1998 /* 8168H family. */ 1999 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2000 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2001 2002 /* 8168G family. */ 2003 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2004 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2005 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2006 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2007 2008 /* 8168F family. */ 2009 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2010 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2011 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2012 2013 /* 8168E family. */ 2014 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2015 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2016 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2017 2018 /* 8168D family. */ 2019 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2020 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2021 2022 /* 8168DP family. */ 2023 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2024 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2025 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2026 2027 /* 8168C family. */ 2028 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2029 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2030 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2031 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2032 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2033 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2034 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2035 2036 /* 8168B family. */ 2037 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2038 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2039 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2040 2041 /* 8101 family. */ 2042 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2043 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2044 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2045 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2046 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2047 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2048 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2049 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2050 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2051 /* RTL8401, reportedly works if treated as RTL8101e */ 2052 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_13 }, 2053 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2054 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2055 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2056 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2057 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2058 /* FIXME: where did these entries come from ? -- FR */ 2059 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2060 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2061 2062 /* 8110 family. */ 2063 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2064 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2065 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2066 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2067 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2068 2069 /* Catch-all */ 2070 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2071 }; 2072 const struct rtl_mac_info *p = mac_info; 2073 enum mac_version ver; 2074 2075 while ((xid & p->mask) != p->val) 2076 p++; 2077 ver = p->ver; 2078 2079 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2080 if (ver == RTL_GIGA_MAC_VER_42) 2081 ver = RTL_GIGA_MAC_VER_43; 2082 else if (ver == RTL_GIGA_MAC_VER_45) 2083 ver = RTL_GIGA_MAC_VER_47; 2084 else if (ver == RTL_GIGA_MAC_VER_46) 2085 ver = RTL_GIGA_MAC_VER_48; 2086 } 2087 2088 return ver; 2089 } 2090 2091 static void rtl_release_firmware(struct rtl8169_private *tp) 2092 { 2093 if (tp->rtl_fw) { 2094 rtl_fw_release_firmware(tp->rtl_fw); 2095 kfree(tp->rtl_fw); 2096 tp->rtl_fw = NULL; 2097 } 2098 } 2099 2100 void r8169_apply_firmware(struct rtl8169_private *tp) 2101 { 2102 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2103 if (tp->rtl_fw) 2104 rtl_fw_write_firmware(tp, tp->rtl_fw); 2105 } 2106 2107 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2108 { 2109 /* Adjust EEE LED frequency */ 2110 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2111 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2112 2113 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003); 2114 } 2115 2116 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2117 { 2118 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2119 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2120 } 2121 2122 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2123 { 2124 const u16 w[] = { 2125 addr[0] | (addr[1] << 8), 2126 addr[2] | (addr[3] << 8), 2127 addr[4] | (addr[5] << 8) 2128 }; 2129 2130 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2131 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2132 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2133 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2134 } 2135 2136 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2137 { 2138 u16 data1, data2, ioffset; 2139 2140 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2141 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2142 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2143 2144 ioffset = (data2 >> 1) & 0x7ff8; 2145 ioffset |= data2 & 0x0007; 2146 if (data1 & BIT(7)) 2147 ioffset |= BIT(15); 2148 2149 return ioffset; 2150 } 2151 2152 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2153 { 2154 set_bit(flag, tp->wk.flags); 2155 schedule_work(&tp->wk.work); 2156 } 2157 2158 static void rtl8169_init_phy(struct rtl8169_private *tp) 2159 { 2160 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2161 2162 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2163 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2164 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2165 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2166 RTL_W8(tp, 0x82, 0x01); 2167 } 2168 2169 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2170 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2171 tp->pci_dev->subsystem_device == 0xe000) 2172 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2173 2174 /* We may have called phy_speed_down before */ 2175 phy_speed_up(tp->phydev); 2176 2177 if (rtl_supports_eee(tp)) 2178 rtl_enable_eee(tp); 2179 2180 genphy_soft_reset(tp->phydev); 2181 } 2182 2183 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 2184 { 2185 rtl_lock_work(tp); 2186 2187 rtl_unlock_config_regs(tp); 2188 2189 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 2190 rtl_pci_commit(tp); 2191 2192 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2193 rtl_pci_commit(tp); 2194 2195 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2196 rtl_rar_exgmac_set(tp, addr); 2197 2198 rtl_lock_config_regs(tp); 2199 2200 rtl_unlock_work(tp); 2201 } 2202 2203 static int rtl_set_mac_address(struct net_device *dev, void *p) 2204 { 2205 struct rtl8169_private *tp = netdev_priv(dev); 2206 struct device *d = tp_to_dev(tp); 2207 int ret; 2208 2209 ret = eth_mac_addr(dev, p); 2210 if (ret) 2211 return ret; 2212 2213 pm_runtime_get_noresume(d); 2214 2215 if (pm_runtime_active(d)) 2216 rtl_rar_set(tp, dev->dev_addr); 2217 2218 pm_runtime_put_noidle(d); 2219 2220 return 0; 2221 } 2222 2223 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 2224 { 2225 switch (tp->mac_version) { 2226 case RTL_GIGA_MAC_VER_25: 2227 case RTL_GIGA_MAC_VER_26: 2228 case RTL_GIGA_MAC_VER_29: 2229 case RTL_GIGA_MAC_VER_30: 2230 case RTL_GIGA_MAC_VER_32: 2231 case RTL_GIGA_MAC_VER_33: 2232 case RTL_GIGA_MAC_VER_34: 2233 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61: 2234 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2235 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2236 break; 2237 default: 2238 break; 2239 } 2240 } 2241 2242 static void rtl_pll_power_down(struct rtl8169_private *tp) 2243 { 2244 if (r8168_check_dash(tp)) 2245 return; 2246 2247 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2248 tp->mac_version == RTL_GIGA_MAC_VER_33) 2249 rtl_ephy_write(tp, 0x19, 0xff64); 2250 2251 if (device_may_wakeup(tp_to_dev(tp))) { 2252 phy_speed_down(tp->phydev, false); 2253 rtl_wol_suspend_quirk(tp); 2254 return; 2255 } 2256 2257 switch (tp->mac_version) { 2258 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2259 case RTL_GIGA_MAC_VER_37: 2260 case RTL_GIGA_MAC_VER_39: 2261 case RTL_GIGA_MAC_VER_43: 2262 case RTL_GIGA_MAC_VER_44: 2263 case RTL_GIGA_MAC_VER_45: 2264 case RTL_GIGA_MAC_VER_46: 2265 case RTL_GIGA_MAC_VER_47: 2266 case RTL_GIGA_MAC_VER_48: 2267 case RTL_GIGA_MAC_VER_50: 2268 case RTL_GIGA_MAC_VER_51: 2269 case RTL_GIGA_MAC_VER_52: 2270 case RTL_GIGA_MAC_VER_60: 2271 case RTL_GIGA_MAC_VER_61: 2272 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2273 break; 2274 case RTL_GIGA_MAC_VER_40: 2275 case RTL_GIGA_MAC_VER_41: 2276 case RTL_GIGA_MAC_VER_49: 2277 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 2278 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2279 break; 2280 default: 2281 break; 2282 } 2283 } 2284 2285 static void rtl_pll_power_up(struct rtl8169_private *tp) 2286 { 2287 switch (tp->mac_version) { 2288 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2289 case RTL_GIGA_MAC_VER_37: 2290 case RTL_GIGA_MAC_VER_39: 2291 case RTL_GIGA_MAC_VER_43: 2292 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 2293 break; 2294 case RTL_GIGA_MAC_VER_44: 2295 case RTL_GIGA_MAC_VER_45: 2296 case RTL_GIGA_MAC_VER_46: 2297 case RTL_GIGA_MAC_VER_47: 2298 case RTL_GIGA_MAC_VER_48: 2299 case RTL_GIGA_MAC_VER_50: 2300 case RTL_GIGA_MAC_VER_51: 2301 case RTL_GIGA_MAC_VER_52: 2302 case RTL_GIGA_MAC_VER_60: 2303 case RTL_GIGA_MAC_VER_61: 2304 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2305 break; 2306 case RTL_GIGA_MAC_VER_40: 2307 case RTL_GIGA_MAC_VER_41: 2308 case RTL_GIGA_MAC_VER_49: 2309 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2310 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000); 2311 break; 2312 default: 2313 break; 2314 } 2315 2316 phy_resume(tp->phydev); 2317 } 2318 2319 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2320 { 2321 switch (tp->mac_version) { 2322 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2323 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2324 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2325 break; 2326 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2327 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2328 case RTL_GIGA_MAC_VER_38: 2329 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2330 break; 2331 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2332 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2333 break; 2334 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2335 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2336 break; 2337 default: 2338 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2339 break; 2340 } 2341 } 2342 2343 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2344 { 2345 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2346 } 2347 2348 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2349 { 2350 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2351 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2352 } 2353 2354 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2355 { 2356 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2357 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2358 } 2359 2360 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2361 { 2362 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2363 } 2364 2365 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2366 { 2367 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2368 } 2369 2370 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2371 { 2372 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2373 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2374 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2375 } 2376 2377 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2378 { 2379 RTL_W8(tp, MaxTxPacketSize, 0x0c); 2380 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2381 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2382 } 2383 2384 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2385 { 2386 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2387 } 2388 2389 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2390 { 2391 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2392 } 2393 2394 static void rtl_jumbo_config(struct rtl8169_private *tp) 2395 { 2396 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2397 2398 rtl_unlock_config_regs(tp); 2399 switch (tp->mac_version) { 2400 case RTL_GIGA_MAC_VER_12: 2401 case RTL_GIGA_MAC_VER_17: 2402 if (jumbo) { 2403 pcie_set_readrq(tp->pci_dev, 512); 2404 r8168b_1_hw_jumbo_enable(tp); 2405 } else { 2406 r8168b_1_hw_jumbo_disable(tp); 2407 } 2408 break; 2409 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2410 if (jumbo) { 2411 pcie_set_readrq(tp->pci_dev, 512); 2412 r8168c_hw_jumbo_enable(tp); 2413 } else { 2414 r8168c_hw_jumbo_disable(tp); 2415 } 2416 break; 2417 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2418 if (jumbo) 2419 r8168dp_hw_jumbo_enable(tp); 2420 else 2421 r8168dp_hw_jumbo_disable(tp); 2422 break; 2423 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2424 if (jumbo) { 2425 pcie_set_readrq(tp->pci_dev, 512); 2426 r8168e_hw_jumbo_enable(tp); 2427 } else { 2428 r8168e_hw_jumbo_disable(tp); 2429 } 2430 break; 2431 default: 2432 break; 2433 } 2434 rtl_lock_config_regs(tp); 2435 2436 if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2437 pcie_set_readrq(tp->pci_dev, 4096); 2438 } 2439 2440 DECLARE_RTL_COND(rtl_chipcmd_cond) 2441 { 2442 return RTL_R8(tp, ChipCmd) & CmdReset; 2443 } 2444 2445 static void rtl_hw_reset(struct rtl8169_private *tp) 2446 { 2447 RTL_W8(tp, ChipCmd, CmdReset); 2448 2449 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2450 } 2451 2452 static void rtl_request_firmware(struct rtl8169_private *tp) 2453 { 2454 struct rtl_fw *rtl_fw; 2455 2456 /* firmware loaded already or no firmware available */ 2457 if (tp->rtl_fw || !tp->fw_name) 2458 return; 2459 2460 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2461 if (!rtl_fw) 2462 return; 2463 2464 rtl_fw->phy_write = rtl_writephy; 2465 rtl_fw->phy_read = rtl_readphy; 2466 rtl_fw->mac_mcu_write = mac_mcu_write; 2467 rtl_fw->mac_mcu_read = mac_mcu_read; 2468 rtl_fw->fw_name = tp->fw_name; 2469 rtl_fw->dev = tp_to_dev(tp); 2470 2471 if (rtl_fw_request_firmware(rtl_fw)) 2472 kfree(rtl_fw); 2473 else 2474 tp->rtl_fw = rtl_fw; 2475 } 2476 2477 static void rtl_rx_close(struct rtl8169_private *tp) 2478 { 2479 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2480 } 2481 2482 DECLARE_RTL_COND(rtl_npq_cond) 2483 { 2484 return RTL_R8(tp, TxPoll) & NPQ; 2485 } 2486 2487 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2488 { 2489 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2490 } 2491 2492 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2493 { 2494 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2495 } 2496 2497 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2498 { 2499 switch (tp->mac_version) { 2500 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2501 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2502 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2503 break; 2504 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2505 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2506 break; 2507 default: 2508 break; 2509 } 2510 } 2511 2512 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2513 { 2514 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2515 fsleep(2000); 2516 rtl_wait_txrx_fifo_empty(tp); 2517 } 2518 2519 static void rtl8169_hw_reset(struct rtl8169_private *tp) 2520 { 2521 /* Disable interrupts */ 2522 rtl8169_irq_mask_and_ack(tp); 2523 2524 rtl_rx_close(tp); 2525 2526 switch (tp->mac_version) { 2527 case RTL_GIGA_MAC_VER_27: 2528 case RTL_GIGA_MAC_VER_28: 2529 case RTL_GIGA_MAC_VER_31: 2530 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 2531 break; 2532 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2533 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2534 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 2535 break; 2536 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 2537 rtl_enable_rxdvgate(tp); 2538 fsleep(2000); 2539 break; 2540 default: 2541 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2542 udelay(100); 2543 break; 2544 } 2545 2546 rtl_hw_reset(tp); 2547 } 2548 2549 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2550 { 2551 u32 val = TX_DMA_BURST << TxDMAShift | 2552 InterFrameGap << TxInterFrameGapShift; 2553 2554 if (rtl_is_8168evl_up(tp)) 2555 val |= TXCFG_AUTO_FIFO; 2556 2557 RTL_W32(tp, TxConfig, val); 2558 } 2559 2560 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2561 { 2562 /* Low hurts. Let's disable the filtering. */ 2563 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2564 } 2565 2566 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2567 { 2568 /* 2569 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2570 * register to be written before TxDescAddrLow to work. 2571 * Switching from MMIO to I/O access fixes the issue as well. 2572 */ 2573 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2574 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2575 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2576 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2577 } 2578 2579 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2580 { 2581 u32 val; 2582 2583 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2584 val = 0x000fff00; 2585 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2586 val = 0x00ffff00; 2587 else 2588 return; 2589 2590 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2591 val |= 0xff; 2592 2593 RTL_W32(tp, 0x7c, val); 2594 } 2595 2596 static void rtl_set_rx_mode(struct net_device *dev) 2597 { 2598 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2599 /* Multicast hash filter */ 2600 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2601 struct rtl8169_private *tp = netdev_priv(dev); 2602 u32 tmp; 2603 2604 if (dev->flags & IFF_PROMISC) { 2605 rx_mode |= AcceptAllPhys; 2606 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2607 dev->flags & IFF_ALLMULTI || 2608 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2609 /* accept all multicasts */ 2610 } else if (netdev_mc_empty(dev)) { 2611 rx_mode &= ~AcceptMulticast; 2612 } else { 2613 struct netdev_hw_addr *ha; 2614 2615 mc_filter[1] = mc_filter[0] = 0; 2616 netdev_for_each_mc_addr(ha, dev) { 2617 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2618 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2619 } 2620 2621 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2622 tmp = mc_filter[0]; 2623 mc_filter[0] = swab32(mc_filter[1]); 2624 mc_filter[1] = swab32(tmp); 2625 } 2626 } 2627 2628 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2629 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2630 2631 tmp = RTL_R32(tp, RxConfig); 2632 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2633 } 2634 2635 DECLARE_RTL_COND(rtl_csiar_cond) 2636 { 2637 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2638 } 2639 2640 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2641 { 2642 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2643 2644 RTL_W32(tp, CSIDR, value); 2645 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2646 CSIAR_BYTE_ENABLE | func << 16); 2647 2648 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2649 } 2650 2651 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2652 { 2653 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2654 2655 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2656 CSIAR_BYTE_ENABLE); 2657 2658 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2659 RTL_R32(tp, CSIDR) : ~0; 2660 } 2661 2662 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2663 { 2664 struct pci_dev *pdev = tp->pci_dev; 2665 u32 csi; 2666 2667 /* According to Realtek the value at config space address 0x070f 2668 * controls the L0s/L1 entrance latency. We try standard ECAM access 2669 * first and if it fails fall back to CSI. 2670 */ 2671 if (pdev->cfg_size > 0x070f && 2672 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2673 return; 2674 2675 netdev_notice_once(tp->dev, 2676 "No native access to PCI extended config space, falling back to CSI\n"); 2677 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2678 rtl_csi_write(tp, 0x070c, csi | val << 24); 2679 } 2680 2681 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2682 { 2683 rtl_csi_access_enable(tp, 0x27); 2684 } 2685 2686 struct ephy_info { 2687 unsigned int offset; 2688 u16 mask; 2689 u16 bits; 2690 }; 2691 2692 static void __rtl_ephy_init(struct rtl8169_private *tp, 2693 const struct ephy_info *e, int len) 2694 { 2695 u16 w; 2696 2697 while (len-- > 0) { 2698 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2699 rtl_ephy_write(tp, e->offset, w); 2700 e++; 2701 } 2702 } 2703 2704 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2705 2706 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2707 { 2708 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2709 PCI_EXP_LNKCTL_CLKREQ_EN); 2710 } 2711 2712 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2713 { 2714 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2715 PCI_EXP_LNKCTL_CLKREQ_EN); 2716 } 2717 2718 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2719 { 2720 /* work around an issue when PCI reset occurs during L2/L3 state */ 2721 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2722 } 2723 2724 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2725 { 2726 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2727 if (enable && tp->aspm_manageable) { 2728 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2729 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2730 } else { 2731 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2732 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2733 } 2734 2735 udelay(10); 2736 } 2737 2738 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2739 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2740 { 2741 /* Usage of dynamic vs. static FIFO is controlled by bit 2742 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2743 */ 2744 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2745 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2746 } 2747 2748 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2749 u8 low, u8 high) 2750 { 2751 /* FIFO thresholds for pause flow control */ 2752 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2753 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2754 } 2755 2756 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2757 { 2758 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2759 } 2760 2761 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2762 { 2763 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2764 2765 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2766 2767 rtl_disable_clock_request(tp); 2768 } 2769 2770 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2771 { 2772 static const struct ephy_info e_info_8168cp[] = { 2773 { 0x01, 0, 0x0001 }, 2774 { 0x02, 0x0800, 0x1000 }, 2775 { 0x03, 0, 0x0042 }, 2776 { 0x06, 0x0080, 0x0000 }, 2777 { 0x07, 0, 0x2000 } 2778 }; 2779 2780 rtl_set_def_aspm_entry_latency(tp); 2781 2782 rtl_ephy_init(tp, e_info_8168cp); 2783 2784 __rtl_hw_start_8168cp(tp); 2785 } 2786 2787 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2788 { 2789 rtl_set_def_aspm_entry_latency(tp); 2790 2791 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2792 } 2793 2794 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2795 { 2796 rtl_set_def_aspm_entry_latency(tp); 2797 2798 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2799 2800 /* Magic. */ 2801 RTL_W8(tp, DBG_REG, 0x20); 2802 } 2803 2804 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2805 { 2806 static const struct ephy_info e_info_8168c_1[] = { 2807 { 0x02, 0x0800, 0x1000 }, 2808 { 0x03, 0, 0x0002 }, 2809 { 0x06, 0x0080, 0x0000 } 2810 }; 2811 2812 rtl_set_def_aspm_entry_latency(tp); 2813 2814 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2815 2816 rtl_ephy_init(tp, e_info_8168c_1); 2817 2818 __rtl_hw_start_8168cp(tp); 2819 } 2820 2821 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2822 { 2823 static const struct ephy_info e_info_8168c_2[] = { 2824 { 0x01, 0, 0x0001 }, 2825 { 0x03, 0x0400, 0x0020 } 2826 }; 2827 2828 rtl_set_def_aspm_entry_latency(tp); 2829 2830 rtl_ephy_init(tp, e_info_8168c_2); 2831 2832 __rtl_hw_start_8168cp(tp); 2833 } 2834 2835 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2836 { 2837 rtl_hw_start_8168c_2(tp); 2838 } 2839 2840 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2841 { 2842 rtl_set_def_aspm_entry_latency(tp); 2843 2844 __rtl_hw_start_8168cp(tp); 2845 } 2846 2847 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2848 { 2849 rtl_set_def_aspm_entry_latency(tp); 2850 2851 rtl_disable_clock_request(tp); 2852 } 2853 2854 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2855 { 2856 static const struct ephy_info e_info_8168d_4[] = { 2857 { 0x0b, 0x0000, 0x0048 }, 2858 { 0x19, 0x0020, 0x0050 }, 2859 { 0x0c, 0x0100, 0x0020 }, 2860 { 0x10, 0x0004, 0x0000 }, 2861 }; 2862 2863 rtl_set_def_aspm_entry_latency(tp); 2864 2865 rtl_ephy_init(tp, e_info_8168d_4); 2866 2867 rtl_enable_clock_request(tp); 2868 } 2869 2870 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2871 { 2872 static const struct ephy_info e_info_8168e_1[] = { 2873 { 0x00, 0x0200, 0x0100 }, 2874 { 0x00, 0x0000, 0x0004 }, 2875 { 0x06, 0x0002, 0x0001 }, 2876 { 0x06, 0x0000, 0x0030 }, 2877 { 0x07, 0x0000, 0x2000 }, 2878 { 0x00, 0x0000, 0x0020 }, 2879 { 0x03, 0x5800, 0x2000 }, 2880 { 0x03, 0x0000, 0x0001 }, 2881 { 0x01, 0x0800, 0x1000 }, 2882 { 0x07, 0x0000, 0x4000 }, 2883 { 0x1e, 0x0000, 0x2000 }, 2884 { 0x19, 0xffff, 0xfe6c }, 2885 { 0x0a, 0x0000, 0x0040 } 2886 }; 2887 2888 rtl_set_def_aspm_entry_latency(tp); 2889 2890 rtl_ephy_init(tp, e_info_8168e_1); 2891 2892 rtl_disable_clock_request(tp); 2893 2894 /* Reset tx FIFO pointer */ 2895 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2896 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2897 2898 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2899 } 2900 2901 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2902 { 2903 static const struct ephy_info e_info_8168e_2[] = { 2904 { 0x09, 0x0000, 0x0080 }, 2905 { 0x19, 0x0000, 0x0224 }, 2906 { 0x00, 0x0000, 0x0004 }, 2907 { 0x0c, 0x3df0, 0x0200 }, 2908 }; 2909 2910 rtl_set_def_aspm_entry_latency(tp); 2911 2912 rtl_ephy_init(tp, e_info_8168e_2); 2913 2914 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2915 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2916 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2917 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2918 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2919 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 2920 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 2921 2922 rtl_disable_clock_request(tp); 2923 2924 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2925 2926 rtl8168_config_eee_mac(tp); 2927 2928 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2929 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2930 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2931 2932 rtl_hw_aspm_clkreq_enable(tp, true); 2933 } 2934 2935 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2936 { 2937 rtl_set_def_aspm_entry_latency(tp); 2938 2939 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2940 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2941 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2942 rtl_reset_packet_filter(tp); 2943 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4)); 2944 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4)); 2945 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2946 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2947 2948 rtl_disable_clock_request(tp); 2949 2950 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2951 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2952 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2953 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2954 2955 rtl8168_config_eee_mac(tp); 2956 } 2957 2958 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2959 { 2960 static const struct ephy_info e_info_8168f_1[] = { 2961 { 0x06, 0x00c0, 0x0020 }, 2962 { 0x08, 0x0001, 0x0002 }, 2963 { 0x09, 0x0000, 0x0080 }, 2964 { 0x19, 0x0000, 0x0224 }, 2965 { 0x00, 0x0000, 0x0004 }, 2966 { 0x0c, 0x3df0, 0x0200 }, 2967 }; 2968 2969 rtl_hw_start_8168f(tp); 2970 2971 rtl_ephy_init(tp, e_info_8168f_1); 2972 2973 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00); 2974 } 2975 2976 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2977 { 2978 static const struct ephy_info e_info_8168f_1[] = { 2979 { 0x06, 0x00c0, 0x0020 }, 2980 { 0x0f, 0xffff, 0x5200 }, 2981 { 0x19, 0x0000, 0x0224 }, 2982 { 0x00, 0x0000, 0x0004 }, 2983 { 0x0c, 0x3df0, 0x0200 }, 2984 }; 2985 2986 rtl_hw_start_8168f(tp); 2987 rtl_pcie_state_l2l3_disable(tp); 2988 2989 rtl_ephy_init(tp, e_info_8168f_1); 2990 2991 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00); 2992 } 2993 2994 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2995 { 2996 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2997 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2998 2999 rtl_set_def_aspm_entry_latency(tp); 3000 3001 rtl_reset_packet_filter(tp); 3002 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3003 3004 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3005 3006 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3007 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3008 3009 rtl8168_config_eee_mac(tp); 3010 3011 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 3012 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3013 3014 rtl_pcie_state_l2l3_disable(tp); 3015 } 3016 3017 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3018 { 3019 static const struct ephy_info e_info_8168g_1[] = { 3020 { 0x00, 0x0008, 0x0000 }, 3021 { 0x0c, 0x3ff0, 0x0820 }, 3022 { 0x1e, 0x0000, 0x0001 }, 3023 { 0x19, 0x8000, 0x0000 } 3024 }; 3025 3026 rtl_hw_start_8168g(tp); 3027 3028 /* disable aspm and clock request before access ephy */ 3029 rtl_hw_aspm_clkreq_enable(tp, false); 3030 rtl_ephy_init(tp, e_info_8168g_1); 3031 rtl_hw_aspm_clkreq_enable(tp, true); 3032 } 3033 3034 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3035 { 3036 static const struct ephy_info e_info_8168g_2[] = { 3037 { 0x00, 0x0008, 0x0000 }, 3038 { 0x0c, 0x3ff0, 0x0820 }, 3039 { 0x19, 0xffff, 0x7c00 }, 3040 { 0x1e, 0xffff, 0x20eb }, 3041 { 0x0d, 0xffff, 0x1666 }, 3042 { 0x00, 0xffff, 0x10a3 }, 3043 { 0x06, 0xffff, 0xf050 }, 3044 { 0x04, 0x0000, 0x0010 }, 3045 { 0x1d, 0x4000, 0x0000 }, 3046 }; 3047 3048 rtl_hw_start_8168g(tp); 3049 3050 /* disable aspm and clock request before access ephy */ 3051 rtl_hw_aspm_clkreq_enable(tp, false); 3052 rtl_ephy_init(tp, e_info_8168g_2); 3053 } 3054 3055 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3056 { 3057 static const struct ephy_info e_info_8411_2[] = { 3058 { 0x00, 0x0008, 0x0000 }, 3059 { 0x0c, 0x37d0, 0x0820 }, 3060 { 0x1e, 0x0000, 0x0001 }, 3061 { 0x19, 0x8021, 0x0000 }, 3062 { 0x1e, 0x0000, 0x2000 }, 3063 { 0x0d, 0x0100, 0x0200 }, 3064 { 0x00, 0x0000, 0x0080 }, 3065 { 0x06, 0x0000, 0x0010 }, 3066 { 0x04, 0x0000, 0x0010 }, 3067 { 0x1d, 0x0000, 0x4000 }, 3068 }; 3069 3070 rtl_hw_start_8168g(tp); 3071 3072 /* disable aspm and clock request before access ephy */ 3073 rtl_hw_aspm_clkreq_enable(tp, false); 3074 rtl_ephy_init(tp, e_info_8411_2); 3075 3076 /* The following Realtek-provided magic fixes an issue with the RX unit 3077 * getting confused after the PHY having been powered-down. 3078 */ 3079 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3080 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3081 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3082 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3083 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3084 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3085 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3086 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3087 mdelay(3); 3088 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3089 3090 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3091 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3092 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3093 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3094 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3095 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3096 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3097 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3098 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3099 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3100 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3101 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3102 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3103 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3104 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3105 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3106 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3107 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3108 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3109 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3110 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3111 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3112 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3113 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3114 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3115 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3116 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3117 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3118 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3119 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3120 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3121 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3122 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3123 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3124 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3125 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3126 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3127 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3128 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3129 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3130 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3131 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3132 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3133 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3134 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3135 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3136 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3137 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3138 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3139 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3140 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3141 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3142 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3143 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3144 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3145 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3146 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3147 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3148 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3149 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3150 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3151 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3152 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3153 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3154 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3155 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3156 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3157 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3158 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3159 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3160 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3161 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3162 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3163 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3164 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3165 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3166 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3167 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3168 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3169 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3170 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3171 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3172 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3173 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3174 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3175 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3176 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3177 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3178 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3179 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3180 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3181 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3182 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3183 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3184 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3185 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3186 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3187 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3188 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3189 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3190 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3191 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3192 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3193 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3194 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3195 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3196 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3197 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3198 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3199 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3200 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3201 3202 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3203 3204 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3205 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3206 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3207 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3208 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3209 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3210 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3211 3212 rtl_hw_aspm_clkreq_enable(tp, true); 3213 } 3214 3215 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3216 { 3217 static const struct ephy_info e_info_8168h_1[] = { 3218 { 0x1e, 0x0800, 0x0001 }, 3219 { 0x1d, 0x0000, 0x0800 }, 3220 { 0x05, 0xffff, 0x2089 }, 3221 { 0x06, 0xffff, 0x5881 }, 3222 { 0x04, 0xffff, 0x854a }, 3223 { 0x01, 0xffff, 0x068b } 3224 }; 3225 int rg_saw_cnt; 3226 3227 /* disable aspm and clock request before access ephy */ 3228 rtl_hw_aspm_clkreq_enable(tp, false); 3229 rtl_ephy_init(tp, e_info_8168h_1); 3230 3231 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3232 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3233 3234 rtl_set_def_aspm_entry_latency(tp); 3235 3236 rtl_reset_packet_filter(tp); 3237 3238 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); 3239 3240 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00); 3241 3242 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3243 3244 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3245 3246 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3247 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3248 3249 rtl8168_config_eee_mac(tp); 3250 3251 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3252 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3253 3254 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3255 3256 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3257 3258 rtl_pcie_state_l2l3_disable(tp); 3259 3260 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3261 if (rg_saw_cnt > 0) { 3262 u16 sw_cnt_1ms_ini; 3263 3264 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3265 sw_cnt_1ms_ini &= 0x0fff; 3266 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3267 } 3268 3269 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3270 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3271 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3272 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3273 3274 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3275 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3276 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3277 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3278 3279 rtl_hw_aspm_clkreq_enable(tp, true); 3280 } 3281 3282 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3283 { 3284 rtl8168ep_stop_cmac(tp); 3285 3286 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3287 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3288 3289 rtl_set_def_aspm_entry_latency(tp); 3290 3291 rtl_reset_packet_filter(tp); 3292 3293 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); 3294 3295 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3296 3297 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3298 3299 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3300 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3301 3302 rtl8168_config_eee_mac(tp); 3303 3304 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06); 3305 3306 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3307 3308 rtl_pcie_state_l2l3_disable(tp); 3309 } 3310 3311 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3312 { 3313 static const struct ephy_info e_info_8168ep_1[] = { 3314 { 0x00, 0xffff, 0x10ab }, 3315 { 0x06, 0xffff, 0xf030 }, 3316 { 0x08, 0xffff, 0x2006 }, 3317 { 0x0d, 0xffff, 0x1666 }, 3318 { 0x0c, 0x3ff0, 0x0000 } 3319 }; 3320 3321 /* disable aspm and clock request before access ephy */ 3322 rtl_hw_aspm_clkreq_enable(tp, false); 3323 rtl_ephy_init(tp, e_info_8168ep_1); 3324 3325 rtl_hw_start_8168ep(tp); 3326 3327 rtl_hw_aspm_clkreq_enable(tp, true); 3328 } 3329 3330 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3331 { 3332 static const struct ephy_info e_info_8168ep_2[] = { 3333 { 0x00, 0xffff, 0x10a3 }, 3334 { 0x19, 0xffff, 0xfc00 }, 3335 { 0x1e, 0xffff, 0x20ea } 3336 }; 3337 3338 /* disable aspm and clock request before access ephy */ 3339 rtl_hw_aspm_clkreq_enable(tp, false); 3340 rtl_ephy_init(tp, e_info_8168ep_2); 3341 3342 rtl_hw_start_8168ep(tp); 3343 3344 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3345 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3346 3347 rtl_hw_aspm_clkreq_enable(tp, true); 3348 } 3349 3350 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3351 { 3352 static const struct ephy_info e_info_8168ep_3[] = { 3353 { 0x00, 0x0000, 0x0080 }, 3354 { 0x0d, 0x0100, 0x0200 }, 3355 { 0x19, 0x8021, 0x0000 }, 3356 { 0x1e, 0x0000, 0x2000 }, 3357 }; 3358 3359 /* disable aspm and clock request before access ephy */ 3360 rtl_hw_aspm_clkreq_enable(tp, false); 3361 rtl_ephy_init(tp, e_info_8168ep_3); 3362 3363 rtl_hw_start_8168ep(tp); 3364 3365 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3366 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3367 3368 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3369 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3370 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3371 3372 rtl_hw_aspm_clkreq_enable(tp, true); 3373 } 3374 3375 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3376 { 3377 static const struct ephy_info e_info_8117[] = { 3378 { 0x19, 0x0040, 0x1100 }, 3379 { 0x59, 0x0040, 0x1100 }, 3380 }; 3381 int rg_saw_cnt; 3382 3383 rtl8168ep_stop_cmac(tp); 3384 3385 /* disable aspm and clock request before access ephy */ 3386 rtl_hw_aspm_clkreq_enable(tp, false); 3387 rtl_ephy_init(tp, e_info_8117); 3388 3389 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3390 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3391 3392 rtl_set_def_aspm_entry_latency(tp); 3393 3394 rtl_reset_packet_filter(tp); 3395 3396 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90); 3397 3398 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3399 3400 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3401 3402 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3403 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3404 3405 rtl8168_config_eee_mac(tp); 3406 3407 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3408 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3409 3410 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3411 3412 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12)); 3413 3414 rtl_pcie_state_l2l3_disable(tp); 3415 3416 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3417 if (rg_saw_cnt > 0) { 3418 u16 sw_cnt_1ms_ini; 3419 3420 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3421 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3422 } 3423 3424 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3425 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3426 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3427 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3428 3429 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3430 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3431 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3432 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3433 3434 /* firmware is for MAC only */ 3435 r8169_apply_firmware(tp); 3436 3437 rtl_hw_aspm_clkreq_enable(tp, true); 3438 } 3439 3440 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3441 { 3442 static const struct ephy_info e_info_8102e_1[] = { 3443 { 0x01, 0, 0x6e65 }, 3444 { 0x02, 0, 0x091f }, 3445 { 0x03, 0, 0xc2f9 }, 3446 { 0x06, 0, 0xafb5 }, 3447 { 0x07, 0, 0x0e00 }, 3448 { 0x19, 0, 0xec80 }, 3449 { 0x01, 0, 0x2e65 }, 3450 { 0x01, 0, 0x6e65 } 3451 }; 3452 u8 cfg1; 3453 3454 rtl_set_def_aspm_entry_latency(tp); 3455 3456 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3457 3458 RTL_W8(tp, Config1, 3459 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3460 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3461 3462 cfg1 = RTL_R8(tp, Config1); 3463 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3464 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3465 3466 rtl_ephy_init(tp, e_info_8102e_1); 3467 } 3468 3469 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3470 { 3471 rtl_set_def_aspm_entry_latency(tp); 3472 3473 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3474 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3475 } 3476 3477 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3478 { 3479 rtl_hw_start_8102e_2(tp); 3480 3481 rtl_ephy_write(tp, 0x03, 0xc2f9); 3482 } 3483 3484 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3485 { 3486 static const struct ephy_info e_info_8105e_1[] = { 3487 { 0x07, 0, 0x4000 }, 3488 { 0x19, 0, 0x0200 }, 3489 { 0x19, 0, 0x0020 }, 3490 { 0x1e, 0, 0x2000 }, 3491 { 0x03, 0, 0x0001 }, 3492 { 0x19, 0, 0x0100 }, 3493 { 0x19, 0, 0x0004 }, 3494 { 0x0a, 0, 0x0020 } 3495 }; 3496 3497 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3498 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3499 3500 /* Disable Early Tally Counter */ 3501 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3502 3503 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3504 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3505 3506 rtl_ephy_init(tp, e_info_8105e_1); 3507 3508 rtl_pcie_state_l2l3_disable(tp); 3509 } 3510 3511 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3512 { 3513 rtl_hw_start_8105e_1(tp); 3514 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3515 } 3516 3517 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3518 { 3519 static const struct ephy_info e_info_8402[] = { 3520 { 0x19, 0xffff, 0xff64 }, 3521 { 0x1e, 0, 0x4000 } 3522 }; 3523 3524 rtl_set_def_aspm_entry_latency(tp); 3525 3526 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3527 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3528 3529 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3530 3531 rtl_ephy_init(tp, e_info_8402); 3532 3533 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3534 rtl_reset_packet_filter(tp); 3535 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3536 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3537 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00); 3538 3539 /* disable EEE */ 3540 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3541 3542 rtl_pcie_state_l2l3_disable(tp); 3543 } 3544 3545 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3546 { 3547 rtl_hw_aspm_clkreq_enable(tp, false); 3548 3549 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3550 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3551 3552 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3553 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3554 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3555 3556 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3557 3558 /* disable EEE */ 3559 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3560 3561 rtl_pcie_state_l2l3_disable(tp); 3562 rtl_hw_aspm_clkreq_enable(tp, true); 3563 } 3564 3565 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3566 { 3567 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3568 } 3569 3570 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3571 { 3572 rtl_pcie_state_l2l3_disable(tp); 3573 3574 RTL_W16(tp, 0x382, 0x221b); 3575 RTL_W8(tp, 0x4500, 0); 3576 RTL_W16(tp, 0x4800, 0); 3577 3578 /* disable UPS */ 3579 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3580 3581 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3582 3583 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3584 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3585 3586 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3587 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3588 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3589 3590 /* disable new tx descriptor format */ 3591 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3592 3593 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3594 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3595 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3596 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3597 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3598 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3599 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3600 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3601 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 3602 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3603 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3604 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 3605 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3606 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3607 udelay(1); 3608 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3609 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3610 3611 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3612 3613 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3614 3615 rtl8125_config_eee_mac(tp); 3616 3617 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3618 udelay(10); 3619 } 3620 3621 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 3622 { 3623 static const struct ephy_info e_info_8125_1[] = { 3624 { 0x01, 0xffff, 0xa812 }, 3625 { 0x09, 0xffff, 0x520c }, 3626 { 0x04, 0xffff, 0xd000 }, 3627 { 0x0d, 0xffff, 0xf702 }, 3628 { 0x0a, 0xffff, 0x8653 }, 3629 { 0x06, 0xffff, 0x001e }, 3630 { 0x08, 0xffff, 0x3595 }, 3631 { 0x20, 0xffff, 0x9455 }, 3632 { 0x21, 0xffff, 0x99ff }, 3633 { 0x02, 0xffff, 0x6046 }, 3634 { 0x29, 0xffff, 0xfe00 }, 3635 { 0x23, 0xffff, 0xab62 }, 3636 3637 { 0x41, 0xffff, 0xa80c }, 3638 { 0x49, 0xffff, 0x520c }, 3639 { 0x44, 0xffff, 0xd000 }, 3640 { 0x4d, 0xffff, 0xf702 }, 3641 { 0x4a, 0xffff, 0x8653 }, 3642 { 0x46, 0xffff, 0x001e }, 3643 { 0x48, 0xffff, 0x3595 }, 3644 { 0x60, 0xffff, 0x9455 }, 3645 { 0x61, 0xffff, 0x99ff }, 3646 { 0x42, 0xffff, 0x6046 }, 3647 { 0x69, 0xffff, 0xfe00 }, 3648 { 0x63, 0xffff, 0xab62 }, 3649 }; 3650 3651 rtl_set_def_aspm_entry_latency(tp); 3652 3653 /* disable aspm and clock request before access ephy */ 3654 rtl_hw_aspm_clkreq_enable(tp, false); 3655 rtl_ephy_init(tp, e_info_8125_1); 3656 3657 rtl_hw_start_8125_common(tp); 3658 } 3659 3660 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 3661 { 3662 static const struct ephy_info e_info_8125_2[] = { 3663 { 0x04, 0xffff, 0xd000 }, 3664 { 0x0a, 0xffff, 0x8653 }, 3665 { 0x23, 0xffff, 0xab66 }, 3666 { 0x20, 0xffff, 0x9455 }, 3667 { 0x21, 0xffff, 0x99ff }, 3668 { 0x29, 0xffff, 0xfe04 }, 3669 3670 { 0x44, 0xffff, 0xd000 }, 3671 { 0x4a, 0xffff, 0x8653 }, 3672 { 0x63, 0xffff, 0xab66 }, 3673 { 0x60, 0xffff, 0x9455 }, 3674 { 0x61, 0xffff, 0x99ff }, 3675 { 0x69, 0xffff, 0xfe04 }, 3676 }; 3677 3678 rtl_set_def_aspm_entry_latency(tp); 3679 3680 /* disable aspm and clock request before access ephy */ 3681 rtl_hw_aspm_clkreq_enable(tp, false); 3682 rtl_ephy_init(tp, e_info_8125_2); 3683 3684 rtl_hw_start_8125_common(tp); 3685 } 3686 3687 static void rtl_hw_config(struct rtl8169_private *tp) 3688 { 3689 static const rtl_generic_fct hw_configs[] = { 3690 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3691 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3692 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3693 [RTL_GIGA_MAC_VER_10] = NULL, 3694 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3695 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3696 [RTL_GIGA_MAC_VER_13] = NULL, 3697 [RTL_GIGA_MAC_VER_14] = NULL, 3698 [RTL_GIGA_MAC_VER_15] = NULL, 3699 [RTL_GIGA_MAC_VER_16] = NULL, 3700 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3701 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3702 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3703 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3704 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3705 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3706 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3707 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3708 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3709 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3710 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3711 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3712 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3713 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3714 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3715 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3716 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3717 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3718 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3719 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3720 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3721 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3722 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3723 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3724 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3725 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3726 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3727 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3728 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3729 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3730 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3731 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3732 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3733 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3734 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3735 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3736 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 3737 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 3738 }; 3739 3740 if (hw_configs[tp->mac_version]) 3741 hw_configs[tp->mac_version](tp); 3742 } 3743 3744 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3745 { 3746 int i; 3747 3748 /* disable interrupt coalescing */ 3749 for (i = 0xa00; i < 0xb00; i += 4) 3750 RTL_W32(tp, i, 0); 3751 3752 rtl_hw_config(tp); 3753 } 3754 3755 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3756 { 3757 if (rtl_is_8168evl_up(tp)) 3758 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3759 else 3760 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3761 3762 rtl_hw_config(tp); 3763 3764 /* disable interrupt coalescing */ 3765 RTL_W16(tp, IntrMitigate, 0x0000); 3766 } 3767 3768 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3769 { 3770 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3771 3772 tp->cp_cmd |= PCIMulRW; 3773 3774 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3775 tp->mac_version == RTL_GIGA_MAC_VER_03) 3776 tp->cp_cmd |= EnAnaPLL; 3777 3778 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3779 3780 rtl8169_set_magic_reg(tp); 3781 3782 /* disable interrupt coalescing */ 3783 RTL_W16(tp, IntrMitigate, 0x0000); 3784 } 3785 3786 static void rtl_hw_start(struct rtl8169_private *tp) 3787 { 3788 rtl_unlock_config_regs(tp); 3789 3790 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3791 3792 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3793 rtl_hw_start_8169(tp); 3794 else if (rtl_is_8125(tp)) 3795 rtl_hw_start_8125(tp); 3796 else 3797 rtl_hw_start_8168(tp); 3798 3799 rtl_set_rx_max_size(tp); 3800 rtl_set_rx_tx_desc_registers(tp); 3801 rtl_lock_config_regs(tp); 3802 3803 rtl_jumbo_config(tp); 3804 3805 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3806 rtl_pci_commit(tp); 3807 3808 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3809 rtl_init_rxcfg(tp); 3810 rtl_set_tx_config_registers(tp); 3811 rtl_set_rx_config_features(tp, tp->dev->features); 3812 rtl_set_rx_mode(tp->dev); 3813 rtl_irq_enable(tp); 3814 } 3815 3816 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3817 { 3818 struct rtl8169_private *tp = netdev_priv(dev); 3819 3820 dev->mtu = new_mtu; 3821 netdev_update_features(dev); 3822 rtl_jumbo_config(tp); 3823 3824 return 0; 3825 } 3826 3827 static inline void rtl8169_mark_to_asic(struct RxDesc *desc) 3828 { 3829 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3830 3831 desc->opts2 = 0; 3832 /* Force memory writes to complete before releasing descriptor */ 3833 dma_wmb(); 3834 3835 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE); 3836 } 3837 3838 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3839 struct RxDesc *desc) 3840 { 3841 struct device *d = tp_to_dev(tp); 3842 int node = dev_to_node(d); 3843 dma_addr_t mapping; 3844 struct page *data; 3845 3846 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3847 if (!data) 3848 return NULL; 3849 3850 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3851 if (unlikely(dma_mapping_error(d, mapping))) { 3852 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3853 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3854 return NULL; 3855 } 3856 3857 desc->addr = cpu_to_le64(mapping); 3858 rtl8169_mark_to_asic(desc); 3859 3860 return data; 3861 } 3862 3863 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3864 { 3865 unsigned int i; 3866 3867 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3868 dma_unmap_page(tp_to_dev(tp), 3869 le64_to_cpu(tp->RxDescArray[i].addr), 3870 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3871 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3872 tp->Rx_databuff[i] = NULL; 3873 tp->RxDescArray[i].addr = 0; 3874 tp->RxDescArray[i].opts1 = 0; 3875 } 3876 } 3877 3878 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3879 { 3880 unsigned int i; 3881 3882 for (i = 0; i < NUM_RX_DESC; i++) { 3883 struct page *data; 3884 3885 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3886 if (!data) { 3887 rtl8169_rx_clear(tp); 3888 return -ENOMEM; 3889 } 3890 tp->Rx_databuff[i] = data; 3891 } 3892 3893 /* mark as last descriptor in the ring */ 3894 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3895 3896 return 0; 3897 } 3898 3899 static int rtl8169_init_ring(struct rtl8169_private *tp) 3900 { 3901 rtl8169_init_ring_indexes(tp); 3902 3903 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3904 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3905 3906 return rtl8169_rx_fill(tp); 3907 } 3908 3909 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3910 { 3911 struct ring_info *tx_skb = tp->tx_skb + entry; 3912 struct TxDesc *desc = tp->TxDescArray + entry; 3913 3914 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3915 DMA_TO_DEVICE); 3916 memset(desc, 0, sizeof(*desc)); 3917 memset(tx_skb, 0, sizeof(*tx_skb)); 3918 } 3919 3920 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3921 unsigned int n) 3922 { 3923 unsigned int i; 3924 3925 for (i = 0; i < n; i++) { 3926 unsigned int entry = (start + i) % NUM_TX_DESC; 3927 struct ring_info *tx_skb = tp->tx_skb + entry; 3928 unsigned int len = tx_skb->len; 3929 3930 if (len) { 3931 struct sk_buff *skb = tx_skb->skb; 3932 3933 rtl8169_unmap_tx_skb(tp, entry); 3934 if (skb) 3935 dev_consume_skb_any(skb); 3936 } 3937 } 3938 } 3939 3940 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3941 { 3942 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3943 tp->cur_tx = tp->dirty_tx = 0; 3944 netdev_reset_queue(tp->dev); 3945 } 3946 3947 static void rtl_reset_work(struct rtl8169_private *tp) 3948 { 3949 struct net_device *dev = tp->dev; 3950 int i; 3951 3952 napi_disable(&tp->napi); 3953 netif_stop_queue(dev); 3954 synchronize_rcu(); 3955 3956 rtl8169_hw_reset(tp); 3957 3958 for (i = 0; i < NUM_RX_DESC; i++) 3959 rtl8169_mark_to_asic(tp->RxDescArray + i); 3960 3961 rtl8169_tx_clear(tp); 3962 rtl8169_init_ring_indexes(tp); 3963 3964 napi_enable(&tp->napi); 3965 rtl_hw_start(tp); 3966 netif_wake_queue(dev); 3967 } 3968 3969 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3970 { 3971 struct rtl8169_private *tp = netdev_priv(dev); 3972 3973 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3974 } 3975 3976 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3977 void *addr, unsigned int entry, bool desc_own) 3978 { 3979 struct TxDesc *txd = tp->TxDescArray + entry; 3980 struct device *d = tp_to_dev(tp); 3981 dma_addr_t mapping; 3982 u32 opts1; 3983 int ret; 3984 3985 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 3986 ret = dma_mapping_error(d, mapping); 3987 if (unlikely(ret)) { 3988 if (net_ratelimit()) 3989 netdev_err(tp->dev, "Failed to map TX data!\n"); 3990 return ret; 3991 } 3992 3993 txd->addr = cpu_to_le64(mapping); 3994 txd->opts2 = cpu_to_le32(opts[1]); 3995 3996 opts1 = opts[0] | len; 3997 if (entry == NUM_TX_DESC - 1) 3998 opts1 |= RingEnd; 3999 if (desc_own) 4000 opts1 |= DescOwn; 4001 txd->opts1 = cpu_to_le32(opts1); 4002 4003 tp->tx_skb[entry].len = len; 4004 4005 return 0; 4006 } 4007 4008 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4009 const u32 *opts, unsigned int entry) 4010 { 4011 struct skb_shared_info *info = skb_shinfo(skb); 4012 unsigned int cur_frag; 4013 4014 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4015 const skb_frag_t *frag = info->frags + cur_frag; 4016 void *addr = skb_frag_address(frag); 4017 u32 len = skb_frag_size(frag); 4018 4019 entry = (entry + 1) % NUM_TX_DESC; 4020 4021 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4022 goto err_out; 4023 } 4024 4025 return 0; 4026 4027 err_out: 4028 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4029 return -EIO; 4030 } 4031 4032 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 4033 { 4034 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 4035 } 4036 4037 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4038 { 4039 u32 mss = skb_shinfo(skb)->gso_size; 4040 4041 if (mss) { 4042 opts[0] |= TD_LSO; 4043 opts[0] |= mss << TD0_MSS_SHIFT; 4044 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4045 const struct iphdr *ip = ip_hdr(skb); 4046 4047 if (ip->protocol == IPPROTO_TCP) 4048 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4049 else if (ip->protocol == IPPROTO_UDP) 4050 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4051 else 4052 WARN_ON_ONCE(1); 4053 } 4054 } 4055 4056 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4057 struct sk_buff *skb, u32 *opts) 4058 { 4059 u32 transport_offset = (u32)skb_transport_offset(skb); 4060 struct skb_shared_info *shinfo = skb_shinfo(skb); 4061 u32 mss = shinfo->gso_size; 4062 4063 if (mss) { 4064 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4065 opts[0] |= TD1_GTSENV4; 4066 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4067 if (skb_cow_head(skb, 0)) 4068 return false; 4069 4070 tcp_v6_gso_csum_prep(skb); 4071 opts[0] |= TD1_GTSENV6; 4072 } else { 4073 WARN_ON_ONCE(1); 4074 } 4075 4076 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4077 opts[1] |= mss << TD1_MSS_SHIFT; 4078 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4079 u8 ip_protocol; 4080 4081 switch (vlan_get_protocol(skb)) { 4082 case htons(ETH_P_IP): 4083 opts[1] |= TD1_IPv4_CS; 4084 ip_protocol = ip_hdr(skb)->protocol; 4085 break; 4086 4087 case htons(ETH_P_IPV6): 4088 opts[1] |= TD1_IPv6_CS; 4089 ip_protocol = ipv6_hdr(skb)->nexthdr; 4090 break; 4091 4092 default: 4093 ip_protocol = IPPROTO_RAW; 4094 break; 4095 } 4096 4097 if (ip_protocol == IPPROTO_TCP) 4098 opts[1] |= TD1_TCP_CS; 4099 else if (ip_protocol == IPPROTO_UDP) 4100 opts[1] |= TD1_UDP_CS; 4101 else 4102 WARN_ON_ONCE(1); 4103 4104 opts[1] |= transport_offset << TCPHO_SHIFT; 4105 } else { 4106 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 4107 return !eth_skb_pad(skb); 4108 } 4109 4110 return true; 4111 } 4112 4113 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 4114 unsigned int nr_frags) 4115 { 4116 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 4117 4118 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4119 return slots_avail > nr_frags; 4120 } 4121 4122 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4123 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4124 { 4125 switch (tp->mac_version) { 4126 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4127 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4128 return false; 4129 default: 4130 return true; 4131 } 4132 } 4133 4134 static void rtl8169_doorbell(struct rtl8169_private *tp) 4135 { 4136 if (rtl_is_8125(tp)) 4137 RTL_W16(tp, TxPoll_8125, BIT(0)); 4138 else 4139 RTL_W8(tp, TxPoll, NPQ); 4140 } 4141 4142 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4143 struct net_device *dev) 4144 { 4145 unsigned int frags = skb_shinfo(skb)->nr_frags; 4146 struct rtl8169_private *tp = netdev_priv(dev); 4147 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4148 struct TxDesc *txd_first, *txd_last; 4149 bool stop_queue, door_bell; 4150 u32 opts[2]; 4151 4152 txd_first = tp->TxDescArray + entry; 4153 4154 if (unlikely(!rtl_tx_slots_avail(tp, frags))) { 4155 if (net_ratelimit()) 4156 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4157 goto err_stop_0; 4158 } 4159 4160 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn)) 4161 goto err_stop_0; 4162 4163 opts[1] = rtl8169_tx_vlan_tag(skb); 4164 opts[0] = 0; 4165 4166 if (!rtl_chip_supports_csum_v2(tp)) 4167 rtl8169_tso_csum_v1(skb, opts); 4168 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4169 goto err_dma_0; 4170 4171 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4172 entry, false))) 4173 goto err_dma_0; 4174 4175 if (frags) { 4176 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4177 goto err_dma_1; 4178 entry = (entry + frags) % NUM_TX_DESC; 4179 } 4180 4181 txd_last = tp->TxDescArray + entry; 4182 txd_last->opts1 |= cpu_to_le32(LastFrag); 4183 tp->tx_skb[entry].skb = skb; 4184 4185 skb_tx_timestamp(skb); 4186 4187 /* Force memory writes to complete before releasing descriptor */ 4188 dma_wmb(); 4189 4190 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4191 4192 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4193 4194 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4195 smp_wmb(); 4196 4197 tp->cur_tx += frags + 1; 4198 4199 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 4200 if (unlikely(stop_queue)) { 4201 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4202 * not miss a ring update when it notices a stopped queue. 4203 */ 4204 smp_wmb(); 4205 netif_stop_queue(dev); 4206 door_bell = true; 4207 } 4208 4209 if (door_bell) 4210 rtl8169_doorbell(tp); 4211 4212 if (unlikely(stop_queue)) { 4213 /* Sync with rtl_tx: 4214 * - publish queue status and cur_tx ring index (write barrier) 4215 * - refresh dirty_tx ring index (read barrier). 4216 * May the current thread have a pessimistic view of the ring 4217 * status and forget to wake up queue, a racing rtl_tx thread 4218 * can't. 4219 */ 4220 smp_mb(); 4221 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 4222 netif_start_queue(dev); 4223 } 4224 4225 return NETDEV_TX_OK; 4226 4227 err_dma_1: 4228 rtl8169_unmap_tx_skb(tp, entry); 4229 err_dma_0: 4230 dev_kfree_skb_any(skb); 4231 dev->stats.tx_dropped++; 4232 return NETDEV_TX_OK; 4233 4234 err_stop_0: 4235 netif_stop_queue(dev); 4236 dev->stats.tx_dropped++; 4237 return NETDEV_TX_BUSY; 4238 } 4239 4240 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4241 { 4242 struct skb_shared_info *info = skb_shinfo(skb); 4243 unsigned int nr_frags = info->nr_frags; 4244 4245 if (!nr_frags) 4246 return UINT_MAX; 4247 4248 return skb_frag_size(info->frags + nr_frags - 1); 4249 } 4250 4251 /* Workaround for hw issues with TSO on RTL8168evl */ 4252 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4253 netdev_features_t features) 4254 { 4255 /* IPv4 header has options field */ 4256 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4257 ip_hdrlen(skb) > sizeof(struct iphdr)) 4258 features &= ~NETIF_F_ALL_TSO; 4259 4260 /* IPv4 TCP header has options field */ 4261 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4262 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4263 features &= ~NETIF_F_ALL_TSO; 4264 4265 else if (rtl_last_frag_len(skb) <= 6) 4266 features &= ~NETIF_F_ALL_TSO; 4267 4268 return features; 4269 } 4270 4271 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4272 struct net_device *dev, 4273 netdev_features_t features) 4274 { 4275 int transport_offset = skb_transport_offset(skb); 4276 struct rtl8169_private *tp = netdev_priv(dev); 4277 4278 if (skb_is_gso(skb)) { 4279 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4280 features = rtl8168evl_fix_tso(skb, features); 4281 4282 if (transport_offset > GTTCPHO_MAX && 4283 rtl_chip_supports_csum_v2(tp)) 4284 features &= ~NETIF_F_ALL_TSO; 4285 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4286 if (skb->len < ETH_ZLEN) { 4287 switch (tp->mac_version) { 4288 case RTL_GIGA_MAC_VER_11: 4289 case RTL_GIGA_MAC_VER_12: 4290 case RTL_GIGA_MAC_VER_17: 4291 case RTL_GIGA_MAC_VER_34: 4292 features &= ~NETIF_F_CSUM_MASK; 4293 break; 4294 default: 4295 break; 4296 } 4297 } 4298 4299 if (transport_offset > TCPHO_MAX && 4300 rtl_chip_supports_csum_v2(tp)) 4301 features &= ~NETIF_F_CSUM_MASK; 4302 } 4303 4304 return vlan_features_check(skb, features); 4305 } 4306 4307 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4308 { 4309 struct rtl8169_private *tp = netdev_priv(dev); 4310 struct pci_dev *pdev = tp->pci_dev; 4311 int pci_status_errs; 4312 u16 pci_cmd; 4313 4314 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4315 4316 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4317 4318 if (net_ratelimit()) 4319 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4320 pci_cmd, pci_status_errs); 4321 /* 4322 * The recovery sequence below admits a very elaborated explanation: 4323 * - it seems to work; 4324 * - I did not see what else could be done; 4325 * - it makes iop3xx happy. 4326 * 4327 * Feel free to adjust to your needs. 4328 */ 4329 if (pdev->broken_parity_status) 4330 pci_cmd &= ~PCI_COMMAND_PARITY; 4331 else 4332 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4333 4334 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4335 4336 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4337 } 4338 4339 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4340 int budget) 4341 { 4342 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 4343 4344 dirty_tx = tp->dirty_tx; 4345 smp_rmb(); 4346 4347 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) { 4348 unsigned int entry = dirty_tx % NUM_TX_DESC; 4349 struct sk_buff *skb = tp->tx_skb[entry].skb; 4350 u32 status; 4351 4352 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4353 if (status & DescOwn) 4354 break; 4355 4356 rtl8169_unmap_tx_skb(tp, entry); 4357 4358 if (skb) { 4359 pkts_compl++; 4360 bytes_compl += skb->len; 4361 napi_consume_skb(skb, budget); 4362 } 4363 dirty_tx++; 4364 } 4365 4366 if (tp->dirty_tx != dirty_tx) { 4367 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4368 4369 u64_stats_update_begin(&tp->tx_stats.syncp); 4370 tp->tx_stats.packets += pkts_compl; 4371 tp->tx_stats.bytes += bytes_compl; 4372 u64_stats_update_end(&tp->tx_stats.syncp); 4373 4374 tp->dirty_tx = dirty_tx; 4375 /* Sync with rtl8169_start_xmit: 4376 * - publish dirty_tx ring index (write barrier) 4377 * - refresh cur_tx ring index and queue status (read barrier) 4378 * May the current thread miss the stopped queue condition, 4379 * a racing xmit thread can only have a right view of the 4380 * ring status. 4381 */ 4382 smp_mb(); 4383 if (netif_queue_stopped(dev) && 4384 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 4385 netif_wake_queue(dev); 4386 } 4387 /* 4388 * 8168 hack: TxPoll requests are lost when the Tx packets are 4389 * too close. Let's kick an extra TxPoll request when a burst 4390 * of start_xmit activity is detected (if it is not detected, 4391 * it is slow enough). -- FR 4392 */ 4393 if (tp->cur_tx != dirty_tx) 4394 rtl8169_doorbell(tp); 4395 } 4396 } 4397 4398 static inline int rtl8169_fragmented_frame(u32 status) 4399 { 4400 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4401 } 4402 4403 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4404 { 4405 u32 status = opts1 & RxProtoMask; 4406 4407 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4408 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 4409 skb->ip_summed = CHECKSUM_UNNECESSARY; 4410 else 4411 skb_checksum_none_assert(skb); 4412 } 4413 4414 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 4415 { 4416 unsigned int cur_rx, rx_left; 4417 unsigned int count; 4418 4419 cur_rx = tp->cur_rx; 4420 4421 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 4422 unsigned int entry = cur_rx % NUM_RX_DESC; 4423 const void *rx_buf = page_address(tp->Rx_databuff[entry]); 4424 struct RxDesc *desc = tp->RxDescArray + entry; 4425 u32 status; 4426 4427 status = le32_to_cpu(desc->opts1); 4428 if (status & DescOwn) 4429 break; 4430 4431 /* This barrier is needed to keep us from reading 4432 * any other fields out of the Rx descriptor until 4433 * we know the status of DescOwn 4434 */ 4435 dma_rmb(); 4436 4437 if (unlikely(status & RxRES)) { 4438 if (net_ratelimit()) 4439 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4440 status); 4441 dev->stats.rx_errors++; 4442 if (status & (RxRWT | RxRUNT)) 4443 dev->stats.rx_length_errors++; 4444 if (status & RxCRC) 4445 dev->stats.rx_crc_errors++; 4446 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) && 4447 dev->features & NETIF_F_RXALL) { 4448 goto process_pkt; 4449 } 4450 } else { 4451 unsigned int pkt_size; 4452 struct sk_buff *skb; 4453 4454 process_pkt: 4455 pkt_size = status & GENMASK(13, 0); 4456 if (likely(!(dev->features & NETIF_F_RXFCS))) 4457 pkt_size -= ETH_FCS_LEN; 4458 /* 4459 * The driver does not support incoming fragmented 4460 * frames. They are seen as a symptom of over-mtu 4461 * sized frames. 4462 */ 4463 if (unlikely(rtl8169_fragmented_frame(status))) { 4464 dev->stats.rx_dropped++; 4465 dev->stats.rx_length_errors++; 4466 goto release_descriptor; 4467 } 4468 4469 skb = napi_alloc_skb(&tp->napi, pkt_size); 4470 if (unlikely(!skb)) { 4471 dev->stats.rx_dropped++; 4472 goto release_descriptor; 4473 } 4474 4475 dma_sync_single_for_cpu(tp_to_dev(tp), 4476 le64_to_cpu(desc->addr), 4477 pkt_size, DMA_FROM_DEVICE); 4478 prefetch(rx_buf); 4479 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4480 skb->tail += pkt_size; 4481 skb->len = pkt_size; 4482 4483 dma_sync_single_for_device(tp_to_dev(tp), 4484 le64_to_cpu(desc->addr), 4485 pkt_size, DMA_FROM_DEVICE); 4486 4487 rtl8169_rx_csum(skb, status); 4488 skb->protocol = eth_type_trans(skb, dev); 4489 4490 rtl8169_rx_vlan_tag(desc, skb); 4491 4492 if (skb->pkt_type == PACKET_MULTICAST) 4493 dev->stats.multicast++; 4494 4495 napi_gro_receive(&tp->napi, skb); 4496 4497 u64_stats_update_begin(&tp->rx_stats.syncp); 4498 tp->rx_stats.packets++; 4499 tp->rx_stats.bytes += pkt_size; 4500 u64_stats_update_end(&tp->rx_stats.syncp); 4501 } 4502 release_descriptor: 4503 rtl8169_mark_to_asic(desc); 4504 } 4505 4506 count = cur_rx - tp->cur_rx; 4507 tp->cur_rx = cur_rx; 4508 4509 return count; 4510 } 4511 4512 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4513 { 4514 struct rtl8169_private *tp = dev_instance; 4515 u32 status = rtl_get_events(tp); 4516 4517 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 4518 !(status & tp->irq_mask)) 4519 return IRQ_NONE; 4520 4521 if (unlikely(status & SYSErr)) { 4522 rtl8169_pcierr_interrupt(tp->dev); 4523 goto out; 4524 } 4525 4526 if (status & LinkChg) 4527 phy_mac_interrupt(tp->phydev); 4528 4529 if (unlikely(status & RxFIFOOver && 4530 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4531 netif_stop_queue(tp->dev); 4532 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4533 } 4534 4535 rtl_irq_disable(tp); 4536 napi_schedule_irqoff(&tp->napi); 4537 out: 4538 rtl_ack_events(tp, status); 4539 4540 return IRQ_HANDLED; 4541 } 4542 4543 static void rtl_task(struct work_struct *work) 4544 { 4545 struct rtl8169_private *tp = 4546 container_of(work, struct rtl8169_private, wk.work); 4547 4548 rtl_lock_work(tp); 4549 4550 if (!netif_running(tp->dev) || 4551 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4552 goto out_unlock; 4553 4554 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) 4555 rtl_reset_work(tp); 4556 out_unlock: 4557 rtl_unlock_work(tp); 4558 } 4559 4560 static int rtl8169_poll(struct napi_struct *napi, int budget) 4561 { 4562 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4563 struct net_device *dev = tp->dev; 4564 int work_done; 4565 4566 work_done = rtl_rx(dev, tp, (u32) budget); 4567 4568 rtl_tx(dev, tp, budget); 4569 4570 if (work_done < budget) { 4571 napi_complete_done(napi, work_done); 4572 rtl_irq_enable(tp); 4573 } 4574 4575 return work_done; 4576 } 4577 4578 static void r8169_phylink_handler(struct net_device *ndev) 4579 { 4580 struct rtl8169_private *tp = netdev_priv(ndev); 4581 4582 if (netif_carrier_ok(ndev)) { 4583 rtl_link_chg_patch(tp); 4584 pm_request_resume(&tp->pci_dev->dev); 4585 } else { 4586 pm_runtime_idle(&tp->pci_dev->dev); 4587 } 4588 4589 if (net_ratelimit()) 4590 phy_print_status(tp->phydev); 4591 } 4592 4593 static int r8169_phy_connect(struct rtl8169_private *tp) 4594 { 4595 struct phy_device *phydev = tp->phydev; 4596 phy_interface_t phy_mode; 4597 int ret; 4598 4599 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4600 PHY_INTERFACE_MODE_MII; 4601 4602 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4603 phy_mode); 4604 if (ret) 4605 return ret; 4606 4607 if (!tp->supports_gmii) 4608 phy_set_max_speed(phydev, SPEED_100); 4609 4610 phy_support_asym_pause(phydev); 4611 4612 phy_attached_info(phydev); 4613 4614 return 0; 4615 } 4616 4617 static void rtl8169_down(struct net_device *dev) 4618 { 4619 struct rtl8169_private *tp = netdev_priv(dev); 4620 4621 phy_stop(tp->phydev); 4622 4623 napi_disable(&tp->napi); 4624 netif_stop_queue(dev); 4625 4626 rtl8169_hw_reset(tp); 4627 4628 /* Give a racing hard_start_xmit a few cycles to complete. */ 4629 synchronize_rcu(); 4630 4631 rtl8169_tx_clear(tp); 4632 4633 rtl8169_rx_clear(tp); 4634 4635 rtl_pll_power_down(tp); 4636 } 4637 4638 static int rtl8169_close(struct net_device *dev) 4639 { 4640 struct rtl8169_private *tp = netdev_priv(dev); 4641 struct pci_dev *pdev = tp->pci_dev; 4642 4643 pm_runtime_get_sync(&pdev->dev); 4644 4645 /* Update counters before going down */ 4646 rtl8169_update_counters(tp); 4647 4648 rtl_lock_work(tp); 4649 /* Clear all task flags */ 4650 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4651 4652 rtl8169_down(dev); 4653 rtl_unlock_work(tp); 4654 4655 cancel_work_sync(&tp->wk.work); 4656 4657 phy_disconnect(tp->phydev); 4658 4659 pci_free_irq(pdev, 0, tp); 4660 4661 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4662 tp->RxPhyAddr); 4663 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4664 tp->TxPhyAddr); 4665 tp->TxDescArray = NULL; 4666 tp->RxDescArray = NULL; 4667 4668 pm_runtime_put_sync(&pdev->dev); 4669 4670 return 0; 4671 } 4672 4673 #ifdef CONFIG_NET_POLL_CONTROLLER 4674 static void rtl8169_netpoll(struct net_device *dev) 4675 { 4676 struct rtl8169_private *tp = netdev_priv(dev); 4677 4678 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4679 } 4680 #endif 4681 4682 static int rtl_open(struct net_device *dev) 4683 { 4684 struct rtl8169_private *tp = netdev_priv(dev); 4685 struct pci_dev *pdev = tp->pci_dev; 4686 int retval = -ENOMEM; 4687 4688 pm_runtime_get_sync(&pdev->dev); 4689 4690 /* 4691 * Rx and Tx descriptors needs 256 bytes alignment. 4692 * dma_alloc_coherent provides more. 4693 */ 4694 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4695 &tp->TxPhyAddr, GFP_KERNEL); 4696 if (!tp->TxDescArray) 4697 goto err_pm_runtime_put; 4698 4699 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4700 &tp->RxPhyAddr, GFP_KERNEL); 4701 if (!tp->RxDescArray) 4702 goto err_free_tx_0; 4703 4704 retval = rtl8169_init_ring(tp); 4705 if (retval < 0) 4706 goto err_free_rx_1; 4707 4708 rtl_request_firmware(tp); 4709 4710 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 4711 dev->name); 4712 if (retval < 0) 4713 goto err_release_fw_2; 4714 4715 retval = r8169_phy_connect(tp); 4716 if (retval) 4717 goto err_free_irq; 4718 4719 rtl_lock_work(tp); 4720 4721 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4722 4723 napi_enable(&tp->napi); 4724 4725 rtl8169_init_phy(tp); 4726 4727 rtl_pll_power_up(tp); 4728 4729 rtl_hw_start(tp); 4730 4731 rtl8169_init_counter_offsets(tp); 4732 4733 phy_start(tp->phydev); 4734 netif_start_queue(dev); 4735 4736 rtl_unlock_work(tp); 4737 4738 pm_runtime_put_sync(&pdev->dev); 4739 out: 4740 return retval; 4741 4742 err_free_irq: 4743 pci_free_irq(pdev, 0, tp); 4744 err_release_fw_2: 4745 rtl_release_firmware(tp); 4746 rtl8169_rx_clear(tp); 4747 err_free_rx_1: 4748 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4749 tp->RxPhyAddr); 4750 tp->RxDescArray = NULL; 4751 err_free_tx_0: 4752 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4753 tp->TxPhyAddr); 4754 tp->TxDescArray = NULL; 4755 err_pm_runtime_put: 4756 pm_runtime_put_noidle(&pdev->dev); 4757 goto out; 4758 } 4759 4760 static void 4761 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4762 { 4763 struct rtl8169_private *tp = netdev_priv(dev); 4764 struct pci_dev *pdev = tp->pci_dev; 4765 struct rtl8169_counters *counters = tp->counters; 4766 unsigned int start; 4767 4768 pm_runtime_get_noresume(&pdev->dev); 4769 4770 netdev_stats_to_stats64(stats, &dev->stats); 4771 4772 do { 4773 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 4774 stats->rx_packets = tp->rx_stats.packets; 4775 stats->rx_bytes = tp->rx_stats.bytes; 4776 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 4777 4778 do { 4779 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 4780 stats->tx_packets = tp->tx_stats.packets; 4781 stats->tx_bytes = tp->tx_stats.bytes; 4782 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 4783 4784 /* 4785 * Fetch additional counter values missing in stats collected by driver 4786 * from tally counters. 4787 */ 4788 if (pm_runtime_active(&pdev->dev)) 4789 rtl8169_update_counters(tp); 4790 4791 /* 4792 * Subtract values fetched during initalization. 4793 * See rtl8169_init_counter_offsets for a description why we do that. 4794 */ 4795 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4796 le64_to_cpu(tp->tc_offset.tx_errors); 4797 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4798 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4799 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4800 le16_to_cpu(tp->tc_offset.tx_aborted); 4801 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4802 le16_to_cpu(tp->tc_offset.rx_missed); 4803 4804 pm_runtime_put_noidle(&pdev->dev); 4805 } 4806 4807 static void rtl8169_net_suspend(struct net_device *dev) 4808 { 4809 struct rtl8169_private *tp = netdev_priv(dev); 4810 4811 if (!netif_running(dev)) 4812 return; 4813 4814 phy_stop(tp->phydev); 4815 netif_device_detach(dev); 4816 4817 rtl_lock_work(tp); 4818 napi_disable(&tp->napi); 4819 /* Clear all task flags */ 4820 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4821 4822 rtl_unlock_work(tp); 4823 4824 rtl_pll_power_down(tp); 4825 } 4826 4827 #ifdef CONFIG_PM 4828 4829 static int rtl8169_suspend(struct device *device) 4830 { 4831 struct net_device *dev = dev_get_drvdata(device); 4832 struct rtl8169_private *tp = netdev_priv(dev); 4833 4834 rtl8169_net_suspend(dev); 4835 clk_disable_unprepare(tp->clk); 4836 4837 return 0; 4838 } 4839 4840 static void __rtl8169_resume(struct net_device *dev) 4841 { 4842 struct rtl8169_private *tp = netdev_priv(dev); 4843 4844 netif_device_attach(dev); 4845 4846 rtl_pll_power_up(tp); 4847 rtl8169_init_phy(tp); 4848 4849 phy_start(tp->phydev); 4850 4851 rtl_lock_work(tp); 4852 napi_enable(&tp->napi); 4853 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4854 rtl_reset_work(tp); 4855 rtl_unlock_work(tp); 4856 } 4857 4858 static int rtl8169_resume(struct device *device) 4859 { 4860 struct net_device *dev = dev_get_drvdata(device); 4861 struct rtl8169_private *tp = netdev_priv(dev); 4862 4863 rtl_rar_set(tp, dev->dev_addr); 4864 4865 clk_prepare_enable(tp->clk); 4866 4867 if (netif_running(dev)) 4868 __rtl8169_resume(dev); 4869 4870 return 0; 4871 } 4872 4873 static int rtl8169_runtime_suspend(struct device *device) 4874 { 4875 struct net_device *dev = dev_get_drvdata(device); 4876 struct rtl8169_private *tp = netdev_priv(dev); 4877 4878 if (!tp->TxDescArray) 4879 return 0; 4880 4881 rtl_lock_work(tp); 4882 __rtl8169_set_wol(tp, WAKE_ANY); 4883 rtl_unlock_work(tp); 4884 4885 rtl8169_net_suspend(dev); 4886 4887 /* Update counters before going runtime suspend */ 4888 rtl8169_update_counters(tp); 4889 4890 return 0; 4891 } 4892 4893 static int rtl8169_runtime_resume(struct device *device) 4894 { 4895 struct net_device *dev = dev_get_drvdata(device); 4896 struct rtl8169_private *tp = netdev_priv(dev); 4897 4898 rtl_rar_set(tp, dev->dev_addr); 4899 4900 if (!tp->TxDescArray) 4901 return 0; 4902 4903 rtl_lock_work(tp); 4904 __rtl8169_set_wol(tp, tp->saved_wolopts); 4905 rtl_unlock_work(tp); 4906 4907 __rtl8169_resume(dev); 4908 4909 return 0; 4910 } 4911 4912 static int rtl8169_runtime_idle(struct device *device) 4913 { 4914 struct net_device *dev = dev_get_drvdata(device); 4915 4916 if (!netif_running(dev) || !netif_carrier_ok(dev)) 4917 pm_schedule_suspend(device, 10000); 4918 4919 return -EBUSY; 4920 } 4921 4922 static const struct dev_pm_ops rtl8169_pm_ops = { 4923 .suspend = rtl8169_suspend, 4924 .resume = rtl8169_resume, 4925 .freeze = rtl8169_suspend, 4926 .thaw = rtl8169_resume, 4927 .poweroff = rtl8169_suspend, 4928 .restore = rtl8169_resume, 4929 .runtime_suspend = rtl8169_runtime_suspend, 4930 .runtime_resume = rtl8169_runtime_resume, 4931 .runtime_idle = rtl8169_runtime_idle, 4932 }; 4933 4934 #define RTL8169_PM_OPS (&rtl8169_pm_ops) 4935 4936 #else /* !CONFIG_PM */ 4937 4938 #define RTL8169_PM_OPS NULL 4939 4940 #endif /* !CONFIG_PM */ 4941 4942 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4943 { 4944 /* WoL fails with 8168b when the receiver is disabled. */ 4945 switch (tp->mac_version) { 4946 case RTL_GIGA_MAC_VER_11: 4947 case RTL_GIGA_MAC_VER_12: 4948 case RTL_GIGA_MAC_VER_17: 4949 pci_clear_master(tp->pci_dev); 4950 4951 RTL_W8(tp, ChipCmd, CmdRxEnb); 4952 rtl_pci_commit(tp); 4953 break; 4954 default: 4955 break; 4956 } 4957 } 4958 4959 static void rtl_shutdown(struct pci_dev *pdev) 4960 { 4961 struct net_device *dev = pci_get_drvdata(pdev); 4962 struct rtl8169_private *tp = netdev_priv(dev); 4963 4964 rtl8169_net_suspend(dev); 4965 4966 /* Restore original MAC address */ 4967 rtl_rar_set(tp, dev->perm_addr); 4968 4969 rtl8169_hw_reset(tp); 4970 4971 if (system_state == SYSTEM_POWER_OFF) { 4972 if (tp->saved_wolopts) { 4973 rtl_wol_suspend_quirk(tp); 4974 rtl_wol_shutdown_quirk(tp); 4975 } 4976 4977 pci_wake_from_d3(pdev, true); 4978 pci_set_power_state(pdev, PCI_D3hot); 4979 } 4980 } 4981 4982 static void rtl_remove_one(struct pci_dev *pdev) 4983 { 4984 struct net_device *dev = pci_get_drvdata(pdev); 4985 struct rtl8169_private *tp = netdev_priv(dev); 4986 4987 if (r8168_check_dash(tp)) 4988 rtl8168_driver_stop(tp); 4989 4990 netif_napi_del(&tp->napi); 4991 4992 unregister_netdev(dev); 4993 mdiobus_unregister(tp->phydev->mdio.bus); 4994 4995 rtl_release_firmware(tp); 4996 4997 if (pci_dev_run_wake(pdev)) 4998 pm_runtime_get_noresume(&pdev->dev); 4999 5000 /* restore original MAC address */ 5001 rtl_rar_set(tp, dev->perm_addr); 5002 } 5003 5004 static const struct net_device_ops rtl_netdev_ops = { 5005 .ndo_open = rtl_open, 5006 .ndo_stop = rtl8169_close, 5007 .ndo_get_stats64 = rtl8169_get_stats64, 5008 .ndo_start_xmit = rtl8169_start_xmit, 5009 .ndo_features_check = rtl8169_features_check, 5010 .ndo_tx_timeout = rtl8169_tx_timeout, 5011 .ndo_validate_addr = eth_validate_addr, 5012 .ndo_change_mtu = rtl8169_change_mtu, 5013 .ndo_fix_features = rtl8169_fix_features, 5014 .ndo_set_features = rtl8169_set_features, 5015 .ndo_set_mac_address = rtl_set_mac_address, 5016 .ndo_do_ioctl = phy_do_ioctl_running, 5017 .ndo_set_rx_mode = rtl_set_rx_mode, 5018 #ifdef CONFIG_NET_POLL_CONTROLLER 5019 .ndo_poll_controller = rtl8169_netpoll, 5020 #endif 5021 5022 }; 5023 5024 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5025 { 5026 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5027 5028 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5029 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5030 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5031 /* special workaround needed */ 5032 tp->irq_mask |= RxFIFOOver; 5033 else 5034 tp->irq_mask |= RxOverflow; 5035 } 5036 5037 static int rtl_alloc_irq(struct rtl8169_private *tp) 5038 { 5039 unsigned int flags; 5040 5041 switch (tp->mac_version) { 5042 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5043 rtl_unlock_config_regs(tp); 5044 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5045 rtl_lock_config_regs(tp); 5046 /* fall through */ 5047 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5048 flags = PCI_IRQ_LEGACY; 5049 break; 5050 default: 5051 flags = PCI_IRQ_ALL_TYPES; 5052 break; 5053 } 5054 5055 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5056 } 5057 5058 static void rtl_read_mac_address(struct rtl8169_private *tp, 5059 u8 mac_addr[ETH_ALEN]) 5060 { 5061 /* Get MAC address */ 5062 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5063 u32 value = rtl_eri_read(tp, 0xe0); 5064 5065 mac_addr[0] = (value >> 0) & 0xff; 5066 mac_addr[1] = (value >> 8) & 0xff; 5067 mac_addr[2] = (value >> 16) & 0xff; 5068 mac_addr[3] = (value >> 24) & 0xff; 5069 5070 value = rtl_eri_read(tp, 0xe4); 5071 mac_addr[4] = (value >> 0) & 0xff; 5072 mac_addr[5] = (value >> 8) & 0xff; 5073 } else if (rtl_is_8125(tp)) { 5074 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5075 } 5076 } 5077 5078 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5079 { 5080 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5081 } 5082 5083 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5084 { 5085 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5086 } 5087 5088 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5089 { 5090 struct rtl8169_private *tp = mii_bus->priv; 5091 5092 if (phyaddr > 0) 5093 return -ENODEV; 5094 5095 return rtl_readphy(tp, phyreg); 5096 } 5097 5098 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5099 int phyreg, u16 val) 5100 { 5101 struct rtl8169_private *tp = mii_bus->priv; 5102 5103 if (phyaddr > 0) 5104 return -ENODEV; 5105 5106 rtl_writephy(tp, phyreg, val); 5107 5108 return 0; 5109 } 5110 5111 static int r8169_mdio_register(struct rtl8169_private *tp) 5112 { 5113 struct pci_dev *pdev = tp->pci_dev; 5114 struct mii_bus *new_bus; 5115 int ret; 5116 5117 new_bus = devm_mdiobus_alloc(&pdev->dev); 5118 if (!new_bus) 5119 return -ENOMEM; 5120 5121 new_bus->name = "r8169"; 5122 new_bus->priv = tp; 5123 new_bus->parent = &pdev->dev; 5124 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5125 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5126 5127 new_bus->read = r8169_mdio_read_reg; 5128 new_bus->write = r8169_mdio_write_reg; 5129 5130 ret = devm_mdiobus_register(new_bus); 5131 if (ret) 5132 return ret; 5133 5134 tp->phydev = mdiobus_get_phy(new_bus, 0); 5135 if (!tp->phydev) { 5136 return -ENODEV; 5137 } else if (!tp->phydev->drv) { 5138 /* Most chip versions fail with the genphy driver. 5139 * Therefore ensure that the dedicated PHY driver is loaded. 5140 */ 5141 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5142 tp->phydev->phy_id); 5143 return -EUNATCH; 5144 } 5145 5146 /* PHY will be woken up in rtl_open() */ 5147 phy_suspend(tp->phydev); 5148 5149 return 0; 5150 } 5151 5152 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5153 { 5154 rtl_enable_rxdvgate(tp); 5155 5156 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5157 msleep(1); 5158 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5159 5160 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5161 r8168g_wait_ll_share_fifo_ready(tp); 5162 5163 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5164 r8168g_wait_ll_share_fifo_ready(tp); 5165 } 5166 5167 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5168 { 5169 rtl_enable_rxdvgate(tp); 5170 5171 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5172 msleep(1); 5173 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5174 5175 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5176 r8168g_wait_ll_share_fifo_ready(tp); 5177 5178 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5179 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5180 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5181 r8168g_wait_ll_share_fifo_ready(tp); 5182 } 5183 5184 static void rtl_hw_initialize(struct rtl8169_private *tp) 5185 { 5186 switch (tp->mac_version) { 5187 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 5188 rtl8168ep_stop_cmac(tp); 5189 /* fall through */ 5190 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5191 rtl_hw_init_8168g(tp); 5192 break; 5193 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 5194 rtl_hw_init_8125(tp); 5195 break; 5196 default: 5197 break; 5198 } 5199 } 5200 5201 static int rtl_jumbo_max(struct rtl8169_private *tp) 5202 { 5203 /* Non-GBit versions don't support jumbo frames */ 5204 if (!tp->supports_gmii) 5205 return 0; 5206 5207 switch (tp->mac_version) { 5208 /* RTL8169 */ 5209 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5210 return JUMBO_7K; 5211 /* RTL8168b */ 5212 case RTL_GIGA_MAC_VER_11: 5213 case RTL_GIGA_MAC_VER_12: 5214 case RTL_GIGA_MAC_VER_17: 5215 return JUMBO_4K; 5216 /* RTL8168c */ 5217 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5218 return JUMBO_6K; 5219 default: 5220 return JUMBO_9K; 5221 } 5222 } 5223 5224 static void rtl_disable_clk(void *data) 5225 { 5226 clk_disable_unprepare(data); 5227 } 5228 5229 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5230 { 5231 struct device *d = tp_to_dev(tp); 5232 struct clk *clk; 5233 int rc; 5234 5235 clk = devm_clk_get(d, "ether_clk"); 5236 if (IS_ERR(clk)) { 5237 rc = PTR_ERR(clk); 5238 if (rc == -ENOENT) 5239 /* clk-core allows NULL (for suspend / resume) */ 5240 rc = 0; 5241 else if (rc != -EPROBE_DEFER) 5242 dev_err(d, "failed to get clk: %d\n", rc); 5243 } else { 5244 tp->clk = clk; 5245 rc = clk_prepare_enable(clk); 5246 if (rc) 5247 dev_err(d, "failed to enable clk: %d\n", rc); 5248 else 5249 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5250 } 5251 5252 return rc; 5253 } 5254 5255 static void rtl_init_mac_address(struct rtl8169_private *tp) 5256 { 5257 struct net_device *dev = tp->dev; 5258 u8 *mac_addr = dev->dev_addr; 5259 int rc; 5260 5261 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5262 if (!rc) 5263 goto done; 5264 5265 rtl_read_mac_address(tp, mac_addr); 5266 if (is_valid_ether_addr(mac_addr)) 5267 goto done; 5268 5269 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5270 if (is_valid_ether_addr(mac_addr)) 5271 goto done; 5272 5273 eth_hw_addr_random(dev); 5274 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5275 done: 5276 rtl_rar_set(tp, mac_addr); 5277 } 5278 5279 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5280 { 5281 struct rtl8169_private *tp; 5282 int jumbo_max, region, rc; 5283 enum mac_version chipset; 5284 struct net_device *dev; 5285 u16 xid; 5286 5287 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5288 if (!dev) 5289 return -ENOMEM; 5290 5291 SET_NETDEV_DEV(dev, &pdev->dev); 5292 dev->netdev_ops = &rtl_netdev_ops; 5293 tp = netdev_priv(dev); 5294 tp->dev = dev; 5295 tp->pci_dev = pdev; 5296 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5297 tp->eee_adv = -1; 5298 tp->ocp_base = OCP_STD_PHY_BASE; 5299 5300 /* Get the *optional* external "ether_clk" used on some boards */ 5301 rc = rtl_get_ether_clk(tp); 5302 if (rc) 5303 return rc; 5304 5305 /* Disable ASPM completely as that cause random device stop working 5306 * problems as well as full system hangs for some PCIe devices users. 5307 */ 5308 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5309 PCIE_LINK_STATE_L1); 5310 tp->aspm_manageable = !rc; 5311 5312 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5313 rc = pcim_enable_device(pdev); 5314 if (rc < 0) { 5315 dev_err(&pdev->dev, "enable failure\n"); 5316 return rc; 5317 } 5318 5319 if (pcim_set_mwi(pdev) < 0) 5320 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5321 5322 /* use first MMIO region */ 5323 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5324 if (region < 0) { 5325 dev_err(&pdev->dev, "no MMIO resource found\n"); 5326 return -ENODEV; 5327 } 5328 5329 /* check for weird/broken PCI region reporting */ 5330 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5331 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5332 return -ENODEV; 5333 } 5334 5335 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5336 if (rc < 0) { 5337 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5338 return rc; 5339 } 5340 5341 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5342 5343 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5344 5345 /* Identify chip attached to board */ 5346 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5347 if (chipset == RTL_GIGA_MAC_NONE) { 5348 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid); 5349 return -ENODEV; 5350 } 5351 5352 tp->mac_version = chipset; 5353 5354 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5355 5356 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5357 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5358 dev->features |= NETIF_F_HIGHDMA; 5359 5360 rtl_init_rxcfg(tp); 5361 5362 rtl8169_irq_mask_and_ack(tp); 5363 5364 rtl_hw_initialize(tp); 5365 5366 rtl_hw_reset(tp); 5367 5368 pci_set_master(pdev); 5369 5370 rc = rtl_alloc_irq(tp); 5371 if (rc < 0) { 5372 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5373 return rc; 5374 } 5375 5376 mutex_init(&tp->wk.mutex); 5377 INIT_WORK(&tp->wk.work, rtl_task); 5378 u64_stats_init(&tp->rx_stats.syncp); 5379 u64_stats_init(&tp->tx_stats.syncp); 5380 5381 rtl_init_mac_address(tp); 5382 5383 dev->ethtool_ops = &rtl8169_ethtool_ops; 5384 5385 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5386 5387 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5388 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5389 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5390 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5391 5392 /* 5393 * Pretend we are using VLANs; This bypasses a nasty bug where 5394 * Interrupts stop flowing on high load on 8110SCd controllers. 5395 */ 5396 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5397 /* Disallow toggling */ 5398 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5399 5400 if (rtl_chip_supports_csum_v2(tp)) 5401 dev->hw_features |= NETIF_F_IPV6_CSUM; 5402 5403 dev->features |= dev->hw_features; 5404 5405 /* There has been a number of reports that using SG/TSO results in 5406 * tx timeouts. However for a lot of people SG/TSO works fine. 5407 * Therefore disable both features by default, but allow users to 5408 * enable them. Use at own risk! 5409 */ 5410 if (rtl_chip_supports_csum_v2(tp)) { 5411 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5412 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5413 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5414 } else { 5415 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5416 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5417 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5418 } 5419 5420 dev->hw_features |= NETIF_F_RXALL; 5421 dev->hw_features |= NETIF_F_RXFCS; 5422 5423 /* configure chip for default features */ 5424 rtl8169_set_features(dev, dev->features); 5425 5426 jumbo_max = rtl_jumbo_max(tp); 5427 if (jumbo_max) 5428 dev->max_mtu = jumbo_max; 5429 5430 rtl_set_irq_mask(tp); 5431 5432 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5433 5434 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5435 &tp->counters_phys_addr, 5436 GFP_KERNEL); 5437 if (!tp->counters) 5438 return -ENOMEM; 5439 5440 pci_set_drvdata(pdev, dev); 5441 5442 rc = r8169_mdio_register(tp); 5443 if (rc) 5444 return rc; 5445 5446 /* chip gets powered up in rtl_open() */ 5447 rtl_pll_power_down(tp); 5448 5449 rc = register_netdev(dev); 5450 if (rc) 5451 return rc; 5452 5453 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5454 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5455 pci_irq_vector(pdev, 0)); 5456 5457 if (jumbo_max) 5458 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5459 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5460 "ok" : "ko"); 5461 5462 if (r8168_check_dash(tp)) 5463 rtl8168_driver_start(tp); 5464 5465 if (pci_dev_run_wake(pdev)) 5466 pm_runtime_put_sync(&pdev->dev); 5467 5468 return 0; 5469 } 5470 5471 static struct pci_driver rtl8169_pci_driver = { 5472 .name = MODULENAME, 5473 .id_table = rtl8169_pci_tbl, 5474 .probe = rtl_init_one, 5475 .remove = rtl_remove_one, 5476 .shutdown = rtl_shutdown, 5477 .driver.pm = RTL8169_PM_OPS, 5478 }; 5479 5480 module_pci_driver(rtl8169_pci_driver); 5481