1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/hwmon.h> 20 #include <linux/phy.h> 21 #include <linux/if_vlan.h> 22 #include <linux/in.h> 23 #include <linux/io.h> 24 #include <linux/ip.h> 25 #include <linux/tcp.h> 26 #include <linux/interrupt.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/bitfield.h> 30 #include <linux/prefetch.h> 31 #include <linux/ipv6.h> 32 #include <linux/unaligned.h> 33 #include <net/ip6_checksum.h> 34 #include <net/netdev_queues.h> 35 36 #include "r8169.h" 37 #include "r8169_firmware.h" 38 39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" 59 #define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" 60 #define FIRMWARE_8126A_2 "rtl_nic/rtl8126a-2.fw" 61 #define FIRMWARE_8126A_3 "rtl_nic/rtl8126a-3.fw" 62 63 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 64 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 65 66 #define R8169_REGS_SIZE 256 67 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 68 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */ 69 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ 70 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 71 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 72 #define R8169_TX_STOP_THRS (MAX_SKB_FRAGS + 1) 73 #define R8169_TX_START_THRS (2 * R8169_TX_STOP_THRS) 74 75 #define OCP_STD_PHY_BASE 0xa400 76 77 #define RTL_CFG_NO_GBIT 1 78 79 /* write/read MMIO register */ 80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 86 87 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 91 92 static const struct { 93 const char *name; 94 const char *fw_name; 95 } rtl_chip_infos[] = { 96 /* PCI devices. */ 97 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 98 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 99 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 100 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 101 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 102 /* PCI-E devices. */ 103 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 105 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 106 [RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e" }, 107 [RTL_GIGA_MAC_VER_14] = {"RTL8401" }, 108 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 109 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 110 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 111 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 112 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 113 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 114 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 115 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 116 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 117 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 118 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 119 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 120 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 121 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 122 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 123 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 124 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 125 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 126 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 127 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 128 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 129 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 130 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 131 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 132 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 133 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 134 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 135 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 136 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 137 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 138 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", }, 139 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3}, 140 /* reserve 62 for CFG_METHOD_4 in the vendor driver */ 141 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2}, 142 [RTL_GIGA_MAC_VER_64] = {"RTL8125D", FIRMWARE_8125D_1}, 143 [RTL_GIGA_MAC_VER_65] = {"RTL8126A", FIRMWARE_8126A_2}, 144 [RTL_GIGA_MAC_VER_66] = {"RTL8126A", FIRMWARE_8126A_3}, 145 }; 146 147 static const struct pci_device_id rtl8169_pci_tbl[] = { 148 { PCI_VDEVICE(REALTEK, 0x2502) }, 149 { PCI_VDEVICE(REALTEK, 0x2600) }, 150 { PCI_VDEVICE(REALTEK, 0x8129) }, 151 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 152 { PCI_VDEVICE(REALTEK, 0x8161) }, 153 { PCI_VDEVICE(REALTEK, 0x8162) }, 154 { PCI_VDEVICE(REALTEK, 0x8167) }, 155 { PCI_VDEVICE(REALTEK, 0x8168) }, 156 { PCI_VDEVICE(NCUBE, 0x8168) }, 157 { PCI_VDEVICE(REALTEK, 0x8169) }, 158 { PCI_VENDOR_ID_DLINK, 0x4300, 159 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 160 { PCI_VDEVICE(DLINK, 0x4300) }, 161 { PCI_VDEVICE(DLINK, 0x4302) }, 162 { PCI_VDEVICE(AT, 0xc107) }, 163 { PCI_VDEVICE(USR, 0x0116) }, 164 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 165 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 166 { PCI_VDEVICE(REALTEK, 0x8125) }, 167 { PCI_VDEVICE(REALTEK, 0x8126) }, 168 { PCI_VDEVICE(REALTEK, 0x3000) }, 169 {} 170 }; 171 172 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 173 174 enum rtl_registers { 175 MAC0 = 0, /* Ethernet hardware address. */ 176 MAC4 = 4, 177 MAR0 = 8, /* Multicast filter. */ 178 CounterAddrLow = 0x10, 179 CounterAddrHigh = 0x14, 180 TxDescStartAddrLow = 0x20, 181 TxDescStartAddrHigh = 0x24, 182 TxHDescStartAddrLow = 0x28, 183 TxHDescStartAddrHigh = 0x2c, 184 FLASH = 0x30, 185 ERSR = 0x36, 186 ChipCmd = 0x37, 187 TxPoll = 0x38, 188 IntrMask = 0x3c, 189 IntrStatus = 0x3e, 190 191 TxConfig = 0x40, 192 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 193 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 194 195 RxConfig = 0x44, 196 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 197 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 198 #define RXCFG_FIFO_SHIFT 13 199 /* No threshold before first PCI xfer */ 200 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 201 #define RX_EARLY_OFF (1 << 11) 202 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */ 203 #define RXCFG_DMA_SHIFT 8 204 /* Unlimited maximum PCI burst. */ 205 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 206 207 Cfg9346 = 0x50, 208 Config0 = 0x51, 209 Config1 = 0x52, 210 Config2 = 0x53, 211 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 212 213 Config3 = 0x54, 214 Config4 = 0x55, 215 Config5 = 0x56, 216 PHYAR = 0x60, 217 PHYstatus = 0x6c, 218 RxMaxSize = 0xda, 219 CPlusCmd = 0xe0, 220 IntrMitigate = 0xe2, 221 222 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 223 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 224 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 225 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 226 227 #define RTL_COALESCE_T_MAX 0x0fU 228 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 229 230 RxDescAddrLow = 0xe4, 231 RxDescAddrHigh = 0xe8, 232 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 233 234 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 235 236 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 237 238 #define TxPacketMax (8064 >> 7) 239 #define EarlySize 0x27 240 241 FuncEvent = 0xf0, 242 FuncEventMask = 0xf4, 243 FuncPresetState = 0xf8, 244 IBCR0 = 0xf8, 245 IBCR2 = 0xf9, 246 IBIMR0 = 0xfa, 247 IBISR0 = 0xfb, 248 FuncForceEvent = 0xfc, 249 }; 250 251 enum rtl8168_8101_registers { 252 CSIDR = 0x64, 253 CSIAR = 0x68, 254 #define CSIAR_FLAG 0x80000000 255 #define CSIAR_WRITE_CMD 0x80000000 256 #define CSIAR_BYTE_ENABLE 0x0000f000 257 #define CSIAR_ADDR_MASK 0x00000fff 258 PMCH = 0x6f, 259 #define D3COLD_NO_PLL_DOWN BIT(7) 260 #define D3HOT_NO_PLL_DOWN BIT(6) 261 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6)) 262 EPHYAR = 0x80, 263 #define EPHYAR_FLAG 0x80000000 264 #define EPHYAR_WRITE_CMD 0x80000000 265 #define EPHYAR_REG_MASK 0x1f 266 #define EPHYAR_REG_SHIFT 16 267 #define EPHYAR_DATA_MASK 0xffff 268 DLLPR = 0xd0, 269 #define PFM_EN (1 << 6) 270 #define TX_10M_PS_EN (1 << 7) 271 DBG_REG = 0xd1, 272 #define FIX_NAK_1 (1 << 4) 273 #define FIX_NAK_2 (1 << 3) 274 TWSI = 0xd2, 275 MCU = 0xd3, 276 #define NOW_IS_OOB (1 << 7) 277 #define TX_EMPTY (1 << 5) 278 #define RX_EMPTY (1 << 4) 279 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 280 #define EN_NDP (1 << 3) 281 #define EN_OOB_RESET (1 << 2) 282 #define LINK_LIST_RDY (1 << 1) 283 EFUSEAR = 0xdc, 284 #define EFUSEAR_FLAG 0x80000000 285 #define EFUSEAR_WRITE_CMD 0x80000000 286 #define EFUSEAR_READ_CMD 0x00000000 287 #define EFUSEAR_REG_MASK 0x03ff 288 #define EFUSEAR_REG_SHIFT 8 289 #define EFUSEAR_DATA_MASK 0xff 290 MISC_1 = 0xf2, 291 #define PFM_D3COLD_EN (1 << 6) 292 }; 293 294 enum rtl8168_registers { 295 LED_CTRL = 0x18, 296 LED_FREQ = 0x1a, 297 EEE_LED = 0x1b, 298 ERIDR = 0x70, 299 ERIAR = 0x74, 300 #define ERIAR_FLAG 0x80000000 301 #define ERIAR_WRITE_CMD 0x80000000 302 #define ERIAR_READ_CMD 0x00000000 303 #define ERIAR_ADDR_BYTE_ALIGN 4 304 #define ERIAR_TYPE_SHIFT 16 305 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 306 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 308 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 309 #define ERIAR_MASK_SHIFT 12 310 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 311 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 313 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 314 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 315 EPHY_RXER_NUM = 0x7c, 316 OCPDR = 0xb0, /* OCP GPHY access */ 317 #define OCPDR_WRITE_CMD 0x80000000 318 #define OCPDR_READ_CMD 0x00000000 319 #define OCPDR_REG_MASK 0x7f 320 #define OCPDR_GPHY_REG_SHIFT 16 321 #define OCPDR_DATA_MASK 0xffff 322 OCPAR = 0xb4, 323 #define OCPAR_FLAG 0x80000000 324 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 325 #define OCPAR_GPHY_READ_CMD 0x0000f060 326 GPHY_OCP = 0xb8, 327 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 328 MISC = 0xf0, /* 8168e only. */ 329 #define TXPLA_RST (1 << 29) 330 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 331 #define PWM_EN (1 << 22) 332 #define RXDV_GATED_EN (1 << 19) 333 #define EARLY_TALLY_EN (1 << 16) 334 }; 335 336 enum rtl8125_registers { 337 LEDSEL0 = 0x18, 338 INT_CFG0_8125 = 0x34, 339 #define INT_CFG0_ENABLE_8125 BIT(0) 340 #define INT_CFG0_CLKREQEN BIT(3) 341 IntrMask_8125 = 0x38, 342 IntrStatus_8125 = 0x3c, 343 INT_CFG1_8125 = 0x7a, 344 LEDSEL2 = 0x84, 345 LEDSEL1 = 0x86, 346 TxPoll_8125 = 0x90, 347 LEDSEL3 = 0x96, 348 MAC0_BKP = 0x19e0, 349 RSS_CTRL_8125 = 0x4500, 350 Q_NUM_CTRL_8125 = 0x4800, 351 EEE_TXIDLE_TIMER_8125 = 0x6048, 352 }; 353 354 #define LEDSEL_MASK_8125 0x23f 355 356 #define RX_VLAN_INNER_8125 BIT(22) 357 #define RX_VLAN_OUTER_8125 BIT(23) 358 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 359 360 #define RX_FETCH_DFLT_8125 (8 << 27) 361 362 enum rtl_register_content { 363 /* InterruptStatusBits */ 364 SYSErr = 0x8000, 365 PCSTimeout = 0x4000, 366 SWInt = 0x0100, 367 TxDescUnavail = 0x0080, 368 RxFIFOOver = 0x0040, 369 LinkChg = 0x0020, 370 RxOverflow = 0x0010, 371 TxErr = 0x0008, 372 TxOK = 0x0004, 373 RxErr = 0x0002, 374 RxOK = 0x0001, 375 376 /* RxStatusDesc */ 377 RxRWT = (1 << 22), 378 RxRES = (1 << 21), 379 RxRUNT = (1 << 20), 380 RxCRC = (1 << 19), 381 382 /* ChipCmdBits */ 383 StopReq = 0x80, 384 CmdReset = 0x10, 385 CmdRxEnb = 0x08, 386 CmdTxEnb = 0x04, 387 RxBufEmpty = 0x01, 388 389 /* TXPoll register p.5 */ 390 HPQ = 0x80, /* Poll cmd on the high prio queue */ 391 NPQ = 0x40, /* Poll cmd on the low prio queue */ 392 FSWInt = 0x01, /* Forced software interrupt */ 393 394 /* Cfg9346Bits */ 395 Cfg9346_Lock = 0x00, 396 Cfg9346_Unlock = 0xc0, 397 398 /* rx_mode_bits */ 399 AcceptErr = 0x20, 400 AcceptRunt = 0x10, 401 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 402 AcceptBroadcast = 0x08, 403 AcceptMulticast = 0x04, 404 AcceptMyPhys = 0x02, 405 AcceptAllPhys = 0x01, 406 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 407 #define RX_CONFIG_ACCEPT_MASK 0x3f 408 409 /* TxConfigBits */ 410 TxInterFrameGapShift = 24, 411 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 412 413 /* Config1 register p.24 */ 414 LEDS1 = (1 << 7), 415 LEDS0 = (1 << 6), 416 Speed_down = (1 << 4), 417 MEMMAP = (1 << 3), 418 IOMAP = (1 << 2), 419 VPD = (1 << 1), 420 PMEnable = (1 << 0), /* Power Management Enable */ 421 422 /* Config2 register p. 25 */ 423 ClkReqEn = (1 << 7), /* Clock Request Enable */ 424 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 425 PCI_Clock_66MHz = 0x01, 426 PCI_Clock_33MHz = 0x00, 427 428 /* Config3 register p.25 */ 429 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 430 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 431 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 432 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 433 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 434 435 /* Config4 register */ 436 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 437 438 /* Config5 register p.27 */ 439 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 440 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 441 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 442 Spi_en = (1 << 3), 443 LanWake = (1 << 1), /* LanWake enable/disable */ 444 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 445 ASPM_en = (1 << 0), /* ASPM enable */ 446 447 /* CPlusCmd p.31 */ 448 EnableBist = (1 << 15), // 8168 8101 449 Mac_dbgo_oe = (1 << 14), // 8168 8101 450 EnAnaPLL = (1 << 14), // 8169 451 Normal_mode = (1 << 13), // unused 452 Force_half_dup = (1 << 12), // 8168 8101 453 Force_rxflow_en = (1 << 11), // 8168 8101 454 Force_txflow_en = (1 << 10), // 8168 8101 455 Cxpl_dbg_sel = (1 << 9), // 8168 8101 456 ASF = (1 << 8), // 8168 8101 457 PktCntrDisable = (1 << 7), // 8168 8101 458 Mac_dbgo_sel = 0x001c, // 8168 459 RxVlan = (1 << 6), 460 RxChkSum = (1 << 5), 461 PCIDAC = (1 << 4), 462 PCIMulRW = (1 << 3), 463 #define INTT_MASK GENMASK(1, 0) 464 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 465 466 /* rtl8169_PHYstatus */ 467 TBI_Enable = 0x80, 468 TxFlowCtrl = 0x40, 469 RxFlowCtrl = 0x20, 470 _1000bpsF = 0x10, 471 _100bps = 0x08, 472 _10bps = 0x04, 473 LinkStatus = 0x02, 474 FullDup = 0x01, 475 476 /* ResetCounterCommand */ 477 CounterReset = 0x1, 478 479 /* DumpCounterCommand */ 480 CounterDump = 0x8, 481 482 /* magic enable v2 */ 483 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 484 }; 485 486 enum rtl_desc_bit { 487 /* First doubleword. */ 488 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 489 RingEnd = (1 << 30), /* End of descriptor ring */ 490 FirstFrag = (1 << 29), /* First segment of a packet */ 491 LastFrag = (1 << 28), /* Final segment of a packet */ 492 }; 493 494 /* Generic case. */ 495 enum rtl_tx_desc_bit { 496 /* First doubleword. */ 497 TD_LSO = (1 << 27), /* Large Send Offload */ 498 #define TD_MSS_MAX 0x07ffu /* MSS value */ 499 500 /* Second doubleword. */ 501 TxVlanTag = (1 << 17), /* Add VLAN tag */ 502 }; 503 504 /* 8169, 8168b and 810x except 8102e. */ 505 enum rtl_tx_desc_bit_0 { 506 /* First doubleword. */ 507 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 508 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 509 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 510 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 511 }; 512 513 /* 8102e, 8168c and beyond. */ 514 enum rtl_tx_desc_bit_1 { 515 /* First doubleword. */ 516 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 517 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 518 #define GTTCPHO_SHIFT 18 519 #define GTTCPHO_MAX 0x7f 520 521 /* Second doubleword. */ 522 #define TCPHO_SHIFT 18 523 #define TCPHO_MAX 0x3ff 524 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 525 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 526 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 527 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 528 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 529 }; 530 531 enum rtl_rx_desc_bit { 532 /* Rx private */ 533 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 534 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 535 536 #define RxProtoUDP (PID1) 537 #define RxProtoTCP (PID0) 538 #define RxProtoIP (PID1 | PID0) 539 #define RxProtoMask RxProtoIP 540 541 IPFail = (1 << 16), /* IP checksum failed */ 542 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 543 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 544 545 #define RxCSFailMask (IPFail | UDPFail | TCPFail) 546 547 RxVlanTag = (1 << 16), /* VLAN tag available */ 548 }; 549 550 #define RTL_GSO_MAX_SIZE_V1 32000 551 #define RTL_GSO_MAX_SEGS_V1 24 552 #define RTL_GSO_MAX_SIZE_V2 64000 553 #define RTL_GSO_MAX_SEGS_V2 64 554 555 struct TxDesc { 556 __le32 opts1; 557 __le32 opts2; 558 __le64 addr; 559 }; 560 561 struct RxDesc { 562 __le32 opts1; 563 __le32 opts2; 564 __le64 addr; 565 }; 566 567 struct ring_info { 568 struct sk_buff *skb; 569 u32 len; 570 }; 571 572 struct rtl8169_counters { 573 __le64 tx_packets; 574 __le64 rx_packets; 575 __le64 tx_errors; 576 __le32 rx_errors; 577 __le16 rx_missed; 578 __le16 align_errors; 579 __le32 tx_one_collision; 580 __le32 tx_multi_collision; 581 __le64 rx_unicast; 582 __le64 rx_broadcast; 583 __le32 rx_multicast; 584 __le16 tx_aborted; 585 __le16 tx_underrun; 586 /* new since RTL8125 */ 587 __le64 tx_octets; 588 __le64 rx_octets; 589 __le64 rx_multicast64; 590 __le64 tx_unicast64; 591 __le64 tx_broadcast64; 592 __le64 tx_multicast64; 593 __le32 tx_pause_on; 594 __le32 tx_pause_off; 595 __le32 tx_pause_all; 596 __le32 tx_deferred; 597 __le32 tx_late_collision; 598 __le32 tx_all_collision; 599 __le32 tx_aborted32; 600 __le32 align_errors32; 601 __le32 rx_frame_too_long; 602 __le32 rx_runt; 603 __le32 rx_pause_on; 604 __le32 rx_pause_off; 605 __le32 rx_pause_all; 606 __le32 rx_unknown_opcode; 607 __le32 rx_mac_error; 608 __le32 tx_underrun32; 609 __le32 rx_mac_missed; 610 __le32 rx_tcam_dropped; 611 __le32 tdu; 612 __le32 rdu; 613 }; 614 615 struct rtl8169_tc_offsets { 616 bool inited; 617 __le64 tx_errors; 618 __le32 tx_multi_collision; 619 __le16 tx_aborted; 620 __le16 rx_missed; 621 }; 622 623 enum rtl_flag { 624 RTL_FLAG_TASK_RESET_PENDING, 625 RTL_FLAG_TASK_TX_TIMEOUT, 626 RTL_FLAG_MAX 627 }; 628 629 enum rtl_dash_type { 630 RTL_DASH_NONE, 631 RTL_DASH_DP, 632 RTL_DASH_EP, 633 }; 634 635 struct rtl8169_private { 636 void __iomem *mmio_addr; /* memory map physical address */ 637 struct pci_dev *pci_dev; 638 struct net_device *dev; 639 struct phy_device *phydev; 640 struct napi_struct napi; 641 enum mac_version mac_version; 642 enum rtl_dash_type dash_type; 643 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 644 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 645 u32 dirty_tx; 646 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 647 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 648 dma_addr_t TxPhyAddr; 649 dma_addr_t RxPhyAddr; 650 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 651 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 652 u16 cp_cmd; 653 u16 tx_lpi_timer; 654 u32 irq_mask; 655 int irq; 656 struct clk *clk; 657 658 struct { 659 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 660 struct work_struct work; 661 } wk; 662 663 raw_spinlock_t mac_ocp_lock; 664 struct mutex led_lock; /* serialize LED ctrl RMW access */ 665 666 unsigned supports_gmii:1; 667 unsigned aspm_manageable:1; 668 unsigned dash_enabled:1; 669 dma_addr_t counters_phys_addr; 670 struct rtl8169_counters *counters; 671 struct rtl8169_tc_offsets tc_offset; 672 u32 saved_wolopts; 673 674 const char *fw_name; 675 struct rtl_fw *rtl_fw; 676 677 struct r8169_led_classdev *leds; 678 679 u32 ocp_base; 680 }; 681 682 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 683 684 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 685 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 686 MODULE_SOFTDEP("pre: realtek"); 687 MODULE_LICENSE("GPL"); 688 MODULE_FIRMWARE(FIRMWARE_8168D_1); 689 MODULE_FIRMWARE(FIRMWARE_8168D_2); 690 MODULE_FIRMWARE(FIRMWARE_8168E_1); 691 MODULE_FIRMWARE(FIRMWARE_8168E_2); 692 MODULE_FIRMWARE(FIRMWARE_8168E_3); 693 MODULE_FIRMWARE(FIRMWARE_8105E_1); 694 MODULE_FIRMWARE(FIRMWARE_8168F_1); 695 MODULE_FIRMWARE(FIRMWARE_8168F_2); 696 MODULE_FIRMWARE(FIRMWARE_8402_1); 697 MODULE_FIRMWARE(FIRMWARE_8411_1); 698 MODULE_FIRMWARE(FIRMWARE_8411_2); 699 MODULE_FIRMWARE(FIRMWARE_8106E_1); 700 MODULE_FIRMWARE(FIRMWARE_8106E_2); 701 MODULE_FIRMWARE(FIRMWARE_8168G_2); 702 MODULE_FIRMWARE(FIRMWARE_8168G_3); 703 MODULE_FIRMWARE(FIRMWARE_8168H_2); 704 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 705 MODULE_FIRMWARE(FIRMWARE_8107E_2); 706 MODULE_FIRMWARE(FIRMWARE_8125A_3); 707 MODULE_FIRMWARE(FIRMWARE_8125B_2); 708 MODULE_FIRMWARE(FIRMWARE_8125D_1); 709 MODULE_FIRMWARE(FIRMWARE_8126A_2); 710 MODULE_FIRMWARE(FIRMWARE_8126A_3); 711 712 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 713 { 714 return &tp->pci_dev->dev; 715 } 716 717 static void rtl_lock_config_regs(struct rtl8169_private *tp) 718 { 719 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 720 } 721 722 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 723 { 724 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 725 } 726 727 static void rtl_pci_commit(struct rtl8169_private *tp) 728 { 729 /* Read an arbitrary register to commit a preceding PCI write */ 730 RTL_R8(tp, ChipCmd); 731 } 732 733 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) 734 { 735 u8 val; 736 737 val = RTL_R8(tp, Config2); 738 RTL_W8(tp, Config2, (val & ~clear) | set); 739 } 740 741 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) 742 { 743 u8 val; 744 745 val = RTL_R8(tp, Config5); 746 RTL_W8(tp, Config5, (val & ~clear) | set); 747 } 748 749 static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg, 750 u8 bits, bool cond) 751 { 752 u8 val, old_val; 753 754 old_val = RTL_R8(tp, reg); 755 if (cond) 756 val = old_val | bits; 757 else 758 val = old_val & ~bits; 759 if (val != old_val) 760 RTL_W8(tp, reg, val); 761 } 762 763 static bool rtl_is_8125(struct rtl8169_private *tp) 764 { 765 return tp->mac_version >= RTL_GIGA_MAC_VER_61; 766 } 767 768 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 769 { 770 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 771 tp->mac_version != RTL_GIGA_MAC_VER_39 && 772 tp->mac_version <= RTL_GIGA_MAC_VER_53; 773 } 774 775 static bool rtl_supports_eee(struct rtl8169_private *tp) 776 { 777 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 778 tp->mac_version != RTL_GIGA_MAC_VER_37 && 779 tp->mac_version != RTL_GIGA_MAC_VER_39; 780 } 781 782 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 783 { 784 int i; 785 786 for (i = 0; i < ETH_ALEN; i++) 787 mac[i] = RTL_R8(tp, reg + i); 788 } 789 790 struct rtl_cond { 791 bool (*check)(struct rtl8169_private *); 792 const char *msg; 793 }; 794 795 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 796 unsigned long usecs, int n, bool high) 797 { 798 int i; 799 800 for (i = 0; i < n; i++) { 801 if (c->check(tp) == high) 802 return true; 803 fsleep(usecs); 804 } 805 806 if (net_ratelimit()) 807 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 808 c->msg, !high, n, usecs); 809 return false; 810 } 811 812 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 813 const struct rtl_cond *c, 814 unsigned long d, int n) 815 { 816 return rtl_loop_wait(tp, c, d, n, true); 817 } 818 819 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 820 const struct rtl_cond *c, 821 unsigned long d, int n) 822 { 823 return rtl_loop_wait(tp, c, d, n, false); 824 } 825 826 #define DECLARE_RTL_COND(name) \ 827 static bool name ## _check(struct rtl8169_private *); \ 828 \ 829 static const struct rtl_cond name = { \ 830 .check = name ## _check, \ 831 .msg = #name \ 832 }; \ 833 \ 834 static bool name ## _check(struct rtl8169_private *tp) 835 836 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) 837 { 838 struct device *dev = tp_to_dev(tp); 839 int ret; 840 841 ret = pm_runtime_resume_and_get(dev); 842 if (ret < 0) 843 return ret; 844 845 mutex_lock(&tp->led_lock); 846 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); 847 mutex_unlock(&tp->led_lock); 848 849 pm_runtime_put_sync(dev); 850 851 return 0; 852 } 853 854 int rtl8168_get_led_mode(struct rtl8169_private *tp) 855 { 856 struct device *dev = tp_to_dev(tp); 857 int ret; 858 859 ret = pm_runtime_resume_and_get(dev); 860 if (ret < 0) 861 return ret; 862 863 ret = RTL_R16(tp, LED_CTRL); 864 865 pm_runtime_put_sync(dev); 866 867 return ret; 868 } 869 870 static int rtl8125_get_led_reg(int index) 871 { 872 static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; 873 874 return led_regs[index]; 875 } 876 877 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) 878 { 879 int reg = rtl8125_get_led_reg(index); 880 struct device *dev = tp_to_dev(tp); 881 int ret; 882 u16 val; 883 884 ret = pm_runtime_resume_and_get(dev); 885 if (ret < 0) 886 return ret; 887 888 mutex_lock(&tp->led_lock); 889 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; 890 RTL_W16(tp, reg, val | mode); 891 mutex_unlock(&tp->led_lock); 892 893 pm_runtime_put_sync(dev); 894 895 return 0; 896 } 897 898 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) 899 { 900 int reg = rtl8125_get_led_reg(index); 901 struct device *dev = tp_to_dev(tp); 902 int ret; 903 904 ret = pm_runtime_resume_and_get(dev); 905 if (ret < 0) 906 return ret; 907 908 ret = RTL_R16(tp, reg); 909 910 pm_runtime_put_sync(dev); 911 912 return ret; 913 } 914 915 void r8169_get_led_name(struct rtl8169_private *tp, int idx, 916 char *buf, int buf_len) 917 { 918 struct pci_dev *pdev = tp->pci_dev; 919 char pdom[8], pfun[8]; 920 int domain; 921 922 domain = pci_domain_nr(pdev->bus); 923 if (domain) 924 snprintf(pdom, sizeof(pdom), "P%d", domain); 925 else 926 pdom[0] = '\0'; 927 928 if (pdev->multifunction) 929 snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn)); 930 else 931 pfun[0] = '\0'; 932 933 snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number, 934 PCI_SLOT(pdev->devfn), pfun, idx); 935 } 936 937 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 938 { 939 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 940 if (type == ERIAR_OOB && 941 (tp->mac_version == RTL_GIGA_MAC_VER_52 || 942 tp->mac_version == RTL_GIGA_MAC_VER_53)) 943 *cmd |= 0xf70 << 18; 944 } 945 946 DECLARE_RTL_COND(rtl_eriar_cond) 947 { 948 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 949 } 950 951 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 952 u32 val, int type) 953 { 954 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 955 956 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) 957 return; 958 959 RTL_W32(tp, ERIDR, val); 960 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 961 RTL_W32(tp, ERIAR, cmd); 962 963 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 964 } 965 966 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 967 u32 val) 968 { 969 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 970 } 971 972 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 973 { 974 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 975 976 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 977 RTL_W32(tp, ERIAR, cmd); 978 979 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 980 RTL_R32(tp, ERIDR) : ~0; 981 } 982 983 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 984 { 985 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 986 } 987 988 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 989 { 990 u32 val = rtl_eri_read(tp, addr); 991 992 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 993 } 994 995 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 996 { 997 rtl_w0w1_eri(tp, addr, p, 0); 998 } 999 1000 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1001 { 1002 rtl_w0w1_eri(tp, addr, 0, m); 1003 } 1004 1005 static bool rtl_ocp_reg_failure(u32 reg) 1006 { 1007 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); 1008 } 1009 1010 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 1011 { 1012 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 1013 } 1014 1015 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1016 { 1017 if (rtl_ocp_reg_failure(reg)) 1018 return; 1019 1020 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 1021 1022 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 1023 } 1024 1025 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 1026 { 1027 if (rtl_ocp_reg_failure(reg)) 1028 return 0; 1029 1030 RTL_W32(tp, GPHY_OCP, reg << 15); 1031 1032 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 1033 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 1034 } 1035 1036 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1037 { 1038 if (rtl_ocp_reg_failure(reg)) 1039 return; 1040 1041 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 1042 } 1043 1044 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 1045 { 1046 unsigned long flags; 1047 1048 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1049 __r8168_mac_ocp_write(tp, reg, data); 1050 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1051 } 1052 1053 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1054 { 1055 if (rtl_ocp_reg_failure(reg)) 1056 return 0; 1057 1058 RTL_W32(tp, OCPDR, reg << 15); 1059 1060 return RTL_R32(tp, OCPDR); 1061 } 1062 1063 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 1064 { 1065 unsigned long flags; 1066 u16 val; 1067 1068 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1069 val = __r8168_mac_ocp_read(tp, reg); 1070 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1071 1072 return val; 1073 } 1074 1075 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 1076 u16 set) 1077 { 1078 unsigned long flags; 1079 u16 data; 1080 1081 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 1082 data = __r8168_mac_ocp_read(tp, reg); 1083 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 1084 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 1085 } 1086 1087 /* Work around a hw issue with RTL8168g PHY, the quirk disables 1088 * PHY MCU interrupts before PHY power-down. 1089 */ 1090 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) 1091 { 1092 switch (tp->mac_version) { 1093 case RTL_GIGA_MAC_VER_40: 1094 if (value & BMCR_RESET || !(value & BMCR_PDOWN)) 1095 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 1096 else 1097 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 1098 break; 1099 default: 1100 break; 1101 } 1102 }; 1103 1104 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 1105 { 1106 if (reg == 0x1f) { 1107 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 1108 return; 1109 } 1110 1111 if (tp->ocp_base != OCP_STD_PHY_BASE) 1112 reg -= 0x10; 1113 1114 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) 1115 rtl8168g_phy_suspend_quirk(tp, value); 1116 1117 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 1118 } 1119 1120 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 1121 { 1122 if (reg == 0x1f) 1123 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 1124 1125 if (tp->ocp_base != OCP_STD_PHY_BASE) 1126 reg -= 0x10; 1127 1128 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 1129 } 1130 1131 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 1132 { 1133 if (reg == 0x1f) { 1134 tp->ocp_base = value << 4; 1135 return; 1136 } 1137 1138 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 1139 } 1140 1141 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 1142 { 1143 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 1144 } 1145 1146 DECLARE_RTL_COND(rtl_phyar_cond) 1147 { 1148 return RTL_R32(tp, PHYAR) & 0x80000000; 1149 } 1150 1151 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 1152 { 1153 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 1154 1155 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 1156 /* 1157 * According to hardware specs a 20us delay is required after write 1158 * complete indication, but before sending next command. 1159 */ 1160 udelay(20); 1161 } 1162 1163 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 1164 { 1165 int value; 1166 1167 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 1168 1169 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 1170 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 1171 1172 /* 1173 * According to hardware specs a 20us delay is required after read 1174 * complete indication, but before sending next command. 1175 */ 1176 udelay(20); 1177 1178 return value; 1179 } 1180 1181 DECLARE_RTL_COND(rtl_ocpar_cond) 1182 { 1183 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 1184 } 1185 1186 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 1187 1188 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 1189 { 1190 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 1191 } 1192 1193 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 1194 { 1195 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 1196 } 1197 1198 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 1199 { 1200 r8168dp_2_mdio_start(tp); 1201 1202 r8169_mdio_write(tp, reg, value); 1203 1204 r8168dp_2_mdio_stop(tp); 1205 } 1206 1207 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 1208 { 1209 int value; 1210 1211 /* Work around issue with chip reporting wrong PHY ID */ 1212 if (reg == MII_PHYSID2) 1213 return 0xc912; 1214 1215 r8168dp_2_mdio_start(tp); 1216 1217 value = r8169_mdio_read(tp, reg); 1218 1219 r8168dp_2_mdio_stop(tp); 1220 1221 return value; 1222 } 1223 1224 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 1225 { 1226 switch (tp->mac_version) { 1227 case RTL_GIGA_MAC_VER_28: 1228 case RTL_GIGA_MAC_VER_31: 1229 r8168dp_2_mdio_write(tp, location, val); 1230 break; 1231 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1232 r8168g_mdio_write(tp, location, val); 1233 break; 1234 default: 1235 r8169_mdio_write(tp, location, val); 1236 break; 1237 } 1238 } 1239 1240 static int rtl_readphy(struct rtl8169_private *tp, int location) 1241 { 1242 switch (tp->mac_version) { 1243 case RTL_GIGA_MAC_VER_28: 1244 case RTL_GIGA_MAC_VER_31: 1245 return r8168dp_2_mdio_read(tp, location); 1246 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 1247 return r8168g_mdio_read(tp, location); 1248 default: 1249 return r8169_mdio_read(tp, location); 1250 } 1251 } 1252 1253 DECLARE_RTL_COND(rtl_ephyar_cond) 1254 { 1255 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1256 } 1257 1258 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1259 { 1260 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1261 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1262 1263 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1264 1265 udelay(10); 1266 } 1267 1268 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1269 { 1270 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1271 1272 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1273 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1274 } 1275 1276 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1277 { 1278 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1279 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1280 RTL_R32(tp, OCPDR) : ~0; 1281 } 1282 1283 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1284 { 1285 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1286 } 1287 1288 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1289 u32 data) 1290 { 1291 RTL_W32(tp, OCPDR, data); 1292 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1293 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1294 } 1295 1296 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1297 u32 data) 1298 { 1299 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1300 data, ERIAR_OOB); 1301 } 1302 1303 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1304 { 1305 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1306 1307 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1308 } 1309 1310 #define OOB_CMD_RESET 0x00 1311 #define OOB_CMD_DRIVER_START 0x05 1312 #define OOB_CMD_DRIVER_STOP 0x06 1313 1314 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1315 { 1316 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1317 } 1318 1319 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1320 { 1321 u16 reg; 1322 1323 reg = rtl8168_get_ocp_reg(tp); 1324 1325 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1326 } 1327 1328 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1329 { 1330 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1331 } 1332 1333 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1334 { 1335 return RTL_R8(tp, IBISR0) & 0x20; 1336 } 1337 1338 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1339 { 1340 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1341 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1342 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1343 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1344 } 1345 1346 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1347 { 1348 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1349 if (tp->dash_enabled) 1350 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1351 } 1352 1353 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1354 { 1355 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1356 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1357 if (tp->dash_enabled) 1358 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); 1359 } 1360 1361 static void rtl8168_driver_start(struct rtl8169_private *tp) 1362 { 1363 if (tp->dash_type == RTL_DASH_DP) 1364 rtl8168dp_driver_start(tp); 1365 else 1366 rtl8168ep_driver_start(tp); 1367 } 1368 1369 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1370 { 1371 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1372 if (tp->dash_enabled) 1373 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1374 } 1375 1376 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1377 { 1378 rtl8168ep_stop_cmac(tp); 1379 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1380 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1381 if (tp->dash_enabled) 1382 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1383 } 1384 1385 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1386 { 1387 if (tp->dash_type == RTL_DASH_DP) 1388 rtl8168dp_driver_stop(tp); 1389 else 1390 rtl8168ep_driver_stop(tp); 1391 } 1392 1393 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1394 { 1395 u16 reg = rtl8168_get_ocp_reg(tp); 1396 1397 return r8168dp_ocp_read(tp, reg) & BIT(15); 1398 } 1399 1400 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1401 { 1402 return r8168ep_ocp_read(tp, 0x128) & BIT(0); 1403 } 1404 1405 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) 1406 { 1407 switch (tp->dash_type) { 1408 case RTL_DASH_DP: 1409 return r8168dp_check_dash(tp); 1410 case RTL_DASH_EP: 1411 return r8168ep_check_dash(tp); 1412 default: 1413 return false; 1414 } 1415 } 1416 1417 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) 1418 { 1419 switch (tp->mac_version) { 1420 case RTL_GIGA_MAC_VER_28: 1421 case RTL_GIGA_MAC_VER_31: 1422 return RTL_DASH_DP; 1423 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 1424 return RTL_DASH_EP; 1425 default: 1426 return RTL_DASH_NONE; 1427 } 1428 } 1429 1430 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) 1431 { 1432 if (tp->mac_version >= RTL_GIGA_MAC_VER_25 && 1433 tp->mac_version != RTL_GIGA_MAC_VER_28 && 1434 tp->mac_version != RTL_GIGA_MAC_VER_31 && 1435 tp->mac_version != RTL_GIGA_MAC_VER_38) 1436 r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, !enable); 1437 } 1438 1439 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1440 { 1441 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1442 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1443 } 1444 1445 DECLARE_RTL_COND(rtl_efusear_cond) 1446 { 1447 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1448 } 1449 1450 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1451 { 1452 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1453 1454 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1455 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1456 } 1457 1458 static u32 rtl_get_events(struct rtl8169_private *tp) 1459 { 1460 if (rtl_is_8125(tp)) 1461 return RTL_R32(tp, IntrStatus_8125); 1462 else 1463 return RTL_R16(tp, IntrStatus); 1464 } 1465 1466 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1467 { 1468 if (rtl_is_8125(tp)) 1469 RTL_W32(tp, IntrStatus_8125, bits); 1470 else 1471 RTL_W16(tp, IntrStatus, bits); 1472 } 1473 1474 static void rtl_irq_disable(struct rtl8169_private *tp) 1475 { 1476 if (rtl_is_8125(tp)) 1477 RTL_W32(tp, IntrMask_8125, 0); 1478 else 1479 RTL_W16(tp, IntrMask, 0); 1480 } 1481 1482 static void rtl_irq_enable(struct rtl8169_private *tp) 1483 { 1484 if (rtl_is_8125(tp)) 1485 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1486 else 1487 RTL_W16(tp, IntrMask, tp->irq_mask); 1488 } 1489 1490 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1491 { 1492 rtl_irq_disable(tp); 1493 rtl_ack_events(tp, 0xffffffff); 1494 rtl_pci_commit(tp); 1495 } 1496 1497 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1498 { 1499 struct phy_device *phydev = tp->phydev; 1500 1501 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1502 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1503 if (phydev->speed == SPEED_1000) { 1504 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1505 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1506 } else if (phydev->speed == SPEED_100) { 1507 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1508 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1509 } else { 1510 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1511 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1512 } 1513 rtl_reset_packet_filter(tp); 1514 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1515 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1516 if (phydev->speed == SPEED_1000) { 1517 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1518 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1519 } else { 1520 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1521 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1522 } 1523 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1524 if (phydev->speed == SPEED_10) { 1525 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1526 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1527 } else { 1528 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1529 } 1530 } 1531 } 1532 1533 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1534 1535 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1536 { 1537 struct rtl8169_private *tp = netdev_priv(dev); 1538 1539 wol->supported = WAKE_ANY; 1540 wol->wolopts = tp->saved_wolopts; 1541 } 1542 1543 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1544 { 1545 rtl_unlock_config_regs(tp); 1546 1547 if (rtl_is_8168evl_up(tp)) { 1548 if (wolopts & WAKE_MAGIC) 1549 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1550 else 1551 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1552 } else if (rtl_is_8125(tp)) { 1553 if (wolopts & WAKE_MAGIC) 1554 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1555 else 1556 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1557 } else { 1558 r8169_mod_reg8_cond(tp, Config3, MagicPacket, 1559 wolopts & WAKE_MAGIC); 1560 } 1561 1562 r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY); 1563 if (rtl_is_8125(tp)) 1564 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, 1565 wolopts & WAKE_PHY ? 0x13 : 0); 1566 r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST); 1567 r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST); 1568 r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST); 1569 r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts); 1570 1571 switch (tp->mac_version) { 1572 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1573 r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts); 1574 break; 1575 case RTL_GIGA_MAC_VER_34: 1576 case RTL_GIGA_MAC_VER_37: 1577 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_66: 1578 r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts); 1579 break; 1580 default: 1581 break; 1582 } 1583 1584 rtl_lock_config_regs(tp); 1585 1586 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1587 1588 if (!tp->dash_enabled) { 1589 rtl_set_d3_pll_down(tp, !wolopts); 1590 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; 1591 } 1592 } 1593 1594 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1595 { 1596 struct rtl8169_private *tp = netdev_priv(dev); 1597 1598 if (wol->wolopts & ~WAKE_ANY) 1599 return -EINVAL; 1600 1601 tp->saved_wolopts = wol->wolopts; 1602 __rtl8169_set_wol(tp, tp->saved_wolopts); 1603 1604 return 0; 1605 } 1606 1607 static void rtl8169_get_drvinfo(struct net_device *dev, 1608 struct ethtool_drvinfo *info) 1609 { 1610 struct rtl8169_private *tp = netdev_priv(dev); 1611 struct rtl_fw *rtl_fw = tp->rtl_fw; 1612 1613 strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); 1614 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1615 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1616 if (rtl_fw) 1617 strscpy(info->fw_version, rtl_fw->version, 1618 sizeof(info->fw_version)); 1619 } 1620 1621 static int rtl8169_get_regs_len(struct net_device *dev) 1622 { 1623 return R8169_REGS_SIZE; 1624 } 1625 1626 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1627 netdev_features_t features) 1628 { 1629 struct rtl8169_private *tp = netdev_priv(dev); 1630 1631 if (dev->mtu > TD_MSS_MAX) 1632 features &= ~NETIF_F_ALL_TSO; 1633 1634 if (dev->mtu > ETH_DATA_LEN && 1635 tp->mac_version > RTL_GIGA_MAC_VER_06) 1636 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1637 1638 return features; 1639 } 1640 1641 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1642 netdev_features_t features) 1643 { 1644 u32 rx_config = RTL_R32(tp, RxConfig); 1645 1646 if (features & NETIF_F_RXALL) 1647 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1648 else 1649 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1650 1651 if (rtl_is_8125(tp)) { 1652 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1653 rx_config |= RX_VLAN_8125; 1654 else 1655 rx_config &= ~RX_VLAN_8125; 1656 } 1657 1658 RTL_W32(tp, RxConfig, rx_config); 1659 } 1660 1661 static int rtl8169_set_features(struct net_device *dev, 1662 netdev_features_t features) 1663 { 1664 struct rtl8169_private *tp = netdev_priv(dev); 1665 1666 rtl_set_rx_config_features(tp, features); 1667 1668 if (features & NETIF_F_RXCSUM) 1669 tp->cp_cmd |= RxChkSum; 1670 else 1671 tp->cp_cmd &= ~RxChkSum; 1672 1673 if (!rtl_is_8125(tp)) { 1674 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1675 tp->cp_cmd |= RxVlan; 1676 else 1677 tp->cp_cmd &= ~RxVlan; 1678 } 1679 1680 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1681 rtl_pci_commit(tp); 1682 1683 return 0; 1684 } 1685 1686 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1687 { 1688 return (skb_vlan_tag_present(skb)) ? 1689 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1690 } 1691 1692 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1693 { 1694 u32 opts2 = le32_to_cpu(desc->opts2); 1695 1696 if (opts2 & RxVlanTag) 1697 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1698 } 1699 1700 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1701 void *p) 1702 { 1703 struct rtl8169_private *tp = netdev_priv(dev); 1704 u32 __iomem *data = tp->mmio_addr; 1705 u32 *dw = p; 1706 int i; 1707 1708 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1709 memcpy_fromio(dw++, data++, 4); 1710 } 1711 1712 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1713 "tx_packets", 1714 "rx_packets", 1715 "tx_errors", 1716 "rx_errors", 1717 "rx_missed", 1718 "align_errors", 1719 "tx_single_collisions", 1720 "tx_multi_collisions", 1721 "unicast", 1722 "broadcast", 1723 "multicast", 1724 "tx_aborted", 1725 "tx_underrun", 1726 }; 1727 1728 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1729 { 1730 switch (sset) { 1731 case ETH_SS_STATS: 1732 return ARRAY_SIZE(rtl8169_gstrings); 1733 default: 1734 return -EOPNOTSUPP; 1735 } 1736 } 1737 1738 DECLARE_RTL_COND(rtl_counters_cond) 1739 { 1740 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1741 } 1742 1743 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1744 { 1745 u32 cmd = lower_32_bits(tp->counters_phys_addr); 1746 1747 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); 1748 rtl_pci_commit(tp); 1749 RTL_W32(tp, CounterAddrLow, cmd); 1750 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1751 1752 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1753 } 1754 1755 static void rtl8169_update_counters(struct rtl8169_private *tp) 1756 { 1757 u8 val = RTL_R8(tp, ChipCmd); 1758 1759 /* 1760 * Some chips are unable to dump tally counters when the receiver 1761 * is disabled. If 0xff chip may be in a PCI power-save state. 1762 */ 1763 if (val & CmdRxEnb && val != 0xff) 1764 rtl8169_do_counters(tp, CounterDump); 1765 } 1766 1767 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1768 { 1769 struct rtl8169_counters *counters = tp->counters; 1770 1771 /* 1772 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1773 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1774 * reset by a power cycle, while the counter values collected by the 1775 * driver are reset at every driver unload/load cycle. 1776 * 1777 * To make sure the HW values returned by @get_stats64 match the SW 1778 * values, we collect the initial values at first open(*) and use them 1779 * as offsets to normalize the values returned by @get_stats64. 1780 * 1781 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1782 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1783 * set at open time by rtl_hw_start. 1784 */ 1785 1786 if (tp->tc_offset.inited) 1787 return; 1788 1789 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { 1790 rtl8169_do_counters(tp, CounterReset); 1791 } else { 1792 rtl8169_update_counters(tp); 1793 tp->tc_offset.tx_errors = counters->tx_errors; 1794 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1795 tp->tc_offset.tx_aborted = counters->tx_aborted; 1796 tp->tc_offset.rx_missed = counters->rx_missed; 1797 } 1798 1799 tp->tc_offset.inited = true; 1800 } 1801 1802 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1803 struct ethtool_stats *stats, u64 *data) 1804 { 1805 struct rtl8169_private *tp = netdev_priv(dev); 1806 struct rtl8169_counters *counters; 1807 1808 counters = tp->counters; 1809 rtl8169_update_counters(tp); 1810 1811 data[0] = le64_to_cpu(counters->tx_packets); 1812 data[1] = le64_to_cpu(counters->rx_packets); 1813 data[2] = le64_to_cpu(counters->tx_errors); 1814 data[3] = le32_to_cpu(counters->rx_errors); 1815 data[4] = le16_to_cpu(counters->rx_missed); 1816 data[5] = le16_to_cpu(counters->align_errors); 1817 data[6] = le32_to_cpu(counters->tx_one_collision); 1818 data[7] = le32_to_cpu(counters->tx_multi_collision); 1819 data[8] = le64_to_cpu(counters->rx_unicast); 1820 data[9] = le64_to_cpu(counters->rx_broadcast); 1821 data[10] = le32_to_cpu(counters->rx_multicast); 1822 data[11] = le16_to_cpu(counters->tx_aborted); 1823 data[12] = le16_to_cpu(counters->tx_underrun); 1824 } 1825 1826 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1827 { 1828 switch(stringset) { 1829 case ETH_SS_STATS: 1830 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1831 break; 1832 } 1833 } 1834 1835 /* 1836 * Interrupt coalescing 1837 * 1838 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1839 * > 8169, 8168 and 810x line of chipsets 1840 * 1841 * 8169, 8168, and 8136(810x) serial chipsets support it. 1842 * 1843 * > 2 - the Tx timer unit at gigabit speed 1844 * 1845 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1846 * (0xe0) bit 1 and bit 0. 1847 * 1848 * For 8169 1849 * bit[1:0] \ speed 1000M 100M 10M 1850 * 0 0 320ns 2.56us 40.96us 1851 * 0 1 2.56us 20.48us 327.7us 1852 * 1 0 5.12us 40.96us 655.4us 1853 * 1 1 10.24us 81.92us 1.31ms 1854 * 1855 * For the other 1856 * bit[1:0] \ speed 1000M 100M 10M 1857 * 0 0 5us 2.56us 40.96us 1858 * 0 1 40us 20.48us 327.7us 1859 * 1 0 80us 40.96us 655.4us 1860 * 1 1 160us 81.92us 1.31ms 1861 */ 1862 1863 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1864 struct rtl_coalesce_info { 1865 u32 speed; 1866 u32 scale_nsecs[4]; 1867 }; 1868 1869 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1870 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1871 1872 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1873 { SPEED_1000, COALESCE_DELAY(320) }, 1874 { SPEED_100, COALESCE_DELAY(2560) }, 1875 { SPEED_10, COALESCE_DELAY(40960) }, 1876 { 0 }, 1877 }; 1878 1879 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1880 { SPEED_1000, COALESCE_DELAY(5000) }, 1881 { SPEED_100, COALESCE_DELAY(2560) }, 1882 { SPEED_10, COALESCE_DELAY(40960) }, 1883 { 0 }, 1884 }; 1885 #undef COALESCE_DELAY 1886 1887 /* get rx/tx scale vector corresponding to current speed */ 1888 static const struct rtl_coalesce_info * 1889 rtl_coalesce_info(struct rtl8169_private *tp) 1890 { 1891 const struct rtl_coalesce_info *ci; 1892 1893 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1894 ci = rtl_coalesce_info_8169; 1895 else 1896 ci = rtl_coalesce_info_8168_8136; 1897 1898 /* if speed is unknown assume highest one */ 1899 if (tp->phydev->speed == SPEED_UNKNOWN) 1900 return ci; 1901 1902 for (; ci->speed; ci++) { 1903 if (tp->phydev->speed == ci->speed) 1904 return ci; 1905 } 1906 1907 return ERR_PTR(-ELNRNG); 1908 } 1909 1910 static int rtl_get_coalesce(struct net_device *dev, 1911 struct ethtool_coalesce *ec, 1912 struct kernel_ethtool_coalesce *kernel_coal, 1913 struct netlink_ext_ack *extack) 1914 { 1915 struct rtl8169_private *tp = netdev_priv(dev); 1916 const struct rtl_coalesce_info *ci; 1917 u32 scale, c_us, c_fr; 1918 u16 intrmit; 1919 1920 if (rtl_is_8125(tp)) 1921 return -EOPNOTSUPP; 1922 1923 memset(ec, 0, sizeof(*ec)); 1924 1925 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1926 ci = rtl_coalesce_info(tp); 1927 if (IS_ERR(ci)) 1928 return PTR_ERR(ci); 1929 1930 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1931 1932 intrmit = RTL_R16(tp, IntrMitigate); 1933 1934 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1935 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1936 1937 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1938 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1939 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1940 1941 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1942 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1943 1944 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1945 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1946 1947 return 0; 1948 } 1949 1950 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1951 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1952 u16 *cp01) 1953 { 1954 const struct rtl_coalesce_info *ci; 1955 u16 i; 1956 1957 ci = rtl_coalesce_info(tp); 1958 if (IS_ERR(ci)) 1959 return PTR_ERR(ci); 1960 1961 for (i = 0; i < 4; i++) { 1962 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1963 *cp01 = i; 1964 return ci->scale_nsecs[i]; 1965 } 1966 } 1967 1968 return -ERANGE; 1969 } 1970 1971 static int rtl_set_coalesce(struct net_device *dev, 1972 struct ethtool_coalesce *ec, 1973 struct kernel_ethtool_coalesce *kernel_coal, 1974 struct netlink_ext_ack *extack) 1975 { 1976 struct rtl8169_private *tp = netdev_priv(dev); 1977 u32 tx_fr = ec->tx_max_coalesced_frames; 1978 u32 rx_fr = ec->rx_max_coalesced_frames; 1979 u32 coal_usec_max, units; 1980 u16 w = 0, cp01 = 0; 1981 int scale; 1982 1983 if (rtl_is_8125(tp)) 1984 return -EOPNOTSUPP; 1985 1986 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1987 return -ERANGE; 1988 1989 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1990 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1991 if (scale < 0) 1992 return scale; 1993 1994 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1995 * not only when usecs=0 because of e.g. the following scenario: 1996 * 1997 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1998 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1999 * - then user does `ethtool -C eth0 rx-usecs 100` 2000 * 2001 * Since ethtool sends to kernel whole ethtool_coalesce settings, 2002 * if we want to ignore rx_frames then it has to be set to 0. 2003 */ 2004 if (rx_fr == 1) 2005 rx_fr = 0; 2006 if (tx_fr == 1) 2007 tx_fr = 0; 2008 2009 /* HW requires time limit to be set if frame limit is set */ 2010 if ((tx_fr && !ec->tx_coalesce_usecs) || 2011 (rx_fr && !ec->rx_coalesce_usecs)) 2012 return -EINVAL; 2013 2014 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 2015 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 2016 2017 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 2018 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 2019 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 2020 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 2021 2022 RTL_W16(tp, IntrMitigate, w); 2023 2024 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 2025 if (rtl_is_8168evl_up(tp)) { 2026 if (!rx_fr && !tx_fr) 2027 /* disable packet counter */ 2028 tp->cp_cmd |= PktCntrDisable; 2029 else 2030 tp->cp_cmd &= ~PktCntrDisable; 2031 } 2032 2033 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 2034 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 2035 rtl_pci_commit(tp); 2036 2037 return 0; 2038 } 2039 2040 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) 2041 { 2042 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; 2043 2044 switch (tp->mac_version) { 2045 case RTL_GIGA_MAC_VER_46: 2046 case RTL_GIGA_MAC_VER_48: 2047 tp->tx_lpi_timer = timer_val; 2048 r8168_mac_ocp_write(tp, 0xe048, timer_val); 2049 break; 2050 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2051 tp->tx_lpi_timer = timer_val; 2052 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); 2053 break; 2054 default: 2055 break; 2056 } 2057 } 2058 2059 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) 2060 { 2061 unsigned int speed = tp->phydev->speed; 2062 unsigned int timer = tp->tx_lpi_timer; 2063 2064 if (!timer || speed == SPEED_UNKNOWN) 2065 return 0; 2066 2067 /* tx_lpi_timer value is in bytes */ 2068 return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed); 2069 } 2070 2071 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data) 2072 { 2073 struct rtl8169_private *tp = netdev_priv(dev); 2074 int ret; 2075 2076 if (!rtl_supports_eee(tp)) 2077 return -EOPNOTSUPP; 2078 2079 ret = phy_ethtool_get_eee(tp->phydev, data); 2080 if (ret) 2081 return ret; 2082 2083 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); 2084 2085 return 0; 2086 } 2087 2088 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data) 2089 { 2090 struct rtl8169_private *tp = netdev_priv(dev); 2091 2092 if (!rtl_supports_eee(tp)) 2093 return -EOPNOTSUPP; 2094 2095 return phy_ethtool_set_eee(tp->phydev, data); 2096 } 2097 2098 static void rtl8169_get_ringparam(struct net_device *dev, 2099 struct ethtool_ringparam *data, 2100 struct kernel_ethtool_ringparam *kernel_data, 2101 struct netlink_ext_ack *extack) 2102 { 2103 data->rx_max_pending = NUM_RX_DESC; 2104 data->rx_pending = NUM_RX_DESC; 2105 data->tx_max_pending = NUM_TX_DESC; 2106 data->tx_pending = NUM_TX_DESC; 2107 } 2108 2109 static void rtl8169_get_pause_stats(struct net_device *dev, 2110 struct ethtool_pause_stats *pause_stats) 2111 { 2112 struct rtl8169_private *tp = netdev_priv(dev); 2113 2114 if (!rtl_is_8125(tp)) 2115 return; 2116 2117 rtl8169_update_counters(tp); 2118 pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on); 2119 pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on); 2120 } 2121 2122 static void rtl8169_get_pauseparam(struct net_device *dev, 2123 struct ethtool_pauseparam *data) 2124 { 2125 struct rtl8169_private *tp = netdev_priv(dev); 2126 bool tx_pause, rx_pause; 2127 2128 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); 2129 2130 data->autoneg = tp->phydev->autoneg; 2131 data->tx_pause = tx_pause ? 1 : 0; 2132 data->rx_pause = rx_pause ? 1 : 0; 2133 } 2134 2135 static int rtl8169_set_pauseparam(struct net_device *dev, 2136 struct ethtool_pauseparam *data) 2137 { 2138 struct rtl8169_private *tp = netdev_priv(dev); 2139 2140 if (dev->mtu > ETH_DATA_LEN) 2141 return -EOPNOTSUPP; 2142 2143 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); 2144 2145 return 0; 2146 } 2147 2148 static void rtl8169_get_eth_mac_stats(struct net_device *dev, 2149 struct ethtool_eth_mac_stats *mac_stats) 2150 { 2151 struct rtl8169_private *tp = netdev_priv(dev); 2152 2153 rtl8169_update_counters(tp); 2154 2155 mac_stats->FramesTransmittedOK = 2156 le64_to_cpu(tp->counters->tx_packets); 2157 mac_stats->SingleCollisionFrames = 2158 le32_to_cpu(tp->counters->tx_one_collision); 2159 mac_stats->MultipleCollisionFrames = 2160 le32_to_cpu(tp->counters->tx_multi_collision); 2161 mac_stats->FramesReceivedOK = 2162 le64_to_cpu(tp->counters->rx_packets); 2163 mac_stats->AlignmentErrors = 2164 le16_to_cpu(tp->counters->align_errors); 2165 mac_stats->FramesLostDueToIntMACXmitError = 2166 le64_to_cpu(tp->counters->tx_errors); 2167 mac_stats->BroadcastFramesReceivedOK = 2168 le64_to_cpu(tp->counters->rx_broadcast); 2169 mac_stats->MulticastFramesReceivedOK = 2170 le32_to_cpu(tp->counters->rx_multicast); 2171 2172 if (!rtl_is_8125(tp)) 2173 return; 2174 2175 mac_stats->AlignmentErrors = 2176 le32_to_cpu(tp->counters->align_errors32); 2177 mac_stats->OctetsTransmittedOK = 2178 le64_to_cpu(tp->counters->tx_octets); 2179 mac_stats->LateCollisions = 2180 le32_to_cpu(tp->counters->tx_late_collision); 2181 mac_stats->FramesAbortedDueToXSColls = 2182 le32_to_cpu(tp->counters->tx_aborted32); 2183 mac_stats->OctetsReceivedOK = 2184 le64_to_cpu(tp->counters->rx_octets); 2185 mac_stats->FramesLostDueToIntMACRcvError = 2186 le32_to_cpu(tp->counters->rx_mac_error); 2187 mac_stats->MulticastFramesXmittedOK = 2188 le64_to_cpu(tp->counters->tx_multicast64); 2189 mac_stats->BroadcastFramesXmittedOK = 2190 le64_to_cpu(tp->counters->tx_broadcast64); 2191 mac_stats->MulticastFramesReceivedOK = 2192 le64_to_cpu(tp->counters->rx_multicast64); 2193 mac_stats->FrameTooLongErrors = 2194 le32_to_cpu(tp->counters->rx_frame_too_long); 2195 } 2196 2197 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev, 2198 struct ethtool_eth_ctrl_stats *ctrl_stats) 2199 { 2200 struct rtl8169_private *tp = netdev_priv(dev); 2201 2202 if (!rtl_is_8125(tp)) 2203 return; 2204 2205 rtl8169_update_counters(tp); 2206 2207 ctrl_stats->UnsupportedOpcodesReceived = 2208 le32_to_cpu(tp->counters->rx_unknown_opcode); 2209 } 2210 2211 static const struct ethtool_ops rtl8169_ethtool_ops = { 2212 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2213 ETHTOOL_COALESCE_MAX_FRAMES, 2214 .get_drvinfo = rtl8169_get_drvinfo, 2215 .get_regs_len = rtl8169_get_regs_len, 2216 .get_link = ethtool_op_get_link, 2217 .get_coalesce = rtl_get_coalesce, 2218 .set_coalesce = rtl_set_coalesce, 2219 .get_regs = rtl8169_get_regs, 2220 .get_wol = rtl8169_get_wol, 2221 .set_wol = rtl8169_set_wol, 2222 .get_strings = rtl8169_get_strings, 2223 .get_sset_count = rtl8169_get_sset_count, 2224 .get_ethtool_stats = rtl8169_get_ethtool_stats, 2225 .get_ts_info = ethtool_op_get_ts_info, 2226 .nway_reset = phy_ethtool_nway_reset, 2227 .get_eee = rtl8169_get_eee, 2228 .set_eee = rtl8169_set_eee, 2229 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2230 .set_link_ksettings = phy_ethtool_set_link_ksettings, 2231 .get_ringparam = rtl8169_get_ringparam, 2232 .get_pause_stats = rtl8169_get_pause_stats, 2233 .get_pauseparam = rtl8169_get_pauseparam, 2234 .set_pauseparam = rtl8169_set_pauseparam, 2235 .get_eth_mac_stats = rtl8169_get_eth_mac_stats, 2236 .get_eth_ctrl_stats = rtl8169_get_eth_ctrl_stats, 2237 }; 2238 2239 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 2240 { 2241 /* 2242 * The driver currently handles the 8168Bf and the 8168Be identically 2243 * but they can be identified more specifically through the test below 2244 * if needed: 2245 * 2246 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 2247 * 2248 * Same thing for the 8101Eb and the 8101Ec: 2249 * 2250 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 2251 */ 2252 static const struct rtl_mac_info { 2253 u16 mask; 2254 u16 val; 2255 enum mac_version ver; 2256 } mac_info[] = { 2257 /* 8126A family. */ 2258 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_66 }, 2259 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_65 }, 2260 2261 /* 8125D family. */ 2262 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, 2263 2264 /* 8125B family. */ 2265 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, 2266 2267 /* 8125A family. */ 2268 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, 2269 /* It seems only XID 609 made it to the mass market. 2270 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2271 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2272 */ 2273 2274 /* RTL8117 */ 2275 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, 2276 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2277 2278 /* 8168EP family. */ 2279 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2280 /* It seems this chip version never made it to 2281 * the wild. Let's disable detection. 2282 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2283 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2284 */ 2285 2286 /* 8168H family. */ 2287 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2288 /* It seems this chip version never made it to 2289 * the wild. Let's disable detection. 2290 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2291 */ 2292 /* Realtek calls it RTL8168M, but it's handled like RTL8168H */ 2293 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, 2294 2295 /* 8168G family. */ 2296 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2297 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2298 /* It seems this chip version never made it to 2299 * the wild. Let's disable detection. 2300 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2301 */ 2302 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2303 2304 /* 8168F family. */ 2305 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2306 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2307 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2308 2309 /* 8168E family. */ 2310 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2311 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2312 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2313 2314 /* 8168D family. */ 2315 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2316 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2317 2318 /* 8168DP family. */ 2319 /* It seems this early RTL8168dp version never made it to 2320 * the wild. Support has been removed. 2321 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2322 */ 2323 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2324 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2325 2326 /* 8168C family. */ 2327 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2328 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2329 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2330 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2331 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2332 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2333 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2334 2335 /* 8168B family. */ 2336 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2337 /* This one is very old and rare, support has been removed. 2338 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2339 */ 2340 2341 /* 8101 family. */ 2342 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2343 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2344 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2345 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2346 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2347 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2348 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2349 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2350 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, 2351 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2352 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2353 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, 2354 2355 /* 8110 family. */ 2356 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2357 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2358 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2359 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2360 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2361 2362 /* Catch-all */ 2363 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2364 }; 2365 const struct rtl_mac_info *p = mac_info; 2366 enum mac_version ver; 2367 2368 while ((xid & p->mask) != p->val) 2369 p++; 2370 ver = p->ver; 2371 2372 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2373 if (ver == RTL_GIGA_MAC_VER_42) 2374 ver = RTL_GIGA_MAC_VER_43; 2375 else if (ver == RTL_GIGA_MAC_VER_46) 2376 ver = RTL_GIGA_MAC_VER_48; 2377 } 2378 2379 return ver; 2380 } 2381 2382 static void rtl_release_firmware(struct rtl8169_private *tp) 2383 { 2384 if (tp->rtl_fw) { 2385 rtl_fw_release_firmware(tp->rtl_fw); 2386 kfree(tp->rtl_fw); 2387 tp->rtl_fw = NULL; 2388 } 2389 } 2390 2391 void r8169_apply_firmware(struct rtl8169_private *tp) 2392 { 2393 int val; 2394 2395 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2396 if (tp->rtl_fw) { 2397 rtl_fw_write_firmware(tp, tp->rtl_fw); 2398 /* At least one firmware doesn't reset tp->ocp_base. */ 2399 tp->ocp_base = OCP_STD_PHY_BASE; 2400 2401 /* PHY soft reset may still be in progress */ 2402 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, 2403 !(val & BMCR_RESET), 2404 50000, 600000, true); 2405 } 2406 } 2407 2408 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2409 { 2410 /* Adjust EEE LED frequency */ 2411 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2412 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2413 2414 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2415 } 2416 2417 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) 2418 { 2419 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2420 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2421 } 2422 2423 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) 2424 { 2425 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2426 } 2427 2428 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) 2429 { 2430 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); 2431 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); 2432 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); 2433 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); 2434 } 2435 2436 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2437 { 2438 u16 data1, data2, ioffset; 2439 2440 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2441 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2442 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2443 2444 ioffset = (data2 >> 1) & 0x7ff8; 2445 ioffset |= data2 & 0x0007; 2446 if (data1 & BIT(7)) 2447 ioffset |= BIT(15); 2448 2449 return ioffset; 2450 } 2451 2452 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2453 { 2454 set_bit(flag, tp->wk.flags); 2455 if (!schedule_work(&tp->wk.work)) 2456 clear_bit(flag, tp->wk.flags); 2457 } 2458 2459 static void rtl8169_init_phy(struct rtl8169_private *tp) 2460 { 2461 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2462 2463 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2464 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2465 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2466 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2467 RTL_W8(tp, 0x82, 0x01); 2468 } 2469 2470 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2471 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2472 tp->pci_dev->subsystem_device == 0xe000) 2473 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2474 2475 /* We may have called phy_speed_down before */ 2476 phy_speed_up(tp->phydev); 2477 2478 genphy_soft_reset(tp->phydev); 2479 } 2480 2481 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) 2482 { 2483 rtl_unlock_config_regs(tp); 2484 2485 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); 2486 rtl_pci_commit(tp); 2487 2488 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); 2489 rtl_pci_commit(tp); 2490 2491 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2492 rtl_rar_exgmac_set(tp, addr); 2493 2494 rtl_lock_config_regs(tp); 2495 } 2496 2497 static int rtl_set_mac_address(struct net_device *dev, void *p) 2498 { 2499 struct rtl8169_private *tp = netdev_priv(dev); 2500 int ret; 2501 2502 ret = eth_mac_addr(dev, p); 2503 if (ret) 2504 return ret; 2505 2506 rtl_rar_set(tp, dev->dev_addr); 2507 2508 return 0; 2509 } 2510 2511 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2512 { 2513 switch (tp->mac_version) { 2514 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2515 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2516 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2517 break; 2518 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2519 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2520 case RTL_GIGA_MAC_VER_38: 2521 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2522 break; 2523 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2524 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2525 break; 2526 case RTL_GIGA_MAC_VER_61: 2527 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2528 break; 2529 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2530 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | 2531 RX_PAUSE_SLOT_ON); 2532 break; 2533 default: 2534 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2535 break; 2536 } 2537 } 2538 2539 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2540 { 2541 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2542 } 2543 2544 static void rtl_jumbo_config(struct rtl8169_private *tp) 2545 { 2546 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2547 int readrq = 4096; 2548 2549 if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 && 2550 tp->mac_version <= RTL_GIGA_MAC_VER_26) 2551 readrq = 512; 2552 2553 rtl_unlock_config_regs(tp); 2554 switch (tp->mac_version) { 2555 case RTL_GIGA_MAC_VER_17: 2556 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2557 break; 2558 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2559 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2560 r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo); 2561 break; 2562 case RTL_GIGA_MAC_VER_28: 2563 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2564 break; 2565 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2566 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); 2567 r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo); 2568 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); 2569 break; 2570 default: 2571 break; 2572 } 2573 rtl_lock_config_regs(tp); 2574 2575 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2576 pcie_set_readrq(tp->pci_dev, readrq); 2577 2578 /* Chip doesn't support pause in jumbo mode */ 2579 if (jumbo) { 2580 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2581 tp->phydev->advertising); 2582 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2583 tp->phydev->advertising); 2584 phy_start_aneg(tp->phydev); 2585 } 2586 } 2587 2588 DECLARE_RTL_COND(rtl_chipcmd_cond) 2589 { 2590 return RTL_R8(tp, ChipCmd) & CmdReset; 2591 } 2592 2593 static void rtl_hw_reset(struct rtl8169_private *tp) 2594 { 2595 RTL_W8(tp, ChipCmd, CmdReset); 2596 2597 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2598 } 2599 2600 static void rtl_request_firmware(struct rtl8169_private *tp) 2601 { 2602 struct rtl_fw *rtl_fw; 2603 2604 /* firmware loaded already or no firmware available */ 2605 if (tp->rtl_fw || !tp->fw_name) 2606 return; 2607 2608 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2609 if (!rtl_fw) 2610 return; 2611 2612 rtl_fw->phy_write = rtl_writephy; 2613 rtl_fw->phy_read = rtl_readphy; 2614 rtl_fw->mac_mcu_write = mac_mcu_write; 2615 rtl_fw->mac_mcu_read = mac_mcu_read; 2616 rtl_fw->fw_name = tp->fw_name; 2617 rtl_fw->dev = tp_to_dev(tp); 2618 2619 if (rtl_fw_request_firmware(rtl_fw)) 2620 kfree(rtl_fw); 2621 else 2622 tp->rtl_fw = rtl_fw; 2623 } 2624 2625 static void rtl_rx_close(struct rtl8169_private *tp) 2626 { 2627 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2628 } 2629 2630 DECLARE_RTL_COND(rtl_npq_cond) 2631 { 2632 return RTL_R8(tp, TxPoll) & NPQ; 2633 } 2634 2635 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2636 { 2637 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2638 } 2639 2640 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2641 { 2642 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2643 } 2644 2645 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2) 2646 { 2647 /* IntrMitigate has new functionality on RTL8125 */ 2648 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; 2649 } 2650 2651 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2652 { 2653 switch (tp->mac_version) { 2654 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53: 2655 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2656 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2657 break; 2658 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61: 2659 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2660 break; 2661 case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_66: 2662 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 2663 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2664 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); 2665 break; 2666 default: 2667 break; 2668 } 2669 } 2670 2671 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) 2672 { 2673 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2674 } 2675 2676 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2677 { 2678 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2679 fsleep(2000); 2680 rtl_wait_txrx_fifo_empty(tp); 2681 } 2682 2683 static void rtl_wol_enable_rx(struct rtl8169_private *tp) 2684 { 2685 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) 2686 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2687 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2688 2689 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) 2690 rtl_disable_rxdvgate(tp); 2691 } 2692 2693 static void rtl_prepare_power_down(struct rtl8169_private *tp) 2694 { 2695 if (tp->dash_enabled) 2696 return; 2697 2698 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2699 tp->mac_version == RTL_GIGA_MAC_VER_33) 2700 rtl_ephy_write(tp, 0x19, 0xff64); 2701 2702 if (device_may_wakeup(tp_to_dev(tp))) { 2703 phy_speed_down(tp->phydev, false); 2704 rtl_wol_enable_rx(tp); 2705 } 2706 } 2707 2708 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2709 { 2710 u32 val = TX_DMA_BURST << TxDMAShift | 2711 InterFrameGap << TxInterFrameGapShift; 2712 2713 if (rtl_is_8168evl_up(tp)) 2714 val |= TXCFG_AUTO_FIFO; 2715 2716 RTL_W32(tp, TxConfig, val); 2717 } 2718 2719 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2720 { 2721 /* Low hurts. Let's disable the filtering. */ 2722 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2723 } 2724 2725 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2726 { 2727 /* 2728 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2729 * register to be written before TxDescAddrLow to work. 2730 * Switching from MMIO to I/O access fixes the issue as well. 2731 */ 2732 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2733 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2734 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2735 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2736 } 2737 2738 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2739 { 2740 u32 val; 2741 2742 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2743 val = 0x000fff00; 2744 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2745 val = 0x00ffff00; 2746 else 2747 return; 2748 2749 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2750 val |= 0xff; 2751 2752 RTL_W32(tp, 0x7c, val); 2753 } 2754 2755 static void rtl_set_rx_mode(struct net_device *dev) 2756 { 2757 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2758 /* Multicast hash filter */ 2759 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2760 struct rtl8169_private *tp = netdev_priv(dev); 2761 u32 tmp; 2762 2763 if (dev->flags & IFF_PROMISC) { 2764 rx_mode |= AcceptAllPhys; 2765 } else if (!(dev->flags & IFF_MULTICAST)) { 2766 rx_mode &= ~AcceptMulticast; 2767 } else if (dev->flags & IFF_ALLMULTI || 2768 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2769 /* accept all multicasts */ 2770 } else if (netdev_mc_empty(dev)) { 2771 rx_mode &= ~AcceptMulticast; 2772 } else { 2773 struct netdev_hw_addr *ha; 2774 2775 mc_filter[1] = mc_filter[0] = 0; 2776 netdev_for_each_mc_addr(ha, dev) { 2777 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2778 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2779 } 2780 2781 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2782 tmp = mc_filter[0]; 2783 mc_filter[0] = swab32(mc_filter[1]); 2784 mc_filter[1] = swab32(tmp); 2785 } 2786 } 2787 2788 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2789 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2790 2791 tmp = RTL_R32(tp, RxConfig); 2792 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2793 } 2794 2795 DECLARE_RTL_COND(rtl_csiar_cond) 2796 { 2797 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2798 } 2799 2800 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2801 { 2802 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2803 2804 RTL_W32(tp, CSIDR, value); 2805 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2806 CSIAR_BYTE_ENABLE | func << 16); 2807 2808 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2809 } 2810 2811 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2812 { 2813 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2814 2815 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2816 CSIAR_BYTE_ENABLE); 2817 2818 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2819 RTL_R32(tp, CSIDR) : ~0; 2820 } 2821 2822 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) 2823 { 2824 struct pci_dev *pdev = tp->pci_dev; 2825 u32 csi; 2826 2827 /* According to Realtek the value at config space address 0x070f 2828 * controls the L0s/L1 entrance latency. We try standard ECAM access 2829 * first and if it fails fall back to CSI. 2830 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) 2831 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us 2832 */ 2833 if (pdev->cfg_size > 0x070f && 2834 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2835 return; 2836 2837 netdev_notice_once(tp->dev, 2838 "No native access to PCI extended config space, falling back to CSI\n"); 2839 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2840 rtl_csi_write(tp, 0x070c, csi | val << 24); 2841 } 2842 2843 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2844 { 2845 /* L0 7us, L1 16us */ 2846 rtl_set_aspm_entry_latency(tp, 0x27); 2847 } 2848 2849 struct ephy_info { 2850 unsigned int offset; 2851 u16 mask; 2852 u16 bits; 2853 }; 2854 2855 static void __rtl_ephy_init(struct rtl8169_private *tp, 2856 const struct ephy_info *e, int len) 2857 { 2858 u16 w; 2859 2860 while (len-- > 0) { 2861 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2862 rtl_ephy_write(tp, e->offset, w); 2863 e++; 2864 } 2865 } 2866 2867 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2868 2869 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2870 { 2871 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2872 PCI_EXP_LNKCTL_CLKREQ_EN); 2873 } 2874 2875 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2876 { 2877 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2878 PCI_EXP_LNKCTL_CLKREQ_EN); 2879 } 2880 2881 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2882 { 2883 /* work around an issue when PCI reset occurs during L2/L3 state */ 2884 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2885 } 2886 2887 static void rtl_enable_exit_l1(struct rtl8169_private *tp) 2888 { 2889 /* Bits control which events trigger ASPM L1 exit: 2890 * Bit 12: rxdv 2891 * Bit 11: ltr_msg 2892 * Bit 10: txdma_poll 2893 * Bit 9: xadm 2894 * Bit 8: pktavi 2895 * Bit 7: txpla 2896 */ 2897 switch (tp->mac_version) { 2898 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2899 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 2900 break; 2901 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38: 2902 rtl_eri_set_bits(tp, 0xd4, 0x0c00); 2903 break; 2904 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2905 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); 2906 break; 2907 default: 2908 break; 2909 } 2910 } 2911 2912 static void rtl_disable_exit_l1(struct rtl8169_private *tp) 2913 { 2914 switch (tp->mac_version) { 2915 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 2916 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); 2917 break; 2918 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 2919 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); 2920 break; 2921 default: 2922 break; 2923 } 2924 } 2925 2926 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2927 { 2928 u8 val8; 2929 2930 if (tp->mac_version < RTL_GIGA_MAC_VER_32) 2931 return; 2932 2933 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2934 if (enable && tp->aspm_manageable) { 2935 /* On these chip versions ASPM can even harm 2936 * bus communication of other PCI devices. 2937 */ 2938 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || 2939 tp->mac_version == RTL_GIGA_MAC_VER_43) 2940 return; 2941 2942 rtl_mod_config5(tp, 0, ASPM_en); 2943 switch (tp->mac_version) { 2944 case RTL_GIGA_MAC_VER_65: 2945 case RTL_GIGA_MAC_VER_66: 2946 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; 2947 RTL_W8(tp, INT_CFG0_8125, val8); 2948 break; 2949 default: 2950 rtl_mod_config2(tp, 0, ClkReqEn); 2951 break; 2952 } 2953 2954 switch (tp->mac_version) { 2955 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2956 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2957 /* reset ephy tx/rx disable timer */ 2958 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); 2959 /* chip can trigger L1.2 */ 2960 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); 2961 break; 2962 default: 2963 break; 2964 } 2965 } else { 2966 switch (tp->mac_version) { 2967 case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: 2968 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 2969 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); 2970 break; 2971 default: 2972 break; 2973 } 2974 2975 switch (tp->mac_version) { 2976 case RTL_GIGA_MAC_VER_65: 2977 case RTL_GIGA_MAC_VER_66: 2978 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; 2979 RTL_W8(tp, INT_CFG0_8125, val8); 2980 break; 2981 default: 2982 rtl_mod_config2(tp, ClkReqEn, 0); 2983 break; 2984 } 2985 rtl_mod_config5(tp, ASPM_en, 0); 2986 } 2987 } 2988 2989 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2990 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2991 { 2992 /* Usage of dynamic vs. static FIFO is controlled by bit 2993 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2994 */ 2995 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2996 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2997 } 2998 2999 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 3000 u8 low, u8 high) 3001 { 3002 /* FIFO thresholds for pause flow control */ 3003 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 3004 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 3005 } 3006 3007 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 3008 { 3009 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3010 } 3011 3012 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 3013 { 3014 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 3015 3016 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3017 3018 rtl_disable_clock_request(tp); 3019 } 3020 3021 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 3022 { 3023 static const struct ephy_info e_info_8168cp[] = { 3024 { 0x01, 0, 0x0001 }, 3025 { 0x02, 0x0800, 0x1000 }, 3026 { 0x03, 0, 0x0042 }, 3027 { 0x06, 0x0080, 0x0000 }, 3028 { 0x07, 0, 0x2000 } 3029 }; 3030 3031 rtl_set_def_aspm_entry_latency(tp); 3032 3033 rtl_ephy_init(tp, e_info_8168cp); 3034 3035 __rtl_hw_start_8168cp(tp); 3036 } 3037 3038 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 3039 { 3040 rtl_set_def_aspm_entry_latency(tp); 3041 3042 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3043 } 3044 3045 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 3046 { 3047 rtl_set_def_aspm_entry_latency(tp); 3048 3049 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3050 3051 /* Magic. */ 3052 RTL_W8(tp, DBG_REG, 0x20); 3053 } 3054 3055 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 3056 { 3057 static const struct ephy_info e_info_8168c_1[] = { 3058 { 0x02, 0x0800, 0x1000 }, 3059 { 0x03, 0, 0x0002 }, 3060 { 0x06, 0x0080, 0x0000 } 3061 }; 3062 3063 rtl_set_def_aspm_entry_latency(tp); 3064 3065 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 3066 3067 rtl_ephy_init(tp, e_info_8168c_1); 3068 3069 __rtl_hw_start_8168cp(tp); 3070 } 3071 3072 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 3073 { 3074 static const struct ephy_info e_info_8168c_2[] = { 3075 { 0x01, 0, 0x0001 }, 3076 { 0x03, 0x0400, 0x0020 } 3077 }; 3078 3079 rtl_set_def_aspm_entry_latency(tp); 3080 3081 rtl_ephy_init(tp, e_info_8168c_2); 3082 3083 __rtl_hw_start_8168cp(tp); 3084 } 3085 3086 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 3087 { 3088 rtl_set_def_aspm_entry_latency(tp); 3089 3090 __rtl_hw_start_8168cp(tp); 3091 } 3092 3093 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 3094 { 3095 rtl_set_def_aspm_entry_latency(tp); 3096 3097 rtl_disable_clock_request(tp); 3098 } 3099 3100 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 3101 { 3102 static const struct ephy_info e_info_8168d_4[] = { 3103 { 0x0b, 0x0000, 0x0048 }, 3104 { 0x19, 0x0020, 0x0050 }, 3105 { 0x0c, 0x0100, 0x0020 }, 3106 { 0x10, 0x0004, 0x0000 }, 3107 }; 3108 3109 rtl_set_def_aspm_entry_latency(tp); 3110 3111 rtl_ephy_init(tp, e_info_8168d_4); 3112 3113 rtl_enable_clock_request(tp); 3114 } 3115 3116 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 3117 { 3118 static const struct ephy_info e_info_8168e_1[] = { 3119 { 0x00, 0x0200, 0x0100 }, 3120 { 0x00, 0x0000, 0x0004 }, 3121 { 0x06, 0x0002, 0x0001 }, 3122 { 0x06, 0x0000, 0x0030 }, 3123 { 0x07, 0x0000, 0x2000 }, 3124 { 0x00, 0x0000, 0x0020 }, 3125 { 0x03, 0x5800, 0x2000 }, 3126 { 0x03, 0x0000, 0x0001 }, 3127 { 0x01, 0x0800, 0x1000 }, 3128 { 0x07, 0x0000, 0x4000 }, 3129 { 0x1e, 0x0000, 0x2000 }, 3130 { 0x19, 0xffff, 0xfe6c }, 3131 { 0x0a, 0x0000, 0x0040 } 3132 }; 3133 3134 rtl_set_def_aspm_entry_latency(tp); 3135 3136 rtl_ephy_init(tp, e_info_8168e_1); 3137 3138 rtl_disable_clock_request(tp); 3139 3140 /* Reset tx FIFO pointer */ 3141 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 3142 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 3143 3144 rtl_mod_config5(tp, Spi_en, 0); 3145 } 3146 3147 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 3148 { 3149 static const struct ephy_info e_info_8168e_2[] = { 3150 { 0x09, 0x0000, 0x0080 }, 3151 { 0x19, 0x0000, 0x0224 }, 3152 { 0x00, 0x0000, 0x0004 }, 3153 { 0x0c, 0x3df0, 0x0200 }, 3154 }; 3155 3156 rtl_set_def_aspm_entry_latency(tp); 3157 3158 rtl_ephy_init(tp, e_info_8168e_2); 3159 3160 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3161 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3162 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3163 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 3164 rtl_reset_packet_filter(tp); 3165 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3166 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3167 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 3168 3169 rtl_disable_clock_request(tp); 3170 3171 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3172 3173 rtl8168_config_eee_mac(tp); 3174 3175 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3176 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3177 rtl_mod_config5(tp, Spi_en, 0); 3178 } 3179 3180 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 3181 { 3182 rtl_set_def_aspm_entry_latency(tp); 3183 3184 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3185 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 3186 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 3187 rtl_reset_packet_filter(tp); 3188 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 3189 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 3190 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 3191 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 3192 3193 rtl_disable_clock_request(tp); 3194 3195 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3196 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3197 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 3198 rtl_mod_config5(tp, Spi_en, 0); 3199 3200 rtl8168_config_eee_mac(tp); 3201 } 3202 3203 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 3204 { 3205 static const struct ephy_info e_info_8168f_1[] = { 3206 { 0x06, 0x00c0, 0x0020 }, 3207 { 0x08, 0x0001, 0x0002 }, 3208 { 0x09, 0x0000, 0x0080 }, 3209 { 0x19, 0x0000, 0x0224 }, 3210 { 0x00, 0x0000, 0x0008 }, 3211 { 0x0c, 0x3df0, 0x0200 }, 3212 }; 3213 3214 rtl_hw_start_8168f(tp); 3215 3216 rtl_ephy_init(tp, e_info_8168f_1); 3217 } 3218 3219 static void rtl_hw_start_8411(struct rtl8169_private *tp) 3220 { 3221 static const struct ephy_info e_info_8168f_1[] = { 3222 { 0x06, 0x00c0, 0x0020 }, 3223 { 0x0f, 0xffff, 0x5200 }, 3224 { 0x19, 0x0000, 0x0224 }, 3225 { 0x00, 0x0000, 0x0008 }, 3226 { 0x0c, 0x3df0, 0x0200 }, 3227 }; 3228 3229 rtl_hw_start_8168f(tp); 3230 rtl_pcie_state_l2l3_disable(tp); 3231 3232 rtl_ephy_init(tp, e_info_8168f_1); 3233 } 3234 3235 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 3236 { 3237 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3238 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3239 3240 rtl_set_def_aspm_entry_latency(tp); 3241 3242 rtl_reset_packet_filter(tp); 3243 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 3244 3245 rtl_disable_rxdvgate(tp); 3246 3247 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3248 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3249 3250 rtl8168_config_eee_mac(tp); 3251 3252 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3253 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3254 3255 rtl_pcie_state_l2l3_disable(tp); 3256 } 3257 3258 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3259 { 3260 static const struct ephy_info e_info_8168g_1[] = { 3261 { 0x00, 0x0008, 0x0000 }, 3262 { 0x0c, 0x3ff0, 0x0820 }, 3263 { 0x1e, 0x0000, 0x0001 }, 3264 { 0x19, 0x8000, 0x0000 } 3265 }; 3266 3267 rtl_hw_start_8168g(tp); 3268 rtl_ephy_init(tp, e_info_8168g_1); 3269 } 3270 3271 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3272 { 3273 static const struct ephy_info e_info_8168g_2[] = { 3274 { 0x00, 0x0008, 0x0000 }, 3275 { 0x0c, 0x3ff0, 0x0820 }, 3276 { 0x19, 0xffff, 0x7c00 }, 3277 { 0x1e, 0xffff, 0x20eb }, 3278 { 0x0d, 0xffff, 0x1666 }, 3279 { 0x00, 0xffff, 0x10a3 }, 3280 { 0x06, 0xffff, 0xf050 }, 3281 { 0x04, 0x0000, 0x0010 }, 3282 { 0x1d, 0x4000, 0x0000 }, 3283 }; 3284 3285 rtl_hw_start_8168g(tp); 3286 rtl_ephy_init(tp, e_info_8168g_2); 3287 } 3288 3289 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) 3290 { 3291 static const u16 fix_data[] = { 3292 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, 3293 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, 3294 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, 3295 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, 3296 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, 3297 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, 3298 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, 3299 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, 3300 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, 3301 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, 3302 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, 3303 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, 3304 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, 3305 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 3306 }; 3307 unsigned long flags; 3308 int i; 3309 3310 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); 3311 for (i = 0; i < ARRAY_SIZE(fix_data); i++) 3312 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); 3313 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); 3314 } 3315 3316 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3317 { 3318 static const struct ephy_info e_info_8411_2[] = { 3319 { 0x00, 0x0008, 0x0000 }, 3320 { 0x0c, 0x37d0, 0x0820 }, 3321 { 0x1e, 0x0000, 0x0001 }, 3322 { 0x19, 0x8021, 0x0000 }, 3323 { 0x1e, 0x0000, 0x2000 }, 3324 { 0x0d, 0x0100, 0x0200 }, 3325 { 0x00, 0x0000, 0x0080 }, 3326 { 0x06, 0x0000, 0x0010 }, 3327 { 0x04, 0x0000, 0x0010 }, 3328 { 0x1d, 0x0000, 0x4000 }, 3329 }; 3330 3331 rtl_hw_start_8168g(tp); 3332 3333 rtl_ephy_init(tp, e_info_8411_2); 3334 3335 /* The following Realtek-provided magic fixes an issue with the RX unit 3336 * getting confused after the PHY having been powered-down. 3337 */ 3338 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3339 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3340 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3341 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3342 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3343 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3344 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3345 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3346 mdelay(3); 3347 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3348 3349 rtl8411b_fix_phy_down(tp); 3350 3351 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3352 3353 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3354 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3355 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3356 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3357 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3358 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3359 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3360 } 3361 3362 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3363 { 3364 static const struct ephy_info e_info_8168h_1[] = { 3365 { 0x1e, 0x0800, 0x0001 }, 3366 { 0x1d, 0x0000, 0x0800 }, 3367 { 0x05, 0xffff, 0x2089 }, 3368 { 0x06, 0xffff, 0x5881 }, 3369 { 0x04, 0xffff, 0x854a }, 3370 { 0x01, 0xffff, 0x068b } 3371 }; 3372 int rg_saw_cnt; 3373 3374 rtl_ephy_init(tp, e_info_8168h_1); 3375 3376 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3377 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3378 3379 rtl_set_def_aspm_entry_latency(tp); 3380 3381 rtl_reset_packet_filter(tp); 3382 3383 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3384 3385 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3386 3387 rtl_disable_rxdvgate(tp); 3388 3389 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3390 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3391 3392 rtl8168_config_eee_mac(tp); 3393 3394 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3395 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3396 3397 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3398 3399 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3400 3401 rtl_pcie_state_l2l3_disable(tp); 3402 3403 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3404 if (rg_saw_cnt > 0) { 3405 u16 sw_cnt_1ms_ini; 3406 3407 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3408 sw_cnt_1ms_ini &= 0x0fff; 3409 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3410 } 3411 3412 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3413 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3414 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3415 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3416 3417 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3418 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3419 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3420 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3421 } 3422 3423 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3424 { 3425 rtl8168ep_stop_cmac(tp); 3426 3427 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3428 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3429 3430 rtl_set_def_aspm_entry_latency(tp); 3431 3432 rtl_reset_packet_filter(tp); 3433 3434 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3435 3436 rtl_disable_rxdvgate(tp); 3437 3438 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3439 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3440 3441 rtl8168_config_eee_mac(tp); 3442 3443 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3444 3445 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3446 3447 rtl_pcie_state_l2l3_disable(tp); 3448 } 3449 3450 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3451 { 3452 static const struct ephy_info e_info_8168ep_3[] = { 3453 { 0x00, 0x0000, 0x0080 }, 3454 { 0x0d, 0x0100, 0x0200 }, 3455 { 0x19, 0x8021, 0x0000 }, 3456 { 0x1e, 0x0000, 0x2000 }, 3457 }; 3458 3459 rtl_ephy_init(tp, e_info_8168ep_3); 3460 3461 rtl_hw_start_8168ep(tp); 3462 3463 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3464 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3465 3466 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3467 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3468 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3469 } 3470 3471 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3472 { 3473 static const struct ephy_info e_info_8117[] = { 3474 { 0x19, 0x0040, 0x1100 }, 3475 { 0x59, 0x0040, 0x1100 }, 3476 }; 3477 int rg_saw_cnt; 3478 3479 rtl8168ep_stop_cmac(tp); 3480 rtl_ephy_init(tp, e_info_8117); 3481 3482 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3483 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3484 3485 rtl_set_def_aspm_entry_latency(tp); 3486 3487 rtl_reset_packet_filter(tp); 3488 3489 rtl_eri_set_bits(tp, 0xd4, 0x0010); 3490 3491 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3492 3493 rtl_disable_rxdvgate(tp); 3494 3495 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3496 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3497 3498 rtl8168_config_eee_mac(tp); 3499 3500 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3501 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3502 3503 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3504 3505 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3506 3507 rtl_pcie_state_l2l3_disable(tp); 3508 3509 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3510 if (rg_saw_cnt > 0) { 3511 u16 sw_cnt_1ms_ini; 3512 3513 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3514 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3515 } 3516 3517 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3518 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3519 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3520 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3521 3522 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3523 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3524 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3525 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3526 3527 /* firmware is for MAC only */ 3528 r8169_apply_firmware(tp); 3529 } 3530 3531 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3532 { 3533 static const struct ephy_info e_info_8102e_1[] = { 3534 { 0x01, 0, 0x6e65 }, 3535 { 0x02, 0, 0x091f }, 3536 { 0x03, 0, 0xc2f9 }, 3537 { 0x06, 0, 0xafb5 }, 3538 { 0x07, 0, 0x0e00 }, 3539 { 0x19, 0, 0xec80 }, 3540 { 0x01, 0, 0x2e65 }, 3541 { 0x01, 0, 0x6e65 } 3542 }; 3543 u8 cfg1; 3544 3545 rtl_set_def_aspm_entry_latency(tp); 3546 3547 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3548 3549 RTL_W8(tp, Config1, 3550 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3551 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3552 3553 cfg1 = RTL_R8(tp, Config1); 3554 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3555 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3556 3557 rtl_ephy_init(tp, e_info_8102e_1); 3558 } 3559 3560 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3561 { 3562 rtl_set_def_aspm_entry_latency(tp); 3563 3564 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3565 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3566 } 3567 3568 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3569 { 3570 rtl_hw_start_8102e_2(tp); 3571 3572 rtl_ephy_write(tp, 0x03, 0xc2f9); 3573 } 3574 3575 static void rtl_hw_start_8401(struct rtl8169_private *tp) 3576 { 3577 static const struct ephy_info e_info_8401[] = { 3578 { 0x01, 0xffff, 0x6fe5 }, 3579 { 0x03, 0xffff, 0x0599 }, 3580 { 0x06, 0xffff, 0xaf25 }, 3581 { 0x07, 0xffff, 0x8e68 }, 3582 }; 3583 3584 rtl_ephy_init(tp, e_info_8401); 3585 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3586 } 3587 3588 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3589 { 3590 static const struct ephy_info e_info_8105e_1[] = { 3591 { 0x07, 0, 0x4000 }, 3592 { 0x19, 0, 0x0200 }, 3593 { 0x19, 0, 0x0020 }, 3594 { 0x1e, 0, 0x2000 }, 3595 { 0x03, 0, 0x0001 }, 3596 { 0x19, 0, 0x0100 }, 3597 { 0x19, 0, 0x0004 }, 3598 { 0x0a, 0, 0x0020 } 3599 }; 3600 3601 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3602 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3603 3604 /* Disable Early Tally Counter */ 3605 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3606 3607 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3608 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3609 3610 rtl_ephy_init(tp, e_info_8105e_1); 3611 3612 rtl_pcie_state_l2l3_disable(tp); 3613 } 3614 3615 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3616 { 3617 rtl_hw_start_8105e_1(tp); 3618 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3619 } 3620 3621 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3622 { 3623 static const struct ephy_info e_info_8402[] = { 3624 { 0x19, 0xffff, 0xff64 }, 3625 { 0x1e, 0, 0x4000 } 3626 }; 3627 3628 rtl_set_def_aspm_entry_latency(tp); 3629 3630 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3631 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3632 3633 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3634 3635 rtl_ephy_init(tp, e_info_8402); 3636 3637 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3638 rtl_reset_packet_filter(tp); 3639 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3640 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3641 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3642 3643 /* disable EEE */ 3644 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3645 3646 rtl_pcie_state_l2l3_disable(tp); 3647 } 3648 3649 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3650 { 3651 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3652 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3653 3654 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3655 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3656 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3657 3658 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */ 3659 rtl_set_aspm_entry_latency(tp, 0x2f); 3660 3661 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3662 3663 /* disable EEE */ 3664 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3665 3666 rtl_pcie_state_l2l3_disable(tp); 3667 } 3668 3669 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3670 { 3671 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3672 } 3673 3674 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3675 { 3676 rtl_pcie_state_l2l3_disable(tp); 3677 3678 RTL_W16(tp, 0x382, 0x221b); 3679 RTL_W32(tp, RSS_CTRL_8125, 0); 3680 RTL_W16(tp, Q_NUM_CTRL_8125, 0); 3681 3682 /* disable UPS */ 3683 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3684 3685 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3686 3687 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3688 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3689 3690 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3691 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3692 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3693 3694 /* disable new tx descriptor format */ 3695 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3696 3697 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3698 tp->mac_version == RTL_GIGA_MAC_VER_66) 3699 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); 3700 3701 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3702 tp->mac_version == RTL_GIGA_MAC_VER_66) 3703 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3704 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3705 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); 3706 else 3707 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); 3708 3709 if (tp->mac_version == RTL_GIGA_MAC_VER_63) 3710 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); 3711 else 3712 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3713 3714 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3715 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3716 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3717 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3718 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3719 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); 3720 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || 3721 tp->mac_version == RTL_GIGA_MAC_VER_66) 3722 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); 3723 else 3724 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3725 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3726 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); 3727 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3728 3729 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3730 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3731 udelay(1); 3732 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3733 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3734 3735 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3736 3737 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3738 3739 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 3740 rtl8125a_config_eee_mac(tp); 3741 else 3742 rtl8125b_config_eee_mac(tp); 3743 3744 rtl_disable_rxdvgate(tp); 3745 } 3746 3747 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) 3748 { 3749 static const struct ephy_info e_info_8125a_2[] = { 3750 { 0x04, 0xffff, 0xd000 }, 3751 { 0x0a, 0xffff, 0x8653 }, 3752 { 0x23, 0xffff, 0xab66 }, 3753 { 0x20, 0xffff, 0x9455 }, 3754 { 0x21, 0xffff, 0x99ff }, 3755 { 0x29, 0xffff, 0xfe04 }, 3756 3757 { 0x44, 0xffff, 0xd000 }, 3758 { 0x4a, 0xffff, 0x8653 }, 3759 { 0x63, 0xffff, 0xab66 }, 3760 { 0x60, 0xffff, 0x9455 }, 3761 { 0x61, 0xffff, 0x99ff }, 3762 { 0x69, 0xffff, 0xfe04 }, 3763 }; 3764 3765 rtl_set_def_aspm_entry_latency(tp); 3766 rtl_ephy_init(tp, e_info_8125a_2); 3767 rtl_hw_start_8125_common(tp); 3768 } 3769 3770 static void rtl_hw_start_8125b(struct rtl8169_private *tp) 3771 { 3772 static const struct ephy_info e_info_8125b[] = { 3773 { 0x0b, 0xffff, 0xa908 }, 3774 { 0x1e, 0xffff, 0x20eb }, 3775 { 0x4b, 0xffff, 0xa908 }, 3776 { 0x5e, 0xffff, 0x20eb }, 3777 { 0x22, 0x0030, 0x0020 }, 3778 { 0x62, 0x0030, 0x0020 }, 3779 }; 3780 3781 rtl_set_def_aspm_entry_latency(tp); 3782 rtl_ephy_init(tp, e_info_8125b); 3783 rtl_hw_start_8125_common(tp); 3784 } 3785 3786 static void rtl_hw_start_8125d(struct rtl8169_private *tp) 3787 { 3788 rtl_set_def_aspm_entry_latency(tp); 3789 rtl_hw_start_8125_common(tp); 3790 } 3791 3792 static void rtl_hw_start_8126a(struct rtl8169_private *tp) 3793 { 3794 rtl_set_def_aspm_entry_latency(tp); 3795 rtl_hw_start_8125_common(tp); 3796 } 3797 3798 static void rtl_hw_config(struct rtl8169_private *tp) 3799 { 3800 static const rtl_generic_fct hw_configs[] = { 3801 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3802 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3803 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3804 [RTL_GIGA_MAC_VER_10] = NULL, 3805 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401, 3806 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3807 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3808 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3809 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3810 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2, 3811 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3812 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3813 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3814 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3815 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3816 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3817 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3818 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3819 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3820 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3821 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3822 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3823 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3824 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3825 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3826 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3827 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3828 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3829 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3830 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3831 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3832 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3833 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3834 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3835 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3836 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117, 3837 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2, 3838 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b, 3839 [RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d, 3840 [RTL_GIGA_MAC_VER_65] = rtl_hw_start_8126a, 3841 [RTL_GIGA_MAC_VER_66] = rtl_hw_start_8126a, 3842 }; 3843 3844 if (hw_configs[tp->mac_version]) 3845 hw_configs[tp->mac_version](tp); 3846 } 3847 3848 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3849 { 3850 int i; 3851 3852 RTL_W8(tp, INT_CFG0_8125, 0x00); 3853 3854 /* disable interrupt coalescing */ 3855 switch (tp->mac_version) { 3856 case RTL_GIGA_MAC_VER_61: 3857 case RTL_GIGA_MAC_VER_64: 3858 for (i = 0xa00; i < 0xb00; i += 4) 3859 RTL_W32(tp, i, 0); 3860 break; 3861 case RTL_GIGA_MAC_VER_63: 3862 case RTL_GIGA_MAC_VER_65: 3863 case RTL_GIGA_MAC_VER_66: 3864 for (i = 0xa00; i < 0xa80; i += 4) 3865 RTL_W32(tp, i, 0); 3866 RTL_W16(tp, INT_CFG1_8125, 0x0000); 3867 break; 3868 default: 3869 break; 3870 } 3871 3872 /* enable extended tally counter */ 3873 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); 3874 3875 rtl_hw_config(tp); 3876 } 3877 3878 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3879 { 3880 if (rtl_is_8168evl_up(tp)) 3881 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3882 else 3883 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3884 3885 rtl_hw_config(tp); 3886 3887 /* disable interrupt coalescing */ 3888 RTL_W16(tp, IntrMitigate, 0x0000); 3889 } 3890 3891 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3892 { 3893 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3894 3895 tp->cp_cmd |= PCIMulRW; 3896 3897 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3898 tp->mac_version == RTL_GIGA_MAC_VER_03) 3899 tp->cp_cmd |= EnAnaPLL; 3900 3901 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3902 3903 rtl8169_set_magic_reg(tp); 3904 3905 /* disable interrupt coalescing */ 3906 RTL_W16(tp, IntrMitigate, 0x0000); 3907 } 3908 3909 static void rtl_hw_start(struct rtl8169_private *tp) 3910 { 3911 rtl_unlock_config_regs(tp); 3912 /* disable aspm and clock request before ephy access */ 3913 rtl_hw_aspm_clkreq_enable(tp, false); 3914 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3915 3916 rtl_set_eee_txidle_timer(tp); 3917 3918 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3919 rtl_hw_start_8169(tp); 3920 else if (rtl_is_8125(tp)) 3921 rtl_hw_start_8125(tp); 3922 else 3923 rtl_hw_start_8168(tp); 3924 3925 rtl_enable_exit_l1(tp); 3926 rtl_hw_aspm_clkreq_enable(tp, true); 3927 rtl_set_rx_max_size(tp); 3928 rtl_set_rx_tx_desc_registers(tp); 3929 rtl_lock_config_regs(tp); 3930 3931 rtl_jumbo_config(tp); 3932 3933 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3934 rtl_pci_commit(tp); 3935 3936 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3937 rtl_init_rxcfg(tp); 3938 rtl_set_tx_config_registers(tp); 3939 rtl_set_rx_config_features(tp, tp->dev->features); 3940 rtl_set_rx_mode(tp->dev); 3941 rtl_irq_enable(tp); 3942 } 3943 3944 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3945 { 3946 struct rtl8169_private *tp = netdev_priv(dev); 3947 3948 WRITE_ONCE(dev->mtu, new_mtu); 3949 netdev_update_features(dev); 3950 rtl_jumbo_config(tp); 3951 rtl_set_eee_txidle_timer(tp); 3952 3953 return 0; 3954 } 3955 3956 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3957 { 3958 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3959 3960 desc->opts2 = 0; 3961 /* Force memory writes to complete before releasing descriptor */ 3962 dma_wmb(); 3963 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3964 } 3965 3966 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3967 struct RxDesc *desc) 3968 { 3969 struct device *d = tp_to_dev(tp); 3970 int node = dev_to_node(d); 3971 dma_addr_t mapping; 3972 struct page *data; 3973 3974 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3975 if (!data) 3976 return NULL; 3977 3978 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3979 if (unlikely(dma_mapping_error(d, mapping))) { 3980 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3981 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3982 return NULL; 3983 } 3984 3985 desc->addr = cpu_to_le64(mapping); 3986 rtl8169_mark_to_asic(desc); 3987 3988 return data; 3989 } 3990 3991 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3992 { 3993 int i; 3994 3995 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3996 dma_unmap_page(tp_to_dev(tp), 3997 le64_to_cpu(tp->RxDescArray[i].addr), 3998 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3999 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 4000 tp->Rx_databuff[i] = NULL; 4001 tp->RxDescArray[i].addr = 0; 4002 tp->RxDescArray[i].opts1 = 0; 4003 } 4004 } 4005 4006 static int rtl8169_rx_fill(struct rtl8169_private *tp) 4007 { 4008 int i; 4009 4010 for (i = 0; i < NUM_RX_DESC; i++) { 4011 struct page *data; 4012 4013 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 4014 if (!data) { 4015 rtl8169_rx_clear(tp); 4016 return -ENOMEM; 4017 } 4018 tp->Rx_databuff[i] = data; 4019 } 4020 4021 /* mark as last descriptor in the ring */ 4022 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 4023 4024 return 0; 4025 } 4026 4027 static int rtl8169_init_ring(struct rtl8169_private *tp) 4028 { 4029 rtl8169_init_ring_indexes(tp); 4030 4031 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 4032 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 4033 4034 return rtl8169_rx_fill(tp); 4035 } 4036 4037 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 4038 { 4039 struct ring_info *tx_skb = tp->tx_skb + entry; 4040 struct TxDesc *desc = tp->TxDescArray + entry; 4041 4042 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 4043 DMA_TO_DEVICE); 4044 memset(desc, 0, sizeof(*desc)); 4045 memset(tx_skb, 0, sizeof(*tx_skb)); 4046 } 4047 4048 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 4049 unsigned int n) 4050 { 4051 unsigned int i; 4052 4053 for (i = 0; i < n; i++) { 4054 unsigned int entry = (start + i) % NUM_TX_DESC; 4055 struct ring_info *tx_skb = tp->tx_skb + entry; 4056 unsigned int len = tx_skb->len; 4057 4058 if (len) { 4059 struct sk_buff *skb = tx_skb->skb; 4060 4061 rtl8169_unmap_tx_skb(tp, entry); 4062 if (skb) 4063 dev_consume_skb_any(skb); 4064 } 4065 } 4066 } 4067 4068 static void rtl8169_tx_clear(struct rtl8169_private *tp) 4069 { 4070 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 4071 netdev_reset_queue(tp->dev); 4072 } 4073 4074 static void rtl8169_cleanup(struct rtl8169_private *tp) 4075 { 4076 napi_disable(&tp->napi); 4077 4078 /* Give a racing hard_start_xmit a few cycles to complete. */ 4079 synchronize_net(); 4080 4081 /* Disable interrupts */ 4082 rtl8169_irq_mask_and_ack(tp); 4083 4084 rtl_rx_close(tp); 4085 4086 switch (tp->mac_version) { 4087 case RTL_GIGA_MAC_VER_28: 4088 case RTL_GIGA_MAC_VER_31: 4089 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 4090 break; 4091 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 4092 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4093 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 4094 break; 4095 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_66: 4096 rtl_enable_rxdvgate(tp); 4097 fsleep(2000); 4098 break; 4099 default: 4100 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 4101 fsleep(100); 4102 break; 4103 } 4104 4105 rtl_hw_reset(tp); 4106 4107 rtl8169_tx_clear(tp); 4108 rtl8169_init_ring_indexes(tp); 4109 } 4110 4111 static void rtl_reset_work(struct rtl8169_private *tp) 4112 { 4113 int i; 4114 4115 netif_stop_queue(tp->dev); 4116 4117 rtl8169_cleanup(tp); 4118 4119 for (i = 0; i < NUM_RX_DESC; i++) 4120 rtl8169_mark_to_asic(tp->RxDescArray + i); 4121 4122 napi_enable(&tp->napi); 4123 rtl_hw_start(tp); 4124 } 4125 4126 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 4127 { 4128 struct rtl8169_private *tp = netdev_priv(dev); 4129 4130 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); 4131 } 4132 4133 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 4134 void *addr, unsigned int entry, bool desc_own) 4135 { 4136 struct TxDesc *txd = tp->TxDescArray + entry; 4137 struct device *d = tp_to_dev(tp); 4138 dma_addr_t mapping; 4139 u32 opts1; 4140 int ret; 4141 4142 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4143 ret = dma_mapping_error(d, mapping); 4144 if (unlikely(ret)) { 4145 if (net_ratelimit()) 4146 netdev_err(tp->dev, "Failed to map TX data!\n"); 4147 return ret; 4148 } 4149 4150 txd->addr = cpu_to_le64(mapping); 4151 txd->opts2 = cpu_to_le32(opts[1]); 4152 4153 opts1 = opts[0] | len; 4154 if (entry == NUM_TX_DESC - 1) 4155 opts1 |= RingEnd; 4156 if (desc_own) 4157 opts1 |= DescOwn; 4158 txd->opts1 = cpu_to_le32(opts1); 4159 4160 tp->tx_skb[entry].len = len; 4161 4162 return 0; 4163 } 4164 4165 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4166 const u32 *opts, unsigned int entry) 4167 { 4168 struct skb_shared_info *info = skb_shinfo(skb); 4169 unsigned int cur_frag; 4170 4171 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4172 const skb_frag_t *frag = info->frags + cur_frag; 4173 void *addr = skb_frag_address(frag); 4174 u32 len = skb_frag_size(frag); 4175 4176 entry = (entry + 1) % NUM_TX_DESC; 4177 4178 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4179 goto err_out; 4180 } 4181 4182 return 0; 4183 4184 err_out: 4185 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4186 return -EIO; 4187 } 4188 4189 static bool rtl_skb_is_udp(struct sk_buff *skb) 4190 { 4191 int no = skb_network_offset(skb); 4192 struct ipv6hdr *i6h, _i6h; 4193 struct iphdr *ih, _ih; 4194 4195 switch (vlan_get_protocol(skb)) { 4196 case htons(ETH_P_IP): 4197 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih); 4198 return ih && ih->protocol == IPPROTO_UDP; 4199 case htons(ETH_P_IPV6): 4200 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h); 4201 return i6h && i6h->nexthdr == IPPROTO_UDP; 4202 default: 4203 return false; 4204 } 4205 } 4206 4207 #define RTL_MIN_PATCH_LEN 47 4208 4209 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */ 4210 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, 4211 struct sk_buff *skb) 4212 { 4213 unsigned int padto = 0, len = skb->len; 4214 4215 if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) && 4216 skb_transport_header_was_set(skb)) { 4217 unsigned int trans_data_len = skb_tail_pointer(skb) - 4218 skb_transport_header(skb); 4219 4220 if (trans_data_len >= offsetof(struct udphdr, len) && 4221 trans_data_len < RTL_MIN_PATCH_LEN) { 4222 u16 dest = ntohs(udp_hdr(skb)->dest); 4223 4224 /* dest is a standard PTP port */ 4225 if (dest == 319 || dest == 320) 4226 padto = len + RTL_MIN_PATCH_LEN - trans_data_len; 4227 } 4228 4229 if (trans_data_len < sizeof(struct udphdr)) 4230 padto = max_t(unsigned int, padto, 4231 len + sizeof(struct udphdr) - trans_data_len); 4232 } 4233 4234 return padto; 4235 } 4236 4237 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, 4238 struct sk_buff *skb) 4239 { 4240 unsigned int padto = 0; 4241 4242 switch (tp->mac_version) { 4243 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63: 4244 padto = rtl8125_quirk_udp_padto(tp, skb); 4245 break; 4246 default: 4247 break; 4248 } 4249 4250 switch (tp->mac_version) { 4251 case RTL_GIGA_MAC_VER_34: 4252 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 4253 padto = max_t(unsigned int, padto, ETH_ZLEN); 4254 break; 4255 default: 4256 break; 4257 } 4258 4259 return padto; 4260 } 4261 4262 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4263 { 4264 u32 mss = skb_shinfo(skb)->gso_size; 4265 4266 if (mss) { 4267 opts[0] |= TD_LSO; 4268 opts[0] |= mss << TD0_MSS_SHIFT; 4269 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4270 const struct iphdr *ip = ip_hdr(skb); 4271 4272 if (ip->protocol == IPPROTO_TCP) 4273 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4274 else if (ip->protocol == IPPROTO_UDP) 4275 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4276 else 4277 WARN_ON_ONCE(1); 4278 } 4279 } 4280 4281 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4282 struct sk_buff *skb, u32 *opts) 4283 { 4284 struct skb_shared_info *shinfo = skb_shinfo(skb); 4285 u32 mss = shinfo->gso_size; 4286 4287 if (mss) { 4288 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4289 opts[0] |= TD1_GTSENV4; 4290 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4291 if (skb_cow_head(skb, 0)) 4292 return false; 4293 4294 tcp_v6_gso_csum_prep(skb); 4295 opts[0] |= TD1_GTSENV6; 4296 } else { 4297 WARN_ON_ONCE(1); 4298 } 4299 4300 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; 4301 opts[1] |= mss << TD1_MSS_SHIFT; 4302 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4303 u8 ip_protocol; 4304 4305 switch (vlan_get_protocol(skb)) { 4306 case htons(ETH_P_IP): 4307 opts[1] |= TD1_IPv4_CS; 4308 ip_protocol = ip_hdr(skb)->protocol; 4309 break; 4310 4311 case htons(ETH_P_IPV6): 4312 opts[1] |= TD1_IPv6_CS; 4313 ip_protocol = ipv6_hdr(skb)->nexthdr; 4314 break; 4315 4316 default: 4317 ip_protocol = IPPROTO_RAW; 4318 break; 4319 } 4320 4321 if (ip_protocol == IPPROTO_TCP) 4322 opts[1] |= TD1_TCP_CS; 4323 else if (ip_protocol == IPPROTO_UDP) 4324 opts[1] |= TD1_UDP_CS; 4325 else 4326 WARN_ON_ONCE(1); 4327 4328 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT; 4329 } else { 4330 unsigned int padto = rtl_quirk_packet_padto(tp, skb); 4331 4332 /* skb_padto would free the skb on error */ 4333 return !__skb_put_padto(skb, padto, false); 4334 } 4335 4336 return true; 4337 } 4338 4339 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) 4340 { 4341 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); 4342 } 4343 4344 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4345 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4346 { 4347 switch (tp->mac_version) { 4348 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4349 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4350 return false; 4351 default: 4352 return true; 4353 } 4354 } 4355 4356 static void rtl8169_doorbell(struct rtl8169_private *tp) 4357 { 4358 if (rtl_is_8125(tp)) 4359 RTL_W16(tp, TxPoll_8125, BIT(0)); 4360 else 4361 RTL_W8(tp, TxPoll, NPQ); 4362 } 4363 4364 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4365 struct net_device *dev) 4366 { 4367 struct rtl8169_private *tp = netdev_priv(dev); 4368 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4369 struct TxDesc *txd_first, *txd_last; 4370 bool stop_queue, door_bell; 4371 unsigned int frags; 4372 u32 opts[2]; 4373 4374 if (unlikely(!rtl_tx_slots_avail(tp))) { 4375 if (net_ratelimit()) 4376 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4377 netif_stop_queue(dev); 4378 return NETDEV_TX_BUSY; 4379 } 4380 4381 opts[1] = rtl8169_tx_vlan_tag(skb); 4382 opts[0] = 0; 4383 4384 if (!rtl_chip_supports_csum_v2(tp)) 4385 rtl8169_tso_csum_v1(skb, opts); 4386 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4387 goto err_dma_0; 4388 4389 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4390 entry, false))) 4391 goto err_dma_0; 4392 4393 txd_first = tp->TxDescArray + entry; 4394 4395 frags = skb_shinfo(skb)->nr_frags; 4396 if (frags) { 4397 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4398 goto err_dma_1; 4399 entry = (entry + frags) % NUM_TX_DESC; 4400 } 4401 4402 txd_last = tp->TxDescArray + entry; 4403 txd_last->opts1 |= cpu_to_le32(LastFrag); 4404 tp->tx_skb[entry].skb = skb; 4405 4406 skb_tx_timestamp(skb); 4407 4408 /* Force memory writes to complete before releasing descriptor */ 4409 dma_wmb(); 4410 4411 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4412 4413 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4414 4415 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4416 smp_wmb(); 4417 4418 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); 4419 4420 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), 4421 R8169_TX_STOP_THRS, 4422 R8169_TX_START_THRS); 4423 if (door_bell || stop_queue) 4424 rtl8169_doorbell(tp); 4425 4426 return NETDEV_TX_OK; 4427 4428 err_dma_1: 4429 rtl8169_unmap_tx_skb(tp, entry); 4430 err_dma_0: 4431 dev_kfree_skb_any(skb); 4432 dev->stats.tx_dropped++; 4433 return NETDEV_TX_OK; 4434 } 4435 4436 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4437 { 4438 struct skb_shared_info *info = skb_shinfo(skb); 4439 unsigned int nr_frags = info->nr_frags; 4440 4441 if (!nr_frags) 4442 return UINT_MAX; 4443 4444 return skb_frag_size(info->frags + nr_frags - 1); 4445 } 4446 4447 /* Workaround for hw issues with TSO on RTL8168evl */ 4448 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4449 netdev_features_t features) 4450 { 4451 /* IPv4 header has options field */ 4452 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4453 ip_hdrlen(skb) > sizeof(struct iphdr)) 4454 features &= ~NETIF_F_ALL_TSO; 4455 4456 /* IPv4 TCP header has options field */ 4457 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4458 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4459 features &= ~NETIF_F_ALL_TSO; 4460 4461 else if (rtl_last_frag_len(skb) <= 6) 4462 features &= ~NETIF_F_ALL_TSO; 4463 4464 return features; 4465 } 4466 4467 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4468 struct net_device *dev, 4469 netdev_features_t features) 4470 { 4471 struct rtl8169_private *tp = netdev_priv(dev); 4472 4473 if (skb_is_gso(skb)) { 4474 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4475 features = rtl8168evl_fix_tso(skb, features); 4476 4477 if (skb_transport_offset(skb) > GTTCPHO_MAX && 4478 rtl_chip_supports_csum_v2(tp)) 4479 features &= ~NETIF_F_ALL_TSO; 4480 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4481 /* work around hw bug on some chip versions */ 4482 if (skb->len < ETH_ZLEN) 4483 features &= ~NETIF_F_CSUM_MASK; 4484 4485 if (rtl_quirk_packet_padto(tp, skb)) 4486 features &= ~NETIF_F_CSUM_MASK; 4487 4488 if (skb_transport_offset(skb) > TCPHO_MAX && 4489 rtl_chip_supports_csum_v2(tp)) 4490 features &= ~NETIF_F_CSUM_MASK; 4491 } 4492 4493 return vlan_features_check(skb, features); 4494 } 4495 4496 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4497 { 4498 struct rtl8169_private *tp = netdev_priv(dev); 4499 struct pci_dev *pdev = tp->pci_dev; 4500 int pci_status_errs; 4501 u16 pci_cmd; 4502 4503 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4504 4505 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4506 4507 if (net_ratelimit()) 4508 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4509 pci_cmd, pci_status_errs); 4510 4511 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4512 } 4513 4514 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4515 int budget) 4516 { 4517 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4518 struct sk_buff *skb; 4519 4520 dirty_tx = tp->dirty_tx; 4521 4522 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4523 unsigned int entry = dirty_tx % NUM_TX_DESC; 4524 u32 status; 4525 4526 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4527 if (status & DescOwn) 4528 break; 4529 4530 skb = tp->tx_skb[entry].skb; 4531 rtl8169_unmap_tx_skb(tp, entry); 4532 4533 if (skb) { 4534 pkts_compl++; 4535 bytes_compl += skb->len; 4536 napi_consume_skb(skb, budget); 4537 } 4538 dirty_tx++; 4539 } 4540 4541 if (tp->dirty_tx != dirty_tx) { 4542 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4543 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4544 4545 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4546 rtl_tx_slots_avail(tp), 4547 R8169_TX_START_THRS); 4548 /* 4549 * 8168 hack: TxPoll requests are lost when the Tx packets are 4550 * too close. Let's kick an extra TxPoll request when a burst 4551 * of start_xmit activity is detected (if it is not detected, 4552 * it is slow enough). -- FR 4553 * If skb is NULL then we come here again once a tx irq is 4554 * triggered after the last fragment is marked transmitted. 4555 */ 4556 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4557 rtl8169_doorbell(tp); 4558 } 4559 } 4560 4561 static inline int rtl8169_fragmented_frame(u32 status) 4562 { 4563 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4564 } 4565 4566 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4567 { 4568 u32 status = opts1 & (RxProtoMask | RxCSFailMask); 4569 4570 if (status == RxProtoTCP || status == RxProtoUDP) 4571 skb->ip_summed = CHECKSUM_UNNECESSARY; 4572 else 4573 skb_checksum_none_assert(skb); 4574 } 4575 4576 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) 4577 { 4578 struct device *d = tp_to_dev(tp); 4579 int count; 4580 4581 for (count = 0; count < budget; count++, tp->cur_rx++) { 4582 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; 4583 struct RxDesc *desc = tp->RxDescArray + entry; 4584 struct sk_buff *skb; 4585 const void *rx_buf; 4586 dma_addr_t addr; 4587 u32 status; 4588 4589 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4590 if (status & DescOwn) 4591 break; 4592 4593 /* This barrier is needed to keep us from reading 4594 * any other fields out of the Rx descriptor until 4595 * we know the status of DescOwn 4596 */ 4597 dma_rmb(); 4598 4599 if (unlikely(status & RxRES)) { 4600 if (net_ratelimit()) 4601 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4602 status); 4603 dev->stats.rx_errors++; 4604 if (status & (RxRWT | RxRUNT)) 4605 dev->stats.rx_length_errors++; 4606 if (status & RxCRC) 4607 dev->stats.rx_crc_errors++; 4608 4609 if (!(dev->features & NETIF_F_RXALL)) 4610 goto release_descriptor; 4611 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4612 goto release_descriptor; 4613 } 4614 4615 pkt_size = status & GENMASK(13, 0); 4616 if (likely(!(dev->features & NETIF_F_RXFCS))) 4617 pkt_size -= ETH_FCS_LEN; 4618 4619 /* The driver does not support incoming fragmented frames. 4620 * They are seen as a symptom of over-mtu sized frames. 4621 */ 4622 if (unlikely(rtl8169_fragmented_frame(status))) { 4623 dev->stats.rx_dropped++; 4624 dev->stats.rx_length_errors++; 4625 goto release_descriptor; 4626 } 4627 4628 skb = napi_alloc_skb(&tp->napi, pkt_size); 4629 if (unlikely(!skb)) { 4630 dev->stats.rx_dropped++; 4631 goto release_descriptor; 4632 } 4633 4634 addr = le64_to_cpu(desc->addr); 4635 rx_buf = page_address(tp->Rx_databuff[entry]); 4636 4637 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4638 prefetch(rx_buf); 4639 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4640 skb->tail += pkt_size; 4641 skb->len = pkt_size; 4642 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4643 4644 rtl8169_rx_csum(skb, status); 4645 skb->protocol = eth_type_trans(skb, dev); 4646 4647 rtl8169_rx_vlan_tag(desc, skb); 4648 4649 if (skb->pkt_type == PACKET_MULTICAST) 4650 dev->stats.multicast++; 4651 4652 napi_gro_receive(&tp->napi, skb); 4653 4654 dev_sw_netstats_rx_add(dev, pkt_size); 4655 release_descriptor: 4656 rtl8169_mark_to_asic(desc); 4657 } 4658 4659 return count; 4660 } 4661 4662 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4663 { 4664 struct rtl8169_private *tp = dev_instance; 4665 u32 status = rtl_get_events(tp); 4666 4667 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) 4668 return IRQ_NONE; 4669 4670 /* At least RTL8168fp may unexpectedly set the SYSErr bit */ 4671 if (unlikely(status & SYSErr && 4672 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { 4673 rtl8169_pcierr_interrupt(tp->dev); 4674 goto out; 4675 } 4676 4677 if (status & LinkChg) 4678 phy_mac_interrupt(tp->phydev); 4679 4680 rtl_irq_disable(tp); 4681 napi_schedule(&tp->napi); 4682 out: 4683 rtl_ack_events(tp, status); 4684 4685 return IRQ_HANDLED; 4686 } 4687 4688 static void rtl_task(struct work_struct *work) 4689 { 4690 struct rtl8169_private *tp = 4691 container_of(work, struct rtl8169_private, wk.work); 4692 int ret; 4693 4694 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { 4695 /* if chip isn't accessible, reset bus to revive it */ 4696 if (RTL_R32(tp, TxConfig) == ~0) { 4697 ret = pci_reset_bus(tp->pci_dev); 4698 if (ret < 0) { 4699 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); 4700 netif_device_detach(tp->dev); 4701 return; 4702 } 4703 } 4704 4705 /* ASPM compatibility issues are a typical reason for tx timeouts */ 4706 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | 4707 PCIE_LINK_STATE_L0S); 4708 if (!ret) 4709 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); 4710 goto reset; 4711 } 4712 4713 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { 4714 reset: 4715 rtl_reset_work(tp); 4716 netif_wake_queue(tp->dev); 4717 } 4718 } 4719 4720 static int rtl8169_poll(struct napi_struct *napi, int budget) 4721 { 4722 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4723 struct net_device *dev = tp->dev; 4724 int work_done; 4725 4726 rtl_tx(dev, tp, budget); 4727 4728 work_done = rtl_rx(dev, tp, budget); 4729 4730 if (work_done < budget && napi_complete_done(napi, work_done)) 4731 rtl_irq_enable(tp); 4732 4733 return work_done; 4734 } 4735 4736 static void r8169_phylink_handler(struct net_device *ndev) 4737 { 4738 struct rtl8169_private *tp = netdev_priv(ndev); 4739 struct device *d = tp_to_dev(tp); 4740 4741 if (netif_carrier_ok(ndev)) { 4742 rtl_link_chg_patch(tp); 4743 pm_request_resume(d); 4744 } else { 4745 pm_runtime_idle(d); 4746 } 4747 4748 phy_print_status(tp->phydev); 4749 } 4750 4751 static int r8169_phy_connect(struct rtl8169_private *tp) 4752 { 4753 struct phy_device *phydev = tp->phydev; 4754 phy_interface_t phy_mode; 4755 int ret; 4756 4757 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4758 PHY_INTERFACE_MODE_MII; 4759 4760 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4761 phy_mode); 4762 if (ret) 4763 return ret; 4764 4765 if (!tp->supports_gmii) 4766 phy_set_max_speed(phydev, SPEED_100); 4767 4768 phy_attached_info(phydev); 4769 4770 return 0; 4771 } 4772 4773 static void rtl8169_down(struct rtl8169_private *tp) 4774 { 4775 disable_work_sync(&tp->wk.work); 4776 /* Clear all task flags */ 4777 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4778 4779 phy_stop(tp->phydev); 4780 4781 rtl8169_update_counters(tp); 4782 4783 pci_clear_master(tp->pci_dev); 4784 rtl_pci_commit(tp); 4785 4786 rtl8169_cleanup(tp); 4787 rtl_disable_exit_l1(tp); 4788 rtl_prepare_power_down(tp); 4789 4790 if (tp->dash_type != RTL_DASH_NONE) 4791 rtl8168_driver_stop(tp); 4792 } 4793 4794 static void rtl8169_up(struct rtl8169_private *tp) 4795 { 4796 if (tp->dash_type != RTL_DASH_NONE) 4797 rtl8168_driver_start(tp); 4798 4799 pci_set_master(tp->pci_dev); 4800 phy_init_hw(tp->phydev); 4801 phy_resume(tp->phydev); 4802 rtl8169_init_phy(tp); 4803 napi_enable(&tp->napi); 4804 enable_work(&tp->wk.work); 4805 rtl_reset_work(tp); 4806 4807 phy_start(tp->phydev); 4808 } 4809 4810 static int rtl8169_close(struct net_device *dev) 4811 { 4812 struct rtl8169_private *tp = netdev_priv(dev); 4813 struct pci_dev *pdev = tp->pci_dev; 4814 4815 pm_runtime_get_sync(&pdev->dev); 4816 4817 netif_stop_queue(dev); 4818 rtl8169_down(tp); 4819 rtl8169_rx_clear(tp); 4820 4821 free_irq(tp->irq, tp); 4822 4823 phy_disconnect(tp->phydev); 4824 4825 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4826 tp->RxPhyAddr); 4827 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4828 tp->TxPhyAddr); 4829 tp->TxDescArray = NULL; 4830 tp->RxDescArray = NULL; 4831 4832 pm_runtime_put_sync(&pdev->dev); 4833 4834 return 0; 4835 } 4836 4837 #ifdef CONFIG_NET_POLL_CONTROLLER 4838 static void rtl8169_netpoll(struct net_device *dev) 4839 { 4840 struct rtl8169_private *tp = netdev_priv(dev); 4841 4842 rtl8169_interrupt(tp->irq, tp); 4843 } 4844 #endif 4845 4846 static int rtl_open(struct net_device *dev) 4847 { 4848 struct rtl8169_private *tp = netdev_priv(dev); 4849 struct pci_dev *pdev = tp->pci_dev; 4850 unsigned long irqflags; 4851 int retval = -ENOMEM; 4852 4853 pm_runtime_get_sync(&pdev->dev); 4854 4855 /* 4856 * Rx and Tx descriptors needs 256 bytes alignment. 4857 * dma_alloc_coherent provides more. 4858 */ 4859 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4860 &tp->TxPhyAddr, GFP_KERNEL); 4861 if (!tp->TxDescArray) 4862 goto out; 4863 4864 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4865 &tp->RxPhyAddr, GFP_KERNEL); 4866 if (!tp->RxDescArray) 4867 goto err_free_tx_0; 4868 4869 retval = rtl8169_init_ring(tp); 4870 if (retval < 0) 4871 goto err_free_rx_1; 4872 4873 rtl_request_firmware(tp); 4874 4875 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED; 4876 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); 4877 if (retval < 0) 4878 goto err_release_fw_2; 4879 4880 retval = r8169_phy_connect(tp); 4881 if (retval) 4882 goto err_free_irq; 4883 4884 rtl8169_up(tp); 4885 rtl8169_init_counter_offsets(tp); 4886 netif_start_queue(dev); 4887 out: 4888 pm_runtime_put_sync(&pdev->dev); 4889 4890 return retval; 4891 4892 err_free_irq: 4893 free_irq(tp->irq, tp); 4894 err_release_fw_2: 4895 rtl_release_firmware(tp); 4896 rtl8169_rx_clear(tp); 4897 err_free_rx_1: 4898 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4899 tp->RxPhyAddr); 4900 tp->RxDescArray = NULL; 4901 err_free_tx_0: 4902 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4903 tp->TxPhyAddr); 4904 tp->TxDescArray = NULL; 4905 goto out; 4906 } 4907 4908 static void 4909 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4910 { 4911 struct rtl8169_private *tp = netdev_priv(dev); 4912 struct pci_dev *pdev = tp->pci_dev; 4913 struct rtl8169_counters *counters = tp->counters; 4914 4915 pm_runtime_get_noresume(&pdev->dev); 4916 4917 netdev_stats_to_stats64(stats, &dev->stats); 4918 dev_fetch_sw_netstats(stats, dev->tstats); 4919 4920 /* 4921 * Fetch additional counter values missing in stats collected by driver 4922 * from tally counters. 4923 */ 4924 if (pm_runtime_active(&pdev->dev)) 4925 rtl8169_update_counters(tp); 4926 4927 /* 4928 * Subtract values fetched during initalization. 4929 * See rtl8169_init_counter_offsets for a description why we do that. 4930 */ 4931 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4932 le64_to_cpu(tp->tc_offset.tx_errors); 4933 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4934 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4935 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4936 le16_to_cpu(tp->tc_offset.tx_aborted); 4937 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4938 le16_to_cpu(tp->tc_offset.rx_missed); 4939 4940 pm_runtime_put_noidle(&pdev->dev); 4941 } 4942 4943 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4944 { 4945 netif_device_detach(tp->dev); 4946 4947 if (netif_running(tp->dev)) 4948 rtl8169_down(tp); 4949 } 4950 4951 static int rtl8169_runtime_resume(struct device *dev) 4952 { 4953 struct rtl8169_private *tp = dev_get_drvdata(dev); 4954 4955 rtl_rar_set(tp, tp->dev->dev_addr); 4956 __rtl8169_set_wol(tp, tp->saved_wolopts); 4957 4958 if (tp->TxDescArray) 4959 rtl8169_up(tp); 4960 4961 netif_device_attach(tp->dev); 4962 4963 return 0; 4964 } 4965 4966 static int rtl8169_suspend(struct device *device) 4967 { 4968 struct rtl8169_private *tp = dev_get_drvdata(device); 4969 4970 rtnl_lock(); 4971 rtl8169_net_suspend(tp); 4972 if (!device_may_wakeup(tp_to_dev(tp))) 4973 clk_disable_unprepare(tp->clk); 4974 rtnl_unlock(); 4975 4976 return 0; 4977 } 4978 4979 static int rtl8169_resume(struct device *device) 4980 { 4981 struct rtl8169_private *tp = dev_get_drvdata(device); 4982 4983 if (!device_may_wakeup(tp_to_dev(tp))) 4984 clk_prepare_enable(tp->clk); 4985 4986 /* Reportedly at least Asus X453MA truncates packets otherwise */ 4987 if (tp->mac_version == RTL_GIGA_MAC_VER_37) 4988 rtl_init_rxcfg(tp); 4989 4990 return rtl8169_runtime_resume(device); 4991 } 4992 4993 static int rtl8169_runtime_suspend(struct device *device) 4994 { 4995 struct rtl8169_private *tp = dev_get_drvdata(device); 4996 4997 if (!tp->TxDescArray) { 4998 netif_device_detach(tp->dev); 4999 return 0; 5000 } 5001 5002 rtnl_lock(); 5003 __rtl8169_set_wol(tp, WAKE_PHY); 5004 rtl8169_net_suspend(tp); 5005 rtnl_unlock(); 5006 5007 return 0; 5008 } 5009 5010 static int rtl8169_runtime_idle(struct device *device) 5011 { 5012 struct rtl8169_private *tp = dev_get_drvdata(device); 5013 5014 if (tp->dash_enabled) 5015 return -EBUSY; 5016 5017 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 5018 pm_schedule_suspend(device, 10000); 5019 5020 return -EBUSY; 5021 } 5022 5023 static const struct dev_pm_ops rtl8169_pm_ops = { 5024 SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 5025 RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 5026 rtl8169_runtime_idle) 5027 }; 5028 5029 static void rtl_shutdown(struct pci_dev *pdev) 5030 { 5031 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5032 5033 rtnl_lock(); 5034 rtl8169_net_suspend(tp); 5035 rtnl_unlock(); 5036 5037 /* Restore original MAC address */ 5038 rtl_rar_set(tp, tp->dev->perm_addr); 5039 5040 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { 5041 pci_wake_from_d3(pdev, tp->saved_wolopts); 5042 pci_set_power_state(pdev, PCI_D3hot); 5043 } 5044 } 5045 5046 static void rtl_remove_one(struct pci_dev *pdev) 5047 { 5048 struct rtl8169_private *tp = pci_get_drvdata(pdev); 5049 5050 if (pci_dev_run_wake(pdev)) 5051 pm_runtime_get_noresume(&pdev->dev); 5052 5053 disable_work_sync(&tp->wk.work); 5054 5055 if (IS_ENABLED(CONFIG_R8169_LEDS)) 5056 r8169_remove_leds(tp->leds); 5057 5058 unregister_netdev(tp->dev); 5059 5060 if (tp->dash_type != RTL_DASH_NONE) 5061 rtl8168_driver_stop(tp); 5062 5063 rtl_release_firmware(tp); 5064 5065 /* restore original MAC address */ 5066 rtl_rar_set(tp, tp->dev->perm_addr); 5067 } 5068 5069 static const struct net_device_ops rtl_netdev_ops = { 5070 .ndo_open = rtl_open, 5071 .ndo_stop = rtl8169_close, 5072 .ndo_get_stats64 = rtl8169_get_stats64, 5073 .ndo_start_xmit = rtl8169_start_xmit, 5074 .ndo_features_check = rtl8169_features_check, 5075 .ndo_tx_timeout = rtl8169_tx_timeout, 5076 .ndo_validate_addr = eth_validate_addr, 5077 .ndo_change_mtu = rtl8169_change_mtu, 5078 .ndo_fix_features = rtl8169_fix_features, 5079 .ndo_set_features = rtl8169_set_features, 5080 .ndo_set_mac_address = rtl_set_mac_address, 5081 .ndo_eth_ioctl = phy_do_ioctl_running, 5082 .ndo_set_rx_mode = rtl_set_rx_mode, 5083 #ifdef CONFIG_NET_POLL_CONTROLLER 5084 .ndo_poll_controller = rtl8169_netpoll, 5085 #endif 5086 5087 }; 5088 5089 static void rtl_set_irq_mask(struct rtl8169_private *tp) 5090 { 5091 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5092 5093 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5094 tp->irq_mask |= SYSErr | RxFIFOOver; 5095 } 5096 5097 static int rtl_alloc_irq(struct rtl8169_private *tp) 5098 { 5099 unsigned int flags; 5100 5101 switch (tp->mac_version) { 5102 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5103 rtl_unlock_config_regs(tp); 5104 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5105 rtl_lock_config_regs(tp); 5106 fallthrough; 5107 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5108 flags = PCI_IRQ_INTX; 5109 break; 5110 default: 5111 flags = PCI_IRQ_ALL_TYPES; 5112 break; 5113 } 5114 5115 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5116 } 5117 5118 static void rtl_read_mac_address(struct rtl8169_private *tp, 5119 u8 mac_addr[ETH_ALEN]) 5120 { 5121 /* Get MAC address */ 5122 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5123 u32 value; 5124 5125 value = rtl_eri_read(tp, 0xe0); 5126 put_unaligned_le32(value, mac_addr); 5127 value = rtl_eri_read(tp, 0xe4); 5128 put_unaligned_le16(value, mac_addr + 4); 5129 } else if (rtl_is_8125(tp)) { 5130 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5131 } 5132 } 5133 5134 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5135 { 5136 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5137 } 5138 5139 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5140 { 5141 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5142 } 5143 5144 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5145 { 5146 struct rtl8169_private *tp = mii_bus->priv; 5147 5148 if (phyaddr > 0) 5149 return -ENODEV; 5150 5151 return rtl_readphy(tp, phyreg); 5152 } 5153 5154 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5155 int phyreg, u16 val) 5156 { 5157 struct rtl8169_private *tp = mii_bus->priv; 5158 5159 if (phyaddr > 0) 5160 return -ENODEV; 5161 5162 rtl_writephy(tp, phyreg, val); 5163 5164 return 0; 5165 } 5166 5167 static int r8169_mdio_register(struct rtl8169_private *tp) 5168 { 5169 struct pci_dev *pdev = tp->pci_dev; 5170 struct mii_bus *new_bus; 5171 int ret; 5172 5173 /* On some boards with this chip version the BIOS is buggy and misses 5174 * to reset the PHY page selector. This results in the PHY ID read 5175 * accessing registers on a different page, returning a more or 5176 * less random value. Fix this by resetting the page selector first. 5177 */ 5178 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || 5179 tp->mac_version == RTL_GIGA_MAC_VER_26) 5180 r8169_mdio_write(tp, 0x1f, 0); 5181 5182 new_bus = devm_mdiobus_alloc(&pdev->dev); 5183 if (!new_bus) 5184 return -ENOMEM; 5185 5186 new_bus->name = "r8169"; 5187 new_bus->priv = tp; 5188 new_bus->parent = &pdev->dev; 5189 new_bus->irq[0] = PHY_MAC_INTERRUPT; 5190 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x", 5191 pci_domain_nr(pdev->bus), pci_dev_id(pdev)); 5192 5193 new_bus->read = r8169_mdio_read_reg; 5194 new_bus->write = r8169_mdio_write_reg; 5195 5196 ret = devm_mdiobus_register(&pdev->dev, new_bus); 5197 if (ret) 5198 return ret; 5199 5200 tp->phydev = mdiobus_get_phy(new_bus, 0); 5201 if (!tp->phydev) { 5202 return -ENODEV; 5203 } else if (!tp->phydev->drv) { 5204 /* Most chip versions fail with the genphy driver. 5205 * Therefore ensure that the dedicated PHY driver is loaded. 5206 */ 5207 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5208 tp->phydev->phy_id); 5209 return -EUNATCH; 5210 } 5211 5212 tp->phydev->mac_managed_pm = true; 5213 if (rtl_supports_eee(tp)) 5214 phy_support_eee(tp->phydev); 5215 phy_support_asym_pause(tp->phydev); 5216 5217 /* mimic behavior of r8125/r8126 vendor drivers */ 5218 if (tp->mac_version == RTL_GIGA_MAC_VER_61) 5219 phy_set_eee_broken(tp->phydev, 5220 ETHTOOL_LINK_MODE_2500baseT_Full_BIT); 5221 phy_set_eee_broken(tp->phydev, ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 5222 5223 /* PHY will be woken up in rtl_open() */ 5224 phy_suspend(tp->phydev); 5225 5226 return 0; 5227 } 5228 5229 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5230 { 5231 rtl_enable_rxdvgate(tp); 5232 5233 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5234 msleep(1); 5235 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5236 5237 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5238 r8168g_wait_ll_share_fifo_ready(tp); 5239 5240 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5241 r8168g_wait_ll_share_fifo_ready(tp); 5242 } 5243 5244 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5245 { 5246 rtl_enable_rxdvgate(tp); 5247 5248 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5249 msleep(1); 5250 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5251 5252 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5253 r8168g_wait_ll_share_fifo_ready(tp); 5254 5255 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5256 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5257 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5258 r8168g_wait_ll_share_fifo_ready(tp); 5259 } 5260 5261 static void rtl_hw_initialize(struct rtl8169_private *tp) 5262 { 5263 switch (tp->mac_version) { 5264 case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53: 5265 rtl8168ep_stop_cmac(tp); 5266 fallthrough; 5267 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5268 rtl_hw_init_8168g(tp); 5269 break; 5270 case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_66: 5271 rtl_hw_init_8125(tp); 5272 break; 5273 default: 5274 break; 5275 } 5276 } 5277 5278 static int rtl_jumbo_max(struct rtl8169_private *tp) 5279 { 5280 /* Non-GBit versions don't support jumbo frames */ 5281 if (!tp->supports_gmii) 5282 return 0; 5283 5284 switch (tp->mac_version) { 5285 /* RTL8169 */ 5286 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5287 return JUMBO_7K; 5288 /* RTL8168b */ 5289 case RTL_GIGA_MAC_VER_17: 5290 return JUMBO_4K; 5291 /* RTL8168c */ 5292 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5293 return JUMBO_6K; 5294 default: 5295 return JUMBO_9K; 5296 } 5297 } 5298 5299 static void rtl_init_mac_address(struct rtl8169_private *tp) 5300 { 5301 u8 mac_addr[ETH_ALEN] __aligned(2) = {}; 5302 struct net_device *dev = tp->dev; 5303 int rc; 5304 5305 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5306 if (!rc) 5307 goto done; 5308 5309 rtl_read_mac_address(tp, mac_addr); 5310 if (is_valid_ether_addr(mac_addr)) 5311 goto done; 5312 5313 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5314 if (is_valid_ether_addr(mac_addr)) 5315 goto done; 5316 5317 eth_random_addr(mac_addr); 5318 dev->addr_assign_type = NET_ADDR_RANDOM; 5319 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5320 done: 5321 eth_hw_addr_set(dev, mac_addr); 5322 rtl_rar_set(tp, mac_addr); 5323 } 5324 5325 /* register is set if system vendor successfully tested ASPM 1.2 */ 5326 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) 5327 { 5328 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && 5329 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) 5330 return true; 5331 5332 return false; 5333 } 5334 5335 static int r8169_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 5336 u32 attr, int channel, long *val) 5337 { 5338 struct rtl8169_private *tp = dev_get_drvdata(dev); 5339 int val_raw; 5340 5341 val_raw = phy_read_paged(tp->phydev, 0xbd8, 0x12) & 0x3ff; 5342 if (val_raw >= 512) 5343 val_raw -= 1024; 5344 5345 *val = 1000 * val_raw / 2; 5346 5347 return 0; 5348 } 5349 5350 static const struct hwmon_ops r8169_hwmon_ops = { 5351 .visible = 0444, 5352 .read = r8169_hwmon_read, 5353 }; 5354 5355 static const struct hwmon_channel_info * const r8169_hwmon_info[] = { 5356 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), 5357 NULL 5358 }; 5359 5360 static const struct hwmon_chip_info r8169_hwmon_chip_info = { 5361 .ops = &r8169_hwmon_ops, 5362 .info = r8169_hwmon_info, 5363 }; 5364 5365 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5366 { 5367 struct rtl8169_private *tp; 5368 int jumbo_max, region, rc; 5369 enum mac_version chipset; 5370 struct net_device *dev; 5371 u32 txconfig; 5372 u16 xid; 5373 5374 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5375 if (!dev) 5376 return -ENOMEM; 5377 5378 SET_NETDEV_DEV(dev, &pdev->dev); 5379 dev->netdev_ops = &rtl_netdev_ops; 5380 tp = netdev_priv(dev); 5381 tp->dev = dev; 5382 tp->pci_dev = pdev; 5383 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5384 tp->ocp_base = OCP_STD_PHY_BASE; 5385 5386 raw_spin_lock_init(&tp->mac_ocp_lock); 5387 mutex_init(&tp->led_lock); 5388 5389 /* Get the *optional* external "ether_clk" used on some boards */ 5390 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); 5391 if (IS_ERR(tp->clk)) 5392 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); 5393 5394 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5395 rc = pcim_enable_device(pdev); 5396 if (rc < 0) 5397 return dev_err_probe(&pdev->dev, rc, "enable failure\n"); 5398 5399 if (pcim_set_mwi(pdev) < 0) 5400 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5401 5402 /* use first MMIO region */ 5403 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5404 if (region < 0) 5405 return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n"); 5406 5407 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME); 5408 if (rc < 0) 5409 return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n"); 5410 5411 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5412 5413 txconfig = RTL_R32(tp, TxConfig); 5414 if (txconfig == ~0U) 5415 return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n"); 5416 5417 xid = (txconfig >> 20) & 0xfcf; 5418 5419 /* Identify chip attached to board */ 5420 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5421 if (chipset == RTL_GIGA_MAC_NONE) 5422 return dev_err_probe(&pdev->dev, -ENODEV, 5423 "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", 5424 xid); 5425 tp->mac_version = chipset; 5426 5427 /* Disable ASPM L1 as that cause random device stop working 5428 * problems as well as full system hangs for some PCIe devices users. 5429 */ 5430 if (rtl_aspm_is_safe(tp)) 5431 rc = 0; 5432 else 5433 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1); 5434 tp->aspm_manageable = !rc; 5435 5436 tp->dash_type = rtl_get_dash_type(tp); 5437 tp->dash_enabled = rtl_dash_is_enabled(tp); 5438 5439 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5440 5441 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5442 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5443 dev->features |= NETIF_F_HIGHDMA; 5444 5445 rtl_init_rxcfg(tp); 5446 5447 rtl8169_irq_mask_and_ack(tp); 5448 5449 rtl_hw_initialize(tp); 5450 5451 rtl_hw_reset(tp); 5452 5453 rc = rtl_alloc_irq(tp); 5454 if (rc < 0) 5455 return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n"); 5456 5457 tp->irq = pci_irq_vector(pdev, 0); 5458 5459 INIT_WORK(&tp->wk.work, rtl_task); 5460 disable_work(&tp->wk.work); 5461 5462 rtl_init_mac_address(tp); 5463 5464 dev->ethtool_ops = &rtl8169_ethtool_ops; 5465 5466 netif_napi_add(dev, &tp->napi, rtl8169_poll); 5467 5468 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5469 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5470 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5471 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5472 5473 /* 5474 * Pretend we are using VLANs; This bypasses a nasty bug where 5475 * Interrupts stop flowing on high load on 8110SCd controllers. 5476 */ 5477 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5478 /* Disallow toggling */ 5479 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5480 5481 if (rtl_chip_supports_csum_v2(tp)) 5482 dev->hw_features |= NETIF_F_IPV6_CSUM; 5483 5484 dev->features |= dev->hw_features; 5485 5486 if (rtl_chip_supports_csum_v2(tp)) { 5487 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5488 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2); 5489 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2); 5490 } else { 5491 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5492 netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1); 5493 netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1); 5494 } 5495 5496 /* There has been a number of reports that using SG/TSO results in 5497 * tx timeouts. However for a lot of people SG/TSO works fine. 5498 * It's not fully clear which chip versions are affected. Vendor 5499 * drivers enable SG/TSO for certain chip versions per default, 5500 * let's mimic this here. On other chip versions users can 5501 * use ethtool to enable SG/TSO, use at own risk! 5502 */ 5503 if (tp->mac_version >= RTL_GIGA_MAC_VER_46 && 5504 tp->mac_version != RTL_GIGA_MAC_VER_61) 5505 dev->features |= dev->hw_features; 5506 5507 dev->hw_features |= NETIF_F_RXALL; 5508 dev->hw_features |= NETIF_F_RXFCS; 5509 5510 dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 5511 5512 netdev_sw_irq_coalesce_default_on(dev); 5513 5514 /* configure chip for default features */ 5515 rtl8169_set_features(dev, dev->features); 5516 5517 if (!tp->dash_enabled) { 5518 rtl_set_d3_pll_down(tp, true); 5519 } else { 5520 rtl_set_d3_pll_down(tp, false); 5521 dev->ethtool->wol_enabled = 1; 5522 } 5523 5524 jumbo_max = rtl_jumbo_max(tp); 5525 if (jumbo_max) 5526 dev->max_mtu = jumbo_max; 5527 5528 rtl_set_irq_mask(tp); 5529 5530 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5531 5532 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5533 &tp->counters_phys_addr, 5534 GFP_KERNEL); 5535 if (!tp->counters) 5536 return -ENOMEM; 5537 5538 pci_set_drvdata(pdev, tp); 5539 5540 rc = r8169_mdio_register(tp); 5541 if (rc) 5542 return rc; 5543 5544 /* The temperature sensor is available from RTl8125B */ 5545 if (IS_REACHABLE(CONFIG_HWMON) && tp->mac_version >= RTL_GIGA_MAC_VER_63) 5546 /* ignore errors */ 5547 devm_hwmon_device_register_with_info(&pdev->dev, "nic_temp", tp, 5548 &r8169_hwmon_chip_info, 5549 NULL); 5550 rc = register_netdev(dev); 5551 if (rc) 5552 return rc; 5553 5554 if (IS_ENABLED(CONFIG_R8169_LEDS)) { 5555 if (rtl_is_8125(tp)) 5556 tp->leds = rtl8125_init_leds(dev); 5557 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) 5558 tp->leds = rtl8168_init_leds(dev); 5559 } 5560 5561 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5562 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); 5563 5564 if (jumbo_max) 5565 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5566 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5567 "ok" : "ko"); 5568 5569 if (tp->dash_type != RTL_DASH_NONE) { 5570 netdev_info(dev, "DASH %s\n", 5571 tp->dash_enabled ? "enabled" : "disabled"); 5572 rtl8168_driver_start(tp); 5573 } 5574 5575 if (pci_dev_run_wake(pdev)) 5576 pm_runtime_put_sync(&pdev->dev); 5577 5578 return 0; 5579 } 5580 5581 static struct pci_driver rtl8169_pci_driver = { 5582 .name = KBUILD_MODNAME, 5583 .id_table = rtl8169_pci_tbl, 5584 .probe = rtl_init_one, 5585 .remove = rtl_remove_one, 5586 .shutdown = rtl_shutdown, 5587 .driver.pm = pm_ptr(&rtl8169_pm_ops), 5588 }; 5589 5590 module_pci_driver(rtl8169_pci_driver); 5591