1 /* 2 3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux. 4 5 Maintained by Jeff Garzik <jgarzik@pobox.com> 6 Copyright 2000-2002 Jeff Garzik 7 8 Much code comes from Donald Becker's rtl8139.c driver, 9 versions 1.13 and older. This driver was originally based 10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13: 11 12 -----<snip>----- 13 14 Written 1997-2001 by Donald Becker. 15 This software may be used and distributed according to the 16 terms of the GNU General Public License (GPL), incorporated 17 herein by reference. Drivers based on or derived from this 18 code fall under the GPL and must retain the authorship, 19 copyright and license notice. This file is not a complete 20 program and may only be used when the entire operating 21 system is licensed under the GPL. 22 23 This driver is for boards based on the RTL8129 and RTL8139 24 PCI ethernet chips. 25 26 The author may be reached as becker@scyld.com, or C/O Scyld 27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis 28 MD 21403 29 30 Support and updates available at 31 http://www.scyld.com/network/rtl8139.html 32 33 Twister-tuning table provided by Kinston 34 <shangh@realtek.com.tw>. 35 36 -----<snip>----- 37 38 This software may be used and distributed according to the terms 39 of the GNU General Public License, incorporated herein by reference. 40 41 Contributors: 42 43 Donald Becker - he wrote the original driver, kudos to him! 44 (but please don't e-mail him for support, this isn't his driver) 45 46 Tigran Aivazian - bug fixes, skbuff free cleanup 47 48 Martin Mares - suggestions for PCI cleanup 49 50 David S. Miller - PCI DMA and softnet updates 51 52 Ernst Gill - fixes ported from BSD driver 53 54 Daniel Kobras - identified specific locations of 55 posted MMIO write bugginess 56 57 Gerard Sharp - bug fix, testing and feedback 58 59 David Ford - Rx ring wrap fix 60 61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me 62 to find and fix a crucial bug on older chipsets. 63 64 Donald Becker/Chris Butterworth/Marcus Westergren - 65 Noticed various Rx packet size-related buglets. 66 67 Santiago Garcia Mantinan - testing and feedback 68 69 Jens David - 2.2.x kernel backports 70 71 Martin Dennett - incredibly helpful insight on undocumented 72 features of the 8139 chips 73 74 Jean-Jacques Michel - bug fix 75 76 Tobias Ringström - Rx interrupt status checking suggestion 77 78 Andrew Morton - Clear blocked signals, avoid 79 buffer overrun setting current->comm. 80 81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls 82 83 Robert Kuebel - Save kernel thread from dying on any signal. 84 85 Submitting bug reports: 86 87 "rtl8139-diag -mmmaaavvveefN" output 88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log 89 90 */ 91 92 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 93 94 #define DRV_NAME "8139too" 95 96 #include <linux/module.h> 97 #include <linux/kernel.h> 98 #include <linux/compiler.h> 99 #include <linux/pci.h> 100 #include <linux/init.h> 101 #include <linux/interrupt.h> 102 #include <linux/netdevice.h> 103 #include <linux/etherdevice.h> 104 #include <linux/rtnetlink.h> 105 #include <linux/delay.h> 106 #include <linux/ethtool.h> 107 #include <linux/mii.h> 108 #include <linux/completion.h> 109 #include <linux/crc32.h> 110 #include <linux/io.h> 111 #include <linux/uaccess.h> 112 #include <linux/gfp.h> 113 #include <linux/if_vlan.h> 114 #include <asm/irq.h> 115 116 /* Default Message level */ 117 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 118 NETIF_MSG_PROBE | \ 119 NETIF_MSG_LINK) 120 121 122 /* define to 1, 2 or 3 to enable copious debugging info */ 123 #define RTL8139_DEBUG 0 124 125 /* define to 1 to disable lightweight runtime debugging checks */ 126 #undef RTL8139_NDEBUG 127 128 129 #ifdef RTL8139_NDEBUG 130 # define assert(expr) do {} while (0) 131 #else 132 # define assert(expr) \ 133 if (unlikely(!(expr))) { \ 134 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \ 135 #expr, __FILE__, __func__, __LINE__); \ 136 } 137 #endif 138 139 140 /* A few user-configurable values. */ 141 /* media options */ 142 #define MAX_UNITS 8 143 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 144 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; 145 146 /* Whether to use MMIO or PIO. Default to MMIO. */ 147 #ifdef CONFIG_8139TOO_PIO 148 static bool use_io = true; 149 #else 150 static bool use_io = false; 151 #endif 152 153 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 154 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 155 static int multicast_filter_limit = 32; 156 157 /* bitmapped message enable number */ 158 static int debug = -1; 159 160 /* 161 * Receive ring size 162 * Warning: 64K ring has hardware issues and may lock up. 163 */ 164 #if defined(CONFIG_SH_DREAMCAST) 165 #define RX_BUF_IDX 0 /* 8K ring */ 166 #else 167 #define RX_BUF_IDX 2 /* 32K ring */ 168 #endif 169 #define RX_BUF_LEN (8192 << RX_BUF_IDX) 170 #define RX_BUF_PAD 16 171 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */ 172 173 #if RX_BUF_LEN == 65536 174 #define RX_BUF_TOT_LEN RX_BUF_LEN 175 #else 176 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD) 177 #endif 178 179 /* Number of Tx descriptor registers. */ 180 #define NUM_TX_DESC 4 181 182 /* max supported ethernet frame size -- must be at least (dev->mtu+18+4).*/ 183 #define MAX_ETH_FRAME_SIZE 1792 184 185 /* max supported payload size */ 186 #define MAX_ETH_DATA_SIZE (MAX_ETH_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN) 187 188 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+18+4). */ 189 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE 190 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) 191 192 /* PCI Tuning Parameters 193 Threshold is bytes transferred to chip before transmission starts. */ 194 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 195 196 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ 197 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ 198 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */ 199 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 200 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */ 201 202 /* Operational parameters that usually are not changed. */ 203 /* Time in jiffies before concluding the transmitter is hung. */ 204 #define TX_TIMEOUT (6*HZ) 205 206 207 enum { 208 HAS_MII_XCVR = 0x010000, 209 HAS_CHIP_XCVR = 0x020000, 210 HAS_LNK_CHNG = 0x040000, 211 }; 212 213 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */ 214 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */ 215 #define RTL_MIN_IO_SIZE 0x80 216 #define RTL8139B_IO_SIZE 256 217 218 #define RTL8129_CAPS HAS_MII_XCVR 219 #define RTL8139_CAPS (HAS_CHIP_XCVR|HAS_LNK_CHNG) 220 221 typedef enum { 222 RTL8139 = 0, 223 RTL8129, 224 } board_t; 225 226 227 /* indexed by board_t, above */ 228 static const struct { 229 const char *name; 230 u32 hw_flags; 231 } board_info[] = { 232 { "RealTek RTL8139", RTL8139_CAPS }, 233 { "RealTek RTL8129", RTL8129_CAPS }, 234 }; 235 236 237 static const struct pci_device_id rtl8139_pci_tbl[] = { 238 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 239 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 240 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 241 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 242 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 243 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 244 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 245 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 246 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 247 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 248 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 249 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 250 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 251 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 252 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 253 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 254 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 255 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 256 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 257 {0x16ec, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 258 259 #ifdef CONFIG_SH_SECUREEDGE5410 260 /* Bogus 8139 silicon reports 8129 without external PROM :-( */ 261 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 }, 262 #endif 263 #ifdef CONFIG_8139TOO_8129 264 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 }, 265 #endif 266 267 /* some crazy cards report invalid vendor ids like 268 * 0x0001 here. The other ids are valid and constant, 269 * so we simply don't match on the main vendor id. 270 */ 271 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 }, 272 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 }, 273 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 }, 274 275 {0,} 276 }; 277 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl); 278 279 static struct { 280 const char str[ETH_GSTRING_LEN]; 281 } ethtool_stats_keys[] = { 282 { "early_rx" }, 283 { "tx_buf_mapped" }, 284 { "tx_timeouts" }, 285 { "rx_lost_in_ring" }, 286 }; 287 288 /* The rest of these values should never change. */ 289 290 /* Symbolic offsets to registers. */ 291 enum RTL8139_registers { 292 MAC0 = 0, /* Ethernet hardware address. */ 293 MAR0 = 8, /* Multicast filter. */ 294 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */ 295 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ 296 RxBuf = 0x30, 297 ChipCmd = 0x37, 298 RxBufPtr = 0x38, 299 RxBufAddr = 0x3A, 300 IntrMask = 0x3C, 301 IntrStatus = 0x3E, 302 TxConfig = 0x40, 303 RxConfig = 0x44, 304 Timer = 0x48, /* A general-purpose counter. */ 305 RxMissed = 0x4C, /* 24 bits valid, write clears. */ 306 Cfg9346 = 0x50, 307 Config0 = 0x51, 308 Config1 = 0x52, 309 TimerInt = 0x54, 310 MediaStatus = 0x58, 311 Config3 = 0x59, 312 Config4 = 0x5A, /* absent on RTL-8139A */ 313 HltClk = 0x5B, 314 MultiIntr = 0x5C, 315 TxSummary = 0x60, 316 BasicModeCtrl = 0x62, 317 BasicModeStatus = 0x64, 318 NWayAdvert = 0x66, 319 NWayLPAR = 0x68, 320 NWayExpansion = 0x6A, 321 /* Undocumented registers, but required for proper operation. */ 322 FIFOTMS = 0x70, /* FIFO Control and test. */ 323 CSCR = 0x74, /* Chip Status and Configuration Register. */ 324 PARA78 = 0x78, 325 FlashReg = 0xD4, /* Communication with Flash ROM, four bytes. */ 326 PARA7c = 0x7c, /* Magic transceiver parameter register. */ 327 Config5 = 0xD8, /* absent on RTL-8139A */ 328 }; 329 330 enum ClearBitMasks { 331 MultiIntrClear = 0xF000, 332 ChipCmdClear = 0xE2, 333 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), 334 }; 335 336 enum ChipCmdBits { 337 CmdReset = 0x10, 338 CmdRxEnb = 0x08, 339 CmdTxEnb = 0x04, 340 RxBufEmpty = 0x01, 341 }; 342 343 /* Interrupt register bits, using my own meaningful names. */ 344 enum IntrStatusBits { 345 PCIErr = 0x8000, 346 PCSTimeout = 0x4000, 347 RxFIFOOver = 0x40, 348 RxUnderrun = 0x20, 349 RxOverflow = 0x10, 350 TxErr = 0x08, 351 TxOK = 0x04, 352 RxErr = 0x02, 353 RxOK = 0x01, 354 355 RxAckBits = RxFIFOOver | RxOverflow | RxOK, 356 }; 357 358 enum TxStatusBits { 359 TxHostOwns = 0x2000, 360 TxUnderrun = 0x4000, 361 TxStatOK = 0x8000, 362 TxOutOfWindow = 0x20000000, 363 TxAborted = 0x40000000, 364 TxCarrierLost = 0x80000000, 365 }; 366 enum RxStatusBits { 367 RxMulticast = 0x8000, 368 RxPhysical = 0x4000, 369 RxBroadcast = 0x2000, 370 RxBadSymbol = 0x0020, 371 RxRunt = 0x0010, 372 RxTooLong = 0x0008, 373 RxCRCErr = 0x0004, 374 RxBadAlign = 0x0002, 375 RxStatusOK = 0x0001, 376 }; 377 378 /* Bits in RxConfig. */ 379 enum rx_mode_bits { 380 AcceptErr = 0x20, 381 AcceptRunt = 0x10, 382 AcceptBroadcast = 0x08, 383 AcceptMulticast = 0x04, 384 AcceptMyPhys = 0x02, 385 AcceptAllPhys = 0x01, 386 }; 387 388 /* Bits in TxConfig. */ 389 enum tx_config_bits { 390 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ 391 TxIFGShift = 24, 392 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ 393 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ 394 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ 395 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ 396 397 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ 398 TxCRC = (1 << 16), /* DISABLE Tx pkt CRC append */ 399 TxClearAbt = (1 << 0), /* Clear abort (WO) */ 400 TxDMAShift = 8, /* DMA burst value (0-7) is shifted X many bits */ 401 TxRetryShift = 4, /* TXRR value (0-15) is shifted X many bits */ 402 403 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ 404 }; 405 406 /* Bits in Config1 */ 407 enum Config1Bits { 408 Cfg1_PM_Enable = 0x01, 409 Cfg1_VPD_Enable = 0x02, 410 Cfg1_PIO = 0x04, 411 Cfg1_MMIO = 0x08, 412 LWAKE = 0x10, /* not on 8139, 8139A */ 413 Cfg1_Driver_Load = 0x20, 414 Cfg1_LED0 = 0x40, 415 Cfg1_LED1 = 0x80, 416 SLEEP = (1 << 1), /* only on 8139, 8139A */ 417 PWRDN = (1 << 0), /* only on 8139, 8139A */ 418 }; 419 420 /* Bits in Config3 */ 421 enum Config3Bits { 422 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */ 423 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */ 424 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */ 425 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */ 426 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */ 427 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */ 428 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */ 429 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */ 430 }; 431 432 /* Bits in Config4 */ 433 enum Config4Bits { 434 LWPTN = (1 << 2), /* not on 8139, 8139A */ 435 }; 436 437 /* Bits in Config5 */ 438 enum Config5Bits { 439 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */ 440 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */ 441 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */ 442 Cfg5_FIFOAddrPtr= (1 << 3), /* Realtek internal SRAM testing */ 443 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */ 444 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */ 445 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */ 446 }; 447 448 enum RxConfigBits { 449 /* rx fifo threshold */ 450 RxCfgFIFOShift = 13, 451 RxCfgFIFONone = (7 << RxCfgFIFOShift), 452 453 /* Max DMA burst */ 454 RxCfgDMAShift = 8, 455 RxCfgDMAUnlimited = (7 << RxCfgDMAShift), 456 457 /* rx ring buffer length */ 458 RxCfgRcv8K = 0, 459 RxCfgRcv16K = (1 << 11), 460 RxCfgRcv32K = (1 << 12), 461 RxCfgRcv64K = (1 << 11) | (1 << 12), 462 463 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */ 464 RxNoWrap = (1 << 7), 465 }; 466 467 /* Twister tuning parameters from RealTek. 468 Completely undocumented, but required to tune bad links on some boards. */ 469 enum CSCRBits { 470 CSCR_LinkOKBit = 0x0400, 471 CSCR_LinkChangeBit = 0x0800, 472 CSCR_LinkStatusBits = 0x0f000, 473 CSCR_LinkDownOffCmd = 0x003c0, 474 CSCR_LinkDownCmd = 0x0f3c0, 475 }; 476 477 enum Cfg9346Bits { 478 Cfg9346_Lock = 0x00, 479 Cfg9346_Unlock = 0xC0, 480 }; 481 482 typedef enum { 483 CH_8139 = 0, 484 CH_8139_K, 485 CH_8139A, 486 CH_8139A_G, 487 CH_8139B, 488 CH_8130, 489 CH_8139C, 490 CH_8100, 491 CH_8100B_8139D, 492 CH_8101, 493 } chip_t; 494 495 enum chip_flags { 496 HasHltClk = (1 << 0), 497 HasLWake = (1 << 1), 498 }; 499 500 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ 501 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) 502 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) 503 504 /* directly indexed by chip_t, above */ 505 static const struct { 506 const char *name; 507 u32 version; /* from RTL8139C/RTL8139D docs */ 508 u32 flags; 509 } rtl_chip_info[] = { 510 { "RTL-8139", 511 HW_REVID(1, 0, 0, 0, 0, 0, 0), 512 HasHltClk, 513 }, 514 515 { "RTL-8139 rev K", 516 HW_REVID(1, 1, 0, 0, 0, 0, 0), 517 HasHltClk, 518 }, 519 520 { "RTL-8139A", 521 HW_REVID(1, 1, 1, 0, 0, 0, 0), 522 HasHltClk, /* XXX undocumented? */ 523 }, 524 525 { "RTL-8139A rev G", 526 HW_REVID(1, 1, 1, 0, 0, 1, 0), 527 HasHltClk, /* XXX undocumented? */ 528 }, 529 530 { "RTL-8139B", 531 HW_REVID(1, 1, 1, 1, 0, 0, 0), 532 HasLWake, 533 }, 534 535 { "RTL-8130", 536 HW_REVID(1, 1, 1, 1, 1, 0, 0), 537 HasLWake, 538 }, 539 540 { "RTL-8139C", 541 HW_REVID(1, 1, 1, 0, 1, 0, 0), 542 HasLWake, 543 }, 544 545 { "RTL-8100", 546 HW_REVID(1, 1, 1, 1, 0, 1, 0), 547 HasLWake, 548 }, 549 550 { "RTL-8100B/8139D", 551 HW_REVID(1, 1, 1, 0, 1, 0, 1), 552 HasHltClk /* XXX undocumented? */ 553 | HasLWake, 554 }, 555 556 { "RTL-8101", 557 HW_REVID(1, 1, 1, 0, 1, 1, 1), 558 HasLWake, 559 }, 560 }; 561 562 struct rtl_extra_stats { 563 unsigned long early_rx; 564 unsigned long tx_buf_mapped; 565 unsigned long tx_timeouts; 566 unsigned long rx_lost_in_ring; 567 }; 568 569 struct rtl8139_stats { 570 u64 packets; 571 u64 bytes; 572 struct u64_stats_sync syncp; 573 }; 574 575 struct rtl8139_private { 576 void __iomem *mmio_addr; 577 int drv_flags; 578 struct pci_dev *pci_dev; 579 u32 msg_enable; 580 struct napi_struct napi; 581 struct net_device *dev; 582 583 unsigned char *rx_ring; 584 unsigned int cur_rx; /* RX buf index of next pkt */ 585 struct rtl8139_stats rx_stats; 586 dma_addr_t rx_ring_dma; 587 588 unsigned int tx_flag; 589 unsigned long cur_tx; 590 unsigned long dirty_tx; 591 struct rtl8139_stats tx_stats; 592 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */ 593 unsigned char *tx_bufs; /* Tx bounce buffer region. */ 594 dma_addr_t tx_bufs_dma; 595 596 signed char phys[4]; /* MII device addresses. */ 597 598 /* Twister tune state. */ 599 char twistie, twist_row, twist_col; 600 601 unsigned int watchdog_fired : 1; 602 unsigned int default_port : 4; /* Last dev->if_port value. */ 603 unsigned int have_thread : 1; 604 605 spinlock_t lock; 606 spinlock_t rx_lock; 607 608 chip_t chipset; 609 u32 rx_config; 610 struct rtl_extra_stats xstats; 611 612 struct delayed_work thread; 613 614 struct mii_if_info mii; 615 unsigned int regs_len; 616 unsigned long fifo_copy_timeout; 617 }; 618 619 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>"); 620 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver"); 621 MODULE_LICENSE("GPL"); 622 623 module_param(use_io, bool, 0); 624 MODULE_PARM_DESC(use_io, "Force use of I/O access mode. 0=MMIO 1=PIO"); 625 module_param(multicast_filter_limit, int, 0); 626 module_param_array(media, int, NULL, 0); 627 module_param_array(full_duplex, int, NULL, 0); 628 module_param(debug, int, 0); 629 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number"); 630 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses"); 631 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps"); 632 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)"); 633 634 static int read_eeprom (void __iomem *ioaddr, int location, int addr_len); 635 static int rtl8139_open (struct net_device *dev); 636 static int mdio_read (struct net_device *dev, int phy_id, int location); 637 static void mdio_write (struct net_device *dev, int phy_id, int location, 638 int val); 639 static void rtl8139_start_thread(struct rtl8139_private *tp); 640 static void rtl8139_tx_timeout (struct net_device *dev, unsigned int txqueue); 641 static void rtl8139_init_ring (struct net_device *dev); 642 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 643 struct net_device *dev); 644 #ifdef CONFIG_NET_POLL_CONTROLLER 645 static void rtl8139_poll_controller(struct net_device *dev); 646 #endif 647 static int rtl8139_set_mac_address(struct net_device *dev, void *p); 648 static int rtl8139_poll(struct napi_struct *napi, int budget); 649 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance); 650 static int rtl8139_close (struct net_device *dev); 651 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd); 652 static void rtl8139_get_stats64(struct net_device *dev, 653 struct rtnl_link_stats64 *stats); 654 static void rtl8139_set_rx_mode (struct net_device *dev); 655 static void __set_rx_mode (struct net_device *dev); 656 static void rtl8139_hw_start (struct net_device *dev); 657 static void rtl8139_thread (struct work_struct *work); 658 static void rtl8139_tx_timeout_task(struct work_struct *work); 659 static const struct ethtool_ops rtl8139_ethtool_ops; 660 661 /* write MMIO register, with flush */ 662 /* Flush avoids rtl8139 bug w/ posted MMIO writes */ 663 #define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0) 664 #define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0) 665 #define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0) 666 667 /* write MMIO register */ 668 #define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg)) 669 #define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg)) 670 #define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg)) 671 672 /* read MMIO register */ 673 #define RTL_R8(reg) ioread8 (ioaddr + (reg)) 674 #define RTL_R16(reg) ioread16 (ioaddr + (reg)) 675 #define RTL_R32(reg) ioread32 (ioaddr + (reg)) 676 677 678 static const u16 rtl8139_intr_mask = 679 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | 680 TxErr | TxOK | RxErr | RxOK; 681 682 static const u16 rtl8139_norx_intr_mask = 683 PCIErr | PCSTimeout | RxUnderrun | 684 TxErr | TxOK | RxErr ; 685 686 #if RX_BUF_IDX == 0 687 static const unsigned int rtl8139_rx_config = 688 RxCfgRcv8K | RxNoWrap | 689 (RX_FIFO_THRESH << RxCfgFIFOShift) | 690 (RX_DMA_BURST << RxCfgDMAShift); 691 #elif RX_BUF_IDX == 1 692 static const unsigned int rtl8139_rx_config = 693 RxCfgRcv16K | RxNoWrap | 694 (RX_FIFO_THRESH << RxCfgFIFOShift) | 695 (RX_DMA_BURST << RxCfgDMAShift); 696 #elif RX_BUF_IDX == 2 697 static const unsigned int rtl8139_rx_config = 698 RxCfgRcv32K | RxNoWrap | 699 (RX_FIFO_THRESH << RxCfgFIFOShift) | 700 (RX_DMA_BURST << RxCfgDMAShift); 701 #elif RX_BUF_IDX == 3 702 static const unsigned int rtl8139_rx_config = 703 RxCfgRcv64K | 704 (RX_FIFO_THRESH << RxCfgFIFOShift) | 705 (RX_DMA_BURST << RxCfgDMAShift); 706 #else 707 #error "Invalid configuration for 8139_RXBUF_IDX" 708 #endif 709 710 static const unsigned int rtl8139_tx_config = 711 TxIFG96 | (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift); 712 713 static void __rtl8139_cleanup_dev (struct net_device *dev) 714 { 715 struct rtl8139_private *tp = netdev_priv(dev); 716 struct pci_dev *pdev; 717 718 assert (dev != NULL); 719 assert (tp->pci_dev != NULL); 720 pdev = tp->pci_dev; 721 722 if (tp->mmio_addr) 723 pci_iounmap (pdev, tp->mmio_addr); 724 725 /* it's ok to call this even if we have no regions to free */ 726 pci_release_regions (pdev); 727 728 free_netdev(dev); 729 } 730 731 732 static void rtl8139_chip_reset (void __iomem *ioaddr) 733 { 734 int i; 735 736 /* Soft reset the chip. */ 737 RTL_W8 (ChipCmd, CmdReset); 738 739 /* Check that the chip has finished the reset. */ 740 for (i = 1000; i > 0; i--) { 741 barrier(); 742 if ((RTL_R8 (ChipCmd) & CmdReset) == 0) 743 break; 744 udelay (10); 745 } 746 } 747 748 749 static struct net_device *rtl8139_init_board(struct pci_dev *pdev) 750 { 751 struct device *d = &pdev->dev; 752 void __iomem *ioaddr; 753 struct net_device *dev; 754 struct rtl8139_private *tp; 755 u8 tmp8; 756 int rc, disable_dev_on_err = 0; 757 unsigned int i, bar; 758 unsigned long io_len; 759 u32 version; 760 static const struct { 761 unsigned long mask; 762 char *type; 763 } res[] = { 764 { IORESOURCE_IO, "PIO" }, 765 { IORESOURCE_MEM, "MMIO" } 766 }; 767 768 assert (pdev != NULL); 769 770 /* dev and priv zeroed in alloc_etherdev */ 771 dev = alloc_etherdev (sizeof (*tp)); 772 if (dev == NULL) 773 return ERR_PTR(-ENOMEM); 774 775 SET_NETDEV_DEV(dev, &pdev->dev); 776 777 tp = netdev_priv(dev); 778 tp->pci_dev = pdev; 779 780 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 781 rc = pci_enable_device (pdev); 782 if (rc) 783 goto err_out; 784 785 disable_dev_on_err = 1; 786 rc = pci_request_regions (pdev, DRV_NAME); 787 if (rc) 788 goto err_out; 789 790 pci_set_master (pdev); 791 792 u64_stats_init(&tp->rx_stats.syncp); 793 u64_stats_init(&tp->tx_stats.syncp); 794 795 retry: 796 /* PIO bar register comes first. */ 797 bar = !use_io; 798 799 io_len = pci_resource_len(pdev, bar); 800 801 dev_dbg(d, "%s region size = 0x%02lX\n", res[bar].type, io_len); 802 803 if (!(pci_resource_flags(pdev, bar) & res[bar].mask)) { 804 dev_err(d, "region #%d not a %s resource, aborting\n", bar, 805 res[bar].type); 806 rc = -ENODEV; 807 goto err_out; 808 } 809 if (io_len < RTL_MIN_IO_SIZE) { 810 dev_err(d, "Invalid PCI %s region size(s), aborting\n", 811 res[bar].type); 812 rc = -ENODEV; 813 goto err_out; 814 } 815 816 ioaddr = pci_iomap(pdev, bar, 0); 817 if (!ioaddr) { 818 dev_err(d, "cannot map %s\n", res[bar].type); 819 if (!use_io) { 820 use_io = true; 821 goto retry; 822 } 823 rc = -ENODEV; 824 goto err_out; 825 } 826 tp->regs_len = io_len; 827 tp->mmio_addr = ioaddr; 828 829 /* Bring old chips out of low-power mode. */ 830 RTL_W8 (HltClk, 'R'); 831 832 /* check for missing/broken hardware */ 833 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) { 834 dev_err(&pdev->dev, "Chip not responding, ignoring board\n"); 835 rc = -EIO; 836 goto err_out; 837 } 838 839 /* identify chip attached to board */ 840 version = RTL_R32 (TxConfig) & HW_REVID_MASK; 841 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++) 842 if (version == rtl_chip_info[i].version) { 843 tp->chipset = i; 844 goto match; 845 } 846 847 /* if unknown chip, assume array element #0, original RTL-8139 in this case */ 848 i = 0; 849 dev_dbg(&pdev->dev, "unknown chip version, assuming RTL-8139\n"); 850 dev_dbg(&pdev->dev, "TxConfig = 0x%x\n", RTL_R32 (TxConfig)); 851 tp->chipset = 0; 852 853 match: 854 pr_debug("chipset id (%d) == index %d, '%s'\n", 855 version, i, rtl_chip_info[i].name); 856 857 if (tp->chipset >= CH_8139B) { 858 u8 new_tmp8 = tmp8 = RTL_R8 (Config1); 859 pr_debug("PCI PM wakeup\n"); 860 if ((rtl_chip_info[tp->chipset].flags & HasLWake) && 861 (tmp8 & LWAKE)) 862 new_tmp8 &= ~LWAKE; 863 new_tmp8 |= Cfg1_PM_Enable; 864 if (new_tmp8 != tmp8) { 865 RTL_W8 (Cfg9346, Cfg9346_Unlock); 866 RTL_W8 (Config1, tmp8); 867 RTL_W8 (Cfg9346, Cfg9346_Lock); 868 } 869 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 870 tmp8 = RTL_R8 (Config4); 871 if (tmp8 & LWPTN) { 872 RTL_W8 (Cfg9346, Cfg9346_Unlock); 873 RTL_W8 (Config4, tmp8 & ~LWPTN); 874 RTL_W8 (Cfg9346, Cfg9346_Lock); 875 } 876 } 877 } else { 878 pr_debug("Old chip wakeup\n"); 879 tmp8 = RTL_R8 (Config1); 880 tmp8 &= ~(SLEEP | PWRDN); 881 RTL_W8 (Config1, tmp8); 882 } 883 884 rtl8139_chip_reset (ioaddr); 885 886 return dev; 887 888 err_out: 889 __rtl8139_cleanup_dev (dev); 890 if (disable_dev_on_err) 891 pci_disable_device (pdev); 892 return ERR_PTR(rc); 893 } 894 895 static int rtl8139_set_features(struct net_device *dev, netdev_features_t features) 896 { 897 struct rtl8139_private *tp = netdev_priv(dev); 898 unsigned long flags; 899 netdev_features_t changed = features ^ dev->features; 900 void __iomem *ioaddr = tp->mmio_addr; 901 902 if (!(changed & (NETIF_F_RXALL))) 903 return 0; 904 905 spin_lock_irqsave(&tp->lock, flags); 906 907 if (changed & NETIF_F_RXALL) { 908 int rx_mode = tp->rx_config; 909 if (features & NETIF_F_RXALL) 910 rx_mode |= (AcceptErr | AcceptRunt); 911 else 912 rx_mode &= ~(AcceptErr | AcceptRunt); 913 tp->rx_config = rtl8139_rx_config | rx_mode; 914 RTL_W32_F(RxConfig, tp->rx_config); 915 } 916 917 spin_unlock_irqrestore(&tp->lock, flags); 918 919 return 0; 920 } 921 922 static const struct net_device_ops rtl8139_netdev_ops = { 923 .ndo_open = rtl8139_open, 924 .ndo_stop = rtl8139_close, 925 .ndo_get_stats64 = rtl8139_get_stats64, 926 .ndo_validate_addr = eth_validate_addr, 927 .ndo_set_mac_address = rtl8139_set_mac_address, 928 .ndo_start_xmit = rtl8139_start_xmit, 929 .ndo_set_rx_mode = rtl8139_set_rx_mode, 930 .ndo_eth_ioctl = netdev_ioctl, 931 .ndo_tx_timeout = rtl8139_tx_timeout, 932 #ifdef CONFIG_NET_POLL_CONTROLLER 933 .ndo_poll_controller = rtl8139_poll_controller, 934 #endif 935 .ndo_set_features = rtl8139_set_features, 936 }; 937 938 static int rtl8139_init_one(struct pci_dev *pdev, 939 const struct pci_device_id *ent) 940 { 941 struct net_device *dev = NULL; 942 struct rtl8139_private *tp; 943 __le16 addr[ETH_ALEN / 2]; 944 int i, addr_len, option; 945 void __iomem *ioaddr; 946 static int board_idx = -1; 947 948 assert (pdev != NULL); 949 assert (ent != NULL); 950 951 board_idx++; 952 953 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 954 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision >= 0x20) { 955 dev_info(&pdev->dev, 956 "This (id %04x:%04x rev %02x) is an enhanced 8139C+ chip, use 8139cp\n", 957 pdev->vendor, pdev->device, pdev->revision); 958 return -ENODEV; 959 } 960 961 if (pdev->vendor == PCI_VENDOR_ID_REALTEK && 962 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && 963 pdev->subsystem_vendor == PCI_VENDOR_ID_ATHEROS && 964 pdev->subsystem_device == PCI_DEVICE_ID_REALTEK_8139) { 965 pr_info("OQO Model 2 detected. Forcing PIO\n"); 966 use_io = true; 967 } 968 969 dev = rtl8139_init_board (pdev); 970 if (IS_ERR(dev)) 971 return PTR_ERR(dev); 972 973 assert (dev != NULL); 974 tp = netdev_priv(dev); 975 tp->dev = dev; 976 977 ioaddr = tp->mmio_addr; 978 assert (ioaddr != NULL); 979 980 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6; 981 for (i = 0; i < 3; i++) 982 addr[i] = cpu_to_le16(read_eeprom (ioaddr, i + 7, addr_len)); 983 eth_hw_addr_set(dev, (u8 *)addr); 984 985 /* The Rtl8139-specific entries in the device structure. */ 986 dev->netdev_ops = &rtl8139_netdev_ops; 987 dev->ethtool_ops = &rtl8139_ethtool_ops; 988 dev->watchdog_timeo = TX_TIMEOUT; 989 netif_napi_add(dev, &tp->napi, rtl8139_poll); 990 991 /* note: the hardware is not capable of sg/csum/highdma, however 992 * through the use of skb_copy_and_csum_dev we enable these 993 * features 994 */ 995 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA; 996 dev->vlan_features = dev->features; 997 998 dev->hw_features |= NETIF_F_RXALL; 999 dev->hw_features |= NETIF_F_RXFCS; 1000 1001 /* MTU range: 68 - 1770 */ 1002 dev->min_mtu = ETH_MIN_MTU; 1003 dev->max_mtu = MAX_ETH_DATA_SIZE; 1004 1005 /* tp zeroed and aligned in alloc_etherdev */ 1006 tp = netdev_priv(dev); 1007 1008 /* note: tp->chipset set in rtl8139_init_board */ 1009 tp->drv_flags = board_info[ent->driver_data].hw_flags; 1010 tp->mmio_addr = ioaddr; 1011 tp->msg_enable = 1012 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1)); 1013 spin_lock_init (&tp->lock); 1014 spin_lock_init (&tp->rx_lock); 1015 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1016 tp->mii.dev = dev; 1017 tp->mii.mdio_read = mdio_read; 1018 tp->mii.mdio_write = mdio_write; 1019 tp->mii.phy_id_mask = 0x3f; 1020 tp->mii.reg_num_mask = 0x1f; 1021 1022 /* dev is fully set up and ready to use now */ 1023 pr_debug("about to register device named %s (%p)...\n", 1024 dev->name, dev); 1025 i = register_netdev (dev); 1026 if (i) goto err_out; 1027 1028 pci_set_drvdata (pdev, dev); 1029 1030 netdev_info(dev, "%s at 0x%p, %pM, IRQ %d\n", 1031 board_info[ent->driver_data].name, 1032 ioaddr, dev->dev_addr, pdev->irq); 1033 1034 netdev_dbg(dev, "Identified 8139 chip type '%s'\n", 1035 rtl_chip_info[tp->chipset].name); 1036 1037 /* Find the connected MII xcvrs. 1038 Doing this in open() would allow detecting external xcvrs later, but 1039 takes too much time. */ 1040 #ifdef CONFIG_8139TOO_8129 1041 if (tp->drv_flags & HAS_MII_XCVR) { 1042 int phy, phy_idx = 0; 1043 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) { 1044 int mii_status = mdio_read(dev, phy, 1); 1045 if (mii_status != 0xffff && mii_status != 0x0000) { 1046 u16 advertising = mdio_read(dev, phy, 4); 1047 tp->phys[phy_idx++] = phy; 1048 netdev_info(dev, "MII transceiver %d status 0x%04x advertising %04x\n", 1049 phy, mii_status, advertising); 1050 } 1051 } 1052 if (phy_idx == 0) { 1053 netdev_info(dev, "No MII transceivers found! Assuming SYM transceiver\n"); 1054 tp->phys[0] = 32; 1055 } 1056 } else 1057 #endif 1058 tp->phys[0] = 32; 1059 tp->mii.phy_id = tp->phys[0]; 1060 1061 /* The lower four bits are the media type. */ 1062 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 1063 if (option > 0) { 1064 tp->mii.full_duplex = (option & 0x210) ? 1 : 0; 1065 tp->default_port = option & 0xFF; 1066 if (tp->default_port) 1067 tp->mii.force_media = 1; 1068 } 1069 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0) 1070 tp->mii.full_duplex = full_duplex[board_idx]; 1071 if (tp->mii.full_duplex) { 1072 netdev_info(dev, "Media type forced to Full Duplex\n"); 1073 /* Changing the MII-advertised media because might prevent 1074 re-connection. */ 1075 tp->mii.force_media = 1; 1076 } 1077 if (tp->default_port) { 1078 netdev_info(dev, " Forcing %dMbps %s-duplex operation\n", 1079 (option & 0x20 ? 100 : 10), 1080 (option & 0x10 ? "full" : "half")); 1081 mdio_write(dev, tp->phys[0], 0, 1082 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */ 1083 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */ 1084 } 1085 1086 /* Put the chip into low-power mode. */ 1087 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1088 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 1089 1090 return 0; 1091 1092 err_out: 1093 __rtl8139_cleanup_dev (dev); 1094 pci_disable_device (pdev); 1095 return i; 1096 } 1097 1098 1099 static void rtl8139_remove_one(struct pci_dev *pdev) 1100 { 1101 struct net_device *dev = pci_get_drvdata (pdev); 1102 struct rtl8139_private *tp = netdev_priv(dev); 1103 1104 assert (dev != NULL); 1105 1106 cancel_delayed_work_sync(&tp->thread); 1107 1108 unregister_netdev (dev); 1109 1110 __rtl8139_cleanup_dev (dev); 1111 pci_disable_device (pdev); 1112 } 1113 1114 1115 /* Serial EEPROM section. */ 1116 1117 /* EEPROM_Ctrl bits. */ 1118 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 1119 #define EE_CS 0x08 /* EEPROM chip select. */ 1120 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 1121 #define EE_WRITE_0 0x00 1122 #define EE_WRITE_1 0x02 1123 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 1124 #define EE_ENB (0x80 | EE_CS) 1125 1126 /* Delay between EEPROM clock transitions. 1127 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 1128 */ 1129 1130 #define eeprom_delay() (void)RTL_R8(Cfg9346) 1131 1132 /* The EEPROM commands include the alway-set leading bit. */ 1133 #define EE_WRITE_CMD (5) 1134 #define EE_READ_CMD (6) 1135 #define EE_ERASE_CMD (7) 1136 1137 static int read_eeprom(void __iomem *ioaddr, int location, int addr_len) 1138 { 1139 int i; 1140 unsigned retval = 0; 1141 int read_cmd = location | (EE_READ_CMD << addr_len); 1142 1143 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS); 1144 RTL_W8 (Cfg9346, EE_ENB); 1145 eeprom_delay (); 1146 1147 /* Shift the read command bits out. */ 1148 for (i = 4 + addr_len; i >= 0; i--) { 1149 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 1150 RTL_W8 (Cfg9346, EE_ENB | dataval); 1151 eeprom_delay (); 1152 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK); 1153 eeprom_delay (); 1154 } 1155 RTL_W8 (Cfg9346, EE_ENB); 1156 eeprom_delay (); 1157 1158 for (i = 16; i > 0; i--) { 1159 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK); 1160 eeprom_delay (); 1161 retval = 1162 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 : 1163 0); 1164 RTL_W8 (Cfg9346, EE_ENB); 1165 eeprom_delay (); 1166 } 1167 1168 /* Terminate the EEPROM access. */ 1169 RTL_W8(Cfg9346, 0); 1170 eeprom_delay (); 1171 1172 return retval; 1173 } 1174 1175 /* MII serial management: mostly bogus for now. */ 1176 /* Read and write the MII management registers using software-generated 1177 serial MDIO protocol. 1178 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually 1179 met by back-to-back PCI I/O cycles, but we insert a delay to avoid 1180 "overclocking" issues. */ 1181 #define MDIO_DIR 0x80 1182 #define MDIO_DATA_OUT 0x04 1183 #define MDIO_DATA_IN 0x02 1184 #define MDIO_CLK 0x01 1185 #define MDIO_WRITE0 (MDIO_DIR) 1186 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT) 1187 1188 #define mdio_delay() RTL_R8(Config4) 1189 1190 1191 static const char mii_2_8139_map[8] = { 1192 BasicModeCtrl, 1193 BasicModeStatus, 1194 0, 1195 0, 1196 NWayAdvert, 1197 NWayLPAR, 1198 NWayExpansion, 1199 0 1200 }; 1201 1202 1203 #ifdef CONFIG_8139TOO_8129 1204 /* Syncronize the MII management interface by shifting 32 one bits out. */ 1205 static void mdio_sync (void __iomem *ioaddr) 1206 { 1207 int i; 1208 1209 for (i = 32; i >= 0; i--) { 1210 RTL_W8 (Config4, MDIO_WRITE1); 1211 mdio_delay (); 1212 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK); 1213 mdio_delay (); 1214 } 1215 } 1216 #endif 1217 1218 static int mdio_read (struct net_device *dev, int phy_id, int location) 1219 { 1220 struct rtl8139_private *tp = netdev_priv(dev); 1221 int retval = 0; 1222 #ifdef CONFIG_8139TOO_8129 1223 void __iomem *ioaddr = tp->mmio_addr; 1224 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; 1225 int i; 1226 #endif 1227 1228 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1229 void __iomem *ioaddr = tp->mmio_addr; 1230 return location < 8 && mii_2_8139_map[location] ? 1231 RTL_R16 (mii_2_8139_map[location]) : 0; 1232 } 1233 1234 #ifdef CONFIG_8139TOO_8129 1235 mdio_sync (ioaddr); 1236 /* Shift the read command bits out. */ 1237 for (i = 15; i >= 0; i--) { 1238 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0; 1239 1240 RTL_W8 (Config4, MDIO_DIR | dataval); 1241 mdio_delay (); 1242 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK); 1243 mdio_delay (); 1244 } 1245 1246 /* Read the two transition, 16 data, and wire-idle bits. */ 1247 for (i = 19; i > 0; i--) { 1248 RTL_W8 (Config4, 0); 1249 mdio_delay (); 1250 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0); 1251 RTL_W8 (Config4, MDIO_CLK); 1252 mdio_delay (); 1253 } 1254 #endif 1255 1256 return (retval >> 1) & 0xffff; 1257 } 1258 1259 1260 static void mdio_write (struct net_device *dev, int phy_id, int location, 1261 int value) 1262 { 1263 struct rtl8139_private *tp = netdev_priv(dev); 1264 #ifdef CONFIG_8139TOO_8129 1265 void __iomem *ioaddr = tp->mmio_addr; 1266 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; 1267 int i; 1268 #endif 1269 1270 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1271 void __iomem *ioaddr = tp->mmio_addr; 1272 if (location == 0) { 1273 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1274 RTL_W16 (BasicModeCtrl, value); 1275 RTL_W8 (Cfg9346, Cfg9346_Lock); 1276 } else if (location < 8 && mii_2_8139_map[location]) 1277 RTL_W16 (mii_2_8139_map[location], value); 1278 return; 1279 } 1280 1281 #ifdef CONFIG_8139TOO_8129 1282 mdio_sync (ioaddr); 1283 1284 /* Shift the command bits out. */ 1285 for (i = 31; i >= 0; i--) { 1286 int dataval = 1287 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 1288 RTL_W8 (Config4, dataval); 1289 mdio_delay (); 1290 RTL_W8 (Config4, dataval | MDIO_CLK); 1291 mdio_delay (); 1292 } 1293 /* Clear out extra bits. */ 1294 for (i = 2; i > 0; i--) { 1295 RTL_W8 (Config4, 0); 1296 mdio_delay (); 1297 RTL_W8 (Config4, MDIO_CLK); 1298 mdio_delay (); 1299 } 1300 #endif 1301 } 1302 1303 1304 static int rtl8139_open (struct net_device *dev) 1305 { 1306 struct rtl8139_private *tp = netdev_priv(dev); 1307 void __iomem *ioaddr = tp->mmio_addr; 1308 const int irq = tp->pci_dev->irq; 1309 int retval; 1310 1311 retval = request_irq(irq, rtl8139_interrupt, IRQF_SHARED, dev->name, dev); 1312 if (retval) 1313 return retval; 1314 1315 tp->tx_bufs = dma_alloc_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1316 &tp->tx_bufs_dma, GFP_KERNEL); 1317 tp->rx_ring = dma_alloc_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1318 &tp->rx_ring_dma, GFP_KERNEL); 1319 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) { 1320 free_irq(irq, dev); 1321 1322 if (tp->tx_bufs) 1323 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 1324 tp->tx_bufs, tp->tx_bufs_dma); 1325 if (tp->rx_ring) 1326 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 1327 tp->rx_ring, tp->rx_ring_dma); 1328 1329 return -ENOMEM; 1330 1331 } 1332 1333 napi_enable(&tp->napi); 1334 1335 tp->mii.full_duplex = tp->mii.force_media; 1336 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000; 1337 1338 rtl8139_init_ring (dev); 1339 rtl8139_hw_start (dev); 1340 netif_start_queue (dev); 1341 1342 netif_dbg(tp, ifup, dev, 1343 "%s() ioaddr %#llx IRQ %d GP Pins %02x %s-duplex\n", 1344 __func__, 1345 (unsigned long long)pci_resource_start (tp->pci_dev, 1), 1346 irq, RTL_R8 (MediaStatus), 1347 tp->mii.full_duplex ? "full" : "half"); 1348 1349 rtl8139_start_thread(tp); 1350 1351 return 0; 1352 } 1353 1354 1355 static void rtl_check_media (struct net_device *dev, unsigned int init_media) 1356 { 1357 struct rtl8139_private *tp = netdev_priv(dev); 1358 1359 if (tp->phys[0] >= 0) { 1360 mii_check_media(&tp->mii, netif_msg_link(tp), init_media); 1361 } 1362 } 1363 1364 /* Start the hardware at open or resume. */ 1365 static void rtl8139_hw_start (struct net_device *dev) 1366 { 1367 struct rtl8139_private *tp = netdev_priv(dev); 1368 void __iomem *ioaddr = tp->mmio_addr; 1369 u32 i; 1370 u8 tmp; 1371 1372 /* Bring old chips out of low-power mode. */ 1373 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 1374 RTL_W8 (HltClk, 'R'); 1375 1376 rtl8139_chip_reset (ioaddr); 1377 1378 /* unlock Config[01234] and BMCR register writes */ 1379 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1380 /* Restore our idea of the MAC address. */ 1381 RTL_W32_F (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0))); 1382 RTL_W32_F (MAC0 + 4, le16_to_cpu (*(__le16 *) (dev->dev_addr + 4))); 1383 1384 tp->cur_rx = 0; 1385 1386 /* init Rx ring buffer DMA address */ 1387 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1388 1389 /* Must enable Tx/Rx before setting transfer thresholds! */ 1390 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1391 1392 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1393 RTL_W32 (RxConfig, tp->rx_config); 1394 RTL_W32 (TxConfig, rtl8139_tx_config); 1395 1396 rtl_check_media (dev, 1); 1397 1398 if (tp->chipset >= CH_8139B) { 1399 /* Disable magic packet scanning, which is enabled 1400 * when PM is enabled in Config1. It can be reenabled 1401 * via ETHTOOL_SWOL if desired. */ 1402 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic); 1403 } 1404 1405 netdev_dbg(dev, "init buffer addresses\n"); 1406 1407 /* Lock Config[01234] and BMCR register writes */ 1408 RTL_W8 (Cfg9346, Cfg9346_Lock); 1409 1410 /* init Tx buffer DMA addresses */ 1411 for (i = 0; i < NUM_TX_DESC; i++) 1412 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs)); 1413 1414 RTL_W32 (RxMissed, 0); 1415 1416 rtl8139_set_rx_mode (dev); 1417 1418 /* no early-rx interrupts */ 1419 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear); 1420 1421 /* make sure RxTx has started */ 1422 tmp = RTL_R8 (ChipCmd); 1423 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb))) 1424 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1425 1426 /* Enable all known interrupts by setting the interrupt mask. */ 1427 RTL_W16 (IntrMask, rtl8139_intr_mask); 1428 } 1429 1430 1431 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1432 static void rtl8139_init_ring (struct net_device *dev) 1433 { 1434 struct rtl8139_private *tp = netdev_priv(dev); 1435 int i; 1436 1437 tp->cur_rx = 0; 1438 tp->cur_tx = 0; 1439 tp->dirty_tx = 0; 1440 1441 for (i = 0; i < NUM_TX_DESC; i++) 1442 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE]; 1443 } 1444 1445 1446 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */ 1447 static int next_tick = 3 * HZ; 1448 1449 #ifndef CONFIG_8139TOO_TUNE_TWISTER 1450 static inline void rtl8139_tune_twister (struct net_device *dev, 1451 struct rtl8139_private *tp) {} 1452 #else 1453 enum TwisterParamVals { 1454 PARA78_default = 0x78fa8388, 1455 PARA7c_default = 0xcb38de43, /* param[0][3] */ 1456 PARA7c_xxx = 0xcb38de43, 1457 }; 1458 1459 static const unsigned long param[4][4] = { 1460 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1461 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1462 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1463 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1464 }; 1465 1466 static void rtl8139_tune_twister (struct net_device *dev, 1467 struct rtl8139_private *tp) 1468 { 1469 int linkcase; 1470 void __iomem *ioaddr = tp->mmio_addr; 1471 1472 /* This is a complicated state machine to configure the "twister" for 1473 impedance/echos based on the cable length. 1474 All of this is magic and undocumented. 1475 */ 1476 switch (tp->twistie) { 1477 case 1: 1478 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) { 1479 /* We have link beat, let us tune the twister. */ 1480 RTL_W16 (CSCR, CSCR_LinkDownOffCmd); 1481 tp->twistie = 2; /* Change to state 2. */ 1482 next_tick = HZ / 10; 1483 } else { 1484 /* Just put in some reasonable defaults for when beat returns. */ 1485 RTL_W16 (CSCR, CSCR_LinkDownCmd); 1486 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */ 1487 RTL_W32 (PARA78, PARA78_default); 1488 RTL_W32 (PARA7c, PARA7c_default); 1489 tp->twistie = 0; /* Bail from future actions. */ 1490 } 1491 break; 1492 case 2: 1493 /* Read how long it took to hear the echo. */ 1494 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits; 1495 if (linkcase == 0x7000) 1496 tp->twist_row = 3; 1497 else if (linkcase == 0x3000) 1498 tp->twist_row = 2; 1499 else if (linkcase == 0x1000) 1500 tp->twist_row = 1; 1501 else 1502 tp->twist_row = 0; 1503 tp->twist_col = 0; 1504 tp->twistie = 3; /* Change to state 2. */ 1505 next_tick = HZ / 10; 1506 break; 1507 case 3: 1508 /* Put out four tuning parameters, one per 100msec. */ 1509 if (tp->twist_col == 0) 1510 RTL_W16 (FIFOTMS, 0); 1511 RTL_W32 (PARA7c, param[(int) tp->twist_row] 1512 [(int) tp->twist_col]); 1513 next_tick = HZ / 10; 1514 if (++tp->twist_col >= 4) { 1515 /* For short cables we are done. 1516 For long cables (row == 3) check for mistune. */ 1517 tp->twistie = 1518 (tp->twist_row == 3) ? 4 : 0; 1519 } 1520 break; 1521 case 4: 1522 /* Special case for long cables: check for mistune. */ 1523 if ((RTL_R16 (CSCR) & 1524 CSCR_LinkStatusBits) == 0x7000) { 1525 tp->twistie = 0; 1526 break; 1527 } else { 1528 RTL_W32 (PARA7c, 0xfb38de03); 1529 tp->twistie = 5; 1530 next_tick = HZ / 10; 1531 } 1532 break; 1533 case 5: 1534 /* Retune for shorter cable (column 2). */ 1535 RTL_W32 (FIFOTMS, 0x20); 1536 RTL_W32 (PARA78, PARA78_default); 1537 RTL_W32 (PARA7c, PARA7c_default); 1538 RTL_W32 (FIFOTMS, 0x00); 1539 tp->twist_row = 2; 1540 tp->twist_col = 0; 1541 tp->twistie = 3; 1542 next_tick = HZ / 10; 1543 break; 1544 1545 default: 1546 /* do nothing */ 1547 break; 1548 } 1549 } 1550 #endif /* CONFIG_8139TOO_TUNE_TWISTER */ 1551 1552 static inline void rtl8139_thread_iter (struct net_device *dev, 1553 struct rtl8139_private *tp, 1554 void __iomem *ioaddr) 1555 { 1556 int mii_lpa; 1557 1558 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA); 1559 1560 if (!tp->mii.force_media && mii_lpa != 0xffff) { 1561 int duplex = ((mii_lpa & LPA_100FULL) || 1562 (mii_lpa & 0x01C0) == 0x0040); 1563 if (tp->mii.full_duplex != duplex) { 1564 tp->mii.full_duplex = duplex; 1565 1566 if (mii_lpa) { 1567 netdev_info(dev, "Setting %s-duplex based on MII #%d link partner ability of %04x\n", 1568 tp->mii.full_duplex ? "full" : "half", 1569 tp->phys[0], mii_lpa); 1570 } else { 1571 netdev_info(dev, "media is unconnected, link down, or incompatible connection\n"); 1572 } 1573 #if 0 1574 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1575 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20); 1576 RTL_W8 (Cfg9346, Cfg9346_Lock); 1577 #endif 1578 } 1579 } 1580 1581 next_tick = HZ * 60; 1582 1583 rtl8139_tune_twister (dev, tp); 1584 1585 netdev_dbg(dev, "Media selection tick, Link partner %04x\n", 1586 RTL_R16(NWayLPAR)); 1587 netdev_dbg(dev, "Other registers are IntMask %04x IntStatus %04x\n", 1588 RTL_R16(IntrMask), RTL_R16(IntrStatus)); 1589 netdev_dbg(dev, "Chip config %02x %02x\n", 1590 RTL_R8(Config0), RTL_R8(Config1)); 1591 } 1592 1593 static void rtl8139_thread (struct work_struct *work) 1594 { 1595 struct rtl8139_private *tp = 1596 container_of(work, struct rtl8139_private, thread.work); 1597 struct net_device *dev = tp->mii.dev; 1598 unsigned long thr_delay = next_tick; 1599 1600 rtnl_lock(); 1601 1602 if (!netif_running(dev)) 1603 goto out_unlock; 1604 1605 if (tp->watchdog_fired) { 1606 tp->watchdog_fired = 0; 1607 rtl8139_tx_timeout_task(work); 1608 } else 1609 rtl8139_thread_iter(dev, tp, tp->mmio_addr); 1610 1611 if (tp->have_thread) 1612 schedule_delayed_work(&tp->thread, thr_delay); 1613 out_unlock: 1614 rtnl_unlock (); 1615 } 1616 1617 static void rtl8139_start_thread(struct rtl8139_private *tp) 1618 { 1619 tp->twistie = 0; 1620 if (tp->chipset == CH_8139_K) 1621 tp->twistie = 1; 1622 else if (tp->drv_flags & HAS_LNK_CHNG) 1623 return; 1624 1625 tp->have_thread = 1; 1626 tp->watchdog_fired = 0; 1627 1628 schedule_delayed_work(&tp->thread, next_tick); 1629 } 1630 1631 static inline void rtl8139_tx_clear (struct rtl8139_private *tp) 1632 { 1633 tp->cur_tx = 0; 1634 tp->dirty_tx = 0; 1635 1636 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */ 1637 } 1638 1639 static void rtl8139_tx_timeout_task (struct work_struct *work) 1640 { 1641 struct rtl8139_private *tp = 1642 container_of(work, struct rtl8139_private, thread.work); 1643 struct net_device *dev = tp->mii.dev; 1644 void __iomem *ioaddr = tp->mmio_addr; 1645 int i; 1646 u8 tmp8; 1647 1648 napi_disable(&tp->napi); 1649 netif_stop_queue(dev); 1650 synchronize_rcu(); 1651 1652 netdev_dbg(dev, "Transmit timeout, status %02x %04x %04x media %02x\n", 1653 RTL_R8(ChipCmd), RTL_R16(IntrStatus), 1654 RTL_R16(IntrMask), RTL_R8(MediaStatus)); 1655 /* Emit info to figure out what went wrong. */ 1656 netdev_dbg(dev, "Tx queue start entry %ld dirty entry %ld\n", 1657 tp->cur_tx, tp->dirty_tx); 1658 for (i = 0; i < NUM_TX_DESC; i++) 1659 netdev_dbg(dev, "Tx descriptor %d is %08x%s\n", 1660 i, RTL_R32(TxStatus0 + (i * 4)), 1661 i == tp->dirty_tx % NUM_TX_DESC ? 1662 " (queue head)" : ""); 1663 1664 tp->xstats.tx_timeouts++; 1665 1666 /* disable Tx ASAP, if not already */ 1667 tmp8 = RTL_R8 (ChipCmd); 1668 if (tmp8 & CmdTxEnb) 1669 RTL_W8 (ChipCmd, CmdRxEnb); 1670 1671 netdev_lock(dev); 1672 spin_lock_bh(&tp->rx_lock); 1673 /* Disable interrupts by clearing the interrupt mask. */ 1674 RTL_W16 (IntrMask, 0x0000); 1675 1676 /* Stop a shared interrupt from scavenging while we are. */ 1677 spin_lock_irq(&tp->lock); 1678 rtl8139_tx_clear (tp); 1679 spin_unlock_irq(&tp->lock); 1680 1681 /* ...and finally, reset everything */ 1682 napi_enable_locked(&tp->napi); 1683 rtl8139_hw_start(dev); 1684 netif_wake_queue(dev); 1685 1686 spin_unlock_bh(&tp->rx_lock); 1687 netdev_unlock(dev); 1688 } 1689 1690 static void rtl8139_tx_timeout(struct net_device *dev, unsigned int txqueue) 1691 { 1692 struct rtl8139_private *tp = netdev_priv(dev); 1693 1694 tp->watchdog_fired = 1; 1695 if (!tp->have_thread) { 1696 INIT_DELAYED_WORK(&tp->thread, rtl8139_thread); 1697 schedule_delayed_work(&tp->thread, next_tick); 1698 } 1699 } 1700 1701 static netdev_tx_t rtl8139_start_xmit (struct sk_buff *skb, 1702 struct net_device *dev) 1703 { 1704 struct rtl8139_private *tp = netdev_priv(dev); 1705 void __iomem *ioaddr = tp->mmio_addr; 1706 unsigned int entry; 1707 unsigned int len = skb->len; 1708 unsigned long flags; 1709 1710 /* Calculate the next Tx descriptor entry. */ 1711 entry = tp->cur_tx % NUM_TX_DESC; 1712 1713 /* Note: the chip doesn't have auto-pad! */ 1714 if (likely(len < TX_BUF_SIZE)) { 1715 if (len < ETH_ZLEN) 1716 memset(tp->tx_buf[entry], 0, ETH_ZLEN); 1717 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]); 1718 dev_kfree_skb_any(skb); 1719 } else { 1720 dev_kfree_skb_any(skb); 1721 dev->stats.tx_dropped++; 1722 return NETDEV_TX_OK; 1723 } 1724 1725 spin_lock_irqsave(&tp->lock, flags); 1726 /* 1727 * Writing to TxStatus triggers a DMA transfer of the data 1728 * copied to tp->tx_buf[entry] above. Use a memory barrier 1729 * to make sure that the device sees the updated data. 1730 */ 1731 wmb(); 1732 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)), 1733 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN)); 1734 1735 tp->cur_tx++; 1736 1737 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) 1738 netif_stop_queue (dev); 1739 spin_unlock_irqrestore(&tp->lock, flags); 1740 1741 netif_dbg(tp, tx_queued, dev, "Queued Tx packet size %u to slot %d\n", 1742 len, entry); 1743 1744 return NETDEV_TX_OK; 1745 } 1746 1747 1748 static void rtl8139_tx_interrupt (struct net_device *dev, 1749 struct rtl8139_private *tp, 1750 void __iomem *ioaddr) 1751 { 1752 unsigned long dirty_tx, tx_left; 1753 1754 assert (dev != NULL); 1755 assert (ioaddr != NULL); 1756 1757 dirty_tx = tp->dirty_tx; 1758 tx_left = tp->cur_tx - dirty_tx; 1759 while (tx_left > 0) { 1760 int entry = dirty_tx % NUM_TX_DESC; 1761 int txstatus; 1762 1763 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32))); 1764 1765 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted))) 1766 break; /* It still hasn't been Txed */ 1767 1768 /* Note: TxCarrierLost is always asserted at 100mbps. */ 1769 if (txstatus & (TxOutOfWindow | TxAborted)) { 1770 /* There was an major error, log it. */ 1771 netif_dbg(tp, tx_err, dev, "Transmit error, Tx status %08x\n", 1772 txstatus); 1773 dev->stats.tx_errors++; 1774 if (txstatus & TxAborted) { 1775 dev->stats.tx_aborted_errors++; 1776 RTL_W32 (TxConfig, TxClearAbt); 1777 RTL_W16 (IntrStatus, TxErr); 1778 wmb(); 1779 } 1780 if (txstatus & TxCarrierLost) 1781 dev->stats.tx_carrier_errors++; 1782 if (txstatus & TxOutOfWindow) 1783 dev->stats.tx_window_errors++; 1784 } else { 1785 if (txstatus & TxUnderrun) { 1786 /* Add 64 to the Tx FIFO threshold. */ 1787 if (tp->tx_flag < 0x00300000) 1788 tp->tx_flag += 0x00020000; 1789 dev->stats.tx_fifo_errors++; 1790 } 1791 dev->stats.collisions += (txstatus >> 24) & 15; 1792 u64_stats_update_begin(&tp->tx_stats.syncp); 1793 tp->tx_stats.packets++; 1794 tp->tx_stats.bytes += txstatus & 0x7ff; 1795 u64_stats_update_end(&tp->tx_stats.syncp); 1796 } 1797 1798 dirty_tx++; 1799 tx_left--; 1800 } 1801 1802 #ifndef RTL8139_NDEBUG 1803 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) { 1804 netdev_err(dev, "Out-of-sync dirty pointer, %ld vs. %ld\n", 1805 dirty_tx, tp->cur_tx); 1806 dirty_tx += NUM_TX_DESC; 1807 } 1808 #endif /* RTL8139_NDEBUG */ 1809 1810 /* only wake the queue if we did work, and the queue is stopped */ 1811 if (tp->dirty_tx != dirty_tx) { 1812 tp->dirty_tx = dirty_tx; 1813 mb(); 1814 netif_wake_queue (dev); 1815 } 1816 } 1817 1818 1819 /* TODO: clean this up! Rx reset need not be this intensive */ 1820 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev, 1821 struct rtl8139_private *tp, void __iomem *ioaddr) 1822 { 1823 u8 tmp8; 1824 #ifdef CONFIG_8139_OLD_RX_RESET 1825 int tmp_work; 1826 #endif 1827 1828 netif_dbg(tp, rx_err, dev, "Ethernet frame had errors, status %08x\n", 1829 rx_status); 1830 dev->stats.rx_errors++; 1831 if (!(rx_status & RxStatusOK)) { 1832 if (rx_status & RxTooLong) { 1833 netdev_dbg(dev, "Oversized Ethernet frame, status %04x!\n", 1834 rx_status); 1835 /* A.C.: The chip hangs here. */ 1836 } 1837 if (rx_status & (RxBadSymbol | RxBadAlign)) 1838 dev->stats.rx_frame_errors++; 1839 if (rx_status & (RxRunt | RxTooLong)) 1840 dev->stats.rx_length_errors++; 1841 if (rx_status & RxCRCErr) 1842 dev->stats.rx_crc_errors++; 1843 } else { 1844 tp->xstats.rx_lost_in_ring++; 1845 } 1846 1847 #ifndef CONFIG_8139_OLD_RX_RESET 1848 tmp8 = RTL_R8 (ChipCmd); 1849 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb); 1850 RTL_W8 (ChipCmd, tmp8); 1851 RTL_W32 (RxConfig, tp->rx_config); 1852 tp->cur_rx = 0; 1853 #else 1854 /* Reset the receiver, based on RealTek recommendation. (Bug?) */ 1855 1856 /* disable receive */ 1857 RTL_W8_F (ChipCmd, CmdTxEnb); 1858 tmp_work = 200; 1859 while (--tmp_work > 0) { 1860 udelay(1); 1861 tmp8 = RTL_R8 (ChipCmd); 1862 if (!(tmp8 & CmdRxEnb)) 1863 break; 1864 } 1865 if (tmp_work <= 0) 1866 netdev_warn(dev, "rx stop wait too long\n"); 1867 /* restart receive */ 1868 tmp_work = 200; 1869 while (--tmp_work > 0) { 1870 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb); 1871 udelay(1); 1872 tmp8 = RTL_R8 (ChipCmd); 1873 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb)) 1874 break; 1875 } 1876 if (tmp_work <= 0) 1877 netdev_warn(dev, "tx/rx enable wait too long\n"); 1878 1879 /* and reinitialize all rx related registers */ 1880 RTL_W8_F (Cfg9346, Cfg9346_Unlock); 1881 /* Must enable Tx/Rx before setting transfer thresholds! */ 1882 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb); 1883 1884 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys; 1885 RTL_W32 (RxConfig, tp->rx_config); 1886 tp->cur_rx = 0; 1887 1888 netdev_dbg(dev, "init buffer addresses\n"); 1889 1890 /* Lock Config[01234] and BMCR register writes */ 1891 RTL_W8 (Cfg9346, Cfg9346_Lock); 1892 1893 /* init Rx ring buffer DMA address */ 1894 RTL_W32_F (RxBuf, tp->rx_ring_dma); 1895 1896 /* A.C.: Reset the multicast list. */ 1897 __set_rx_mode (dev); 1898 #endif 1899 } 1900 1901 #if RX_BUF_IDX == 3 1902 static inline void wrap_copy(struct sk_buff *skb, const unsigned char *ring, 1903 u32 offset, unsigned int size) 1904 { 1905 u32 left = RX_BUF_LEN - offset; 1906 1907 if (size > left) { 1908 skb_copy_to_linear_data(skb, ring + offset, left); 1909 skb_copy_to_linear_data_offset(skb, left, ring, size - left); 1910 } else 1911 skb_copy_to_linear_data(skb, ring + offset, size); 1912 } 1913 #endif 1914 1915 static void rtl8139_isr_ack(struct rtl8139_private *tp) 1916 { 1917 void __iomem *ioaddr = tp->mmio_addr; 1918 u16 status; 1919 1920 status = RTL_R16 (IntrStatus) & RxAckBits; 1921 1922 /* Clear out errors and receive interrupts */ 1923 if (likely(status != 0)) { 1924 if (unlikely(status & (RxFIFOOver | RxOverflow))) { 1925 tp->dev->stats.rx_errors++; 1926 if (status & RxFIFOOver) 1927 tp->dev->stats.rx_fifo_errors++; 1928 } 1929 RTL_W16_F (IntrStatus, RxAckBits); 1930 } 1931 } 1932 1933 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp, 1934 int budget) 1935 { 1936 void __iomem *ioaddr = tp->mmio_addr; 1937 int received = 0; 1938 unsigned char *rx_ring = tp->rx_ring; 1939 unsigned int cur_rx = tp->cur_rx; 1940 unsigned int rx_size = 0; 1941 1942 netdev_dbg(dev, "In %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 1943 __func__, (u16)cur_rx, 1944 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 1945 1946 while (netif_running(dev) && received < budget && 1947 (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) { 1948 u32 ring_offset = cur_rx % RX_BUF_LEN; 1949 u32 rx_status; 1950 unsigned int pkt_size; 1951 struct sk_buff *skb; 1952 1953 rmb(); 1954 1955 /* read size+status of next frame from DMA ring buffer */ 1956 rx_status = le32_to_cpu (*(__le32 *) (rx_ring + ring_offset)); 1957 rx_size = rx_status >> 16; 1958 if (likely(!(dev->features & NETIF_F_RXFCS))) 1959 pkt_size = rx_size - 4; 1960 else 1961 pkt_size = rx_size; 1962 1963 netif_dbg(tp, rx_status, dev, "%s() status %04x, size %04x, cur %04x\n", 1964 __func__, rx_status, rx_size, cur_rx); 1965 #if RTL8139_DEBUG > 2 1966 print_hex_dump(KERN_DEBUG, "Frame contents: ", 1967 DUMP_PREFIX_OFFSET, 16, 1, 1968 &rx_ring[ring_offset], 70, true); 1969 #endif 1970 1971 /* Packet copy from FIFO still in progress. 1972 * Theoretically, this should never happen 1973 * since EarlyRx is disabled. 1974 */ 1975 if (unlikely(rx_size == 0xfff0)) { 1976 if (!tp->fifo_copy_timeout) 1977 tp->fifo_copy_timeout = jiffies + 2; 1978 else if (time_after(jiffies, tp->fifo_copy_timeout)) { 1979 netdev_dbg(dev, "hung FIFO. Reset\n"); 1980 rx_size = 0; 1981 goto no_early_rx; 1982 } 1983 netif_dbg(tp, intr, dev, "fifo copy in progress\n"); 1984 tp->xstats.early_rx++; 1985 break; 1986 } 1987 1988 no_early_rx: 1989 tp->fifo_copy_timeout = 0; 1990 1991 /* If Rx err or invalid rx_size/rx_status received 1992 * (which happens if we get lost in the ring), 1993 * Rx process gets reset, so we abort any further 1994 * Rx processing. 1995 */ 1996 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) || 1997 (rx_size < 8) || 1998 (!(rx_status & RxStatusOK)))) { 1999 if ((dev->features & NETIF_F_RXALL) && 2000 (rx_size <= (MAX_ETH_FRAME_SIZE + 4)) && 2001 (rx_size >= 8) && 2002 (!(rx_status & RxStatusOK))) { 2003 /* Length is at least mostly OK, but pkt has 2004 * error. I'm hoping we can handle some of these 2005 * errors without resetting the chip. --Ben 2006 */ 2007 dev->stats.rx_errors++; 2008 if (rx_status & RxCRCErr) { 2009 dev->stats.rx_crc_errors++; 2010 goto keep_pkt; 2011 } 2012 if (rx_status & RxRunt) { 2013 dev->stats.rx_length_errors++; 2014 goto keep_pkt; 2015 } 2016 } 2017 rtl8139_rx_err (rx_status, dev, tp, ioaddr); 2018 received = -1; 2019 goto out; 2020 } 2021 2022 keep_pkt: 2023 /* Malloc up new buffer, compatible with net-2e. */ 2024 /* Omit the four octet CRC from the length. */ 2025 2026 skb = napi_alloc_skb(&tp->napi, pkt_size); 2027 if (likely(skb)) { 2028 #if RX_BUF_IDX == 3 2029 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size); 2030 #else 2031 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size); 2032 #endif 2033 skb_put (skb, pkt_size); 2034 2035 skb->protocol = eth_type_trans (skb, dev); 2036 2037 u64_stats_update_begin(&tp->rx_stats.syncp); 2038 tp->rx_stats.packets++; 2039 tp->rx_stats.bytes += pkt_size; 2040 u64_stats_update_end(&tp->rx_stats.syncp); 2041 2042 netif_receive_skb (skb); 2043 } else { 2044 dev->stats.rx_dropped++; 2045 } 2046 received++; 2047 2048 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 2049 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16)); 2050 2051 rtl8139_isr_ack(tp); 2052 } 2053 2054 if (unlikely(!received || rx_size == 0xfff0)) 2055 rtl8139_isr_ack(tp); 2056 2057 netdev_dbg(dev, "Done %s(), current %04x BufAddr %04x, free to %04x, Cmd %02x\n", 2058 __func__, cur_rx, 2059 RTL_R16(RxBufAddr), RTL_R16(RxBufPtr), RTL_R8(ChipCmd)); 2060 2061 tp->cur_rx = cur_rx; 2062 2063 /* 2064 * The receive buffer should be mostly empty. 2065 * Tell NAPI to reenable the Rx irq. 2066 */ 2067 if (tp->fifo_copy_timeout) 2068 received = budget; 2069 2070 out: 2071 return received; 2072 } 2073 2074 2075 static void rtl8139_weird_interrupt (struct net_device *dev, 2076 struct rtl8139_private *tp, 2077 void __iomem *ioaddr, 2078 int status, int link_changed) 2079 { 2080 netdev_dbg(dev, "Abnormal interrupt, status %08x\n", status); 2081 2082 assert (dev != NULL); 2083 assert (tp != NULL); 2084 assert (ioaddr != NULL); 2085 2086 /* Update the error count. */ 2087 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2088 RTL_W32 (RxMissed, 0); 2089 2090 if ((status & RxUnderrun) && link_changed && 2091 (tp->drv_flags & HAS_LNK_CHNG)) { 2092 rtl_check_media(dev, 0); 2093 status &= ~RxUnderrun; 2094 } 2095 2096 if (status & (RxUnderrun | RxErr)) 2097 dev->stats.rx_errors++; 2098 2099 if (status & PCSTimeout) 2100 dev->stats.rx_length_errors++; 2101 if (status & RxUnderrun) 2102 dev->stats.rx_fifo_errors++; 2103 if (status & PCIErr) { 2104 u16 pci_cmd_status; 2105 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status); 2106 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status); 2107 2108 netdev_err(dev, "PCI Bus error %04x\n", pci_cmd_status); 2109 } 2110 } 2111 2112 static int rtl8139_poll(struct napi_struct *napi, int budget) 2113 { 2114 struct rtl8139_private *tp = container_of(napi, struct rtl8139_private, napi); 2115 struct net_device *dev = tp->dev; 2116 void __iomem *ioaddr = tp->mmio_addr; 2117 int work_done; 2118 2119 spin_lock(&tp->rx_lock); 2120 work_done = 0; 2121 if (likely(RTL_R16(IntrStatus) & RxAckBits)) 2122 work_done += rtl8139_rx(dev, tp, budget); 2123 2124 if (work_done < budget) { 2125 unsigned long flags; 2126 2127 spin_lock_irqsave(&tp->lock, flags); 2128 if (napi_complete_done(napi, work_done)) 2129 RTL_W16_F(IntrMask, rtl8139_intr_mask); 2130 spin_unlock_irqrestore(&tp->lock, flags); 2131 } 2132 spin_unlock(&tp->rx_lock); 2133 2134 return work_done; 2135 } 2136 2137 /* The interrupt handler does all of the Rx thread work and cleans up 2138 after the Tx thread. */ 2139 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance) 2140 { 2141 struct net_device *dev = (struct net_device *) dev_instance; 2142 struct rtl8139_private *tp = netdev_priv(dev); 2143 void __iomem *ioaddr = tp->mmio_addr; 2144 u16 status, ackstat; 2145 int link_changed = 0; /* avoid bogus "uninit" warning */ 2146 int handled = 0; 2147 2148 spin_lock (&tp->lock); 2149 status = RTL_R16 (IntrStatus); 2150 2151 /* shared irq? */ 2152 if (unlikely((status & rtl8139_intr_mask) == 0)) 2153 goto out; 2154 2155 handled = 1; 2156 2157 /* h/w no longer present (hotplug?) or major error, bail */ 2158 if (unlikely(status == 0xFFFF)) 2159 goto out; 2160 2161 /* close possible race's with dev_close */ 2162 if (unlikely(!netif_running(dev))) { 2163 RTL_W16 (IntrMask, 0); 2164 goto out; 2165 } 2166 2167 /* Acknowledge all of the current interrupt sources ASAP, but 2168 an first get an additional status bit from CSCR. */ 2169 if (unlikely(status & RxUnderrun)) 2170 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit; 2171 2172 ackstat = status & ~(RxAckBits | TxErr); 2173 if (ackstat) 2174 RTL_W16 (IntrStatus, ackstat); 2175 2176 /* Receive packets are processed by poll routine. 2177 If not running start it now. */ 2178 if (status & RxAckBits){ 2179 if (napi_schedule_prep(&tp->napi)) { 2180 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask); 2181 __napi_schedule(&tp->napi); 2182 } 2183 } 2184 2185 /* Check uncommon events with one test. */ 2186 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr))) 2187 rtl8139_weird_interrupt (dev, tp, ioaddr, 2188 status, link_changed); 2189 2190 if (status & (TxOK | TxErr)) { 2191 rtl8139_tx_interrupt (dev, tp, ioaddr); 2192 if (status & TxErr) 2193 RTL_W16 (IntrStatus, TxErr); 2194 } 2195 out: 2196 spin_unlock (&tp->lock); 2197 2198 netdev_dbg(dev, "exiting interrupt, intr_status=%#4.4x\n", 2199 RTL_R16(IntrStatus)); 2200 return IRQ_RETVAL(handled); 2201 } 2202 2203 #ifdef CONFIG_NET_POLL_CONTROLLER 2204 /* 2205 * Polling receive - used by netconsole and other diagnostic tools 2206 * to allow network i/o with interrupts disabled. 2207 */ 2208 static void rtl8139_poll_controller(struct net_device *dev) 2209 { 2210 struct rtl8139_private *tp = netdev_priv(dev); 2211 const int irq = tp->pci_dev->irq; 2212 2213 disable_irq_nosync(irq); 2214 rtl8139_interrupt(irq, dev); 2215 enable_irq(irq); 2216 } 2217 #endif 2218 2219 static int rtl8139_set_mac_address(struct net_device *dev, void *p) 2220 { 2221 struct rtl8139_private *tp = netdev_priv(dev); 2222 void __iomem *ioaddr = tp->mmio_addr; 2223 struct sockaddr *addr = p; 2224 2225 if (!is_valid_ether_addr(addr->sa_data)) 2226 return -EADDRNOTAVAIL; 2227 2228 eth_hw_addr_set(dev, addr->sa_data); 2229 2230 spin_lock_irq(&tp->lock); 2231 2232 RTL_W8_F(Cfg9346, Cfg9346_Unlock); 2233 RTL_W32_F(MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0))); 2234 RTL_W32_F(MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4))); 2235 RTL_W8_F(Cfg9346, Cfg9346_Lock); 2236 2237 spin_unlock_irq(&tp->lock); 2238 2239 return 0; 2240 } 2241 2242 static int rtl8139_close (struct net_device *dev) 2243 { 2244 struct rtl8139_private *tp = netdev_priv(dev); 2245 void __iomem *ioaddr = tp->mmio_addr; 2246 unsigned long flags; 2247 2248 netif_stop_queue(dev); 2249 napi_disable(&tp->napi); 2250 2251 netif_dbg(tp, ifdown, dev, "Shutting down ethercard, status was 0x%04x\n", 2252 RTL_R16(IntrStatus)); 2253 2254 spin_lock_irqsave (&tp->lock, flags); 2255 2256 /* Stop the chip's Tx and Rx DMA processes. */ 2257 RTL_W8 (ChipCmd, 0); 2258 2259 /* Disable interrupts by clearing the interrupt mask. */ 2260 RTL_W16 (IntrMask, 0); 2261 2262 /* Update the error counts. */ 2263 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2264 RTL_W32 (RxMissed, 0); 2265 2266 spin_unlock_irqrestore (&tp->lock, flags); 2267 2268 free_irq(tp->pci_dev->irq, dev); 2269 2270 rtl8139_tx_clear (tp); 2271 2272 dma_free_coherent(&tp->pci_dev->dev, RX_BUF_TOT_LEN, 2273 tp->rx_ring, tp->rx_ring_dma); 2274 dma_free_coherent(&tp->pci_dev->dev, TX_BUF_TOT_LEN, 2275 tp->tx_bufs, tp->tx_bufs_dma); 2276 tp->rx_ring = NULL; 2277 tp->tx_bufs = NULL; 2278 2279 /* Green! Put the chip in low-power mode. */ 2280 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2281 2282 if (rtl_chip_info[tp->chipset].flags & HasHltClk) 2283 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */ 2284 2285 return 0; 2286 } 2287 2288 2289 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to 2290 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and 2291 other threads or interrupts aren't messing with the 8139. */ 2292 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2293 { 2294 struct rtl8139_private *tp = netdev_priv(dev); 2295 void __iomem *ioaddr = tp->mmio_addr; 2296 2297 spin_lock_irq(&tp->lock); 2298 if (rtl_chip_info[tp->chipset].flags & HasLWake) { 2299 u8 cfg3 = RTL_R8 (Config3); 2300 u8 cfg5 = RTL_R8 (Config5); 2301 2302 wol->supported = WAKE_PHY | WAKE_MAGIC 2303 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; 2304 2305 wol->wolopts = 0; 2306 if (cfg3 & Cfg3_LinkUp) 2307 wol->wolopts |= WAKE_PHY; 2308 if (cfg3 & Cfg3_Magic) 2309 wol->wolopts |= WAKE_MAGIC; 2310 /* (KON)FIXME: See how netdev_set_wol() handles the 2311 following constants. */ 2312 if (cfg5 & Cfg5_UWF) 2313 wol->wolopts |= WAKE_UCAST; 2314 if (cfg5 & Cfg5_MWF) 2315 wol->wolopts |= WAKE_MCAST; 2316 if (cfg5 & Cfg5_BWF) 2317 wol->wolopts |= WAKE_BCAST; 2318 } 2319 spin_unlock_irq(&tp->lock); 2320 } 2321 2322 2323 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes 2324 that wol points to kernel memory and other threads or interrupts 2325 aren't messing with the 8139. */ 2326 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2327 { 2328 struct rtl8139_private *tp = netdev_priv(dev); 2329 void __iomem *ioaddr = tp->mmio_addr; 2330 u32 support; 2331 u8 cfg3, cfg5; 2332 2333 support = ((rtl_chip_info[tp->chipset].flags & HasLWake) 2334 ? (WAKE_PHY | WAKE_MAGIC 2335 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST) 2336 : 0); 2337 if (wol->wolopts & ~support) 2338 return -EINVAL; 2339 2340 spin_lock_irq(&tp->lock); 2341 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic); 2342 if (wol->wolopts & WAKE_PHY) 2343 cfg3 |= Cfg3_LinkUp; 2344 if (wol->wolopts & WAKE_MAGIC) 2345 cfg3 |= Cfg3_Magic; 2346 RTL_W8 (Cfg9346, Cfg9346_Unlock); 2347 RTL_W8 (Config3, cfg3); 2348 RTL_W8 (Cfg9346, Cfg9346_Lock); 2349 2350 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF); 2351 /* (KON)FIXME: These are untested. We may have to set the 2352 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no 2353 documentation. */ 2354 if (wol->wolopts & WAKE_UCAST) 2355 cfg5 |= Cfg5_UWF; 2356 if (wol->wolopts & WAKE_MCAST) 2357 cfg5 |= Cfg5_MWF; 2358 if (wol->wolopts & WAKE_BCAST) 2359 cfg5 |= Cfg5_BWF; 2360 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */ 2361 spin_unlock_irq(&tp->lock); 2362 2363 return 0; 2364 } 2365 2366 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2367 { 2368 struct rtl8139_private *tp = netdev_priv(dev); 2369 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 2370 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 2371 } 2372 2373 static int rtl8139_get_link_ksettings(struct net_device *dev, 2374 struct ethtool_link_ksettings *cmd) 2375 { 2376 struct rtl8139_private *tp = netdev_priv(dev); 2377 spin_lock_irq(&tp->lock); 2378 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 2379 spin_unlock_irq(&tp->lock); 2380 return 0; 2381 } 2382 2383 static int rtl8139_set_link_ksettings(struct net_device *dev, 2384 const struct ethtool_link_ksettings *cmd) 2385 { 2386 struct rtl8139_private *tp = netdev_priv(dev); 2387 int rc; 2388 spin_lock_irq(&tp->lock); 2389 rc = mii_ethtool_set_link_ksettings(&tp->mii, cmd); 2390 spin_unlock_irq(&tp->lock); 2391 return rc; 2392 } 2393 2394 static int rtl8139_nway_reset(struct net_device *dev) 2395 { 2396 struct rtl8139_private *tp = netdev_priv(dev); 2397 return mii_nway_restart(&tp->mii); 2398 } 2399 2400 static u32 rtl8139_get_link(struct net_device *dev) 2401 { 2402 struct rtl8139_private *tp = netdev_priv(dev); 2403 return mii_link_ok(&tp->mii); 2404 } 2405 2406 static u32 rtl8139_get_msglevel(struct net_device *dev) 2407 { 2408 struct rtl8139_private *tp = netdev_priv(dev); 2409 return tp->msg_enable; 2410 } 2411 2412 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum) 2413 { 2414 struct rtl8139_private *tp = netdev_priv(dev); 2415 tp->msg_enable = datum; 2416 } 2417 2418 static int rtl8139_get_regs_len(struct net_device *dev) 2419 { 2420 struct rtl8139_private *tp; 2421 /* TODO: we are too slack to do reg dumping for pio, for now */ 2422 if (use_io) 2423 return 0; 2424 tp = netdev_priv(dev); 2425 return tp->regs_len; 2426 } 2427 2428 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf) 2429 { 2430 struct rtl8139_private *tp; 2431 2432 /* TODO: we are too slack to do reg dumping for pio, for now */ 2433 if (use_io) 2434 return; 2435 tp = netdev_priv(dev); 2436 2437 regs->version = RTL_REGS_VER; 2438 2439 spin_lock_irq(&tp->lock); 2440 memcpy_fromio(regbuf, tp->mmio_addr, regs->len); 2441 spin_unlock_irq(&tp->lock); 2442 } 2443 2444 static int rtl8139_get_sset_count(struct net_device *dev, int sset) 2445 { 2446 switch (sset) { 2447 case ETH_SS_STATS: 2448 return RTL_NUM_STATS; 2449 default: 2450 return -EOPNOTSUPP; 2451 } 2452 } 2453 2454 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) 2455 { 2456 struct rtl8139_private *tp = netdev_priv(dev); 2457 2458 data[0] = tp->xstats.early_rx; 2459 data[1] = tp->xstats.tx_buf_mapped; 2460 data[2] = tp->xstats.tx_timeouts; 2461 data[3] = tp->xstats.rx_lost_in_ring; 2462 } 2463 2464 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2465 { 2466 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); 2467 } 2468 2469 static const struct ethtool_ops rtl8139_ethtool_ops = { 2470 .get_drvinfo = rtl8139_get_drvinfo, 2471 .get_regs_len = rtl8139_get_regs_len, 2472 .get_regs = rtl8139_get_regs, 2473 .nway_reset = rtl8139_nway_reset, 2474 .get_link = rtl8139_get_link, 2475 .get_msglevel = rtl8139_get_msglevel, 2476 .set_msglevel = rtl8139_set_msglevel, 2477 .get_wol = rtl8139_get_wol, 2478 .set_wol = rtl8139_set_wol, 2479 .get_strings = rtl8139_get_strings, 2480 .get_sset_count = rtl8139_get_sset_count, 2481 .get_ethtool_stats = rtl8139_get_ethtool_stats, 2482 .get_link_ksettings = rtl8139_get_link_ksettings, 2483 .set_link_ksettings = rtl8139_set_link_ksettings, 2484 }; 2485 2486 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2487 { 2488 struct rtl8139_private *tp = netdev_priv(dev); 2489 int rc; 2490 2491 if (!netif_running(dev)) 2492 return -EINVAL; 2493 2494 spin_lock_irq(&tp->lock); 2495 rc = generic_mii_ioctl(&tp->mii, if_mii(rq), cmd, NULL); 2496 spin_unlock_irq(&tp->lock); 2497 2498 return rc; 2499 } 2500 2501 2502 static void 2503 rtl8139_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 2504 { 2505 struct rtl8139_private *tp = netdev_priv(dev); 2506 void __iomem *ioaddr = tp->mmio_addr; 2507 unsigned long flags; 2508 unsigned int start; 2509 2510 if (netif_running(dev)) { 2511 spin_lock_irqsave (&tp->lock, flags); 2512 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2513 RTL_W32 (RxMissed, 0); 2514 spin_unlock_irqrestore (&tp->lock, flags); 2515 } 2516 2517 netdev_stats_to_stats64(stats, &dev->stats); 2518 2519 do { 2520 start = u64_stats_fetch_begin(&tp->rx_stats.syncp); 2521 stats->rx_packets = tp->rx_stats.packets; 2522 stats->rx_bytes = tp->rx_stats.bytes; 2523 } while (u64_stats_fetch_retry(&tp->rx_stats.syncp, start)); 2524 2525 do { 2526 start = u64_stats_fetch_begin(&tp->tx_stats.syncp); 2527 stats->tx_packets = tp->tx_stats.packets; 2528 stats->tx_bytes = tp->tx_stats.bytes; 2529 } while (u64_stats_fetch_retry(&tp->tx_stats.syncp, start)); 2530 } 2531 2532 /* Set or clear the multicast filter for this adaptor. 2533 This routine is not state sensitive and need not be SMP locked. */ 2534 2535 static void __set_rx_mode (struct net_device *dev) 2536 { 2537 struct rtl8139_private *tp = netdev_priv(dev); 2538 void __iomem *ioaddr = tp->mmio_addr; 2539 u32 mc_filter[2]; /* Multicast hash filter */ 2540 int rx_mode; 2541 u32 tmp; 2542 2543 netdev_dbg(dev, "rtl8139_set_rx_mode(%04x) done -- Rx config %08x\n", 2544 dev->flags, RTL_R32(RxConfig)); 2545 2546 /* Note: do not reorder, GCC is clever about common statements. */ 2547 if (dev->flags & IFF_PROMISC) { 2548 rx_mode = 2549 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 2550 AcceptAllPhys; 2551 mc_filter[1] = mc_filter[0] = 0xffffffff; 2552 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2553 (dev->flags & IFF_ALLMULTI)) { 2554 /* Too many to filter perfectly -- accept all multicasts. */ 2555 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 2556 mc_filter[1] = mc_filter[0] = 0xffffffff; 2557 } else { 2558 struct netdev_hw_addr *ha; 2559 rx_mode = AcceptBroadcast | AcceptMyPhys; 2560 mc_filter[1] = mc_filter[0] = 0; 2561 netdev_for_each_mc_addr(ha, dev) { 2562 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2563 2564 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2565 rx_mode |= AcceptMulticast; 2566 } 2567 } 2568 2569 if (dev->features & NETIF_F_RXALL) 2570 rx_mode |= (AcceptErr | AcceptRunt); 2571 2572 /* We can safely update without stopping the chip. */ 2573 tmp = rtl8139_rx_config | rx_mode; 2574 if (tp->rx_config != tmp) { 2575 RTL_W32_F (RxConfig, tmp); 2576 tp->rx_config = tmp; 2577 } 2578 RTL_W32_F (MAR0 + 0, mc_filter[0]); 2579 RTL_W32_F (MAR0 + 4, mc_filter[1]); 2580 } 2581 2582 static void rtl8139_set_rx_mode (struct net_device *dev) 2583 { 2584 unsigned long flags; 2585 struct rtl8139_private *tp = netdev_priv(dev); 2586 2587 spin_lock_irqsave (&tp->lock, flags); 2588 __set_rx_mode(dev); 2589 spin_unlock_irqrestore (&tp->lock, flags); 2590 } 2591 2592 static int __maybe_unused rtl8139_suspend(struct device *device) 2593 { 2594 struct net_device *dev = dev_get_drvdata(device); 2595 struct rtl8139_private *tp = netdev_priv(dev); 2596 void __iomem *ioaddr = tp->mmio_addr; 2597 unsigned long flags; 2598 2599 if (!netif_running (dev)) 2600 return 0; 2601 2602 netif_device_detach (dev); 2603 2604 spin_lock_irqsave (&tp->lock, flags); 2605 2606 /* Disable interrupts, stop Tx and Rx. */ 2607 RTL_W16 (IntrMask, 0); 2608 RTL_W8 (ChipCmd, 0); 2609 2610 /* Update the error counts. */ 2611 dev->stats.rx_missed_errors += RTL_R32 (RxMissed); 2612 RTL_W32 (RxMissed, 0); 2613 2614 spin_unlock_irqrestore (&tp->lock, flags); 2615 2616 return 0; 2617 } 2618 2619 static int __maybe_unused rtl8139_resume(struct device *device) 2620 { 2621 struct net_device *dev = dev_get_drvdata(device); 2622 2623 if (!netif_running (dev)) 2624 return 0; 2625 2626 rtl8139_init_ring (dev); 2627 rtl8139_hw_start (dev); 2628 netif_device_attach (dev); 2629 return 0; 2630 } 2631 2632 static SIMPLE_DEV_PM_OPS(rtl8139_pm_ops, rtl8139_suspend, rtl8139_resume); 2633 2634 static struct pci_driver rtl8139_pci_driver = { 2635 .name = DRV_NAME, 2636 .id_table = rtl8139_pci_tbl, 2637 .probe = rtl8139_init_one, 2638 .remove = rtl8139_remove_one, 2639 .driver.pm = &rtl8139_pm_ops, 2640 }; 2641 2642 module_pci_driver(rtl8139_pci_driver); 2643