1 /* 2 * RDC R6040 Fast Ethernet MAC support 3 * 4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw> 5 * Copyright (C) 2007 6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us> 7 * Florian Fainelli <florian@openwrt.org> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 2 12 * of the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the 21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, 22 * Boston, MA 02110-1301, USA. 23 */ 24 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/moduleparam.h> 28 #include <linux/string.h> 29 #include <linux/timer.h> 30 #include <linux/errno.h> 31 #include <linux/ioport.h> 32 #include <linux/interrupt.h> 33 #include <linux/pci.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/skbuff.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/mii.h> 40 #include <linux/ethtool.h> 41 #include <linux/crc32.h> 42 #include <linux/spinlock.h> 43 #include <linux/bitops.h> 44 #include <linux/io.h> 45 #include <linux/irq.h> 46 #include <linux/uaccess.h> 47 #include <linux/phy.h> 48 49 #include <asm/processor.h> 50 51 #define DRV_NAME "r6040" 52 #define DRV_VERSION "0.28" 53 #define DRV_RELDATE "07Oct2011" 54 55 /* PHY CHIP Address */ 56 #define PHY1_ADDR 1 /* For MAC1 */ 57 #define PHY2_ADDR 3 /* For MAC2 */ 58 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */ 59 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */ 60 61 /* Time in jiffies before concluding the transmitter is hung. */ 62 #define TX_TIMEOUT (6000 * HZ / 1000) 63 64 /* RDC MAC I/O Size */ 65 #define R6040_IO_SIZE 256 66 67 /* MAX RDC MAC */ 68 #define MAX_MAC 2 69 70 /* MAC registers */ 71 #define MCR0 0x00 /* Control register 0 */ 72 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */ 73 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */ 74 #define MCR1 0x04 /* Control register 1 */ 75 #define MAC_RST 0x0001 /* Reset the MAC */ 76 #define MBCR 0x08 /* Bus control */ 77 #define MT_ICR 0x0C /* TX interrupt control */ 78 #define MR_ICR 0x10 /* RX interrupt control */ 79 #define MTPR 0x14 /* TX poll command register */ 80 #define MR_BSR 0x18 /* RX buffer size */ 81 #define MR_DCR 0x1A /* RX descriptor control */ 82 #define MLSR 0x1C /* Last status */ 83 #define MMDIO 0x20 /* MDIO control register */ 84 #define MDIO_WRITE 0x4000 /* MDIO write */ 85 #define MDIO_READ 0x2000 /* MDIO read */ 86 #define MMRD 0x24 /* MDIO read data register */ 87 #define MMWD 0x28 /* MDIO write data register */ 88 #define MTD_SA0 0x2C /* TX descriptor start address 0 */ 89 #define MTD_SA1 0x30 /* TX descriptor start address 1 */ 90 #define MRD_SA0 0x34 /* RX descriptor start address 0 */ 91 #define MRD_SA1 0x38 /* RX descriptor start address 1 */ 92 #define MISR 0x3C /* Status register */ 93 #define MIER 0x40 /* INT enable register */ 94 #define MSK_INT 0x0000 /* Mask off interrupts */ 95 #define RX_FINISH 0x0001 /* RX finished */ 96 #define RX_NO_DESC 0x0002 /* No RX descriptor available */ 97 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */ 98 #define RX_EARLY 0x0008 /* RX early */ 99 #define TX_FINISH 0x0010 /* TX finished */ 100 #define TX_EARLY 0x0080 /* TX early */ 101 #define EVENT_OVRFL 0x0100 /* Event counter overflow */ 102 #define LINK_CHANGED 0x0200 /* PHY link changed */ 103 #define ME_CISR 0x44 /* Event counter INT status */ 104 #define ME_CIER 0x48 /* Event counter INT enable */ 105 #define MR_CNT 0x50 /* Successfully received packet counter */ 106 #define ME_CNT0 0x52 /* Event counter 0 */ 107 #define ME_CNT1 0x54 /* Event counter 1 */ 108 #define ME_CNT2 0x56 /* Event counter 2 */ 109 #define ME_CNT3 0x58 /* Event counter 3 */ 110 #define MT_CNT 0x5A /* Successfully transmit packet counter */ 111 #define ME_CNT4 0x5C /* Event counter 4 */ 112 #define MP_CNT 0x5E /* Pause frame counter register */ 113 #define MAR0 0x60 /* Hash table 0 */ 114 #define MAR1 0x62 /* Hash table 1 */ 115 #define MAR2 0x64 /* Hash table 2 */ 116 #define MAR3 0x66 /* Hash table 3 */ 117 #define MID_0L 0x68 /* Multicast address MID0 Low */ 118 #define MID_0M 0x6A /* Multicast address MID0 Medium */ 119 #define MID_0H 0x6C /* Multicast address MID0 High */ 120 #define MID_1L 0x70 /* MID1 Low */ 121 #define MID_1M 0x72 /* MID1 Medium */ 122 #define MID_1H 0x74 /* MID1 High */ 123 #define MID_2L 0x78 /* MID2 Low */ 124 #define MID_2M 0x7A /* MID2 Medium */ 125 #define MID_2H 0x7C /* MID2 High */ 126 #define MID_3L 0x80 /* MID3 Low */ 127 #define MID_3M 0x82 /* MID3 Medium */ 128 #define MID_3H 0x84 /* MID3 High */ 129 #define PHY_CC 0x88 /* PHY status change configuration register */ 130 #define PHY_ST 0x8A /* PHY status register */ 131 #define MAC_SM 0xAC /* MAC status machine */ 132 #define MAC_ID 0xBE /* Identifier register */ 133 134 #define TX_DCNT 0x80 /* TX descriptor count */ 135 #define RX_DCNT 0x80 /* RX descriptor count */ 136 #define MAX_BUF_SIZE 0x600 137 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor)) 138 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor)) 139 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */ 140 #define MCAST_MAX 3 /* Max number multicast addresses to filter */ 141 142 /* Descriptor status */ 143 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */ 144 #define DSC_RX_OK 0x4000 /* RX was successful */ 145 #define DSC_RX_ERR 0x0800 /* RX PHY error */ 146 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */ 147 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */ 148 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */ 149 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */ 150 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */ 151 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */ 152 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */ 153 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */ 154 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */ 155 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */ 156 157 /* PHY settings */ 158 #define ICPLUS_PHY_ID 0x0243 159 160 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>," 161 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>," 162 "Florian Fainelli <florian@openwrt.org>"); 163 MODULE_LICENSE("GPL"); 164 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver"); 165 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE); 166 167 /* RX and TX interrupts that we handle */ 168 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH) 169 #define TX_INTS (TX_FINISH) 170 #define INT_MASK (RX_INTS | TX_INTS) 171 172 struct r6040_descriptor { 173 u16 status, len; /* 0-3 */ 174 __le32 buf; /* 4-7 */ 175 __le32 ndesc; /* 8-B */ 176 u32 rev1; /* C-F */ 177 char *vbufp; /* 10-13 */ 178 struct r6040_descriptor *vndescp; /* 14-17 */ 179 struct sk_buff *skb_ptr; /* 18-1B */ 180 u32 rev2; /* 1C-1F */ 181 } __attribute__((aligned(32))); 182 183 struct r6040_private { 184 spinlock_t lock; /* driver lock */ 185 struct pci_dev *pdev; 186 struct r6040_descriptor *rx_insert_ptr; 187 struct r6040_descriptor *rx_remove_ptr; 188 struct r6040_descriptor *tx_insert_ptr; 189 struct r6040_descriptor *tx_remove_ptr; 190 struct r6040_descriptor *rx_ring; 191 struct r6040_descriptor *tx_ring; 192 dma_addr_t rx_ring_dma; 193 dma_addr_t tx_ring_dma; 194 u16 tx_free_desc, phy_addr; 195 u16 mcr0, mcr1; 196 struct net_device *dev; 197 struct mii_bus *mii_bus; 198 struct napi_struct napi; 199 void __iomem *base; 200 struct phy_device *phydev; 201 int old_link; 202 int old_duplex; 203 }; 204 205 static char version[] __devinitdata = DRV_NAME 206 ": RDC R6040 NAPI net driver," 207 "version "DRV_VERSION " (" DRV_RELDATE ")"; 208 209 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR }; 210 211 /* Read a word data from PHY Chip */ 212 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg) 213 { 214 int limit = 2048; 215 u16 cmd; 216 217 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO); 218 /* Wait for the read bit to be cleared */ 219 while (limit--) { 220 cmd = ioread16(ioaddr + MMDIO); 221 if (!(cmd & MDIO_READ)) 222 break; 223 } 224 225 return ioread16(ioaddr + MMRD); 226 } 227 228 /* Write a word data from PHY Chip */ 229 static void r6040_phy_write(void __iomem *ioaddr, 230 int phy_addr, int reg, u16 val) 231 { 232 int limit = 2048; 233 u16 cmd; 234 235 iowrite16(val, ioaddr + MMWD); 236 /* Write the command to the MDIO bus */ 237 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO); 238 /* Wait for the write bit to be cleared */ 239 while (limit--) { 240 cmd = ioread16(ioaddr + MMDIO); 241 if (!(cmd & MDIO_WRITE)) 242 break; 243 } 244 } 245 246 static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg) 247 { 248 struct net_device *dev = bus->priv; 249 struct r6040_private *lp = netdev_priv(dev); 250 void __iomem *ioaddr = lp->base; 251 252 return r6040_phy_read(ioaddr, phy_addr, reg); 253 } 254 255 static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr, 256 int reg, u16 value) 257 { 258 struct net_device *dev = bus->priv; 259 struct r6040_private *lp = netdev_priv(dev); 260 void __iomem *ioaddr = lp->base; 261 262 r6040_phy_write(ioaddr, phy_addr, reg, value); 263 264 return 0; 265 } 266 267 static int r6040_mdiobus_reset(struct mii_bus *bus) 268 { 269 return 0; 270 } 271 272 static void r6040_free_txbufs(struct net_device *dev) 273 { 274 struct r6040_private *lp = netdev_priv(dev); 275 int i; 276 277 for (i = 0; i < TX_DCNT; i++) { 278 if (lp->tx_insert_ptr->skb_ptr) { 279 pci_unmap_single(lp->pdev, 280 le32_to_cpu(lp->tx_insert_ptr->buf), 281 MAX_BUF_SIZE, PCI_DMA_TODEVICE); 282 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr); 283 lp->tx_insert_ptr->skb_ptr = NULL; 284 } 285 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp; 286 } 287 } 288 289 static void r6040_free_rxbufs(struct net_device *dev) 290 { 291 struct r6040_private *lp = netdev_priv(dev); 292 int i; 293 294 for (i = 0; i < RX_DCNT; i++) { 295 if (lp->rx_insert_ptr->skb_ptr) { 296 pci_unmap_single(lp->pdev, 297 le32_to_cpu(lp->rx_insert_ptr->buf), 298 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE); 299 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr); 300 lp->rx_insert_ptr->skb_ptr = NULL; 301 } 302 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp; 303 } 304 } 305 306 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring, 307 dma_addr_t desc_dma, int size) 308 { 309 struct r6040_descriptor *desc = desc_ring; 310 dma_addr_t mapping = desc_dma; 311 312 while (size-- > 0) { 313 mapping += sizeof(*desc); 314 desc->ndesc = cpu_to_le32(mapping); 315 desc->vndescp = desc + 1; 316 desc++; 317 } 318 desc--; 319 desc->ndesc = cpu_to_le32(desc_dma); 320 desc->vndescp = desc_ring; 321 } 322 323 static void r6040_init_txbufs(struct net_device *dev) 324 { 325 struct r6040_private *lp = netdev_priv(dev); 326 327 lp->tx_free_desc = TX_DCNT; 328 329 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring; 330 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT); 331 } 332 333 static int r6040_alloc_rxbufs(struct net_device *dev) 334 { 335 struct r6040_private *lp = netdev_priv(dev); 336 struct r6040_descriptor *desc; 337 struct sk_buff *skb; 338 int rc; 339 340 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring; 341 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT); 342 343 /* Allocate skbs for the rx descriptors */ 344 desc = lp->rx_ring; 345 do { 346 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE); 347 if (!skb) { 348 netdev_err(dev, "failed to alloc skb for rx\n"); 349 rc = -ENOMEM; 350 goto err_exit; 351 } 352 desc->skb_ptr = skb; 353 desc->buf = cpu_to_le32(pci_map_single(lp->pdev, 354 desc->skb_ptr->data, 355 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE)); 356 desc->status = DSC_OWNER_MAC; 357 desc = desc->vndescp; 358 } while (desc != lp->rx_ring); 359 360 return 0; 361 362 err_exit: 363 /* Deallocate all previously allocated skbs */ 364 r6040_free_rxbufs(dev); 365 return rc; 366 } 367 368 static void r6040_init_mac_regs(struct net_device *dev) 369 { 370 struct r6040_private *lp = netdev_priv(dev); 371 void __iomem *ioaddr = lp->base; 372 int limit = 2048; 373 u16 cmd; 374 375 /* Mask Off Interrupt */ 376 iowrite16(MSK_INT, ioaddr + MIER); 377 378 /* Reset RDC MAC */ 379 iowrite16(MAC_RST, ioaddr + MCR1); 380 while (limit--) { 381 cmd = ioread16(ioaddr + MCR1); 382 if (cmd & 0x1) 383 break; 384 } 385 /* Reset internal state machine */ 386 iowrite16(2, ioaddr + MAC_SM); 387 iowrite16(0, ioaddr + MAC_SM); 388 mdelay(5); 389 390 /* MAC Bus Control Register */ 391 iowrite16(MBCR_DEFAULT, ioaddr + MBCR); 392 393 /* Buffer Size Register */ 394 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR); 395 396 /* Write TX ring start address */ 397 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0); 398 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1); 399 400 /* Write RX ring start address */ 401 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0); 402 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1); 403 404 /* Set interrupt waiting time and packet numbers */ 405 iowrite16(0, ioaddr + MT_ICR); 406 iowrite16(0, ioaddr + MR_ICR); 407 408 /* Enable interrupts */ 409 iowrite16(INT_MASK, ioaddr + MIER); 410 411 /* Enable TX and RX */ 412 iowrite16(lp->mcr0 | 0x0002, ioaddr); 413 414 /* Let TX poll the descriptors 415 * we may got called by r6040_tx_timeout which has left 416 * some unsent tx buffers */ 417 iowrite16(0x01, ioaddr + MTPR); 418 } 419 420 static void r6040_tx_timeout(struct net_device *dev) 421 { 422 struct r6040_private *priv = netdev_priv(dev); 423 void __iomem *ioaddr = priv->base; 424 425 netdev_warn(dev, "transmit timed out, int enable %4.4x " 426 "status %4.4x\n", 427 ioread16(ioaddr + MIER), 428 ioread16(ioaddr + MISR)); 429 430 dev->stats.tx_errors++; 431 432 /* Reset MAC and re-init all registers */ 433 r6040_init_mac_regs(dev); 434 } 435 436 static struct net_device_stats *r6040_get_stats(struct net_device *dev) 437 { 438 struct r6040_private *priv = netdev_priv(dev); 439 void __iomem *ioaddr = priv->base; 440 unsigned long flags; 441 442 spin_lock_irqsave(&priv->lock, flags); 443 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1); 444 dev->stats.multicast += ioread8(ioaddr + ME_CNT0); 445 spin_unlock_irqrestore(&priv->lock, flags); 446 447 return &dev->stats; 448 } 449 450 /* Stop RDC MAC and Free the allocated resource */ 451 static void r6040_down(struct net_device *dev) 452 { 453 struct r6040_private *lp = netdev_priv(dev); 454 void __iomem *ioaddr = lp->base; 455 int limit = 2048; 456 u16 *adrp; 457 u16 cmd; 458 459 /* Stop MAC */ 460 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */ 461 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */ 462 while (limit--) { 463 cmd = ioread16(ioaddr + MCR1); 464 if (cmd & 0x1) 465 break; 466 } 467 468 /* Restore MAC Address to MIDx */ 469 adrp = (u16 *) dev->dev_addr; 470 iowrite16(adrp[0], ioaddr + MID_0L); 471 iowrite16(adrp[1], ioaddr + MID_0M); 472 iowrite16(adrp[2], ioaddr + MID_0H); 473 474 phy_stop(lp->phydev); 475 } 476 477 static int r6040_close(struct net_device *dev) 478 { 479 struct r6040_private *lp = netdev_priv(dev); 480 struct pci_dev *pdev = lp->pdev; 481 482 spin_lock_irq(&lp->lock); 483 napi_disable(&lp->napi); 484 netif_stop_queue(dev); 485 r6040_down(dev); 486 487 free_irq(dev->irq, dev); 488 489 /* Free RX buffer */ 490 r6040_free_rxbufs(dev); 491 492 /* Free TX buffer */ 493 r6040_free_txbufs(dev); 494 495 spin_unlock_irq(&lp->lock); 496 497 /* Free Descriptor memory */ 498 if (lp->rx_ring) { 499 pci_free_consistent(pdev, 500 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma); 501 lp->rx_ring = NULL; 502 } 503 504 if (lp->tx_ring) { 505 pci_free_consistent(pdev, 506 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma); 507 lp->tx_ring = NULL; 508 } 509 510 return 0; 511 } 512 513 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 514 { 515 struct r6040_private *lp = netdev_priv(dev); 516 517 if (!lp->phydev) 518 return -EINVAL; 519 520 return phy_mii_ioctl(lp->phydev, rq, cmd); 521 } 522 523 static int r6040_rx(struct net_device *dev, int limit) 524 { 525 struct r6040_private *priv = netdev_priv(dev); 526 struct r6040_descriptor *descptr = priv->rx_remove_ptr; 527 struct sk_buff *skb_ptr, *new_skb; 528 int count = 0; 529 u16 err; 530 531 /* Limit not reached and the descriptor belongs to the CPU */ 532 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) { 533 /* Read the descriptor status */ 534 err = descptr->status; 535 /* Global error status set */ 536 if (err & DSC_RX_ERR) { 537 /* RX dribble */ 538 if (err & DSC_RX_ERR_DRI) 539 dev->stats.rx_frame_errors++; 540 /* Buffer length exceeded */ 541 if (err & DSC_RX_ERR_BUF) 542 dev->stats.rx_length_errors++; 543 /* Packet too long */ 544 if (err & DSC_RX_ERR_LONG) 545 dev->stats.rx_length_errors++; 546 /* Packet < 64 bytes */ 547 if (err & DSC_RX_ERR_RUNT) 548 dev->stats.rx_length_errors++; 549 /* CRC error */ 550 if (err & DSC_RX_ERR_CRC) { 551 spin_lock(&priv->lock); 552 dev->stats.rx_crc_errors++; 553 spin_unlock(&priv->lock); 554 } 555 goto next_descr; 556 } 557 558 /* Packet successfully received */ 559 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE); 560 if (!new_skb) { 561 dev->stats.rx_dropped++; 562 goto next_descr; 563 } 564 skb_ptr = descptr->skb_ptr; 565 skb_ptr->dev = priv->dev; 566 567 /* Do not count the CRC */ 568 skb_put(skb_ptr, descptr->len - 4); 569 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf), 570 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE); 571 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev); 572 573 /* Send to upper layer */ 574 netif_receive_skb(skb_ptr); 575 dev->stats.rx_packets++; 576 dev->stats.rx_bytes += descptr->len - 4; 577 578 /* put new skb into descriptor */ 579 descptr->skb_ptr = new_skb; 580 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev, 581 descptr->skb_ptr->data, 582 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE)); 583 584 next_descr: 585 /* put the descriptor back to the MAC */ 586 descptr->status = DSC_OWNER_MAC; 587 descptr = descptr->vndescp; 588 count++; 589 } 590 priv->rx_remove_ptr = descptr; 591 592 return count; 593 } 594 595 static void r6040_tx(struct net_device *dev) 596 { 597 struct r6040_private *priv = netdev_priv(dev); 598 struct r6040_descriptor *descptr; 599 void __iomem *ioaddr = priv->base; 600 struct sk_buff *skb_ptr; 601 u16 err; 602 603 spin_lock(&priv->lock); 604 descptr = priv->tx_remove_ptr; 605 while (priv->tx_free_desc < TX_DCNT) { 606 /* Check for errors */ 607 err = ioread16(ioaddr + MLSR); 608 609 if (err & 0x0200) 610 dev->stats.rx_fifo_errors++; 611 if (err & (0x2000 | 0x4000)) 612 dev->stats.tx_carrier_errors++; 613 614 if (descptr->status & DSC_OWNER_MAC) 615 break; /* Not complete */ 616 skb_ptr = descptr->skb_ptr; 617 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf), 618 skb_ptr->len, PCI_DMA_TODEVICE); 619 /* Free buffer */ 620 dev_kfree_skb_irq(skb_ptr); 621 descptr->skb_ptr = NULL; 622 /* To next descriptor */ 623 descptr = descptr->vndescp; 624 priv->tx_free_desc++; 625 } 626 priv->tx_remove_ptr = descptr; 627 628 if (priv->tx_free_desc) 629 netif_wake_queue(dev); 630 spin_unlock(&priv->lock); 631 } 632 633 static int r6040_poll(struct napi_struct *napi, int budget) 634 { 635 struct r6040_private *priv = 636 container_of(napi, struct r6040_private, napi); 637 struct net_device *dev = priv->dev; 638 void __iomem *ioaddr = priv->base; 639 int work_done; 640 641 work_done = r6040_rx(dev, budget); 642 643 if (work_done < budget) { 644 napi_complete(napi); 645 /* Enable RX interrupt */ 646 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER); 647 } 648 return work_done; 649 } 650 651 /* The RDC interrupt handler. */ 652 static irqreturn_t r6040_interrupt(int irq, void *dev_id) 653 { 654 struct net_device *dev = dev_id; 655 struct r6040_private *lp = netdev_priv(dev); 656 void __iomem *ioaddr = lp->base; 657 u16 misr, status; 658 659 /* Save MIER */ 660 misr = ioread16(ioaddr + MIER); 661 /* Mask off RDC MAC interrupt */ 662 iowrite16(MSK_INT, ioaddr + MIER); 663 /* Read MISR status and clear */ 664 status = ioread16(ioaddr + MISR); 665 666 if (status == 0x0000 || status == 0xffff) { 667 /* Restore RDC MAC interrupt */ 668 iowrite16(misr, ioaddr + MIER); 669 return IRQ_NONE; 670 } 671 672 /* RX interrupt request */ 673 if (status & RX_INTS) { 674 if (status & RX_NO_DESC) { 675 /* RX descriptor unavailable */ 676 dev->stats.rx_dropped++; 677 dev->stats.rx_missed_errors++; 678 } 679 if (status & RX_FIFO_FULL) 680 dev->stats.rx_fifo_errors++; 681 682 if (likely(napi_schedule_prep(&lp->napi))) { 683 /* Mask off RX interrupt */ 684 misr &= ~RX_INTS; 685 __napi_schedule(&lp->napi); 686 } 687 } 688 689 /* TX interrupt request */ 690 if (status & TX_INTS) 691 r6040_tx(dev); 692 693 /* Restore RDC MAC interrupt */ 694 iowrite16(misr, ioaddr + MIER); 695 696 return IRQ_HANDLED; 697 } 698 699 #ifdef CONFIG_NET_POLL_CONTROLLER 700 static void r6040_poll_controller(struct net_device *dev) 701 { 702 disable_irq(dev->irq); 703 r6040_interrupt(dev->irq, dev); 704 enable_irq(dev->irq); 705 } 706 #endif 707 708 /* Init RDC MAC */ 709 static int r6040_up(struct net_device *dev) 710 { 711 struct r6040_private *lp = netdev_priv(dev); 712 void __iomem *ioaddr = lp->base; 713 int ret; 714 715 /* Initialise and alloc RX/TX buffers */ 716 r6040_init_txbufs(dev); 717 ret = r6040_alloc_rxbufs(dev); 718 if (ret) 719 return ret; 720 721 /* improve performance (by RDC guys) */ 722 r6040_phy_write(ioaddr, 30, 17, 723 (r6040_phy_read(ioaddr, 30, 17) | 0x4000)); 724 r6040_phy_write(ioaddr, 30, 17, 725 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000)); 726 r6040_phy_write(ioaddr, 0, 19, 0x0000); 727 r6040_phy_write(ioaddr, 0, 30, 0x01F0); 728 729 /* Initialize all MAC registers */ 730 r6040_init_mac_regs(dev); 731 732 phy_start(lp->phydev); 733 734 return 0; 735 } 736 737 738 /* Read/set MAC address routines */ 739 static void r6040_mac_address(struct net_device *dev) 740 { 741 struct r6040_private *lp = netdev_priv(dev); 742 void __iomem *ioaddr = lp->base; 743 u16 *adrp; 744 745 /* MAC operation register */ 746 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */ 747 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */ 748 iowrite16(0, ioaddr + MAC_SM); 749 mdelay(5); 750 751 /* Restore MAC Address */ 752 adrp = (u16 *) dev->dev_addr; 753 iowrite16(adrp[0], ioaddr + MID_0L); 754 iowrite16(adrp[1], ioaddr + MID_0M); 755 iowrite16(adrp[2], ioaddr + MID_0H); 756 757 /* Store MAC Address in perm_addr */ 758 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN); 759 } 760 761 static int r6040_open(struct net_device *dev) 762 { 763 struct r6040_private *lp = netdev_priv(dev); 764 int ret; 765 766 /* Request IRQ and Register interrupt handler */ 767 ret = request_irq(dev->irq, r6040_interrupt, 768 IRQF_SHARED, dev->name, dev); 769 if (ret) 770 goto out; 771 772 /* Set MAC address */ 773 r6040_mac_address(dev); 774 775 /* Allocate Descriptor memory */ 776 lp->rx_ring = 777 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma); 778 if (!lp->rx_ring) { 779 ret = -ENOMEM; 780 goto err_free_irq; 781 } 782 783 lp->tx_ring = 784 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma); 785 if (!lp->tx_ring) { 786 ret = -ENOMEM; 787 goto err_free_rx_ring; 788 } 789 790 ret = r6040_up(dev); 791 if (ret) 792 goto err_free_tx_ring; 793 794 napi_enable(&lp->napi); 795 netif_start_queue(dev); 796 797 return 0; 798 799 err_free_tx_ring: 800 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring, 801 lp->tx_ring_dma); 802 err_free_rx_ring: 803 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring, 804 lp->rx_ring_dma); 805 err_free_irq: 806 free_irq(dev->irq, dev); 807 out: 808 return ret; 809 } 810 811 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb, 812 struct net_device *dev) 813 { 814 struct r6040_private *lp = netdev_priv(dev); 815 struct r6040_descriptor *descptr; 816 void __iomem *ioaddr = lp->base; 817 unsigned long flags; 818 819 /* Critical Section */ 820 spin_lock_irqsave(&lp->lock, flags); 821 822 /* TX resource check */ 823 if (!lp->tx_free_desc) { 824 spin_unlock_irqrestore(&lp->lock, flags); 825 netif_stop_queue(dev); 826 netdev_err(dev, ": no tx descriptor\n"); 827 return NETDEV_TX_BUSY; 828 } 829 830 /* Statistic Counter */ 831 dev->stats.tx_packets++; 832 dev->stats.tx_bytes += skb->len; 833 /* Set TX descriptor & Transmit it */ 834 lp->tx_free_desc--; 835 descptr = lp->tx_insert_ptr; 836 if (skb->len < MISR) 837 descptr->len = MISR; 838 else 839 descptr->len = skb->len; 840 841 descptr->skb_ptr = skb; 842 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, 843 skb->data, skb->len, PCI_DMA_TODEVICE)); 844 descptr->status = DSC_OWNER_MAC; 845 846 skb_tx_timestamp(skb); 847 848 /* Trigger the MAC to check the TX descriptor */ 849 iowrite16(0x01, ioaddr + MTPR); 850 lp->tx_insert_ptr = descptr->vndescp; 851 852 /* If no tx resource, stop */ 853 if (!lp->tx_free_desc) 854 netif_stop_queue(dev); 855 856 spin_unlock_irqrestore(&lp->lock, flags); 857 858 return NETDEV_TX_OK; 859 } 860 861 static void r6040_multicast_list(struct net_device *dev) 862 { 863 struct r6040_private *lp = netdev_priv(dev); 864 void __iomem *ioaddr = lp->base; 865 unsigned long flags; 866 struct netdev_hw_addr *ha; 867 int i; 868 u16 *adrp; 869 u16 hash_table[4] = { 0 }; 870 871 spin_lock_irqsave(&lp->lock, flags); 872 873 /* Keep our MAC Address */ 874 adrp = (u16 *)dev->dev_addr; 875 iowrite16(adrp[0], ioaddr + MID_0L); 876 iowrite16(adrp[1], ioaddr + MID_0M); 877 iowrite16(adrp[2], ioaddr + MID_0H); 878 879 /* Clear AMCP & PROM bits */ 880 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN); 881 882 /* Promiscuous mode */ 883 if (dev->flags & IFF_PROMISC) 884 lp->mcr0 |= MCR0_PROMISC; 885 886 /* Enable multicast hash table function to 887 * receive all multicast packets. */ 888 else if (dev->flags & IFF_ALLMULTI) { 889 lp->mcr0 |= MCR0_HASH_EN; 890 891 for (i = 0; i < MCAST_MAX ; i++) { 892 iowrite16(0, ioaddr + MID_1L + 8 * i); 893 iowrite16(0, ioaddr + MID_1M + 8 * i); 894 iowrite16(0, ioaddr + MID_1H + 8 * i); 895 } 896 897 for (i = 0; i < 4; i++) 898 hash_table[i] = 0xffff; 899 } 900 /* Use internal multicast address registers if the number of 901 * multicast addresses is not greater than MCAST_MAX. */ 902 else if (netdev_mc_count(dev) <= MCAST_MAX) { 903 i = 0; 904 netdev_for_each_mc_addr(ha, dev) { 905 u16 *adrp = (u16 *) ha->addr; 906 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i); 907 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i); 908 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i); 909 i++; 910 } 911 while (i < MCAST_MAX) { 912 iowrite16(0, ioaddr + MID_1L + 8 * i); 913 iowrite16(0, ioaddr + MID_1M + 8 * i); 914 iowrite16(0, ioaddr + MID_1H + 8 * i); 915 i++; 916 } 917 } 918 /* Otherwise, Enable multicast hash table function. */ 919 else { 920 u32 crc; 921 922 lp->mcr0 |= MCR0_HASH_EN; 923 924 for (i = 0; i < MCAST_MAX ; i++) { 925 iowrite16(0, ioaddr + MID_1L + 8 * i); 926 iowrite16(0, ioaddr + MID_1M + 8 * i); 927 iowrite16(0, ioaddr + MID_1H + 8 * i); 928 } 929 930 /* Build multicast hash table */ 931 netdev_for_each_mc_addr(ha, dev) { 932 u8 *addrs = ha->addr; 933 934 crc = ether_crc(ETH_ALEN, addrs); 935 crc >>= 26; 936 hash_table[crc >> 4] |= 1 << (crc & 0xf); 937 } 938 } 939 940 iowrite16(lp->mcr0, ioaddr + MCR0); 941 942 /* Fill the MAC hash tables with their values */ 943 if (lp->mcr0 && MCR0_HASH_EN) { 944 iowrite16(hash_table[0], ioaddr + MAR0); 945 iowrite16(hash_table[1], ioaddr + MAR1); 946 iowrite16(hash_table[2], ioaddr + MAR2); 947 iowrite16(hash_table[3], ioaddr + MAR3); 948 } 949 950 spin_unlock_irqrestore(&lp->lock, flags); 951 } 952 953 static void netdev_get_drvinfo(struct net_device *dev, 954 struct ethtool_drvinfo *info) 955 { 956 struct r6040_private *rp = netdev_priv(dev); 957 958 strcpy(info->driver, DRV_NAME); 959 strcpy(info->version, DRV_VERSION); 960 strcpy(info->bus_info, pci_name(rp->pdev)); 961 } 962 963 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 964 { 965 struct r6040_private *rp = netdev_priv(dev); 966 967 return phy_ethtool_gset(rp->phydev, cmd); 968 } 969 970 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 971 { 972 struct r6040_private *rp = netdev_priv(dev); 973 974 return phy_ethtool_sset(rp->phydev, cmd); 975 } 976 977 static const struct ethtool_ops netdev_ethtool_ops = { 978 .get_drvinfo = netdev_get_drvinfo, 979 .get_settings = netdev_get_settings, 980 .set_settings = netdev_set_settings, 981 .get_link = ethtool_op_get_link, 982 }; 983 984 static const struct net_device_ops r6040_netdev_ops = { 985 .ndo_open = r6040_open, 986 .ndo_stop = r6040_close, 987 .ndo_start_xmit = r6040_start_xmit, 988 .ndo_get_stats = r6040_get_stats, 989 .ndo_set_rx_mode = r6040_multicast_list, 990 .ndo_change_mtu = eth_change_mtu, 991 .ndo_validate_addr = eth_validate_addr, 992 .ndo_set_mac_address = eth_mac_addr, 993 .ndo_do_ioctl = r6040_ioctl, 994 .ndo_tx_timeout = r6040_tx_timeout, 995 #ifdef CONFIG_NET_POLL_CONTROLLER 996 .ndo_poll_controller = r6040_poll_controller, 997 #endif 998 }; 999 1000 static void r6040_adjust_link(struct net_device *dev) 1001 { 1002 struct r6040_private *lp = netdev_priv(dev); 1003 struct phy_device *phydev = lp->phydev; 1004 int status_changed = 0; 1005 void __iomem *ioaddr = lp->base; 1006 1007 BUG_ON(!phydev); 1008 1009 if (lp->old_link != phydev->link) { 1010 status_changed = 1; 1011 lp->old_link = phydev->link; 1012 } 1013 1014 /* reflect duplex change */ 1015 if (phydev->link && (lp->old_duplex != phydev->duplex)) { 1016 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? 0x8000 : 0); 1017 iowrite16(lp->mcr0, ioaddr); 1018 1019 status_changed = 1; 1020 lp->old_duplex = phydev->duplex; 1021 } 1022 1023 if (status_changed) { 1024 pr_info("%s: link %s", dev->name, phydev->link ? 1025 "UP" : "DOWN"); 1026 if (phydev->link) 1027 pr_cont(" - %d/%s", phydev->speed, 1028 DUPLEX_FULL == phydev->duplex ? "full" : "half"); 1029 pr_cont("\n"); 1030 } 1031 } 1032 1033 static int r6040_mii_probe(struct net_device *dev) 1034 { 1035 struct r6040_private *lp = netdev_priv(dev); 1036 struct phy_device *phydev = NULL; 1037 1038 phydev = phy_find_first(lp->mii_bus); 1039 if (!phydev) { 1040 dev_err(&lp->pdev->dev, "no PHY found\n"); 1041 return -ENODEV; 1042 } 1043 1044 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link, 1045 0, PHY_INTERFACE_MODE_MII); 1046 1047 if (IS_ERR(phydev)) { 1048 dev_err(&lp->pdev->dev, "could not attach to PHY\n"); 1049 return PTR_ERR(phydev); 1050 } 1051 1052 /* mask with MAC supported features */ 1053 phydev->supported &= (SUPPORTED_10baseT_Half 1054 | SUPPORTED_10baseT_Full 1055 | SUPPORTED_100baseT_Half 1056 | SUPPORTED_100baseT_Full 1057 | SUPPORTED_Autoneg 1058 | SUPPORTED_MII 1059 | SUPPORTED_TP); 1060 1061 phydev->advertising = phydev->supported; 1062 lp->phydev = phydev; 1063 lp->old_link = 0; 1064 lp->old_duplex = -1; 1065 1066 dev_info(&lp->pdev->dev, "attached PHY driver [%s] " 1067 "(mii_bus:phy_addr=%s)\n", 1068 phydev->drv->name, dev_name(&phydev->dev)); 1069 1070 return 0; 1071 } 1072 1073 static int __devinit r6040_init_one(struct pci_dev *pdev, 1074 const struct pci_device_id *ent) 1075 { 1076 struct net_device *dev; 1077 struct r6040_private *lp; 1078 void __iomem *ioaddr; 1079 int err, io_size = R6040_IO_SIZE; 1080 static int card_idx = -1; 1081 int bar = 0; 1082 u16 *adrp; 1083 int i; 1084 1085 pr_info("%s\n", version); 1086 1087 err = pci_enable_device(pdev); 1088 if (err) 1089 goto err_out; 1090 1091 /* this should always be supported */ 1092 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1093 if (err) { 1094 dev_err(&pdev->dev, "32-bit PCI DMA addresses" 1095 "not supported by the card\n"); 1096 goto err_out; 1097 } 1098 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 1099 if (err) { 1100 dev_err(&pdev->dev, "32-bit PCI DMA addresses" 1101 "not supported by the card\n"); 1102 goto err_out; 1103 } 1104 1105 /* IO Size check */ 1106 if (pci_resource_len(pdev, bar) < io_size) { 1107 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n"); 1108 err = -EIO; 1109 goto err_out; 1110 } 1111 1112 pci_set_master(pdev); 1113 1114 dev = alloc_etherdev(sizeof(struct r6040_private)); 1115 if (!dev) { 1116 dev_err(&pdev->dev, "Failed to allocate etherdev\n"); 1117 err = -ENOMEM; 1118 goto err_out; 1119 } 1120 SET_NETDEV_DEV(dev, &pdev->dev); 1121 lp = netdev_priv(dev); 1122 1123 err = pci_request_regions(pdev, DRV_NAME); 1124 1125 if (err) { 1126 dev_err(&pdev->dev, "Failed to request PCI regions\n"); 1127 goto err_out_free_dev; 1128 } 1129 1130 ioaddr = pci_iomap(pdev, bar, io_size); 1131 if (!ioaddr) { 1132 dev_err(&pdev->dev, "ioremap failed for device\n"); 1133 err = -EIO; 1134 goto err_out_free_res; 1135 } 1136 /* If PHY status change register is still set to zero it means the 1137 * bootloader didn't initialize it */ 1138 if (ioread16(ioaddr + PHY_CC) == 0) 1139 iowrite16(0x9f07, ioaddr + PHY_CC); 1140 1141 /* Init system & device */ 1142 lp->base = ioaddr; 1143 dev->irq = pdev->irq; 1144 1145 spin_lock_init(&lp->lock); 1146 pci_set_drvdata(pdev, dev); 1147 1148 /* Set MAC address */ 1149 card_idx++; 1150 1151 adrp = (u16 *)dev->dev_addr; 1152 adrp[0] = ioread16(ioaddr + MID_0L); 1153 adrp[1] = ioread16(ioaddr + MID_0M); 1154 adrp[2] = ioread16(ioaddr + MID_0H); 1155 1156 /* Some bootloader/BIOSes do not initialize 1157 * MAC address, warn about that */ 1158 if (!(adrp[0] || adrp[1] || adrp[2])) { 1159 netdev_warn(dev, "MAC address not initialized, " 1160 "generating random\n"); 1161 random_ether_addr(dev->dev_addr); 1162 } 1163 1164 /* Link new device into r6040_root_dev */ 1165 lp->pdev = pdev; 1166 lp->dev = dev; 1167 1168 /* Init RDC private data */ 1169 lp->mcr0 = 0x1002; 1170 lp->phy_addr = phy_table[card_idx]; 1171 1172 /* The RDC-specific entries in the device structure. */ 1173 dev->netdev_ops = &r6040_netdev_ops; 1174 dev->ethtool_ops = &netdev_ethtool_ops; 1175 dev->watchdog_timeo = TX_TIMEOUT; 1176 1177 netif_napi_add(dev, &lp->napi, r6040_poll, 64); 1178 1179 lp->mii_bus = mdiobus_alloc(); 1180 if (!lp->mii_bus) { 1181 dev_err(&pdev->dev, "mdiobus_alloc() failed\n"); 1182 err = -ENOMEM; 1183 goto err_out_unmap; 1184 } 1185 1186 lp->mii_bus->priv = dev; 1187 lp->mii_bus->read = r6040_mdiobus_read; 1188 lp->mii_bus->write = r6040_mdiobus_write; 1189 lp->mii_bus->reset = r6040_mdiobus_reset; 1190 lp->mii_bus->name = "r6040_eth_mii"; 1191 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x", card_idx); 1192 lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); 1193 if (!lp->mii_bus->irq) { 1194 dev_err(&pdev->dev, "mii_bus irq allocation failed\n"); 1195 err = -ENOMEM; 1196 goto err_out_mdio; 1197 } 1198 1199 for (i = 0; i < PHY_MAX_ADDR; i++) 1200 lp->mii_bus->irq[i] = PHY_POLL; 1201 1202 err = mdiobus_register(lp->mii_bus); 1203 if (err) { 1204 dev_err(&pdev->dev, "failed to register MII bus\n"); 1205 goto err_out_mdio_irq; 1206 } 1207 1208 err = r6040_mii_probe(dev); 1209 if (err) { 1210 dev_err(&pdev->dev, "failed to probe MII bus\n"); 1211 goto err_out_mdio_unregister; 1212 } 1213 1214 /* Register net device. After this dev->name assign */ 1215 err = register_netdev(dev); 1216 if (err) { 1217 dev_err(&pdev->dev, "Failed to register net device\n"); 1218 goto err_out_mdio_unregister; 1219 } 1220 return 0; 1221 1222 err_out_mdio_unregister: 1223 mdiobus_unregister(lp->mii_bus); 1224 err_out_mdio_irq: 1225 kfree(lp->mii_bus->irq); 1226 err_out_mdio: 1227 mdiobus_free(lp->mii_bus); 1228 err_out_unmap: 1229 pci_iounmap(pdev, ioaddr); 1230 err_out_free_res: 1231 pci_release_regions(pdev); 1232 err_out_free_dev: 1233 free_netdev(dev); 1234 err_out: 1235 return err; 1236 } 1237 1238 static void __devexit r6040_remove_one(struct pci_dev *pdev) 1239 { 1240 struct net_device *dev = pci_get_drvdata(pdev); 1241 struct r6040_private *lp = netdev_priv(dev); 1242 1243 unregister_netdev(dev); 1244 mdiobus_unregister(lp->mii_bus); 1245 kfree(lp->mii_bus->irq); 1246 mdiobus_free(lp->mii_bus); 1247 pci_release_regions(pdev); 1248 free_netdev(dev); 1249 pci_disable_device(pdev); 1250 pci_set_drvdata(pdev, NULL); 1251 } 1252 1253 1254 static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = { 1255 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) }, 1256 { 0 } 1257 }; 1258 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl); 1259 1260 static struct pci_driver r6040_driver = { 1261 .name = DRV_NAME, 1262 .id_table = r6040_pci_tbl, 1263 .probe = r6040_init_one, 1264 .remove = __devexit_p(r6040_remove_one), 1265 }; 1266 1267 1268 static int __init r6040_init(void) 1269 { 1270 return pci_register_driver(&r6040_driver); 1271 } 1272 1273 1274 static void __exit r6040_cleanup(void) 1275 { 1276 pci_unregister_driver(&r6040_driver); 1277 } 1278 1279 module_init(r6040_init); 1280 module_exit(r6040_cleanup); 1281