1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 /* Qualcomm Technologies, Inc. EMAC Gigabit Ethernet Driver */ 14 15 #include <linux/if_ether.h> 16 #include <linux/if_vlan.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_device.h> 23 #include <linux/phy.h> 24 #include <linux/platform_device.h> 25 #include "emac.h" 26 #include "emac-mac.h" 27 #include "emac-phy.h" 28 #include "emac-sgmii.h" 29 30 #define EMAC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 31 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP) 32 33 #define EMAC_RRD_SIZE 4 34 /* The RRD size if timestamping is enabled: */ 35 #define EMAC_TS_RRD_SIZE 6 36 #define EMAC_TPD_SIZE 4 37 #define EMAC_RFD_SIZE 2 38 39 #define REG_MAC_RX_STATUS_BIN EMAC_RXMAC_STATC_REG0 40 #define REG_MAC_RX_STATUS_END EMAC_RXMAC_STATC_REG22 41 #define REG_MAC_TX_STATUS_BIN EMAC_TXMAC_STATC_REG0 42 #define REG_MAC_TX_STATUS_END EMAC_TXMAC_STATC_REG24 43 44 #define RXQ0_NUM_RFD_PREF_DEF 8 45 #define TXQ0_NUM_TPD_PREF_DEF 5 46 47 #define EMAC_PREAMBLE_DEF 7 48 49 #define DMAR_DLY_CNT_DEF 15 50 #define DMAW_DLY_CNT_DEF 4 51 52 #define IMR_NORMAL_MASK (\ 53 ISR_ERROR |\ 54 ISR_GPHY_LINK |\ 55 ISR_TX_PKT |\ 56 GPHY_WAKEUP_INT) 57 58 #define IMR_EXTENDED_MASK (\ 59 SW_MAN_INT |\ 60 ISR_OVER |\ 61 ISR_ERROR |\ 62 ISR_GPHY_LINK |\ 63 ISR_TX_PKT |\ 64 GPHY_WAKEUP_INT) 65 66 #define ISR_TX_PKT (\ 67 TX_PKT_INT |\ 68 TX_PKT_INT1 |\ 69 TX_PKT_INT2 |\ 70 TX_PKT_INT3) 71 72 #define ISR_GPHY_LINK (\ 73 GPHY_LINK_UP_INT |\ 74 GPHY_LINK_DOWN_INT) 75 76 #define ISR_OVER (\ 77 RFD0_UR_INT |\ 78 RFD1_UR_INT |\ 79 RFD2_UR_INT |\ 80 RFD3_UR_INT |\ 81 RFD4_UR_INT |\ 82 RXF_OF_INT |\ 83 TXF_UR_INT) 84 85 #define ISR_ERROR (\ 86 DMAR_TO_INT |\ 87 DMAW_TO_INT |\ 88 TXQ_TO_INT) 89 90 /* in sync with enum emac_clk_id */ 91 static const char * const emac_clk_name[] = { 92 "axi_clk", "cfg_ahb_clk", "high_speed_clk", "mdio_clk", "tx_clk", 93 "rx_clk", "sys_clk" 94 }; 95 96 void emac_reg_update32(void __iomem *addr, u32 mask, u32 val) 97 { 98 u32 data = readl(addr); 99 100 writel(((data & ~mask) | val), addr); 101 } 102 103 /* reinitialize */ 104 int emac_reinit_locked(struct emac_adapter *adpt) 105 { 106 int ret; 107 108 mutex_lock(&adpt->reset_lock); 109 110 emac_mac_down(adpt); 111 emac_sgmii_reset(adpt); 112 ret = emac_mac_up(adpt); 113 114 mutex_unlock(&adpt->reset_lock); 115 116 return ret; 117 } 118 119 /* NAPI */ 120 static int emac_napi_rtx(struct napi_struct *napi, int budget) 121 { 122 struct emac_rx_queue *rx_q = 123 container_of(napi, struct emac_rx_queue, napi); 124 struct emac_adapter *adpt = netdev_priv(rx_q->netdev); 125 struct emac_irq *irq = rx_q->irq; 126 int work_done = 0; 127 128 emac_mac_rx_process(adpt, rx_q, &work_done, budget); 129 130 if (work_done < budget) { 131 napi_complete(napi); 132 133 irq->mask |= rx_q->intr; 134 writel(irq->mask, adpt->base + EMAC_INT_MASK); 135 } 136 137 return work_done; 138 } 139 140 /* Transmit the packet */ 141 static int emac_start_xmit(struct sk_buff *skb, struct net_device *netdev) 142 { 143 struct emac_adapter *adpt = netdev_priv(netdev); 144 145 return emac_mac_tx_buf_send(adpt, &adpt->tx_q, skb); 146 } 147 148 irqreturn_t emac_isr(int _irq, void *data) 149 { 150 struct emac_irq *irq = data; 151 struct emac_adapter *adpt = 152 container_of(irq, struct emac_adapter, irq); 153 struct emac_rx_queue *rx_q = &adpt->rx_q; 154 u32 isr, status; 155 156 /* disable the interrupt */ 157 writel(0, adpt->base + EMAC_INT_MASK); 158 159 isr = readl_relaxed(adpt->base + EMAC_INT_STATUS); 160 161 status = isr & irq->mask; 162 if (status == 0) 163 goto exit; 164 165 if (status & ISR_ERROR) { 166 netif_warn(adpt, intr, adpt->netdev, 167 "warning: error irq status 0x%lx\n", 168 status & ISR_ERROR); 169 /* reset MAC */ 170 schedule_work(&adpt->work_thread); 171 } 172 173 /* Schedule the napi for receive queue with interrupt 174 * status bit set 175 */ 176 if (status & rx_q->intr) { 177 if (napi_schedule_prep(&rx_q->napi)) { 178 irq->mask &= ~rx_q->intr; 179 __napi_schedule(&rx_q->napi); 180 } 181 } 182 183 if (status & TX_PKT_INT) 184 emac_mac_tx_process(adpt, &adpt->tx_q); 185 186 if (status & ISR_OVER) 187 net_warn_ratelimited("warning: TX/RX overflow\n"); 188 189 /* link event */ 190 if (status & ISR_GPHY_LINK) 191 phy_mac_interrupt(adpt->phydev, !!(status & GPHY_LINK_UP_INT)); 192 193 exit: 194 /* enable the interrupt */ 195 writel(irq->mask, adpt->base + EMAC_INT_MASK); 196 197 return IRQ_HANDLED; 198 } 199 200 /* Configure VLAN tag strip/insert feature */ 201 static int emac_set_features(struct net_device *netdev, 202 netdev_features_t features) 203 { 204 netdev_features_t changed = features ^ netdev->features; 205 struct emac_adapter *adpt = netdev_priv(netdev); 206 207 /* We only need to reprogram the hardware if the VLAN tag features 208 * have changed, and if it's already running. 209 */ 210 if (!(changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX))) 211 return 0; 212 213 if (!netif_running(netdev)) 214 return 0; 215 216 /* emac_mac_mode_config() uses netdev->features to configure the EMAC, 217 * so make sure it's set first. 218 */ 219 netdev->features = features; 220 221 return emac_reinit_locked(adpt); 222 } 223 224 /* Configure Multicast and Promiscuous modes */ 225 static void emac_rx_mode_set(struct net_device *netdev) 226 { 227 struct emac_adapter *adpt = netdev_priv(netdev); 228 struct netdev_hw_addr *ha; 229 230 emac_mac_mode_config(adpt); 231 232 /* update multicast address filtering */ 233 emac_mac_multicast_addr_clear(adpt); 234 netdev_for_each_mc_addr(ha, netdev) 235 emac_mac_multicast_addr_set(adpt, ha->addr); 236 } 237 238 /* Change the Maximum Transfer Unit (MTU) */ 239 static int emac_change_mtu(struct net_device *netdev, int new_mtu) 240 { 241 unsigned int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 242 struct emac_adapter *adpt = netdev_priv(netdev); 243 244 if ((max_frame < EMAC_MIN_ETH_FRAME_SIZE) || 245 (max_frame > EMAC_MAX_ETH_FRAME_SIZE)) { 246 netdev_err(adpt->netdev, "error: invalid MTU setting\n"); 247 return -EINVAL; 248 } 249 250 netif_info(adpt, hw, adpt->netdev, 251 "changing MTU from %d to %d\n", netdev->mtu, 252 new_mtu); 253 netdev->mtu = new_mtu; 254 255 if (netif_running(netdev)) 256 return emac_reinit_locked(adpt); 257 258 return 0; 259 } 260 261 /* Called when the network interface is made active */ 262 static int emac_open(struct net_device *netdev) 263 { 264 struct emac_adapter *adpt = netdev_priv(netdev); 265 int ret; 266 267 /* allocate rx/tx dma buffer & descriptors */ 268 ret = emac_mac_rx_tx_rings_alloc_all(adpt); 269 if (ret) { 270 netdev_err(adpt->netdev, "error allocating rx/tx rings\n"); 271 return ret; 272 } 273 274 ret = emac_mac_up(adpt); 275 if (ret) { 276 emac_mac_rx_tx_rings_free_all(adpt); 277 return ret; 278 } 279 280 emac_mac_start(adpt); 281 282 return 0; 283 } 284 285 /* Called when the network interface is disabled */ 286 static int emac_close(struct net_device *netdev) 287 { 288 struct emac_adapter *adpt = netdev_priv(netdev); 289 290 mutex_lock(&adpt->reset_lock); 291 292 emac_mac_down(adpt); 293 emac_mac_rx_tx_rings_free_all(adpt); 294 295 mutex_unlock(&adpt->reset_lock); 296 297 return 0; 298 } 299 300 /* Respond to a TX hang */ 301 static void emac_tx_timeout(struct net_device *netdev) 302 { 303 struct emac_adapter *adpt = netdev_priv(netdev); 304 305 schedule_work(&adpt->work_thread); 306 } 307 308 /* IOCTL support for the interface */ 309 static int emac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 310 { 311 if (!netif_running(netdev)) 312 return -EINVAL; 313 314 if (!netdev->phydev) 315 return -ENODEV; 316 317 return phy_mii_ioctl(netdev->phydev, ifr, cmd); 318 } 319 320 /* Provide network statistics info for the interface */ 321 static struct rtnl_link_stats64 *emac_get_stats64(struct net_device *netdev, 322 struct rtnl_link_stats64 *net_stats) 323 { 324 struct emac_adapter *adpt = netdev_priv(netdev); 325 unsigned int addr = REG_MAC_RX_STATUS_BIN; 326 struct emac_stats *stats = &adpt->stats; 327 u64 *stats_itr = &adpt->stats.rx_ok; 328 u32 val; 329 330 spin_lock(&stats->lock); 331 332 while (addr <= REG_MAC_RX_STATUS_END) { 333 val = readl_relaxed(adpt->base + addr); 334 *stats_itr += val; 335 stats_itr++; 336 addr += sizeof(u32); 337 } 338 339 /* additional rx status */ 340 val = readl_relaxed(adpt->base + EMAC_RXMAC_STATC_REG23); 341 adpt->stats.rx_crc_align += val; 342 val = readl_relaxed(adpt->base + EMAC_RXMAC_STATC_REG24); 343 adpt->stats.rx_jabbers += val; 344 345 /* update tx status */ 346 addr = REG_MAC_TX_STATUS_BIN; 347 stats_itr = &adpt->stats.tx_ok; 348 349 while (addr <= REG_MAC_TX_STATUS_END) { 350 val = readl_relaxed(adpt->base + addr); 351 *stats_itr += val; 352 ++stats_itr; 353 addr += sizeof(u32); 354 } 355 356 /* additional tx status */ 357 val = readl_relaxed(adpt->base + EMAC_TXMAC_STATC_REG25); 358 adpt->stats.tx_col += val; 359 360 /* return parsed statistics */ 361 net_stats->rx_packets = stats->rx_ok; 362 net_stats->tx_packets = stats->tx_ok; 363 net_stats->rx_bytes = stats->rx_byte_cnt; 364 net_stats->tx_bytes = stats->tx_byte_cnt; 365 net_stats->multicast = stats->rx_mcast; 366 net_stats->collisions = stats->tx_1_col + stats->tx_2_col * 2 + 367 stats->tx_late_col + stats->tx_abort_col; 368 369 net_stats->rx_errors = stats->rx_frag + stats->rx_fcs_err + 370 stats->rx_len_err + stats->rx_sz_ov + 371 stats->rx_align_err; 372 net_stats->rx_fifo_errors = stats->rx_rxf_ov; 373 net_stats->rx_length_errors = stats->rx_len_err; 374 net_stats->rx_crc_errors = stats->rx_fcs_err; 375 net_stats->rx_frame_errors = stats->rx_align_err; 376 net_stats->rx_over_errors = stats->rx_rxf_ov; 377 net_stats->rx_missed_errors = stats->rx_rxf_ov; 378 379 net_stats->tx_errors = stats->tx_late_col + stats->tx_abort_col + 380 stats->tx_underrun + stats->tx_trunc; 381 net_stats->tx_fifo_errors = stats->tx_underrun; 382 net_stats->tx_aborted_errors = stats->tx_abort_col; 383 net_stats->tx_window_errors = stats->tx_late_col; 384 385 spin_unlock(&stats->lock); 386 387 return net_stats; 388 } 389 390 static const struct net_device_ops emac_netdev_ops = { 391 .ndo_open = emac_open, 392 .ndo_stop = emac_close, 393 .ndo_validate_addr = eth_validate_addr, 394 .ndo_start_xmit = emac_start_xmit, 395 .ndo_set_mac_address = eth_mac_addr, 396 .ndo_change_mtu = emac_change_mtu, 397 .ndo_do_ioctl = emac_ioctl, 398 .ndo_tx_timeout = emac_tx_timeout, 399 .ndo_get_stats64 = emac_get_stats64, 400 .ndo_set_features = emac_set_features, 401 .ndo_set_rx_mode = emac_rx_mode_set, 402 }; 403 404 /* Watchdog task routine, called to reinitialize the EMAC */ 405 static void emac_work_thread(struct work_struct *work) 406 { 407 struct emac_adapter *adpt = 408 container_of(work, struct emac_adapter, work_thread); 409 410 emac_reinit_locked(adpt); 411 } 412 413 /* Initialize various data structures */ 414 static void emac_init_adapter(struct emac_adapter *adpt) 415 { 416 u32 reg; 417 418 /* descriptors */ 419 adpt->tx_desc_cnt = EMAC_DEF_TX_DESCS; 420 adpt->rx_desc_cnt = EMAC_DEF_RX_DESCS; 421 422 /* dma */ 423 adpt->dma_order = emac_dma_ord_out; 424 adpt->dmar_block = emac_dma_req_4096; 425 adpt->dmaw_block = emac_dma_req_128; 426 adpt->dmar_dly_cnt = DMAR_DLY_CNT_DEF; 427 adpt->dmaw_dly_cnt = DMAW_DLY_CNT_DEF; 428 adpt->tpd_burst = TXQ0_NUM_TPD_PREF_DEF; 429 adpt->rfd_burst = RXQ0_NUM_RFD_PREF_DEF; 430 431 /* irq moderator */ 432 reg = ((EMAC_DEF_RX_IRQ_MOD >> 1) << IRQ_MODERATOR2_INIT_SHFT) | 433 ((EMAC_DEF_TX_IRQ_MOD >> 1) << IRQ_MODERATOR_INIT_SHFT); 434 adpt->irq_mod = reg; 435 436 /* others */ 437 adpt->preamble = EMAC_PREAMBLE_DEF; 438 } 439 440 /* Get the clock */ 441 static int emac_clks_get(struct platform_device *pdev, 442 struct emac_adapter *adpt) 443 { 444 unsigned int i; 445 446 for (i = 0; i < EMAC_CLK_CNT; i++) { 447 struct clk *clk = devm_clk_get(&pdev->dev, emac_clk_name[i]); 448 449 if (IS_ERR(clk)) { 450 dev_err(&pdev->dev, 451 "could not claim clock %s (error=%li)\n", 452 emac_clk_name[i], PTR_ERR(clk)); 453 454 return PTR_ERR(clk); 455 } 456 457 adpt->clk[i] = clk; 458 } 459 460 return 0; 461 } 462 463 /* Initialize clocks */ 464 static int emac_clks_phase1_init(struct platform_device *pdev, 465 struct emac_adapter *adpt) 466 { 467 int ret; 468 469 ret = emac_clks_get(pdev, adpt); 470 if (ret) 471 return ret; 472 473 ret = clk_prepare_enable(adpt->clk[EMAC_CLK_AXI]); 474 if (ret) 475 return ret; 476 477 ret = clk_prepare_enable(adpt->clk[EMAC_CLK_CFG_AHB]); 478 if (ret) 479 return ret; 480 481 ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 19200000); 482 if (ret) 483 return ret; 484 485 return clk_prepare_enable(adpt->clk[EMAC_CLK_HIGH_SPEED]); 486 } 487 488 /* Enable clocks; needs emac_clks_phase1_init to be called before */ 489 static int emac_clks_phase2_init(struct platform_device *pdev, 490 struct emac_adapter *adpt) 491 { 492 int ret; 493 494 ret = clk_set_rate(adpt->clk[EMAC_CLK_TX], 125000000); 495 if (ret) 496 return ret; 497 498 ret = clk_prepare_enable(adpt->clk[EMAC_CLK_TX]); 499 if (ret) 500 return ret; 501 502 ret = clk_set_rate(adpt->clk[EMAC_CLK_HIGH_SPEED], 125000000); 503 if (ret) 504 return ret; 505 506 ret = clk_set_rate(adpt->clk[EMAC_CLK_MDIO], 25000000); 507 if (ret) 508 return ret; 509 510 ret = clk_prepare_enable(adpt->clk[EMAC_CLK_MDIO]); 511 if (ret) 512 return ret; 513 514 ret = clk_prepare_enable(adpt->clk[EMAC_CLK_RX]); 515 if (ret) 516 return ret; 517 518 return clk_prepare_enable(adpt->clk[EMAC_CLK_SYS]); 519 } 520 521 static void emac_clks_teardown(struct emac_adapter *adpt) 522 { 523 524 unsigned int i; 525 526 for (i = 0; i < EMAC_CLK_CNT; i++) 527 clk_disable_unprepare(adpt->clk[i]); 528 } 529 530 /* Get the resources */ 531 static int emac_probe_resources(struct platform_device *pdev, 532 struct emac_adapter *adpt) 533 { 534 struct device_node *node = pdev->dev.of_node; 535 struct net_device *netdev = adpt->netdev; 536 struct resource *res; 537 const void *maddr; 538 int ret = 0; 539 540 /* get mac address */ 541 maddr = of_get_mac_address(node); 542 if (!maddr) 543 eth_hw_addr_random(netdev); 544 else 545 ether_addr_copy(netdev->dev_addr, maddr); 546 547 /* Core 0 interrupt */ 548 ret = platform_get_irq(pdev, 0); 549 if (ret < 0) { 550 dev_err(&pdev->dev, 551 "error: missing core0 irq resource (error=%i)\n", ret); 552 return ret; 553 } 554 adpt->irq.irq = ret; 555 556 /* base register address */ 557 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 558 adpt->base = devm_ioremap_resource(&pdev->dev, res); 559 if (IS_ERR(adpt->base)) 560 return PTR_ERR(adpt->base); 561 562 /* CSR register address */ 563 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 564 adpt->csr = devm_ioremap_resource(&pdev->dev, res); 565 if (IS_ERR(adpt->csr)) 566 return PTR_ERR(adpt->csr); 567 568 netdev->base_addr = (unsigned long)adpt->base; 569 570 return 0; 571 } 572 573 static const struct of_device_id emac_dt_match[] = { 574 { 575 .compatible = "qcom,fsm9900-emac", 576 }, 577 {} 578 }; 579 580 static int emac_probe(struct platform_device *pdev) 581 { 582 struct net_device *netdev; 583 struct emac_adapter *adpt; 584 struct emac_phy *phy; 585 u16 devid, revid; 586 u32 reg; 587 int ret; 588 589 /* The EMAC itself is capable of 64-bit DMA, so try that first. */ 590 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 591 if (ret) { 592 /* Some platforms may restrict the EMAC's address bus to less 593 * then the size of DDR. In this case, we need to try a 594 * smaller mask. We could try every possible smaller mask, 595 * but that's overkill. Instead, just fall to 32-bit, which 596 * should always work. 597 */ 598 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 599 if (ret) { 600 dev_err(&pdev->dev, "could not set DMA mask\n"); 601 return ret; 602 } 603 } 604 605 netdev = alloc_etherdev(sizeof(struct emac_adapter)); 606 if (!netdev) 607 return -ENOMEM; 608 609 dev_set_drvdata(&pdev->dev, netdev); 610 SET_NETDEV_DEV(netdev, &pdev->dev); 611 612 adpt = netdev_priv(netdev); 613 adpt->netdev = netdev; 614 adpt->msg_enable = EMAC_MSG_DEFAULT; 615 616 phy = &adpt->phy; 617 618 mutex_init(&adpt->reset_lock); 619 spin_lock_init(&adpt->stats.lock); 620 621 adpt->irq.mask = RX_PKT_INT0 | IMR_NORMAL_MASK; 622 623 ret = emac_probe_resources(pdev, adpt); 624 if (ret) 625 goto err_undo_netdev; 626 627 /* initialize clocks */ 628 ret = emac_clks_phase1_init(pdev, adpt); 629 if (ret) { 630 dev_err(&pdev->dev, "could not initialize clocks\n"); 631 goto err_undo_netdev; 632 } 633 634 netdev->watchdog_timeo = EMAC_WATCHDOG_TIME; 635 netdev->irq = adpt->irq.irq; 636 637 adpt->rrd_size = EMAC_RRD_SIZE; 638 adpt->tpd_size = EMAC_TPD_SIZE; 639 adpt->rfd_size = EMAC_RFD_SIZE; 640 641 netdev->netdev_ops = &emac_netdev_ops; 642 643 emac_init_adapter(adpt); 644 645 /* init external phy */ 646 ret = emac_phy_config(pdev, adpt); 647 if (ret) 648 goto err_undo_clocks; 649 650 /* init internal sgmii phy */ 651 ret = emac_sgmii_config(pdev, adpt); 652 if (ret) 653 goto err_undo_mdiobus; 654 655 /* enable clocks */ 656 ret = emac_clks_phase2_init(pdev, adpt); 657 if (ret) { 658 dev_err(&pdev->dev, "could not initialize clocks\n"); 659 goto err_undo_mdiobus; 660 } 661 662 emac_mac_reset(adpt); 663 664 /* set hw features */ 665 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM | 666 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 667 NETIF_F_HW_VLAN_CTAG_TX; 668 netdev->hw_features = netdev->features; 669 670 netdev->vlan_features |= NETIF_F_SG | NETIF_F_HW_CSUM | 671 NETIF_F_TSO | NETIF_F_TSO6; 672 673 INIT_WORK(&adpt->work_thread, emac_work_thread); 674 675 /* Initialize queues */ 676 emac_mac_rx_tx_ring_init_all(pdev, adpt); 677 678 netif_napi_add(netdev, &adpt->rx_q.napi, emac_napi_rtx, 679 NAPI_POLL_WEIGHT); 680 681 ret = register_netdev(netdev); 682 if (ret) { 683 dev_err(&pdev->dev, "could not register net device\n"); 684 goto err_undo_napi; 685 } 686 687 reg = readl_relaxed(adpt->base + EMAC_DMA_MAS_CTRL); 688 devid = (reg & DEV_ID_NUM_BMSK) >> DEV_ID_NUM_SHFT; 689 revid = (reg & DEV_REV_NUM_BMSK) >> DEV_REV_NUM_SHFT; 690 reg = readl_relaxed(adpt->base + EMAC_CORE_HW_VERSION); 691 692 netif_info(adpt, probe, netdev, 693 "hardware id %d.%d, hardware version %d.%d.%d\n", 694 devid, revid, 695 (reg & MAJOR_BMSK) >> MAJOR_SHFT, 696 (reg & MINOR_BMSK) >> MINOR_SHFT, 697 (reg & STEP_BMSK) >> STEP_SHFT); 698 699 return 0; 700 701 err_undo_napi: 702 netif_napi_del(&adpt->rx_q.napi); 703 err_undo_mdiobus: 704 mdiobus_unregister(adpt->mii_bus); 705 err_undo_clocks: 706 emac_clks_teardown(adpt); 707 err_undo_netdev: 708 free_netdev(netdev); 709 710 return ret; 711 } 712 713 static int emac_remove(struct platform_device *pdev) 714 { 715 struct net_device *netdev = dev_get_drvdata(&pdev->dev); 716 struct emac_adapter *adpt = netdev_priv(netdev); 717 718 unregister_netdev(netdev); 719 netif_napi_del(&adpt->rx_q.napi); 720 721 emac_clks_teardown(adpt); 722 723 mdiobus_unregister(adpt->mii_bus); 724 free_netdev(netdev); 725 dev_set_drvdata(&pdev->dev, NULL); 726 727 return 0; 728 } 729 730 static struct platform_driver emac_platform_driver = { 731 .probe = emac_probe, 732 .remove = emac_remove, 733 .driver = { 734 .owner = THIS_MODULE, 735 .name = "qcom-emac", 736 .of_match_table = emac_dt_match, 737 }, 738 }; 739 740 module_platform_driver(emac_platform_driver); 741 742 MODULE_LICENSE("GPL v2"); 743 MODULE_ALIAS("platform:qcom-emac"); 744