1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver. 14 */ 15 16 #include <linux/iopoll.h> 17 #include <linux/acpi.h> 18 #include <linux/of_device.h> 19 #include "emac.h" 20 #include "emac-mac.h" 21 #include "emac-sgmii.h" 22 23 /* EMAC_SGMII register offsets */ 24 #define EMAC_SGMII_PHY_AUTONEG_CFG2 0x0048 25 #define EMAC_SGMII_PHY_SPEED_CFG1 0x0074 26 #define EMAC_SGMII_PHY_IRQ_CMD 0x00ac 27 #define EMAC_SGMII_PHY_INTERRUPT_CLEAR 0x00b0 28 #define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4 29 #define EMAC_SGMII_PHY_INTERRUPT_STATUS 0x00b8 30 #define EMAC_SGMII_PHY_RX_CHK_STATUS 0x00d4 31 32 #define FORCE_AN_TX_CFG BIT(5) 33 #define FORCE_AN_RX_CFG BIT(4) 34 #define AN_ENABLE BIT(0) 35 36 #define DUPLEX_MODE BIT(4) 37 #define SPDMODE_1000 BIT(1) 38 #define SPDMODE_100 BIT(0) 39 #define SPDMODE_10 0 40 41 #define CDR_ALIGN_DET BIT(6) 42 43 #define IRQ_GLOBAL_CLEAR BIT(0) 44 45 #define DECODE_CODE_ERR BIT(7) 46 #define DECODE_DISP_ERR BIT(6) 47 48 #define SGMII_PHY_IRQ_CLR_WAIT_TIME 10 49 50 #define SGMII_PHY_INTERRUPT_ERR (DECODE_CODE_ERR | DECODE_DISP_ERR) 51 #define SGMII_ISR_MASK (SGMII_PHY_INTERRUPT_ERR) 52 53 #define SERDES_START_WAIT_TIMES 100 54 55 /* Initialize the SGMII link between the internal and external PHYs. */ 56 static void emac_sgmii_link_init(struct emac_adapter *adpt) 57 { 58 struct emac_sgmii *phy = &adpt->phy; 59 u32 val; 60 61 /* Always use autonegotiation. It works no matter how the external 62 * PHY is configured. 63 */ 64 val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); 65 val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG); 66 val |= AN_ENABLE; 67 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); 68 } 69 70 static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u32 irq_bits) 71 { 72 struct emac_sgmii *phy = &adpt->phy; 73 u32 status; 74 75 writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); 76 writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD); 77 /* Ensure interrupt clear command is written to HW */ 78 wmb(); 79 80 /* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must 81 * be confirmed before clearing the bits in other registers. 82 * It takes a few cycles for hw to clear the interrupt status. 83 */ 84 if (readl_poll_timeout_atomic(phy->base + 85 EMAC_SGMII_PHY_INTERRUPT_STATUS, 86 status, !(status & irq_bits), 1, 87 SGMII_PHY_IRQ_CLR_WAIT_TIME)) { 88 netdev_err(adpt->netdev, 89 "error: failed clear SGMII irq: status:0x%x bits:0x%x\n", 90 status, irq_bits); 91 return -EIO; 92 } 93 94 /* Finalize clearing procedure */ 95 writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD); 96 writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); 97 98 /* Ensure that clearing procedure finalization is written to HW */ 99 wmb(); 100 101 return 0; 102 } 103 104 /* The number of decode errors that triggers a reset */ 105 #define DECODE_ERROR_LIMIT 2 106 107 static irqreturn_t emac_sgmii_interrupt(int irq, void *data) 108 { 109 struct emac_adapter *adpt = data; 110 struct emac_sgmii *phy = &adpt->phy; 111 u32 status; 112 113 status = readl(phy->base + EMAC_SGMII_PHY_INTERRUPT_STATUS); 114 status &= SGMII_ISR_MASK; 115 if (!status) 116 return IRQ_HANDLED; 117 118 /* If we get a decoding error and CDR is not locked, then try 119 * resetting the internal PHY. The internal PHY uses an embedded 120 * clock with Clock and Data Recovery (CDR) to recover the 121 * clock and data. 122 */ 123 if (status & SGMII_PHY_INTERRUPT_ERR) { 124 int count; 125 126 /* The SGMII is capable of recovering from some decode 127 * errors automatically. However, if we get multiple 128 * decode errors in a row, then assume that something 129 * is wrong and reset the interface. 130 */ 131 count = atomic_inc_return(&phy->decode_error_count); 132 if (count == DECODE_ERROR_LIMIT) { 133 schedule_work(&adpt->work_thread); 134 atomic_set(&phy->decode_error_count, 0); 135 } 136 } else { 137 /* We only care about consecutive decode errors. */ 138 atomic_set(&phy->decode_error_count, 0); 139 } 140 141 if (emac_sgmii_irq_clear(adpt, status)) { 142 netdev_warn(adpt->netdev, "failed to clear SGMII interrupt\n"); 143 schedule_work(&adpt->work_thread); 144 } 145 146 return IRQ_HANDLED; 147 } 148 149 static void emac_sgmii_reset_prepare(struct emac_adapter *adpt) 150 { 151 struct emac_sgmii *phy = &adpt->phy; 152 u32 val; 153 154 /* Reset PHY */ 155 val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); 156 writel(((val & ~PHY_RESET) | PHY_RESET), phy->base + 157 EMAC_EMAC_WRAPPER_CSR2); 158 /* Ensure phy-reset command is written to HW before the release cmd */ 159 msleep(50); 160 val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); 161 writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2); 162 /* Ensure phy-reset release command is written to HW before initializing 163 * SGMII 164 */ 165 msleep(50); 166 } 167 168 void emac_sgmii_reset(struct emac_adapter *adpt) 169 { 170 int ret; 171 172 emac_sgmii_reset_prepare(adpt); 173 emac_sgmii_link_init(adpt); 174 175 ret = adpt->phy.initialize(adpt); 176 if (ret) 177 netdev_err(adpt->netdev, 178 "could not reinitialize internal PHY (error=%i)\n", 179 ret); 180 } 181 182 static int emac_sgmii_open(struct emac_adapter *adpt) 183 { 184 struct emac_sgmii *sgmii = &adpt->phy; 185 int ret; 186 187 if (sgmii->irq) { 188 /* Make sure interrupts are cleared and disabled first */ 189 ret = emac_sgmii_irq_clear(adpt, 0xff); 190 if (ret) 191 return ret; 192 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); 193 194 ret = request_irq(sgmii->irq, emac_sgmii_interrupt, 0, 195 "emac-sgmii", adpt); 196 if (ret) { 197 netdev_err(adpt->netdev, 198 "could not register handler for internal PHY\n"); 199 return ret; 200 } 201 } 202 203 return 0; 204 } 205 206 static int emac_sgmii_close(struct emac_adapter *adpt) 207 { 208 struct emac_sgmii *sgmii = &adpt->phy; 209 210 /* Make sure interrupts are disabled */ 211 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); 212 free_irq(sgmii->irq, adpt); 213 214 return 0; 215 } 216 217 /* The error interrupts are only valid after the link is up */ 218 static int emac_sgmii_link_up(struct emac_adapter *adpt) 219 { 220 struct emac_sgmii *sgmii = &adpt->phy; 221 int ret; 222 223 /* Clear and enable interrupts */ 224 ret = emac_sgmii_irq_clear(adpt, 0xff); 225 if (ret) 226 return ret; 227 228 writel(SGMII_ISR_MASK, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); 229 230 return 0; 231 } 232 233 static int emac_sgmii_link_down(struct emac_adapter *adpt) 234 { 235 struct emac_sgmii *sgmii = &adpt->phy; 236 237 /* Disable interrupts */ 238 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); 239 synchronize_irq(sgmii->irq); 240 241 return 0; 242 } 243 244 static int emac_sgmii_acpi_match(struct device *dev, void *data) 245 { 246 #ifdef CONFIG_ACPI 247 static const struct acpi_device_id match_table[] = { 248 { 249 .id = "QCOM8071", 250 }, 251 {} 252 }; 253 const struct acpi_device_id *id = acpi_match_device(match_table, dev); 254 emac_sgmii_function *initialize = data; 255 256 if (id) { 257 acpi_handle handle = ACPI_HANDLE(dev); 258 unsigned long long hrv; 259 acpi_status status; 260 261 status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv); 262 if (status) { 263 if (status == AE_NOT_FOUND) 264 /* Older versions of the QDF2432 ACPI tables do 265 * not have an _HRV property. 266 */ 267 hrv = 1; 268 else 269 /* Something is wrong with the tables */ 270 return 0; 271 } 272 273 switch (hrv) { 274 case 1: 275 *initialize = emac_sgmii_init_qdf2432; 276 return 1; 277 case 2: 278 *initialize = emac_sgmii_init_qdf2400; 279 return 1; 280 } 281 } 282 #endif 283 284 return 0; 285 } 286 287 static const struct of_device_id emac_sgmii_dt_match[] = { 288 { 289 .compatible = "qcom,fsm9900-emac-sgmii", 290 .data = emac_sgmii_init_fsm9900, 291 }, 292 { 293 .compatible = "qcom,qdf2432-emac-sgmii", 294 .data = emac_sgmii_init_qdf2432, 295 }, 296 {} 297 }; 298 299 int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt) 300 { 301 struct platform_device *sgmii_pdev = NULL; 302 struct emac_sgmii *phy = &adpt->phy; 303 struct resource *res; 304 int ret; 305 306 if (has_acpi_companion(&pdev->dev)) { 307 struct device *dev; 308 309 dev = device_find_child(&pdev->dev, &phy->initialize, 310 emac_sgmii_acpi_match); 311 312 if (!dev) { 313 dev_err(&pdev->dev, "cannot find internal phy node\n"); 314 return -ENODEV; 315 } 316 317 sgmii_pdev = to_platform_device(dev); 318 } else { 319 const struct of_device_id *match; 320 struct device_node *np; 321 322 np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0); 323 if (!np) { 324 dev_err(&pdev->dev, "missing internal-phy property\n"); 325 return -ENODEV; 326 } 327 328 sgmii_pdev = of_find_device_by_node(np); 329 if (!sgmii_pdev) { 330 dev_err(&pdev->dev, "invalid internal-phy property\n"); 331 return -ENODEV; 332 } 333 334 match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev); 335 if (!match) { 336 dev_err(&pdev->dev, "unrecognized internal phy node\n"); 337 ret = -ENODEV; 338 goto error_put_device; 339 } 340 341 phy->initialize = (emac_sgmii_function)match->data; 342 } 343 344 phy->open = emac_sgmii_open; 345 phy->close = emac_sgmii_close; 346 phy->link_up = emac_sgmii_link_up; 347 phy->link_down = emac_sgmii_link_down; 348 349 /* Base address is the first address */ 350 res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0); 351 if (!res) { 352 ret = -EINVAL; 353 goto error_put_device; 354 } 355 356 phy->base = ioremap(res->start, resource_size(res)); 357 if (!phy->base) { 358 ret = -ENOMEM; 359 goto error_put_device; 360 } 361 362 /* v2 SGMII has a per-lane digital digital, so parse it if it exists */ 363 res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 1); 364 if (res) { 365 phy->digital = ioremap(res->start, resource_size(res)); 366 if (!phy->digital) { 367 ret = -ENOMEM; 368 goto error_unmap_base; 369 } 370 } 371 372 ret = phy->initialize(adpt); 373 if (ret) 374 goto error; 375 376 emac_sgmii_link_init(adpt); 377 378 ret = platform_get_irq(sgmii_pdev, 0); 379 if (ret > 0) 380 phy->irq = ret; 381 382 /* We've remapped the addresses, so we don't need the device any 383 * more. of_find_device_by_node() says we should release it. 384 */ 385 put_device(&sgmii_pdev->dev); 386 387 return 0; 388 389 error: 390 if (phy->digital) 391 iounmap(phy->digital); 392 error_unmap_base: 393 iounmap(phy->base); 394 error_put_device: 395 put_device(&sgmii_pdev->dev); 396 397 return ret; 398 } 399