1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 3 */ 4 5 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/iopoll.h> 10 #include <linux/acpi.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_platform.h> 14 #include "emac.h" 15 #include "emac-mac.h" 16 #include "emac-sgmii.h" 17 18 /* EMAC_SGMII register offsets */ 19 #define EMAC_SGMII_PHY_AUTONEG_CFG2 0x0048 20 #define EMAC_SGMII_PHY_SPEED_CFG1 0x0074 21 #define EMAC_SGMII_PHY_IRQ_CMD 0x00ac 22 #define EMAC_SGMII_PHY_INTERRUPT_CLEAR 0x00b0 23 #define EMAC_SGMII_PHY_INTERRUPT_MASK 0x00b4 24 #define EMAC_SGMII_PHY_INTERRUPT_STATUS 0x00b8 25 #define EMAC_SGMII_PHY_RX_CHK_STATUS 0x00d4 26 27 #define FORCE_AN_TX_CFG BIT(5) 28 #define FORCE_AN_RX_CFG BIT(4) 29 #define AN_ENABLE BIT(0) 30 31 #define DUPLEX_MODE BIT(4) 32 #define SPDMODE_1000 BIT(1) 33 #define SPDMODE_100 BIT(0) 34 #define SPDMODE_10 0 35 36 #define CDR_ALIGN_DET BIT(6) 37 38 #define IRQ_GLOBAL_CLEAR BIT(0) 39 40 #define DECODE_CODE_ERR BIT(7) 41 #define DECODE_DISP_ERR BIT(6) 42 43 #define SGMII_PHY_IRQ_CLR_WAIT_TIME 10 44 45 #define SGMII_PHY_INTERRUPT_ERR (DECODE_CODE_ERR | DECODE_DISP_ERR) 46 #define SGMII_ISR_MASK (SGMII_PHY_INTERRUPT_ERR) 47 48 #define SERDES_START_WAIT_TIMES 100 49 50 int emac_sgmii_init(struct emac_adapter *adpt) 51 { 52 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->init)) 53 return 0; 54 55 return adpt->phy.sgmii_ops->init(adpt); 56 } 57 58 int emac_sgmii_open(struct emac_adapter *adpt) 59 { 60 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->open)) 61 return 0; 62 63 return adpt->phy.sgmii_ops->open(adpt); 64 } 65 66 void emac_sgmii_close(struct emac_adapter *adpt) 67 { 68 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->close)) 69 return; 70 71 adpt->phy.sgmii_ops->close(adpt); 72 } 73 74 int emac_sgmii_link_change(struct emac_adapter *adpt, bool link_state) 75 { 76 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->link_change)) 77 return 0; 78 79 return adpt->phy.sgmii_ops->link_change(adpt, link_state); 80 } 81 82 void emac_sgmii_reset(struct emac_adapter *adpt) 83 { 84 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->reset)) 85 return; 86 87 adpt->phy.sgmii_ops->reset(adpt); 88 } 89 90 /* Initialize the SGMII link between the internal and external PHYs. */ 91 static void emac_sgmii_link_init(struct emac_adapter *adpt) 92 { 93 struct emac_sgmii *phy = &adpt->phy; 94 u32 val; 95 96 /* Always use autonegotiation. It works no matter how the external 97 * PHY is configured. 98 */ 99 val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); 100 val &= ~(FORCE_AN_RX_CFG | FORCE_AN_TX_CFG); 101 val |= AN_ENABLE; 102 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); 103 } 104 105 static int emac_sgmii_irq_clear(struct emac_adapter *adpt, u8 irq_bits) 106 { 107 struct emac_sgmii *phy = &adpt->phy; 108 u8 status; 109 110 writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); 111 writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD); 112 /* Ensure interrupt clear command is written to HW */ 113 wmb(); 114 115 /* After set the IRQ_GLOBAL_CLEAR bit, the status clearing must 116 * be confirmed before clearing the bits in other registers. 117 * It takes a few cycles for hw to clear the interrupt status. 118 */ 119 if (readl_poll_timeout_atomic(phy->base + 120 EMAC_SGMII_PHY_INTERRUPT_STATUS, 121 status, !(status & irq_bits), 1, 122 SGMII_PHY_IRQ_CLR_WAIT_TIME)) { 123 net_err_ratelimited("%s: failed to clear SGMII irq: status:0x%x bits:0x%x\n", 124 adpt->netdev->name, status, irq_bits); 125 return -EIO; 126 } 127 128 /* Finalize clearing procedure */ 129 writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD); 130 writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); 131 132 /* Ensure that clearing procedure finalization is written to HW */ 133 wmb(); 134 135 return 0; 136 } 137 138 /* The number of decode errors that triggers a reset */ 139 #define DECODE_ERROR_LIMIT 2 140 141 static irqreturn_t emac_sgmii_interrupt(int irq, void *data) 142 { 143 struct emac_adapter *adpt = data; 144 struct emac_sgmii *phy = &adpt->phy; 145 u8 status; 146 147 status = readl(phy->base + EMAC_SGMII_PHY_INTERRUPT_STATUS); 148 status &= SGMII_ISR_MASK; 149 if (!status) 150 return IRQ_HANDLED; 151 152 /* If we get a decoding error and CDR is not locked, then try 153 * resetting the internal PHY. The internal PHY uses an embedded 154 * clock with Clock and Data Recovery (CDR) to recover the 155 * clock and data. 156 */ 157 if (status & SGMII_PHY_INTERRUPT_ERR) { 158 int count; 159 160 /* The SGMII is capable of recovering from some decode 161 * errors automatically. However, if we get multiple 162 * decode errors in a row, then assume that something 163 * is wrong and reset the interface. 164 */ 165 count = atomic_inc_return(&phy->decode_error_count); 166 if (count == DECODE_ERROR_LIMIT) { 167 schedule_work(&adpt->work_thread); 168 atomic_set(&phy->decode_error_count, 0); 169 } 170 } else { 171 /* We only care about consecutive decode errors. */ 172 atomic_set(&phy->decode_error_count, 0); 173 } 174 175 if (emac_sgmii_irq_clear(adpt, status)) 176 schedule_work(&adpt->work_thread); 177 178 return IRQ_HANDLED; 179 } 180 181 static void emac_sgmii_reset_prepare(struct emac_adapter *adpt) 182 { 183 struct emac_sgmii *phy = &adpt->phy; 184 u32 val; 185 186 /* Reset PHY */ 187 val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); 188 writel(((val & ~PHY_RESET) | PHY_RESET), phy->base + 189 EMAC_EMAC_WRAPPER_CSR2); 190 /* Ensure phy-reset command is written to HW before the release cmd */ 191 msleep(50); 192 val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); 193 writel((val & ~PHY_RESET), phy->base + EMAC_EMAC_WRAPPER_CSR2); 194 /* Ensure phy-reset release command is written to HW before initializing 195 * SGMII 196 */ 197 msleep(50); 198 } 199 200 static void emac_sgmii_common_reset(struct emac_adapter *adpt) 201 { 202 int ret; 203 204 emac_sgmii_reset_prepare(adpt); 205 emac_sgmii_link_init(adpt); 206 207 ret = emac_sgmii_init(adpt); 208 if (ret) 209 netdev_err(adpt->netdev, 210 "could not reinitialize internal PHY (error=%i)\n", 211 ret); 212 } 213 214 static int emac_sgmii_common_open(struct emac_adapter *adpt) 215 { 216 struct emac_sgmii *sgmii = &adpt->phy; 217 int ret; 218 219 if (sgmii->irq) { 220 /* Make sure interrupts are cleared and disabled first */ 221 ret = emac_sgmii_irq_clear(adpt, 0xff); 222 if (ret) 223 return ret; 224 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); 225 226 ret = request_irq(sgmii->irq, emac_sgmii_interrupt, 0, 227 "emac-sgmii", adpt); 228 if (ret) { 229 netdev_err(adpt->netdev, 230 "could not register handler for internal PHY\n"); 231 return ret; 232 } 233 } 234 235 return 0; 236 } 237 238 static void emac_sgmii_common_close(struct emac_adapter *adpt) 239 { 240 struct emac_sgmii *sgmii = &adpt->phy; 241 242 /* Make sure interrupts are disabled */ 243 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); 244 free_irq(sgmii->irq, adpt); 245 } 246 247 /* The error interrupts are only valid after the link is up */ 248 static int emac_sgmii_common_link_change(struct emac_adapter *adpt, bool linkup) 249 { 250 struct emac_sgmii *sgmii = &adpt->phy; 251 int ret; 252 253 if (linkup) { 254 /* Clear and enable interrupts */ 255 ret = emac_sgmii_irq_clear(adpt, 0xff); 256 if (ret) 257 return ret; 258 259 writel(SGMII_ISR_MASK, 260 sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); 261 } else { 262 /* Disable interrupts */ 263 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); 264 synchronize_irq(sgmii->irq); 265 } 266 267 return 0; 268 } 269 270 static struct sgmii_ops fsm9900_ops = { 271 .init = emac_sgmii_init_fsm9900, 272 .open = emac_sgmii_common_open, 273 .close = emac_sgmii_common_close, 274 .link_change = emac_sgmii_common_link_change, 275 .reset = emac_sgmii_common_reset, 276 }; 277 278 static struct sgmii_ops qdf2432_ops = { 279 .init = emac_sgmii_init_qdf2432, 280 .open = emac_sgmii_common_open, 281 .close = emac_sgmii_common_close, 282 .link_change = emac_sgmii_common_link_change, 283 .reset = emac_sgmii_common_reset, 284 }; 285 286 #ifdef CONFIG_ACPI 287 static struct sgmii_ops qdf2400_ops = { 288 .init = emac_sgmii_init_qdf2400, 289 .open = emac_sgmii_common_open, 290 .close = emac_sgmii_common_close, 291 .link_change = emac_sgmii_common_link_change, 292 .reset = emac_sgmii_common_reset, 293 }; 294 #endif 295 296 static int emac_sgmii_acpi_match(struct device *dev, void *data) 297 { 298 #ifdef CONFIG_ACPI 299 static const struct acpi_device_id match_table[] = { 300 { 301 .id = "QCOM8071", 302 }, 303 {} 304 }; 305 const struct acpi_device_id *id = acpi_match_device(match_table, dev); 306 struct sgmii_ops **ops = data; 307 308 if (id) { 309 acpi_handle handle = ACPI_HANDLE(dev); 310 unsigned long long hrv; 311 acpi_status status; 312 313 status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv); 314 if (status) { 315 if (status == AE_NOT_FOUND) 316 /* Older versions of the QDF2432 ACPI tables do 317 * not have an _HRV property. 318 */ 319 hrv = 1; 320 else 321 /* Something is wrong with the tables */ 322 return 0; 323 } 324 325 switch (hrv) { 326 case 1: 327 *ops = &qdf2432_ops; 328 return 1; 329 case 2: 330 *ops = &qdf2400_ops; 331 return 1; 332 } 333 } 334 #endif 335 336 return 0; 337 } 338 339 static const struct of_device_id emac_sgmii_dt_match[] = { 340 { 341 .compatible = "qcom,fsm9900-emac-sgmii", 342 .data = &fsm9900_ops, 343 }, 344 { 345 .compatible = "qcom,qdf2432-emac-sgmii", 346 .data = &qdf2432_ops, 347 }, 348 {} 349 }; 350 351 int emac_sgmii_config(struct platform_device *pdev, struct emac_adapter *adpt) 352 { 353 struct platform_device *sgmii_pdev = NULL; 354 struct emac_sgmii *phy = &adpt->phy; 355 struct resource *res; 356 int ret; 357 358 if (has_acpi_companion(&pdev->dev)) { 359 struct device *dev; 360 361 dev = device_find_child(&pdev->dev, &phy->sgmii_ops, 362 emac_sgmii_acpi_match); 363 364 if (!dev) { 365 dev_warn(&pdev->dev, "cannot find internal phy node\n"); 366 return 0; 367 } 368 369 sgmii_pdev = to_platform_device(dev); 370 } else { 371 const struct of_device_id *match; 372 struct device_node *np; 373 374 np = of_parse_phandle(pdev->dev.of_node, "internal-phy", 0); 375 if (!np) { 376 dev_err(&pdev->dev, "missing internal-phy property\n"); 377 return -ENODEV; 378 } 379 380 sgmii_pdev = of_find_device_by_node(np); 381 of_node_put(np); 382 if (!sgmii_pdev) { 383 dev_err(&pdev->dev, "invalid internal-phy property\n"); 384 return -ENODEV; 385 } 386 387 match = of_match_device(emac_sgmii_dt_match, &sgmii_pdev->dev); 388 if (!match) { 389 dev_err(&pdev->dev, "unrecognized internal phy node\n"); 390 ret = -ENODEV; 391 goto error_put_device; 392 } 393 394 phy->sgmii_ops = (struct sgmii_ops *)match->data; 395 } 396 397 /* Base address is the first address */ 398 res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 0); 399 if (!res) { 400 ret = -EINVAL; 401 goto error_put_device; 402 } 403 404 phy->base = ioremap(res->start, resource_size(res)); 405 if (!phy->base) { 406 ret = -ENOMEM; 407 goto error_put_device; 408 } 409 410 /* v2 SGMII has a per-lane digital digital, so parse it if it exists */ 411 res = platform_get_resource(sgmii_pdev, IORESOURCE_MEM, 1); 412 if (res) { 413 phy->digital = ioremap(res->start, resource_size(res)); 414 if (!phy->digital) { 415 ret = -ENOMEM; 416 goto error_unmap_base; 417 } 418 } 419 420 ret = emac_sgmii_init(adpt); 421 if (ret) 422 goto error; 423 424 emac_sgmii_link_init(adpt); 425 426 ret = platform_get_irq(sgmii_pdev, 0); 427 if (ret > 0) 428 phy->irq = ret; 429 430 /* We've remapped the addresses, so we don't need the device any 431 * more. of_find_device_by_node() says we should release it. 432 */ 433 put_device(&sgmii_pdev->dev); 434 435 return 0; 436 437 error: 438 if (phy->digital) 439 iounmap(phy->digital); 440 error_unmap_base: 441 iounmap(phy->base); 442 error_put_device: 443 put_device(&sgmii_pdev->dev); 444 445 return ret; 446 } 447