1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic qlcnic NIC Driver 4 * Copyright (c) 2009-2013 QLogic Corporation 5 */ 6 7 #include <linux/types.h> 8 9 #include "qlcnic_sriov.h" 10 #include "qlcnic.h" 11 #include "qlcnic_83xx_hw.h" 12 13 #define QLC_BC_COMMAND 0 14 #define QLC_BC_RESPONSE 1 15 16 #define QLC_MBOX_RESP_TIMEOUT (10 * HZ) 17 #define QLC_MBOX_CH_FREE_TIMEOUT (10 * HZ) 18 19 #define QLC_BC_MSG 0 20 #define QLC_BC_CFREE 1 21 #define QLC_BC_FLR 2 22 #define QLC_BC_HDR_SZ 16 23 #define QLC_BC_PAYLOAD_SZ (1024 - QLC_BC_HDR_SZ) 24 25 #define QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF 2048 26 #define QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF 512 27 28 #define QLC_83XX_VF_RESET_FAIL_THRESH 8 29 #define QLC_BC_CMD_MAX_RETRY_CNT 5 30 31 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work); 32 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *); 33 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *, u32); 34 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *); 35 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *); 36 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *); 37 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *, 38 struct qlcnic_cmd_args *); 39 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *, u8); 40 static void qlcnic_sriov_process_bc_cmd(struct work_struct *); 41 static int qlcnic_sriov_vf_shutdown(struct pci_dev *); 42 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *); 43 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *, 44 struct qlcnic_cmd_args *); 45 46 static struct qlcnic_hardware_ops qlcnic_sriov_vf_hw_ops = { 47 .read_crb = qlcnic_83xx_read_crb, 48 .write_crb = qlcnic_83xx_write_crb, 49 .read_reg = qlcnic_83xx_rd_reg_indirect, 50 .write_reg = qlcnic_83xx_wrt_reg_indirect, 51 .get_mac_address = qlcnic_83xx_get_mac_address, 52 .setup_intr = qlcnic_83xx_setup_intr, 53 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args, 54 .mbx_cmd = qlcnic_sriov_issue_cmd, 55 .get_func_no = qlcnic_83xx_get_func_no, 56 .api_lock = qlcnic_83xx_cam_lock, 57 .api_unlock = qlcnic_83xx_cam_unlock, 58 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag, 59 .create_rx_ctx = qlcnic_83xx_create_rx_ctx, 60 .create_tx_ctx = qlcnic_83xx_create_tx_ctx, 61 .del_rx_ctx = qlcnic_83xx_del_rx_ctx, 62 .del_tx_ctx = qlcnic_83xx_del_tx_ctx, 63 .setup_link_event = qlcnic_83xx_setup_link_event, 64 .get_nic_info = qlcnic_83xx_get_nic_info, 65 .get_pci_info = qlcnic_83xx_get_pci_info, 66 .set_nic_info = qlcnic_83xx_set_nic_info, 67 .change_macvlan = qlcnic_83xx_sre_macaddr_change, 68 .napi_enable = qlcnic_83xx_napi_enable, 69 .napi_disable = qlcnic_83xx_napi_disable, 70 .config_intr_coal = qlcnic_83xx_config_intr_coal, 71 .config_rss = qlcnic_83xx_config_rss, 72 .config_hw_lro = qlcnic_83xx_config_hw_lro, 73 .config_promisc_mode = qlcnic_83xx_nic_set_promisc, 74 .change_l2_filter = qlcnic_83xx_change_l2_filter, 75 .get_board_info = qlcnic_83xx_get_port_info, 76 .free_mac_list = qlcnic_sriov_vf_free_mac_list, 77 .enable_sds_intr = qlcnic_83xx_enable_sds_intr, 78 .disable_sds_intr = qlcnic_83xx_disable_sds_intr, 79 .encap_rx_offload = qlcnic_83xx_encap_rx_offload, 80 .encap_tx_offload = qlcnic_83xx_encap_tx_offload, 81 }; 82 83 static struct qlcnic_nic_template qlcnic_sriov_vf_ops = { 84 .config_bridged_mode = qlcnic_config_bridged_mode, 85 .config_led = qlcnic_config_led, 86 .cancel_idc_work = qlcnic_sriov_vf_cancel_fw_work, 87 .napi_add = qlcnic_83xx_napi_add, 88 .napi_del = qlcnic_83xx_napi_del, 89 .shutdown = qlcnic_sriov_vf_shutdown, 90 .resume = qlcnic_sriov_vf_resume, 91 .config_ipaddr = qlcnic_83xx_config_ipaddr, 92 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr, 93 }; 94 95 static const struct qlcnic_mailbox_metadata qlcnic_sriov_bc_mbx_tbl[] = { 96 {QLCNIC_BC_CMD_CHANNEL_INIT, 2, 2}, 97 {QLCNIC_BC_CMD_CHANNEL_TERM, 2, 2}, 98 {QLCNIC_BC_CMD_GET_ACL, 3, 14}, 99 {QLCNIC_BC_CMD_CFG_GUEST_VLAN, 2, 2}, 100 }; 101 102 static inline bool qlcnic_sriov_bc_msg_check(u32 val) 103 { 104 return (val & (1 << QLC_BC_MSG)) ? true : false; 105 } 106 107 static inline bool qlcnic_sriov_channel_free_check(u32 val) 108 { 109 return (val & (1 << QLC_BC_CFREE)) ? true : false; 110 } 111 112 static inline bool qlcnic_sriov_flr_check(u32 val) 113 { 114 return (val & (1 << QLC_BC_FLR)) ? true : false; 115 } 116 117 static inline u8 qlcnic_sriov_target_func_id(u32 val) 118 { 119 return (val >> 4) & 0xff; 120 } 121 122 static int qlcnic_sriov_virtid_fn(struct qlcnic_adapter *adapter, int vf_id) 123 { 124 struct pci_dev *dev = adapter->pdev; 125 int pos; 126 u16 stride, offset; 127 128 if (qlcnic_sriov_vf_check(adapter)) 129 return 0; 130 131 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); 132 if (!pos) 133 return 0; 134 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset); 135 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride); 136 137 return (dev->devfn + offset + stride * vf_id) & 0xff; 138 } 139 140 int qlcnic_sriov_init(struct qlcnic_adapter *adapter, int num_vfs) 141 { 142 struct qlcnic_sriov *sriov; 143 struct qlcnic_back_channel *bc; 144 struct workqueue_struct *wq; 145 struct qlcnic_vport *vp; 146 struct qlcnic_vf_info *vf; 147 int err, i; 148 149 if (!qlcnic_sriov_enable_check(adapter)) 150 return -EIO; 151 152 sriov = kzalloc(sizeof(struct qlcnic_sriov), GFP_KERNEL); 153 if (!sriov) 154 return -ENOMEM; 155 156 adapter->ahw->sriov = sriov; 157 sriov->num_vfs = num_vfs; 158 bc = &sriov->bc; 159 sriov->vf_info = kcalloc(num_vfs, sizeof(struct qlcnic_vf_info), 160 GFP_KERNEL); 161 if (!sriov->vf_info) { 162 err = -ENOMEM; 163 goto qlcnic_free_sriov; 164 } 165 166 wq = create_singlethread_workqueue("bc-trans"); 167 if (wq == NULL) { 168 err = -ENOMEM; 169 dev_err(&adapter->pdev->dev, 170 "Cannot create bc-trans workqueue\n"); 171 goto qlcnic_free_vf_info; 172 } 173 174 bc->bc_trans_wq = wq; 175 176 wq = create_singlethread_workqueue("async"); 177 if (wq == NULL) { 178 err = -ENOMEM; 179 dev_err(&adapter->pdev->dev, "Cannot create async workqueue\n"); 180 goto qlcnic_destroy_trans_wq; 181 } 182 183 bc->bc_async_wq = wq; 184 INIT_LIST_HEAD(&bc->async_cmd_list); 185 INIT_WORK(&bc->vf_async_work, qlcnic_sriov_handle_async_issue_cmd); 186 spin_lock_init(&bc->queue_lock); 187 bc->adapter = adapter; 188 189 for (i = 0; i < num_vfs; i++) { 190 vf = &sriov->vf_info[i]; 191 vf->adapter = adapter; 192 vf->pci_func = qlcnic_sriov_virtid_fn(adapter, i); 193 mutex_init(&vf->send_cmd_lock); 194 spin_lock_init(&vf->vlan_list_lock); 195 INIT_LIST_HEAD(&vf->rcv_act.wait_list); 196 INIT_LIST_HEAD(&vf->rcv_pend.wait_list); 197 spin_lock_init(&vf->rcv_act.lock); 198 spin_lock_init(&vf->rcv_pend.lock); 199 init_completion(&vf->ch_free_cmpl); 200 201 INIT_WORK(&vf->trans_work, qlcnic_sriov_process_bc_cmd); 202 203 if (qlcnic_sriov_pf_check(adapter)) { 204 vp = kzalloc(sizeof(struct qlcnic_vport), GFP_KERNEL); 205 if (!vp) { 206 err = -ENOMEM; 207 goto qlcnic_destroy_async_wq; 208 } 209 sriov->vf_info[i].vp = vp; 210 vp->vlan_mode = QLC_GUEST_VLAN_MODE; 211 vp->max_tx_bw = MAX_BW; 212 vp->min_tx_bw = MIN_BW; 213 vp->spoofchk = false; 214 eth_random_addr(vp->mac); 215 dev_info(&adapter->pdev->dev, 216 "MAC Address %pM is configured for VF %d\n", 217 vp->mac, i); 218 } 219 } 220 221 return 0; 222 223 qlcnic_destroy_async_wq: 224 destroy_workqueue(bc->bc_async_wq); 225 226 qlcnic_destroy_trans_wq: 227 destroy_workqueue(bc->bc_trans_wq); 228 229 qlcnic_free_vf_info: 230 kfree(sriov->vf_info); 231 232 qlcnic_free_sriov: 233 kfree(adapter->ahw->sriov); 234 return err; 235 } 236 237 void qlcnic_sriov_cleanup_list(struct qlcnic_trans_list *t_list) 238 { 239 struct qlcnic_bc_trans *trans; 240 struct qlcnic_cmd_args cmd; 241 unsigned long flags; 242 243 spin_lock_irqsave(&t_list->lock, flags); 244 245 while (!list_empty(&t_list->wait_list)) { 246 trans = list_first_entry(&t_list->wait_list, 247 struct qlcnic_bc_trans, list); 248 list_del(&trans->list); 249 t_list->count--; 250 cmd.req.arg = (u32 *)trans->req_pay; 251 cmd.rsp.arg = (u32 *)trans->rsp_pay; 252 qlcnic_free_mbx_args(&cmd); 253 qlcnic_sriov_cleanup_transaction(trans); 254 } 255 256 spin_unlock_irqrestore(&t_list->lock, flags); 257 } 258 259 void __qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter) 260 { 261 struct qlcnic_sriov *sriov = adapter->ahw->sriov; 262 struct qlcnic_back_channel *bc = &sriov->bc; 263 struct qlcnic_vf_info *vf; 264 int i; 265 266 if (!qlcnic_sriov_enable_check(adapter)) 267 return; 268 269 qlcnic_sriov_cleanup_async_list(bc); 270 destroy_workqueue(bc->bc_async_wq); 271 272 for (i = 0; i < sriov->num_vfs; i++) { 273 vf = &sriov->vf_info[i]; 274 qlcnic_sriov_cleanup_list(&vf->rcv_pend); 275 cancel_work_sync(&vf->trans_work); 276 qlcnic_sriov_cleanup_list(&vf->rcv_act); 277 } 278 279 destroy_workqueue(bc->bc_trans_wq); 280 281 for (i = 0; i < sriov->num_vfs; i++) 282 kfree(sriov->vf_info[i].vp); 283 284 kfree(sriov->vf_info); 285 kfree(adapter->ahw->sriov); 286 } 287 288 static void qlcnic_sriov_vf_cleanup(struct qlcnic_adapter *adapter) 289 { 290 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM); 291 qlcnic_sriov_cfg_bc_intr(adapter, 0); 292 __qlcnic_sriov_cleanup(adapter); 293 } 294 295 void qlcnic_sriov_cleanup(struct qlcnic_adapter *adapter) 296 { 297 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state)) 298 return; 299 300 qlcnic_sriov_free_vlans(adapter); 301 302 if (qlcnic_sriov_pf_check(adapter)) 303 qlcnic_sriov_pf_cleanup(adapter); 304 305 if (qlcnic_sriov_vf_check(adapter)) 306 qlcnic_sriov_vf_cleanup(adapter); 307 } 308 309 static int qlcnic_sriov_post_bc_msg(struct qlcnic_adapter *adapter, u32 *hdr, 310 u32 *pay, u8 pci_func, u8 size) 311 { 312 struct qlcnic_hardware_context *ahw = adapter->ahw; 313 struct qlcnic_mailbox *mbx = ahw->mailbox; 314 struct qlcnic_cmd_args cmd; 315 unsigned long timeout; 316 int err; 317 318 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args)); 319 cmd.hdr = hdr; 320 cmd.pay = pay; 321 cmd.pay_size = size; 322 cmd.func_num = pci_func; 323 cmd.op_type = QLC_83XX_MBX_POST_BC_OP; 324 cmd.cmd_op = ((struct qlcnic_bc_hdr *)hdr)->cmd_op; 325 326 err = mbx->ops->enqueue_cmd(adapter, &cmd, &timeout); 327 if (err) { 328 dev_err(&adapter->pdev->dev, 329 "%s: Mailbox not available, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 330 __func__, cmd.cmd_op, cmd.type, ahw->pci_func, 331 ahw->op_mode); 332 return err; 333 } 334 335 if (!wait_for_completion_timeout(&cmd.completion, timeout)) { 336 dev_err(&adapter->pdev->dev, 337 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n", 338 __func__, cmd.cmd_op, cmd.type, ahw->pci_func, 339 ahw->op_mode); 340 flush_workqueue(mbx->work_q); 341 } 342 343 return cmd.rsp_opcode; 344 } 345 346 static void qlcnic_sriov_vf_cfg_buff_desc(struct qlcnic_adapter *adapter) 347 { 348 adapter->num_rxd = QLC_DEFAULT_RCV_DESCRIPTORS_SRIOV_VF; 349 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G; 350 adapter->num_jumbo_rxd = QLC_DEFAULT_JUMBO_RCV_DESCRIPTORS_SRIOV_VF; 351 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G; 352 adapter->num_txd = MAX_CMD_DESCRIPTORS; 353 adapter->max_rds_rings = MAX_RDS_RINGS; 354 } 355 356 int qlcnic_sriov_get_vf_vport_info(struct qlcnic_adapter *adapter, 357 struct qlcnic_info *npar_info, u16 vport_id) 358 { 359 struct device *dev = &adapter->pdev->dev; 360 struct qlcnic_cmd_args cmd; 361 int err; 362 u32 status; 363 364 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO); 365 if (err) 366 return err; 367 368 cmd.req.arg[1] = vport_id << 16 | 0x1; 369 err = qlcnic_issue_cmd(adapter, &cmd); 370 if (err) { 371 dev_err(&adapter->pdev->dev, 372 "Failed to get vport info, err=%d\n", err); 373 qlcnic_free_mbx_args(&cmd); 374 return err; 375 } 376 377 status = cmd.rsp.arg[2] & 0xffff; 378 if (status & BIT_0) 379 npar_info->min_tx_bw = MSW(cmd.rsp.arg[2]); 380 if (status & BIT_1) 381 npar_info->max_tx_bw = LSW(cmd.rsp.arg[3]); 382 if (status & BIT_2) 383 npar_info->max_tx_ques = MSW(cmd.rsp.arg[3]); 384 if (status & BIT_3) 385 npar_info->max_tx_mac_filters = LSW(cmd.rsp.arg[4]); 386 if (status & BIT_4) 387 npar_info->max_rx_mcast_mac_filters = MSW(cmd.rsp.arg[4]); 388 if (status & BIT_5) 389 npar_info->max_rx_ucast_mac_filters = LSW(cmd.rsp.arg[5]); 390 if (status & BIT_6) 391 npar_info->max_rx_ip_addr = MSW(cmd.rsp.arg[5]); 392 if (status & BIT_7) 393 npar_info->max_rx_lro_flow = LSW(cmd.rsp.arg[6]); 394 if (status & BIT_8) 395 npar_info->max_rx_status_rings = MSW(cmd.rsp.arg[6]); 396 if (status & BIT_9) 397 npar_info->max_rx_buf_rings = LSW(cmd.rsp.arg[7]); 398 399 npar_info->max_rx_ques = MSW(cmd.rsp.arg[7]); 400 npar_info->max_tx_vlan_keys = LSW(cmd.rsp.arg[8]); 401 npar_info->max_local_ipv6_addrs = MSW(cmd.rsp.arg[8]); 402 npar_info->max_remote_ipv6_addrs = LSW(cmd.rsp.arg[9]); 403 404 dev_info(dev, "\n\tmin_tx_bw: %d, max_tx_bw: %d max_tx_ques: %d,\n" 405 "\tmax_tx_mac_filters: %d max_rx_mcast_mac_filters: %d,\n" 406 "\tmax_rx_ucast_mac_filters: 0x%x, max_rx_ip_addr: %d,\n" 407 "\tmax_rx_lro_flow: %d max_rx_status_rings: %d,\n" 408 "\tmax_rx_buf_rings: %d, max_rx_ques: %d, max_tx_vlan_keys %d\n" 409 "\tlocal_ipv6_addr: %d, remote_ipv6_addr: %d\n", 410 npar_info->min_tx_bw, npar_info->max_tx_bw, 411 npar_info->max_tx_ques, npar_info->max_tx_mac_filters, 412 npar_info->max_rx_mcast_mac_filters, 413 npar_info->max_rx_ucast_mac_filters, npar_info->max_rx_ip_addr, 414 npar_info->max_rx_lro_flow, npar_info->max_rx_status_rings, 415 npar_info->max_rx_buf_rings, npar_info->max_rx_ques, 416 npar_info->max_tx_vlan_keys, npar_info->max_local_ipv6_addrs, 417 npar_info->max_remote_ipv6_addrs); 418 419 qlcnic_free_mbx_args(&cmd); 420 return err; 421 } 422 423 static int qlcnic_sriov_set_pvid_mode(struct qlcnic_adapter *adapter, 424 struct qlcnic_cmd_args *cmd) 425 { 426 adapter->rx_pvid = MSW(cmd->rsp.arg[1]) & 0xffff; 427 adapter->flags &= ~QLCNIC_TAGGING_ENABLED; 428 return 0; 429 } 430 431 static int qlcnic_sriov_set_guest_vlan_mode(struct qlcnic_adapter *adapter, 432 struct qlcnic_cmd_args *cmd) 433 { 434 struct qlcnic_sriov *sriov = adapter->ahw->sriov; 435 int i, num_vlans, ret; 436 u16 *vlans; 437 438 if (sriov->allowed_vlans) 439 return 0; 440 441 sriov->any_vlan = cmd->rsp.arg[2] & 0xf; 442 sriov->num_allowed_vlans = cmd->rsp.arg[2] >> 16; 443 dev_info(&adapter->pdev->dev, "Number of allowed Guest VLANs = %d\n", 444 sriov->num_allowed_vlans); 445 446 ret = qlcnic_sriov_alloc_vlans(adapter); 447 if (ret) 448 return ret; 449 450 if (!sriov->any_vlan) 451 return 0; 452 453 num_vlans = sriov->num_allowed_vlans; 454 sriov->allowed_vlans = kcalloc(num_vlans, sizeof(u16), GFP_KERNEL); 455 if (!sriov->allowed_vlans) 456 return -ENOMEM; 457 458 vlans = (u16 *)&cmd->rsp.arg[3]; 459 for (i = 0; i < num_vlans; i++) 460 sriov->allowed_vlans[i] = vlans[i]; 461 462 return 0; 463 } 464 465 static int qlcnic_sriov_get_vf_acl(struct qlcnic_adapter *adapter) 466 { 467 struct qlcnic_sriov *sriov = adapter->ahw->sriov; 468 struct qlcnic_cmd_args cmd; 469 int ret = 0; 470 471 memset(&cmd, 0, sizeof(cmd)); 472 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd, QLCNIC_BC_CMD_GET_ACL); 473 if (ret) 474 return ret; 475 476 ret = qlcnic_issue_cmd(adapter, &cmd); 477 if (ret) { 478 dev_err(&adapter->pdev->dev, "Failed to get ACL, err=%d\n", 479 ret); 480 } else { 481 sriov->vlan_mode = cmd.rsp.arg[1] & 0x3; 482 switch (sriov->vlan_mode) { 483 case QLC_GUEST_VLAN_MODE: 484 ret = qlcnic_sriov_set_guest_vlan_mode(adapter, &cmd); 485 break; 486 case QLC_PVID_MODE: 487 ret = qlcnic_sriov_set_pvid_mode(adapter, &cmd); 488 break; 489 } 490 } 491 492 qlcnic_free_mbx_args(&cmd); 493 return ret; 494 } 495 496 static int qlcnic_sriov_vf_init_driver(struct qlcnic_adapter *adapter) 497 { 498 struct qlcnic_hardware_context *ahw = adapter->ahw; 499 struct qlcnic_info nic_info; 500 int err; 501 502 err = qlcnic_sriov_get_vf_vport_info(adapter, &nic_info, 0); 503 if (err) 504 return err; 505 506 ahw->max_mc_count = nic_info.max_rx_mcast_mac_filters; 507 508 err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func); 509 if (err) 510 return -EIO; 511 512 if (qlcnic_83xx_get_port_info(adapter)) 513 return -EIO; 514 515 qlcnic_sriov_vf_cfg_buff_desc(adapter); 516 adapter->flags |= QLCNIC_ADAPTER_INITIALIZED; 517 dev_info(&adapter->pdev->dev, "HAL Version: %d\n", 518 adapter->ahw->fw_hal_version); 519 520 ahw->physical_port = (u8) nic_info.phys_port; 521 ahw->switch_mode = nic_info.switch_mode; 522 ahw->max_mtu = nic_info.max_mtu; 523 ahw->op_mode = nic_info.op_mode; 524 ahw->capabilities = nic_info.capabilities; 525 return 0; 526 } 527 528 static int qlcnic_sriov_setup_vf(struct qlcnic_adapter *adapter, 529 int pci_using_dac) 530 { 531 int err; 532 533 adapter->flags |= QLCNIC_VLAN_FILTERING; 534 adapter->ahw->total_nic_func = 1; 535 INIT_LIST_HEAD(&adapter->vf_mc_list); 536 if (!qlcnic_use_msi_x && !!qlcnic_use_msi) 537 dev_warn(&adapter->pdev->dev, 538 "Device does not support MSI interrupts\n"); 539 540 /* compute and set default and max tx/sds rings */ 541 qlcnic_set_tx_ring_count(adapter, QLCNIC_SINGLE_RING); 542 qlcnic_set_sds_ring_count(adapter, QLCNIC_SINGLE_RING); 543 544 err = qlcnic_setup_intr(adapter); 545 if (err) { 546 dev_err(&adapter->pdev->dev, "Failed to setup interrupt\n"); 547 goto err_out_disable_msi; 548 } 549 550 err = qlcnic_83xx_setup_mbx_intr(adapter); 551 if (err) 552 goto err_out_disable_msi; 553 554 err = qlcnic_sriov_init(adapter, 1); 555 if (err) 556 goto err_out_disable_mbx_intr; 557 558 err = qlcnic_sriov_cfg_bc_intr(adapter, 1); 559 if (err) 560 goto err_out_cleanup_sriov; 561 562 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT); 563 if (err) 564 goto err_out_disable_bc_intr; 565 566 err = qlcnic_sriov_vf_init_driver(adapter); 567 if (err) 568 goto err_out_send_channel_term; 569 570 err = qlcnic_sriov_get_vf_acl(adapter); 571 if (err) 572 goto err_out_send_channel_term; 573 574 err = qlcnic_setup_netdev(adapter, adapter->netdev, pci_using_dac); 575 if (err) 576 goto err_out_send_channel_term; 577 578 pci_set_drvdata(adapter->pdev, adapter); 579 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n", 580 adapter->netdev->name); 581 582 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state, 583 adapter->ahw->idc.delay); 584 return 0; 585 586 err_out_send_channel_term: 587 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM); 588 589 err_out_disable_bc_intr: 590 qlcnic_sriov_cfg_bc_intr(adapter, 0); 591 592 err_out_cleanup_sriov: 593 __qlcnic_sriov_cleanup(adapter); 594 595 err_out_disable_mbx_intr: 596 qlcnic_83xx_free_mbx_intr(adapter); 597 598 err_out_disable_msi: 599 qlcnic_teardown_intr(adapter); 600 return err; 601 } 602 603 static int qlcnic_sriov_check_dev_ready(struct qlcnic_adapter *adapter) 604 { 605 u32 state; 606 607 do { 608 msleep(20); 609 if (++adapter->fw_fail_cnt > QLC_BC_CMD_MAX_RETRY_CNT) 610 return -EIO; 611 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 612 } while (state != QLC_83XX_IDC_DEV_READY); 613 614 return 0; 615 } 616 617 int qlcnic_sriov_vf_init(struct qlcnic_adapter *adapter, int pci_using_dac) 618 { 619 struct qlcnic_hardware_context *ahw = adapter->ahw; 620 int err; 621 622 set_bit(QLC_83XX_MODULE_LOADED, &ahw->idc.status); 623 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; 624 ahw->reset_context = 0; 625 adapter->fw_fail_cnt = 0; 626 ahw->msix_supported = 1; 627 adapter->need_fw_reset = 0; 628 adapter->flags |= QLCNIC_TX_INTR_SHARED; 629 630 err = qlcnic_sriov_check_dev_ready(adapter); 631 if (err) 632 return err; 633 634 err = qlcnic_sriov_setup_vf(adapter, pci_using_dac); 635 if (err) 636 return err; 637 638 if (qlcnic_read_mac_addr(adapter)) 639 dev_warn(&adapter->pdev->dev, "failed to read mac addr\n"); 640 641 INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work); 642 643 clear_bit(__QLCNIC_RESETTING, &adapter->state); 644 return 0; 645 } 646 647 void qlcnic_sriov_vf_set_ops(struct qlcnic_adapter *adapter) 648 { 649 struct qlcnic_hardware_context *ahw = adapter->ahw; 650 651 ahw->op_mode = QLCNIC_SRIOV_VF_FUNC; 652 dev_info(&adapter->pdev->dev, 653 "HAL Version: %d Non Privileged SRIOV function\n", 654 ahw->fw_hal_version); 655 adapter->nic_ops = &qlcnic_sriov_vf_ops; 656 set_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state); 657 return; 658 } 659 660 void qlcnic_sriov_vf_register_map(struct qlcnic_hardware_context *ahw) 661 { 662 ahw->hw_ops = &qlcnic_sriov_vf_hw_ops; 663 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; 664 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl; 665 } 666 667 static u32 qlcnic_sriov_get_bc_paysize(u32 real_pay_size, u8 curr_frag) 668 { 669 u32 pay_size; 670 671 pay_size = real_pay_size / ((curr_frag + 1) * QLC_BC_PAYLOAD_SZ); 672 673 if (pay_size) 674 pay_size = QLC_BC_PAYLOAD_SZ; 675 else 676 pay_size = real_pay_size % QLC_BC_PAYLOAD_SZ; 677 678 return pay_size; 679 } 680 681 int qlcnic_sriov_func_to_index(struct qlcnic_adapter *adapter, u8 pci_func) 682 { 683 struct qlcnic_vf_info *vf_info = adapter->ahw->sriov->vf_info; 684 u8 i; 685 686 if (qlcnic_sriov_vf_check(adapter)) 687 return 0; 688 689 for (i = 0; i < adapter->ahw->sriov->num_vfs; i++) { 690 if (vf_info[i].pci_func == pci_func) 691 return i; 692 } 693 694 return -EINVAL; 695 } 696 697 static inline int qlcnic_sriov_alloc_bc_trans(struct qlcnic_bc_trans **trans) 698 { 699 *trans = kzalloc(sizeof(struct qlcnic_bc_trans), GFP_ATOMIC); 700 if (!*trans) 701 return -ENOMEM; 702 703 init_completion(&(*trans)->resp_cmpl); 704 return 0; 705 } 706 707 static inline int qlcnic_sriov_alloc_bc_msg(struct qlcnic_bc_hdr **hdr, 708 u32 size) 709 { 710 *hdr = kcalloc(size, sizeof(struct qlcnic_bc_hdr), GFP_ATOMIC); 711 if (!*hdr) 712 return -ENOMEM; 713 714 return 0; 715 } 716 717 static int qlcnic_sriov_alloc_bc_mbx_args(struct qlcnic_cmd_args *mbx, u32 type) 718 { 719 const struct qlcnic_mailbox_metadata *mbx_tbl; 720 int i, size; 721 722 mbx_tbl = qlcnic_sriov_bc_mbx_tbl; 723 size = ARRAY_SIZE(qlcnic_sriov_bc_mbx_tbl); 724 725 for (i = 0; i < size; i++) { 726 if (type == mbx_tbl[i].cmd) { 727 mbx->op_type = QLC_BC_CMD; 728 mbx->req.num = mbx_tbl[i].in_args; 729 mbx->rsp.num = mbx_tbl[i].out_args; 730 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32), 731 GFP_ATOMIC); 732 if (!mbx->req.arg) 733 return -ENOMEM; 734 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32), 735 GFP_ATOMIC); 736 if (!mbx->rsp.arg) { 737 kfree(mbx->req.arg); 738 mbx->req.arg = NULL; 739 return -ENOMEM; 740 } 741 mbx->req.arg[0] = (type | (mbx->req.num << 16) | 742 (3 << 29)); 743 mbx->rsp.arg[0] = (type & 0xffff) | mbx->rsp.num << 16; 744 return 0; 745 } 746 } 747 return -EINVAL; 748 } 749 750 static int qlcnic_sriov_prepare_bc_hdr(struct qlcnic_bc_trans *trans, 751 struct qlcnic_cmd_args *cmd, 752 u16 seq, u8 msg_type) 753 { 754 struct qlcnic_bc_hdr *hdr; 755 int i; 756 u32 num_regs, bc_pay_sz; 757 u16 remainder; 758 u8 cmd_op, num_frags, t_num_frags; 759 760 bc_pay_sz = QLC_BC_PAYLOAD_SZ; 761 if (msg_type == QLC_BC_COMMAND) { 762 trans->req_pay = (struct qlcnic_bc_payload *)cmd->req.arg; 763 trans->rsp_pay = (struct qlcnic_bc_payload *)cmd->rsp.arg; 764 num_regs = cmd->req.num; 765 trans->req_pay_size = (num_regs * 4); 766 num_regs = cmd->rsp.num; 767 trans->rsp_pay_size = (num_regs * 4); 768 cmd_op = cmd->req.arg[0] & 0xff; 769 remainder = (trans->req_pay_size) % (bc_pay_sz); 770 num_frags = (trans->req_pay_size) / (bc_pay_sz); 771 if (remainder) 772 num_frags++; 773 t_num_frags = num_frags; 774 if (qlcnic_sriov_alloc_bc_msg(&trans->req_hdr, num_frags)) 775 return -ENOMEM; 776 remainder = (trans->rsp_pay_size) % (bc_pay_sz); 777 num_frags = (trans->rsp_pay_size) / (bc_pay_sz); 778 if (remainder) 779 num_frags++; 780 if (qlcnic_sriov_alloc_bc_msg(&trans->rsp_hdr, num_frags)) 781 return -ENOMEM; 782 num_frags = t_num_frags; 783 hdr = trans->req_hdr; 784 } else { 785 cmd->req.arg = (u32 *)trans->req_pay; 786 cmd->rsp.arg = (u32 *)trans->rsp_pay; 787 cmd_op = cmd->req.arg[0] & 0xff; 788 cmd->cmd_op = cmd_op; 789 remainder = (trans->rsp_pay_size) % (bc_pay_sz); 790 num_frags = (trans->rsp_pay_size) / (bc_pay_sz); 791 if (remainder) 792 num_frags++; 793 cmd->req.num = trans->req_pay_size / 4; 794 cmd->rsp.num = trans->rsp_pay_size / 4; 795 hdr = trans->rsp_hdr; 796 cmd->op_type = trans->req_hdr->op_type; 797 } 798 799 trans->trans_id = seq; 800 trans->cmd_id = cmd_op; 801 for (i = 0; i < num_frags; i++) { 802 hdr[i].version = 2; 803 hdr[i].msg_type = msg_type; 804 hdr[i].op_type = cmd->op_type; 805 hdr[i].num_cmds = 1; 806 hdr[i].num_frags = num_frags; 807 hdr[i].frag_num = i + 1; 808 hdr[i].cmd_op = cmd_op; 809 hdr[i].seq_id = seq; 810 } 811 return 0; 812 } 813 814 static void qlcnic_sriov_cleanup_transaction(struct qlcnic_bc_trans *trans) 815 { 816 if (!trans) 817 return; 818 kfree(trans->req_hdr); 819 kfree(trans->rsp_hdr); 820 kfree(trans); 821 } 822 823 static int qlcnic_sriov_clear_trans(struct qlcnic_vf_info *vf, 824 struct qlcnic_bc_trans *trans, u8 type) 825 { 826 struct qlcnic_trans_list *t_list; 827 unsigned long flags; 828 int ret = 0; 829 830 if (type == QLC_BC_RESPONSE) { 831 t_list = &vf->rcv_act; 832 spin_lock_irqsave(&t_list->lock, flags); 833 t_list->count--; 834 list_del(&trans->list); 835 if (t_list->count > 0) 836 ret = 1; 837 spin_unlock_irqrestore(&t_list->lock, flags); 838 } 839 if (type == QLC_BC_COMMAND) { 840 while (test_and_set_bit(QLC_BC_VF_SEND, &vf->state)) 841 msleep(100); 842 vf->send_cmd = NULL; 843 clear_bit(QLC_BC_VF_SEND, &vf->state); 844 } 845 return ret; 846 } 847 848 static void qlcnic_sriov_schedule_bc_cmd(struct qlcnic_sriov *sriov, 849 struct qlcnic_vf_info *vf, 850 work_func_t func) 851 { 852 if (test_bit(QLC_BC_VF_FLR, &vf->state) || 853 vf->adapter->need_fw_reset) 854 return; 855 856 queue_work(sriov->bc.bc_trans_wq, &vf->trans_work); 857 } 858 859 static inline void qlcnic_sriov_wait_for_resp(struct qlcnic_bc_trans *trans) 860 { 861 struct completion *cmpl = &trans->resp_cmpl; 862 863 if (wait_for_completion_timeout(cmpl, QLC_MBOX_RESP_TIMEOUT)) 864 trans->trans_state = QLC_END; 865 else 866 trans->trans_state = QLC_ABORT; 867 868 return; 869 } 870 871 static void qlcnic_sriov_handle_multi_frags(struct qlcnic_bc_trans *trans, 872 u8 type) 873 { 874 if (type == QLC_BC_RESPONSE) { 875 trans->curr_rsp_frag++; 876 if (trans->curr_rsp_frag < trans->rsp_hdr->num_frags) 877 trans->trans_state = QLC_INIT; 878 else 879 trans->trans_state = QLC_END; 880 } else { 881 trans->curr_req_frag++; 882 if (trans->curr_req_frag < trans->req_hdr->num_frags) 883 trans->trans_state = QLC_INIT; 884 else 885 trans->trans_state = QLC_WAIT_FOR_RESP; 886 } 887 } 888 889 static void qlcnic_sriov_wait_for_channel_free(struct qlcnic_bc_trans *trans, 890 u8 type) 891 { 892 struct qlcnic_vf_info *vf = trans->vf; 893 struct completion *cmpl = &vf->ch_free_cmpl; 894 895 if (!wait_for_completion_timeout(cmpl, QLC_MBOX_CH_FREE_TIMEOUT)) { 896 trans->trans_state = QLC_ABORT; 897 return; 898 } 899 900 clear_bit(QLC_BC_VF_CHANNEL, &vf->state); 901 qlcnic_sriov_handle_multi_frags(trans, type); 902 } 903 904 static void qlcnic_sriov_pull_bc_msg(struct qlcnic_adapter *adapter, 905 u32 *hdr, u32 *pay, u32 size) 906 { 907 struct qlcnic_hardware_context *ahw = adapter->ahw; 908 u8 i, max = 2, hdr_size, j; 909 910 hdr_size = (sizeof(struct qlcnic_bc_hdr) / sizeof(u32)); 911 max = (size / sizeof(u32)) + hdr_size; 912 913 for (i = 2, j = 0; j < hdr_size; i++, j++) 914 *(hdr++) = readl(QLCNIC_MBX_FW(ahw, i)); 915 for (; j < max; i++, j++) 916 *(pay++) = readl(QLCNIC_MBX_FW(ahw, i)); 917 } 918 919 static int __qlcnic_sriov_issue_bc_post(struct qlcnic_vf_info *vf) 920 { 921 int ret = -EBUSY; 922 u32 timeout = 10000; 923 924 do { 925 if (!test_and_set_bit(QLC_BC_VF_CHANNEL, &vf->state)) { 926 ret = 0; 927 break; 928 } 929 mdelay(1); 930 } while (--timeout); 931 932 return ret; 933 } 934 935 static int qlcnic_sriov_issue_bc_post(struct qlcnic_bc_trans *trans, u8 type) 936 { 937 struct qlcnic_vf_info *vf = trans->vf; 938 u32 pay_size; 939 u32 *hdr, *pay; 940 int ret; 941 u8 pci_func = trans->func_id; 942 943 if (__qlcnic_sriov_issue_bc_post(vf)) 944 return -EBUSY; 945 946 if (type == QLC_BC_COMMAND) { 947 hdr = (u32 *)(trans->req_hdr + trans->curr_req_frag); 948 pay = (u32 *)(trans->req_pay + trans->curr_req_frag); 949 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size, 950 trans->curr_req_frag); 951 pay_size = (pay_size / sizeof(u32)); 952 } else { 953 hdr = (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag); 954 pay = (u32 *)(trans->rsp_pay + trans->curr_rsp_frag); 955 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size, 956 trans->curr_rsp_frag); 957 pay_size = (pay_size / sizeof(u32)); 958 } 959 960 ret = qlcnic_sriov_post_bc_msg(vf->adapter, hdr, pay, 961 pci_func, pay_size); 962 return ret; 963 } 964 965 static int __qlcnic_sriov_send_bc_msg(struct qlcnic_bc_trans *trans, 966 struct qlcnic_vf_info *vf, u8 type) 967 { 968 bool flag = true; 969 int err = -EIO; 970 971 while (flag) { 972 if (test_bit(QLC_BC_VF_FLR, &vf->state) || 973 vf->adapter->need_fw_reset) 974 trans->trans_state = QLC_ABORT; 975 976 switch (trans->trans_state) { 977 case QLC_INIT: 978 trans->trans_state = QLC_WAIT_FOR_CHANNEL_FREE; 979 if (qlcnic_sriov_issue_bc_post(trans, type)) 980 trans->trans_state = QLC_ABORT; 981 break; 982 case QLC_WAIT_FOR_CHANNEL_FREE: 983 qlcnic_sriov_wait_for_channel_free(trans, type); 984 break; 985 case QLC_WAIT_FOR_RESP: 986 qlcnic_sriov_wait_for_resp(trans); 987 break; 988 case QLC_END: 989 err = 0; 990 flag = false; 991 break; 992 case QLC_ABORT: 993 err = -EIO; 994 flag = false; 995 clear_bit(QLC_BC_VF_CHANNEL, &vf->state); 996 break; 997 default: 998 err = -EIO; 999 flag = false; 1000 } 1001 } 1002 return err; 1003 } 1004 1005 static int qlcnic_sriov_send_bc_cmd(struct qlcnic_adapter *adapter, 1006 struct qlcnic_bc_trans *trans, int pci_func) 1007 { 1008 struct qlcnic_vf_info *vf; 1009 int err, index = qlcnic_sriov_func_to_index(adapter, pci_func); 1010 1011 if (index < 0) 1012 return -EIO; 1013 1014 vf = &adapter->ahw->sriov->vf_info[index]; 1015 trans->vf = vf; 1016 trans->func_id = pci_func; 1017 1018 if (!test_bit(QLC_BC_VF_STATE, &vf->state)) { 1019 if (qlcnic_sriov_pf_check(adapter)) 1020 return -EIO; 1021 if (qlcnic_sriov_vf_check(adapter) && 1022 trans->cmd_id != QLCNIC_BC_CMD_CHANNEL_INIT) 1023 return -EIO; 1024 } 1025 1026 mutex_lock(&vf->send_cmd_lock); 1027 vf->send_cmd = trans; 1028 err = __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_COMMAND); 1029 qlcnic_sriov_clear_trans(vf, trans, QLC_BC_COMMAND); 1030 mutex_unlock(&vf->send_cmd_lock); 1031 return err; 1032 } 1033 1034 static void __qlcnic_sriov_process_bc_cmd(struct qlcnic_adapter *adapter, 1035 struct qlcnic_bc_trans *trans, 1036 struct qlcnic_cmd_args *cmd) 1037 { 1038 #ifdef CONFIG_QLCNIC_SRIOV 1039 if (qlcnic_sriov_pf_check(adapter)) { 1040 qlcnic_sriov_pf_process_bc_cmd(adapter, trans, cmd); 1041 return; 1042 } 1043 #endif 1044 cmd->rsp.arg[0] |= (0x9 << 25); 1045 return; 1046 } 1047 1048 static void qlcnic_sriov_process_bc_cmd(struct work_struct *work) 1049 { 1050 struct qlcnic_vf_info *vf = container_of(work, struct qlcnic_vf_info, 1051 trans_work); 1052 struct qlcnic_bc_trans *trans = NULL; 1053 struct qlcnic_adapter *adapter = vf->adapter; 1054 struct qlcnic_cmd_args cmd; 1055 u8 req; 1056 1057 if (adapter->need_fw_reset) 1058 return; 1059 1060 if (test_bit(QLC_BC_VF_FLR, &vf->state)) 1061 return; 1062 1063 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args)); 1064 trans = list_first_entry(&vf->rcv_act.wait_list, 1065 struct qlcnic_bc_trans, list); 1066 adapter = vf->adapter; 1067 1068 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, trans->req_hdr->seq_id, 1069 QLC_BC_RESPONSE)) 1070 goto cleanup_trans; 1071 1072 __qlcnic_sriov_process_bc_cmd(adapter, trans, &cmd); 1073 trans->trans_state = QLC_INIT; 1074 __qlcnic_sriov_send_bc_msg(trans, vf, QLC_BC_RESPONSE); 1075 1076 cleanup_trans: 1077 qlcnic_free_mbx_args(&cmd); 1078 req = qlcnic_sriov_clear_trans(vf, trans, QLC_BC_RESPONSE); 1079 qlcnic_sriov_cleanup_transaction(trans); 1080 if (req) 1081 qlcnic_sriov_schedule_bc_cmd(adapter->ahw->sriov, vf, 1082 qlcnic_sriov_process_bc_cmd); 1083 } 1084 1085 static void qlcnic_sriov_handle_bc_resp(struct qlcnic_bc_hdr *hdr, 1086 struct qlcnic_vf_info *vf) 1087 { 1088 struct qlcnic_bc_trans *trans; 1089 u32 pay_size; 1090 1091 if (test_and_set_bit(QLC_BC_VF_SEND, &vf->state)) 1092 return; 1093 1094 trans = vf->send_cmd; 1095 1096 if (trans == NULL) 1097 goto clear_send; 1098 1099 if (trans->trans_id != hdr->seq_id) 1100 goto clear_send; 1101 1102 pay_size = qlcnic_sriov_get_bc_paysize(trans->rsp_pay_size, 1103 trans->curr_rsp_frag); 1104 qlcnic_sriov_pull_bc_msg(vf->adapter, 1105 (u32 *)(trans->rsp_hdr + trans->curr_rsp_frag), 1106 (u32 *)(trans->rsp_pay + trans->curr_rsp_frag), 1107 pay_size); 1108 if (++trans->curr_rsp_frag < trans->rsp_hdr->num_frags) 1109 goto clear_send; 1110 1111 complete(&trans->resp_cmpl); 1112 1113 clear_send: 1114 clear_bit(QLC_BC_VF_SEND, &vf->state); 1115 } 1116 1117 int __qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov, 1118 struct qlcnic_vf_info *vf, 1119 struct qlcnic_bc_trans *trans) 1120 { 1121 struct qlcnic_trans_list *t_list = &vf->rcv_act; 1122 1123 t_list->count++; 1124 list_add_tail(&trans->list, &t_list->wait_list); 1125 if (t_list->count == 1) 1126 qlcnic_sriov_schedule_bc_cmd(sriov, vf, 1127 qlcnic_sriov_process_bc_cmd); 1128 return 0; 1129 } 1130 1131 static int qlcnic_sriov_add_act_list(struct qlcnic_sriov *sriov, 1132 struct qlcnic_vf_info *vf, 1133 struct qlcnic_bc_trans *trans) 1134 { 1135 struct qlcnic_trans_list *t_list = &vf->rcv_act; 1136 1137 spin_lock(&t_list->lock); 1138 1139 __qlcnic_sriov_add_act_list(sriov, vf, trans); 1140 1141 spin_unlock(&t_list->lock); 1142 return 0; 1143 } 1144 1145 static void qlcnic_sriov_handle_pending_trans(struct qlcnic_sriov *sriov, 1146 struct qlcnic_vf_info *vf, 1147 struct qlcnic_bc_hdr *hdr) 1148 { 1149 struct qlcnic_bc_trans *trans = NULL; 1150 struct list_head *node; 1151 u32 pay_size, curr_frag; 1152 u8 found = 0, active = 0; 1153 1154 spin_lock(&vf->rcv_pend.lock); 1155 if (vf->rcv_pend.count > 0) { 1156 list_for_each(node, &vf->rcv_pend.wait_list) { 1157 trans = list_entry(node, struct qlcnic_bc_trans, list); 1158 if (trans->trans_id == hdr->seq_id) { 1159 found = 1; 1160 break; 1161 } 1162 } 1163 } 1164 1165 if (found) { 1166 curr_frag = trans->curr_req_frag; 1167 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size, 1168 curr_frag); 1169 qlcnic_sriov_pull_bc_msg(vf->adapter, 1170 (u32 *)(trans->req_hdr + curr_frag), 1171 (u32 *)(trans->req_pay + curr_frag), 1172 pay_size); 1173 trans->curr_req_frag++; 1174 if (trans->curr_req_frag >= hdr->num_frags) { 1175 vf->rcv_pend.count--; 1176 list_del(&trans->list); 1177 active = 1; 1178 } 1179 } 1180 spin_unlock(&vf->rcv_pend.lock); 1181 1182 if (active) 1183 if (qlcnic_sriov_add_act_list(sriov, vf, trans)) 1184 qlcnic_sriov_cleanup_transaction(trans); 1185 1186 return; 1187 } 1188 1189 static void qlcnic_sriov_handle_bc_cmd(struct qlcnic_sriov *sriov, 1190 struct qlcnic_bc_hdr *hdr, 1191 struct qlcnic_vf_info *vf) 1192 { 1193 struct qlcnic_bc_trans *trans; 1194 struct qlcnic_adapter *adapter = vf->adapter; 1195 struct qlcnic_cmd_args cmd; 1196 u32 pay_size; 1197 int err; 1198 u8 cmd_op; 1199 1200 if (adapter->need_fw_reset) 1201 return; 1202 1203 if (!test_bit(QLC_BC_VF_STATE, &vf->state) && 1204 hdr->op_type != QLC_BC_CMD && 1205 hdr->cmd_op != QLCNIC_BC_CMD_CHANNEL_INIT) 1206 return; 1207 1208 if (hdr->frag_num > 1) { 1209 qlcnic_sriov_handle_pending_trans(sriov, vf, hdr); 1210 return; 1211 } 1212 1213 memset(&cmd, 0, sizeof(struct qlcnic_cmd_args)); 1214 cmd_op = hdr->cmd_op; 1215 if (qlcnic_sriov_alloc_bc_trans(&trans)) 1216 return; 1217 1218 if (hdr->op_type == QLC_BC_CMD) 1219 err = qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op); 1220 else 1221 err = qlcnic_alloc_mbx_args(&cmd, adapter, cmd_op); 1222 1223 if (err) { 1224 qlcnic_sriov_cleanup_transaction(trans); 1225 return; 1226 } 1227 1228 cmd.op_type = hdr->op_type; 1229 if (qlcnic_sriov_prepare_bc_hdr(trans, &cmd, hdr->seq_id, 1230 QLC_BC_COMMAND)) { 1231 qlcnic_free_mbx_args(&cmd); 1232 qlcnic_sriov_cleanup_transaction(trans); 1233 return; 1234 } 1235 1236 pay_size = qlcnic_sriov_get_bc_paysize(trans->req_pay_size, 1237 trans->curr_req_frag); 1238 qlcnic_sriov_pull_bc_msg(vf->adapter, 1239 (u32 *)(trans->req_hdr + trans->curr_req_frag), 1240 (u32 *)(trans->req_pay + trans->curr_req_frag), 1241 pay_size); 1242 trans->func_id = vf->pci_func; 1243 trans->vf = vf; 1244 trans->trans_id = hdr->seq_id; 1245 trans->curr_req_frag++; 1246 1247 if (qlcnic_sriov_soft_flr_check(adapter, trans, vf)) 1248 return; 1249 1250 if (trans->curr_req_frag == trans->req_hdr->num_frags) { 1251 if (qlcnic_sriov_add_act_list(sriov, vf, trans)) { 1252 qlcnic_free_mbx_args(&cmd); 1253 qlcnic_sriov_cleanup_transaction(trans); 1254 } 1255 } else { 1256 spin_lock(&vf->rcv_pend.lock); 1257 list_add_tail(&trans->list, &vf->rcv_pend.wait_list); 1258 vf->rcv_pend.count++; 1259 spin_unlock(&vf->rcv_pend.lock); 1260 } 1261 } 1262 1263 static void qlcnic_sriov_handle_msg_event(struct qlcnic_sriov *sriov, 1264 struct qlcnic_vf_info *vf) 1265 { 1266 struct qlcnic_bc_hdr hdr; 1267 u32 *ptr = (u32 *)&hdr; 1268 u8 msg_type, i; 1269 1270 for (i = 2; i < 6; i++) 1271 ptr[i - 2] = readl(QLCNIC_MBX_FW(vf->adapter->ahw, i)); 1272 msg_type = hdr.msg_type; 1273 1274 switch (msg_type) { 1275 case QLC_BC_COMMAND: 1276 qlcnic_sriov_handle_bc_cmd(sriov, &hdr, vf); 1277 break; 1278 case QLC_BC_RESPONSE: 1279 qlcnic_sriov_handle_bc_resp(&hdr, vf); 1280 break; 1281 } 1282 } 1283 1284 static void qlcnic_sriov_handle_flr_event(struct qlcnic_sriov *sriov, 1285 struct qlcnic_vf_info *vf) 1286 { 1287 struct qlcnic_adapter *adapter = vf->adapter; 1288 1289 if (qlcnic_sriov_pf_check(adapter)) 1290 qlcnic_sriov_pf_handle_flr(sriov, vf); 1291 else 1292 dev_err(&adapter->pdev->dev, 1293 "Invalid event to VF. VF should not get FLR event\n"); 1294 } 1295 1296 void qlcnic_sriov_handle_bc_event(struct qlcnic_adapter *adapter, u32 event) 1297 { 1298 struct qlcnic_vf_info *vf; 1299 struct qlcnic_sriov *sriov; 1300 int index; 1301 u8 pci_func; 1302 1303 sriov = adapter->ahw->sriov; 1304 pci_func = qlcnic_sriov_target_func_id(event); 1305 index = qlcnic_sriov_func_to_index(adapter, pci_func); 1306 1307 if (index < 0) 1308 return; 1309 1310 vf = &sriov->vf_info[index]; 1311 vf->pci_func = pci_func; 1312 1313 if (qlcnic_sriov_channel_free_check(event)) 1314 complete(&vf->ch_free_cmpl); 1315 1316 if (qlcnic_sriov_flr_check(event)) { 1317 qlcnic_sriov_handle_flr_event(sriov, vf); 1318 return; 1319 } 1320 1321 if (qlcnic_sriov_bc_msg_check(event)) 1322 qlcnic_sriov_handle_msg_event(sriov, vf); 1323 } 1324 1325 int qlcnic_sriov_cfg_bc_intr(struct qlcnic_adapter *adapter, u8 enable) 1326 { 1327 struct qlcnic_cmd_args cmd; 1328 int err; 1329 1330 if (!test_bit(__QLCNIC_SRIOV_ENABLE, &adapter->state)) 1331 return 0; 1332 1333 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_BC_EVENT_SETUP)) 1334 return -ENOMEM; 1335 1336 if (enable) 1337 cmd.req.arg[1] = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7); 1338 1339 err = qlcnic_83xx_issue_cmd(adapter, &cmd); 1340 1341 if (err != QLCNIC_RCODE_SUCCESS) { 1342 dev_err(&adapter->pdev->dev, 1343 "Failed to %s bc events, err=%d\n", 1344 (enable ? "enable" : "disable"), err); 1345 } 1346 1347 qlcnic_free_mbx_args(&cmd); 1348 return err; 1349 } 1350 1351 static int qlcnic_sriov_retry_bc_cmd(struct qlcnic_adapter *adapter, 1352 struct qlcnic_bc_trans *trans) 1353 { 1354 u8 max = QLC_BC_CMD_MAX_RETRY_CNT; 1355 u32 state; 1356 1357 state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1358 if (state == QLC_83XX_IDC_DEV_READY) { 1359 msleep(20); 1360 clear_bit(QLC_BC_VF_CHANNEL, &trans->vf->state); 1361 trans->trans_state = QLC_INIT; 1362 if (++adapter->fw_fail_cnt > max) 1363 return -EIO; 1364 else 1365 return 0; 1366 } 1367 1368 return -EIO; 1369 } 1370 1371 static int __qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter, 1372 struct qlcnic_cmd_args *cmd) 1373 { 1374 struct qlcnic_hardware_context *ahw = adapter->ahw; 1375 struct qlcnic_mailbox *mbx = ahw->mailbox; 1376 struct device *dev = &adapter->pdev->dev; 1377 struct qlcnic_bc_trans *trans; 1378 int err; 1379 u32 rsp_data, opcode, mbx_err_code, rsp; 1380 u16 seq = ++adapter->ahw->sriov->bc.trans_counter; 1381 u8 func = ahw->pci_func; 1382 1383 rsp = qlcnic_sriov_alloc_bc_trans(&trans); 1384 if (rsp) 1385 goto free_cmd; 1386 1387 rsp = qlcnic_sriov_prepare_bc_hdr(trans, cmd, seq, QLC_BC_COMMAND); 1388 if (rsp) 1389 goto cleanup_transaction; 1390 1391 retry: 1392 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status)) { 1393 rsp = -EIO; 1394 QLCDB(adapter, DRV, "MBX not Ready!(cmd 0x%x) for VF 0x%x\n", 1395 QLCNIC_MBX_RSP(cmd->req.arg[0]), func); 1396 goto err_out; 1397 } 1398 1399 err = qlcnic_sriov_send_bc_cmd(adapter, trans, func); 1400 if (err) { 1401 dev_err(dev, "MBX command 0x%x timed out for VF %d\n", 1402 (cmd->req.arg[0] & 0xffff), func); 1403 rsp = QLCNIC_RCODE_TIMEOUT; 1404 1405 /* After adapter reset PF driver may take some time to 1406 * respond to VF's request. Retry request till maximum retries. 1407 */ 1408 if ((trans->req_hdr->cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT) && 1409 !qlcnic_sriov_retry_bc_cmd(adapter, trans)) 1410 goto retry; 1411 1412 goto err_out; 1413 } 1414 1415 rsp_data = cmd->rsp.arg[0]; 1416 mbx_err_code = QLCNIC_MBX_STATUS(rsp_data); 1417 opcode = QLCNIC_MBX_RSP(cmd->req.arg[0]); 1418 1419 if ((mbx_err_code == QLCNIC_MBX_RSP_OK) || 1420 (mbx_err_code == QLCNIC_MBX_PORT_RSP_OK)) { 1421 rsp = QLCNIC_RCODE_SUCCESS; 1422 } else { 1423 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) { 1424 rsp = QLCNIC_RCODE_SUCCESS; 1425 } else { 1426 rsp = mbx_err_code; 1427 if (!rsp) 1428 rsp = 1; 1429 1430 dev_err(dev, 1431 "MBX command 0x%x failed with err:0x%x for VF %d\n", 1432 opcode, mbx_err_code, func); 1433 } 1434 } 1435 1436 err_out: 1437 if (rsp == QLCNIC_RCODE_TIMEOUT) { 1438 ahw->reset_context = 1; 1439 adapter->need_fw_reset = 1; 1440 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 1441 } 1442 1443 cleanup_transaction: 1444 qlcnic_sriov_cleanup_transaction(trans); 1445 1446 free_cmd: 1447 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) { 1448 qlcnic_free_mbx_args(cmd); 1449 kfree(cmd); 1450 } 1451 1452 return rsp; 1453 } 1454 1455 1456 static int qlcnic_sriov_issue_cmd(struct qlcnic_adapter *adapter, 1457 struct qlcnic_cmd_args *cmd) 1458 { 1459 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) 1460 return qlcnic_sriov_async_issue_cmd(adapter, cmd); 1461 else 1462 return __qlcnic_sriov_issue_cmd(adapter, cmd); 1463 } 1464 1465 static int qlcnic_sriov_channel_cfg_cmd(struct qlcnic_adapter *adapter, u8 cmd_op) 1466 { 1467 struct qlcnic_cmd_args cmd; 1468 struct qlcnic_vf_info *vf = &adapter->ahw->sriov->vf_info[0]; 1469 int ret; 1470 1471 memset(&cmd, 0, sizeof(cmd)); 1472 if (qlcnic_sriov_alloc_bc_mbx_args(&cmd, cmd_op)) 1473 return -ENOMEM; 1474 1475 ret = qlcnic_issue_cmd(adapter, &cmd); 1476 if (ret) { 1477 dev_err(&adapter->pdev->dev, 1478 "Failed bc channel %s %d\n", cmd_op ? "term" : "init", 1479 ret); 1480 goto out; 1481 } 1482 1483 cmd_op = (cmd.rsp.arg[0] & 0xff); 1484 if (cmd.rsp.arg[0] >> 25 == 2) 1485 return 2; 1486 if (cmd_op == QLCNIC_BC_CMD_CHANNEL_INIT) 1487 set_bit(QLC_BC_VF_STATE, &vf->state); 1488 else 1489 clear_bit(QLC_BC_VF_STATE, &vf->state); 1490 1491 out: 1492 qlcnic_free_mbx_args(&cmd); 1493 return ret; 1494 } 1495 1496 static void qlcnic_vf_add_mc_list(struct net_device *netdev, const u8 *mac, 1497 enum qlcnic_mac_type mac_type) 1498 { 1499 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1500 struct qlcnic_sriov *sriov = adapter->ahw->sriov; 1501 struct qlcnic_vf_info *vf; 1502 u16 vlan_id; 1503 int i; 1504 1505 vf = &adapter->ahw->sriov->vf_info[0]; 1506 1507 if (!qlcnic_sriov_check_any_vlan(vf)) { 1508 qlcnic_nic_add_mac(adapter, mac, 0, mac_type); 1509 } else { 1510 spin_lock(&vf->vlan_list_lock); 1511 for (i = 0; i < sriov->num_allowed_vlans; i++) { 1512 vlan_id = vf->sriov_vlans[i]; 1513 if (vlan_id) 1514 qlcnic_nic_add_mac(adapter, mac, vlan_id, 1515 mac_type); 1516 } 1517 spin_unlock(&vf->vlan_list_lock); 1518 if (qlcnic_84xx_check(adapter)) 1519 qlcnic_nic_add_mac(adapter, mac, 0, mac_type); 1520 } 1521 } 1522 1523 void qlcnic_sriov_cleanup_async_list(struct qlcnic_back_channel *bc) 1524 { 1525 struct list_head *head = &bc->async_cmd_list; 1526 struct qlcnic_async_cmd *entry; 1527 1528 flush_workqueue(bc->bc_async_wq); 1529 cancel_work_sync(&bc->vf_async_work); 1530 1531 spin_lock(&bc->queue_lock); 1532 while (!list_empty(head)) { 1533 entry = list_entry(head->next, struct qlcnic_async_cmd, 1534 list); 1535 list_del(&entry->list); 1536 kfree(entry->cmd); 1537 kfree(entry); 1538 } 1539 spin_unlock(&bc->queue_lock); 1540 } 1541 1542 void qlcnic_sriov_vf_set_multi(struct net_device *netdev) 1543 { 1544 struct qlcnic_adapter *adapter = netdev_priv(netdev); 1545 struct qlcnic_hardware_context *ahw = adapter->ahw; 1546 static const u8 bcast_addr[ETH_ALEN] = { 1547 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 1548 }; 1549 struct netdev_hw_addr *ha; 1550 u32 mode = VPORT_MISS_MODE_DROP; 1551 1552 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) 1553 return; 1554 1555 if (netdev->flags & IFF_PROMISC) { 1556 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED)) 1557 mode = VPORT_MISS_MODE_ACCEPT_ALL; 1558 } else if ((netdev->flags & IFF_ALLMULTI) || 1559 (netdev_mc_count(netdev) > ahw->max_mc_count)) { 1560 mode = VPORT_MISS_MODE_ACCEPT_MULTI; 1561 } else { 1562 qlcnic_vf_add_mc_list(netdev, bcast_addr, QLCNIC_BROADCAST_MAC); 1563 if (!netdev_mc_empty(netdev)) { 1564 qlcnic_flush_mcast_mac(adapter); 1565 netdev_for_each_mc_addr(ha, netdev) 1566 qlcnic_vf_add_mc_list(netdev, ha->addr, 1567 QLCNIC_MULTICAST_MAC); 1568 } 1569 } 1570 1571 /* configure unicast MAC address, if there is not sufficient space 1572 * to store all the unicast addresses then enable promiscuous mode 1573 */ 1574 if (netdev_uc_count(netdev) > ahw->max_uc_count) { 1575 mode = VPORT_MISS_MODE_ACCEPT_ALL; 1576 } else if (!netdev_uc_empty(netdev)) { 1577 netdev_for_each_uc_addr(ha, netdev) 1578 qlcnic_vf_add_mc_list(netdev, ha->addr, 1579 QLCNIC_UNICAST_MAC); 1580 } 1581 1582 if (adapter->pdev->is_virtfn) { 1583 if (mode == VPORT_MISS_MODE_ACCEPT_ALL && 1584 !adapter->fdb_mac_learn) { 1585 qlcnic_alloc_lb_filters_mem(adapter); 1586 adapter->drv_mac_learn = true; 1587 adapter->rx_mac_learn = true; 1588 } else { 1589 adapter->drv_mac_learn = false; 1590 adapter->rx_mac_learn = false; 1591 } 1592 } 1593 1594 qlcnic_nic_set_promisc(adapter, mode); 1595 } 1596 1597 static void qlcnic_sriov_handle_async_issue_cmd(struct work_struct *work) 1598 { 1599 struct qlcnic_async_cmd *entry, *tmp; 1600 struct qlcnic_back_channel *bc; 1601 struct qlcnic_cmd_args *cmd; 1602 struct list_head *head; 1603 LIST_HEAD(del_list); 1604 1605 bc = container_of(work, struct qlcnic_back_channel, vf_async_work); 1606 head = &bc->async_cmd_list; 1607 1608 spin_lock(&bc->queue_lock); 1609 list_splice_init(head, &del_list); 1610 spin_unlock(&bc->queue_lock); 1611 1612 list_for_each_entry_safe(entry, tmp, &del_list, list) { 1613 list_del(&entry->list); 1614 cmd = entry->cmd; 1615 __qlcnic_sriov_issue_cmd(bc->adapter, cmd); 1616 kfree(entry); 1617 } 1618 1619 if (!list_empty(head)) 1620 queue_work(bc->bc_async_wq, &bc->vf_async_work); 1621 1622 return; 1623 } 1624 1625 static struct qlcnic_async_cmd * 1626 qlcnic_sriov_alloc_async_cmd(struct qlcnic_back_channel *bc, 1627 struct qlcnic_cmd_args *cmd) 1628 { 1629 struct qlcnic_async_cmd *entry = NULL; 1630 1631 entry = kzalloc(sizeof(*entry), GFP_ATOMIC); 1632 if (!entry) 1633 return NULL; 1634 1635 entry->cmd = cmd; 1636 1637 spin_lock(&bc->queue_lock); 1638 list_add_tail(&entry->list, &bc->async_cmd_list); 1639 spin_unlock(&bc->queue_lock); 1640 1641 return entry; 1642 } 1643 1644 static void qlcnic_sriov_schedule_async_cmd(struct qlcnic_back_channel *bc, 1645 struct qlcnic_cmd_args *cmd) 1646 { 1647 struct qlcnic_async_cmd *entry = NULL; 1648 1649 entry = qlcnic_sriov_alloc_async_cmd(bc, cmd); 1650 if (!entry) { 1651 qlcnic_free_mbx_args(cmd); 1652 kfree(cmd); 1653 return; 1654 } 1655 1656 queue_work(bc->bc_async_wq, &bc->vf_async_work); 1657 } 1658 1659 static int qlcnic_sriov_async_issue_cmd(struct qlcnic_adapter *adapter, 1660 struct qlcnic_cmd_args *cmd) 1661 { 1662 1663 struct qlcnic_back_channel *bc = &adapter->ahw->sriov->bc; 1664 1665 if (adapter->need_fw_reset) 1666 return -EIO; 1667 1668 qlcnic_sriov_schedule_async_cmd(bc, cmd); 1669 1670 return 0; 1671 } 1672 1673 static int qlcnic_sriov_vf_reinit_driver(struct qlcnic_adapter *adapter) 1674 { 1675 int err; 1676 1677 adapter->need_fw_reset = 0; 1678 qlcnic_83xx_reinit_mbx_work(adapter->ahw->mailbox); 1679 qlcnic_83xx_enable_mbx_interrupt(adapter); 1680 1681 err = qlcnic_sriov_cfg_bc_intr(adapter, 1); 1682 if (err) 1683 return err; 1684 1685 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT); 1686 if (err) 1687 goto err_out_cleanup_bc_intr; 1688 1689 err = qlcnic_sriov_vf_init_driver(adapter); 1690 if (err) 1691 goto err_out_term_channel; 1692 1693 return 0; 1694 1695 err_out_term_channel: 1696 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM); 1697 1698 err_out_cleanup_bc_intr: 1699 qlcnic_sriov_cfg_bc_intr(adapter, 0); 1700 return err; 1701 } 1702 1703 static void qlcnic_sriov_vf_attach(struct qlcnic_adapter *adapter) 1704 { 1705 struct net_device *netdev = adapter->netdev; 1706 1707 if (netif_running(netdev)) { 1708 if (!qlcnic_up(adapter, netdev)) 1709 qlcnic_restore_indev_addr(netdev, NETDEV_UP); 1710 } 1711 1712 netif_device_attach(netdev); 1713 } 1714 1715 static void qlcnic_sriov_vf_detach(struct qlcnic_adapter *adapter) 1716 { 1717 struct qlcnic_hardware_context *ahw = adapter->ahw; 1718 struct qlcnic_intrpt_config *intr_tbl = ahw->intr_tbl; 1719 struct net_device *netdev = adapter->netdev; 1720 u8 i, max_ints = ahw->num_msix - 1; 1721 1722 netif_device_detach(netdev); 1723 qlcnic_83xx_detach_mailbox_work(adapter); 1724 qlcnic_83xx_disable_mbx_intr(adapter); 1725 1726 if (netif_running(netdev)) 1727 qlcnic_down(adapter, netdev); 1728 1729 for (i = 0; i < max_ints; i++) { 1730 intr_tbl[i].id = i; 1731 intr_tbl[i].enabled = 0; 1732 intr_tbl[i].src = 0; 1733 } 1734 ahw->reset_context = 0; 1735 } 1736 1737 static int qlcnic_sriov_vf_handle_dev_ready(struct qlcnic_adapter *adapter) 1738 { 1739 struct qlcnic_hardware_context *ahw = adapter->ahw; 1740 struct device *dev = &adapter->pdev->dev; 1741 struct qlc_83xx_idc *idc = &ahw->idc; 1742 u8 func = ahw->pci_func; 1743 u32 state; 1744 1745 if ((idc->prev_state == QLC_83XX_IDC_DEV_NEED_RESET) || 1746 (idc->prev_state == QLC_83XX_IDC_DEV_INIT)) { 1747 if (!qlcnic_sriov_vf_reinit_driver(adapter)) { 1748 qlcnic_sriov_vf_attach(adapter); 1749 adapter->fw_fail_cnt = 0; 1750 dev_info(dev, 1751 "%s: Reinitialization of VF 0x%x done after FW reset\n", 1752 __func__, func); 1753 } else { 1754 dev_err(dev, 1755 "%s: Reinitialization of VF 0x%x failed after FW reset\n", 1756 __func__, func); 1757 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE); 1758 dev_info(dev, "Current state 0x%x after FW reset\n", 1759 state); 1760 } 1761 } 1762 1763 return 0; 1764 } 1765 1766 static int qlcnic_sriov_vf_handle_context_reset(struct qlcnic_adapter *adapter) 1767 { 1768 struct qlcnic_hardware_context *ahw = adapter->ahw; 1769 struct qlcnic_mailbox *mbx = ahw->mailbox; 1770 struct device *dev = &adapter->pdev->dev; 1771 struct qlc_83xx_idc *idc = &ahw->idc; 1772 u8 func = ahw->pci_func; 1773 u32 state; 1774 1775 adapter->reset_ctx_cnt++; 1776 1777 /* Skip the context reset and check if FW is hung */ 1778 if (adapter->reset_ctx_cnt < 3) { 1779 adapter->need_fw_reset = 1; 1780 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 1781 dev_info(dev, 1782 "Resetting context, wait here to check if FW is in failed state\n"); 1783 return 0; 1784 } 1785 1786 /* Check if number of resets exceed the threshold. 1787 * If it exceeds the threshold just fail the VF. 1788 */ 1789 if (adapter->reset_ctx_cnt > QLC_83XX_VF_RESET_FAIL_THRESH) { 1790 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status); 1791 adapter->tx_timeo_cnt = 0; 1792 adapter->fw_fail_cnt = 0; 1793 adapter->reset_ctx_cnt = 0; 1794 qlcnic_sriov_vf_detach(adapter); 1795 dev_err(dev, 1796 "Device context resets have exceeded the threshold, device interface will be shutdown\n"); 1797 return -EIO; 1798 } 1799 1800 dev_info(dev, "Resetting context of VF 0x%x\n", func); 1801 dev_info(dev, "%s: Context reset count %d for VF 0x%x\n", 1802 __func__, adapter->reset_ctx_cnt, func); 1803 set_bit(__QLCNIC_RESETTING, &adapter->state); 1804 adapter->need_fw_reset = 1; 1805 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 1806 qlcnic_sriov_vf_detach(adapter); 1807 adapter->need_fw_reset = 0; 1808 1809 if (!qlcnic_sriov_vf_reinit_driver(adapter)) { 1810 qlcnic_sriov_vf_attach(adapter); 1811 adapter->tx_timeo_cnt = 0; 1812 adapter->reset_ctx_cnt = 0; 1813 adapter->fw_fail_cnt = 0; 1814 dev_info(dev, "Done resetting context for VF 0x%x\n", func); 1815 } else { 1816 dev_err(dev, "%s: Reinitialization of VF 0x%x failed\n", 1817 __func__, func); 1818 state = QLCRDX(ahw, QLC_83XX_IDC_DEV_STATE); 1819 dev_info(dev, "%s: Current state 0x%x\n", __func__, state); 1820 } 1821 1822 return 0; 1823 } 1824 1825 static int qlcnic_sriov_vf_idc_ready_state(struct qlcnic_adapter *adapter) 1826 { 1827 struct qlcnic_hardware_context *ahw = adapter->ahw; 1828 int ret = 0; 1829 1830 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) 1831 ret = qlcnic_sriov_vf_handle_dev_ready(adapter); 1832 else if (ahw->reset_context) 1833 ret = qlcnic_sriov_vf_handle_context_reset(adapter); 1834 1835 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1836 return ret; 1837 } 1838 1839 static int qlcnic_sriov_vf_idc_failed_state(struct qlcnic_adapter *adapter) 1840 { 1841 struct qlc_83xx_idc *idc = &adapter->ahw->idc; 1842 1843 dev_err(&adapter->pdev->dev, "Device is in failed state\n"); 1844 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) 1845 qlcnic_sriov_vf_detach(adapter); 1846 1847 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status); 1848 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1849 return -EIO; 1850 } 1851 1852 static int 1853 qlcnic_sriov_vf_idc_need_quiescent_state(struct qlcnic_adapter *adapter) 1854 { 1855 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 1856 struct qlc_83xx_idc *idc = &adapter->ahw->idc; 1857 1858 dev_info(&adapter->pdev->dev, "Device is in quiescent state\n"); 1859 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) { 1860 set_bit(__QLCNIC_RESETTING, &adapter->state); 1861 adapter->tx_timeo_cnt = 0; 1862 adapter->reset_ctx_cnt = 0; 1863 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 1864 qlcnic_sriov_vf_detach(adapter); 1865 } 1866 1867 return 0; 1868 } 1869 1870 static int qlcnic_sriov_vf_idc_init_reset_state(struct qlcnic_adapter *adapter) 1871 { 1872 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox; 1873 struct qlc_83xx_idc *idc = &adapter->ahw->idc; 1874 u8 func = adapter->ahw->pci_func; 1875 1876 if (idc->prev_state == QLC_83XX_IDC_DEV_READY) { 1877 dev_err(&adapter->pdev->dev, 1878 "Firmware hang detected by VF 0x%x\n", func); 1879 set_bit(__QLCNIC_RESETTING, &adapter->state); 1880 adapter->tx_timeo_cnt = 0; 1881 adapter->reset_ctx_cnt = 0; 1882 clear_bit(QLC_83XX_MBX_READY, &mbx->status); 1883 qlcnic_sriov_vf_detach(adapter); 1884 } 1885 return 0; 1886 } 1887 1888 static int qlcnic_sriov_vf_idc_unknown_state(struct qlcnic_adapter *adapter) 1889 { 1890 dev_err(&adapter->pdev->dev, "%s: Device in unknown state\n", __func__); 1891 return 0; 1892 } 1893 1894 static void qlcnic_sriov_vf_periodic_tasks(struct qlcnic_adapter *adapter) 1895 { 1896 if (adapter->fhash.fnum) 1897 qlcnic_prune_lb_filters(adapter); 1898 } 1899 1900 static void qlcnic_sriov_vf_poll_dev_state(struct work_struct *work) 1901 { 1902 struct qlcnic_adapter *adapter; 1903 struct qlc_83xx_idc *idc; 1904 int ret = 0; 1905 1906 adapter = container_of(work, struct qlcnic_adapter, fw_work.work); 1907 idc = &adapter->ahw->idc; 1908 idc->curr_state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE); 1909 1910 switch (idc->curr_state) { 1911 case QLC_83XX_IDC_DEV_READY: 1912 ret = qlcnic_sriov_vf_idc_ready_state(adapter); 1913 break; 1914 case QLC_83XX_IDC_DEV_NEED_RESET: 1915 case QLC_83XX_IDC_DEV_INIT: 1916 ret = qlcnic_sriov_vf_idc_init_reset_state(adapter); 1917 break; 1918 case QLC_83XX_IDC_DEV_NEED_QUISCENT: 1919 ret = qlcnic_sriov_vf_idc_need_quiescent_state(adapter); 1920 break; 1921 case QLC_83XX_IDC_DEV_FAILED: 1922 ret = qlcnic_sriov_vf_idc_failed_state(adapter); 1923 break; 1924 case QLC_83XX_IDC_DEV_QUISCENT: 1925 break; 1926 default: 1927 ret = qlcnic_sriov_vf_idc_unknown_state(adapter); 1928 } 1929 1930 idc->prev_state = idc->curr_state; 1931 qlcnic_sriov_vf_periodic_tasks(adapter); 1932 1933 if (!ret && test_bit(QLC_83XX_MODULE_LOADED, &idc->status)) 1934 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state, 1935 idc->delay); 1936 } 1937 1938 static void qlcnic_sriov_vf_cancel_fw_work(struct qlcnic_adapter *adapter) 1939 { 1940 while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 1941 msleep(20); 1942 1943 clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); 1944 clear_bit(__QLCNIC_RESETTING, &adapter->state); 1945 cancel_delayed_work_sync(&adapter->fw_work); 1946 } 1947 1948 static int qlcnic_sriov_check_vlan_id(struct qlcnic_sriov *sriov, 1949 struct qlcnic_vf_info *vf, u16 vlan_id) 1950 { 1951 int i, err = -EINVAL; 1952 1953 if (!vf->sriov_vlans) 1954 return err; 1955 1956 spin_lock_bh(&vf->vlan_list_lock); 1957 1958 for (i = 0; i < sriov->num_allowed_vlans; i++) { 1959 if (vf->sriov_vlans[i] == vlan_id) { 1960 err = 0; 1961 break; 1962 } 1963 } 1964 1965 spin_unlock_bh(&vf->vlan_list_lock); 1966 return err; 1967 } 1968 1969 static int qlcnic_sriov_validate_num_vlans(struct qlcnic_sriov *sriov, 1970 struct qlcnic_vf_info *vf) 1971 { 1972 int err = 0; 1973 1974 spin_lock_bh(&vf->vlan_list_lock); 1975 1976 if (vf->num_vlan >= sriov->num_allowed_vlans) 1977 err = -EINVAL; 1978 1979 spin_unlock_bh(&vf->vlan_list_lock); 1980 return err; 1981 } 1982 1983 static int qlcnic_sriov_validate_vlan_cfg(struct qlcnic_adapter *adapter, 1984 u16 vid, u8 enable) 1985 { 1986 struct qlcnic_sriov *sriov = adapter->ahw->sriov; 1987 struct qlcnic_vf_info *vf; 1988 bool vlan_exist; 1989 u8 allowed = 0; 1990 int i; 1991 1992 vf = &adapter->ahw->sriov->vf_info[0]; 1993 vlan_exist = qlcnic_sriov_check_any_vlan(vf); 1994 if (sriov->vlan_mode != QLC_GUEST_VLAN_MODE) 1995 return -EINVAL; 1996 1997 if (enable) { 1998 if (qlcnic_83xx_vf_check(adapter) && vlan_exist) 1999 return -EINVAL; 2000 2001 if (qlcnic_sriov_validate_num_vlans(sriov, vf)) 2002 return -EINVAL; 2003 2004 if (sriov->any_vlan) { 2005 for (i = 0; i < sriov->num_allowed_vlans; i++) { 2006 if (sriov->allowed_vlans[i] == vid) 2007 allowed = 1; 2008 } 2009 2010 if (!allowed) 2011 return -EINVAL; 2012 } 2013 } else { 2014 if (!vlan_exist || qlcnic_sriov_check_vlan_id(sriov, vf, vid)) 2015 return -EINVAL; 2016 } 2017 2018 return 0; 2019 } 2020 2021 static void qlcnic_sriov_vlan_operation(struct qlcnic_vf_info *vf, u16 vlan_id, 2022 enum qlcnic_vlan_operations opcode) 2023 { 2024 struct qlcnic_adapter *adapter = vf->adapter; 2025 struct qlcnic_sriov *sriov; 2026 2027 sriov = adapter->ahw->sriov; 2028 2029 if (!vf->sriov_vlans) 2030 return; 2031 2032 spin_lock_bh(&vf->vlan_list_lock); 2033 2034 switch (opcode) { 2035 case QLC_VLAN_ADD: 2036 qlcnic_sriov_add_vlan_id(sriov, vf, vlan_id); 2037 break; 2038 case QLC_VLAN_DELETE: 2039 qlcnic_sriov_del_vlan_id(sriov, vf, vlan_id); 2040 break; 2041 default: 2042 netdev_err(adapter->netdev, "Invalid VLAN operation\n"); 2043 } 2044 2045 spin_unlock_bh(&vf->vlan_list_lock); 2046 return; 2047 } 2048 2049 int qlcnic_sriov_cfg_vf_guest_vlan(struct qlcnic_adapter *adapter, 2050 u16 vid, u8 enable) 2051 { 2052 struct qlcnic_sriov *sriov = adapter->ahw->sriov; 2053 struct net_device *netdev = adapter->netdev; 2054 struct qlcnic_vf_info *vf; 2055 struct qlcnic_cmd_args cmd; 2056 int ret; 2057 2058 memset(&cmd, 0, sizeof(cmd)); 2059 if (vid == 0) 2060 return 0; 2061 2062 vf = &adapter->ahw->sriov->vf_info[0]; 2063 ret = qlcnic_sriov_validate_vlan_cfg(adapter, vid, enable); 2064 if (ret) 2065 return ret; 2066 2067 ret = qlcnic_sriov_alloc_bc_mbx_args(&cmd, 2068 QLCNIC_BC_CMD_CFG_GUEST_VLAN); 2069 if (ret) 2070 return ret; 2071 2072 cmd.req.arg[1] = (enable & 1) | vid << 16; 2073 2074 qlcnic_sriov_cleanup_async_list(&sriov->bc); 2075 ret = qlcnic_issue_cmd(adapter, &cmd); 2076 if (ret) { 2077 dev_err(&adapter->pdev->dev, 2078 "Failed to configure guest VLAN, err=%d\n", ret); 2079 } else { 2080 netif_addr_lock_bh(netdev); 2081 qlcnic_free_mac_list(adapter); 2082 netif_addr_unlock_bh(netdev); 2083 2084 if (enable) 2085 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_ADD); 2086 else 2087 qlcnic_sriov_vlan_operation(vf, vid, QLC_VLAN_DELETE); 2088 2089 netif_addr_lock_bh(netdev); 2090 qlcnic_set_multi(netdev); 2091 netif_addr_unlock_bh(netdev); 2092 } 2093 2094 qlcnic_free_mbx_args(&cmd); 2095 return ret; 2096 } 2097 2098 static void qlcnic_sriov_vf_free_mac_list(struct qlcnic_adapter *adapter) 2099 { 2100 struct list_head *head = &adapter->mac_list; 2101 struct qlcnic_mac_vlan_list *cur; 2102 2103 while (!list_empty(head)) { 2104 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list); 2105 qlcnic_sre_macaddr_change(adapter, cur->mac_addr, cur->vlan_id, 2106 QLCNIC_MAC_DEL); 2107 list_del(&cur->list); 2108 kfree(cur); 2109 } 2110 } 2111 2112 2113 static int qlcnic_sriov_vf_shutdown(struct pci_dev *pdev) 2114 { 2115 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev); 2116 struct net_device *netdev = adapter->netdev; 2117 2118 netif_device_detach(netdev); 2119 qlcnic_cancel_idc_work(adapter); 2120 2121 if (netif_running(netdev)) 2122 qlcnic_down(adapter, netdev); 2123 2124 qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_TERM); 2125 qlcnic_sriov_cfg_bc_intr(adapter, 0); 2126 qlcnic_83xx_disable_mbx_intr(adapter); 2127 cancel_delayed_work_sync(&adapter->idc_aen_work); 2128 2129 return pci_save_state(pdev); 2130 } 2131 2132 static int qlcnic_sriov_vf_resume(struct qlcnic_adapter *adapter) 2133 { 2134 struct qlc_83xx_idc *idc = &adapter->ahw->idc; 2135 struct net_device *netdev = adapter->netdev; 2136 int err; 2137 2138 set_bit(QLC_83XX_MODULE_LOADED, &idc->status); 2139 qlcnic_83xx_enable_mbx_interrupt(adapter); 2140 err = qlcnic_sriov_cfg_bc_intr(adapter, 1); 2141 if (err) 2142 return err; 2143 2144 err = qlcnic_sriov_channel_cfg_cmd(adapter, QLCNIC_BC_CMD_CHANNEL_INIT); 2145 if (!err) { 2146 if (netif_running(netdev)) { 2147 err = qlcnic_up(adapter, netdev); 2148 if (!err) 2149 qlcnic_restore_indev_addr(netdev, NETDEV_UP); 2150 } 2151 } 2152 2153 netif_device_attach(netdev); 2154 qlcnic_schedule_work(adapter, qlcnic_sriov_vf_poll_dev_state, 2155 idc->delay); 2156 return err; 2157 } 2158 2159 int qlcnic_sriov_alloc_vlans(struct qlcnic_adapter *adapter) 2160 { 2161 struct qlcnic_sriov *sriov = adapter->ahw->sriov; 2162 struct qlcnic_vf_info *vf; 2163 int i; 2164 2165 for (i = 0; i < sriov->num_vfs; i++) { 2166 vf = &sriov->vf_info[i]; 2167 vf->sriov_vlans = kcalloc(sriov->num_allowed_vlans, 2168 sizeof(*vf->sriov_vlans), GFP_KERNEL); 2169 if (!vf->sriov_vlans) 2170 return -ENOMEM; 2171 } 2172 2173 return 0; 2174 } 2175 2176 void qlcnic_sriov_free_vlans(struct qlcnic_adapter *adapter) 2177 { 2178 struct qlcnic_sriov *sriov = adapter->ahw->sriov; 2179 struct qlcnic_vf_info *vf; 2180 int i; 2181 2182 for (i = 0; i < sriov->num_vfs; i++) { 2183 vf = &sriov->vf_info[i]; 2184 kfree(vf->sriov_vlans); 2185 vf->sriov_vlans = NULL; 2186 } 2187 } 2188 2189 void qlcnic_sriov_add_vlan_id(struct qlcnic_sriov *sriov, 2190 struct qlcnic_vf_info *vf, u16 vlan_id) 2191 { 2192 int i; 2193 2194 for (i = 0; i < sriov->num_allowed_vlans; i++) { 2195 if (!vf->sriov_vlans[i]) { 2196 vf->sriov_vlans[i] = vlan_id; 2197 vf->num_vlan++; 2198 return; 2199 } 2200 } 2201 } 2202 2203 void qlcnic_sriov_del_vlan_id(struct qlcnic_sriov *sriov, 2204 struct qlcnic_vf_info *vf, u16 vlan_id) 2205 { 2206 int i; 2207 2208 for (i = 0; i < sriov->num_allowed_vlans; i++) { 2209 if (vf->sriov_vlans[i] == vlan_id) { 2210 vf->sriov_vlans[i] = 0; 2211 vf->num_vlan--; 2212 return; 2213 } 2214 } 2215 } 2216 2217 bool qlcnic_sriov_check_any_vlan(struct qlcnic_vf_info *vf) 2218 { 2219 bool err = false; 2220 2221 spin_lock_bh(&vf->vlan_list_lock); 2222 2223 if (vf->num_vlan) 2224 err = true; 2225 2226 spin_unlock_bh(&vf->vlan_list_lock); 2227 return err; 2228 } 2229