1 /* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8 #ifndef __QLCNIC_HDR_H_ 9 #define __QLCNIC_HDR_H_ 10 11 #include <linux/kernel.h> 12 #include <linux/types.h> 13 14 #include "qlcnic_hw.h" 15 16 /* 17 * The basic unit of access when reading/writing control registers. 18 */ 19 20 enum { 21 QLCNIC_HW_H0_CH_HUB_ADR = 0x05, 22 QLCNIC_HW_H1_CH_HUB_ADR = 0x0E, 23 QLCNIC_HW_H2_CH_HUB_ADR = 0x03, 24 QLCNIC_HW_H3_CH_HUB_ADR = 0x01, 25 QLCNIC_HW_H4_CH_HUB_ADR = 0x06, 26 QLCNIC_HW_H5_CH_HUB_ADR = 0x07, 27 QLCNIC_HW_H6_CH_HUB_ADR = 0x08 28 }; 29 30 /* Hub 0 */ 31 enum { 32 QLCNIC_HW_MN_CRB_AGT_ADR = 0x15, 33 QLCNIC_HW_MS_CRB_AGT_ADR = 0x25 34 }; 35 36 /* Hub 1 */ 37 enum { 38 QLCNIC_HW_PS_CRB_AGT_ADR = 0x73, 39 QLCNIC_HW_SS_CRB_AGT_ADR = 0x20, 40 QLCNIC_HW_RPMX3_CRB_AGT_ADR = 0x0b, 41 QLCNIC_HW_QMS_CRB_AGT_ADR = 0x00, 42 QLCNIC_HW_SQGS0_CRB_AGT_ADR = 0x01, 43 QLCNIC_HW_SQGS1_CRB_AGT_ADR = 0x02, 44 QLCNIC_HW_SQGS2_CRB_AGT_ADR = 0x03, 45 QLCNIC_HW_SQGS3_CRB_AGT_ADR = 0x04, 46 QLCNIC_HW_C2C0_CRB_AGT_ADR = 0x58, 47 QLCNIC_HW_C2C1_CRB_AGT_ADR = 0x59, 48 QLCNIC_HW_C2C2_CRB_AGT_ADR = 0x5a, 49 QLCNIC_HW_RPMX2_CRB_AGT_ADR = 0x0a, 50 QLCNIC_HW_RPMX4_CRB_AGT_ADR = 0x0c, 51 QLCNIC_HW_RPMX7_CRB_AGT_ADR = 0x0f, 52 QLCNIC_HW_RPMX9_CRB_AGT_ADR = 0x12, 53 QLCNIC_HW_SMB_CRB_AGT_ADR = 0x18 54 }; 55 56 /* Hub 2 */ 57 enum { 58 QLCNIC_HW_NIU_CRB_AGT_ADR = 0x31, 59 QLCNIC_HW_I2C0_CRB_AGT_ADR = 0x19, 60 QLCNIC_HW_I2C1_CRB_AGT_ADR = 0x29, 61 62 QLCNIC_HW_SN_CRB_AGT_ADR = 0x10, 63 QLCNIC_HW_I2Q_CRB_AGT_ADR = 0x20, 64 QLCNIC_HW_LPC_CRB_AGT_ADR = 0x22, 65 QLCNIC_HW_ROMUSB_CRB_AGT_ADR = 0x21, 66 QLCNIC_HW_QM_CRB_AGT_ADR = 0x66, 67 QLCNIC_HW_SQG0_CRB_AGT_ADR = 0x60, 68 QLCNIC_HW_SQG1_CRB_AGT_ADR = 0x61, 69 QLCNIC_HW_SQG2_CRB_AGT_ADR = 0x62, 70 QLCNIC_HW_SQG3_CRB_AGT_ADR = 0x63, 71 QLCNIC_HW_RPMX1_CRB_AGT_ADR = 0x09, 72 QLCNIC_HW_RPMX5_CRB_AGT_ADR = 0x0d, 73 QLCNIC_HW_RPMX6_CRB_AGT_ADR = 0x0e, 74 QLCNIC_HW_RPMX8_CRB_AGT_ADR = 0x11 75 }; 76 77 /* Hub 3 */ 78 enum { 79 QLCNIC_HW_PH_CRB_AGT_ADR = 0x1A, 80 QLCNIC_HW_SRE_CRB_AGT_ADR = 0x50, 81 QLCNIC_HW_EG_CRB_AGT_ADR = 0x51, 82 QLCNIC_HW_RPMX0_CRB_AGT_ADR = 0x08 83 }; 84 85 /* Hub 4 */ 86 enum { 87 QLCNIC_HW_PEGN0_CRB_AGT_ADR = 0x40, 88 QLCNIC_HW_PEGN1_CRB_AGT_ADR, 89 QLCNIC_HW_PEGN2_CRB_AGT_ADR, 90 QLCNIC_HW_PEGN3_CRB_AGT_ADR, 91 QLCNIC_HW_PEGNI_CRB_AGT_ADR, 92 QLCNIC_HW_PEGND_CRB_AGT_ADR, 93 QLCNIC_HW_PEGNC_CRB_AGT_ADR, 94 QLCNIC_HW_PEGR0_CRB_AGT_ADR, 95 QLCNIC_HW_PEGR1_CRB_AGT_ADR, 96 QLCNIC_HW_PEGR2_CRB_AGT_ADR, 97 QLCNIC_HW_PEGR3_CRB_AGT_ADR, 98 QLCNIC_HW_PEGN4_CRB_AGT_ADR 99 }; 100 101 /* Hub 5 */ 102 enum { 103 QLCNIC_HW_PEGS0_CRB_AGT_ADR = 0x40, 104 QLCNIC_HW_PEGS1_CRB_AGT_ADR, 105 QLCNIC_HW_PEGS2_CRB_AGT_ADR, 106 QLCNIC_HW_PEGS3_CRB_AGT_ADR, 107 QLCNIC_HW_PEGSI_CRB_AGT_ADR, 108 QLCNIC_HW_PEGSD_CRB_AGT_ADR, 109 QLCNIC_HW_PEGSC_CRB_AGT_ADR 110 }; 111 112 /* Hub 6 */ 113 enum { 114 QLCNIC_HW_CAS0_CRB_AGT_ADR = 0x46, 115 QLCNIC_HW_CAS1_CRB_AGT_ADR = 0x47, 116 QLCNIC_HW_CAS2_CRB_AGT_ADR = 0x48, 117 QLCNIC_HW_CAS3_CRB_AGT_ADR = 0x49, 118 QLCNIC_HW_NCM_CRB_AGT_ADR = 0x16, 119 QLCNIC_HW_TMR_CRB_AGT_ADR = 0x17, 120 QLCNIC_HW_XDMA_CRB_AGT_ADR = 0x05, 121 QLCNIC_HW_OCM0_CRB_AGT_ADR = 0x06, 122 QLCNIC_HW_OCM1_CRB_AGT_ADR = 0x07 123 }; 124 125 /* Floaters - non existent modules */ 126 #define QLCNIC_HW_EFC_RPMX0_CRB_AGT_ADR 0x67 127 128 /* This field defines PCI/X adr [25:20] of agents on the CRB */ 129 enum { 130 QLCNIC_HW_PX_MAP_CRB_PH = 0, 131 QLCNIC_HW_PX_MAP_CRB_PS, 132 QLCNIC_HW_PX_MAP_CRB_MN, 133 QLCNIC_HW_PX_MAP_CRB_MS, 134 QLCNIC_HW_PX_MAP_CRB_PGR1, 135 QLCNIC_HW_PX_MAP_CRB_SRE, 136 QLCNIC_HW_PX_MAP_CRB_NIU, 137 QLCNIC_HW_PX_MAP_CRB_QMN, 138 QLCNIC_HW_PX_MAP_CRB_SQN0, 139 QLCNIC_HW_PX_MAP_CRB_SQN1, 140 QLCNIC_HW_PX_MAP_CRB_SQN2, 141 QLCNIC_HW_PX_MAP_CRB_SQN3, 142 QLCNIC_HW_PX_MAP_CRB_QMS, 143 QLCNIC_HW_PX_MAP_CRB_SQS0, 144 QLCNIC_HW_PX_MAP_CRB_SQS1, 145 QLCNIC_HW_PX_MAP_CRB_SQS2, 146 QLCNIC_HW_PX_MAP_CRB_SQS3, 147 QLCNIC_HW_PX_MAP_CRB_PGN0, 148 QLCNIC_HW_PX_MAP_CRB_PGN1, 149 QLCNIC_HW_PX_MAP_CRB_PGN2, 150 QLCNIC_HW_PX_MAP_CRB_PGN3, 151 QLCNIC_HW_PX_MAP_CRB_PGND, 152 QLCNIC_HW_PX_MAP_CRB_PGNI, 153 QLCNIC_HW_PX_MAP_CRB_PGS0, 154 QLCNIC_HW_PX_MAP_CRB_PGS1, 155 QLCNIC_HW_PX_MAP_CRB_PGS2, 156 QLCNIC_HW_PX_MAP_CRB_PGS3, 157 QLCNIC_HW_PX_MAP_CRB_PGSD, 158 QLCNIC_HW_PX_MAP_CRB_PGSI, 159 QLCNIC_HW_PX_MAP_CRB_SN, 160 QLCNIC_HW_PX_MAP_CRB_PGR2, 161 QLCNIC_HW_PX_MAP_CRB_EG, 162 QLCNIC_HW_PX_MAP_CRB_PH2, 163 QLCNIC_HW_PX_MAP_CRB_PS2, 164 QLCNIC_HW_PX_MAP_CRB_CAM, 165 QLCNIC_HW_PX_MAP_CRB_CAS0, 166 QLCNIC_HW_PX_MAP_CRB_CAS1, 167 QLCNIC_HW_PX_MAP_CRB_CAS2, 168 QLCNIC_HW_PX_MAP_CRB_C2C0, 169 QLCNIC_HW_PX_MAP_CRB_C2C1, 170 QLCNIC_HW_PX_MAP_CRB_TIMR, 171 QLCNIC_HW_PX_MAP_CRB_PGR3, 172 QLCNIC_HW_PX_MAP_CRB_RPMX1, 173 QLCNIC_HW_PX_MAP_CRB_RPMX2, 174 QLCNIC_HW_PX_MAP_CRB_RPMX3, 175 QLCNIC_HW_PX_MAP_CRB_RPMX4, 176 QLCNIC_HW_PX_MAP_CRB_RPMX5, 177 QLCNIC_HW_PX_MAP_CRB_RPMX6, 178 QLCNIC_HW_PX_MAP_CRB_RPMX7, 179 QLCNIC_HW_PX_MAP_CRB_XDMA, 180 QLCNIC_HW_PX_MAP_CRB_I2Q, 181 QLCNIC_HW_PX_MAP_CRB_ROMUSB, 182 QLCNIC_HW_PX_MAP_CRB_CAS3, 183 QLCNIC_HW_PX_MAP_CRB_RPMX0, 184 QLCNIC_HW_PX_MAP_CRB_RPMX8, 185 QLCNIC_HW_PX_MAP_CRB_RPMX9, 186 QLCNIC_HW_PX_MAP_CRB_OCM0, 187 QLCNIC_HW_PX_MAP_CRB_OCM1, 188 QLCNIC_HW_PX_MAP_CRB_SMB, 189 QLCNIC_HW_PX_MAP_CRB_I2C0, 190 QLCNIC_HW_PX_MAP_CRB_I2C1, 191 QLCNIC_HW_PX_MAP_CRB_LPC, 192 QLCNIC_HW_PX_MAP_CRB_PGNC, 193 QLCNIC_HW_PX_MAP_CRB_PGR0 194 }; 195 196 #define BIT_0 0x1 197 #define BIT_1 0x2 198 #define BIT_2 0x4 199 #define BIT_3 0x8 200 #define BIT_4 0x10 201 #define BIT_5 0x20 202 #define BIT_6 0x40 203 #define BIT_7 0x80 204 #define BIT_8 0x100 205 #define BIT_9 0x200 206 #define BIT_10 0x400 207 #define BIT_11 0x800 208 #define BIT_12 0x1000 209 #define BIT_13 0x2000 210 #define BIT_14 0x4000 211 #define BIT_15 0x8000 212 #define BIT_16 0x10000 213 #define BIT_17 0x20000 214 #define BIT_18 0x40000 215 #define BIT_19 0x80000 216 #define BIT_20 0x100000 217 #define BIT_21 0x200000 218 #define BIT_22 0x400000 219 #define BIT_23 0x800000 220 #define BIT_24 0x1000000 221 #define BIT_25 0x2000000 222 #define BIT_26 0x4000000 223 #define BIT_27 0x8000000 224 #define BIT_28 0x10000000 225 #define BIT_29 0x20000000 226 #define BIT_30 0x40000000 227 #define BIT_31 0x80000000 228 229 /* This field defines CRB adr [31:20] of the agents */ 230 231 #define QLCNIC_HW_CRB_HUB_AGT_ADR_MN \ 232 ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MN_CRB_AGT_ADR) 233 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PH \ 234 ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_PH_CRB_AGT_ADR) 235 #define QLCNIC_HW_CRB_HUB_AGT_ADR_MS \ 236 ((QLCNIC_HW_H0_CH_HUB_ADR << 7) | QLCNIC_HW_MS_CRB_AGT_ADR) 237 238 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PS \ 239 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_PS_CRB_AGT_ADR) 240 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SS \ 241 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SS_CRB_AGT_ADR) 242 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3 \ 243 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX3_CRB_AGT_ADR) 244 #define QLCNIC_HW_CRB_HUB_AGT_ADR_QMS \ 245 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_QMS_CRB_AGT_ADR) 246 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS0 \ 247 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS0_CRB_AGT_ADR) 248 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS1 \ 249 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS1_CRB_AGT_ADR) 250 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS2 \ 251 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS2_CRB_AGT_ADR) 252 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQS3 \ 253 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SQGS3_CRB_AGT_ADR) 254 #define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C0 \ 255 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C0_CRB_AGT_ADR) 256 #define QLCNIC_HW_CRB_HUB_AGT_ADR_C2C1 \ 257 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_C2C1_CRB_AGT_ADR) 258 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2 \ 259 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX2_CRB_AGT_ADR) 260 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4 \ 261 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX4_CRB_AGT_ADR) 262 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7 \ 263 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX7_CRB_AGT_ADR) 264 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9 \ 265 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX9_CRB_AGT_ADR) 266 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SMB \ 267 ((QLCNIC_HW_H1_CH_HUB_ADR << 7) | QLCNIC_HW_SMB_CRB_AGT_ADR) 268 269 #define QLCNIC_HW_CRB_HUB_AGT_ADR_NIU \ 270 ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_NIU_CRB_AGT_ADR) 271 #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0 \ 272 ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C0_CRB_AGT_ADR) 273 #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1 \ 274 ((QLCNIC_HW_H2_CH_HUB_ADR << 7) | QLCNIC_HW_I2C1_CRB_AGT_ADR) 275 276 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SRE \ 277 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SRE_CRB_AGT_ADR) 278 #define QLCNIC_HW_CRB_HUB_AGT_ADR_EG \ 279 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_EG_CRB_AGT_ADR) 280 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0 \ 281 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX0_CRB_AGT_ADR) 282 #define QLCNIC_HW_CRB_HUB_AGT_ADR_QMN \ 283 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_QM_CRB_AGT_ADR) 284 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0 \ 285 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG0_CRB_AGT_ADR) 286 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1 \ 287 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG1_CRB_AGT_ADR) 288 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2 \ 289 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG2_CRB_AGT_ADR) 290 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3 \ 291 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_SQG3_CRB_AGT_ADR) 292 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1 \ 293 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX1_CRB_AGT_ADR) 294 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5 \ 295 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX5_CRB_AGT_ADR) 296 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6 \ 297 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX6_CRB_AGT_ADR) 298 #define QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8 \ 299 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_RPMX8_CRB_AGT_ADR) 300 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS0 \ 301 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS0_CRB_AGT_ADR) 302 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS1 \ 303 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS1_CRB_AGT_ADR) 304 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS2 \ 305 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS2_CRB_AGT_ADR) 306 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAS3 \ 307 ((QLCNIC_HW_H3_CH_HUB_ADR << 7) | QLCNIC_HW_CAS3_CRB_AGT_ADR) 308 309 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI \ 310 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNI_CRB_AGT_ADR) 311 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGND \ 312 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGND_CRB_AGT_ADR) 313 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0 \ 314 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN0_CRB_AGT_ADR) 315 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1 \ 316 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN1_CRB_AGT_ADR) 317 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2 \ 318 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN2_CRB_AGT_ADR) 319 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3 \ 320 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN3_CRB_AGT_ADR) 321 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4 \ 322 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGN4_CRB_AGT_ADR) 323 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC \ 324 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGNC_CRB_AGT_ADR) 325 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR0 \ 326 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR0_CRB_AGT_ADR) 327 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR1 \ 328 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR1_CRB_AGT_ADR) 329 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR2 \ 330 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR2_CRB_AGT_ADR) 331 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGR3 \ 332 ((QLCNIC_HW_H4_CH_HUB_ADR << 7) | QLCNIC_HW_PEGR3_CRB_AGT_ADR) 333 334 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI \ 335 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSI_CRB_AGT_ADR) 336 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSD \ 337 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSD_CRB_AGT_ADR) 338 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0 \ 339 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS0_CRB_AGT_ADR) 340 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1 \ 341 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS1_CRB_AGT_ADR) 342 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2 \ 343 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS2_CRB_AGT_ADR) 344 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3 \ 345 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGS3_CRB_AGT_ADR) 346 #define QLCNIC_HW_CRB_HUB_AGT_ADR_PGSC \ 347 ((QLCNIC_HW_H5_CH_HUB_ADR << 7) | QLCNIC_HW_PEGSC_CRB_AGT_ADR) 348 349 #define QLCNIC_HW_CRB_HUB_AGT_ADR_CAM \ 350 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_NCM_CRB_AGT_ADR) 351 #define QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR \ 352 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_TMR_CRB_AGT_ADR) 353 #define QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA \ 354 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_XDMA_CRB_AGT_ADR) 355 #define QLCNIC_HW_CRB_HUB_AGT_ADR_SN \ 356 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_SN_CRB_AGT_ADR) 357 #define QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q \ 358 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_I2Q_CRB_AGT_ADR) 359 #define QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB \ 360 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_ROMUSB_CRB_AGT_ADR) 361 #define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0 \ 362 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM0_CRB_AGT_ADR) 363 #define QLCNIC_HW_CRB_HUB_AGT_ADR_OCM1 \ 364 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_OCM1_CRB_AGT_ADR) 365 #define QLCNIC_HW_CRB_HUB_AGT_ADR_LPC \ 366 ((QLCNIC_HW_H6_CH_HUB_ADR << 7) | QLCNIC_HW_LPC_CRB_AGT_ADR) 367 368 #define QLCNIC_SRE_MISC (QLCNIC_CRB_SRE + 0x0002c) 369 370 #define QLCNIC_I2Q_CLR_PCI_HI (QLCNIC_CRB_I2Q + 0x00034) 371 372 #define ROMUSB_GLB (QLCNIC_CRB_ROMUSB + 0x00000) 373 #define ROMUSB_ROM (QLCNIC_CRB_ROMUSB + 0x10000) 374 375 #define QLCNIC_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) 376 #define QLCNIC_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) 377 #define QLCNIC_ROMUSB_GLB_PAD_GPIO_I (ROMUSB_GLB + 0x000c) 378 #define QLCNIC_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) 379 #define QLCNIC_ROMUSB_GLB_TEST_MUX_SEL (ROMUSB_GLB + 0x0044) 380 #define QLCNIC_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) 381 #define QLCNIC_ROMUSB_GLB_CHIP_CLK_CTRL (ROMUSB_GLB + 0x00A8) 382 383 #define QLCNIC_ROMUSB_GPIO(n) (ROMUSB_GLB + 0x60 + (4 * (n))) 384 385 #define QLCNIC_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) 386 #define QLCNIC_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) 387 #define QLCNIC_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) 388 #define QLCNIC_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) 389 #define QLCNIC_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) 390 #define QLCNIC_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) 391 392 /****************************************************************************** 393 * 394 * Definitions specific to M25P flash 395 * 396 ******************************************************************************* 397 */ 398 399 /* all are 1MB windows */ 400 401 #define QLCNIC_PCI_CRB_WINDOWSIZE 0x00100000 402 #define QLCNIC_PCI_CRB_WINDOW(A) \ 403 (QLCNIC_PCI_CRBSPACE + (A)*QLCNIC_PCI_CRB_WINDOWSIZE) 404 405 #define QLCNIC_CRB_NIU QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_NIU) 406 #define QLCNIC_CRB_SRE QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE) 407 #define QLCNIC_CRB_ROMUSB \ 408 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB) 409 #define QLCNIC_CRB_EPG QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_EG) 410 #define QLCNIC_CRB_I2Q QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q) 411 #define QLCNIC_CRB_TIMER QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_TIMR) 412 #define QLCNIC_CRB_I2C0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0) 413 #define QLCNIC_CRB_SMB QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB) 414 #define QLCNIC_CRB_MAX QLCNIC_PCI_CRB_WINDOW(64) 415 416 #define QLCNIC_CRB_PCIX_HOST QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH) 417 #define QLCNIC_CRB_PCIX_HOST2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PH2) 418 #define QLCNIC_CRB_PEG_NET_0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN0) 419 #define QLCNIC_CRB_PEG_NET_1 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN1) 420 #define QLCNIC_CRB_PEG_NET_2 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN2) 421 #define QLCNIC_CRB_PEG_NET_3 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGN3) 422 #define QLCNIC_CRB_PEG_NET_4 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SQS2) 423 #define QLCNIC_CRB_PEG_NET_D QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGND) 424 #define QLCNIC_CRB_PEG_NET_I QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PGNI) 425 #define QLCNIC_CRB_DDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_MN) 426 #define QLCNIC_CRB_QDR_NET QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SN) 427 428 #define QLCNIC_CRB_PCIX_MD QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_PS) 429 #define QLCNIC_CRB_PCIE QLCNIC_CRB_PCIX_MD 430 431 #define ISR_INT_VECTOR (QLCNIC_PCIX_PS_REG(PCIX_INT_VECTOR)) 432 #define ISR_INT_MASK (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK)) 433 #define ISR_INT_MASK_SLOW (QLCNIC_PCIX_PS_REG(PCIX_INT_MASK)) 434 #define ISR_INT_TARGET_STATUS (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS)) 435 #define ISR_INT_TARGET_MASK (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK)) 436 #define ISR_INT_TARGET_STATUS_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) 437 #define ISR_INT_TARGET_MASK_F1 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) 438 #define ISR_INT_TARGET_STATUS_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) 439 #define ISR_INT_TARGET_MASK_F2 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) 440 #define ISR_INT_TARGET_STATUS_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) 441 #define ISR_INT_TARGET_MASK_F3 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) 442 #define ISR_INT_TARGET_STATUS_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) 443 #define ISR_INT_TARGET_MASK_F4 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) 444 #define ISR_INT_TARGET_STATUS_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) 445 #define ISR_INT_TARGET_MASK_F5 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) 446 #define ISR_INT_TARGET_STATUS_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) 447 #define ISR_INT_TARGET_MASK_F6 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) 448 #define ISR_INT_TARGET_STATUS_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) 449 #define ISR_INT_TARGET_MASK_F7 (QLCNIC_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) 450 451 #define QLCNIC_PCI_OCM0_2M (0x000c0000UL) 452 #define QLCNIC_PCI_CRBSPACE (0x06000000UL) 453 #define QLCNIC_PCI_CAMQM (0x04800000UL) 454 #define QLCNIC_PCI_CAMQM_END (0x04800800UL) 455 #define QLCNIC_PCI_CAMQM_2M_BASE (0x000ff800UL) 456 457 #define QLCNIC_CRB_CAM QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_CAM) 458 459 #define QLCNIC_ADDR_DDR_NET (0x0000000000000000ULL) 460 #define QLCNIC_ADDR_DDR_NET_MAX (0x000000000fffffffULL) 461 #define QLCNIC_ADDR_OCM0 (0x0000000200000000ULL) 462 #define QLCNIC_ADDR_OCM0_MAX (0x00000002000fffffULL) 463 #define QLCNIC_ADDR_OCM1 (0x0000000200400000ULL) 464 #define QLCNIC_ADDR_OCM1_MAX (0x00000002004fffffULL) 465 #define QLCNIC_ADDR_QDR_NET (0x0000000300000000ULL) 466 #define QLCNIC_ADDR_QDR_NET_MAX (0x0000000307ffffffULL) 467 468 /* 469 * Register offsets for MN 470 */ 471 #define QLCNIC_MIU_CONTROL (0x000) 472 #define QLCNIC_MIU_MN_CONTROL (QLCNIC_CRB_DDR_NET+QLCNIC_MIU_CONTROL) 473 474 /* 200ms delay in each loop */ 475 #define QLCNIC_NIU_PHY_WAITLEN 200000 476 /* 10 seconds before we give up */ 477 #define QLCNIC_NIU_PHY_WAITMAX 50 478 #define QLCNIC_NIU_MAX_GBE_PORTS 4 479 #define QLCNIC_NIU_MAX_XG_PORTS 2 480 481 #define QLCNIC_NIU_MODE (QLCNIC_CRB_NIU + 0x00000) 482 #define QLCNIC_NIU_GB_PAUSE_CTL (QLCNIC_CRB_NIU + 0x0030c) 483 #define QLCNIC_NIU_XG_PAUSE_CTL (QLCNIC_CRB_NIU + 0x00098) 484 485 #define QLCNIC_NIU_GB_MAC_CONFIG_0(I) \ 486 (QLCNIC_CRB_NIU + 0x30000 + (I)*0x10000) 487 #define QLCNIC_NIU_GB_MAC_CONFIG_1(I) \ 488 (QLCNIC_CRB_NIU + 0x30004 + (I)*0x10000) 489 490 #define MAX_CTL_CHECK 1000 491 #define TEST_AGT_CTRL (0x00) 492 493 #define TA_CTL_START BIT_0 494 #define TA_CTL_ENABLE BIT_1 495 #define TA_CTL_WRITE BIT_2 496 #define TA_CTL_BUSY BIT_3 497 498 /* XG Link status */ 499 #define XG_LINK_UP 0x10 500 #define XG_LINK_DOWN 0x20 501 502 #define XG_LINK_UP_P3P 0x01 503 #define XG_LINK_DOWN_P3P 0x02 504 #define XG_LINK_STATE_P3P_MASK 0xf 505 #define XG_LINK_STATE_P3P(pcifn, val) \ 506 (((val) >> ((pcifn) * 4)) & XG_LINK_STATE_P3P_MASK) 507 508 #define P3P_LINK_SPEED_MHZ 100 509 #define P3P_LINK_SPEED_MASK 0xff 510 #define P3P_LINK_SPEED_REG(pcifn) \ 511 (CRB_PF_LINK_SPEED_1 + (((pcifn) / 4) * 4)) 512 #define P3P_LINK_SPEED_VAL(pcifn, reg) \ 513 (((reg) >> (8 * ((pcifn) & 0x3))) & P3P_LINK_SPEED_MASK) 514 515 #define QLCNIC_CAM_RAM_BASE (QLCNIC_CRB_CAM + 0x02000) 516 #define QLCNIC_CAM_RAM(reg) (QLCNIC_CAM_RAM_BASE + (reg)) 517 #define QLCNIC_ROM_LOCK_ID (QLCNIC_CAM_RAM(0x100)) 518 #define QLCNIC_PHY_LOCK_ID (QLCNIC_CAM_RAM(0x120)) 519 #define QLCNIC_CRB_WIN_LOCK_ID (QLCNIC_CAM_RAM(0x124)) 520 521 #define NIC_CRB_BASE (QLCNIC_CAM_RAM(0x200)) 522 #define NIC_CRB_BASE_2 (QLCNIC_CAM_RAM(0x700)) 523 #define QLCNIC_REG(X) (NIC_CRB_BASE+(X)) 524 #define QLCNIC_REG_2(X) (NIC_CRB_BASE_2+(X)) 525 526 #define QLCNIC_CDRP_MAX_ARGS 4 527 #define QLCNIC_CDRP_ARG(i) (QLCNIC_REG(0x18 + ((i) * 4))) 528 529 #define QLCNIC_CDRP_CRB_OFFSET (QLCNIC_REG(0x18)) 530 #define QLCNIC_SIGN_CRB_OFFSET (QLCNIC_REG(0x28)) 531 532 #define CRB_XG_STATE_P3P (QLCNIC_REG(0x98)) 533 #define CRB_PF_LINK_SPEED_1 (QLCNIC_REG(0xe8)) 534 #define CRB_DRIVER_VERSION (QLCNIC_REG(0x2a0)) 535 536 #define CRB_FW_CAPABILITIES_2 (QLCNIC_CAM_RAM(0x12c)) 537 538 /* 539 * CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address 540 * which can be read by the Phantom host to get producer/consumer indexes from 541 * Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following 542 * registers will be used for the addresses of the ring's shared memory 543 * on the Phantom. 544 */ 545 546 #define qlcnic_get_temp_val(x) ((x) >> 16) 547 #define qlcnic_get_temp_state(x) ((x) & 0xffff) 548 #define qlcnic_encode_temp(val, state) (((val) << 16) | (state)) 549 550 /* 551 * Temperature control. 552 */ 553 enum { 554 QLCNIC_TEMP_NORMAL = 0x1, /* Normal operating range */ 555 QLCNIC_TEMP_WARN, /* Sound alert, temperature getting high */ 556 QLCNIC_TEMP_PANIC /* Fatal error, hardware has shut down. */ 557 }; 558 559 560 /* Lock IDs for PHY lock */ 561 #define PHY_LOCK_DRIVER 0x44524956 562 563 #define PCIX_INT_VECTOR (0x10100) 564 #define PCIX_INT_MASK (0x10104) 565 566 #define PCIX_OCM_WINDOW (0x10800) 567 #define PCIX_OCM_WINDOW_REG(func) (PCIX_OCM_WINDOW + 0x4 * (func)) 568 569 #define PCIX_TARGET_STATUS (0x10118) 570 #define PCIX_TARGET_STATUS_F1 (0x10160) 571 #define PCIX_TARGET_STATUS_F2 (0x10164) 572 #define PCIX_TARGET_STATUS_F3 (0x10168) 573 #define PCIX_TARGET_STATUS_F4 (0x10360) 574 #define PCIX_TARGET_STATUS_F5 (0x10364) 575 #define PCIX_TARGET_STATUS_F6 (0x10368) 576 #define PCIX_TARGET_STATUS_F7 (0x1036c) 577 578 #define PCIX_TARGET_MASK (0x10128) 579 #define PCIX_TARGET_MASK_F1 (0x10170) 580 #define PCIX_TARGET_MASK_F2 (0x10174) 581 #define PCIX_TARGET_MASK_F3 (0x10178) 582 #define PCIX_TARGET_MASK_F4 (0x10370) 583 #define PCIX_TARGET_MASK_F5 (0x10374) 584 #define PCIX_TARGET_MASK_F6 (0x10378) 585 #define PCIX_TARGET_MASK_F7 (0x1037c) 586 587 #define PCIX_MSI_F(i) (0x13000+((i)*4)) 588 589 #define QLCNIC_PCIX_PH_REG(reg) (QLCNIC_CRB_PCIE + (reg)) 590 #define QLCNIC_PCIX_PS_REG(reg) (QLCNIC_CRB_PCIX_MD + (reg)) 591 #define QLCNIC_PCIE_REG(reg) (QLCNIC_CRB_PCIE + (reg)) 592 593 #define PCIE_SEM0_LOCK (0x1c000) 594 #define PCIE_SEM0_UNLOCK (0x1c004) 595 #define PCIE_SEM_LOCK(N) (PCIE_SEM0_LOCK + 8*(N)) 596 #define PCIE_SEM_UNLOCK(N) (PCIE_SEM0_UNLOCK + 8*(N)) 597 598 #define PCIE_SETUP_FUNCTION (0x12040) 599 #define PCIE_SETUP_FUNCTION2 (0x12048) 600 #define PCIE_MISCCFG_RC (0x1206c) 601 #define PCIE_TGT_SPLIT_CHICKEN (0x12080) 602 #define PCIE_CHICKEN3 (0x120c8) 603 604 #define ISR_INT_STATE_REG (QLCNIC_PCIX_PS_REG(PCIE_MISCCFG_RC)) 605 #define PCIE_MAX_MASTER_SPLIT (0x14048) 606 607 #define QLCNIC_PORT_MODE_NONE 0 608 #define QLCNIC_PORT_MODE_XG 1 609 #define QLCNIC_PORT_MODE_GB 2 610 #define QLCNIC_PORT_MODE_802_3_AP 3 611 #define QLCNIC_PORT_MODE_AUTO_NEG 4 612 #define QLCNIC_PORT_MODE_AUTO_NEG_1G 5 613 #define QLCNIC_PORT_MODE_AUTO_NEG_XG 6 614 #define QLCNIC_PORT_MODE_ADDR (QLCNIC_CAM_RAM(0x24)) 615 #define QLCNIC_WOL_PORT_MODE (QLCNIC_CAM_RAM(0x198)) 616 617 #define QLCNIC_WOL_CONFIG_NV (QLCNIC_CAM_RAM(0x184)) 618 #define QLCNIC_WOL_CONFIG (QLCNIC_CAM_RAM(0x188)) 619 620 #define QLCNIC_PEG_TUNE_MN_PRESENT 0x1 621 #define QLCNIC_PEG_TUNE_CAPABILITY (QLCNIC_CAM_RAM(0x02c)) 622 623 #define QLCNIC_DMA_WATCHDOG_CTRL (QLCNIC_CAM_RAM(0x14)) 624 #define QLCNIC_ROM_DEV_INIT_TIMEOUT (0x3e885c) 625 #define QLCNIC_ROM_DRV_RESET_TIMEOUT (0x3e8860) 626 627 /* Device State */ 628 #define QLCNIC_DEV_COLD 0x1 629 #define QLCNIC_DEV_INITIALIZING 0x2 630 #define QLCNIC_DEV_READY 0x3 631 #define QLCNIC_DEV_NEED_RESET 0x4 632 #define QLCNIC_DEV_NEED_QUISCENT 0x5 633 #define QLCNIC_DEV_FAILED 0x6 634 #define QLCNIC_DEV_QUISCENT 0x7 635 636 #define QLCNIC_DEV_BADBAD 0xbad0bad0 637 638 #define QLCNIC_DEV_NPAR_NON_OPER 0 /* NON Operational */ 639 #define QLCNIC_DEV_NPAR_OPER 1 /* NPAR Operational */ 640 #define QLCNIC_DEV_NPAR_OPER_TIMEO 30 /* Operational time out */ 641 642 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) 643 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) 644 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) 645 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) 646 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) 647 648 #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4))) 649 #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4)) 650 651 #define QLCNIC_TYPE_NIC 1 652 #define QLCNIC_TYPE_FCOE 2 653 #define QLCNIC_TYPE_ISCSI 3 654 655 #define QLCNIC_RCODE_DRIVER_INFO 0x20000000 656 #define QLCNIC_RCODE_DRIVER_CAN_RELOAD BIT_30 657 #define QLCNIC_RCODE_FATAL_ERROR BIT_31 658 #define QLCNIC_FWERROR_PEGNUM(code) ((code) & 0xff) 659 #define QLCNIC_FWERROR_CODE(code) ((code >> 8) & 0x1fffff) 660 #define QLCNIC_FWERROR_FAN_FAILURE 0x16 661 662 #define FW_POLL_DELAY (1 * HZ) 663 #define FW_FAIL_THRESH 2 664 665 #define QLCNIC_RESET_TIMEOUT_SECS 10 666 #define QLCNIC_INIT_TIMEOUT_SECS 30 667 #define QLCNIC_RCVPEG_CHECK_RETRY_COUNT 2000 668 #define QLCNIC_RCVPEG_CHECK_DELAY 10 669 #define QLCNIC_CMDPEG_CHECK_RETRY_COUNT 60 670 #define QLCNIC_CMDPEG_CHECK_DELAY 500 671 #define QLCNIC_HEARTBEAT_PERIOD_MSECS 200 672 #define QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT 10 673 674 #define QLCNIC_MAX_MC_COUNT 38 675 #define QLCNIC_MAX_UC_COUNT 512 676 #define QLCNIC_WATCHDOG_TIMEOUTVALUE 5 677 678 #define ISR_MSI_INT_TRIGGER(FUNC) (QLCNIC_PCIX_PS_REG(PCIX_MSI_F(FUNC))) 679 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) 680 681 /* 682 * PCI Interrupt Vector Values. 683 */ 684 #define PCIX_INT_VECTOR_BIT_F0 0x0080 685 #define PCIX_INT_VECTOR_BIT_F1 0x0100 686 #define PCIX_INT_VECTOR_BIT_F2 0x0200 687 #define PCIX_INT_VECTOR_BIT_F3 0x0400 688 #define PCIX_INT_VECTOR_BIT_F4 0x0800 689 #define PCIX_INT_VECTOR_BIT_F5 0x1000 690 #define PCIX_INT_VECTOR_BIT_F6 0x2000 691 #define PCIX_INT_VECTOR_BIT_F7 0x4000 692 693 struct qlcnic_legacy_intr_set { 694 u32 int_vec_bit; 695 u32 tgt_status_reg; 696 u32 tgt_mask_reg; 697 u32 pci_int_reg; 698 }; 699 700 #define QLCNIC_MSIX_BASE 0x132110 701 #define QLCNIC_MAX_VLAN_FILTERS 64 702 703 #define FLASH_ROM_WINDOW 0x42110030 704 #define FLASH_ROM_DATA 0x42150000 705 706 #define QLCNIC_FW_DUMP_REG1 0x00130060 707 #define QLCNIC_FW_DUMP_REG2 0x001e0000 708 #define QLCNIC_FLASH_SEM2_LK 0x0013C010 709 #define QLCNIC_FLASH_SEM2_ULK 0x0013C014 710 #define QLCNIC_FLASH_LOCK_ID 0x001B2100 711 712 /* PCI function operational mode */ 713 enum { 714 QLCNIC_MGMT_FUNC = 0, 715 QLCNIC_PRIV_FUNC = 1, 716 QLCNIC_NON_PRIV_FUNC = 2, 717 QLCNIC_SRIOV_PF_FUNC = 3, 718 QLCNIC_SRIOV_VF_FUNC = 4, 719 QLCNIC_UNKNOWN_FUNC_MODE = 5 720 }; 721 722 enum { 723 QLCNIC_PORT_DEFAULTS = 0, 724 QLCNIC_ADD_VLAN = 1, 725 QLCNIC_DEL_VLAN = 2 726 }; 727 728 #define QLC_DEV_DRV_DEFAULT 0x11111111 729 730 #define LSB(x) ((uint8_t)(x)) 731 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 732 733 #define LSW(x) ((uint16_t)((uint32_t)(x))) 734 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 735 736 #define LSD(x) ((uint32_t)((uint64_t)(x))) 737 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 738 739 #define QLCNIC_MS_CTRL 0x41000090 740 #define QLCNIC_MS_ADDR_LO 0x41000094 741 #define QLCNIC_MS_ADDR_HI 0x41000098 742 #define QLCNIC_MS_WRTDATA_LO 0x410000A0 743 #define QLCNIC_MS_WRTDATA_HI 0x410000A4 744 #define QLCNIC_MS_WRTDATA_ULO 0x410000B0 745 #define QLCNIC_MS_WRTDATA_UHI 0x410000B4 746 #define QLCNIC_MS_RDDATA_LO 0x410000A8 747 #define QLCNIC_MS_RDDATA_HI 0x410000AC 748 #define QLCNIC_MS_RDDATA_ULO 0x410000B8 749 #define QLCNIC_MS_RDDATA_UHI 0x410000BC 750 751 #define QLCNIC_TA_WRITE_ENABLE (TA_CTL_ENABLE | TA_CTL_WRITE) 752 #define QLCNIC_TA_WRITE_START (TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE) 753 #define QLCNIC_TA_START_ENABLE (TA_CTL_START | TA_CTL_ENABLE) 754 755 #define QLCNIC_LEGACY_INTR_CONFIG \ 756 { \ 757 { \ 758 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \ 759 .tgt_status_reg = ISR_INT_TARGET_STATUS, \ 760 .tgt_mask_reg = ISR_INT_TARGET_MASK, }, \ 761 \ 762 { \ 763 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \ 764 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \ 765 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, }, \ 766 \ 767 { \ 768 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \ 769 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \ 770 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, }, \ 771 \ 772 { \ 773 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \ 774 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \ 775 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, }, \ 776 \ 777 { \ 778 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \ 779 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \ 780 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, }, \ 781 \ 782 { \ 783 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \ 784 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \ 785 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, }, \ 786 \ 787 { \ 788 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \ 789 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \ 790 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, }, \ 791 \ 792 { \ 793 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \ 794 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \ 795 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, }, \ 796 } 797 798 /* NIU REGS */ 799 800 #define _qlcnic_crb_get_bit(var, bit) ((var >> bit) & 0x1) 801 802 /* 803 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3) 804 * 805 * Bit 0 : enable_tx => 1:enable frame xmit, 0:disable 806 * Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream 807 * Bit 2 : enable_rx => 1:enable frame recv, 0:disable 808 * Bit 3 : rx_synced => R/O: recv enable synched to recv stream 809 * Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable 810 * Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore 811 * Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal 812 * Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op 813 * Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op 814 * Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op 815 * Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op 816 * Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op 817 */ 818 #define qlcnic_gb_rx_flowctl(config_word) \ 819 ((config_word) |= 1 << 5) 820 #define qlcnic_gb_get_rx_flowctl(config_word) \ 821 _qlcnic_crb_get_bit((config_word), 5) 822 #define qlcnic_gb_unset_rx_flowctl(config_word) \ 823 ((config_word) &= ~(1 << 5)) 824 825 /* 826 * NIU GB Pause Ctl Register 827 */ 828 829 #define qlcnic_gb_set_gb0_mask(config_word) \ 830 ((config_word) |= 1 << 0) 831 #define qlcnic_gb_set_gb1_mask(config_word) \ 832 ((config_word) |= 1 << 2) 833 #define qlcnic_gb_set_gb2_mask(config_word) \ 834 ((config_word) |= 1 << 4) 835 #define qlcnic_gb_set_gb3_mask(config_word) \ 836 ((config_word) |= 1 << 6) 837 838 #define qlcnic_gb_get_gb0_mask(config_word) \ 839 _qlcnic_crb_get_bit((config_word), 0) 840 #define qlcnic_gb_get_gb1_mask(config_word) \ 841 _qlcnic_crb_get_bit((config_word), 2) 842 #define qlcnic_gb_get_gb2_mask(config_word) \ 843 _qlcnic_crb_get_bit((config_word), 4) 844 #define qlcnic_gb_get_gb3_mask(config_word) \ 845 _qlcnic_crb_get_bit((config_word), 6) 846 847 #define qlcnic_gb_unset_gb0_mask(config_word) \ 848 ((config_word) &= ~(1 << 0)) 849 #define qlcnic_gb_unset_gb1_mask(config_word) \ 850 ((config_word) &= ~(1 << 2)) 851 #define qlcnic_gb_unset_gb2_mask(config_word) \ 852 ((config_word) &= ~(1 << 4)) 853 #define qlcnic_gb_unset_gb3_mask(config_word) \ 854 ((config_word) &= ~(1 << 6)) 855 856 /* 857 * NIU XG Pause Ctl Register 858 * 859 * Bit 0 : xg0_mask => 1:disable tx pause frames 860 * Bit 1 : xg0_request => 1:request single pause frame 861 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off 862 * Bit 3 : xg1_mask => 1:disable tx pause frames 863 * Bit 4 : xg1_request => 1:request single pause frame 864 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off 865 */ 866 867 #define qlcnic_xg_set_xg0_mask(config_word) \ 868 ((config_word) |= 1 << 0) 869 #define qlcnic_xg_set_xg1_mask(config_word) \ 870 ((config_word) |= 1 << 3) 871 872 #define qlcnic_xg_get_xg0_mask(config_word) \ 873 _qlcnic_crb_get_bit((config_word), 0) 874 #define qlcnic_xg_get_xg1_mask(config_word) \ 875 _qlcnic_crb_get_bit((config_word), 3) 876 877 #define qlcnic_xg_unset_xg0_mask(config_word) \ 878 ((config_word) &= ~(1 << 0)) 879 #define qlcnic_xg_unset_xg1_mask(config_word) \ 880 ((config_word) &= ~(1 << 3)) 881 882 /* 883 * NIU XG Pause Ctl Register 884 * 885 * Bit 0 : xg0_mask => 1:disable tx pause frames 886 * Bit 1 : xg0_request => 1:request single pause frame 887 * Bit 2 : xg0_on_off => 1:request is pause on, 0:off 888 * Bit 3 : xg1_mask => 1:disable tx pause frames 889 * Bit 4 : xg1_request => 1:request single pause frame 890 * Bit 5 : xg1_on_off => 1:request is pause on, 0:off 891 */ 892 893 /* 894 * PHY-Specific MII control/status registers. 895 */ 896 #define QLCNIC_NIU_GB_MII_MGMT_ADDR_AUTONEG 4 897 #define QLCNIC_NIU_GB_MII_MGMT_ADDR_PHY_STATUS 17 898 899 /* 900 * PHY-Specific Status Register (reg 17). 901 * 902 * Bit 0 : jabber => 1:jabber detected, 0:not 903 * Bit 1 : polarity => 1:polarity reversed, 0:normal 904 * Bit 2 : recvpause => 1:receive pause enabled, 0:disabled 905 * Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled 906 * Bit 4 : energydetect => 1:sleep, 0:active 907 * Bit 5 : downshift => 1:downshift, 0:no downshift 908 * Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover) 909 * Bits 7-9 : cablelen => not valid in 10Mb/s mode 910 * 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m 911 * Bit 10 : link => 1:link up, 0:link down 912 * Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet 913 * Bit 12 : pagercvd => 1:page received, 0:page not received 914 * Bit 13 : duplex => 1:full duplex, 0:half duplex 915 * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd 916 */ 917 918 #define qlcnic_get_phy_speed(config_word) (((config_word) >> 14) & 0x03) 919 920 #define qlcnic_set_phy_speed(config_word, val) \ 921 ((config_word) |= ((val & 0x03) << 14)) 922 #define qlcnic_set_phy_duplex(config_word) \ 923 ((config_word) |= 1 << 13) 924 #define qlcnic_clear_phy_duplex(config_word) \ 925 ((config_word) &= ~(1 << 13)) 926 927 #define qlcnic_get_phy_link(config_word) \ 928 _qlcnic_crb_get_bit(config_word, 10) 929 #define qlcnic_get_phy_duplex(config_word) \ 930 _qlcnic_crb_get_bit(config_word, 13) 931 932 #define QLCNIC_NIU_NON_PROMISC_MODE 0 933 #define QLCNIC_NIU_PROMISC_MODE 1 934 #define QLCNIC_NIU_ALLMULTI_MODE 2 935 936 #define QLCNIC_PCIE_SEM_TIMEOUT 10000 937 938 struct crb_128M_2M_sub_block_map { 939 unsigned valid; 940 unsigned start_128M; 941 unsigned end_128M; 942 unsigned start_2M; 943 }; 944 945 struct crb_128M_2M_block_map{ 946 struct crb_128M_2M_sub_block_map sub_block[16]; 947 }; 948 #endif /* __QLCNIC_HDR_H_ */ 949